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xf.libfc6e712025-02-07 01:54:34 -08001/* FPU control word bits. Mips version.
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4 Contributed by Olaf Flebbe and Ralf Baechle.
5
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
10
11 The GNU C Library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
15
16 You should have received a copy of the GNU Lesser General Public
17 License along with the GNU C Library. If not, see
18 <http://www.gnu.org/licenses/>. */
19
20#ifndef _FPU_CONTROL_H
21#define _FPU_CONTROL_H
22
23/* MIPS FPU floating point control register bits.
24 *
25 * 31-25 -> floating point conditions code bits 7-1. These bits are only
26 * available in MIPS IV.
27 * 24 -> flush denormalized results to zero instead of
28 * causing unimplemented operation exception. This bit is only
29 * available for MIPS III and newer.
30 * 23 -> Condition bit
31 * 22-21 -> reserved for architecture implementers
32 * 20 -> reserved (read as 0, write with 0)
33 * 19 -> IEEE 754-2008 non-arithmetic ABS.fmt and NEG.fmt enable
34 * 18 -> IEEE 754-2008 recommended NaN encoding enable
35 * 17 -> cause bit for unimplemented operation
36 * 16 -> cause bit for invalid exception
37 * 15 -> cause bit for division by zero exception
38 * 14 -> cause bit for overflow exception
39 * 13 -> cause bit for underflow exception
40 * 12 -> cause bit for inexact exception
41 * 11 -> enable exception for invalid exception
42 * 10 -> enable exception for division by zero exception
43 * 9 -> enable exception for overflow exception
44 * 8 -> enable exception for underflow exception
45 * 7 -> enable exception for inexact exception
46 * 6 -> flag invalid exception
47 * 5 -> flag division by zero exception
48 * 4 -> flag overflow exception
49 * 3 -> flag underflow exception
50 * 2 -> flag inexact exception
51 * 1-0 -> rounding control
52 *
53 *
54 * Rounding Control:
55 * 00 - rounding to nearest (RN)
56 * 01 - rounding toward zero (RZ)
57 * 10 - rounding (up) toward plus infinity (RP)
58 * 11 - rounding (down)toward minus infinity (RM)
59 */
60
61#include <features.h>
62
63#ifdef __mips_soft_float
64
65#define _FPU_RESERVED 0xffffffff
66#define _FPU_DEFAULT 0x00000000
67typedef unsigned int fpu_control_t;
68#define _FPU_GETCW(cw) (cw) = 0
69#define _FPU_SETCW(cw) (void) (cw)
70extern fpu_control_t __fpu_control;
71
72#else /* __mips_soft_float */
73
74/* Masks for interrupts. */
75#define _FPU_MASK_V 0x0800 /* Invalid operation */
76#define _FPU_MASK_Z 0x0400 /* Division by zero */
77#define _FPU_MASK_O 0x0200 /* Overflow */
78#define _FPU_MASK_U 0x0100 /* Underflow */
79#define _FPU_MASK_I 0x0080 /* Inexact operation */
80
81/* Flush denormalized numbers to zero. */
82#define _FPU_FLUSH_TZ 0x1000000
83
84/* IEEE 754-2008 compliance control. */
85#define _FPU_ABS2008 0x80000
86#define _FPU_NAN2008 0x40000
87
88/* Rounding control. */
89#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
90#define _FPU_RC_ZERO 0x1
91#define _FPU_RC_UP 0x2
92#define _FPU_RC_DOWN 0x3
93/* Mask for rounding control. */
94#define _FPU_RC_MASK 0x3
95
96#define _FPU_RESERVED 0xfe8c0000 /* Reserved bits in cw, incl ABS/NAN2008. */
97
98
99/* The fdlibm code requires strict IEEE double precision arithmetic,
100 and no interrupts for exceptions, rounding to nearest. */
101#ifdef __mips_nan2008
102# define _FPU_DEFAULT 0x000C0000
103#else
104# define _FPU_DEFAULT 0x00000000
105#endif
106
107/* IEEE: same as above, but exceptions. */
108#ifdef __mips_nan2008
109# define _FPU_IEEE 0x000C0F80
110#else
111# define _FPU_IEEE 0x00000F80
112#endif
113
114/* Type of the control word. */
115typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
116
117/* Macros for accessing the hardware control word. */
118extern fpu_control_t __mips_fpu_getcw (void) __THROW;
119extern void __mips_fpu_setcw (fpu_control_t) __THROW;
120#ifdef __mips16
121# define _FPU_GETCW(cw) do { (cw) = __mips_fpu_getcw (); } while (0)
122# define _FPU_SETCW(cw) __mips_fpu_setcw (cw)
123#else
124# define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw))
125# define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw))
126#endif
127
128/* Default control word set at startup. */
129extern fpu_control_t __fpu_control;
130
131#endif /* __mips_soft_float */
132
133#endif /* fpu_control.h */