blob: c99465565122d77b19f1392dff8b3737267d3458 [file] [log] [blame]
xf.libfc6e712025-02-07 01:54:34 -08001/*
2 * Universal Host Controller Interface driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
13 */
14
15static const __u8 root_hub_hub_des[] =
16{
17 0x09, /* __u8 bLength; */
18 0x29, /* __u8 bDescriptorType; Hub-descriptor */
19 0x02, /* __u8 bNbrPorts; */
20 0x0a, /* __u16 wHubCharacteristics; */
21 0x00, /* (per-port OC, no power switching) */
22 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
23 0x00, /* __u8 bHubContrCurrent; 0 mA */
24 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */
25 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */
26};
27
28#define UHCI_RH_MAXCHILD 7
29
30/* must write as zeroes */
31#define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4)
32
33/* status change bits: nonzero writes will clear */
34#define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC)
35
36/* suspend/resume bits: port suspended or port resuming */
37#define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD)
38
39/* A port that either is connected or has a changed-bit set will prevent
40 * us from AUTO_STOPPING.
41 */
42static int any_ports_active(struct uhci_hcd *uhci)
43{
44 int port;
45
46 for (port = 0; port < uhci->rh_numports; ++port) {
47 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
48 (USBPORTSC_CCS | RWC_BITS)) ||
49 test_bit(port, &uhci->port_c_suspend))
50 return 1;
51 }
52 return 0;
53}
54
55static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
56{
57 int port;
58 int mask = RWC_BITS;
59
60 /* Some boards (both VIA and Intel apparently) report bogus
61 * overcurrent indications, causing massive log spam unless
62 * we completely ignore them. This doesn't seem to be a problem
63 * with the chipset so much as with the way it is connected on
64 * the motherboard; if the overcurrent input is left to float
65 * then it may constantly register false positives. */
66 if (ignore_oc)
67 mask &= ~USBPORTSC_OCC;
68
69 *buf = 0;
70 for (port = 0; port < uhci->rh_numports; ++port) {
71 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
72 test_bit(port, &uhci->port_c_suspend))
73 *buf |= (1 << (port + 1));
74 }
75 return !!*buf;
76}
77
78#define OK(x) len = (x); break
79
80#define CLR_RH_PORTSTAT(x) \
81 status = uhci_readw(uhci, port_addr); \
82 status &= ~(RWC_BITS|WZ_BITS); \
83 status &= ~(x); \
84 status |= RWC_BITS & (x); \
85 uhci_writew(uhci, status, port_addr)
86
87#define SET_RH_PORTSTAT(x) \
88 status = uhci_readw(uhci, port_addr); \
89 status |= (x); \
90 status &= ~(RWC_BITS|WZ_BITS); \
91 uhci_writew(uhci, status, port_addr)
92
93/* UHCI controllers don't automatically stop resume signalling after 20 msec,
94 * so we have to poll and check timeouts in order to take care of it.
95 */
96static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
97 unsigned long port_addr)
98{
99 int status;
100 int i;
101
102 if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
103 CLR_RH_PORTSTAT(SUSPEND_BITS);
104 if (test_bit(port, &uhci->resuming_ports))
105 set_bit(port, &uhci->port_c_suspend);
106
107 /* The controller won't actually turn off the RD bit until
108 * it has had a chance to send a low-speed EOP sequence,
109 * which is supposed to take 3 bit times (= 2 microseconds).
110 * Experiments show that some controllers take longer, so
111 * we'll poll for completion. */
112 for (i = 0; i < 10; ++i) {
113 if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
114 break;
115 udelay(1);
116 }
117 }
118 clear_bit(port, &uhci->resuming_ports);
119}
120
121/* Wait for the UHCI controller in HP's iLO2 server management chip.
122 * It can take up to 250 us to finish a reset and set the CSC bit.
123 */
124static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
125{
126 int i;
127
128 for (i = 10; i < 250; i += 10) {
129 if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
130 return;
131 udelay(10);
132 }
133 /* Log a warning? */
134}
135
136static void uhci_check_ports(struct uhci_hcd *uhci)
137{
138 unsigned int port;
139 unsigned long port_addr;
140 int status;
141
142 for (port = 0; port < uhci->rh_numports; ++port) {
143 port_addr = USBPORTSC1 + 2 * port;
144 status = uhci_readw(uhci, port_addr);
145 if (unlikely(status & USBPORTSC_PR)) {
146 if (time_after_eq(jiffies, uhci->ports_timeout)) {
147 CLR_RH_PORTSTAT(USBPORTSC_PR);
148 udelay(10);
149
150 /* HP's server management chip requires
151 * a longer delay. */
152 if (uhci->wait_for_hp)
153 wait_for_HP(uhci, port_addr);
154
155 /* If the port was enabled before, turning
156 * reset on caused a port enable change.
157 * Turning reset off causes a port connect
158 * status change. Clear these changes. */
159 CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC);
160 SET_RH_PORTSTAT(USBPORTSC_PE);
161 }
162 }
163 if (unlikely(status & USBPORTSC_RD)) {
164 if (!test_bit(port, &uhci->resuming_ports)) {
165
166 /* Port received a wakeup request */
167 set_bit(port, &uhci->resuming_ports);
168 uhci->ports_timeout = jiffies +
169 msecs_to_jiffies(25);
170
171 /* Make sure we see the port again
172 * after the resuming period is over. */
173 mod_timer(&uhci_to_hcd(uhci)->rh_timer,
174 uhci->ports_timeout);
175 } else if (time_after_eq(jiffies,
176 uhci->ports_timeout)) {
177 uhci_finish_suspend(uhci, port, port_addr);
178 }
179 }
180 }
181}
182
183static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf)
184{
185 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
186 unsigned long flags;
187 int status = 0;
188
189 spin_lock_irqsave(&uhci->lock, flags);
190
191 uhci_scan_schedule(uhci);
192 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
193 goto done;
194 uhci_check_ports(uhci);
195
196 status = get_hub_status_data(uhci, buf);
197
198 switch (uhci->rh_state) {
199 case UHCI_RH_SUSPENDED:
200 /* if port change, ask to be resumed */
201 if (status || uhci->resuming_ports) {
202 status = 1;
203 usb_hcd_resume_root_hub(hcd);
204 }
205 break;
206
207 case UHCI_RH_AUTO_STOPPED:
208 /* if port change, auto start */
209 if (status)
210 wakeup_rh(uhci);
211 break;
212
213 case UHCI_RH_RUNNING:
214 /* are any devices attached? */
215 if (!any_ports_active(uhci)) {
216 uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
217 uhci->auto_stop_time = jiffies + HZ;
218 }
219 break;
220
221 case UHCI_RH_RUNNING_NODEVS:
222 /* auto-stop if nothing connected for 1 second */
223 if (any_ports_active(uhci))
224 uhci->rh_state = UHCI_RH_RUNNING;
225 else if (time_after_eq(jiffies, uhci->auto_stop_time) &&
226 !uhci->wait_for_hp)
227 suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
228 break;
229
230 default:
231 break;
232 }
233
234done:
235 spin_unlock_irqrestore(&uhci->lock, flags);
236 return status;
237}
238
239/* size of returned buffer is part of USB spec */
240static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
241 u16 wIndex, char *buf, u16 wLength)
242{
243 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
244 int status, lstatus, retval = 0, len = 0;
245 unsigned int port = wIndex - 1;
246 unsigned long port_addr = USBPORTSC1 + 2 * port;
247 u16 wPortChange, wPortStatus;
248 unsigned long flags;
249
250 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
251 return -ETIMEDOUT;
252
253 spin_lock_irqsave(&uhci->lock, flags);
254 switch (typeReq) {
255
256 case GetHubStatus:
257 *(__le32 *)buf = cpu_to_le32(0);
258 OK(4); /* hub power */
259 case GetPortStatus:
260 if (port >= uhci->rh_numports)
261 goto err;
262
263 uhci_check_ports(uhci);
264 status = uhci_readw(uhci, port_addr);
265
266 /* Intel controllers report the OverCurrent bit active on.
267 * VIA controllers report it active off, so we'll adjust the
268 * bit value. (It's not standardized in the UHCI spec.)
269 */
270 if (uhci->oc_low)
271 status ^= USBPORTSC_OC;
272
273 /* UHCI doesn't support C_RESET (always false) */
274 wPortChange = lstatus = 0;
275 if (status & USBPORTSC_CSC)
276 wPortChange |= USB_PORT_STAT_C_CONNECTION;
277 if (status & USBPORTSC_PEC)
278 wPortChange |= USB_PORT_STAT_C_ENABLE;
279 if ((status & USBPORTSC_OCC) && !ignore_oc)
280 wPortChange |= USB_PORT_STAT_C_OVERCURRENT;
281
282 if (test_bit(port, &uhci->port_c_suspend)) {
283 wPortChange |= USB_PORT_STAT_C_SUSPEND;
284 lstatus |= 1;
285 }
286 if (test_bit(port, &uhci->resuming_ports))
287 lstatus |= 4;
288
289 /* UHCI has no power switching (always on) */
290 wPortStatus = USB_PORT_STAT_POWER;
291 if (status & USBPORTSC_CCS)
292 wPortStatus |= USB_PORT_STAT_CONNECTION;
293 if (status & USBPORTSC_PE) {
294 wPortStatus |= USB_PORT_STAT_ENABLE;
295 if (status & SUSPEND_BITS)
296 wPortStatus |= USB_PORT_STAT_SUSPEND;
297 }
298 if (status & USBPORTSC_OC)
299 wPortStatus |= USB_PORT_STAT_OVERCURRENT;
300 if (status & USBPORTSC_PR)
301 wPortStatus |= USB_PORT_STAT_RESET;
302 if (status & USBPORTSC_LSDA)
303 wPortStatus |= USB_PORT_STAT_LOW_SPEED;
304
305 if (wPortChange)
306 dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
307 wIndex, status, lstatus);
308
309 *(__le16 *)buf = cpu_to_le16(wPortStatus);
310 *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange);
311 OK(4);
312 case SetHubFeature: /* We don't implement these */
313 case ClearHubFeature:
314 switch (wValue) {
315 case C_HUB_OVER_CURRENT:
316 case C_HUB_LOCAL_POWER:
317 OK(0);
318 default:
319 goto err;
320 }
321 break;
322 case SetPortFeature:
323 if (port >= uhci->rh_numports)
324 goto err;
325
326 switch (wValue) {
327 case USB_PORT_FEAT_SUSPEND:
328 SET_RH_PORTSTAT(USBPORTSC_SUSP);
329 OK(0);
330 case USB_PORT_FEAT_RESET:
331 SET_RH_PORTSTAT(USBPORTSC_PR);
332
333 /* Reset terminates Resume signalling */
334 uhci_finish_suspend(uhci, port, port_addr);
335
336 /* USB v2.0 7.1.7.5 */
337 uhci->ports_timeout = jiffies + msecs_to_jiffies(50);
338 OK(0);
339 case USB_PORT_FEAT_POWER:
340 /* UHCI has no power switching */
341 OK(0);
342 default:
343 goto err;
344 }
345 break;
346 case ClearPortFeature:
347 if (port >= uhci->rh_numports)
348 goto err;
349
350 switch (wValue) {
351 case USB_PORT_FEAT_ENABLE:
352 CLR_RH_PORTSTAT(USBPORTSC_PE);
353
354 /* Disable terminates Resume signalling */
355 uhci_finish_suspend(uhci, port, port_addr);
356 OK(0);
357 case USB_PORT_FEAT_C_ENABLE:
358 CLR_RH_PORTSTAT(USBPORTSC_PEC);
359 OK(0);
360 case USB_PORT_FEAT_SUSPEND:
361 if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
362
363 /* Make certain the port isn't suspended */
364 uhci_finish_suspend(uhci, port, port_addr);
365 } else if (!test_and_set_bit(port,
366 &uhci->resuming_ports)) {
367 SET_RH_PORTSTAT(USBPORTSC_RD);
368
369 /* The controller won't allow RD to be set
370 * if the port is disabled. When this happens
371 * just skip the Resume signalling.
372 */
373 if (!(uhci_readw(uhci, port_addr) &
374 USBPORTSC_RD))
375 uhci_finish_suspend(uhci, port,
376 port_addr);
377 else
378 /* USB v2.0 7.1.7.7 */
379 uhci->ports_timeout = jiffies +
380 msecs_to_jiffies(20);
381 }
382 OK(0);
383 case USB_PORT_FEAT_C_SUSPEND:
384 clear_bit(port, &uhci->port_c_suspend);
385 OK(0);
386 case USB_PORT_FEAT_POWER:
387 /* UHCI has no power switching */
388 goto err;
389 case USB_PORT_FEAT_C_CONNECTION:
390 CLR_RH_PORTSTAT(USBPORTSC_CSC);
391 OK(0);
392 case USB_PORT_FEAT_C_OVER_CURRENT:
393 CLR_RH_PORTSTAT(USBPORTSC_OCC);
394 OK(0);
395 case USB_PORT_FEAT_C_RESET:
396 /* this driver won't report these */
397 OK(0);
398 default:
399 goto err;
400 }
401 break;
402 case GetHubDescriptor:
403 len = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
404 memcpy(buf, root_hub_hub_des, len);
405 if (len > 2)
406 buf[2] = uhci->rh_numports;
407 OK(len);
408 default:
409err:
410 retval = -EPIPE;
411 }
412 spin_unlock_irqrestore(&uhci->lock, flags);
413
414 return retval;
415}