commit 142f84ebd61c4ddc6aad3fe0d3f7b4ce4f2ed9ed
author xy.he <xy.he@mobiletek.cn> Mon Sep 02 10:22:10 2024 +0800
committer xy.he <xy.he@mobiletek.cn> Mon Sep 02 06:43:20 2024 +0000
tree 13419ef72881447001b8cf657983c304c50c481d
parent ac0d388563c1a03516d7413015ec065c8bdbb02f

[BugFix][L805A][bug-view-156/bug-view-162]If the switching main card is the current main card, 0 is returned instead of 2

    Only Configure: Yes
    Affected branch: DSDS
    Affected module: Sim
    Is it affected on both ZXIC and MTK: only MTK
    Self-test: Yes
    Doc Update: No

Change-Id: I70a221a1ddad2ecec0f61e10e87f3e66a363e637

common_src/framework/lynq-ril-service/src/common.cpp

diff --git a/common_src/framework/lynq-ril-service/src/common.cpp b/common_src/framework/lynq-ril-service/src/common.cpp
index 26cdce0..149c842 100755
--- a/common_src/framework/lynq-ril-service/src/common.cpp
+++ b/common_src/framework/lynq-ril-service/src/common.cpp
@@ -425,11 +425,16 @@
     }
     else
     {
+        //xy.he modified for bug-view-162/bug-view-156 @20240902 started
+        RLOGD("[%s][%d]Already in required sim%d",__FUNCTION__,__LINE__,slot);
+        //xy.he modified for bug-view-162/bug-view-156 @20240902 end
         android::Parcel allow_data_p;
         allow_data_p.writeInt32 (1);
         allow_data_p.writeInt32 (LYNQ_URC_ALLOW_DATA);
         allow_data_p.writeInt32 (slot);
-        allow_data_p.writeInt32 (RIL_E_GENERIC_FAILURE);
+        //xy.he modified for bug-view-162/bug-view-156 @20240902 started
+        allow_data_p.writeInt32 (0);
+        //xy.he modified for bug-view-162/bug-view-156 @20240902 end
         android::LYNQ_RIL_urcBroadcast(allow_data_p,LYNQ_URC_ALLOW_DATA);
     }
     pthread_mutex_unlock(&s_DataMutex);