zte's code,first commit
Change-Id: I9a04da59e459a9bc0d67f101f700d9d7dc8d681b
diff --git a/boot/common/src/loader/include/asm/arch-m0/cpu.h b/boot/common/src/loader/include/asm/arch-m0/cpu.h
new file mode 100644
index 0000000..f1bc765
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/cpu.h
@@ -0,0 +1,41 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZXIC Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author: zhouqi
+ * Date: 2013-4-2
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __CPU_H__
+#define __CPU_H__
+#include <config.h>
+
+
+#define SYS_BOOTSEL_BASE 0x0013b004
+
+#define SYS_IRAM0_BASE 0x82000000 /* 120k */
+#define SYS_IRAM1_BASE 0x100000 /* 64k *//* for A9 start */
+#define SYS_IRAM2_BASE 0x80000 /* 64k */
+
+#define CPU_A9_SUBSYS_CFG 0x013B138 /* for A9 reset */
+#define CPU_UFI_SW_RSTEN 0xf
+
+#define CORE_OUTPUT_SWITCH_CONFIG_REG (0x0013a000 + 0x0AC)
+#define CORE_OUTPUT_SW_CONFIG_REG1 (0x0013a000 + 0x0B8)
+#define CORE_OUTPUT_SW_CONFIG_REG2 (0x0013a000 + 0x0BC)
+
+#define USB_RESET (0x0013B080)
+
+extern void timer_init(void);
+
+
+#endif /*__CPU_H__*/
diff --git a/boot/common/src/loader/include/asm/arch-m0/denali.h b/boot/common/src/loader/include/asm/arch-m0/denali.h
new file mode 100644
index 0000000..35dbec8
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/denali.h
@@ -0,0 +1,484 @@
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef _DENALI_H_
+#define _DENALI_H_
+
+
+#define NAND_BASE 0x1214000 // ¼Ä´æÆ÷»ùµØÖ·
+#define NAND_DATA 0x1215000 // Êý¾Ý»ùµØÖ·
+#define NAND_DATA_10 (NAND_DATA + 0x10)
+
+#define DEVICE_RESET (NAND_BASE + 0x0)
+#define DEVICE_RESET__BANK0 0x0001
+#define DEVICE_RESET__BANK1 0x0002
+#define DEVICE_RESET__BANK2 0x0004
+#define DEVICE_RESET__BANK3 0x0008
+
+#define TRANSFER_SPARE_REG (NAND_BASE + 0x10)
+#define TRANSFER_SPARE_REG__FLAG 0x0001
+#define TRANSFER_MAIN_REG__FLAG 0x0000
+
+#define LOAD_WAIT_CNT (NAND_BASE + 0x20)
+#define LOAD_WAIT_CNT__VALUE 0xffff
+
+#define PROGRAM_WAIT_CNT (NAND_BASE + 0x30)
+#define PROGRAM_WAIT_CNT__VALUE 0xffff
+
+#define ERASE_WAIT_CNT (NAND_BASE + 0x40)
+#define ERASE_WAIT_CNT__VALUE 0xffff
+
+#define INT_MON_CYCCNT (NAND_BASE + 0x50)
+#define INT_MON_CYCCNT__VALUE 0xffff
+
+#define RB_PIN_ENABLED (NAND_BASE + 0x60)
+#define RB_PIN_ENABLED__BANK0 0x0001
+#define RB_PIN_ENABLED__BANK1 0x0002
+#define RB_PIN_ENABLED__BANK2 0x0004
+#define RB_PIN_ENABLED__BANK3 0x0008
+
+#define MULTIPLANE_OPERATION (NAND_BASE + 0x70)
+#define MULTIPLANE_OPERATION__FLAG 0x0001
+
+#define MULTIPLANE_READ_ENABLE (NAND_BASE + 0x80)
+#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
+
+#define COPYBACK_DISABLE (NAND_BASE + 0x90)
+#define COPYBACK_DISABLE__FLAG 0x0001
+
+#define CACHE_WRITE_ENABLE (NAND_BASE + 0xa0)
+#define CACHE_WRITE_ENABLE__FLAG 0x0001
+
+#define CACHE_READ_ENABLE (NAND_BASE + 0xb0)
+#define CACHE_READ_ENABLE__FLAG 0x0001
+
+#define PREFETCH_MODE (NAND_BASE + 0xc0)
+#define PREFETCH_MODE__PREFETCH_EN 0x0001
+#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
+
+#define CHIP_ENABLE_DONT_CARE (NAND_BASE + 0xd0)
+#define CHIP_EN_DONT_CARE__FLAG 0x01
+
+#define ECC_ENABLE (NAND_BASE + 0xe0)
+#define ECC_ENABLE__FLAG 0x0001
+#define ECC_DISABLE__FLAG 0x0000
+
+#define GLOBAL_INT_ENABLE (NAND_BASE + 0xf0)
+#define GLOBAL_INT_EN_FLAG 0x01
+
+#define WE_2_RE (NAND_BASE + 0x100)
+#define WE_2_RE__VALUE 0x003f
+
+#define ADDR_2_DATA (NAND_BASE + 0x110)
+#define ADDR_2_DATA__VALUE 0x003f
+
+#define RE_2_WE (NAND_BASE + 0x120)
+#define RE_2_WE__VALUE 0x003f
+
+#define ACC_CLKS (NAND_BASE + 0x130)
+#define ACC_CLKS__VALUE 0x000f
+
+#define NUMBER_OF_PLANES (NAND_BASE + 0x140)
+#define NUMBER_OF_PLANES__VALUE 0x0007
+
+#define PAGES_PER_BLOCK (NAND_BASE + 0x150)
+#define PAGES_PER_BLOCK__VALUE 0xffff
+
+#define DEVICE_WIDTH (NAND_BASE + 0x160)
+#define DEVICE_WIDTH__VALUE 0x0003
+
+#define DEVICE_MAIN_AREA_SIZE (NAND_BASE + 0x170)
+#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
+
+#define DEVICE_SPARE_AREA_SIZE (NAND_BASE + 0x180)
+#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
+
+#define TWO_ROW_ADDR_CYCLES (NAND_BASE + 0x190)
+#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
+
+#define MULTIPLANE_ADDR_RESTRICT (NAND_BASE + 0x1a0)
+#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
+
+#define ECC_CORRECTION (NAND_BASE + 0x1b0)
+#define ECC_CORRECTION__VALUE 0x001f
+
+#define READ_MODE (NAND_BASE + 0x1c0)
+#define READ_MODE__VALUE 0x000f
+
+#define WRITE_MODE (NAND_BASE + 0x1d0)
+#define WRITE_MODE__VALUE 0x000f
+
+#define COPYBACK_MODE (NAND_BASE + 0x1e0)
+#define COPYBACK_MODE__VALUE 0x000f
+
+#define RDWR_EN_LO_CNT (NAND_BASE + 0x1f0)
+#define RDWR_EN_LO_CNT__VALUE 0x001f
+
+#define RDWR_EN_HI_CNT (NAND_BASE + 0x200)
+#define RDWR_EN_HI_CNT__VALUE 0x001f
+
+#define MAX_RD_DELAY (NAND_BASE + 0x210)
+#define MAX_RD_DELAY__VALUE 0x000f
+
+#define CS_SETUP_CNT (NAND_BASE + 0x220)
+#define CS_SETUP_CNT__VALUE 0x001f
+
+#define SPARE_AREA_SKIP_BYTES (NAND_BASE + 0x230)
+#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
+
+#define SPARE_AREA_MARKER (NAND_BASE + 0x240)
+#define SPARE_AREA_MARKER__VALUE 0xffff
+
+#define DEVICES_CONNECTED (NAND_BASE + 0x250)
+#define DEVICES_CONNECTED__VALUE 0x0007
+
+#define DIE_MASK (NAND_BASE + 0x260)
+#define DIE_MASK__VALUE 0x00ff
+
+#define FIRST_BLOCK_OF_NEXT_PLANE (NAND_BASE + 0x270)
+#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
+
+#define WRITE_PROTECT (NAND_BASE + 0x280)
+#define WRITE_PROTECT__FLAG 0x0001
+
+#define RE_2_RE (NAND_BASE + 0x290)
+#define RE_2_RE__VALUE 0x003f
+
+#define MANUFACTURER_ID (NAND_BASE + 0x300)
+#define MANUFACTURER_ID__VALUE 0x00ff
+
+#define DEVICE_ID (NAND_BASE + 0x310)
+#define DEVICE_ID__VALUE 0x00ff
+
+#define DEVICE_PARAM_0 (NAND_BASE + 0x320)
+#define DEVICE_PARAM_0__VALUE 0x00ff
+
+#define DEVICE_PARAM_1 (NAND_BASE + 0x330)
+#define DEVICE_PARAM_1__VALUE 0x00ff
+
+#define DEVICE_PARAM_2 (NAND_BASE + 0x340)
+#define DEVICE_PARAM_2__VALUE 0x00ff
+
+#define LOGICAL_PAGE_DATA_SIZE (NAND_BASE + 0x350)
+#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
+
+#define LOGICAL_PAGE_SPARE_SIZE (NAND_BASE + 0x360)
+#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
+
+#define REVISION (NAND_BASE + 0x370)
+#define REVISION__VALUE 0xffff
+
+#define ONFI_DEVICE_FEATURES (NAND_BASE + 0x380)
+#define ONFI_DEVICE_FEATURES__VALUE 0x003f
+
+#define ONFI_OPTIONAL_COMMANDS (NAND_BASE + 0x390)
+#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
+
+#define ONFI_TIMING_MODE (NAND_BASE + 0x3a0)
+#define ONFI_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_PGM_CACHE_TIMING_MODE (NAND_BASE + 0x3b0)
+#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_DEVICE_NO_OF_LUNS (NAND_BASE + 0x3c0)
+#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
+#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L (NAND_BASE + 0x3d0)
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U (NAND_BASE + 0x3e0)
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
+
+#define FEATURES (NAND_BASE + 0x3f0)
+#define FEATURES__N_BANKS 0x0003
+#define FEATURES__ECC_MAX_ERR 0x003c
+#define FEATURES__DMA 0x0040
+#define FEATURES__CMD_DMA 0x0080
+#define FEATURES__PARTITION 0x0100
+#define FEATURES__XDMA_SIDEBAND 0x0200
+#define FEATURES__GPREG 0x0400
+#define FEATURES__INDEX_ADDR 0x0800
+
+#define TRANSFER_MODE (NAND_BASE + 0x400)
+#define TRANSFER_MODE__VALUE 0x0003
+
+#define INTR_STATUS(__bank) (NAND_BASE + 0x410 + ((__bank) * 0x50))
+#define INTR_EN(__bank) (NAND_BASE + 0x420 + ((__bank) * 0x50))
+
+
+#define INTR_STATUS__ECC_ERR 0x0001
+#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0002
+#define INTR_STATUS__DMA_CMD_COMP 0x0004
+#define INTR_STATUS__TIME_OUT 0x0008
+#define INTR_STATUS__PROGRAM_FAIL 0x0010
+#define INTR_STATUS__ERASE_FAIL 0x0020
+#define INTR_STATUS__LOAD_COMP 0x0040
+#define INTR_STATUS__PROGRAM_COMP 0x0080
+#define INTR_STATUS__ERASE_COMP 0x0100
+#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_STATUS__LOCKED_BLK 0x0400
+#define INTR_STATUS__UNSUP_CMD 0x0800
+#define INTR_STATUS__INT_ACT 0x1000
+#define INTR_STATUS__RST_COMP 0x2000
+#define INTR_STATUS__PIPE_CMD_ERR 0x4000
+#define INTR_STATUS__PAGE_XFER_INC 0x8000
+
+#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
+#define INTR_EN__ECC_ERR 0x0002
+#define INTR_EN__DMA_CMD_COMP 0x0004
+#define INTR_EN__TIME_OUT 0x0008
+#define INTR_EN__PROGRAM_FAIL 0x0010
+#define INTR_EN__ERASE_FAIL 0x0020
+#define INTR_EN__LOAD_COMP 0x0040
+#define INTR_EN__PROGRAM_COMP 0x0080
+#define INTR_EN__ERASE_COMP 0x0100
+#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_EN__LOCKED_BLK 0x0400
+#define INTR_EN__UNSUP_CMD 0x0800
+#define INTR_EN__INT_ACT 0x1000
+#define INTR_EN__RST_COMP 0x2000
+#define INTR_EN__PIPE_CMD_ERR 0x4000
+#define INTR_EN__PAGE_XFER_INC 0x8000
+
+#define PAGE_CNT(__bank) (NAND_BASE + 0x430 + ((__bank) * 0x50))
+#define ERR_PAGE_ADDR(__bank) (NAND_BASE + 0x440 + ((__bank) * 0x50))
+#define ERR_BLOCK_ADDR(__bank) (NAND_BASE + 0x450 + ((__bank) * 0x50))
+
+#define DATA_INTR (NAND_BASE + 0x550)
+#define DATA_INTR__WRITE_SPACE_AV 0x0001
+#define DATA_INTR__READ_DATA_AV 0x0002
+
+#define DATA_INTR_EN (NAND_BASE + 0x560)
+#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
+#define DATA_INTR_EN__READ_DATA_AV 0x0002
+
+#define GPREG_0 (NAND_BASE + 0x570)
+#define GPREG_0__VALUE 0xffff
+
+#define GPREG_1 (NAND_BASE + 0x580)
+#define GPREG_1__VALUE 0xffff
+
+#define GPREG_2 (NAND_BASE + 0x590)
+#define GPREG_2__VALUE 0xffff
+
+#define GPREG_3 (NAND_BASE + 0x5a0)
+#define GPREG_3__VALUE 0xffff
+
+#define ECC_THRESHOLD (NAND_BASE + 0x600)
+#define ECC_THRESHOLD__VALUE 0x03ff
+
+#define ECC_ERROR_BLOCK_ADDRESS (NAND_BASE + 0x610)
+#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
+
+#define ECC_ERROR_PAGE_ADDRESS (NAND_BASE + 0x620)
+#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
+#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
+
+#define ECC_ERROR_ADDRESS (NAND_BASE + 0x630)
+#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
+#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
+
+#define ERR_CORRECTION_INFO (NAND_BASE + 0x640)
+#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
+#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
+#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
+#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
+
+#define DMA_ENABLE (NAND_BASE + 0x700)
+#define DMA_ENABLE__FLAG 0x0001
+#define DMA_DISABLE__FLAG 0x0000
+
+#define IGNORE_ECC_DONE (NAND_BASE + 0x710)
+#define IGNORE_ECC_DONE__FLAG 0x0001
+
+#define DMA_INTR (NAND_BASE + 0x720)
+#define DMA_INTR__TARGET_ERROR 0x0001
+#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
+
+#define DMA_INTR_EN (NAND_BASE + 0x730)
+#define DMA_INTR_EN__TARGET_ERROR 0x0001
+#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
+
+#define TARGET_ERR_ADDR_LO (NAND_BASE + 0x740)
+#define TARGET_ERR_ADDR_LO__VALUE 0xffff
+
+#define TARGET_ERR_ADDR_HI (NAND_BASE + 0x750)
+#define TARGET_ERR_ADDR_HI__VALUE 0xffff
+
+#define CHNL_ACTIVE (NAND_BASE + 0x760)
+#define CHNL_ACTIVE__CHANNEL0 0x0001
+#define CHNL_ACTIVE__CHANNEL1 0x0002
+#define CHNL_ACTIVE__CHANNEL2 0x0004
+#define CHNL_ACTIVE__CHANNEL3 0x0008
+
+#define ACTIVE_SRC_ID (NAND_BASE + 0x800)
+#define ACTIVE_SRC_ID__VALUE 0x00ff
+
+#define PTN_INTR (NAND_BASE + 0x810)
+#define PTN_INTR__CONFIG_ERROR 0x0001
+#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR__REG_ACCESS_ERROR 0x0020
+
+#define PTN_INTR_EN (NAND_BASE + 0x820)
+#define PTN_INTR_EN__CONFIG_ERROR 0x0001
+#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
+
+#define PERM_SRC_ID(__bank) (NAND_BASE + 0x830 + ((__bank) * 0x40))
+#define PERM_SRC_ID__SRCID 0x00ff
+#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
+#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
+#define PERM_SRC_ID__READ_ACTIVE 0x4000
+#define PERM_SRC_ID__PARTITION_VALID 0x8000
+
+#define MIN_BLK_ADDR(__bank) (NAND_BASE + 0x840 + ((__bank) * 0x40))
+#define MIN_BLK_ADDR__VALUE 0xffff
+
+#define MAX_BLK_ADDR(__bank) (NAND_BASE + 0x850 + ((__bank) * 0x40))
+#define MAX_BLK_ADDR__VALUE 0xffff
+
+#define MIN_MAX_BANK(__bank) (NAND_BASE + 0x860 + ((__bank) * 0x40))
+#define MIN_MAX_BANK__MIN_VALUE 0x0003
+#define MIN_MAX_BANK__MAX_VALUE 0x000c
+
+
+/* ffsdefs.h */
+#define CLEAR 0 /*use this to clear a field instead of "fail"*/
+#define SET 1 /*use this to set a field instead of "pass"*/
+#define FAIL 1 /*failed flag*/
+#define PASS 0 /*success flag*/
+#define ERR -1 /*error flag*/
+
+/* lld.h */
+#define GOOD_BLOCK 0
+#define DEFECTIVE_BLOCK 1
+#define READ_ERROR 2
+
+#define CLK_X 5
+#define CLK_MULTI 4
+
+/* spectraswconfig.h */
+#define CMD_DMA 0
+
+#define SPECTRA_PARTITION_ID 0
+/**** Block Table and Reserved Block Parameters *****/
+#define SPECTRA_START_BLOCK 3
+#define NUM_FREE_BLOCKS_GATE 30
+
+/* KBV - Updated to LNW scratch register address */
+#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
+#define SCRATCH_REG_SIZE 64
+
+#define GLOB_HWCTL_DEFAULT_BLKS 2048
+
+#define SUPPORT_15BITECC 1
+#define SUPPORT_8BITECC 1
+
+#define CUSTOM_CONF_PARAMS 0
+
+#define ONFI_BLOOM_TIME 1
+#define MODE5_WORKAROUND 0
+
+/* lld_nand.h */
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright (c) 2009, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#define MODE_00 0x00000000
+#define MODE_01 0x04000000
+#define MODE_10 0x08000000
+#define MODE_11 0x0C000000
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS 0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DATA_TRANSFER_MODE 0
+#define PROTECTION_PER_BLOCK 1
+#define LOAD_WAIT_COUNT 2
+#define PROGRAM_WAIT_COUNT 3
+#define ERASE_WAIT_COUNT 4
+#define INT_MONITOR_CYCLE_COUNT 5
+#define READ_BUSY_PIN_ENABLED 6
+#define MULTIPLANE_OPERATION_SUPPORT 7
+#define PRE_FETCH_MODE 8
+#define CE_DONT_CARE_SUPPORT 9
+#define COPYBACK_SUPPORT 10
+#define CACHE_WRITE_SUPPORT 11
+#define CACHE_READ_SUPPORT 12
+#define NUM_PAGES_IN_BLOCK 13
+#define ECC_ENABLE_SELECT 14
+#define WRITE_ENABLE_2_READ_ENABLE 15
+#define ADDRESS_2_DATA 16
+#define READ_ENABLE_2_WRITE_ENABLE 17
+#define TWO_ROW_ADDRESS_CYCLES 18
+#define MULTIPLANE_ADDRESS_RESTRICT 19
+#define ACC_CLOCKS 20
+#define READ_WRITE_ENABLE_LOW_COUNT 21
+#define READ_WRITE_ENABLE_HIGH_COUNT 22
+
+/*nand É豸ÃèÊö½á¹¹Ìå*/
+struct nand_flash_device_para
+{
+ uint8_t manuf_id; /* ³§¼ÒID */
+ uint8_t device_id; /* É豸ID */
+ uint8_t res_id; /* Æ÷¼þID */
+ uint8_t bus_num; /* 0:8λ 1:16λ */
+ uint16_t ecc_strength; /*ECC ¾À´íÄÜÁ¦*/
+ uint16_t page_size; /* ÿҳmainÇøÓò´óС */
+ uint16_t page_size_shift;
+ uint16_t oob_size; /* ÿҳspareÇøÓò´óС */
+ uint16_t block_size_shift;
+ uint16_t block_num; /* ¿éÊý */
+ uint32_t block_size; /* ÿ¿éµÄ´óС */
+};
+
+#endif /* _DENALI_H_*/
+
diff --git a/boot/common/src/loader/include/asm/arch-m0/gpio.h b/boot/common/src/loader/include/asm/arch-m0/gpio.h
new file mode 100644
index 0000000..82db90f
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/gpio.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZXIC Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author: zhouqi
+ * Date: 2013-4-2
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __GPIO_7520_H__
+#define __GPIO_7520_H__
+
+
+/*
+*******************************************************************************
+ * GPIO MUX UART1
+ ******************************************************************************
+ */
+#if 0
+#define STANDBY_PAD 0x0010E000
+#define STANDBY_PAD_UART1_RXD (STANDBY_PAD + 0x5C)
+#define UART1_RXD (0x1 << 24)
+#define STANDBY_PAD_UART1_TXD (STANDBY_PAD + 0x60)
+#define UART1_TXD (0x1 << 24)
+
+#define STANDBY_PAD_UART_MASK (0x7 << 24)
+#endif
+
+/*PIN MUX*/
+#define ZX29_PIN_MUX 0x01303000
+#define GPIO_PINMUX_REG_BASE ZX29_PIN_MUX
+
+/*PAD*/
+#define ZX29_A1_PAD_CTRL0 0x0013C000
+#define PAD_CTRL_REG_BASE ZX29_A1_PAD_CTRL0
+
+
+#define PD_FUNC_SEL_BASE (GPIO_PINMUX_REG_BASE)
+#define AON_FUNC_SEL_BASE (PAD_CTRL_REG_BASE)
+#define TOP_FUNC_SEL_BASE (PAD_CTRL_REG_BASE)
+#define IO_CFG_BASE (PAD_CTRL_REG_BASE+0x800)
+
+
+#endif /*__GPIO_7520_H__*/
+
diff --git a/boot/common/src/loader/include/asm/arch-m0/spifc.h b/boot/common/src/loader/include/asm/arch-m0/spifc.h
new file mode 100755
index 0000000..f507dbc
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/spifc.h
@@ -0,0 +1,251 @@
+/*********************************************************************
+ Copyright 2016 by ZXIC Corporation.
+*
+* FileName:: spi_fc.h
+* File Mark:
+* Description:
+* Others:
+* Version:
+* Author:
+* Date:
+
+* History 1:
+* Date: 2014.1.15
+* Version:
+* Author: zhouqi
+* Modification:
+* History 2:
+**********************************************************************/
+
+#ifndef __SPI_FC_H__
+#define __SPI_FC_H__
+
+
+#define SYS_SPI_NAND_BASE 0x01407000
+
+
+struct spi_t
+{
+ uint32_t VER_REG; //0x00
+ uint32_t SFC_START; //0x04
+ uint32_t SFC_EN; //0x08
+ uint32_t SFC_CTRL0; //0x0c
+ uint32_t SFC_CTRL1; //0x10
+ uint32_t SFC_CTRL2; //0x14
+ uint32_t SFC_BYTE_NUM; //0x18
+ uint32_t SFC_ADDR; //0x1c
+ uint32_t SFC_INS; //0x20
+ uint32_t SFC_TIMING; //0x24
+ uint32_t SFC_INT_EN; //0x28
+ uint32_t SFC_INT_RAW; //0x2c
+ uint32_t SFC_INT_SW_CLR; //0x30
+ uint32_t SFC_SW; //0x34
+ uint32_t SFC_DATA; //0x38
+};
+
+/*spifc start 0x4*/
+#define FC_START (1<<0)
+#define FC_BUSY (1<<0)
+
+/*spifc enable 0x8*/
+#define FC_EN_BACK (1<<1)
+#define FC_EN (1<<0)
+
+/*spifc main ctr0 0xc*/
+#define FC_SCLK_PAUSE_CLR_ALLOW (1<<17)
+#define FC_SCLK_PAUSE_EN (1<<16)
+#define FC_TXFIFO_CLR (1<<15)
+#define FC_RXFIFO_CLR (1<<14)
+#define FC_TXFIFO_THRES (1<<10)
+#define FC_RXFIFO_THRES (1<<6)
+#define FC_TX_DMA_EN (1<<5)
+#define FC_RX_DMA_EN (1<<4)
+#define FC_WDOG_EN (1<<3)
+#define FC_SPI_MODE (1<<1)
+#define FC_WR_PROTECT (1<<0)
+
+/*spifc ctrl1 0x10 in the condition : SFC_EN = 1 SFC_BUSY = 0*/
+#define FC_ADDR_TX_EN (4)
+#define FC_DUMMY_TX_EN (2)
+#define FC_READ_DAT_EN (1)
+#define FC_WRITE_DAT_EN (0)
+
+/*spifc ctrl2 0x14*/
+#define FC_DUMMY_BYTE_NUM (12) /* [12:15} */
+#define FC_DUMMY_BIT_NUM (8) /* [8:10] */
+#define FC_ADDR_BYTE_NUM (5) /* [5:6] */
+#define FC_ADDR_BYTE_NUM_8 (0)
+#define FC_ADDR_BYTE_NUM_16 (1)
+#define FC_ADDR_BYTE_NUM_24 (2)
+#define FC_ADDR_BYTE_NUM_32 (3)
+#define FC_ADDR_MULTI_LINE_EN (1<<4)
+#define FC_DAT_MULTI_LINE_EN (1<<2)
+#define FC_TRANS_MOD (1<<0)
+
+/*spifc timing 0x24*/
+#define FC_READ_DELAY (1<<16) /* [17:16} */
+#define FC_T_CS_SETUP (1<<11) /* [11:13} */
+#define FC_T_CS_HOLD (1<<6) /* [8:6} */
+#define FC_T_CS_DESEL (1<<0) /* [0:3} */
+
+
+/*spifc int enable 0x28*/
+#define FC_INT_EN_TX_BYD_THES (1<<7)
+#define FC_INT_EN_RX_BYD_THES (1<<6)
+#define FC_INT_EN_TX_UNDERRUN (1<<5)
+#define FC_INT_EN_RX_OVERRUN (1<<4)
+#define FC_INT_EN_WDOG_OVERRUN (1<<2)
+#define FC_INT_EN_FMT_ERR (1<<1)
+#define FC_INT_EN_CMD_END (1<<0)
+
+/*spifc raw interrupt 0x2c*/
+#define FC_INT_RAW_TX_BYD_THES (1<<7)
+#define FC_INT_RAW_RX_BYD_THES (1<<6)
+#define FC_INT_RAW_TX_UNDERRUN (1<<5)
+#define FC_INT_RAW_RX_OVERRUN (1<<4)
+#define FC_INT_RAW_WDOG_OVERRUN (1<<2)
+#define FC_INT_RAW_FMT_ERR (1<<1)
+#define FC_INT_RAW_CMD_END (1<<0)
+#define FC_INT_RAW_MASK (FC_INT_RAW_TX_UNDERRUN| \
+ FC_INT_RAW_RX_OVERRUN| \
+ FC_INT_RAW_WDOG_OVERRUN| \
+ FC_INT_RAW_FMT_ERR| \
+ FC_INT_RAW_CMD_END)
+
+/*spifc int startus and clr 0x30*/
+#define FC_INT_CLR_TX_BYD_THES (1<<7)
+#define FC_INT_CLR_RX_BYD_THES (1<<6)
+#define FC_INT_CLR_TX_UNDERRUN (1<<5)
+#define FC_INT_CLR_RX_OVERRUN (1<<4)
+#define FC_INT_CLR_WDOG_OVERRUN (1<<2)
+#define FC_INT_CLR_FMT_ERR (1<<1)
+#define FC_INT_CLR_CMD_END (1<<0)
+
+/*spifc sw 0x34*/
+#define FC_TX_FIFO_CNT (16) /* [16:20} */
+#define FC_TX_FIFO_CNT_MASK (0x1F) /* [8:12} */
+#define FC_RX_FIFO_CNT (8) /* [8:12} */
+#define FC_RX_FIFO_CNT_MASK (0x1F) /* [8:12} */
+#define FC_TX_BYD_THRES (1<<5)
+#define FC_RX_BYD_THRES (1<<4)
+#define FC_SCLK_PAUSE_FLAG (1<<3)
+#define FC_WAIT_FLAG (1<<2)
+#define FC_FORMAT_ERR (1<<1)
+
+
+#define FC_DMA_NONE 0
+#define FC_DMA_TX 1
+#define FC_DMA_RX 2
+
+
+#define ADDR_TX_EN 1 /* µØÖ·Âë·¢ËÍʹÄÜ */
+#define ADDR_TX_DIS 0
+#define DATA_TX_EN 1
+#define DATA_TX_DIS 0
+#define DATA_RX_EN 1
+#define DATA_RX_DIS 0
+#define DUMY_TX_EN 1
+#define DUMY_TX_DIS 0
+
+#define ADDR_WIDTH_8 0
+#define ADDR_WIDTH_16 1
+#define ADDR_WIDTH_24 2
+#define ADDR_WIDTH_32 3
+
+struct spiflash_cmd_t
+{
+ uint8_t cmd; /* Ö¸ÁîÂë */
+ uint8_t addr_tx_en; /* µØÖ·Âë·¢ËÍʹÄÜ */
+ uint8_t addr_width; /* µØÖ·Âë¿í¶È */
+ uint8_t data_tx_en; /* ·¢ËÍÊý¾ÝʹÄÜ---д */
+ uint8_t data_rx_en; /* ½ÓÊÕÊý¾ÝʹÄÜ---¶Á */
+ uint8_t dumy_tx_en; /* ¿ÕÏеȴýÖÜÆÚʹÄÜ */
+ uint8_t dumy_bytes; /* ¿ÕÏеȴýÖÜÆÚ x8 */
+ uint8_t dumy_bits; /* ¿ÕÏеȴýÖÜÆÚ x1 */
+};
+
+
+/* SPI NAND CMD */
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_WRITE_DISABLE 0x04
+#define CMD_GET_FEATURE 0x0F
+#define CMD_SET_FEATURE 0x1F
+
+#define CMD_READ_PAGE_TO_CACHE 0x13
+#define CMD_READ_FROM_CACHE 0x03
+//#define CMD_READ_FROM_CACHE_X2 0x3B
+#define CMD_READ_FROM_CACHE_X4 0x6B
+#define CMD_READ_FROM_CACHE_QIO 0xEB
+
+#define CMD_READ_ID 0x9F
+#define ID_ADDR0 0x00
+#define ID_ADDR1 0x01
+
+#define CMD_PROGRAM_LOAD 0x02
+#define CMD_PROGRAM_LOAD_X4 0x32
+
+#define CMD_PROGRAM_EXECUTE 0x10
+//#define CMD_PROGRAM_LOAD_RANDOM 0x84
+//#define CMD_PROGRAM_LOAD_RANDOM_X4 0xC4
+//#define CMD_PROGRAM_LOAD_RANDOM_QIO 0x72
+
+#define CMD_BLOCK_ERASE 0xD8
+
+#define CMD_RESET 0xFF
+
+//fpga
+#define CMD_READ_BYTE 0x03
+#define CMD_READ_TO_CACHE 0x13
+#define CMD_GET_FEATURE 0x0F
+#define CMD_END 0x00//unused cmd
+#define OIP_BIT (1<<0)
+
+
+#define SINGLE_MODE 0
+//#define DUAL_MODE 1
+#define RDX4_MODE 2
+#define RDQIO_MODE 3
+#define PLX4_MODE 4
+
+/*read and write mode configuration*/
+//#define RD_MODE RDX4_MODE
+#define RD_MODE RDQIO_MODE
+//#define RD_MODE SINGLE_MODE
+#define WR_MODE PLX4_MODE
+
+/* SPI NAND REGISTER */
+#define REG_PROTECTION 0xA0
+#define REG_FEATURE 0xB0
+#define ECC_EN (0x1<<4)
+#define QE 0x0
+#define REG_STATUS 0xC0
+#define ECC_ERR_BIT (0x4) /* ECC ERR */
+#define ECC_ERR_MASK (0x3<<4) /* ECC ERR */
+#define P_FAIL (0x1<<3) /* program fail*/
+#define E_FAIL (0x1<<2) /* erase fail */
+#define WEL (0x1<<1) /* Write Enable Latch */
+#define OIP (0x1<<0) /* Operation In Progress */
+
+#define WRAP_SIZE_MAIN_OOB (0x0<<12) /* 2048 +64 = 2112 */
+#define WRAP_SIZE_MAIN (0x4<<12) /* 2048 */
+#define WRAP_SIZE_OOB (0x8<<12) /* 64 */
+#define WRAP_SIZE_MINI (0xC<<12) /* 16 */
+
+
+/*spi flash É豸ÃèÊö½á¹¹Ìå*/
+struct spi_flash_device_para
+{
+ uint8_t manuf_id; /* ³§¼ÒID */
+ uint8_t device_id; /* É豸ID */
+ uint8_t res_id; /* Æ÷¼þID */
+ uint16_t page_size; /* ÿҳmainÇøÓò´óС */
+ uint16_t page_size_shift;
+ uint16_t oob_size; /* ÿҳspareÇøÓò´óС */
+ uint16_t block_size_shift;
+ uint16_t block_num; /* ¿éÊý */
+ uint32_t block_size; /* ÿ¿éµÄ´óС */
+ uint32_t planes;
+};
+
+#endif /* __SPI_FC_H__ */
+
diff --git a/boot/common/src/loader/include/asm/arch-m0/top_clock.h b/boot/common/src/loader/include/asm/arch-m0/top_clock.h
new file mode 100644
index 0000000..2325e31
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/top_clock.h
@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZXIC Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author: zhouqi
+ * Date: 2013-4-2
+ * History 1:
+ * Date: 2013-6-25
+ * Version:v1.1
+ * Author: cjg
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __TOP_CLOCK_H__
+#define __TOP_CLOCK_H__
+
+//----------- TOP_CRM ------------------------------------------------
+#define TOP_CRM_BASE 0x013B000
+
+#define WIFI_SSBUFFER (TOP_CRM_BASE+0x008)
+#define WIFI_SSBUFFER_EN (0x1 << 0) /* Def: 0 */
+
+#define WIFI_SSBUFFER (TOP_CRM_BASE+0x008)
+#define WIFI_SSBUFFER_EN (0x1 << 0) /* Def: 0 */
+
+#define BOOTSEL_INFO (TOP_CRM_BASE+0x4)
+
+
+//----------- LSP_CRPM ------------------------------------------------
+#define LSP_CRPM_BASE 0x01400000
+
+#define CRPM_CLKSET (LSP_CRPM_BASE + 0x0)
+#define COM_CLK_SEL (0x1 << 0)
+
+#define CRPM_CLKDIV1 (LSP_CRPM_BASE + 0x24)
+#define CRPM_CLKDIV1_MASK (0xF << 16)
+#define TIMER0_DIV_12 (0xB << 16)
+
+//----------- SOCCRM ---------------------------------------------------
+#define STANDBY_CRM_BASE 0x01306000
+
+#define MATRIX_AXI_SEL (STANDBY_CRM_BASE + 0x00)
+#define PS_CORE_SEL (STANDBY_CRM_BASE + 0x20)
+#define PHY_CORE_SEL (STANDBY_CRM_BASE + 0x30)
+#define AP_CORE_SEL (STANDBY_CRM_BASE + 0x40)
+
+//#define NAND_CLKDIV (STANDBY_CRM_BASE + 0x40)
+#define MATRIX_MODEM_RESET (STANDBY_CRM_BASE + 0x50)
+
+#define NAND_WCLK_SEL (0x1)//26M
+
+
+//----------- PCU ----------------------------------------------
+#define SYSTEM_CONFIG_REG 0x0010d600
+#define PULL_OUTPUT_SEL (0x1 << 30)
+
+//----------- TOP_SYSCLK ----------------------------------------------
+#define TOP_SYSCLK_BASE 0x0013b000
+
+#define MPLL_CFG0_REG ( TOP_SYSCLK_BASE + 0x008 )
+#define UPLL_CFG0_REG ( TOP_SYSCLK_BASE + 0x010 )
+#define GPLL_CFG0_REG ( TOP_SYSCLK_BASE + 0x110 )
+//#define APLL_CFG0_REG ( TOP_SYSCLK_BASE + 0x018 )
+//#define DPLL_CFG0_REG ( TOP_SYSCLK_BASE + 0x028 )
+//#define DPLL_CFG1_REG ( TOP_SYSCLK_BASE + 0x02c )
+
+#define M0_CORE_SEL (TOP_SYSCLK_BASE + 0x038)
+#define HS_AHB_CLK (TOP_SYSCLK_BASE + 0x03c)
+
+#define PLL_LOCK_CNT0 ( TOP_SYSCLK_BASE + 0x030 )
+#define PLL_LOCK_CNT1 ( TOP_SYSCLK_BASE + 0x034 )
+#define RMCORE_CLK_CFG_REG ( TOP_SYSCLK_BASE + 0x050 )
+#define RM_MOD_CLKSEL ( TOP_SYSCLK_BASE + 0x054 )
+
+/*pll cfg0 reg map*/
+
+/*pll cfg1 reg map*/
+#define PLL_CFG1_DACAP (0x1 << 27)
+#define PLL_CFG1_FOUT4PHASEPD (0x1 << 26)
+#define PLL_CFG1_FOUTPOSTDIVPD (0x1 << 25)
+#define PLL_CFG1_FOUTVCOPD (0x1 << 24)
+#define PLL_CFG1_FRAC (0x1 << 0)
+
+#endif /*__TOP_CLOCK_H__*/
diff --git a/boot/common/src/loader/include/asm/arch-m0/uart.h b/boot/common/src/loader/include/asm/arch-m0/uart.h
new file mode 100644
index 0000000..8084fed
--- /dev/null
+++ b/boot/common/src/loader/include/asm/arch-m0/uart.h
@@ -0,0 +1,84 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZXIC Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author: zhouqi
+ * Date: 2013-4-2
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __UART_7520_H__
+#define __UART_7520_H__
+#include "common.h"
+
+
+/********************************************************************************
+ * UART
+ *******************************************************************************/
+#define UART0_BASE 0X131000
+#define UART1_BASE 0x1408000
+#define UART2_BASE 0x140d000
+#define PAD_TOP_FUNC_BASE 0x13c000
+#define PAD_PD_FUNC_BASE 0x1303000
+
+#define UART_BASE UART1_BASE
+
+#define UART_VS (UART_BASE + 0x00)
+#define UART_DR (UART_BASE + 0x04)
+#define UART_TSC (UART_BASE + 0x08)
+#define UART_RSR (UART_BASE + 0x10)
+#define UART_FR (UART_BASE + 0x14)
+#define UART_TXFF (0x1 << 5)
+#define UART_RXFE (0x1 << 4)
+#define UART_FR_TXBUSY (1<<8)
+
+#define UART_ILPR (UART_BASE + 0x20)
+#define UART_IBRD (UART_BASE + 0x24)
+#define UART_FBRD (UART_BASE + 0x28)
+#define UART_LCR_H (UART_BASE + 0x30)
+#define UART_SPS (0x1 << 7) // Stick Parity select
+#define UART_WLEN_8 (0x3 << 5) // Word length: 8 bits
+#define UART_FEN (0x1 << 4) // Enable FIFOs
+#define UART_STP2 (0x1 << 3) // Number of stop bits,"1": 2stop bits transmitted
+#define UART_EPS (0x1 << 2) // Even parity select
+#define UART_PEN (0x1 << 1) // Parity enable
+#define UART_BREAK (0x1 << 0) // Send break
+#define UART_CR (UART_BASE + 0x34)
+#define UART_CTSE (0x1 << 15) // CTS hardware flow control enable
+#define UART_RTSE (0x1 << 14) // RTS hardware flow control enable
+#define UART_OUT2 (0x1 << 13) // out2
+#define UART_OUT1 (0x1 << 12) // out1
+#define UART_RTS (0x1 << 11) // request to send
+#define UART_DTR (0x1 << 10) // data transmit ready
+#define UART_RXE (0x1 << 9) // Receive Enable (RXE)"1"
+#define UART_TXE (0x1 << 8) // "1": Transmit Enable (TXE)
+#define UART_LBE (0x1 << 7) // "1": Loop Back Enable
+#define UART_SIRLP (0x1 << 2) // "1": IrDA SIR Low Power Mode
+#define UART_SIR_EN (0x1 << 1) // "0": SIR disable; "1": SIR enable
+#define UART_EN (0x1 << 0) // "0": uart disable; "1": uart enable
+#define UART_IFLS (UART_BASE + 0x38)
+#define UART_IMSC (UART_BASE + 0x40)
+#define UART_RIS (UART_BASE + 0x44)
+#define UART_MIS (UART_BASE + 0x48)
+#define UART_ICR (UART_BASE + 0x4C)
+#define UART_DMACR (UART_BASE + 0x50)
+
+#define UART_INT_MASK (0xFFFFFFFF)
+
+
+extern void uart_init(void);
+extern char uart_getc(void);
+extern void uart_putc(const char c);
+extern void uart_puts(const char *s);
+
+
+#endif /*__UART_7520_H__*/
+