| data.set 0x01306100 %long 0x00cfe000 //ddr all reset enable bit6-12=0 | |
| Wait 0.01s | |
| data.set 0x01306100 %long 0x00cff400 //release ddr apb(bit10) and phy reset(bit12) | |
| Wait 0.01s | |
| data.set 0x0121a004 %long 0xf0000001 //PIR //bypass pll lock, DDL cal and ZQ cal | |
| //check 0x0121a018 bit0=1 | |
| Wait 0.01s | |
| //select ddr work mode here, then select ddr top clk | |
| data.set 0x0121a020 %long 0xa01b8000 //bypass | |
| //data.set 0x0121a020 %long 0x001b8000 //misson | |
| //DDR top clock select top clk 624M, bit0-2, 0=624, 1=26, 2=416, 3=312, 4=208, 5=200, 6=104 | |
| //0: top clk=624M, ddr use bypss mode , dram io clk=312M | |
| //1: top clk=26M, ddr use bypss mode , dram io clk=13M | |
| //2: top clk=416M, ddr use bypss mode , dram io clk=208M | |
| //3: top clk=312M, ddr use bypss mode , dram io clk=156M | |
| //4: top clk=208M, ddr use bypss mode , dram io clk=104M, ddr use mission mode , dram io clk=416M | |
| //5: top clk=200M, ddr use bypss mode , dram io clk=100M, ddr use mission mode , dram io clk=400M | |
| //6: top clk=104M, ddr use bypss mode , dram io clk=52M | |
| data.set 0x01306050 %long 0x01511110 | |
| //phy register init | |
| data.set 0x0121a00C %long 0x0380c7a0 //VALUE_PGCR1 / LBMODE:RW:31:1:=0x0 LBGDQS:RW:29:2:=0x0 LBDQSS:RW:28:1:=0x0 IOLB:RW:27:1:=0x0 INHVT:RW:26:1:=0x0 PHYHRST:RW:25:1:=0x1 ACBVT:RW:24:1:=0x1 ACDLVT:RW:23:1:=0x1 DLDLMT:RW:15:8:=0x1 FDEPTH:RW:13:2:=0x2 LPFDEPTH:RW:11:2:=0x0 LPFEN:RW:10:1:=0x1 MDLEN:RW:9:1:=0x1 IODDRM:RW:7:2:=0x3 WLSELT:RW:6:1:=0x0 DDLBYPMODE:RW:4:2:=0x2 WLUNCRT:RW:3:1:=0x0 WLSTEP:RW:2:1:=0x0 WLMODE:RW:1:1:=0x0 GPULSE:RW:0:1:=0x0 | |
| data.set 0x0121a014 %long 0x90aa0060 //VALUE_PGCR3 / LPWAKEUP_THRSH:RW:28:4:=0x9 cfg_pub_mode:RW:26:1:=0x0 GDQSS:RW:25:1:=0x0 PRFBYP:RW:24:1:=0x0 CKEN:RW:16:8:=0xaa GATEDXRDCLK:RW:15:1:=0x1 GATEDXDDRCLK:RW:14:1:=0x1 GATEDXCTLCLK:RW:13:1:=0x1 DISACOE:RW:12:1:=0x0 GATEACRDCLK:RW:11:1:=0x1 GATEACDDRCLK:RW:10:1:=0x1 GATEACCTLCLK:RW:9:1:=0x1 RDDLY:RW:5:4:=0x3 RDMODE:RW:3:2:=0x0 DISRST:RW:2:1:=0x0 CLKLEVEL:RW:0:2:=0x0 | |
| data.set 0x0121a024 %long 0x0d20684f //VALUE_PTR0 / tPLLPD:RW:21:11:=0x69 tPLLGS:RW:6:15:=0x1a1 tPHYRST:RW:0:6:=0xf | |
| data.set 0x0121a028 %long 0x0a2903a9 //VALUE_PTR1 / tPLLLOCK:RW:16:16:=0xa29 tPLLRST:RW:0:13:=0x3a9 | |
| data.set 0x0121a030 %long 0x0200f362 //VALUE_PTR3 / tDINIT1:RW:20:9:=0x20 tDINIT0:RW:0:20:=0xf362 | |
| data.set 0x0121a034 %long 0x04e00d64 //VALUE_PTR4 / tDINIT3:RW:18:11:=0x138 tDINIT2:RW:0:18:=0xd64 | |
| data.set 0x0121a080 %long 0x00181224 //VALUE_DXCCR / UDQIOM:RW:21:1:=0x0 UDQPDR:RW:20:1:=0x1 UDQPDD:RW:19:1:=0x1 UDQODT:RW:18:1:=0x0 MSBUDQ:RW:15:3:=0x0 DXSR:RW:13:2:=0x0 DQSNRES:RW:9:4:=0x9 DQSRES:RW:5:4:=0x1 MDLEN:RW:2:1:=0x1 DXIOM:RW:1:1:=0x0 DXODT:RW:0:1:=0x0 | |
| //dfi lowpower enable io powerdown and pll powerdown | |
| data.set 0x0121a084 %long 0x00046487 //VALUE_DSGCR / RSTOE:RW:21:1:=0x0 SDRMODE:RW:19:2:=0x0 RRMODE:RW:18:1:=0x1 ATOAE:RW:17:1:=0x0 DTOOE:RW:16:1:=0x0 DTOIOM:RW:15:1:=0x0 DTOPDR:RW:14:1:=0x1 DTOPDD:RW:13:1:=0x1 DTOODT:RW:12:1:=0x0 PUAD:RW:8:4:=0x4 DQSGX:RW:6:2:=0x2 CUAEN:RW:5:1:=0x0 LPPLLPD:RW:4:1:=0x1 LPIOPD:RW:3:1:=0x0 ZUEN:RW:2:1:=0x1 BDISEN:RW:1:1:=0x1 PUREN:RW:0:1:=0x1 | |
| data.set 0x0121a088 %long 0x00000408 //VALUE_DCR / UDIMM:RW:29:1:=0x0 DDR2T:RW:28:1:=0x0 NOSRA:RW:27:1:=0x0 BYTEMASK:RW:10:8:=0x1 MPRDQ:RW:7:1:=0x0 PDQ:RW:4:3:=0x0 DDR8BNK:RW:3:1:=0x1 DDRMD:RW:0:3:=0x0 | |
| data.set 0x0121a08C %long 0x150e0583 //VALUE_DTPR0 / tRCD:RW:26:5:=0x5 tRRD:RW:22:4:=0x4 tRAS:RW:16:6:=0xe tRP:RW:8:5:=0x5 tWTR:RW:4:4:=0x8 tRTP:RW:0:4:=0x3 | |
| data.set 0x0121a090 %long 0x22814a10 //VALUE_DTPR1 / tAOND_AOFD:RW:30:2:=0x0 tWLO:RW:26:4:=0x8 tWLMRD:RW:20:6:=0x28 tRFC:RW:11:9:=0x29 tFAW:RW:5:6:=0x10 tMOD:RW:2:3:=0x4 | |
| data.set 0x0121a094 %long 0x10000c2c //VALUE_DTPR2 / tCCD:RW:31:1:=0x0 tRTW:RW:30:1:=0x0 tRTODT:RW:29:1:=0x0 tDLLK:RW:19:10:=0x200 tXP:RW:10:5:=0x3 tXS:RW:0:10:=0x2c | |
| data.set 0x0121a098 %long 0x001464d1 //VALUE_DTPR3 / tAOFDx:RW:29:3:=0x0 tMRD:RW:18:5:=0x5 tCKE:RW:13:5:=0x3 tRC:RW:6:7:=0x13 tDQSCKmax:RW:3:3:=0x2 tDQSCK:RW:0:3:=0x1 | |
| data.set 0x0121a0A4 %long 0x00000003 //VALUE_MR2 / WRLEVELING:RW:7:1:=0x0 WLSELECT:RW:6:1:=0x0 nWRE:RW:4:1:=0x0 rl_wl:RW:0:4:=0x6 | |
| data.set 0x0121a0A0 %long 0x00000063 //VALUE_MR1 / nWR:W:5:3:=0x3 WC:W:4:1:=0x0 BT:W:3:1:=0x0 BL:W:0:3:=0x3 | |
| data.set 0x0121a0A8 %long 0x00000002 //VALUE_MR3 / DS:RW:0:4:=0x2 | |
| data.set 0x0121a1A0 %long 0x00000000 //VALUE_MR11 / PDCTL:RW:2:1:=0x0 DQODT:RW:0:2:=0x0 | |
| data.set 0x0121a240 %long 0x04058900 //VALUE_ZQCR / FORCE_ZCAL_VT_UPDATE:RW:27:1:=0x0 DIS_NON_LIN_COMP:RW:26:1:=0x1 PU_ODT_ONLY:RW:25:1:=0x0 ASYM_DRV_EN:RW:24:1:=0x0 IODLMT:RW:17:7:=0x2 AVGEN:RW:16:1:=0x1 AVGMAX:RW:14:2:=0x2 ZCAL:RW:11:3:=0x1 PGWAIT:RW:8:3:=0x1 ZQPD:RW:2:1:=0x0 TERM_OFF:RW:1:1:=0x0 ZCALBYP:RW:0:1:=0x0 | |
| //bit0-3 output:lpddr2(5=80ohm£¬7=60ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm),lpddr3(1=240ohm£¬3=120ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm) | |
| data.set 0x0121a244 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb | |
| data.set 0x0121a254 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb | |
| data.set 0x0121a238 %long 0x00480048 //VALUE_IOVCR0 / EDXVREF:RW:24:7:=0x0 IDXVREF:RW:16:7:=0x48 EACVREF:RW:8:7:=0x0 IACVREF:RW:0:7:=0x48 | |
| data.set 0x0121a23C %long 0x00000048 //VALUE_IOVCR1 / ZQVREF:RW:0:7:=0x48 | |
| //controller register init | |
| data.set 0x01216000 %long 0x03040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0 | |
| data.set 0x01216010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0 | |
| data.set 0x01216030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1 | |
| data.set 0x01216034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2 | |
| data.set 0x01216038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1 | |
| data.set 0x01216050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0 | |
| data.set 0x01216064 %long 0x00260014 //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14 | |
| data.set 0x012160d0 %long 0x001f0001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:11:=0x1 | |
| data.set 0x012160d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0 | |
| data.set 0x012160d8 %long 0x00000405 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5 | |
| data.set 0x012160dc %long 0x00630006 //VALUE_INIT3 / mr:RW:16:16:=0x63 emr:RW:0:16:=0x6 | |
| //dram DS:[19:16] 1:34ohm, 2:40ohm, 3:48ohm | |
| data.set 0x012160e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0 | |
| data.set 0x012160e4 %long 0x00050002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2 | |
| data.set 0x012160f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf | |
| data.set 0x01216100 %long 0x06080a07 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7 | |
| data.set 0x01216104 %long 0x00020209 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9 | |
| data.set 0x01216108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6 | |
| data.set 0x0121610c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0 | |
| data.set 0x01216110 %long 0x03010204 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x3 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4 | |
| data.set 0x01216114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3 | |
| data.set 0x01216118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3 | |
| data.set 0x0121611c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2 | |
| data.set 0x01216138 %long 0x00000016 //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x16 | |
| data.set 0x01216180 %long 0x4039000f //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf | |
| data.set 0x01216184 %long 0x00800100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100 | |
| data.set 0x01216188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0 | |
| data.set 0x01216190 %long 0x07030101 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x7 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x1 dfi_tphy_wrlat:RW:0:6:=0x1 | |
| data.set 0x01216194 %long 0x00030404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x3 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4 | |
| data.set 0x01216198 %long 0x07000101 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x7 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x0 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x0 dfi_lp_en_pd:RW:0:1:=0x1 | |
| data.set 0x012161a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3 | |
| data.set 0x012161a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0 | |
| data.set 0x012161a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10 | |
| data.set 0x012161ac %long 0x00100010 //VALUE_DFIUPD3 / dfi_phyupd_type3:RW:16:12:=0x10 dfi_phyupd_type2:RW:0:12:=0x10 | |
| data.set 0x012161b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0 | |
| data.set 0x01216200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f | |
| data.set 0x01216204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7 | |
| data.set 0x01216208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0 | |
| data.set 0x0121620c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0 | |
| data.set 0x01216210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf | |
| data.set 0x01216214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6 | |
| data.set 0x01216218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6 | |
| data.set 0x01216240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0 | |
| data.set 0x01216244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0 | |
| data.set 0x01216250 %long 0x00001005 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x10 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1 | |
| data.set 0x01216254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0 | |
| //ddr_prority_config | |
| //port read static priority bit0-9, bit0-4 timeout, bit5-9 prority | |
| data.set 0x01216404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff | |
| data.set 0x012164b4 %long 0x000010ff //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20 | |
| data.set 0x01216564 %long 0x0000103f //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0 | |
| data.set 0x01216614 %long 0x0000105f //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4 | |
| //port write static priority bit0-9 | |
| data.set 0x01216408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff | |
| data.set 0x012164b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff | |
| data.set 0x01216568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f | |
| data.set 0x01216618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f | |
| //port read region set | |
| //data.set 0x01216494 %long 0x02000e00 //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| //data.set 0x01216544 %long 0x02000e00 //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| //data.set 0x012165f4 %long 0x02000e00 //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| //data.set 0x012166a4 %long 0x02000e00 //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| //port write region set | |
| //data.set 0x0121649c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| //data.set 0x0121654c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| //data.set 0x012165fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| //data.set 0x012166ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| //vpr timeout, region2 is red queue | |
| //data.set 0x01216498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| //data.set 0x01216548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| //data.set 0x012165f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| //data.set 0x012166a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| //vpw timeout | |
| //data.set 0x012164a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0 | |
| //data.set 0x01216550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0 | |
| //data.set 0x01216600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0 | |
| //data.set 0x012166b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0 | |
| //in CAM set | |
| //data,set 0x0121625c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1 | |
| //data,set 0x01216264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f | |
| //data,set 0x0121626c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f | |
| //data,set 0x01216274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0 | |
| //data,set 0x01216278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0 | |
| //port extern static priority | |
| //REG32(0x00146064) = 0x00000000; //port0,1 level=0=LP; port2,3 level=0=LP | |
| //wait all register config into hardware | |
| Wait 0.01s | |
| data.set 0x01306100 %long 0x00cfffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) | |
| Wait 0.01s | |
| //sw config done | |
| data.set 0x01216320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0 | |
| //check phy auto init done, wait 0x01216324 bit0 =0 | |
| Wait 0.01s | |
| data.set 0x0121a004 %long 0x00040001 //PIR //notify phy that sdram will be initialized by controller | |
| //check 0x0121a018 bit0=1 and bit4=1 | |
| Wait 0.01s | |
| //manual trigger calibrate | |
| data.set 0x0121a004 %long 0x00000023 //PIR //DDL cal, ZQ cal (for bypass) | |
| //data.set 0x0121a004 %long 0x00000033 //PIR //DDL cal, ZQ cal, PLL init (for mission) | |
| //check 0x0121a018 bit0-3=1011 | |
| Wait 0.01s | |
| //enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd | |
| data.set 0x012161b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 | |
| //check controller status is sdram init done,wait 0x01216004 bit0-2 !=0 | |
| Wait 0.01s | |
| //training | |
| //bit0-1 auto enter powerdown and selfrefresh, training must close this function | |
| //data.set 0x01216030 %long 0x00000000 //PWRCTL // selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1 | |
| //data.set 0x0121a0b0 %long 0x81001097 //DTCR //only select rank0 do training 0x91001087 bit13ÊÇ·ñ´ò¿ª£¿ | |
| //data.set 0x0121a004 %long 0xf001 | |
| //check 0x0121a018 bit0=1 and bit8-11=1111 | |
| Wait 0.01s | |
| data.set 0x01216490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1 | |
| data.set 0x01216540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1 | |
| data.set 0x012165f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1 | |
| data.set 0x012166a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1 |