| //enable pcu_ddrc/phy_clken | |
| data.set 0x01307078 %long 0x3 | |
| //bit6-12 default=0 is reset on, bit10=1,bit12=1,ddr phy_core_clk and pclk domain reset release | |
| data.set 0x01307080 %long 0x000ff400 | |
| Wait 0.01s | |
| //pll lock bypass | |
| data.set 0x01304004 %long 0xf0000001 // INITBYP:RWSC:31:1:=0x0 ZCALBYP:RWSC:30:1:=0x0 DCALBYP:RWSC:29:1:=0x0 LOCKBYP:RWSC:28:1:=0x1 CLRSR:RWSC:27:1:=0x0 RDIMMINIT:RW:19:1:=0x0 CTLDINIT:RW:18:1:=0x0 PLLBYP:RW:17:1:=0x1 ICPC:RW:16:1:=0x0 WREYE:RW:15:1:=0x0 RDEYE:RW:14:1:=0x0 WRDSKW:RW:13:1:=0x0 RDDSKW:RW:12:1:=0x0 WLADJ:RW:11:1:=0x0 QSGATE:RW:10:1:=0x0 WL:RW:9:1:=0x0 DRAMINIT:RW:8:1:=0x0 DRAMRST:RW:7:1:=0x0 PHYRST:RW:6:1:=0x0 DCAL:RW:5:1:=0x0 PLLINIT:RW:4:1:=0x0 CA:RW:2:1:=0x0 INIT:RWSC:0:1:=0x1 | |
| Wait 0.01s | |
| //DDR top clock select top clk 624M, bit0-2, 0=624, 1=26, 2=491.52, 3=416, 4=312, 5=104, 6=208, 7=245.76 | |
| //0: top clk=624M, ddr use bypss mode , dram io clk=312M | |
| //1: top clk=26M, ddr use bypss mode , dram io clk=13M | |
| //2: top clk=491.52M, ddr use bypss mode , dram io clk=245M | |
| //3: top clk=416M, ddr use bypss mode , dram io clk=208M | |
| //4: top clk=312M, ddr use bypss mode , dram io clk=156M | |
| //5: top clk=104M, ddr use bypss mode , dram io clk=52M | |
| //6: top clk=208M, ddr use bypss mode , dram io clk=104M, ddr use mission mode , dram io clk=416M | |
| //7: top clk=245.76M, ddr use bypss mode , dram io clk=122M, ddr use mission mode , dram io clk=491M | |
| data.set 0x01307040 %long 0x00010010 | |
| //pll bypass and powerdown | |
| data.set 0x01304020 %long 0xa01b8000 // BYP:RW:31:1:=0x1 PLLRST:RW:30:1:=0x0 PLLPD:RW:29:1:=0x1 LOCKPS:RW:24:1:=0x0 LOCKCS:RW:23:1:=0x0 LOCKDS:RW:22:1:=0x0 RGVINT:RW:21:1:=0x0 FRQSEL:RW:19:2:=0x3 RGSHIFT:RW:18:1:=0x0 CPPC:RW:14:4:=0xe CPIC:RW:12:2:=0x0 GSHIFT:RW:11:1:=0x0 ATOEN:RW:7:4:=0x0 ATC:RW:3:4:=0x0 DTC:RW:0:3:=0x0 | |
| //phy register init | |
| data.set 0x01304240 %long 0x04058802 // FORCE_ZCAL_VT_UPDATE:RW:27:1:=0x0 DIS_NON_LIN_COMP:RW:26:1:=0x1 PU_ODT_ONLY:RW:25:1:=0x0 ASYM_DRV_EN:RW:24:1:=0x0 IODLMT:RW:17:7:=0x2 AVGEN:RW:16:1:=0x1 AVGMAX:RW:14:2:=0x2 ZCAL:RW:11:3:=0x1 PGWAIT:RW:8:3:=0x0 ZQPD:RW:2:1:=0x0 ZCAL:RW:1:1:=0x1 ZCALBYP:RW:0:1:=0x0 | |
| data.set 0x01304024 %long 0x09e04e4f // tPLLPD:RW:21:11:=0x4f tPLLGS:RW:6:15:=0x139 tPHYRST:RW:0:6:=0xf | |
| data.set 0x01304028 %long 0x07a202c0 // tPLLLOCK:RW:16:16:=0x7a2 tPLLRST:RW:0:13:=0x2c0 | |
| data.set 0x01304088 %long 0x00000408 // UDIMM:RW:29:1:=0x0 DDR2T:RW:28:1:=0x0 NOSRA:RW:27:1:=0x0 BYTEMASK:RW:10:8:=0x1 MPRDQ:RW:7:1:=0x0 PDQ:RW:4:3:=0x0 DDR8BNK:RW:3:1:=0x1 DDRMD:RW:0:3:=0x0 | |
| data.set 0x01304030 %long 0x0200f362 // tDINIT1:RW:20:9:=0x20 tDINIT0:RW:0:20:=0xf362 | |
| data.set 0x01304034 %long 0x04e00d64 // tDINIT3:RW:18:11:=0x138 tDINIT2:RW:0:18:=0xd64 | |
| data.set 0x013040A4 %long 0x00000006 // WRLEVELING:RW:7:1:=0x0 WLSELECT:RW:6:1:=0x0 nWRE:RW:4:1:=0x0 rl_wl:RW:0:4:=0x6 | |
| data.set 0x013040A0 %long 0x00000063 // nWR:W:5:3:=0x3 WC:W:4:1:=0x0 BT:W:3:1:=0x0 BL:W:0:3:=0x3 | |
| data.set 0x013040A8 %long 0x00000002 // DS:RW:0:4:=0x2 | |
| data.set 0x013041A0 %long 0x00000000 // PDCTL:RW:2:1:=0x0 DQODT:RW:0:2:=0x0 | |
| data.set 0x01304080 %long 0x00181224 // UDQIOM:RW:21:1:=0x0 UDQPDR:RW:20:1:=0x1 UDQPDD:RW:19:1:=0x1 UDQODT:RW:18:1:=0x0 MSBUDQ:RW:15:3:=0x0 DXSR:RW:13:2:=0x0 DQSNRES:RW:9:4:=0x9 DQSRES:RW:5:4:=0x1 MDLEN:RW:2:1:=0x1 DXIOM:RW:1:1:=0x0 DXODT:RW:0:1:=0x0 | |
| data.set 0x01304084 %long 0x0004649f // RSTOE:RW:21:1:=0x0 SDRMODE:RW:19:2:=0x0 RRMODE:RW:18:1:=0x1 ATOAE:RW:17:1:=0x0 DTOOE:RW:16:1:=0x0 DTOIOM:RW:15:1:=0x0 DTOPDR:RW:14:1:=0x1 DTOPDD:RW:13:1:=0x1 DTOODT:RW:12:1:=0x0 PUAD:RW:8:4:=0x4 DQSGX:RW:6:2:=0x2 CUAEN:RW:5:1:=0x0 LPPLLPD:RW:4:1:=0x1 LPIOPD:RW:3:1:=0x1 ZUEN:RW:2:1:=0x1 BDISEN:RW:1:1:=0x1 PUREN:RW:0:1:=0x1 | |
| data.set 0x0130408C %long 0x150e0583 // tRCD:RW:26:5:=0x5 tRRD:RW:22:4:=0x4 tRAS:RW:16:6:=0xe tRP:RW:8:5:=0x5 tWTR:RW:4:4:=0x8 tRTP:RW:0:4:=0x3 | |
| data.set 0x01304090 %long 0x22814a10 // tAOND_AOFD:RW:30:2:=0x0 tWLO:RW:26:4:=0x8 tWLMRD:RW:20:6:=0x28 tRFC:RW:11:9:=0x29 tFAW:RW:5:6:=0x10 tMOD:RW:2:3:=0x4 | |
| data.set 0x01304094 %long 0x10000c2c // tCCD:RW:31:1:=0x0 tRTW:RW:30:1:=0x0 tRTODT:RW:29:1:=0x0 tDLLK:RW:19:10:=0x200 tXP:RW:10:5:=0x3 tXS:RW:0:10:=0x2c | |
| data.set 0x01304098 %long 0x001464d1 // tAOFDx:RW:29:3:=0x0 tMRD:RW:18:5:=0x5 tCKE:RW:13:5:=0x3 tRC:RW:6:7:=0x13 tDQSCKmax:RW:3:3:=0x2 tDQSCK:RW:0:3:=0x1 | |
| data.set 0x01304014 %long 0x90aaee60 // LPWAKEUP_THRSH:RW:28:4:=0x9 GDQSS:RW:25:1:=0x0 PRFBYP:RW:24:1:=0x0 CKEN:RW:16:8:=0xaa GATEDXRDCLK:RW:15:1:=0x1 GATEDXDDRCLK:RW:14:1:=0x1 GATEDXCTLCLK:RW:13:1:=0x1 DISACOE:RW:12:1:=0x0 GATEACRDCLK:RW:11:1:=0x1 GATEACDDRCLK:RW:10:1:=0x1 GATEACCTLCLK:RW:9:1:=0x1 RDDLY:RW:5:4:=0x3 RDMODE:RW:3:2:=0x0 DISRST:RW:2:1:=0x0 CLKLEVEL:RW:0:2:=0x0 | |
| data.set 0x01304238 %long 0x00480048 // EDXVREF:RW:24:7:=0x0 IDXVREF:RW:16:7:=0x48 EACVREF:RW:8:7:=0x0 IACVREF:RW:0:7:=0x48 | |
| data.set 0x0130423C %long 0x00000048 // ZQVREF:RW:0:7:=0x48 | |
| //controller register init | |
| data.set 0x01303000 %long 0x03040004 // device_config:RW:30:2:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0 | |
| data.set 0x01303020 %long 0x00000000 // derate_value:RW:0:1:=0x0 derate_enable:RW:0:1:=0x0 | |
| data.set 0x01303024 %long 0x00800000 // mr4_read_interval:RW:0:32:=0x800000 | |
| data.set 0x01303030 %long 0x00000003 // selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1 | |
| data.set 0x01303034 %long 0x00052002 // selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2 | |
| data.set 0x01303038 %long 0x00030003 // hw_lp_idle_x32:RW:16:12:=0x0 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1 | |
| data.set 0x01303050 %long 0x00210000 // refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0 | |
| data.set 0x01303054 %long 0x00000000 // refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0 | |
| data.set 0x01303058 %long 0x00000000 // refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0 | |
| data.set 0x01303060 %long 0x00000000 // refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0 | |
| data.set 0x01303064 %long 0x00260014 // t_rfc_nom_x32:RW:16:12:=0x26 t_rfc_min:RW:0:9:=0x14 | |
| data.set 0x013030d0 %long 0x001f0001 // skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:10:=0x1 | |
| data.set 0x013030d4 %long 0x00000000 // dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0 | |
| data.set 0x013030d8 %long 0x00000405 // idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5 | |
| data.set 0x013030dc %long 0x00630006 // mr:RW:16:16:=0x63 emr:RW:0:16:=0x6 | |
| data.set 0x013030e0 %long 0x00020000 // emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0 | |
| data.set 0x013030e4 %long 0x00050002 // dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2 | |
| data.set 0x013030f4 %long 0x0000066f // diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf | |
| data.set 0x01303100 %long 0x06080a07 // wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7 | |
| data.set 0x01303104 %long 0x00020209 // t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9 | |
| data.set 0x01303108 %long 0x0204060a // write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:5:=0x6 wr2rd:RW:0:6:=0xa | |
| data.set 0x0130310c %long 0x00501000 // t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0 | |
| data.set 0x01303110 %long 0x03010204 // t_rcd:RW:24:5:=0x3 t_ccd:RW:16:3:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4 | |
| data.set 0x01303114 %long 0x01010303 // t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3 | |
| data.set 0x01303118 %long 0x02020003 // t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3 | |
| data.set 0x0130311c %long 0x00000202 // t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2 | |
| data.set 0x01303120 %long 0x03030202 // t_xs_fast_x32:RW:24:7:=0x3 t_xs_abort_x32:RW:16:7:=0x3 t_xs_dll_x32:RW:8:7:=0x2 t_xs_x32:RW:0:7:=0x2 | |
| data.set 0x01303180 %long 0x2039000f // dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x0 zq_resistor_shared:RW:29:1:=0x1 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf | |
| data.set 0x01303184 %long 0x00800100 // t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100 | |
| data.set 0x01303188 %long 0x00000000 // zq_reset:RW:0:1:=0x0 | |
| data.set 0x01303190 %long 0x07020101 // dfi_t_ctrl_delay:RW:24:5:=0x7 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x2 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x1 dfi_tphy_wrlat:RW:0:6:=0x1 | |
| data.set 0x01303194 %long 0x00030404 // dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x3 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4 | |
| data.set 0x01303198 %long 0x07000101 // dfi_tlp_resp:RW:24:4:=0x7 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x0 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x0 dfi_lp_en_pd:RW:0:1:=0x1 | |
| data.set 0x013031a0 %long 0x80400003 // dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3 | |
| data.set 0x013031a4 %long 0x00000000 // dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0 | |
| data.set 0x013031a8 %long 0x80100010 // dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10 | |
| data.set 0x013031b0 %long 0x00000000 // dfi_phyupd_type3:RW:16:12:=0x10 dfi_phyupd_type2:RW:0:12:=0x10 | |
| //config ddr size 1Gbit, row=13,col=9; offset: addrmap0-addrmap8 | |
| data.set 0x01303200 %long 0x00001f12 //addrmap0 // addrmap_cs_bit1:RW:8:5:=0x1f addrmap_cs_bit0:RW:0:5:=0x12 | |
| data.set 0x01303204 %long 0x00060606 //addrmap1 // addrmap_bank_b2:RW:16:4:=0x6 addrmap_bank_b1:RW:8:4:=0x6 addrmap_bank_b0:RW:0:4:=0x6 | |
| data.set 0x01303208 %long 0x00000000 //addrmap2 // addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0 | |
| data.set 0x0130320c %long 0x0f0f0000 //addrmap3 // addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0xf addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0 | |
| data.set 0x01303210 %long 0x00000f0f //addrmap4 // addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf | |
| data.set 0x01303214 %long 0x05050505 //addrmap5 // addrmap_row_b11:RW:24:4:=0x5 addrmap_row_b2_10:RW:16:4:=0x5 addrmap_row_b1:RW:8:4:=0x5 addrmap_row_b0:RW:0:4:=0x5 | |
| data.set 0x01303218 %long 0x0f0f0f05 //addrmap6 // addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x5 | |
| data.set 0x01303240 %long 0x04000400 // wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0 | |
| data.set 0x01303244 %long 0x00000000 // rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0 | |
| data.set 0x01303250 %long 0x00001005 // rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x10 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1 | |
| data.set 0x01303300 %long 0x00000000 // dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0 | |
| data.set 0x01303304 %long 0x00000000 // dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0 | |
| data.set 0x01303400 %long 0x00000000 // pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0 | |
| //port read static priority bit0-9 | |
| data.set 0x01303404 %long 0x1bff //matrix and ph //VALUE_PCFGR_0,rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff | |
| data.set 0x013034b4 %long 0x5820 //LTE //VALUE_PCFGR_1,rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20 | |
| data.set 0x01303564 %long 0x1800 //ZSP880 //VALUE_PCFGR_2,rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0 | |
| data.set 0x01303614 %long 0x1804 //R7 //VALUE_PCFGR_3,rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4 | |
| //port write static priority bit0-9 | |
| data.set 0x01303408 %long 0x13ff //VALUE_PCFGW_0,wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff | |
| data.set 0x013034b8 %long 0x50ff //VALUE_PCFGW_1,wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff | |
| data.set 0x01303568 %long 0x103f //VALUE_PCFGW_2,wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f | |
| data.set 0x01303618 %long 0x105f //VALUE_PCFGW_3,wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f | |
| //port read region set | |
| data.set 0x01303494 %long 0x2100e00 // 0=LPR, 1-14=VPR, 15=HPR //VALUE_PCFGQOS0_0,rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| data.set 0x01303544 %long 0x2100e00 //VALUE_PCFGQOS0_1,rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| data.set 0x013035f4 %long 0x2100e00 //VALUE_PCFGQOS0_2,rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| data.set 0x013036a4 %long 0x2100e00 //VALUE_PCFGQOS0_3,rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0 | |
| //port write region set | |
| data.set 0x0130349c %long 0x100000 //0=NPW, 1-15=VPW //VALUE_PCFGWQOS0_0,wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| data.set 0x0130354c %long 0x100000 //VALUE_PCFGWQOS0_1,wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| data.set 0x013035fc %long 0x100000 //VALUE_PCFGWQOS0_2,wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| data.set 0x013036ac %long 0x100000 //VALUE_PCFGWQOS0_3,wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0 | |
| //vpr timeout, region2 is red queue | |
| data.set 0x01303498 %long 0x200030 //read queue=0x20, blue queue=0x30 //VALUE_PCFGQOS1_0,rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| data.set 0x01303548 %long 0x200030 //VALUE_PCFGQOS1_1,rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| data.set 0x013035f8 %long 0x200030 //VALUE_PCFGQOS1_2,rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| data.set 0x013036a8 %long 0x200030 //VALUE_PCFGQOS1_3,rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0 | |
| //vpw timeout | |
| data.set 0x013034a0 %long 0x40 //write timeout=0x40 //VALUE_PCFGWQOS1_0,wqos_map_timeout:RW:0:11:=0x0 | |
| data.set 0x01303550 %long 0x40 //VALUE_PCFGWQOS1_1,wqos_map_timeout:RW:0:11:=0x0 | |
| data.set 0x01303600 %long 0x40 //VALUE_PCFGWQOS1_2,wqos_map_timeout:RW:0:11:=0x0 | |
| data.set 0x013036b0 %long 0x40 //VALUE_PCFGWQOS1_3,wqos_map_timeout:RW:0:11:=0x0 | |
| //in CAM set | |
| data.set 0x0130325c %long 0x20000004 //HPR in CAM starve time=4 and run length=0x20 // hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1 | |
| data.set 0x01303264 %long 0x07000800 //LPR in CAM starve time=0x800 and run length=7 // lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f | |
| data.set 0x0130326c %long 0x10000060 //NPW in CAM starve time=0x60 and run length=0x10// w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f | |
| data.set 0x01303274 %long 0xf //VPR in CAM timeout range=0xf vpr_timeout_range:RW:0:11:=0x0 | |
| data.set 0x01303278 %long 0xf //VPW in CAM timeout range=0xf vpw_timeout_range:RW:0:11:=0x0 | |
| //port extern static priority | |
| data.set 0x00146064 %long 0xffff0000 //port0,1 LP=0; port2,3 HP=15 | |
| data.set 0x01303490 %long 0x00000001 //VALUE_PCTRL_0, port_en:RW:0:1:=0x1 | |
| data.set 0x01303540 %long 0x00000001 //VALUE_PCTRL_1, port_en:RW:0:1:=0x1 | |
| data.set 0x013035f0 %long 0x00000001 //VALUE_PCTRL_2, port_en:RW:0:1:=0x1 | |
| data.set 0x013036a0 %long 0x00000001 //VALUE_PCTRL_3, port_en:RW:0:1:=0x1 | |
| //wait all register configer done in hardware | |
| Wait 0.01s | |
| //release controller and axi sw reset | |
| data.set 0x01307080 %long 0x000fffc0 | |
| //sw config done | |
| data.set 0x01303320 %long 0x0 | |
| //check phy auto init done, wait 0x01304018 bit0-3 =1 | |
| Wait 0.01s | |
| //notify phy that sdram will inited by controller, wait 0x01304018 bit0=1 | |
| data.set 0x01304004 %long 0x10040001 // PIR | |
| Wait 0.01s | |
| //manual trigger calibrate | |
| data.set 0x01304004 %long 0x21 | |
| data.set 0x01304240 %long 0x04058800 | |
| data.set 0x01304240 %long 0x04058802 | |
| //trigger controller to start sdram init | |
| data.set 0x013031b0 %long 0x1 // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0 | |
| //check sdram init done, wait 0x01303004 bit0-2 !=0 | |
| Wait 0.01s |