/******************************************************************************* | |
* Copyright (C) 2013, ZTE Corporation. | |
* | |
* File Name: drvs_zx297510_regmap.inc | |
* File Mark: | |
* Description: This file contains the register map of zx297510. | |
* Others: | |
* Version: V1.0 | |
* Author: geanfeng | |
* Date: 2013-04-07 | |
* History 1: | |
* | |
*********************************************************************************/ | |
#ifndef _DRVS_ZX297510_REGMAP_H | |
#define _DRVS_ZX297510_REGMAP_H | |
#define ZX297510_A1_SYS 0x00100000 | |
#define ZX297510_A1_CRM 0x00101000 | |
#define ZX297510_A1_UART0 0x00102000 | |
#define ZX297510_A1_UART1 0x00103000 | |
#define ZX297510_A1_SPI0 0x00104000 | |
#define ZX297510_A1_I2C0 0x00106000 | |
#define ZX297510_A1_TIMER0 0x00108000 | |
#define ZX297510_A1_TIMER1 0x00109000 | |
#define ZX297510_A1_RTC 0x0010B000 | |
#define ZX297510_SOC_CRM 0x0010C000 | |
#define ZX297510_TOP_SYS 0x0010D000 | |
#define ZX297510_APB_TIMER 0x00123000 | |
#define ZX297510_APB_WATCHDOG 0x00124000 | |
#define ZX297510_MG_ICU 0x00800000 | |
#define ZX297510_MG_TIMER 0x00801000 | |
#define ZX297510_MG_WATCHDOG 0x00802000 | |
#define ZX297510_MG_CRPM 0x00803000 | |
#define ZX297510_MG_INST_AS_CFG 0x00810000 | |
#define ZX297510_MG_DATA_AS_CFG 0x00811000 | |
#define ZX297510_MG_L2CACHE 0x00C00000 | |
#define ZX297510_DDR_CFG 0x01203000 | |
#define ZX297510_NAND_REG 0x01207000 | |
#define ZX297510_NAND_DATA 0x01208000 | |
#define ZX297510_EDCP 0x01210000 | |
#define ZX297510_CHECKSUM 0x01220000 | |
#define ZX297510_USB0_CFG 0x01240000 | |
#define ZX297510_USB1_CFG 0x01280000 | |
#define ZX297510_A2_DMA_INT_MUX 0x01300000 | |
#define ZX297510_DMA0_CFG 0x01301000 | |
#define ZX297510_DMA1_CFG 0x01302000 | |
#define ZX297510_SOC_SYS 0x01303000 | |
#define ZX297510_USIM 0x01304000 | |
#define ZX297510_SSC 0x01305000 | |
#define ZX297510_MG_LSP_CRPM 0x01400000 | |
#define ZX297510_MG_LSP_I2S0 0x01406000 | |
#define ZX297510_MG_LSP_I2S1 0x01407000 | |
#define ZX297510_MG_LSP_SDMMC0 0x01408000 | |
#define ZX297510_MG_LSP_I2C0 0x01409000 | |
#define ZX297510_MG_LSP_BLG 0x0140C000 | |
#define ZX297510_MG_LSP_TIMER0 0x0140E000 | |
#define ZX297510_MG_LSP_TIMER1 0x0140F000 | |
#define ZX297510_MG_LSP_SDMMC1 0x01415000 | |
#define ZX297510_IRAM1_IRAM3 0x10000000 | |
#define ZX297510_NIC301_GPV 0x10400000 | |
#define ZX297510_DDR_BASE 0x20000000 | |
#define ZX297510_ICP0 0x60000000 | |
#define ZX297510_ICP1 0x60001000 | |
#define ZX297510_ZSP_CFG 0x70000000 | |
#define ZX297510_IRAM0_IRAM2 0x90000000 | |
#define ZX297510_IRAM6 0x90020000 | |
#define ZX297510_TD_MODEM2 0xA0000000 | |
#define ZX297510_LTE_MODEM2 0xA0800000 | |
#define ZX297510_LTE_MODEM1 0xF0000000 | |
#define ZX297510_TD_MODEM1 0xF2000000 | |
#define ZX297510_GSM_MODEM1 0xF4000000 | |
#define ZX297510_GSM_MODEM2 0xF6000000 | |
#endif |