blob: c080be52f4e9381e6838894e40e2dd8abc560d28 [file] [log] [blame]
yuezonghe824eb0c2024-06-27 02:32:26 -07001/*
2 * omap_wdt.c
3 *
4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/fs.h>
35#include <linux/mm.h>
36#include <linux/miscdevice.h>
37#include <linux/watchdog.h>
38#include <linux/reboot.h>
39#include <linux/init.h>
40#include <linux/err.h>
41#include <linux/platform_device.h>
42#include <linux/moduleparam.h>
43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/uaccess.h>
46#include <linux/slab.h>
47#include <linux/pm_runtime.h>
48#include <mach/hardware.h>
49#include <plat/prcm.h>
50
51#include "omap_wdt.h"
52
53static struct platform_device *omap_wdt_dev;
54
55static unsigned timer_margin;
56module_param(timer_margin, uint, 0);
57MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
58
59static unsigned int wdt_trgr_pattern = 0x1234;
60static DEFINE_SPINLOCK(wdt_lock);
61
62struct omap_wdt_dev {
63 void __iomem *base; /* physical */
64 struct device *dev;
65 int omap_wdt_users;
66 struct resource *mem;
67 struct miscdevice omap_wdt_miscdev;
68};
69
70static void omap_wdt_ping(struct omap_wdt_dev *wdev)
71{
72 void __iomem *base = wdev->base;
73
74 /* wait for posted write to complete */
75 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
76 cpu_relax();
77
78 wdt_trgr_pattern = ~wdt_trgr_pattern;
79 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
80
81 /* wait for posted write to complete */
82 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
83 cpu_relax();
84 /* reloaded WCRR from WLDR */
85}
86
87static void omap_wdt_enable(struct omap_wdt_dev *wdev)
88{
89 void __iomem *base = wdev->base;
90
91 /* Sequence to enable the watchdog */
92 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
93 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
94 cpu_relax();
95
96 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
97 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
98 cpu_relax();
99}
100
101static void omap_wdt_disable(struct omap_wdt_dev *wdev)
102{
103 void __iomem *base = wdev->base;
104
105 /* sequence required to disable watchdog */
106 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
107 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
108 cpu_relax();
109
110 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
111 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
112 cpu_relax();
113}
114
115static void omap_wdt_adjust_timeout(unsigned new_timeout)
116{
117 if (new_timeout < TIMER_MARGIN_MIN)
118 new_timeout = TIMER_MARGIN_DEFAULT;
119 if (new_timeout > TIMER_MARGIN_MAX)
120 new_timeout = TIMER_MARGIN_MAX;
121 timer_margin = new_timeout;
122}
123
124static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
125{
126 u32 pre_margin = GET_WLDR_VAL(timer_margin);
127 void __iomem *base = wdev->base;
128
129 pm_runtime_get_sync(wdev->dev);
130
131 /* just count up at 32 KHz */
132 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
133 cpu_relax();
134
135 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
136 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
137 cpu_relax();
138
139 pm_runtime_put_sync(wdev->dev);
140}
141
142/*
143 * Allow only one task to hold it open
144 */
145static int omap_wdt_open(struct inode *inode, struct file *file)
146{
147 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
148 void __iomem *base = wdev->base;
149
150 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
151 return -EBUSY;
152
153 pm_runtime_get_sync(wdev->dev);
154
155 /*
156 * Make sure the watchdog is disabled. This is unfortunately required
157 * because writing to various registers with the watchdog running has no
158 * effect.
159 */
160 omap_wdt_disable(wdev);
161
162 /* initialize prescaler */
163 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
164 cpu_relax();
165
166 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
167 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
168 cpu_relax();
169
170 file->private_data = (void *) wdev;
171
172 omap_wdt_set_timeout(wdev);
173 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
174 omap_wdt_enable(wdev);
175
176 pm_runtime_put_sync(wdev->dev);
177
178 return nonseekable_open(inode, file);
179}
180
181static int omap_wdt_release(struct inode *inode, struct file *file)
182{
183 struct omap_wdt_dev *wdev = file->private_data;
184
185 /*
186 * Shut off the timer unless NOWAYOUT is defined.
187 */
188#ifndef CONFIG_WATCHDOG_NOWAYOUT
189 pm_runtime_get_sync(wdev->dev);
190
191 omap_wdt_disable(wdev);
192
193 pm_runtime_put_sync(wdev->dev);
194#else
195 pr_crit("Unexpected close, not stopping!\n");
196#endif
197 wdev->omap_wdt_users = 0;
198
199 return 0;
200}
201
202static ssize_t omap_wdt_write(struct file *file, const char __user *data,
203 size_t len, loff_t *ppos)
204{
205 struct omap_wdt_dev *wdev = file->private_data;
206
207 /* Refresh LOAD_TIME. */
208 if (len) {
209 pm_runtime_get_sync(wdev->dev);
210 spin_lock(&wdt_lock);
211 omap_wdt_ping(wdev);
212 spin_unlock(&wdt_lock);
213 pm_runtime_put_sync(wdev->dev);
214 }
215 return len;
216}
217
218static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
219 unsigned long arg)
220{
221 struct omap_wdt_dev *wdev;
222 int new_margin;
223 static const struct watchdog_info ident = {
224 .identity = "OMAP Watchdog",
225 .options = WDIOF_SETTIMEOUT,
226 .firmware_version = 0,
227 };
228
229 wdev = file->private_data;
230
231 switch (cmd) {
232 case WDIOC_GETSUPPORT:
233 return copy_to_user((struct watchdog_info __user *)arg, &ident,
234 sizeof(ident));
235 case WDIOC_GETSTATUS:
236 return put_user(0, (int __user *)arg);
237 case WDIOC_GETBOOTSTATUS:
238 if (cpu_is_omap16xx())
239 return put_user(__raw_readw(ARM_SYSST),
240 (int __user *)arg);
241 if (cpu_is_omap24xx())
242 return put_user(omap_prcm_get_reset_sources(),
243 (int __user *)arg);
244 return put_user(0, (int __user *)arg);
245 case WDIOC_KEEPALIVE:
246 pm_runtime_get_sync(wdev->dev);
247 spin_lock(&wdt_lock);
248 omap_wdt_ping(wdev);
249 spin_unlock(&wdt_lock);
250 pm_runtime_put_sync(wdev->dev);
251 return 0;
252 case WDIOC_SETTIMEOUT:
253 if (get_user(new_margin, (int __user *)arg))
254 return -EFAULT;
255 omap_wdt_adjust_timeout(new_margin);
256
257 pm_runtime_get_sync(wdev->dev);
258 spin_lock(&wdt_lock);
259 omap_wdt_disable(wdev);
260 omap_wdt_set_timeout(wdev);
261 omap_wdt_enable(wdev);
262
263 omap_wdt_ping(wdev);
264 spin_unlock(&wdt_lock);
265 pm_runtime_put_sync(wdev->dev);
266 /* Fall */
267 case WDIOC_GETTIMEOUT:
268 return put_user(timer_margin, (int __user *)arg);
269 default:
270 return -ENOTTY;
271 }
272}
273
274static const struct file_operations omap_wdt_fops = {
275 .owner = THIS_MODULE,
276 .write = omap_wdt_write,
277 .unlocked_ioctl = omap_wdt_ioctl,
278 .open = omap_wdt_open,
279 .release = omap_wdt_release,
280 .llseek = no_llseek,
281};
282
283static int __devinit omap_wdt_probe(struct platform_device *pdev)
284{
285 struct resource *res, *mem;
286 struct omap_wdt_dev *wdev;
287 int ret;
288
289 /* reserve static register mappings */
290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
291 if (!res) {
292 ret = -ENOENT;
293 goto err_get_resource;
294 }
295
296 if (omap_wdt_dev) {
297 ret = -EBUSY;
298 goto err_busy;
299 }
300
301 mem = request_mem_region(res->start, resource_size(res), pdev->name);
302 if (!mem) {
303 ret = -EBUSY;
304 goto err_busy;
305 }
306
307 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
308 if (!wdev) {
309 ret = -ENOMEM;
310 goto err_kzalloc;
311 }
312
313 wdev->omap_wdt_users = 0;
314 wdev->mem = mem;
315 wdev->dev = &pdev->dev;
316
317 wdev->base = ioremap(res->start, resource_size(res));
318 if (!wdev->base) {
319 ret = -ENOMEM;
320 goto err_ioremap;
321 }
322
323 platform_set_drvdata(pdev, wdev);
324
325 pm_runtime_enable(wdev->dev);
326 pm_runtime_get_sync(wdev->dev);
327
328 omap_wdt_disable(wdev);
329 omap_wdt_adjust_timeout(timer_margin);
330
331 wdev->omap_wdt_miscdev.parent = &pdev->dev;
332 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
333 wdev->omap_wdt_miscdev.name = "watchdog";
334 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
335
336 ret = misc_register(&(wdev->omap_wdt_miscdev));
337 if (ret)
338 goto err_misc;
339
340 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
341 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
342 timer_margin);
343
344 pm_runtime_put_sync(wdev->dev);
345
346 omap_wdt_dev = pdev;
347
348 return 0;
349
350err_misc:
351 pm_runtime_disable(wdev->dev);
352 platform_set_drvdata(pdev, NULL);
353 iounmap(wdev->base);
354
355err_ioremap:
356 wdev->base = NULL;
357 kfree(wdev);
358
359err_kzalloc:
360 release_mem_region(res->start, resource_size(res));
361
362err_busy:
363err_get_resource:
364
365 return ret;
366}
367
368static void omap_wdt_shutdown(struct platform_device *pdev)
369{
370 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
371
372 if (wdev->omap_wdt_users) {
373 pm_runtime_get_sync(wdev->dev);
374 omap_wdt_disable(wdev);
375 pm_runtime_put_sync(wdev->dev);
376 }
377}
378
379static int __devexit omap_wdt_remove(struct platform_device *pdev)
380{
381 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
382 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383
384 pm_runtime_disable(wdev->dev);
385 if (!res)
386 return -ENOENT;
387
388 misc_deregister(&(wdev->omap_wdt_miscdev));
389 release_mem_region(res->start, resource_size(res));
390 platform_set_drvdata(pdev, NULL);
391
392 iounmap(wdev->base);
393
394 kfree(wdev);
395 omap_wdt_dev = NULL;
396
397 return 0;
398}
399
400#ifdef CONFIG_PM
401
402/* REVISIT ... not clear this is the best way to handle system suspend; and
403 * it's very inappropriate for selective device suspend (e.g. suspending this
404 * through sysfs rather than by stopping the watchdog daemon). Also, this
405 * may not play well enough with NOWAYOUT...
406 */
407
408static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
409{
410 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
411
412 if (wdev->omap_wdt_users) {
413 pm_runtime_get_sync(wdev->dev);
414 omap_wdt_disable(wdev);
415 pm_runtime_put_sync(wdev->dev);
416 }
417
418 return 0;
419}
420
421static int omap_wdt_resume(struct platform_device *pdev)
422{
423 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
424
425 if (wdev->omap_wdt_users) {
426 pm_runtime_get_sync(wdev->dev);
427 omap_wdt_enable(wdev);
428 omap_wdt_ping(wdev);
429 pm_runtime_put_sync(wdev->dev);
430 }
431
432 return 0;
433}
434
435#else
436#define omap_wdt_suspend NULL
437#define omap_wdt_resume NULL
438#endif
439
440static struct platform_driver omap_wdt_driver = {
441 .probe = omap_wdt_probe,
442 .remove = __devexit_p(omap_wdt_remove),
443 .shutdown = omap_wdt_shutdown,
444 .suspend = omap_wdt_suspend,
445 .resume = omap_wdt_resume,
446 .driver = {
447 .owner = THIS_MODULE,
448 .name = "omap_wdt",
449 },
450};
451
452module_platform_driver(omap_wdt_driver);
453
454MODULE_AUTHOR("George G. Davis");
455MODULE_LICENSE("GPL");
456MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
457MODULE_ALIAS("platform:omap_wdt");