yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/kernel/topology.c |
| 3 | * |
| 4 | * Copyright (C) 2011 Linaro Limited. |
| 5 | * Written by: Vincent Guittot |
| 6 | * |
| 7 | * based on arch/sh/kernel/topology.c |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/cpu.h> |
| 15 | #include <linux/cpumask.h> |
| 16 | #include <linux/export.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/percpu.h> |
| 19 | #include <linux/node.h> |
| 20 | #include <linux/nodemask.h> |
| 21 | #include <linux/sched.h> |
| 22 | |
| 23 | #include <asm/cputype.h> |
| 24 | #include <asm/topology.h> |
| 25 | |
| 26 | #define MPIDR_SMP_BITMASK (0x3 << 30) |
| 27 | #define MPIDR_SMP_VALUE (0x2 << 30) |
| 28 | |
| 29 | #define MPIDR_MT_BITMASK (0x1 << 24) |
| 30 | |
| 31 | /* |
| 32 | * These masks reflect the current use of the affinity levels. |
| 33 | * The affinity level can be up to 16 bits according to ARM ARM |
| 34 | */ |
| 35 | |
| 36 | #define MPIDR_LEVEL0_MASK 0x3 |
| 37 | #define MPIDR_LEVEL0_SHIFT 0 |
| 38 | |
| 39 | #define MPIDR_LEVEL1_MASK 0xF |
| 40 | #define MPIDR_LEVEL1_SHIFT 8 |
| 41 | |
| 42 | #define MPIDR_LEVEL2_MASK 0xFF |
| 43 | #define MPIDR_LEVEL2_SHIFT 16 |
| 44 | |
| 45 | struct cputopo_arm cpu_topology[NR_CPUS]; |
| 46 | EXPORT_SYMBOL_GPL(cpu_topology); |
| 47 | |
| 48 | const struct cpumask *cpu_coregroup_mask(int cpu) |
| 49 | { |
| 50 | return &cpu_topology[cpu].core_sibling; |
| 51 | } |
| 52 | |
| 53 | /* |
| 54 | * store_cpu_topology is called at boot when only one cpu is running |
| 55 | * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, |
| 56 | * which prevents simultaneous write access to cpu_topology array |
| 57 | */ |
| 58 | void store_cpu_topology(unsigned int cpuid) |
| 59 | { |
| 60 | struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid]; |
| 61 | unsigned int mpidr; |
| 62 | unsigned int cpu; |
| 63 | |
| 64 | /* If the cpu topology has been already set, just return */ |
| 65 | if (cpuid_topo->core_id != -1) |
| 66 | return; |
| 67 | |
| 68 | mpidr = read_cpuid_mpidr(); |
| 69 | |
| 70 | /* create cpu topology mapping */ |
| 71 | if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { |
| 72 | /* |
| 73 | * This is a multiprocessor system |
| 74 | * multiprocessor format & multiprocessor mode field are set |
| 75 | */ |
| 76 | |
| 77 | if (mpidr & MPIDR_MT_BITMASK) { |
| 78 | /* core performance interdependency */ |
| 79 | cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT) |
| 80 | & MPIDR_LEVEL0_MASK; |
| 81 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT) |
| 82 | & MPIDR_LEVEL1_MASK; |
| 83 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT) |
| 84 | & MPIDR_LEVEL2_MASK; |
| 85 | } else { |
| 86 | /* largely independent cores */ |
| 87 | cpuid_topo->thread_id = -1; |
| 88 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT) |
| 89 | & MPIDR_LEVEL0_MASK; |
| 90 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT) |
| 91 | & MPIDR_LEVEL1_MASK; |
| 92 | } |
| 93 | } else { |
| 94 | /* |
| 95 | * This is an uniprocessor system |
| 96 | * we are in multiprocessor format but uniprocessor system |
| 97 | * or in the old uniprocessor format |
| 98 | */ |
| 99 | cpuid_topo->thread_id = -1; |
| 100 | cpuid_topo->core_id = 0; |
| 101 | cpuid_topo->socket_id = -1; |
| 102 | } |
| 103 | |
| 104 | /* update core and thread sibling masks */ |
| 105 | for_each_possible_cpu(cpu) { |
| 106 | struct cputopo_arm *cpu_topo = &cpu_topology[cpu]; |
| 107 | |
| 108 | if (cpuid_topo->socket_id == cpu_topo->socket_id) { |
| 109 | cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); |
| 110 | if (cpu != cpuid) |
| 111 | cpumask_set_cpu(cpu, |
| 112 | &cpuid_topo->core_sibling); |
| 113 | |
| 114 | if (cpuid_topo->core_id == cpu_topo->core_id) { |
| 115 | cpumask_set_cpu(cpuid, |
| 116 | &cpu_topo->thread_sibling); |
| 117 | if (cpu != cpuid) |
| 118 | cpumask_set_cpu(cpu, |
| 119 | &cpuid_topo->thread_sibling); |
| 120 | } |
| 121 | } |
| 122 | } |
| 123 | smp_wmb(); |
| 124 | |
| 125 | printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", |
| 126 | cpuid, cpu_topology[cpuid].thread_id, |
| 127 | cpu_topology[cpuid].core_id, |
| 128 | cpu_topology[cpuid].socket_id, mpidr); |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * init_cpu_topology is called at boot when only one cpu is running |
| 133 | * which prevent simultaneous write access to cpu_topology array |
| 134 | */ |
| 135 | void init_cpu_topology(void) |
| 136 | { |
| 137 | unsigned int cpu; |
| 138 | |
| 139 | /* init core mask */ |
| 140 | for_each_possible_cpu(cpu) { |
| 141 | struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); |
| 142 | |
| 143 | cpu_topo->thread_id = -1; |
| 144 | cpu_topo->core_id = -1; |
| 145 | cpu_topo->socket_id = -1; |
| 146 | cpumask_clear(&cpu_topo->core_sibling); |
| 147 | cpumask_clear(&cpu_topo->thread_sibling); |
| 148 | } |
| 149 | smp_wmb(); |
| 150 | } |