| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Secondary CPU startup routine source file. |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 8 | * |
| 9 | * Interface functions needed for the SMP. This file is based on arm |
| 10 | * realview smp platform. |
| 11 | * Copyright (c) 2003 ARM Limited. |
| 12 | * |
| 13 | * This program is free software,you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/linkage.h> |
| 19 | #include <linux/init.h> |
| 20 | |
| 21 | __CPUINIT |
| 22 | /* |
| 23 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
| 24 | * code. This routine also provides a holding flag into which |
| 25 | * secondary core is held until we're ready for it to initialise. |
| 26 | * The primary core will update this flag using a hardware |
| 27 | * register AuxCoreBoot0. |
| 28 | */ |
| 29 | ENTRY(omap_secondary_startup) |
| 30 | hold: ldr r12,=0x103 |
| 31 | dsb |
| 32 | smc #0 @ read from AuxCoreBoot0 |
| 33 | mov r0, r0, lsr #9 |
| 34 | mrc p15, 0, r4, c0, c0, 5 |
| 35 | and r4, r4, #0x0f |
| 36 | cmp r0, r4 |
| 37 | bne hold |
| 38 | |
| 39 | /* |
| 40 | * we've been released from the wait loop,secondary_stack |
| 41 | * should now contain the SVC stack for this core |
| 42 | */ |
| 43 | b secondary_startup |
| 44 | ENDPROC(omap_secondary_startup) |
| 45 | |