| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * OMAP44xx Clock Management register bits |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) |
| 8 | * Rajendra Nayak (rnayak@ti.com) |
| 9 | * Benoit Cousson (b-cousson@ti.com) |
| 10 | * |
| 11 | * This file is automatically generated from the OMAP hardware databases. |
| 12 | * We respectfully ask that any modifications to this file be coordinated |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 14 | * authors above to ensure that the autogeneration scripts are kept |
| 15 | * up-to-date with the file contents. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. |
| 20 | */ |
| 21 | |
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 24 | |
| 25 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| 26 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 |
| 27 | #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) |
| 28 | |
| 29 | /* |
| 30 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| 31 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 32 | */ |
| 33 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
| 34 | #define OMAP4430_ABE_STATDEP_MASK (1 << 3) |
| 35 | |
| 36 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 37 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 |
| 38 | #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) |
| 39 | |
| 40 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| 41 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 |
| 42 | #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) |
| 43 | |
| 44 | /* |
| 45 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, |
| 46 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, |
| 47 | * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB |
| 48 | */ |
| 49 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 |
| 50 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
| 51 | |
| 52 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 53 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 |
| 54 | #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) |
| 55 | |
| 56 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| 57 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 |
| 58 | #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) |
| 59 | |
| 60 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 61 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 |
| 62 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) |
| 63 | |
| 64 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 65 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 |
| 66 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) |
| 67 | |
| 68 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 69 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 |
| 70 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) |
| 71 | |
| 72 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 73 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 |
| 74 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) |
| 75 | |
| 76 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 77 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 |
| 78 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) |
| 79 | |
| 80 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 81 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 |
| 82 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) |
| 83 | |
| 84 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 85 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 |
| 86 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) |
| 87 | |
| 88 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 89 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 |
| 90 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) |
| 91 | |
| 92 | /* Used by CM_CAM_CLKSTCTRL */ |
| 93 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 |
| 94 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) |
| 95 | |
| 96 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 97 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 |
| 98 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) |
| 99 | |
| 100 | /* Used by CM_EMU_CLKSTCTRL */ |
| 101 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 |
| 102 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) |
| 103 | |
| 104 | /* Used by CM_L4CFG_CLKSTCTRL */ |
| 105 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 |
| 106 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) |
| 107 | |
| 108 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 109 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 |
| 110 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) |
| 111 | |
| 112 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 113 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 |
| 114 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) |
| 115 | |
| 116 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 117 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 |
| 118 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) |
| 119 | |
| 120 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 121 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 |
| 122 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) |
| 123 | |
| 124 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 125 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 |
| 126 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) |
| 127 | |
| 128 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 129 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 |
| 130 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) |
| 131 | |
| 132 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 133 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 |
| 134 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) |
| 135 | |
| 136 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 137 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 |
| 138 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) |
| 139 | |
| 140 | /* Used by CM_DSS_CLKSTCTRL */ |
| 141 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 |
| 142 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) |
| 143 | |
| 144 | /* Used by CM_DSS_CLKSTCTRL */ |
| 145 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 |
| 146 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) |
| 147 | |
| 148 | /* Used by CM_DUCATI_CLKSTCTRL */ |
| 149 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 |
| 150 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) |
| 151 | |
| 152 | /* Used by CM_EMU_CLKSTCTRL */ |
| 153 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 |
| 154 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) |
| 155 | |
| 156 | /* Used by CM_CAM_CLKSTCTRL */ |
| 157 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 |
| 158 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) |
| 159 | |
| 160 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 161 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 |
| 162 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) |
| 163 | |
| 164 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 165 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 |
| 166 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) |
| 167 | |
| 168 | /* Used by CM_DSS_CLKSTCTRL */ |
| 169 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 |
| 170 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) |
| 171 | |
| 172 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 173 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 |
| 174 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) |
| 175 | |
| 176 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 177 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 |
| 178 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) |
| 179 | |
| 180 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 181 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 |
| 182 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) |
| 183 | |
| 184 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 185 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 |
| 186 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) |
| 187 | |
| 188 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 189 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 |
| 190 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) |
| 191 | |
| 192 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 193 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 |
| 194 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) |
| 195 | |
| 196 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 197 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 |
| 198 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) |
| 199 | |
| 200 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 201 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 |
| 202 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) |
| 203 | |
| 204 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 205 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 |
| 206 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) |
| 207 | |
| 208 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 209 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 |
| 210 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) |
| 211 | |
| 212 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 213 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 |
| 214 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) |
| 215 | |
| 216 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 217 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 |
| 218 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) |
| 219 | |
| 220 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 221 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 |
| 222 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) |
| 223 | |
| 224 | /* Used by CM_CAM_CLKSTCTRL */ |
| 225 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 |
| 226 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) |
| 227 | |
| 228 | /* Used by CM_IVAHD_CLKSTCTRL */ |
| 229 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 |
| 230 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) |
| 231 | |
| 232 | /* Used by CM_D2D_CLKSTCTRL */ |
| 233 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 |
| 234 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) |
| 235 | |
| 236 | /* Used by CM_L3_1_CLKSTCTRL */ |
| 237 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 |
| 238 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) |
| 239 | |
| 240 | /* Used by CM_L3_2_CLKSTCTRL */ |
| 241 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 |
| 242 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) |
| 243 | |
| 244 | /* Used by CM_D2D_CLKSTCTRL */ |
| 245 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 |
| 246 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) |
| 247 | |
| 248 | /* Used by CM_SDMA_CLKSTCTRL */ |
| 249 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 |
| 250 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) |
| 251 | |
| 252 | /* Used by CM_DSS_CLKSTCTRL */ |
| 253 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 |
| 254 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) |
| 255 | |
| 256 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 257 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 |
| 258 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) |
| 259 | |
| 260 | /* Used by CM_GFX_CLKSTCTRL */ |
| 261 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 |
| 262 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) |
| 263 | |
| 264 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 265 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 |
| 266 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) |
| 267 | |
| 268 | /* Used by CM_L3INSTR_CLKSTCTRL */ |
| 269 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 |
| 270 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) |
| 271 | |
| 272 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| 273 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 |
| 274 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) |
| 275 | |
| 276 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 277 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 |
| 278 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) |
| 279 | |
| 280 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 281 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 |
| 282 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) |
| 283 | |
| 284 | /* Used by CM_L4CFG_CLKSTCTRL */ |
| 285 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 |
| 286 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) |
| 287 | |
| 288 | /* Used by CM_D2D_CLKSTCTRL */ |
| 289 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 |
| 290 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) |
| 291 | |
| 292 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 293 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 |
| 294 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) |
| 295 | |
| 296 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 297 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 |
| 298 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) |
| 299 | |
| 300 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| 301 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 |
| 302 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) |
| 303 | |
| 304 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 305 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 |
| 306 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) |
| 307 | |
| 308 | /* Used by CM_MPU_CLKSTCTRL */ |
| 309 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 |
| 310 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) |
| 311 | |
| 312 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 313 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 |
| 314 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) |
| 315 | |
| 316 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 317 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 |
| 318 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) |
| 319 | |
| 320 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 321 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 |
| 322 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) |
| 323 | |
| 324 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 325 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 |
| 326 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) |
| 327 | |
| 328 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 329 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 |
| 330 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) |
| 331 | |
| 332 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 333 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 |
| 334 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) |
| 335 | |
| 336 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 337 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 |
| 338 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) |
| 339 | |
| 340 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 341 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 |
| 342 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) |
| 343 | |
| 344 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 345 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 |
| 346 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) |
| 347 | |
| 348 | /* Used by CM_L4PER_CLKSTCTRL */ |
| 349 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 |
| 350 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) |
| 351 | |
| 352 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| 353 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 |
| 354 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) |
| 355 | |
| 356 | /* Used by CM_GFX_CLKSTCTRL */ |
| 357 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 |
| 358 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) |
| 359 | |
| 360 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 361 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 |
| 362 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) |
| 363 | |
| 364 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 365 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 |
| 366 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) |
| 367 | |
| 368 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 369 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 |
| 370 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) |
| 371 | |
| 372 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 373 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 |
| 374 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) |
| 375 | |
| 376 | /* Used by CM_TESLA_CLKSTCTRL */ |
| 377 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 |
| 378 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) |
| 379 | |
| 380 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 381 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 |
| 382 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) |
| 383 | |
| 384 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 385 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 |
| 386 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) |
| 387 | |
| 388 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 389 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 |
| 390 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) |
| 391 | |
| 392 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 393 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 |
| 394 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) |
| 395 | |
| 396 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 397 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 |
| 398 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) |
| 399 | |
| 400 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 401 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 |
| 402 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) |
| 403 | |
| 404 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 405 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 |
| 406 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) |
| 407 | |
| 408 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 409 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 |
| 410 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) |
| 411 | |
| 412 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 413 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 |
| 414 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) |
| 415 | |
| 416 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 417 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 |
| 418 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) |
| 419 | |
| 420 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 421 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 |
| 422 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) |
| 423 | |
| 424 | /* |
| 425 | * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, |
| 426 | * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
| 427 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, |
| 428 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, |
| 429 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, |
| 430 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, |
| 431 | * CM_WKUP_TIMER1_CLKCTRL |
| 432 | */ |
| 433 | #define OMAP4430_CLKSEL_SHIFT 24 |
| 434 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
| 435 | |
| 436 | /* |
| 437 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, |
| 438 | * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL |
| 439 | */ |
| 440 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
| 441 | #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) |
| 442 | |
| 443 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ |
| 444 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
| 445 | #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) |
| 446 | |
| 447 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ |
| 448 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
| 449 | #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) |
| 450 | |
| 451 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| 452 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
| 453 | #define OMAP4430_CLKSEL_60M_MASK (1 << 24) |
| 454 | |
| 455 | /* Used by CM_MPU_MPU_CLKCTRL */ |
| 456 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 |
| 457 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) |
| 458 | |
| 459 | /* Used by CM1_ABE_AESS_CLKCTRL */ |
| 460 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
| 461 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) |
| 462 | |
| 463 | /* Used by CM_CLKSEL_CORE */ |
| 464 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
| 465 | #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) |
| 466 | |
| 467 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 468 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 |
| 469 | #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) |
| 470 | |
| 471 | /* Used by CM_WKUP_USIM_CLKCTRL */ |
| 472 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
| 473 | #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) |
| 474 | |
| 475 | /* Used by CM_MPU_MPU_CLKCTRL */ |
| 476 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 |
| 477 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) |
| 478 | |
| 479 | /* Used by CM_CAM_FDIF_CLKCTRL */ |
| 480 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
| 481 | #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) |
| 482 | |
| 483 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| 484 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
| 485 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) |
| 486 | |
| 487 | /* |
| 488 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, |
| 489 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| 490 | * CM1_ABE_MCBSP3_CLKCTRL |
| 491 | */ |
| 492 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 |
| 493 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) |
| 494 | |
| 495 | /* Used by CM_CLKSEL_CORE */ |
| 496 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
| 497 | #define OMAP4430_CLKSEL_L3_MASK (1 << 4) |
| 498 | |
| 499 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 500 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 |
| 501 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) |
| 502 | |
| 503 | /* Used by CM_CLKSEL_CORE */ |
| 504 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
| 505 | #define OMAP4430_CLKSEL_L4_MASK (1 << 8) |
| 506 | |
| 507 | /* Used by CM_CLKSEL_ABE */ |
| 508 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
| 509 | #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) |
| 510 | |
| 511 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 512 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
| 513 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) |
| 514 | |
| 515 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 516 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 |
| 517 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
| 518 | |
| 519 | /* Used by CM_GFX_GFX_CLKCTRL */ |
| 520 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 |
| 521 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
| 522 | |
| 523 | /* |
| 524 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, |
| 525 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL |
| 526 | */ |
| 527 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 |
| 528 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
| 529 | |
| 530 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| 531 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 |
| 532 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
| 533 | |
| 534 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 535 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
| 536 | #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) |
| 537 | |
| 538 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 539 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
| 540 | #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) |
| 541 | |
| 542 | /* |
| 543 | * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, |
| 544 | * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, |
| 545 | * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, |
| 546 | * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, |
| 547 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, |
| 548 | * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, |
| 549 | * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL |
| 550 | */ |
| 551 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
| 552 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
| 553 | |
| 554 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| 555 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 |
| 556 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) |
| 557 | |
| 558 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| 559 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 |
| 560 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) |
| 561 | |
| 562 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 563 | #define OMAP4430_CUSTOM_SHIFT 6 |
| 564 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) |
| 565 | |
| 566 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| 567 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 |
| 568 | #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) |
| 569 | |
| 570 | /* Used by CM_MPU_STATICDEP */ |
| 571 | #define OMAP4430_D2D_STATDEP_SHIFT 18 |
| 572 | #define OMAP4430_D2D_STATDEP_MASK (1 << 18) |
| 573 | |
| 574 | /* Used by CM_CLKSEL_DPLL_MPU */ |
| 575 | #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 |
| 576 | #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) |
| 577 | |
| 578 | /* Used by CM_CLKSEL_DPLL_MPU */ |
| 579 | #define OMAP4460_DCC_EN_SHIFT 22 |
| 580 | #define OMAP4460_DCC_EN_MASK (1 << 22) |
| 581 | |
| 582 | /* |
| 583 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, |
| 584 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, |
| 585 | * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, |
| 586 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB |
| 587 | */ |
| 588 | #define OMAP4430_DELTAMSTEP_SHIFT 0 |
| 589 | #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) |
| 590 | |
| 591 | /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ |
| 592 | #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 |
| 593 | #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) |
| 594 | |
| 595 | /* Used by CM_DLL_CTRL */ |
| 596 | #define OMAP4430_DLL_OVERRIDE_SHIFT 0 |
| 597 | #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) |
| 598 | |
| 599 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ |
| 600 | #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 |
| 601 | #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) |
| 602 | |
| 603 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| 604 | #define OMAP4430_DLL_RESET_SHIFT 3 |
| 605 | #define OMAP4430_DLL_RESET_MASK (1 << 3) |
| 606 | |
| 607 | /* |
| 608 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| 609 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| 610 | * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB |
| 611 | */ |
| 612 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
| 613 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) |
| 614 | |
| 615 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| 616 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 |
| 617 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) |
| 618 | |
| 619 | /* Used by CM_CLKSEL_DPLL_CORE */ |
| 620 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 |
| 621 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) |
| 622 | |
| 623 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| 624 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 |
| 625 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
| 626 | |
| 627 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| 628 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 |
| 629 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) |
| 630 | |
| 631 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| 632 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
| 633 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) |
| 634 | |
| 635 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
| 636 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 |
| 637 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
| 638 | |
| 639 | /* |
| 640 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 641 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO |
| 642 | */ |
| 643 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
| 644 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| 645 | |
| 646 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ |
| 647 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 |
| 648 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
| 649 | |
| 650 | /* |
| 651 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 652 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO |
| 653 | */ |
| 654 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 |
| 655 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) |
| 656 | |
| 657 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ |
| 658 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 |
| 659 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) |
| 660 | |
| 661 | /* |
| 662 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 663 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB |
| 664 | */ |
| 665 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 |
| 666 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
| 667 | |
| 668 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| 669 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 |
| 670 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) |
| 671 | |
| 672 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| 673 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 |
| 674 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) |
| 675 | |
| 676 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 677 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 |
| 678 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) |
| 679 | |
| 680 | /* |
| 681 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| 682 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| 683 | * CM_CLKSEL_DPLL_UNIPRO |
| 684 | */ |
| 685 | #define OMAP4430_DPLL_DIV_SHIFT 0 |
| 686 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
| 687 | |
| 688 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ |
| 689 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 |
| 690 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
| 691 | |
| 692 | /* |
| 693 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 694 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| 695 | */ |
| 696 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 |
| 697 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
| 698 | |
| 699 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ |
| 700 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 |
| 701 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) |
| 702 | |
| 703 | /* |
| 704 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 705 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 706 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| 707 | */ |
| 708 | #define OMAP4430_DPLL_EN_SHIFT 0 |
| 709 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
| 710 | |
| 711 | /* |
| 712 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 713 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 714 | * CM_CLKMODE_DPLL_UNIPRO |
| 715 | */ |
| 716 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 |
| 717 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
| 718 | |
| 719 | /* |
| 720 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| 721 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| 722 | * CM_CLKSEL_DPLL_UNIPRO |
| 723 | */ |
| 724 | #define OMAP4430_DPLL_MULT_SHIFT 8 |
| 725 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
| 726 | |
| 727 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ |
| 728 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 |
| 729 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
| 730 | |
| 731 | /* |
| 732 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 733 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 734 | * CM_CLKMODE_DPLL_UNIPRO |
| 735 | */ |
| 736 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 |
| 737 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
| 738 | |
| 739 | /* Used by CM_CLKSEL_DPLL_USB */ |
| 740 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 |
| 741 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
| 742 | |
| 743 | /* |
| 744 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 745 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 746 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| 747 | */ |
| 748 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 |
| 749 | #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) |
| 750 | |
| 751 | /* |
| 752 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 753 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 754 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| 755 | */ |
| 756 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 |
| 757 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) |
| 758 | |
| 759 | /* |
| 760 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| 761 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| 762 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| 763 | */ |
| 764 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 |
| 765 | #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) |
| 766 | |
| 767 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 768 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 |
| 769 | #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) |
| 770 | |
| 771 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
| 772 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
| 773 | #define OMAP4430_DSS_STATDEP_MASK (1 << 8) |
| 774 | |
| 775 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 776 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 |
| 777 | #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) |
| 778 | |
| 779 | /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
| 780 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
| 781 | #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) |
| 782 | |
| 783 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| 784 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 |
| 785 | #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) |
| 786 | |
| 787 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 788 | #define OMAP4430_FUNC_SHIFT 16 |
| 789 | #define OMAP4430_FUNC_MASK (0xfff << 16) |
| 790 | |
| 791 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 792 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 |
| 793 | #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) |
| 794 | |
| 795 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 796 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
| 797 | #define OMAP4430_GFX_STATDEP_MASK (1 << 10) |
| 798 | |
| 799 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 800 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 |
| 801 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) |
| 802 | |
| 803 | /* |
| 804 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| 805 | * CM_DIV_M4_DPLL_PER |
| 806 | */ |
| 807 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
| 808 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
| 809 | |
| 810 | /* |
| 811 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| 812 | * CM_DIV_M4_DPLL_PER |
| 813 | */ |
| 814 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 |
| 815 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) |
| 816 | |
| 817 | /* |
| 818 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| 819 | * CM_DIV_M4_DPLL_PER |
| 820 | */ |
| 821 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 |
| 822 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) |
| 823 | |
| 824 | /* |
| 825 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| 826 | * CM_DIV_M4_DPLL_PER |
| 827 | */ |
| 828 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 |
| 829 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) |
| 830 | |
| 831 | /* |
| 832 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| 833 | * CM_DIV_M5_DPLL_PER |
| 834 | */ |
| 835 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
| 836 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
| 837 | |
| 838 | /* |
| 839 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| 840 | * CM_DIV_M5_DPLL_PER |
| 841 | */ |
| 842 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 |
| 843 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) |
| 844 | |
| 845 | /* |
| 846 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| 847 | * CM_DIV_M5_DPLL_PER |
| 848 | */ |
| 849 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 |
| 850 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) |
| 851 | |
| 852 | /* |
| 853 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| 854 | * CM_DIV_M5_DPLL_PER |
| 855 | */ |
| 856 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 |
| 857 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) |
| 858 | |
| 859 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| 860 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
| 861 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
| 862 | |
| 863 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| 864 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 |
| 865 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) |
| 866 | |
| 867 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| 868 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 |
| 869 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) |
| 870 | |
| 871 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| 872 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 |
| 873 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) |
| 874 | |
| 875 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| 876 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 |
| 877 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
| 878 | |
| 879 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| 880 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 |
| 881 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) |
| 882 | |
| 883 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| 884 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 |
| 885 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) |
| 886 | |
| 887 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| 888 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 |
| 889 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) |
| 890 | |
| 891 | /* |
| 892 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, |
| 893 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| 894 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, |
| 895 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, |
| 896 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, |
| 897 | * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, |
| 898 | * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, |
| 899 | * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, |
| 900 | * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, |
| 901 | * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
| 902 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
| 903 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, |
| 904 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, |
| 905 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, |
| 906 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, |
| 907 | * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, |
| 908 | * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, |
| 909 | * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, |
| 910 | * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 911 | * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, |
| 912 | * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, |
| 913 | * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, |
| 914 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
| 915 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, |
| 916 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, |
| 917 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
| 918 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, |
| 919 | * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, |
| 920 | * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, |
| 921 | * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, |
| 922 | * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, |
| 923 | * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, |
| 924 | * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, |
| 925 | * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, |
| 926 | * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, |
| 927 | * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, |
| 928 | * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, |
| 929 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
| 930 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, |
| 931 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, |
| 932 | * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
| 933 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
| 934 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, |
| 935 | * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, |
| 936 | * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL |
| 937 | */ |
| 938 | #define OMAP4430_IDLEST_SHIFT 16 |
| 939 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
| 940 | |
| 941 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| 942 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 |
| 943 | #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) |
| 944 | |
| 945 | /* |
| 946 | * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, |
| 947 | * CM_TESLA_STATICDEP |
| 948 | */ |
| 949 | #define OMAP4430_ISS_STATDEP_SHIFT 9 |
| 950 | #define OMAP4430_ISS_STATDEP_MASK (1 << 9) |
| 951 | |
| 952 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| 953 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 |
| 954 | #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) |
| 955 | |
| 956 | /* |
| 957 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| 958 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, |
| 959 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 960 | */ |
| 961 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
| 962 | #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) |
| 963 | |
| 964 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 965 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 |
| 966 | #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) |
| 967 | |
| 968 | /* |
| 969 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, |
| 970 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 971 | */ |
| 972 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
| 973 | #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) |
| 974 | |
| 975 | /* |
| 976 | * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, |
| 977 | * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| 978 | */ |
| 979 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 |
| 980 | #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) |
| 981 | |
| 982 | /* |
| 983 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| 984 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| 985 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| 986 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 987 | */ |
| 988 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
| 989 | #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) |
| 990 | |
| 991 | /* |
| 992 | * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, |
| 993 | * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, |
| 994 | * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| 995 | * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP |
| 996 | */ |
| 997 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 |
| 998 | #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) |
| 999 | |
| 1000 | /* |
| 1001 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| 1002 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| 1003 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| 1004 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 1005 | */ |
| 1006 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
| 1007 | #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) |
| 1008 | |
| 1009 | /* Used by CM_L3_1_DYNAMICDEP */ |
| 1010 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 |
| 1011 | #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) |
| 1012 | |
| 1013 | /* |
| 1014 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| 1015 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 1016 | */ |
| 1017 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
| 1018 | #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) |
| 1019 | |
| 1020 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 1021 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 |
| 1022 | #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) |
| 1023 | |
| 1024 | /* |
| 1025 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| 1026 | * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 1027 | */ |
| 1028 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
| 1029 | #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) |
| 1030 | |
| 1031 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 1032 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 |
| 1033 | #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) |
| 1034 | |
| 1035 | /* |
| 1036 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
| 1037 | * CM_SDMA_STATICDEP |
| 1038 | */ |
| 1039 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
| 1040 | #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) |
| 1041 | |
| 1042 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1043 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 |
| 1044 | #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) |
| 1045 | |
| 1046 | /* |
| 1047 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
| 1048 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 1049 | */ |
| 1050 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
| 1051 | #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) |
| 1052 | |
| 1053 | /* |
| 1054 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| 1055 | * CM_MPU_DYNAMICDEP |
| 1056 | */ |
| 1057 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 |
| 1058 | #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) |
| 1059 | |
| 1060 | /* |
| 1061 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| 1062 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| 1063 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| 1064 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| 1065 | */ |
| 1066 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
| 1067 | #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) |
| 1068 | |
| 1069 | /* |
| 1070 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
| 1071 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| 1072 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, |
| 1073 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB |
| 1074 | */ |
| 1075 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 |
| 1076 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) |
| 1077 | |
| 1078 | /* |
| 1079 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
| 1080 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| 1081 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, |
| 1082 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB |
| 1083 | */ |
| 1084 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 |
| 1085 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) |
| 1086 | |
| 1087 | /* |
| 1088 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, |
| 1089 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| 1090 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, |
| 1091 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, |
| 1092 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, |
| 1093 | * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, |
| 1094 | * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, |
| 1095 | * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, |
| 1096 | * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, |
| 1097 | * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
| 1098 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
| 1099 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, |
| 1100 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, |
| 1101 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, |
| 1102 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, |
| 1103 | * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, |
| 1104 | * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, |
| 1105 | * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, |
| 1106 | * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 1107 | * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, |
| 1108 | * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, |
| 1109 | * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, |
| 1110 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
| 1111 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, |
| 1112 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, |
| 1113 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
| 1114 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, |
| 1115 | * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, |
| 1116 | * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, |
| 1117 | * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, |
| 1118 | * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, |
| 1119 | * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, |
| 1120 | * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, |
| 1121 | * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, |
| 1122 | * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, |
| 1123 | * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, |
| 1124 | * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, |
| 1125 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
| 1126 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, |
| 1127 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, |
| 1128 | * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
| 1129 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
| 1130 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, |
| 1131 | * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, |
| 1132 | * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL |
| 1133 | */ |
| 1134 | #define OMAP4430_MODULEMODE_SHIFT 0 |
| 1135 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
| 1136 | |
| 1137 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1138 | #define OMAP4460_MPU_DYNDEP_SHIFT 19 |
| 1139 | #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) |
| 1140 | |
| 1141 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1142 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
| 1143 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) |
| 1144 | |
| 1145 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
| 1146 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
| 1147 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) |
| 1148 | |
| 1149 | /* Used by CM_ALWON_USBPHY_CLKCTRL */ |
| 1150 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 |
| 1151 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) |
| 1152 | |
| 1153 | /* Used by CM_CAM_ISS_CLKCTRL */ |
| 1154 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
| 1155 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) |
| 1156 | |
| 1157 | /* |
| 1158 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, |
| 1159 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, |
| 1160 | * CM_WKUP_GPIO1_CLKCTRL |
| 1161 | */ |
| 1162 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
| 1163 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) |
| 1164 | |
| 1165 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ |
| 1166 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 |
| 1167 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) |
| 1168 | |
| 1169 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1170 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
| 1171 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) |
| 1172 | |
| 1173 | /* Used by CM_WKUP_USIM_CLKCTRL */ |
| 1174 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 |
| 1175 | #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) |
| 1176 | |
| 1177 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1178 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
| 1179 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) |
| 1180 | |
| 1181 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1182 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
| 1183 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) |
| 1184 | |
| 1185 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1186 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
| 1187 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) |
| 1188 | |
| 1189 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1190 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
| 1191 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) |
| 1192 | |
| 1193 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1194 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
| 1195 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) |
| 1196 | |
| 1197 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1198 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
| 1199 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) |
| 1200 | |
| 1201 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1202 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
| 1203 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) |
| 1204 | |
| 1205 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1206 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
| 1207 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) |
| 1208 | |
| 1209 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1210 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
| 1211 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) |
| 1212 | |
| 1213 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1214 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
| 1215 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) |
| 1216 | |
| 1217 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ |
| 1218 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
| 1219 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) |
| 1220 | |
| 1221 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1222 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
| 1223 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) |
| 1224 | |
| 1225 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1226 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
| 1227 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) |
| 1228 | |
| 1229 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1230 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
| 1231 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) |
| 1232 | |
| 1233 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
| 1234 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 |
| 1235 | #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) |
| 1236 | |
| 1237 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1238 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
| 1239 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) |
| 1240 | |
| 1241 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ |
| 1242 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 |
| 1243 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) |
| 1244 | |
| 1245 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| 1246 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
| 1247 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) |
| 1248 | |
| 1249 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| 1250 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
| 1251 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) |
| 1252 | |
| 1253 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| 1254 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
| 1255 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) |
| 1256 | |
| 1257 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1258 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
| 1259 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) |
| 1260 | |
| 1261 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1262 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
| 1263 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) |
| 1264 | |
| 1265 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| 1266 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
| 1267 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) |
| 1268 | |
| 1269 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| 1270 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
| 1271 | #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) |
| 1272 | |
| 1273 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| 1274 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 |
| 1275 | #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) |
| 1276 | |
| 1277 | /* Used by CM_CLKSEL_ABE */ |
| 1278 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
| 1279 | #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) |
| 1280 | |
| 1281 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ |
| 1282 | #define OMAP4430_PERF_CURRENT_SHIFT 0 |
| 1283 | #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) |
| 1284 | |
| 1285 | /* |
| 1286 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, |
| 1287 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, |
| 1288 | * CM_IVA_DVFS_PERF_TESLA |
| 1289 | */ |
| 1290 | #define OMAP4430_PERF_REQ_SHIFT 0 |
| 1291 | #define OMAP4430_PERF_REQ_MASK (0xff << 0) |
| 1292 | |
| 1293 | /* Used by CM_RESTORE_ST */ |
| 1294 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 |
| 1295 | #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) |
| 1296 | |
| 1297 | /* Used by CM_RESTORE_ST */ |
| 1298 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 |
| 1299 | #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) |
| 1300 | |
| 1301 | /* Used by CM_RESTORE_ST */ |
| 1302 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 |
| 1303 | #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) |
| 1304 | |
| 1305 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 1306 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
| 1307 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) |
| 1308 | |
| 1309 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 1310 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
| 1311 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) |
| 1312 | |
| 1313 | /* Used by CM_DYN_DEP_PRESCAL */ |
| 1314 | #define OMAP4430_PRESCAL_SHIFT 0 |
| 1315 | #define OMAP4430_PRESCAL_MASK (0x3f << 0) |
| 1316 | |
| 1317 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 1318 | #define OMAP4430_R_RTL_SHIFT 11 |
| 1319 | #define OMAP4430_R_RTL_MASK (0x1f << 11) |
| 1320 | |
| 1321 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ |
| 1322 | #define OMAP4430_SAR_MODE_SHIFT 4 |
| 1323 | #define OMAP4430_SAR_MODE_MASK (1 << 4) |
| 1324 | |
| 1325 | /* Used by CM_SCALE_FCLK */ |
| 1326 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
| 1327 | #define OMAP4430_SCALE_FCLK_MASK (1 << 0) |
| 1328 | |
| 1329 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 1330 | #define OMAP4430_SCHEME_SHIFT 30 |
| 1331 | #define OMAP4430_SCHEME_MASK (0x3 << 30) |
| 1332 | |
| 1333 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1334 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 |
| 1335 | #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) |
| 1336 | |
| 1337 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 1338 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 |
| 1339 | #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) |
| 1340 | |
| 1341 | /* Used by CM_CLKSEL_ABE */ |
| 1342 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
| 1343 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) |
| 1344 | |
| 1345 | /* |
| 1346 | * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, |
| 1347 | * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, |
| 1348 | * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, |
| 1349 | * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, |
| 1350 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, |
| 1351 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, |
| 1352 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, |
| 1353 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| 1354 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, |
| 1355 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
| 1356 | * CM_TESLA_TESLA_CLKCTRL |
| 1357 | */ |
| 1358 | #define OMAP4430_STBYST_SHIFT 18 |
| 1359 | #define OMAP4430_STBYST_MASK (1 << 18) |
| 1360 | |
| 1361 | /* |
| 1362 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
| 1363 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, |
| 1364 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB |
| 1365 | */ |
| 1366 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 |
| 1367 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
| 1368 | |
| 1369 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| 1370 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 |
| 1371 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) |
| 1372 | |
| 1373 | /* |
| 1374 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 1375 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB |
| 1376 | */ |
| 1377 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 |
| 1378 | #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) |
| 1379 | |
| 1380 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| 1381 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 |
| 1382 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) |
| 1383 | |
| 1384 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
| 1385 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 |
| 1386 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) |
| 1387 | |
| 1388 | /* |
| 1389 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| 1390 | * CM_DIV_M4_DPLL_PER |
| 1391 | */ |
| 1392 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 |
| 1393 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) |
| 1394 | |
| 1395 | /* |
| 1396 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| 1397 | * CM_DIV_M5_DPLL_PER |
| 1398 | */ |
| 1399 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 |
| 1400 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) |
| 1401 | |
| 1402 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| 1403 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 |
| 1404 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) |
| 1405 | |
| 1406 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| 1407 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 |
| 1408 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) |
| 1409 | |
| 1410 | /* |
| 1411 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
| 1412 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, |
| 1413 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB |
| 1414 | */ |
| 1415 | #define OMAP4430_ST_MN_BYPASS_SHIFT 8 |
| 1416 | #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) |
| 1417 | |
| 1418 | /* Used by CM_SYS_CLKSEL */ |
| 1419 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
| 1420 | #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) |
| 1421 | |
| 1422 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1423 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 |
| 1424 | #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) |
| 1425 | |
| 1426 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 1427 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
| 1428 | #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) |
| 1429 | |
| 1430 | /* |
| 1431 | * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, |
| 1432 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| 1433 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| 1434 | */ |
| 1435 | #define OMAP4430_WINDOWSIZE_SHIFT 24 |
| 1436 | #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) |
| 1437 | |
| 1438 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 1439 | #define OMAP4430_X_MAJOR_SHIFT 8 |
| 1440 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) |
| 1441 | |
| 1442 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| 1443 | #define OMAP4430_Y_MINOR_SHIFT 0 |
| 1444 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) |
| 1445 | #endif |