blob: d37df98b5c32588d65450867900e7d87a6f4aec9 [file] [log] [blame]
yuezonghe824eb0c2024-06-27 02:32:26 -07001/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 */
7#include <linux/io.h>
8#include <linux/errno.h>
9#include <linux/clksrc-dbx500-prcmu.h>
10#include <linux/of.h>
11
12#include <asm/smp_twd.h>
13
14#include <plat/mtu.h>
15
16#include <mach/setup.h>
17#include <mach/hardware.h>
18#include <mach/irqs.h>
19
20#ifdef CONFIG_HAVE_ARM_TWD
21static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
22 U5500_TWD_BASE, IRQ_LOCALTIMER);
23static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
24 U8500_TWD_BASE, IRQ_LOCALTIMER);
25
26static void __init ux500_twd_init(void)
27{
28 struct twd_local_timer *twd_local_timer;
29 int err;
30
31 twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
32 &u8500_twd_local_timer;
33
34 if (of_have_populated_dt())
35 twd_local_timer_of_register();
36 else {
37 err = twd_local_timer_register(twd_local_timer);
38 if (err)
39 pr_err("twd_local_timer_register failed %d\n", err);
40 }
41}
42#else
43#define ux500_twd_init() do { } while(0)
44#endif
45
46static void __init ux500_timer_init(void)
47{
48 void __iomem *mtu_timer_base;
49 void __iomem *prcmu_timer_base;
50
51 if (cpu_is_u5500()) {
52 mtu_timer_base = __io_address(U5500_MTU0_BASE);
53 prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
54 } else if (cpu_is_u8500()) {
55 mtu_timer_base = __io_address(U8500_MTU0_BASE);
56 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
57 } else {
58 ux500_unknown_soc();
59 }
60
61 /*
62 * Here we register the timerblocks active in the system.
63 * Localtimers (twd) is started when both cpu is up and running.
64 * MTU register a clocksource, clockevent and sched_clock.
65 * Since the MTU is located in the VAPE power domain
66 * it will be cleared in sleep which makes it unsuitable.
67 * We however need it as a timer tick (clockevent)
68 * during boot to calibrate delay until twd is started.
69 * RTC-RTT have problems as timer tick during boot since it is
70 * depending on delay which is not yet calibrated. RTC-RTT is in the
71 * always-on powerdomain and is used as clockevent instead of twd when
72 * sleeping.
73 * The PRCMU timer 4(3 for DB5500) register a clocksource and
74 * sched_clock with higher rating then MTU since is always-on.
75 *
76 */
77
78 nmdk_timer_init(mtu_timer_base);
79 clksrc_dbx500_prcmu_init(prcmu_timer_base);
80 ux500_twd_init();
81}
82
83static void ux500_timer_reset(void)
84{
85 nmdk_clkevt_reset();
86 nmdk_clksrc_reset();
87}
88
89struct sys_timer ux500_timer = {
90 .init = ux500_timer_init,
91 .resume = ux500_timer_reset,
92};