yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-zx297520v2/mach/clock.h |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | #ifndef CLOCK_H |
| 9 | #define CLOCK_H |
| 10 | |
| 11 | #include <linux/clkdev.h> |
| 12 | #include <mach/iomap.h> |
| 13 | #include <mach/board.h> |
| 14 | |
| 15 | #define name_main_clk_32k "main_clk_32k" |
| 16 | #define name_main_clk_26m "main_clk_26m" |
| 17 | #define name_mpll_clk_12m "mpll_clk_12m" |
| 18 | #define name_mpll_clk_24m "mpll_clk_24m" |
| 19 | #define name_mpll_clk_39m "mpll_clk_39m" |
| 20 | #define name_mpll_clk_52m "mpll_clk_52m" |
| 21 | #define name_mpll_clk_78m "mpll_clk_78m" |
| 22 | #define name_mpll_clk_104m "mpll_clk_104m" |
| 23 | #define name_mpll_clk_124m8 "mpll_clk_124m8" |
| 24 | #define name_mpll_clk_156m "mpll_clk_156m" |
| 25 | #define name_mpll_clk_208m "mpll_clk_208m" |
| 26 | #define name_mpll_clk_312m "mpll_clk_312m" |
| 27 | #define name_mpll_clk_624m "mpll_clk_624m" |
| 28 | #define name_dpll_clk_491m52 "dpll_clk_491m52" |
| 29 | #define name_dpll_clk_122m88 "dpll_clk_122m88" |
| 30 | #define name_dpll_clk_81m92 "dpll_clk_81m92" |
| 31 | #define name_upll_clk_480m "upll_clk_480m" |
| 32 | #define name_upll_clk_96m "upll_clk_96m" |
| 33 | #define name_gpll_clk_25m "gpll_clk_25m" |
| 34 | #define name_gpll_clk_50m "gpll_clk_50m" |
| 35 | #define name_gpll_clk_100m "gpll_clk_100m" |
| 36 | #define name_gpll_clk_178m "gpll_clk_178m" |
| 37 | #define name_gpll_clk_200m "gpll_clk_200m" |
| 38 | |
| 39 | /* |
| 40 | * flags used across common struct clk. these flags should only affect the |
| 41 | * top-level framework. custom flags for dealing with hardware specifics |
| 42 | * belong in struct clk_foo |
| 43 | */ |
| 44 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
| 45 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ |
| 46 | #define CLK_AUTO_ROUND_PARENT BIT(5) /* auto round parent to select rate */ |
| 47 | #define CLK_NO_ODD_DIV BIT(6) /* no div or even div */ |
| 48 | |
| 49 | struct clk; |
| 50 | |
| 51 | /** |
| 52 | * struct clk_hw - handle for traversing from a struct clk to its corresponding |
| 53 | * hardware-specific structure. struct clk_hw should be declared within struct |
| 54 | * clk_foo and then referenced by the struct clk instance that uses struct |
| 55 | * clk_foo's clk_ops |
| 56 | * |
| 57 | * clk: pointer to the struct clk instance that points back to this struct |
| 58 | * clk_hw instance |
| 59 | */ |
| 60 | struct clk_hw |
| 61 | { |
| 62 | struct clk *clk; |
| 63 | }; |
| 64 | |
| 65 | struct clk_ops { |
| 66 | int (*prepare)(struct clk_hw *hw); |
| 67 | void (*unprepare)(struct clk_hw *hw); |
| 68 | |
| 69 | int (*enable)(struct clk_hw *hw); |
| 70 | void (*disable)(struct clk_hw *hw); |
| 71 | int (*is_enabled)(struct clk_hw *hw); |
| 72 | |
| 73 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
| 74 | unsigned long parent_rate); |
| 75 | long (*round_rate)(struct clk_hw *hw, unsigned long, |
| 76 | unsigned long *); |
| 77 | int (*set_rate)(struct clk_hw *hw, unsigned long); |
| 78 | |
| 79 | int (*set_parent)(struct clk_hw *hw, u8 index); |
| 80 | u8 (*get_parent)(struct clk_hw *hw); |
| 81 | void (*init)(struct clk_hw *hw); /*called when register to clk_dev*/ |
| 82 | int (*set_auto_gate)(struct clk_hw *hw, bool enable); |
| 83 | }; |
| 84 | struct clk |
| 85 | { |
| 86 | const char *name; |
| 87 | const struct clk_ops *ops; |
| 88 | struct clk_hw *hw; |
| 89 | struct clk *parent; |
| 90 | char **parent_names; |
| 91 | struct clk **parents; |
| 92 | u8 num_parents; |
| 93 | unsigned long rate; |
| 94 | unsigned long new_rate; |
| 95 | unsigned long flags; |
| 96 | unsigned int enable_count; |
| 97 | struct list_head list; |
| 98 | }; |
| 99 | |
| 100 | #define CLK_ZX29_CONFIG(dev, con, ck) \ |
| 101 | { \ |
| 102 | .dev_id = dev, \ |
| 103 | .con_id = con, \ |
| 104 | .clk = ck, \ |
| 105 | } |
| 106 | |
| 107 | #define NAME_CLK(clk) name_##clk |
| 108 | |
| 109 | #define DEFINE_ZX29_ROOT_CLK(root_clk,clk_rate) \ |
| 110 | static struct clk root_clk = { \ |
| 111 | .name = NAME_CLK(root_clk), \ |
| 112 | .rate = clk_rate, \ |
| 113 | .ops = &root_clk_ops, \ |
| 114 | .flags = CLK_IS_ROOT, \ |
| 115 | } |
| 116 | |
| 117 | struct zx29_hwclk |
| 118 | { |
| 119 | struct clk_hw hw; |
| 120 | struct zx29_reg_conf clk_en_reg; |
| 121 | struct zx29_reg_conf clk_sel_reg; |
| 122 | struct zx29_reg_conf clk_div_reg; |
| 123 | struct zx29_reg_conf clk_gate_reg; |
| 124 | }; |
| 125 | |
| 126 | #define to_zx29_hwclk(_hw) container_of(_hw, struct zx29_hwclk, hw) |
| 127 | |
| 128 | extern struct clk_lookup periph_clocks_lookups[]; |
| 129 | extern unsigned int periph_clocks_lookups_num; |
| 130 | #endif |