| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * ES8312.h -- ES8312 ALSA SoC Audio Codec |
| 3 | * |
| 4 | * Authors: |
| 5 | * |
| 6 | * Based on ES8374.h by David Yang |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _ES8312_H |
| 14 | #define _ES8312_H |
| 15 | |
| 16 | /* |
| 17 | * ES8312_REGISTER NAME_REG_REGISTER ADDRESS |
| 18 | */ |
| 19 | #define ES8312_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/ |
| 20 | |
| 21 | /* |
| 22 | * Clock Scheme Register definition |
| 23 | */ |
| 24 | #define ES8312_CLK_MANAGER_REG01 0x01 /* select clk src for mclk, enable clock for codec */ |
| 25 | #define ES8312_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */ |
| 26 | #define ES8312_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */ |
| 27 | #define ES8312_CLK_MANAGER_REG04 0x04 /* dac osr */ |
| 28 | #define ES8312_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */ |
| 29 | #define ES8312_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */ |
| 30 | #define ES8312_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */ |
| 31 | #define ES8312_CLK_MANAGER_REG08 0x08 /* lrck divider */ |
| 32 | #define ES8312_SDPIN_REG09 0x09 /* dac serial digital port */ |
| 33 | #define ES8312_SDPOUT_REG0A 0x0A /* adc serial digital port */ |
| 34 | #define ES8312_SYSTEM_REG0B 0x0B /* system */ |
| 35 | #define ES8312_SYSTEM_REG0C 0x0C /* system */ |
| 36 | #define ES8312_SYSTEM_REG0D 0x0D /* system, power up/down */ |
| 37 | #define ES8312_SYSTEM_REG0E 0x0E /* system, power up/down */ |
| 38 | #define ES8312_SYSTEM_REG0F 0x0F /* system, low power */ |
| 39 | #define ES8312_SYSTEM_REG10 0x10 /* system */ |
| 40 | #define ES8312_SYSTEM_REG11 0x11 /* system */ |
| 41 | #define ES8312_SYSTEM_REG12 0x12 /* system, Enable DAC */ |
| 42 | #define ES8312_SYSTEM_REG13 0x13 /* system */ |
| 43 | #define ES8312_SYSTEM_REG14 0x14 /* system, select DMIC, select analog pga gain */ |
| 44 | #define ES8312_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */ |
| 45 | #define ES8312_ADC_REG16 0x16 /* ADC */ |
| 46 | #define ES8312_ADC_REG17 0x17 /* ADC, volume */ |
| 47 | #define ES8312_ADC_REG18 0x18 /* ADC, alc enable and winsize */ |
| 48 | #define ES8312_ADC_REG19 0x19 /* ADC, alc maxlevel */ |
| 49 | #define ES8312_ADC_REG1A 0x1A /* ADC, alc automute */ |
| 50 | #define ES8312_ADC_REG1B 0x1B /* ADC, alc automute, adc hpf s1 */ |
| 51 | #define ES8312_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */ |
| 52 | |
| 53 | #define ES8312_ADC_EQ_REG1D 0x1D /* ADC equalizer */ |
| 54 | #define ES8312_ADC_EQ_REG1E 0x1E /* ADC equalizer */ |
| 55 | #define ES8312_ADC_EQ_REG1F 0x1F /* ADC equalizer */ |
| 56 | #define ES8312_ADC_EQ_REG20 0x20 /* ADC equalizer */ |
| 57 | #define ES8312_ADC_EQ_REG21 0x21 /* ADC equalizer */ |
| 58 | #define ES8312_ADC_EQ_REG22 0x22 /* ADC equalizer */ |
| 59 | #define ES8312_ADC_EQ_REG24 0x24 /* ADC equalizer */ |
| 60 | #define ES8312_ADC_EQ_REG25 0x25 /* ADC equalizer */ |
| 61 | #define ES8312_ADC_EQ_REG26 0x26 /* ADC equalizer */ |
| 62 | #define ES8312_ADC_EQ_REG27 0x27 /* ADC equalizer */ |
| 63 | #define ES8312_ADC_EQ_REG28 0x28 /* ADC equalizer */ |
| 64 | #define ES8312_ADC_EQ_REG29 0x29 /* ADC equalizer */ |
| 65 | #define ES8312_ADC_EQ_REG2A 0x2A /* ADC equalizer */ |
| 66 | #define ES8312_ADC_EQ_REG2B 0x2B /* ADC equalizer */ |
| 67 | #define ES8312_ADC_EQ_REG2C 0x2C /* ADC equalizer */ |
| 68 | #define ES8312_ADC_EQ_REG2D 0x2D /* ADC equalizer */ |
| 69 | #define ES8312_ADC_EQ_REG2E 0x2E /* ADC equalizer */ |
| 70 | #define ES8312_ADC_EQ_REG2F 0x2F /* ADC equalizer */ |
| 71 | #define ES8312_ADC_EQ_REG30 0x30 /* ADC equalizer */ |
| 72 | |
| 73 | #define ES8312_DAC_REG31 0x31 /* DAC, mute */ |
| 74 | #define ES8312_DAC_REG32 0x32 /* DAC, volume */ |
| 75 | #define ES8312_DAC_REG33 0x33 /* DAC, offset */ |
| 76 | #define ES8312_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */ |
| 77 | #define ES8312_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */ |
| 78 | |
| 79 | #define ES8312_DAC_REG37 0x37 /* DAC, ramprate */ |
| 80 | #define ES8312_DAC_EQ_REG38 0x38 /* DAC equalizer */ |
| 81 | #define ES8312_DAC_EQ_REG39 0x39 /* DAC equalizer */ |
| 82 | #define ES8312_DAC_EQ_REG40 0x40 /* DAC equalizer */ |
| 83 | #define ES8312_DAC_EQ_REG41 0x41 /* DAC equalizer */ |
| 84 | #define ES8312_DAC_EQ_REG42 0x42 /* DAC equalizer */ |
| 85 | #define ES8312_DAC_EQ_REG43 0x43 /* DAC equalizer */ |
| 86 | |
| 87 | #define ES8312_GPIO_REG44 0x44 /* GPIO, dac2adc for test */ |
| 88 | #define ES8312_GP_REG45 0x45 /* GP CONTROL */ |
| 89 | |
| 90 | #define ES8312_I2C_REGFA 0xFA /* DAC offset */ |
| 91 | #define ES8312_FLAG_REGFC 0xFC /* CHIP state machine, adc automute flag */ |
| 92 | #define ES8312_CHD1_REGFD 0xFD /* CHIP ID1 */ |
| 93 | #define ES8312_CHD2_REGFE 0xFE /* CHIP ID2 */ |
| 94 | #define ES8312_CHVER_REGFF 0xFF /* VERSION */ |
| 95 | |
| 96 | #define ES8312_MAX_REGISTER 0xFF |
| 97 | |
| 98 | |
| 99 | |
| 100 | #define ES8312_CLKID_MCLK 0 |
| 101 | #define ES8312_CLKID_BCLK 1 |
| 102 | #endif |