| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /******************************************************************************* |
| 2 | * Copyright (C) 2016, ZXIC Corporation. |
| 3 | * |
| 4 | * File Name: |
| 5 | * File Mark: |
| 6 | * Description: |
| 7 | * Others: |
| 8 | * Version: v1.0 |
| 9 | * Author: zhouqi |
| 10 | * Date: 2013-4-2 |
| 11 | * History 1: |
| 12 | * Date: |
| 13 | * Version: |
| 14 | * Author: |
| 15 | * Modification: |
| 16 | * History 2: |
| 17 | ********************************************************************************/ |
| 18 | #ifndef __CPU_H__ |
| 19 | #define __CPU_H__ |
| 20 | #include <config.h> |
| 21 | |
| 22 | |
| 23 | #define SYS_BOOTSEL_BASE 0x0013b004 |
| 24 | |
| 25 | #define SYS_IRAM0_BASE 0x82000000 /* 120k */ |
| 26 | #define SYS_IRAM1_BASE 0x100000 /* 64k *//* for A9 start */ |
| 27 | #define SYS_IRAM2_BASE 0x80000 /* 64k */ |
| 28 | |
| 29 | #define CPU_A9_SUBSYS_CFG 0x013B138 /* for A9 reset */ |
| 30 | #define CPU_UFI_SW_RSTEN 0xf |
| 31 | |
| 32 | #define CORE_OUTPUT_SWITCH_CONFIG_REG (0x0013a000 + 0x0AC) |
| 33 | #define CORE_OUTPUT_SW_CONFIG_REG1 (0x0013a000 + 0x0B8) |
| 34 | #define CORE_OUTPUT_SW_CONFIG_REG2 (0x0013a000 + 0x0BC) |
| 35 | |
| 36 | #define USB_RESET (0x0013B080) |
| 37 | |
| 38 | extern void timer_init(void); |
| 39 | |
| 40 | |
| 41 | #endif /*__CPU_H__*/ |