| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /******************************************************************************* |
| 2 | * Copyright (C) 2016, ZXIC Corporation. |
| 3 | * |
| 4 | * File Name: |
| 5 | * File Mark: |
| 6 | * Description: |
| 7 | * Others: |
| 8 | * Version: v1.0 |
| 9 | * Author: zhouqi |
| 10 | * Date: 2013-4-2 |
| 11 | * History 1: |
| 12 | * Date: |
| 13 | * Version: |
| 14 | * Author: |
| 15 | * Modification: |
| 16 | * History 2: |
| 17 | ********************************************************************************/ |
| 18 | #ifndef __UART_7520_H__ |
| 19 | #define __UART_7520_H__ |
| 20 | #include "common.h" |
| 21 | |
| 22 | |
| 23 | /******************************************************************************** |
| 24 | * UART |
| 25 | *******************************************************************************/ |
| 26 | #define UART0_BASE 0X131000 |
| 27 | #define UART1_BASE 0x1408000 |
| 28 | #define UART2_BASE 0x140d000 |
| 29 | #define PAD_TOP_FUNC_BASE 0x13c000 |
| 30 | #define PAD_PD_FUNC_BASE 0x1303000 |
| 31 | |
| 32 | #define UART_BASE UART1_BASE |
| 33 | |
| 34 | #define UART_VS (UART_BASE + 0x00) |
| 35 | #define UART_DR (UART_BASE + 0x04) |
| 36 | #define UART_TSC (UART_BASE + 0x08) |
| 37 | #define UART_RSR (UART_BASE + 0x10) |
| 38 | #define UART_FR (UART_BASE + 0x14) |
| 39 | #define UART_TXFF (0x1 << 5) |
| 40 | #define UART_RXFE (0x1 << 4) |
| 41 | #define UART_FR_TXBUSY (1<<8) |
| 42 | |
| 43 | #define UART_ILPR (UART_BASE + 0x20) |
| 44 | #define UART_IBRD (UART_BASE + 0x24) |
| 45 | #define UART_FBRD (UART_BASE + 0x28) |
| 46 | #define UART_LCR_H (UART_BASE + 0x30) |
| 47 | #define UART_SPS (0x1 << 7) // Stick Parity select |
| 48 | #define UART_WLEN_8 (0x3 << 5) // Word length: 8 bits |
| 49 | #define UART_FEN (0x1 << 4) // Enable FIFOs |
| 50 | #define UART_STP2 (0x1 << 3) // Number of stop bits,"1": 2stop bits transmitted |
| 51 | #define UART_EPS (0x1 << 2) // Even parity select |
| 52 | #define UART_PEN (0x1 << 1) // Parity enable |
| 53 | #define UART_BREAK (0x1 << 0) // Send break |
| 54 | #define UART_CR (UART_BASE + 0x34) |
| 55 | #define UART_CTSE (0x1 << 15) // CTS hardware flow control enable |
| 56 | #define UART_RTSE (0x1 << 14) // RTS hardware flow control enable |
| 57 | #define UART_OUT2 (0x1 << 13) // out2 |
| 58 | #define UART_OUT1 (0x1 << 12) // out1 |
| 59 | #define UART_RTS (0x1 << 11) // request to send |
| 60 | #define UART_DTR (0x1 << 10) // data transmit ready |
| 61 | #define UART_RXE (0x1 << 9) // Receive Enable (RXE)"1" |
| 62 | #define UART_TXE (0x1 << 8) // "1": Transmit Enable (TXE) |
| 63 | #define UART_LBE (0x1 << 7) // "1": Loop Back Enable |
| 64 | #define UART_SIRLP (0x1 << 2) // "1": IrDA SIR Low Power Mode |
| 65 | #define UART_SIR_EN (0x1 << 1) // "0": SIR disable; "1": SIR enable |
| 66 | #define UART_EN (0x1 << 0) // "0": uart disable; "1": uart enable |
| 67 | #define UART_IFLS (UART_BASE + 0x38) |
| 68 | #define UART_IMSC (UART_BASE + 0x40) |
| 69 | #define UART_RIS (UART_BASE + 0x44) |
| 70 | #define UART_MIS (UART_BASE + 0x48) |
| 71 | #define UART_ICR (UART_BASE + 0x4C) |
| 72 | #define UART_DMACR (UART_BASE + 0x50) |
| 73 | |
| 74 | #define UART_INT_MASK (0xFFFFFFFF) |
| 75 | |
| 76 | |
| 77 | extern void uart_init(void); |
| 78 | extern char uart_getc(void); |
| 79 | extern void uart_putc(const char c); |
| 80 | extern void uart_puts(const char *s); |
| 81 | |
| 82 | |
| 83 | #endif /*__UART_7520_H__*/ |
| 84 | |