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192.168.1.100 / R306 / 824eb0c6ade808c4501e62fbcf0025f4e694cd11 / . / cp / ps / driver / inc / misc / drvs_nand_ids.h
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yuezonghe824eb0c2024-06-27 02:32:26 -0700[diff] [blame^]1/***********************************************************************
2* Copyright (C) 2001, ZTE Corporation.
3*
4* File Name: drvs_nand.h
5* File Mark:
6* Description: tu hal interface declaration.
7* Others:
8* Version: v1.0
9* Author: wangxia
10* Date: 2008-08-28
11*
12* History 1:
13* Date:
14* Version:
15* Author:
16* Modification:
17
18* History 2:
19**********************************************************************/
20
21#ifndef DRV_NAND_IDS_H
22#define DRV_NAND_IDS_H
23
24/*************************************************************************
25 * Include files *
26 *************************************************************************/
27
28
29/*************************************************************************
30 * Macro *
31 *************************************************************************/
32
33
34/**************************************************************************
35 * Types *
36 **************************************************************************/
37#if 1
38/*
39* nand_flash_timing
40*/
41struct nand_flash_timing
42{
43 unsigned char Twhr; /*reg offset 0x100*/ /*spi nand: rd delay*/
44 unsigned char Trr1; /*spi nand: cs setup*/
45 unsigned char Tadl; /*reg offset 0x110*/ /*spi nand: cs hold*/
46 unsigned char Trr2; /*spi nand: cs desel*/
47 unsigned char Trhw; /*reg offset 0x120*/
48 unsigned char Trea; /*reg offset 0x130*/
49 unsigned char Trp; /*reg offset 0x1f0, or Twp*/
50 unsigned char Treh; /*reg offset 0x200, or Tweh*/
51 unsigned char Tcs; /*reg offset 0x220*/
52 unsigned char Trhz; /*reg offset 0x290*/
53};
54
55
56struct nand_ecc
57{
58 unsigned int strength; /*ECC ¾À´íÄÜÁ¦*/
59 unsigned int sector_size; /*ECC ¾À´íµÄÊý¾Ý¿é´óС*/
60};
61
62
63/*nand É豸ÃèÊö½á¹¹Ìå*/
64struct nand_flash_device_para
65{
66 unsigned char manuf_id; /* ³§¼ÒID */
67 unsigned char device_id; /* É豸ID */
68 unsigned char res_id; /* Æ÷¼þID */
69 unsigned char bus_num; /* 0:8λ 1:16λ */
70 unsigned int page_size; /* ÿҳmainÇøÓò´óС */
71 unsigned int oob_size; /* ÿҳspareÇøÓò´óС */
72 unsigned int column_addr_num; /* ÁеØÖ·Ñ°Ö·ÖÜÆÚÊý */
73 unsigned int row_addr_num; /* ÐеØÖ·Ñ°Ö·ÖÜÆÚÊý */
74 unsigned int block_size; /* ÿ¿éµÄ´óС */
75 unsigned int pages_per_block; /* ÿ¿éµÄÒ³Êý */
76 unsigned int block_num; /* ¿éÊý */
77 unsigned int die_num;
78 unsigned int bad_block_markpos; /* »µ¿é±ê־λλÖÃ,´Ó0¿ªÊ¼ */
79 struct nand_flash_timing nand_timeing;
80
81 struct nand_ecc ecc;
82};
83#endif
84
85
86/**
87 * struct nand_flash_dev - NAND Flash Device ID Structure
88 * @name: Identify the device type
89 * @id: device ID code
90 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
91 * If the pagesize is 0, then the real pagesize
92 * and the eraseize are determined from the
93 * extended id bytes in the chip
94 * @erasesize: Size of an erase block in the flash device.
95 * @chipsize: Total chipsize in Mega Bytes
96 * @options: Bitfield to store chip relevant options
97 */
98struct nand_flash_dev {
99 char *name;
100 int id;
101 unsigned long pagesize;
102 unsigned long chipsize;
103 unsigned long erasesize;
104 unsigned long options;
105};
106
107/**
108 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
109 * @name: Manufacturer name
110 * @id: manufacturer ID code of device.
111*/
112struct nand_manufacturers {
113 int id;
114 char * name;
115};
116
117
118
119
120/* Option constants for bizarre disfunctionality and real
121* features
122*/
123/* Chip can not auto increment pages */
124#define NAND_NO_AUTOINCR 0x00000001
125/* Buswitdh is 16 bit */
126#define NAND_BUSWIDTH_16 0x00000002
127/* Device supports partial programming without padding */
128#define NAND_NO_PADDING 0x00000004
129/* Chip has cache program function */
130#define NAND_CACHEPRG 0x00000008
131/* Chip has copy back function */
132#define NAND_COPYBACK 0x00000010
133/* AND Chip which has 4 banks and a confusing page / block
134 * assignment. See Renesas datasheet for further information */
135#define NAND_IS_AND 0x00000020
136/* Chip has a array of 4 pages which can be read without
137 * additional ready /busy waits */
138#define NAND_4PAGE_ARRAY 0x00000040
139/* Chip requires that BBT is periodically rewritten to prevent
140 * bits from adjacent blocks from 'leaking' in altering data.
141 * This happens with the Renesas AG-AND chips, possibly others. */
142#define BBT_AUTO_REFRESH 0x00000080
143/* Chip does not require ready check on read. True
144 * for all large page devices, as they do not support
145 * autoincrement.*/
146#define NAND_NO_READRDY 0x00000100
147/* Chip does not allow subpage writes */
148#define NAND_NO_SUBPAGE_WRITE 0x00000200
149
150/*
151 * NAND Flash Manufacturer ID Codes
152 */
153#define NAND_MFR_TOSHIBA 0x98
154#define NAND_MFR_SAMSUNG 0xec
155#define NAND_MFR_FUJITSU 0x04
156#define NAND_MFR_NATIONAL 0x8f
157#define NAND_MFR_RENESAS 0x07
158#define NAND_MFR_STMICRO 0x20
159#define NAND_MFR_HYNIX 0xad
160#define NAND_MFR_MICRON 0x2c
161#define NAND_MFR_AMD 0x01
162#define NAND_MFR_GIGADEVICE 0xC8
163
164
165#endif /* DRV_NAND_IDS_H */
166