| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame^] | 1 | /*******************************************************************************
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| 2 | * Copyright (C) 2016, ZTE Corporation.
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| 3 | *
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| 4 | * File Name: drvs_pmic_addr.h
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| 5 | * File Mark: register addresses of pmic
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| 6 | * Description:
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| 7 | * Others:
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| 8 | * Version: V1.0
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| 9 | * Author: yuxiang
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| 10 | * Date: 2016-01-27
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| 11 | * History 1:
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| 12 | * Date:
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| 13 | * Version:
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| 14 | * Author:
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| 15 | * Modification:
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| 16 | * History 2:
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| 17 | ********************************************************************************/
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| 18 | #ifndef _DRVS_PMIC_ADDR_H
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| 19 | #define _DRVS_PMIC_ADDR_H
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| 20 |
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| 21 | #if defined(_USE_PMIC_ZX234290)
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| 22 |
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| 23 | /////////////////////////////////////////////////
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| 24 | /*slave address 0x12*/
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| 25 | /////////////////////////////////////////////////
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| 26 | #define ZX234290_I2C_SLAVE_ADDR0 (0x12)
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| 27 |
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| 28 | /* interrupt and mask */
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| 29 | #define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
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| 30 | #define ZX234290_REG_ADDR_INTB 0x01
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| 31 | #define ZX234290_REG_ADDR_INTA_MASK 0x02
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| 32 | #define ZX234290_REG_ADDR_INTB_MASK 0x03
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| 33 |
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| 34 | /* interrupt status */
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| 35 | #define ZX234290_REG_ADDR_STSA 0x04
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| 36 | #define ZX234290_REG_ADDR_STSB 0x05
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| 37 | #define ZX234290_REG_ADDR_STS_STARTUP 0x06
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| 38 |
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| 39 | /* adc & softon select */
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| 40 | #define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
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| 41 |
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| 42 | /* bucks normal voltage and sleep voltage */
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| 43 | #define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
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| 44 | #define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
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| 45 |
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| 46 | /* bucks mode */
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| 47 | #define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
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| 48 | #define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
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| 49 | #define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
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| 50 |
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| 51 | /* ldo normal voltage */
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| 52 | #define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
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| 53 | #define ZX234290_REG_ADDR_LDO34_VOL 0x13
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| 54 | #define ZX234290_REG_ADDR_LDO56_VOL 0x14
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| 55 | #define ZX234290_REG_ADDR_LDO78_VOL 0x15
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| 56 | #define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
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| 57 | #define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
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| 58 |
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| 59 |
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| 60 | #define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
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| 61 |
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| 62 | /* ldo sleep voltage */
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| 63 | #define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
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| 64 | #define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
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| 65 | #define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
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| 66 | #define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
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| 67 | #define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
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| 68 |
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| 69 | /* ldo mode */
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| 70 | #define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
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| 71 | #define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
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| 72 | #define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
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| 73 |
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| 74 | /* ldo enable */
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| 75 | #define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
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| 76 | #define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
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| 77 |
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| 78 | /* adc code */
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| 79 | #define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
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| 80 | #define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
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| 81 | #define ZX234290_REG_ADDR_ADC1_MSB 0x25
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| 82 | #define ZX234290_REG_ADDR_ADC1_LSB 0x26
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| 83 | #define ZX234290_REG_ADDR_ADC2_MSB 0x27
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| 84 | #define ZX234290_REG_ADDR_ADC2_LSB 0x28
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| 85 |
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| 86 | /* rtc */
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| 87 | #define ZX234290_REG_ADDR_RTC_CTRL1 0x30
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| 88 | #define ZX234290_REG_ADDR_RTC_CTRL2 0x31
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| 89 |
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| 90 | /* date and time */
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| 91 | #define ZX234290_REG_ADDR_SECONDS 0x32
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| 92 | #define ZX234290_REG_ADDR_MINUTES 0x33
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| 93 | #define ZX234290_REG_ADDR_HOURS 0x34
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| 94 | #define ZX234290_REG_ADDR_DAY 0x35
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| 95 | #define ZX234290_REG_ADDR_WEEK 0x36
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| 96 | #define ZX234290_REG_ADDR_MONTH 0x37
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| 97 | #define ZX234290_REG_ADDR_YEAR 0x38
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| 98 |
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| 99 | /* alarm */
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| 100 | #define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
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| 101 | #define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
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| 102 | #define ZX234290_REG_ADDR_ALARM_DAY 0x3B
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| 103 | #define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
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| 104 | #define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
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| 105 |
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| 106 | #define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
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| 107 | #define ZX234290_REG_ADDR_TIMER_CNT 0x3F
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| 108 |
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| 109 | /* enable ldo output discharge resistance */
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| 110 | #define ZX234290_REG_ADDR_EN_DISCH1 0x40
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| 111 | #define ZX234290_REG_ADDR_EN_DISCH2 0x41
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| 112 |
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| 113 | /* power key control */
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| 114 | #define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
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| 115 | #define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
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| 116 |
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| 117 | #define ZX234290_REG_ADDR_VERSION 0x44
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| 118 |
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| 119 | /*fault status*/
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| 120 | #define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
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| 121 | #define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
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| 122 |
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| 123 | #define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
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| 124 | #define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
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| 125 |
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| 126 | #define ZX234290_REG_ADDR_USER_RESERVED 0x50
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| 127 |
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| 128 | #define ZX234290_REG_ADDR_GMT_TESTING 0xf1
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| 129 |
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| 130 | #endif
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| 131 |
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| 132 | #endif
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