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192.168.1.100 / R306 / d2d5ce1c3b5150b4e785d55d94aebeebaf7a90dc / . / cp / ps / driver / inc / cfg / drvs_chip_cfg.h
blob: 425e621663dcec4007681e017ca3eb2f0611850a [file] [log] [blame]
yuezonghe824eb0c2024-06-27 02:32:26 -0700[diff] [blame]1/*******************************************************************************
2 * Copyright (C) 2008, ZTE Corporation.
3 *
4 * File Name: drv_chip_cfg.h
5 * File Mark:
6 * Description: This file contains the
7 * Others:
8 * Version: V1.0
9 * Author: zhangdongdong
10 * Date: 2015-07-31
11 * History 1:
12 *
13 *********************************************************************************/
14
15#ifndef _DRV_CHIP_CFG_H
16#define _DRV_CHIP_CFG_H
17
18#include "drvs_bits.h"
19
20
21/****************************************************************************
22* type
23****************************************************************************/
24
25
26/****************************************************************************
27* MACRO
28****************************************************************************/
29
30#define TOP_MAIN_CLK_IN 26000000 /* 26MHz */
31
32/****************************************************************************
33* register map
34****************************************************************************/
35#ifdef _OS_TOS
36
37#include "drvs_regmap.inc"
38
39/*SYS*/
40#define TOP_SYS_REG_BASE ADDR_SOC_SYS
41#define SOC_SYS_REG_BASE ADDR_SOC_SYS
42#define A1_SYS_REG_BASE ADDR_SOC_SYS
43
44/*CRM*/
45#define SOC_CRM_REG_BASE ADDR_STD_CRM
46#define LSP_CRM_REG_BASE ADDR_LSP_CRM
47#define A1_CRM_REG_BASE ADDR_TOP_CRM
48#define PS_CRM_REG_BASE ADDR_MG_CRM
49
50/*PS*/
51#define PS_CFG_REG_BASE ADDR_MG_CFG
52
53#if defined (_CHIP_ZX297520V2)
54/*L2 CACHE*/
55#define L2CACHE_REG_BASE ADDR_MG_L2CACHE
56#endif
57
58/*PCU*/
59#define PCU_REG_BASE ADDR_PCU
60
61/*SCU*/
62#if defined (_CHIP_ZX297520V2)
63#define SCU_REG_BASE ADDR_MG_SCU /*only in 7520v2*/
64#endif
65
66/*GIC*/
67#define GICC_REG_BASE ADDR_MG_GICC
68#define GICD_REG_BASE ADDR_MG_GICD
69#if defined (_CHIP_ZX297520V3)
70#define GICR_REG_BASE ADDR_MG_GICR
71#endif
72
73/*TIMER*/
74#define TIMER0_REG_BASE ADDR_LSP_PS_TIMER0 /*ps tick*/
75#define TIMER1_REG_BASE ADDR_PS_TIMER1 /*psm wake timer*/
76#define TIMER2_REG_BASE ADDR_PS_TIMER2
77#define PSRM_TIMER_REG_BASE ADDR_LSP_PS_RM_TIMER /*uicc timer*/
78#define TIMER3_REG_BASE ADDR_RM_TIMER1 /*psm compensate timer*/
79
80/*WDT*/
81#define EXT_WDT_BASE ADDR_LSP_PS_WDT
82//#define PT_WDT_BASE ADDR_MG_PT_WDT
83
84/*I2C*/
85//#define I2C0_REG_BASE ADDR_APB_I2C0 /*V2¾«¼òµôÁËÒ»¸öI2C*/
86#define I2C1_REG_BASE ADDR_LSP_I2C1
87#define I2C_PMIC_REG_BASE ADDR_I2C_PMIC
88
89/*USB*/
90#define USB0_REG_BASE ADDR_HSIC
91#define USB1_REG_BASE ADDR_USB
92
93/*NAND*/
94#define NAND_REG_BASE ADDR_NAND_REG
95#define NAND_DATA_BASE ADDR_NAND_DATA
96
97/*DMA*/
98#define DMA0_REG_BASE ADDR_DMA_PS
99#define DMA1_REG_BASE ADDR_DMA_PHY
100
101/*SPI*/
102#define SPI0_REG_BASE ADDR_LSP_SSP0
103#define SPI1_REG_BASE ADDR_LSP_SSP1
104
105/*ICP*/
106#define ICP0_REG_BASE ADDR_ICP
107
108/*I2S*/
109#define I2S0_REG_BASE ADDR_LSP_I2S0
110#define I2S1_REG_BASE ADDR_LSP_I2S1
111
112/*SDMMC*/
113#define SDMMC0_REG_BASE ADDR_SD0
114#define SDMMC1_REG_BASE ADDR_SD1
115
116/*USIM*/
117#define USIM0_REG_BASE ADDR_GSM_USIM /*´ýÈ·ÈÏ£¬V2¾«¼òµôÁËÒ»¸öUSIM*/
118
119/*EDCP*/
120#define EDCP0_REG_BASE ADDR_EDCP
121
122/*CHECKSUM*/
123#define CHECKSUM0_REG_BASE 0
124
125/*UART*/
126#define UART0_REG_BASE ADDR_UART0
127#define UART1_REG_BASE ADDR_LSP_UART1
128#define UART2_REG_BASE ADDR_LSP_UART2
129
130/*PAD*/
131#define PAD_CTRL_REG_BASE ADDR_PAD_CTRL_A0
132
133/*GPIO*/
134#define GPIO0_REG_BASE ADDR_GPIO0
135#define GPIO1_REG_BASE ADDR_GPIO1
136
137/*PIN MUX*/
138#define GPIO_PINMUX_REG_BASE ADDR_PIN_MUX
139
140/*GSM_MODEM1*/
141#define GSM_MODEM1 ADDR_GSM_MODEM1
142
143/*GSM_MODEM2*/
144#define GSM_MODEM2 ADDR_GSM_MODEM2
145
146/*DDR*/
147#define DDR_CTRL_BASE ADDR_DDR_CTRL
148#define DDR_PHY_BASE ADDR_DDR_PHY
149#if defined (_CHIP_ZX297520V3)
150#define DDR_FFC_BASE ADDR_DDR_FFC
151#endif
152
153/*IRAM*/
154#define IRAM1_BASE ADDR_IRAM1 /*Ê¡µç½»»¥£¬²»µôµçIRAM*/
155#define IRAM2_BASE ADDR_IRAM2 /*ÔËÐÐM0Èí¼þ´úÂë*/
156
157/*LPM*/
158#define GSM_LPM_BASE ADDR_LPM_GSM
159#define LTE_LPM_BASE ADDR_LPM_LTE
160#define TD_LPM_BASE ADDR_LPM_TD
161#define W_LPM_BASE ADDR_LPM_W
162
163/*EFUSE*/
164#define EFUSE_BASE_ADDR ADDR_EFUSE
165
166#if defined (_CHIP_ZX297520V3)
167/*VOU*/
168#define VOU_CTRL_BASE ADDR_VOU_CFG
169#define VOU_CLK_CTRL_BASE ADDR_STD_CRM
170#endif
171#endif
172
173#ifdef _OS_LINUX
174#include <mach/iomap.h>
175
176/*SYS*/
177#define TOP_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
178#define SOC_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
179#define A1_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
180
181/*CRM*/
182#define SOC_CRM_REG_BASE ((unsigned int)ZX_MATRIX_CRM_BASE)
183#define LSP_CRM_REG_BASE ((unsigned int)ZX_LSP_CRPM_BASE)
184#define A1_CRM_REG_BASE ((unsigned int)ZX_TOP_CRM_BASE)
185#define PS_CRM_REG_BASE ((unsigned int)ZX_AP_PERIPHERAL_BASE)
186
187/*PS*/
188//#define PS_CFG_REG_BASE ZX297520V3_MG_CFG
189
190/*L2 CACHE*/
191//#define L2CACHE_REG_BASE ZX297520V3_MG_L2CACHE
192
193/*PCU*/
194#define PCU_REG_BASE ((unsigned int)ZX_PCU_BASE)
195
196/*GIC*/
197#define GICC_REG_BASE ((unsigned int)ZX_GICC_BASE)
198#define GICD_REG_BASE ((unsigned int)ZX_GIC_BASE)
199#define GICR_REG_BASE ((unsigned int)GIC_REDIST_BASE)
200
201
202/*TIMER*/
203#define TIMER0_REG_BASE ((unsigned int)ZX_PS_TIMER0_BASE) /*ps tick*/
204#define TIMER1_REG_BASE ((unsigned int)ZX_PS_TIMER1_BASE) /*psm wake timer*/
205#define TIMER2_REG_BASE ((unsigned int)ZX_PS_TIMER2_BASE) /*psm compensate timer*/
206#define PSRM_TIMER_REG_BASE ((unsigned int)ZX_PS_RM_TIMER_BASE) /*uicc timer*/
207#define TIMER3_REG_BASE ((unsigned int)ZX_RM_TIMER1_BASE) /*rm timer1*/
208
209/*WDT*/
210#define EXT_WDT_BASE ((unsigned int)ZX_PS_WDT_BASE)
211//#define PT_WDT_BASE ZX297520V3_MG_PT_WDT
212
213/*I2C*/
214//#define I2C0_REG_BASE ZX297520V3_APB_I2C0 /*V2¾«¼òµôÁËÒ»¸öI2C*/
215#define I2C1_REG_BASE ((unsigned int)ZX_I2C1_BASE)
216#define I2C_PMIC_REG_BASE ((unsigned int)ZX_PMIC_I2C_BASE)
217
218/*USB*/
219#define USB0_REG_BASE ((unsigned int)ZX_HSIC_BASE)
220#define USB1_REG_BASE ((unsigned int)ZX_USB_BASE)
221
222/*NAND*/
223#define NAND_REG_BASE ((unsigned int)ZX_NAND_REG_BASE)
224#define NAND_DATA_BASE ((unsigned int)ZX_NAND_DATA_BASE)
225
226/*DMA*/
227#define DMA0_REG_BASE ((unsigned int)ZX_DMA_PS_BASE)
228#define DMA1_REG_BASE ((unsigned int)ZX_DMA_PHY_BASE)
229
230/*SPI*/
231#define SPI0_REG_BASE ((unsigned int)ZX_SSP0_BASE)
232#define SPI1_REG_BASE ((unsigned int)ZX_SSP1_BASE)
233
234/*ICP*/
235#define ICP0_REG_BASE ((unsigned int)ZX_ICP_BASE)
236
237/*I2S*/
238#define I2S0_REG_BASE ((unsigned int)ZX_I2S0_BASE)
239#define I2S1_REG_BASE ((unsigned int)ZX_I2S1_BASE)
240
241/*TDM*/
242#define TDM_REG_BASE ((unsigned int)ZX_TDM_BASE)
243
244/*SDMMC*/
245#define SDMMC0_REG_BASE ((unsigned int)ZX_SD0_BASE)
246#define SDMMC1_REG_BASE ((unsigned int)ZX_SD1_BASE)
247
248/*USIM*/
249//#define USIM0_REG_BASE ZX297520V3_GSM_USIM /*´ýÈ·ÈÏ£¬V2¾«¼òµôÁËÒ»¸öUSIM*/
250#define USIM1_REG_BASE ((unsigned int)ZX_USIM1_BASE)
251
252/*EDCP*/
253#define EDCP0_REG_BASE ((unsigned int)ZX_EDCP_BASE)
254
255/*CHECKSUM*/
256#define CHECKSUM0_REG_BASE 0
257
258/*UART*/
259#define UART0_REG_BASE ((unsigned int)ZX_UART0_BASE)
260#define UART1_REG_BASE ((unsigned int)ZX_UART1_BASE)
261#define UART2_REG_BASE ((unsigned int)ZX_UART2_BASE)
262
263/*PAD*/
264#define PAD_CTRL_REG_BASE ((unsigned int)ZX_PAD_CTRL_BASE)
265
266/*GPIO*/
267#define GPIO0_REG_BASE ((unsigned int)ZX_GPIO0_BASE)
268#define GPIO1_REG_BASE ((unsigned int)ZX_GPIO1_BASE)
269
270/*PIN MUX*/
271#define GPIO_PINMUX_REG_BASE ((unsigned int)ZX_PIN_MUX_BASE)
272
273/*GSM_CFG*/
274#define GSM_CFG_BASE ((unsigned int)ZX_GSM_CFG_BASE)
275
276/*GSM_MODEM1*/
277#define GSM_MODEM1 ((unsigned int)ZX_GSM_MODEM_BASE)
278
279/*GSM_MODEM2*/
280#define GSM_MODEM2 ((unsigned int)(ZX_GSM_MODEM_BASE+0x2000000))
281
282/*DDR*/
283#define DDR_CTRL_BASE ((unsigned int)ZX_DDR_CTRL_BASE)
284#define DDR_PHY_BASE ((unsigned int)ZX_DDR_PHY_BASE)
285#define DDR_FFC_BASE ((unsigned int)ZX_DDR_FFC_BASE)
286/**/
287#define SYS_CTRL_BASE ((unsigned int)ZX_SOC_SYS_BASE)
288
289/*IRAM*/
290#define IRAM1_BASE ((unsigned int)ZX_IRAM1_BASE) /*Ê¡µç½»»¥£¬²»µôµçIRAM*/
291#define IRAM2_BASE_ADDR ((unsigned int)ZX_IRAM2_BASE) /*ÔËÐÐM0Èí¼þ´úÂë*/
292
293/*LPM*/
294#define GSM_LPM_BASE ((unsigned int)ZX_LPM_GSM_BASE)
295#define LTE_LPM_BASE ((unsigned int)ZX_LPM_LTE_BASE)
296#define TD_LPM_BASE ((unsigned int)ZX_LPM_TD_BASE)
297#define W_LPM_BASE ((unsigned int)ZX_LPM_W_BASE)
298
299/*EFUSE*/
300#define EFUSE_BASE_ADDR ((unsigned int)ZX_EFUSE_BASE)
301/*VOU*/
302#define VOU_CTRL_BASE ((unsigned int)ZX_VOU_CFG_BASE)
303#define VOU_CLK_CTRL_BASE ((unsigned int)ZX_MATRIX_CRM_BASE)
304#endif
305
306#endif/*_DRV_CFG_H*/
307