| yuezonghe | 824eb0c | 2024-06-27 02:32:26 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 clock function prototypes and macros |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2010 Nokia Corporation |
| 6 | */ |
| 7 | |
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
| 10 | |
| 11 | /* |
| 12 | * OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is |
| 13 | * set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM |
| 14 | * vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters") |
| 15 | */ |
| 16 | #define OMAP4430_REGM4XEN_MULT 4 |
| 17 | |
| 18 | int omap4xxx_clk_init(void); |
| 19 | |
| 20 | #endif |