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192.168.1.100 / R306 / e9c802e48ec32db8da81b4ddcaec2fee0090fbe0 / . / ap / os / linux / linux-3.4.x / arch / arm / mach-zx297510 / gpio.c
blob: 972413221b4a4ae9c036d79a5d526822cfcebdb7 [file] [log] [blame]
yuezonghe824eb0c2024-06-27 02:32:26 -0700[diff] [blame]1/*
2 * linux/arch/arm/mach-zx297510/gpio.c
3 *
4 * Copyright (C) 2013 ZTE-TSP
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/errno.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/debugfs.h>
17#include <linux/seq_file.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/io.h>
22
23#include <mach/iomap.h>
24#include <mach/gpio.h>
25#include <mach/debug.h>
26
27
28#define AO_GPIO_1V8_IN_VA (ZX29_TOP_VA+0xC00)
29#define AO_GPIO_1V8_OEN_VA (ZX29_TOP_VA+0xC04)
30#define AO_GPIO_1V8_OUT_VA (ZX29_TOP_VA+0xC08)
31
32#define AO_GPIO_1V8_SEL_VA (ZX29_TOP_VA+0x400)
33
34#define ZX29_STB_GPIO_VA (ZX297510_STB_GPIO_BASE - ZX297510_A2APB_BASE + ZX29_A2APB_VA)
35
36#define STB_GPIO_1V8_IN0_VA (ZX29_STB_GPIO_VA+0x800)
37#define STB_GPIO_1V8_IN1_VA (ZX29_STB_GPIO_VA+0x804)
38#define STB_GPIO_1V8_IN2_VA (ZX29_STB_GPIO_VA+0x808)
39#define STB_GPIO_1V8_IN3_VA (ZX29_STB_GPIO_VA+0x80c)
40#define STB_GPIO_1V8_OEN0_VA (ZX29_STB_GPIO_VA+0x810)
41#define STB_GPIO_1V8_OEN1_VA (ZX29_STB_GPIO_VA+0x814)
42#define STB_GPIO_1V8_OEN2_VA (ZX29_STB_GPIO_VA+0x818)
43#define STB_GPIO_1V8_OEN3_VA (ZX29_STB_GPIO_VA+0x81c)
44#define STB_GPIO_1V8_OUT0_VA (ZX29_STB_GPIO_VA+0x820)
45#define STB_GPIO_1V8_OUT1_VA (ZX29_STB_GPIO_VA+0x824)
46#define STB_GPIO_1V8_OUT2_VA (ZX29_STB_GPIO_VA+0x828)
47#define STB_GPIO_1V8_OUT3_VA (ZX29_STB_GPIO_VA+0x82c)
48
49#define STB_GPIO_1V8_SEL_VA (ZX29_TOP_VA+0x1000)
50
51static void ao_gpio_sel(unsigned int pin_num, unsigned int value)
52{
53 unsigned int tmp=0;
54 unsigned int offset=0;
55
56 if(pin_num<=1)
57 offset=0;
58 else{
59 if(pin_num>=6)
60 offset=7;
61 else
62 offset=4;
63 }
64
65 tmp = ioread32(AO_GPIO_1V8_SEL_VA+(pin_num+offset)*4);
66 tmp &= ~0x0f000000;
67 tmp |=(value&0xf)<<24;
68 iowrite32(tmp, AO_GPIO_1V8_SEL_VA+(pin_num+offset)*4);
69}
70static void stb_gpio_sel(unsigned int pin_num, unsigned int value)
71{
72 unsigned int tmp=0;
73 unsigned int offset=0;
74
75 if((pin_num<=55)||((pin_num>=68)&&(pin_num<=95)))
76 offset=25;
77 else
78 if((pin_num>=56)&&(pin_num<=61))
79 offset=19;
80 else
81 if((pin_num>=62)&&(pin_num<=67))
82 offset=31;
83 else
84 if((pin_num>=97)&&(pin_num<=150))
85 offset=26;
86 else
87 ZDRV_ASSERT(0);
88
89 tmp = ioread32(STB_GPIO_1V8_SEL_VA+(pin_num-offset)*4);
90 tmp &= ~0x0f000000;
91 tmp |=(value&0xf)<<24;
92 iowrite32(tmp, STB_GPIO_1V8_SEL_VA+(pin_num-offset)*4);
93}
94
95void zx29_gpio1v8_function_sel(unsigned int pin_num, unsigned int value)
96{
97 if(pin_num<=24)
98 ao_gpio_sel(pin_num,value);
99 else
100 stb_gpio_sel(pin_num,value);
101}
102
103static unsigned int ao_gpio_sel_get(unsigned int pin_num)
104{
105 unsigned int tmp=0;
106 unsigned int offset=0;
107
108 if(pin_num<=1)
109 offset=0;
110 else{
111 if(pin_num>=6)
112 offset=7;
113 else
114 offset=4;
115 }
116
117 tmp = ioread32(AO_GPIO_1V8_SEL_VA+(pin_num+offset)*4);
118 return tmp;
119}
120static unsigned int stb_gpio_sel_get(unsigned int pin_num)
121{
122 unsigned int tmp=0;
123 unsigned int offset=0;
124
125 if((pin_num<=55)||((pin_num>=68)&&(pin_num<=95)))
126 offset=25;
127 else
128 if((pin_num>=56)&&(pin_num<=61))
129 offset=19;
130 else
131 if((pin_num>=62)&&(pin_num<=67))
132 offset=31;
133 else
134 if((pin_num>=97)&&(pin_num<=150))
135 offset=26;
136 else
137 ZDRV_ASSERT(0);
138
139 tmp = ioread32(STB_GPIO_1V8_SEL_VA+(pin_num-offset)*4);
140 return tmp;
141}
142
143unsigned int zx29_gpio1v8_function_sel_get(unsigned int pin_num)
144{
145 unsigned int tmp = 0;
146 if(pin_num<=24)
147 tmp = ao_gpio_sel_get(pin_num);
148 else
149 tmp = stb_gpio_sel_get(pin_num);
150 return tmp;
151}
152EXPORT_SYMBOL(zx29_gpio1v8_function_sel_get);
153
154
155/*
156 *set always on area gpio pull-down and pull-up function
157 */
158static void ao_gpio_pd_pu_set(unsigned int pin_num, unsigned int type, unsigned int value)
159{
160 unsigned int tmp=0;
161 unsigned int offset=0;
162 unsigned int shift=0;
163
164 if(pin_num<=1)
165 offset=0;
166 else{
167 if(pin_num>=6)
168 offset=7;
169 else
170 offset=4;
171 }
172
173 if(type)
174 shift=10;
175 else
176 shift=11;
177
178 tmp = ioread32(AO_GPIO_1V8_SEL_VA+(pin_num+offset)*4);
179 tmp &= ~(0x1<<shift);
180 tmp |=(value&0x1)<<shift;
181 iowrite32(tmp, AO_GPIO_1V8_SEL_VA+(pin_num+offset)*4);
182}
183
184/*
185 *set standby area gpio pull-down and pull-up function
186 */
187static void stb_gpio_pd_pu_set(unsigned int pin_num, unsigned int type, unsigned int value)
188{
189 unsigned int tmp=0;
190 unsigned int offset=0;
191 unsigned int shift=0;
192
193 if((pin_num<=55)||((pin_num>=68)&&(pin_num<=95)))
194 offset=25;
195 else
196 if((pin_num>=56)&&(pin_num<=61))
197 offset=19;
198 else
199 if((pin_num>=62)&&(pin_num<=67))
200 offset=31;
201 else
202 if((pin_num>=97)&&(pin_num<=150))
203 offset=26;
204 else
205 ZDRV_ASSERT(0);
206
207 if(type)
208 shift=10;
209 else
210 shift=11;
211
212 tmp = ioread32(STB_GPIO_1V8_SEL_VA+(pin_num-offset)*4);
213 tmp &= ~(0x1<<shift);
214 tmp |=(value&0x1)<<shift;
215 iowrite32(tmp, STB_GPIO_1V8_SEL_VA+(pin_num-offset)*4);
216}
217
218
219/*
220 * set gpio resistance of pull-up and pull-down status
221 *@ pin_num: gpio pin number
222 *@ type: 0 pull-down 1 pull-up
223 *@ value: register value according to manual, only one bit
224 */
225void zx29_gpio1v8_pd_pu_set(unsigned int pin_num, unsigned int type,unsigned int value)
226{
227 if(pin_num<=24)
228 ao_gpio_pd_pu_set(pin_num,type,value);
229 else
230 stb_gpio_pd_pu_set(pin_num,type,value);
231}
232
233/*
234 * enable pull-down resistance
235 */
236void zx29_gpio1v8_pd_enable(unsigned int pin_num)
237{
238 zx29_gpio1v8_pd_pu_set(pin_num,0,1);
239}
240EXPORT_SYMBOL(zx29_gpio1v8_pd_enable);
241
242/*
243 * disable pull-down resistance
244 */
245void zx29_gpio1v8_pd_disable(unsigned int pin_num)
246{
247 zx29_gpio1v8_pd_pu_set(pin_num,0,0);
248}
249EXPORT_SYMBOL(zx29_gpio1v8_pd_disable);
250
251/*
252 * enable pull-up resistance
253 */
254void zx29_gpio1v8_pu_enable(unsigned int pin_num)
255{
256 zx29_gpio1v8_pd_pu_set(pin_num,1,1);
257}
258EXPORT_SYMBOL(zx29_gpio1v8_pu_enable);
259
260/*
261 * disable pull-up resistance
262 */
263void zx29_gpio1v8_pu_disable(unsigned int pin_num)
264{
265 zx29_gpio1v8_pd_pu_set(pin_num,1,0);
266}
267EXPORT_SYMBOL(zx29_gpio1v8_pu_disable);
268
269
270void zx29_gpio1v8_set_direction(unsigned int pin_num, unsigned int value)
271{
272 unsigned int bit_offset=pin_num%32;
273 unsigned int reg_index=pin_num/32;
274 unsigned int tmp=0;
275 void __iomem * reg_base=NULL;
276
277 if(pin_num<25){
278 reg_base=AO_GPIO_1V8_OEN_VA;
279 bit_offset=pin_num;
280 reg_index=0;
281 }
282 else{
283 if((pin_num<52)&&(pin_num>47)){
284 reg_base=AO_GPIO_1V8_OEN_VA;
285 bit_offset=pin_num-23;
286 reg_index=0;
287 }
288 else{
289 reg_base=STB_GPIO_1V8_OEN0_VA;
290 bit_offset=(pin_num-25)%32;
291 reg_index=(pin_num-25)/32;
292 }
293 }
294
295 tmp = ioread32(reg_base+reg_index*4);
296 /* value 0--output 1--input */
297 if (value)
298 {
299 tmp |= (1<<bit_offset);
300 }
301 else
302 {
303 tmp &= ~(1<<bit_offset);
304 }
305 iowrite32(tmp, reg_base+reg_index*4);
306}
307EXPORT_SYMBOL(zx29_gpio1v8_set_direction);
308
309unsigned int zx29_gpio1v8_get_direction(unsigned int pin_num)
310{
311 unsigned int bit_offset=pin_num%32;
312 unsigned int reg_index=pin_num/32;
313 unsigned int tmp=0;
314 void __iomem * reg_base=NULL;
315
316 if(pin_num<25){
317 reg_base=AO_GPIO_1V8_OEN_VA;
318 bit_offset=pin_num;
319 reg_index=0;
320 }
321 else{
322 if((pin_num<52)&&(pin_num>47)){
323 reg_base=AO_GPIO_1V8_OEN_VA;
324 bit_offset=pin_num-23;
325 reg_index=0;
326 }
327 else{
328 reg_base=STB_GPIO_1V8_OEN0_VA;
329 bit_offset=(pin_num-25)%32;
330 reg_index=(pin_num-25)/32;
331 }
332 }
333
334 tmp = ioread32(reg_base+reg_index*4);
335 /* value 0--output 1--input */
336 return ((tmp>>bit_offset)&0x1);
337}
338
339
340void zx29_gpio1v8_output_data(unsigned int pin_num, unsigned int value)
341{
342 unsigned int bit_offset=0;
343 unsigned int reg_index=0;
344 unsigned int tmp=0;
345 void __iomem * reg_base=NULL;
346
347 if(pin_num<25){
348 reg_base=AO_GPIO_1V8_OUT_VA;
349 bit_offset=pin_num;
350 reg_index=0;
351 }
352 else{
353 if((pin_num<52)&&(pin_num>47)){
354 reg_base=AO_GPIO_1V8_OUT_VA;
355 bit_offset=pin_num-23;
356 reg_index=0;
357 }
358 else{
359 reg_base=STB_GPIO_1V8_OUT0_VA;
360 bit_offset=(pin_num-25)%32;
361 reg_index=(pin_num-25)/32;
362 }
363 }
364
365 tmp = ioread32(reg_base+reg_index*4);
366 if (value)
367 {
368 tmp |= (1<<bit_offset);
369 }
370 else
371 {
372 tmp &= ~(1<<bit_offset);
373 }
374 iowrite32(tmp, reg_base+reg_index*4);
375}
376EXPORT_SYMBOL(zx29_gpio1v8_output_data);
377
378
379unsigned int zx29_gpio1v8_input_data(unsigned int pin_num)
380{
381 unsigned int bit_offset=0;
382 unsigned int reg_index=0;
383 unsigned int tmp=0;
384 void __iomem * reg_base=NULL;
385
386 if(pin_num<25){
387 reg_base=AO_GPIO_1V8_IN_VA;
388 bit_offset=pin_num;
389 reg_index=0;
390 }
391 else{
392 if((pin_num<52)&&(pin_num>47)){
393 reg_base=AO_GPIO_1V8_IN_VA;
394 bit_offset=pin_num-23;
395 reg_index=0;
396 }
397 else{
398 reg_base=STB_GPIO_1V8_IN0_VA;
399 bit_offset=(pin_num-25)%32;
400 reg_index=(pin_num-25)/32;
401 }
402 }
403 tmp = ioread32(reg_base+reg_index*4);
404 tmp >>= bit_offset;
405
406 return (tmp&0x1);
407}
408EXPORT_SYMBOL(zx29_gpio1v8_input_data);
409
410/*
411 * this function is used to config jtag mode
412 * jtag_num: jtag port ID
413 * function: jtag mode
414 */
415void jtag_config(unsigned int jtag_num, unsigned int function)
416{
417 unsigned int tmp = 0;
418
419 if((jtag_num>2) || (function > 7)){
420 printk(KERN_INFO"jtag configuration error!\n");
421 return;
422 }
423
424 if (jtag_num == 0)
425 {
426 /*
427 *Jtag0
428 *0:M0Jtag, 1:function, 2:gpio, 3:psJtag, 4:phyJtag, 5:dspJtag, 6:ufiJtag, 7:gpio
429 */
430 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x68);
431 tmp = (tmp&0xf0ffffff)|(function)<<24;
432 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x68);
433
434 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x6c);
435 tmp = (tmp&0xf0ffffff)|(function)<<24;
436 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x6c);
437
438 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x70);
439 tmp = (tmp&0xf0ffffff)|(function)<<24;
440 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x70);
441
442 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x74);
443 tmp = (tmp&0xf0ffffff)|(function)<<24;
444 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x74);
445
446 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x78);
447 tmp = (tmp&0xf0ffffff)|(function)<<24;
448 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x78);
449
450 tmp = ioread32(AO_GPIO_1V8_SEL_VA+0x7c);
451 tmp = (tmp&0xf0ffffff)|(function)<<24;
452 iowrite32(tmp,AO_GPIO_1V8_SEL_VA+0x7c);
453
454 }
455 else if (jtag_num == 1)
456 {
457 /*
458 *D0/Jtag1
459 *0:gpio, 1:sd0, 2:M0Jtag, 3:psJtag, 4:phyJtag, 5:dspJtag, 6:ufiJtag, 7:testpin
460 */
461 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x7c);
462 tmp = (tmp&0xf0ffffff)|(function)<<24;
463 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x7c);
464
465 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x80);
466 tmp = (tmp&0xf0ffffff)|(function)<<24;
467 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x80);
468
469 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x84);
470 tmp = (tmp&0xf0ffffff)|(function)<<24;
471 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x84);
472
473 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x88);
474 tmp = (tmp&0xf0ffffff)|(function)<<24;
475 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x88);
476
477 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x8c);
478 tmp = (tmp&0xf0ffffff)|(function)<<24;
479 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x8c);
480
481 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x90);
482 tmp = (tmp&0xf0ffffff)|(function)<<24;
483 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x90);
484
485 }
486 else if (jtag_num == 2)
487 {
488 /*
489 *SD1/Jtag2
490 *0:gpio, 1:sd1, 2:m0Jtag, 3:psJtag, 4:phyJtag, 5:dspJtag,6:gpio
491 */
492 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x94);
493 tmp = (tmp&0xf0ffffff)|(function)<<24;
494 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x94);
495
496 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x98);
497 tmp = (tmp&0xf0ffffff)|(function)<<24;
498 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x98);
499
500 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0x9c);
501 tmp = (tmp&0xf0ffffff)|(function)<<24;
502 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0x9c);
503
504 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0xa0);
505 tmp = (tmp&0xf0ffffff)|(function)<<24;
506 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0xa0);
507
508 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0xa4);
509 tmp = (tmp&0xf0ffffff)|(function)<<24;
510 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0xa4);
511
512 tmp = ioread32(STB_GPIO_1V8_SEL_VA+0xa8);
513 tmp = (tmp&0xf0ffffff)|(function)<<24;
514 iowrite32(tmp,STB_GPIO_1V8_SEL_VA+0xa8);
515
516 }
517
518 printk(KERN_INFO"jtag%d config finished, function is %d!\n", jtag_num, function);
519}
520EXPORT_SYMBOL(jtag_config);