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192.168.1.100 / R306 / e9c802e48ec32db8da81b4ddcaec2fee0090fbe0 / . / ap / os / linux / linux-3.4.x / sound / soc / codecs / wm8994.c
blob: c93c573f967a480f8ef6b9768d2f010f267da2c5 [file] [log] [blame]
yuezonghe824eb0c2024-06-27 02:32:26 -0700[diff] [blame]1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/jack.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
94static void wm8958_default_micdet(u16 status, void *data);
95
96static const struct wm8958_micd_rate micdet_rates[] = {
97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
101};
102
103static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
106 { 44100 * 256, true, 7, 10 },
107 { 44100 * 256, false, 7, 10 },
108};
109
110static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111{
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 if (wm8994->jack_cb != wm8958_default_micdet)
119 return;
120
121 idle = !wm8994->jack_mic;
122
123 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
124 if (sysclk & WM8994_SYSCLK_SRC)
125 sysclk = wm8994->aifclk[1];
126 else
127 sysclk = wm8994->aifclk[0];
128
129 if (wm8994->pdata && wm8994->pdata->micd_rates) {
130 rates = wm8994->pdata->micd_rates;
131 num_rates = wm8994->pdata->num_micd_rates;
132 } else if (wm8994->jackdet) {
133 rates = jackdet_rates;
134 num_rates = ARRAY_SIZE(jackdet_rates);
135 } else {
136 rates = micdet_rates;
137 num_rates = ARRAY_SIZE(micdet_rates);
138 }
139
140 best = 0;
141 for (i = 0; i < num_rates; i++) {
142 if (rates[i].idle != idle)
143 continue;
144 if (abs(rates[i].sysclk - sysclk) <
145 abs(rates[best].sysclk - sysclk))
146 best = i;
147 else if (rates[best].idle != idle)
148 best = i;
149 }
150
151 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
152 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
153
154 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
155 WM8958_MICD_BIAS_STARTTIME_MASK |
156 WM8958_MICD_RATE_MASK, val);
157}
158
159static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
160{
161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
162 int rate;
163 int reg1 = 0;
164 int offset;
165
166 if (aif)
167 offset = 4;
168 else
169 offset = 0;
170
171 switch (wm8994->sysclk[aif]) {
172 case WM8994_SYSCLK_MCLK1:
173 rate = wm8994->mclk[0];
174 break;
175
176 case WM8994_SYSCLK_MCLK2:
177 reg1 |= 0x8;
178 rate = wm8994->mclk[1];
179 break;
180
181 case WM8994_SYSCLK_FLL1:
182 reg1 |= 0x10;
183 rate = wm8994->fll[0].out;
184 break;
185
186 case WM8994_SYSCLK_FLL2:
187 reg1 |= 0x18;
188 rate = wm8994->fll[1].out;
189 break;
190
191 default:
192 return -EINVAL;
193 }
194
195 if (rate >= 13500000) {
196 rate /= 2;
197 reg1 |= WM8994_AIF1CLK_DIV;
198
199 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
200 aif + 1, rate);
201 }
202
203 wm8994->aifclk[aif] = rate;
204
205 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
206 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
207 reg1);
208
209 return 0;
210}
211
212static int configure_clock(struct snd_soc_codec *codec)
213{
214 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
215 int change, new;
216
217 /* Bring up the AIF clocks first */
218 configure_aif_clock(codec, 0);
219 configure_aif_clock(codec, 1);
220
221 /* Then switch CLK_SYS over to the higher of them; a change
222 * can only happen as a result of a clocking change which can
223 * only be made outside of DAPM so we can safely redo the
224 * clocking.
225 */
226
227 /* If they're equal it doesn't matter which is used */
228 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
229 wm8958_micd_set_rate(codec);
230 return 0;
231 }
232
233 if (wm8994->aifclk[0] < wm8994->aifclk[1])
234 new = WM8994_SYSCLK_SRC;
235 else
236 new = 0;
237
238 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
239 WM8994_SYSCLK_SRC, new);
240 if (change)
241 snd_soc_dapm_sync(&codec->dapm);
242
243 wm8958_micd_set_rate(codec);
244
245 return 0;
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
252 const char *clk;
253
254 /* Check what we're currently using for CLK_SYS */
255 if (reg & WM8994_SYSCLK_SRC)
256 clk = "AIF2CLK";
257 else
258 clk = "AIF1CLK";
259
260 return strcmp(source->name, clk) == 0;
261}
262
263static const char *sidetone_hpf_text[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
265};
266
267static const struct soc_enum sidetone_hpf =
268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
269
270static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
272};
273
274static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
279
280static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
282
283static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
284static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
285static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
286static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
287static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
288static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
289static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
290
291#define WM8994_DRC_SWITCH(xname, reg, shift) \
292{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
294 .put = wm8994_put_drc_sw, \
295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
296
297static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
303 int mask, ret;
304
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
309 else
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
311
312 ret = snd_soc_read(codec, mc->reg);
313 if (ret < 0)
314 return ret;
315 if (ret & mask)
316 return -EINVAL;
317
318 return snd_soc_put_volsw(kcontrol, ucontrol);
319}
320
321static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
322{
323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
324 struct wm8994_pdata *pdata = wm8994->pdata;
325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341}
342
343/* Icky as hell but saves code duplication */
344static int wm8994_get_drc(const char *name)
345{
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353}
354
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360 struct wm8994_pdata *pdata = wm8994->pdata;
361 int drc = wm8994_get_drc(kcontrol->id.name);
362 int value = ucontrol->value.integer.value[0];
363
364 if (drc < 0)
365 return drc;
366
367 if (value >= pdata->num_drc_cfgs)
368 return -EINVAL;
369
370 wm8994->drc_cfg[drc] = value;
371
372 wm8994_set_drc(codec, drc);
373
374 return 0;
375}
376
377static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
378 struct snd_ctl_elem_value *ucontrol)
379{
380 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
381 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
382 int drc = wm8994_get_drc(kcontrol->id.name);
383
384 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
385
386 return 0;
387}
388
389static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
390{
391 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
392 struct wm8994_pdata *pdata = wm8994->pdata;
393 int base = wm8994_retune_mobile_base[block];
394 int iface, best, best_val, save, i, cfg;
395
396 if (!pdata || !wm8994->num_retune_mobile_texts)
397 return;
398
399 switch (block) {
400 case 0:
401 case 1:
402 iface = 0;
403 break;
404 case 2:
405 iface = 1;
406 break;
407 default:
408 return;
409 }
410
411 /* Find the version of the currently selected configuration
412 * with the nearest sample rate. */
413 cfg = wm8994->retune_mobile_cfg[block];
414 best = 0;
415 best_val = INT_MAX;
416 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
417 if (strcmp(pdata->retune_mobile_cfgs[i].name,
418 wm8994->retune_mobile_texts[cfg]) == 0 &&
419 abs(pdata->retune_mobile_cfgs[i].rate
420 - wm8994->dac_rates[iface]) < best_val) {
421 best = i;
422 best_val = abs(pdata->retune_mobile_cfgs[i].rate
423 - wm8994->dac_rates[iface]);
424 }
425 }
426
427 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
428 block,
429 pdata->retune_mobile_cfgs[best].name,
430 pdata->retune_mobile_cfgs[best].rate,
431 wm8994->dac_rates[iface]);
432
433 /* The EQ will be disabled while reconfiguring it, remember the
434 * current configuration.
435 */
436 save = snd_soc_read(codec, base);
437 save &= WM8994_AIF1DAC1_EQ_ENA;
438
439 for (i = 0; i < WM8994_EQ_REGS; i++)
440 snd_soc_update_bits(codec, base + i, 0xffff,
441 pdata->retune_mobile_cfgs[best].regs[i]);
442
443 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
444}
445
446/* Icky as hell but saves code duplication */
447static int wm8994_get_retune_mobile_block(const char *name)
448{
449 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
450 return 0;
451 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
452 return 1;
453 if (strcmp(name, "AIF2 EQ Mode") == 0)
454 return 2;
455 return -EINVAL;
456}
457
458static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
463 struct wm8994_pdata *pdata = wm8994->pdata;
464 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
465 int value = ucontrol->value.integer.value[0];
466
467 if (block < 0)
468 return block;
469
470 if (value >= pdata->num_retune_mobile_cfgs)
471 return -EINVAL;
472
473 wm8994->retune_mobile_cfg[block] = value;
474
475 wm8994_set_retune_mobile(codec, block);
476
477 return 0;
478}
479
480static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_value *ucontrol)
482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
484 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
485 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
486
487 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
488
489 return 0;
490}
491
492static const char *aif_chan_src_text[] = {
493 "Left", "Right"
494};
495
496static const struct soc_enum aif1adcl_src =
497 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
498
499static const struct soc_enum aif1adcr_src =
500 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
501
502static const struct soc_enum aif2adcl_src =
503 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
504
505static const struct soc_enum aif2adcr_src =
506 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
507
508static const struct soc_enum aif1dacl_src =
509 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
510
511static const struct soc_enum aif1dacr_src =
512 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
513
514static const struct soc_enum aif2dacl_src =
515 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
516
517static const struct soc_enum aif2dacr_src =
518 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
519
520static const char *osr_text[] = {
521 "Low Power", "High Performance",
522};
523
524static const struct soc_enum dac_osr =
525 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
526
527static const struct soc_enum adc_osr =
528 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
529
530static const struct snd_kcontrol_new wm8994_snd_controls[] = {
531SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
532 WM8994_AIF1_ADC1_RIGHT_VOLUME,
533 1, 119, 0, digital_tlv),
534SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
535 WM8994_AIF1_ADC2_RIGHT_VOLUME,
536 1, 119, 0, digital_tlv),
537SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
538 WM8994_AIF2_ADC_RIGHT_VOLUME,
539 1, 119, 0, digital_tlv),
540
541SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
542SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
543SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
544SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
545
546SOC_ENUM("AIF1DACL Source", aif1dacl_src),
547SOC_ENUM("AIF1DACR Source", aif1dacr_src),
548SOC_ENUM("AIF2DACL Source", aif2dacl_src),
549SOC_ENUM("AIF2DACR Source", aif2dacr_src),
550
551SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
552 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
553SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
554 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
555SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
556 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
557
558SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
559SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
560
561SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
562SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
563SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
564
565WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
566WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
567WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
568
569WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
570WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
571WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
572
573WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
574WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
575WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
576
577SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
578 5, 12, 0, st_tlv),
579SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
580 0, 12, 0, st_tlv),
581SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
582 5, 12, 0, st_tlv),
583SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
584 0, 12, 0, st_tlv),
585SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
586SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
587
588SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
589SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
590
591SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
592SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
593
594SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
595SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
596
597SOC_ENUM("ADC OSR", adc_osr),
598SOC_ENUM("DAC OSR", dac_osr),
599
600SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
601 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
602SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
603 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
604
605SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
606 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
608 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
609
610SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
611 6, 1, 1, wm_hubs_spkmix_tlv),
612SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
613 2, 1, 1, wm_hubs_spkmix_tlv),
614
615SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
621 10, 15, 0, wm8994_3d_tlv),
622SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
623 8, 1, 0),
624SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
625 10, 15, 0, wm8994_3d_tlv),
626SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
627 8, 1, 0),
628SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
630SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
631 8, 1, 0),
632};
633
634static const struct snd_kcontrol_new wm8994_eq_controls[] = {
635SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
636 eq_tlv),
637SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
638 eq_tlv),
639SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
640 eq_tlv),
641SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
642 eq_tlv),
643SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
644 eq_tlv),
645
646SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
649 eq_tlv),
650SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
655 eq_tlv),
656
657SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
660 eq_tlv),
661SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
664 eq_tlv),
665SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
666 eq_tlv),
667};
668
669static const char *wm8958_ng_text[] = {
670 "30ms", "125ms", "250ms", "500ms",
671};
672
673static const struct soc_enum wm8958_aif1dac1_ng_hold =
674 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
675 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
676
677static const struct soc_enum wm8958_aif1dac2_ng_hold =
678 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
679 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
680
681static const struct soc_enum wm8958_aif2dac_ng_hold =
682 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
683 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
684
685static const struct snd_kcontrol_new wm8958_snd_controls[] = {
686SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
687
688SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
689 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
690SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
691SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
692 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
693 7, 1, ng_tlv),
694
695SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
697SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
698SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
699 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
700 7, 1, ng_tlv),
701
702SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
703 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
704SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
705SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
706 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
707 7, 1, ng_tlv),
708};
709
710static const struct snd_kcontrol_new wm1811_snd_controls[] = {
711SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
712 mixin_boost_tlv),
713SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
714 mixin_boost_tlv),
715};
716
717/* We run all mode setting through a function to enforce audio mode */
718static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
719{
720 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
721
722 if (!wm8994->jackdet || !wm8994->jack_cb)
723 return;
724
725 if (wm8994->active_refcount)
726 mode = WM1811_JACKDET_MODE_AUDIO;
727
728 if (mode == wm8994->jackdet_mode)
729 return;
730
731 wm8994->jackdet_mode = mode;
732
733 /* Always use audio mode to detect while the system is active */
734 if (mode != WM1811_JACKDET_MODE_NONE)
735 mode = WM1811_JACKDET_MODE_AUDIO;
736
737 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
738 WM1811_JACKDET_MODE_MASK, mode);
739}
740
741static void active_reference(struct snd_soc_codec *codec)
742{
743 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744
745 mutex_lock(&wm8994->accdet_lock);
746
747 wm8994->active_refcount++;
748
749 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
750 wm8994->active_refcount);
751
752 /* If we're using jack detection go into audio mode */
753 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
754
755 mutex_unlock(&wm8994->accdet_lock);
756}
757
758static void active_dereference(struct snd_soc_codec *codec)
759{
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761 u16 mode;
762
763 mutex_lock(&wm8994->accdet_lock);
764
765 wm8994->active_refcount--;
766
767 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
768 wm8994->active_refcount);
769
770 if (wm8994->active_refcount == 0) {
771 /* Go into appropriate detection only mode */
772 if (wm8994->jack_mic || wm8994->mic_detecting)
773 mode = WM1811_JACKDET_MODE_MIC;
774 else
775 mode = WM1811_JACKDET_MODE_JACK;
776
777 wm1811_jackdet_set_mode(codec, mode);
778 }
779
780 mutex_unlock(&wm8994->accdet_lock);
781}
782
783static int clk_sys_event(struct snd_soc_dapm_widget *w,
784 struct snd_kcontrol *kcontrol, int event)
785{
786 struct snd_soc_codec *codec = w->codec;
787
788 switch (event) {
789 case SND_SOC_DAPM_PRE_PMU:
790 return configure_clock(codec);
791
792 case SND_SOC_DAPM_POST_PMD:
793 configure_clock(codec);
794 break;
795 }
796
797 return 0;
798}
799
800static void vmid_reference(struct snd_soc_codec *codec)
801{
802 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
803
804 pm_runtime_get_sync(codec->dev);
805
806 wm8994->vmid_refcount++;
807
808 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
809 wm8994->vmid_refcount);
810
811 if (wm8994->vmid_refcount == 1) {
812 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
813 WM8994_LINEOUT1_DISCH |
814 WM8994_LINEOUT2_DISCH, 0);
815
816 wm_hubs_vmid_ena(codec);
817
818 switch (wm8994->vmid_mode) {
819 default:
820 WARN_ON(0 == "Invalid VMID mode");
821 case WM8994_VMID_NORMAL:
822 /* Startup bias, VMID ramp & buffer */
823 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
824 WM8994_BIAS_SRC |
825 WM8994_VMID_DISCH |
826 WM8994_STARTUP_BIAS_ENA |
827 WM8994_VMID_BUF_ENA |
828 WM8994_VMID_RAMP_MASK,
829 WM8994_BIAS_SRC |
830 WM8994_STARTUP_BIAS_ENA |
831 WM8994_VMID_BUF_ENA |
832 (0x3 << WM8994_VMID_RAMP_SHIFT));
833
834 /* Main bias enable, VMID=2x40k */
835 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
836 WM8994_BIAS_ENA |
837 WM8994_VMID_SEL_MASK,
838 WM8994_BIAS_ENA | 0x2);
839
840 msleep(50);
841
842 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
843 WM8994_VMID_RAMP_MASK |
844 WM8994_BIAS_SRC,
845 0);
846 break;
847
848 case WM8994_VMID_FORCE:
849 /* Startup bias, slow VMID ramp & buffer */
850 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
851 WM8994_BIAS_SRC |
852 WM8994_VMID_DISCH |
853 WM8994_STARTUP_BIAS_ENA |
854 WM8994_VMID_BUF_ENA |
855 WM8994_VMID_RAMP_MASK,
856 WM8994_BIAS_SRC |
857 WM8994_STARTUP_BIAS_ENA |
858 WM8994_VMID_BUF_ENA |
859 (0x2 << WM8994_VMID_RAMP_SHIFT));
860
861 /* Main bias enable, VMID=2x40k */
862 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
863 WM8994_BIAS_ENA |
864 WM8994_VMID_SEL_MASK,
865 WM8994_BIAS_ENA | 0x2);
866
867 msleep(400);
868
869 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
870 WM8994_VMID_RAMP_MASK |
871 WM8994_BIAS_SRC,
872 0);
873 break;
874 }
875 }
876}
877
878static void vmid_dereference(struct snd_soc_codec *codec)
879{
880 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
881
882 wm8994->vmid_refcount--;
883
884 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
885 wm8994->vmid_refcount);
886
887 if (wm8994->vmid_refcount == 0) {
888 if (wm8994->hubs.lineout1_se)
889 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
890 WM8994_LINEOUT1N_ENA |
891 WM8994_LINEOUT1P_ENA,
892 WM8994_LINEOUT1N_ENA |
893 WM8994_LINEOUT1P_ENA);
894
895 if (wm8994->hubs.lineout2_se)
896 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
897 WM8994_LINEOUT2N_ENA |
898 WM8994_LINEOUT2P_ENA,
899 WM8994_LINEOUT2N_ENA |
900 WM8994_LINEOUT2P_ENA);
901
902 /* Start discharging VMID */
903 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
904 WM8994_BIAS_SRC |
905 WM8994_VMID_DISCH,
906 WM8994_BIAS_SRC |
907 WM8994_VMID_DISCH);
908
909 switch (wm8994->vmid_mode) {
910 case WM8994_VMID_FORCE:
911 msleep(350);
912 break;
913 default:
914 break;
915 }
916
917 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
918 WM8994_VROI, WM8994_VROI);
919
920 /* Active discharge */
921 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
922 WM8994_LINEOUT1_DISCH |
923 WM8994_LINEOUT2_DISCH,
924 WM8994_LINEOUT1_DISCH |
925 WM8994_LINEOUT2_DISCH);
926
927 msleep(150);
928
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT1N_ENA |
931 WM8994_LINEOUT1P_ENA |
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA, 0);
934
935 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
936 WM8994_VROI, 0);
937
938 /* Switch off startup biases */
939 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
940 WM8994_BIAS_SRC |
941 WM8994_STARTUP_BIAS_ENA |
942 WM8994_VMID_BUF_ENA |
943 WM8994_VMID_RAMP_MASK, 0);
944
945 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
946 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
947
948 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
949 WM8994_VMID_RAMP_MASK, 0);
950 }
951
952 pm_runtime_put(codec->dev);
953}
954
955static int vmid_event(struct snd_soc_dapm_widget *w,
956 struct snd_kcontrol *kcontrol, int event)
957{
958 struct snd_soc_codec *codec = w->codec;
959
960 switch (event) {
961 case SND_SOC_DAPM_PRE_PMU:
962 vmid_reference(codec);
963 break;
964
965 case SND_SOC_DAPM_POST_PMD:
966 vmid_dereference(codec);
967 break;
968 }
969
970 return 0;
971}
972
973static void wm8994_update_class_w(struct snd_soc_codec *codec)
974{
975 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
976 int enable = 1;
977 int source = 0; /* GCC flow analysis can't track enable */
978 int reg, reg_r;
979
980 /* Only support direct DAC->headphone paths */
981 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
982 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
983 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
984 enable = 0;
985 }
986
987 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
988 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
989 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
990 enable = 0;
991 }
992
993 /* We also need the same setting for L/R and only one path */
994 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
995 switch (reg) {
996 case WM8994_AIF2DACL_TO_DAC1L:
997 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
998 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
999 break;
1000 case WM8994_AIF1DAC2L_TO_DAC1L:
1001 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1002 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC1L_TO_DAC1L:
1005 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1006 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 default:
1009 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1010 enable = 0;
1011 break;
1012 }
1013
1014 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1015 if (reg_r != reg) {
1016 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1017 enable = 0;
1018 }
1019
1020 if (enable) {
1021 dev_dbg(codec->dev, "Class W enabled\n");
1022 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1023 WM8994_CP_DYN_PWR |
1024 WM8994_CP_DYN_SRC_SEL_MASK,
1025 source | WM8994_CP_DYN_PWR);
1026 wm8994->hubs.class_w = true;
1027
1028 } else {
1029 dev_dbg(codec->dev, "Class W disabled\n");
1030 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1031 WM8994_CP_DYN_PWR, 0);
1032 wm8994->hubs.class_w = false;
1033 }
1034}
1035
1036static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1037 struct snd_kcontrol *kcontrol, int event)
1038{
1039 struct snd_soc_codec *codec = w->codec;
1040 struct wm8994 *control = codec->control_data;
1041 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1042 int i;
1043 int dac;
1044 int adc;
1045 int val;
1046
1047 switch (control->type) {
1048 case WM8994:
1049 case WM8958:
1050 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1051 break;
1052 default:
1053 break;
1054 }
1055
1056 switch (event) {
1057 case SND_SOC_DAPM_PRE_PMU:
1058 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1059 if ((val & WM8994_AIF1ADCL_SRC) &&
1060 (val & WM8994_AIF1ADCR_SRC))
1061 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1062 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1063 !(val & WM8994_AIF1ADCR_SRC))
1064 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1065 else
1066 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1067 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1068
1069 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1070 if ((val & WM8994_AIF1DACL_SRC) &&
1071 (val & WM8994_AIF1DACR_SRC))
1072 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1073 else if (!(val & WM8994_AIF1DACL_SRC) &&
1074 !(val & WM8994_AIF1DACR_SRC))
1075 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1076 else
1077 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1078 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1079
1080 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1081 mask, adc);
1082 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1083 mask, dac);
1084 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1085 WM8994_AIF1DSPCLK_ENA |
1086 WM8994_SYSDSPCLK_ENA,
1087 WM8994_AIF1DSPCLK_ENA |
1088 WM8994_SYSDSPCLK_ENA);
1089 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1090 WM8994_AIF1ADC1R_ENA |
1091 WM8994_AIF1ADC1L_ENA |
1092 WM8994_AIF1ADC2R_ENA |
1093 WM8994_AIF1ADC2L_ENA);
1094 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1095 WM8994_AIF1DAC1R_ENA |
1096 WM8994_AIF1DAC1L_ENA |
1097 WM8994_AIF1DAC2R_ENA |
1098 WM8994_AIF1DAC2L_ENA);
1099 break;
1100
1101 case SND_SOC_DAPM_POST_PMU:
1102 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1103 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1104 snd_soc_read(codec,
1105 wm8994_vu_bits[i].reg));
1106 break;
1107
1108 case SND_SOC_DAPM_PRE_PMD:
1109 case SND_SOC_DAPM_POST_PMD:
1110 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1111 mask, 0);
1112 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1113 mask, 0);
1114
1115 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1116 if (val & WM8994_AIF2DSPCLK_ENA)
1117 val = WM8994_SYSDSPCLK_ENA;
1118 else
1119 val = 0;
1120 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1121 WM8994_SYSDSPCLK_ENA |
1122 WM8994_AIF1DSPCLK_ENA, val);
1123 break;
1124 }
1125
1126 return 0;
1127}
1128
1129static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1130 struct snd_kcontrol *kcontrol, int event)
1131{
1132 struct snd_soc_codec *codec = w->codec;
1133 int i;
1134 int dac;
1135 int adc;
1136 int val;
1137
1138 switch (event) {
1139 case SND_SOC_DAPM_PRE_PMU:
1140 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1141 if ((val & WM8994_AIF2ADCL_SRC) &&
1142 (val & WM8994_AIF2ADCR_SRC))
1143 adc = WM8994_AIF2ADCR_ENA;
1144 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1145 !(val & WM8994_AIF2ADCR_SRC))
1146 adc = WM8994_AIF2ADCL_ENA;
1147 else
1148 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1149
1150
1151 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1152 if ((val & WM8994_AIF2DACL_SRC) &&
1153 (val & WM8994_AIF2DACR_SRC))
1154 dac = WM8994_AIF2DACR_ENA;
1155 else if (!(val & WM8994_AIF2DACL_SRC) &&
1156 !(val & WM8994_AIF2DACR_SRC))
1157 dac = WM8994_AIF2DACL_ENA;
1158 else
1159 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1160
1161 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1162 WM8994_AIF2ADCL_ENA |
1163 WM8994_AIF2ADCR_ENA, adc);
1164 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1165 WM8994_AIF2DACL_ENA |
1166 WM8994_AIF2DACR_ENA, dac);
1167 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1168 WM8994_AIF2DSPCLK_ENA |
1169 WM8994_SYSDSPCLK_ENA,
1170 WM8994_AIF2DSPCLK_ENA |
1171 WM8994_SYSDSPCLK_ENA);
1172 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1173 WM8994_AIF2ADCL_ENA |
1174 WM8994_AIF2ADCR_ENA,
1175 WM8994_AIF2ADCL_ENA |
1176 WM8994_AIF2ADCR_ENA);
1177 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1178 WM8994_AIF2DACL_ENA |
1179 WM8994_AIF2DACR_ENA,
1180 WM8994_AIF2DACL_ENA |
1181 WM8994_AIF2DACR_ENA);
1182 break;
1183
1184 case SND_SOC_DAPM_POST_PMU:
1185 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1186 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1187 snd_soc_read(codec,
1188 wm8994_vu_bits[i].reg));
1189 break;
1190
1191 case SND_SOC_DAPM_PRE_PMD:
1192 case SND_SOC_DAPM_POST_PMD:
1193 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1194 WM8994_AIF2DACL_ENA |
1195 WM8994_AIF2DACR_ENA, 0);
1196 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1197 WM8994_AIF2ADCL_ENA |
1198 WM8994_AIF2ADCR_ENA, 0);
1199
1200 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1201 if (val & WM8994_AIF1DSPCLK_ENA)
1202 val = WM8994_SYSDSPCLK_ENA;
1203 else
1204 val = 0;
1205 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1206 WM8994_SYSDSPCLK_ENA |
1207 WM8994_AIF2DSPCLK_ENA, val);
1208 break;
1209 }
1210
1211 return 0;
1212}
1213
1214static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1215 struct snd_kcontrol *kcontrol, int event)
1216{
1217 struct snd_soc_codec *codec = w->codec;
1218 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1219
1220 switch (event) {
1221 case SND_SOC_DAPM_PRE_PMU:
1222 wm8994->aif1clk_enable = 1;
1223 break;
1224 case SND_SOC_DAPM_POST_PMD:
1225 wm8994->aif1clk_disable = 1;
1226 break;
1227 }
1228
1229 return 0;
1230}
1231
1232static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1233 struct snd_kcontrol *kcontrol, int event)
1234{
1235 struct snd_soc_codec *codec = w->codec;
1236 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1237
1238 switch (event) {
1239 case SND_SOC_DAPM_PRE_PMU:
1240 wm8994->aif2clk_enable = 1;
1241 break;
1242 case SND_SOC_DAPM_POST_PMD:
1243 wm8994->aif2clk_disable = 1;
1244 break;
1245 }
1246
1247 return 0;
1248}
1249
1250static int late_enable_ev(struct snd_soc_dapm_widget *w,
1251 struct snd_kcontrol *kcontrol, int event)
1252{
1253 struct snd_soc_codec *codec = w->codec;
1254 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1255
1256 switch (event) {
1257 case SND_SOC_DAPM_PRE_PMU:
1258 if (wm8994->aif1clk_enable) {
1259 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1260 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1261 WM8994_AIF1CLK_ENA_MASK,
1262 WM8994_AIF1CLK_ENA);
1263 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1264 wm8994->aif1clk_enable = 0;
1265 }
1266 if (wm8994->aif2clk_enable) {
1267 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1268 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1269 WM8994_AIF2CLK_ENA_MASK,
1270 WM8994_AIF2CLK_ENA);
1271 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1272 wm8994->aif2clk_enable = 0;
1273 }
1274 break;
1275 }
1276
1277 /* We may also have postponed startup of DSP, handle that. */
1278 wm8958_aif_ev(w, kcontrol, event);
1279
1280 return 0;
1281}
1282
1283static int late_disable_ev(struct snd_soc_dapm_widget *w,
1284 struct snd_kcontrol *kcontrol, int event)
1285{
1286 struct snd_soc_codec *codec = w->codec;
1287 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1288
1289 switch (event) {
1290 case SND_SOC_DAPM_POST_PMD:
1291 if (wm8994->aif1clk_disable) {
1292 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1293 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1294 WM8994_AIF1CLK_ENA_MASK, 0);
1295 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1296 wm8994->aif1clk_disable = 0;
1297 }
1298 if (wm8994->aif2clk_disable) {
1299 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1300 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1301 WM8994_AIF2CLK_ENA_MASK, 0);
1302 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1303 wm8994->aif2clk_disable = 0;
1304 }
1305 break;
1306 }
1307
1308 return 0;
1309}
1310
1311static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1312 struct snd_kcontrol *kcontrol, int event)
1313{
1314 late_enable_ev(w, kcontrol, event);
1315 return 0;
1316}
1317
1318static int micbias_ev(struct snd_soc_dapm_widget *w,
1319 struct snd_kcontrol *kcontrol, int event)
1320{
1321 late_enable_ev(w, kcontrol, event);
1322 return 0;
1323}
1324
1325static int dac_ev(struct snd_soc_dapm_widget *w,
1326 struct snd_kcontrol *kcontrol, int event)
1327{
1328 struct snd_soc_codec *codec = w->codec;
1329 unsigned int mask = 1 << w->shift;
1330
1331 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1332 mask, mask);
1333 return 0;
1334}
1335
1336static const char *hp_mux_text[] = {
1337 "Mixer",
1338 "DAC",
1339};
1340
1341#define WM8994_HP_ENUM(xname, xenum) \
1342{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1343 .info = snd_soc_info_enum_double, \
1344 .get = snd_soc_dapm_get_enum_double, \
1345 .put = wm8994_put_hp_enum, \
1346 .private_value = (unsigned long)&xenum }
1347
1348static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1349 struct snd_ctl_elem_value *ucontrol)
1350{
1351 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1352 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1353 struct snd_soc_codec *codec = w->codec;
1354 int ret;
1355
1356 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1357
1358 wm8994_update_class_w(codec);
1359
1360 return ret;
1361}
1362
1363static const struct soc_enum hpl_enum =
1364 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1365
1366static const struct snd_kcontrol_new hpl_mux =
1367 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1368
1369static const struct soc_enum hpr_enum =
1370 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1371
1372static const struct snd_kcontrol_new hpr_mux =
1373 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1374
1375static const char *adc_mux_text[] = {
1376 "ADC",
1377 "DMIC",
1378};
1379
1380static const struct soc_enum adc_enum =
1381 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1382
1383static const struct snd_kcontrol_new adcl_mux =
1384 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1385
1386static const struct snd_kcontrol_new adcr_mux =
1387 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1388
1389static const struct snd_kcontrol_new left_speaker_mixer[] = {
1390SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1391SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1392SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1393SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1394SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1395};
1396
1397static const struct snd_kcontrol_new right_speaker_mixer[] = {
1398SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1399SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1400SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1401SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1402SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1403};
1404
1405/* Debugging; dump chip status after DAPM transitions */
1406static int post_ev(struct snd_soc_dapm_widget *w,
1407 struct snd_kcontrol *kcontrol, int event)
1408{
1409 struct snd_soc_codec *codec = w->codec;
1410 dev_dbg(codec->dev, "SRC status: %x\n",
1411 snd_soc_read(codec,
1412 WM8994_RATE_STATUS));
1413 return 0;
1414}
1415
1416static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1417SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1418 1, 1, 0),
1419SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1420 0, 1, 0),
1421};
1422
1423static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1424SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1425 1, 1, 0),
1426SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1427 0, 1, 0),
1428};
1429
1430static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1431SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1432 1, 1, 0),
1433SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1434 0, 1, 0),
1435};
1436
1437static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1438SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1439 1, 1, 0),
1440SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1441 0, 1, 0),
1442};
1443
1444static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1445SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1446 5, 1, 0),
1447SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1448 4, 1, 0),
1449SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1450 2, 1, 0),
1451SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1452 1, 1, 0),
1453SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1454 0, 1, 0),
1455};
1456
1457static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1458SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1459 5, 1, 0),
1460SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1461 4, 1, 0),
1462SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1463 2, 1, 0),
1464SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1465 1, 1, 0),
1466SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1467 0, 1, 0),
1468};
1469
1470#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1471{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1472 .info = snd_soc_info_volsw, \
1473 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1474 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1475
1476static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1477 struct snd_ctl_elem_value *ucontrol)
1478{
1479 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1480 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1481 struct snd_soc_codec *codec = w->codec;
1482 int ret;
1483
1484 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1485
1486 wm8994_update_class_w(codec);
1487
1488 return ret;
1489}
1490
1491static const struct snd_kcontrol_new dac1l_mix[] = {
1492WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1493 5, 1, 0),
1494WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1495 4, 1, 0),
1496WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1497 2, 1, 0),
1498WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1499 1, 1, 0),
1500WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1501 0, 1, 0),
1502};
1503
1504static const struct snd_kcontrol_new dac1r_mix[] = {
1505WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1506 5, 1, 0),
1507WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1508 4, 1, 0),
1509WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1510 2, 1, 0),
1511WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1512 1, 1, 0),
1513WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1514 0, 1, 0),
1515};
1516
1517static const char *sidetone_text[] = {
1518 "ADC/DMIC1", "DMIC2",
1519};
1520
1521static const struct soc_enum sidetone1_enum =
1522 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1523
1524static const struct snd_kcontrol_new sidetone1_mux =
1525 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1526
1527static const struct soc_enum sidetone2_enum =
1528 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1529
1530static const struct snd_kcontrol_new sidetone2_mux =
1531 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1532
1533static const char *aif1dac_text[] = {
1534 "AIF1DACDAT", "AIF3DACDAT",
1535};
1536
1537static const struct soc_enum aif1dac_enum =
1538 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1539
1540static const struct snd_kcontrol_new aif1dac_mux =
1541 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1542
1543static const char *aif2dac_text[] = {
1544 "AIF2DACDAT", "AIF3DACDAT",
1545};
1546
1547static const struct soc_enum aif2dac_enum =
1548 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1549
1550static const struct snd_kcontrol_new aif2dac_mux =
1551 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1552
1553static const char *aif2adc_text[] = {
1554 "AIF2ADCDAT", "AIF3DACDAT",
1555};
1556
1557static const struct soc_enum aif2adc_enum =
1558 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1559
1560static const struct snd_kcontrol_new aif2adc_mux =
1561 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1562
1563static const char *aif3adc_text[] = {
1564 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1565};
1566
1567static const struct soc_enum wm8994_aif3adc_enum =
1568 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1569
1570static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1571 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1572
1573static const struct soc_enum wm8958_aif3adc_enum =
1574 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1575
1576static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1577 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1578
1579static const char *mono_pcm_out_text[] = {
1580 "None", "AIF2ADCL", "AIF2ADCR",
1581};
1582
1583static const struct soc_enum mono_pcm_out_enum =
1584 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1585
1586static const struct snd_kcontrol_new mono_pcm_out_mux =
1587 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1588
1589static const char *aif2dac_src_text[] = {
1590 "AIF2", "AIF3",
1591};
1592
1593/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1594static const struct soc_enum aif2dacl_src_enum =
1595 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1596
1597static const struct snd_kcontrol_new aif2dacl_src_mux =
1598 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1599
1600static const struct soc_enum aif2dacr_src_enum =
1601 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1602
1603static const struct snd_kcontrol_new aif2dacr_src_mux =
1604 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1605
1606static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1607SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1608 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1609SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1610 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1611
1612SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1614SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1616SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1617 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1618SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1619 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1620SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1621 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1622
1623SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1624 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1625 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1626SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1627 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1628 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1629SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1630 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1631SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1632 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1633
1634SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1635};
1636
1637static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1638SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1639 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1640 SND_SOC_DAPM_PRE_PMD),
1641SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1642 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1643 SND_SOC_DAPM_PRE_PMD),
1644SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1645SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1646 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1647SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1648 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1649SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1650SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1651};
1652
1653static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1654SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1655 dac_ev, SND_SOC_DAPM_PRE_PMU),
1656SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1657 dac_ev, SND_SOC_DAPM_PRE_PMU),
1658SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1659 dac_ev, SND_SOC_DAPM_PRE_PMU),
1660SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1661 dac_ev, SND_SOC_DAPM_PRE_PMU),
1662};
1663
1664static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1665SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1666SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1667SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1668SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1669};
1670
1671static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1672SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1673 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1674SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1675 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1676};
1677
1678static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1679SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1680SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1681};
1682
1683static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1684SND_SOC_DAPM_INPUT("DMIC1DAT"),
1685SND_SOC_DAPM_INPUT("DMIC2DAT"),
1686SND_SOC_DAPM_INPUT("Clock"),
1687
1688SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1689 SND_SOC_DAPM_PRE_PMU),
1690SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1692
1693SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1694 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1695
1696SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1697SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1698SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1699
1700SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1701 0, SND_SOC_NOPM, 9, 0),
1702SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1703 0, SND_SOC_NOPM, 8, 0),
1704SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1705 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1706 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1707SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1708 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1709 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1710
1711SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1712 0, SND_SOC_NOPM, 11, 0),
1713SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1714 0, SND_SOC_NOPM, 10, 0),
1715SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1716 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1717 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1718SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1719 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1720 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1721
1722SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1723 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1724SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1725 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1726
1727SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1728 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1729SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1730 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1731
1732SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1733 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1734SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1735 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1736
1737SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1738SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1739
1740SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1741 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1742SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1743 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1744
1745SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1746 SND_SOC_NOPM, 13, 0),
1747SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1748 SND_SOC_NOPM, 12, 0),
1749SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1750 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1751 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1752SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1753 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1754 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1755
1756SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1757SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1758SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1759SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1760
1761SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1762SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1763SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1764
1765SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1766SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1767
1768SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1769
1770SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1771SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1772SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1773SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1774
1775/* Power is done with the muxes since the ADC power also controls the
1776 * downsampling chain, the chip will automatically manage the analogue
1777 * specific portions.
1778 */
1779SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1780SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1781
1782SND_SOC_DAPM_POST("Debug log", post_ev),
1783};
1784
1785static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1786SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1787};
1788
1789static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1790SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1791SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1792SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1793SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1794};
1795
1796static const struct snd_soc_dapm_route intercon[] = {
1797 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1798 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1799
1800 { "DSP1CLK", NULL, "CLK_SYS" },
1801 { "DSP2CLK", NULL, "CLK_SYS" },
1802 { "DSPINTCLK", NULL, "CLK_SYS" },
1803
1804 { "AIF1ADC1L", NULL, "AIF1CLK" },
1805 { "AIF1ADC1L", NULL, "DSP1CLK" },
1806 { "AIF1ADC1R", NULL, "AIF1CLK" },
1807 { "AIF1ADC1R", NULL, "DSP1CLK" },
1808 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1809
1810 { "AIF1DAC1L", NULL, "AIF1CLK" },
1811 { "AIF1DAC1L", NULL, "DSP1CLK" },
1812 { "AIF1DAC1R", NULL, "AIF1CLK" },
1813 { "AIF1DAC1R", NULL, "DSP1CLK" },
1814 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1815
1816 { "AIF1ADC2L", NULL, "AIF1CLK" },
1817 { "AIF1ADC2L", NULL, "DSP1CLK" },
1818 { "AIF1ADC2R", NULL, "AIF1CLK" },
1819 { "AIF1ADC2R", NULL, "DSP1CLK" },
1820 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1821
1822 { "AIF1DAC2L", NULL, "AIF1CLK" },
1823 { "AIF1DAC2L", NULL, "DSP1CLK" },
1824 { "AIF1DAC2R", NULL, "AIF1CLK" },
1825 { "AIF1DAC2R", NULL, "DSP1CLK" },
1826 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1827
1828 { "AIF2ADCL", NULL, "AIF2CLK" },
1829 { "AIF2ADCL", NULL, "DSP2CLK" },
1830 { "AIF2ADCR", NULL, "AIF2CLK" },
1831 { "AIF2ADCR", NULL, "DSP2CLK" },
1832 { "AIF2ADCR", NULL, "DSPINTCLK" },
1833
1834 { "AIF2DACL", NULL, "AIF2CLK" },
1835 { "AIF2DACL", NULL, "DSP2CLK" },
1836 { "AIF2DACR", NULL, "AIF2CLK" },
1837 { "AIF2DACR", NULL, "DSP2CLK" },
1838 { "AIF2DACR", NULL, "DSPINTCLK" },
1839
1840 { "DMIC1L", NULL, "DMIC1DAT" },
1841 { "DMIC1L", NULL, "CLK_SYS" },
1842 { "DMIC1R", NULL, "DMIC1DAT" },
1843 { "DMIC1R", NULL, "CLK_SYS" },
1844 { "DMIC2L", NULL, "DMIC2DAT" },
1845 { "DMIC2L", NULL, "CLK_SYS" },
1846 { "DMIC2R", NULL, "DMIC2DAT" },
1847 { "DMIC2R", NULL, "CLK_SYS" },
1848
1849 { "ADCL", NULL, "AIF1CLK" },
1850 { "ADCL", NULL, "DSP1CLK" },
1851 { "ADCL", NULL, "DSPINTCLK" },
1852
1853 { "ADCR", NULL, "AIF1CLK" },
1854 { "ADCR", NULL, "DSP1CLK" },
1855 { "ADCR", NULL, "DSPINTCLK" },
1856
1857 { "ADCL Mux", "ADC", "ADCL" },
1858 { "ADCL Mux", "DMIC", "DMIC1L" },
1859 { "ADCR Mux", "ADC", "ADCR" },
1860 { "ADCR Mux", "DMIC", "DMIC1R" },
1861
1862 { "DAC1L", NULL, "AIF1CLK" },
1863 { "DAC1L", NULL, "DSP1CLK" },
1864 { "DAC1L", NULL, "DSPINTCLK" },
1865
1866 { "DAC1R", NULL, "AIF1CLK" },
1867 { "DAC1R", NULL, "DSP1CLK" },
1868 { "DAC1R", NULL, "DSPINTCLK" },
1869
1870 { "DAC2L", NULL, "AIF2CLK" },
1871 { "DAC2L", NULL, "DSP2CLK" },
1872 { "DAC2L", NULL, "DSPINTCLK" },
1873
1874 { "DAC2R", NULL, "AIF2DACR" },
1875 { "DAC2R", NULL, "AIF2CLK" },
1876 { "DAC2R", NULL, "DSP2CLK" },
1877 { "DAC2R", NULL, "DSPINTCLK" },
1878
1879 { "TOCLK", NULL, "CLK_SYS" },
1880
1881 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1882 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1883 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1884
1885 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1886 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1887 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1888
1889 /* AIF1 outputs */
1890 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1891 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1892 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1893
1894 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1895 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1896 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1897
1898 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1899 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1900 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1901
1902 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1903 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1904 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905
1906 /* Pin level routing for AIF3 */
1907 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1908 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1909 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1910 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1911
1912 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1913 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1914 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1915 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1916 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1917 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1918 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1919
1920 /* DAC1 inputs */
1921 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1922 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1923 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1924 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1925 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1926
1927 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1928 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1929 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1930 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1931 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1932
1933 /* DAC2/AIF2 outputs */
1934 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1935 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1936 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1937 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1938 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1939 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1940
1941 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1942 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1943 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1944 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1945 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1946 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1947
1948 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1949 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1950 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1951 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1952
1953 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1954
1955 /* AIF3 output */
1956 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1957 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1958 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1959 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1960 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1961 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1962 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1963 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1964
1965 /* Sidetone */
1966 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1967 { "Left Sidetone", "DMIC2", "DMIC2L" },
1968 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1969 { "Right Sidetone", "DMIC2", "DMIC2R" },
1970
1971 /* Output stages */
1972 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1973 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1974
1975 { "SPKL", "DAC1 Switch", "DAC1L" },
1976 { "SPKL", "DAC2 Switch", "DAC2L" },
1977
1978 { "SPKR", "DAC1 Switch", "DAC1R" },
1979 { "SPKR", "DAC2 Switch", "DAC2R" },
1980
1981 { "Left Headphone Mux", "DAC", "DAC1L" },
1982 { "Right Headphone Mux", "DAC", "DAC1R" },
1983};
1984
1985static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1986 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1987 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1988 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1989 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1990 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1991 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1992 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1993 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1994};
1995
1996static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1997 { "DAC1L", NULL, "DAC1L Mixer" },
1998 { "DAC1R", NULL, "DAC1R Mixer" },
1999 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2000 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2001};
2002
2003static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2004 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2005 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2006 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2007 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2008 { "MICBIAS1", NULL, "CLK_SYS" },
2009 { "MICBIAS1", NULL, "MICBIAS Supply" },
2010 { "MICBIAS2", NULL, "CLK_SYS" },
2011 { "MICBIAS2", NULL, "MICBIAS Supply" },
2012};
2013
2014static const struct snd_soc_dapm_route wm8994_intercon[] = {
2015 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2016 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2017 { "MICBIAS1", NULL, "VMID" },
2018 { "MICBIAS2", NULL, "VMID" },
2019};
2020
2021static const struct snd_soc_dapm_route wm8958_intercon[] = {
2022 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2023 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2024
2025 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2026 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2027 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2028 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2029
2030 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2031 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2032
2033 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2034};
2035
2036/* The size in bits of the FLL divide multiplied by 10
2037 * to allow rounding later */
2038#define FIXED_FLL_SIZE ((1 << 16) * 10)
2039
2040struct fll_div {
2041 u16 outdiv;
2042 u16 n;
2043 u16 k;
2044 u16 clk_ref_div;
2045 u16 fll_fratio;
2046};
2047
2048static int wm8994_get_fll_config(struct fll_div *fll,
2049 int freq_in, int freq_out)
2050{
2051 u64 Kpart;
2052 unsigned int K, Ndiv, Nmod;
2053
2054 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2055
2056 /* Scale the input frequency down to <= 13.5MHz */
2057 fll->clk_ref_div = 0;
2058 while (freq_in > 13500000) {
2059 fll->clk_ref_div++;
2060 freq_in /= 2;
2061
2062 if (fll->clk_ref_div > 3)
2063 return -EINVAL;
2064 }
2065 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2066
2067 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2068 fll->outdiv = 3;
2069 while (freq_out * (fll->outdiv + 1) < 90000000) {
2070 fll->outdiv++;
2071 if (fll->outdiv > 63)
2072 return -EINVAL;
2073 }
2074 freq_out *= fll->outdiv + 1;
2075 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2076
2077 if (freq_in > 1000000) {
2078 fll->fll_fratio = 0;
2079 } else if (freq_in > 256000) {
2080 fll->fll_fratio = 1;
2081 freq_in *= 2;
2082 } else if (freq_in > 128000) {
2083 fll->fll_fratio = 2;
2084 freq_in *= 4;
2085 } else if (freq_in > 64000) {
2086 fll->fll_fratio = 3;
2087 freq_in *= 8;
2088 } else {
2089 fll->fll_fratio = 4;
2090 freq_in *= 16;
2091 }
2092 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2093
2094 /* Now, calculate N.K */
2095 Ndiv = freq_out / freq_in;
2096
2097 fll->n = Ndiv;
2098 Nmod = freq_out % freq_in;
2099 pr_debug("Nmod=%d\n", Nmod);
2100
2101 /* Calculate fractional part - scale up so we can round. */
2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2103
2104 do_div(Kpart, freq_in);
2105
2106 K = Kpart & 0xFFFFFFFF;
2107
2108 if ((K % 10) >= 5)
2109 K += 5;
2110
2111 /* Move down to proper range now rounding is done */
2112 fll->k = K / 10;
2113
2114 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2115
2116 return 0;
2117}
2118
2119static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2120 unsigned int freq_in, unsigned int freq_out)
2121{
2122 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2123 struct wm8994 *control = wm8994->wm8994;
2124 int reg_offset, ret;
2125 struct fll_div fll;
2126 u16 reg, aif1, aif2;
2127 unsigned long timeout;
2128 bool was_enabled;
2129
2130 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2131 & WM8994_AIF1CLK_ENA;
2132
2133 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2134 & WM8994_AIF2CLK_ENA;
2135
2136 switch (id) {
2137 case WM8994_FLL1:
2138 reg_offset = 0;
2139 id = 0;
2140 break;
2141 case WM8994_FLL2:
2142 reg_offset = 0x20;
2143 id = 1;
2144 break;
2145 default:
2146 return -EINVAL;
2147 }
2148
2149 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2150 was_enabled = reg & WM8994_FLL1_ENA;
2151
2152 switch (src) {
2153 case 0:
2154 /* Allow no source specification when stopping */
2155 if (freq_out)
2156 return -EINVAL;
2157 src = wm8994->fll[id].src;
2158 break;
2159 case WM8994_FLL_SRC_MCLK1:
2160 case WM8994_FLL_SRC_MCLK2:
2161 case WM8994_FLL_SRC_LRCLK:
2162 case WM8994_FLL_SRC_BCLK:
2163 break;
2164 default:
2165 return -EINVAL;
2166 }
2167
2168 /* Are we changing anything? */
2169 if (wm8994->fll[id].src == src &&
2170 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2171 return 0;
2172
2173 /* If we're stopping the FLL redo the old config - no
2174 * registers will actually be written but we avoid GCC flow
2175 * analysis bugs spewing warnings.
2176 */
2177 if (freq_out)
2178 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2179 else
2180 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2181 wm8994->fll[id].out);
2182 if (ret < 0)
2183 return ret;
2184
2185 /* Gate the AIF clocks while we reclock */
2186 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2187 WM8994_AIF1CLK_ENA, 0);
2188 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2189 WM8994_AIF2CLK_ENA, 0);
2190
2191 /* We always need to disable the FLL while reconfiguring */
2192 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2193 WM8994_FLL1_ENA, 0);
2194
2195 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2196 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2197 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2198 WM8994_FLL1_OUTDIV_MASK |
2199 WM8994_FLL1_FRATIO_MASK, reg);
2200
2201 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2202 WM8994_FLL1_K_MASK, fll.k);
2203
2204 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2205 WM8994_FLL1_N_MASK,
2206 fll.n << WM8994_FLL1_N_SHIFT);
2207
2208 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2209 WM8994_FLL1_REFCLK_DIV_MASK |
2210 WM8994_FLL1_REFCLK_SRC_MASK,
2211 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2212 (src - 1));
2213
2214 /* Clear any pending completion from a previous failure */
2215 try_wait_for_completion(&wm8994->fll_locked[id]);
2216
2217 /* Enable (with fractional mode if required) */
2218 if (freq_out) {
2219 /* Enable VMID if we need it */
2220 if (!was_enabled) {
2221 active_reference(codec);
2222
2223 switch (control->type) {
2224 case WM8994:
2225 vmid_reference(codec);
2226 break;
2227 case WM8958:
2228 if (wm8994->revision < 1)
2229 vmid_reference(codec);
2230 break;
2231 default:
2232 break;
2233 }
2234 }
2235
2236 if (fll.k)
2237 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2238 else
2239 reg = WM8994_FLL1_ENA;
2240 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2241 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2242 reg);
2243
2244 if (wm8994->fll_locked_irq) {
2245 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2246 msecs_to_jiffies(10));
2247 if (timeout == 0)
2248 dev_warn(codec->dev,
2249 "Timed out waiting for FLL lock\n");
2250 } else {
2251 msleep(5);
2252 }
2253 } else {
2254 if (was_enabled) {
2255 switch (control->type) {
2256 case WM8994:
2257 vmid_dereference(codec);
2258 break;
2259 case WM8958:
2260 if (wm8994->revision < 1)
2261 vmid_dereference(codec);
2262 break;
2263 default:
2264 break;
2265 }
2266
2267 active_dereference(codec);
2268 }
2269 }
2270
2271 wm8994->fll[id].in = freq_in;
2272 wm8994->fll[id].out = freq_out;
2273 wm8994->fll[id].src = src;
2274
2275 /* Enable any gated AIF clocks */
2276 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2277 WM8994_AIF1CLK_ENA, aif1);
2278 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2279 WM8994_AIF2CLK_ENA, aif2);
2280
2281 configure_clock(codec);
2282
2283 return 0;
2284}
2285
2286static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2287{
2288 struct completion *completion = data;
2289
2290 complete(completion);
2291
2292 return IRQ_HANDLED;
2293}
2294
2295static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2296
2297static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2298 unsigned int freq_in, unsigned int freq_out)
2299{
2300 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2301}
2302
2303static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2304 int clk_id, unsigned int freq, int dir)
2305{
2306 struct snd_soc_codec *codec = dai->codec;
2307 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2308 int i;
2309
2310 switch (dai->id) {
2311 case 1:
2312 case 2:
2313 break;
2314
2315 default:
2316 /* AIF3 shares clocking with AIF1/2 */
2317 return -EINVAL;
2318 }
2319
2320 switch (clk_id) {
2321 case WM8994_SYSCLK_MCLK1:
2322 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2323 wm8994->mclk[0] = freq;
2324 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2325 dai->id, freq);
2326 break;
2327
2328 case WM8994_SYSCLK_MCLK2:
2329 /* TODO: Set GPIO AF */
2330 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2331 wm8994->mclk[1] = freq;
2332 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2333 dai->id, freq);
2334 break;
2335
2336 case WM8994_SYSCLK_FLL1:
2337 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2338 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2339 break;
2340
2341 case WM8994_SYSCLK_FLL2:
2342 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2343 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2344 break;
2345
2346 case WM8994_SYSCLK_OPCLK:
2347 /* Special case - a division (times 10) is given and
2348 * no effect on main clocking.
2349 */
2350 if (freq) {
2351 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2352 if (opclk_divs[i] == freq)
2353 break;
2354 if (i == ARRAY_SIZE(opclk_divs))
2355 return -EINVAL;
2356 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2357 WM8994_OPCLK_DIV_MASK, i);
2358 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2359 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2360 } else {
2361 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2362 WM8994_OPCLK_ENA, 0);
2363 }
2364
2365 default:
2366 return -EINVAL;
2367 }
2368
2369 configure_clock(codec);
2370
2371 return 0;
2372}
2373
2374static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2375 enum snd_soc_bias_level level)
2376{
2377 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2378 struct wm8994 *control = wm8994->wm8994;
2379
2380 wm_hubs_set_bias_level(codec, level);
2381
2382 switch (level) {
2383 case SND_SOC_BIAS_ON:
2384 break;
2385
2386 case SND_SOC_BIAS_PREPARE:
2387 /* MICBIAS into regulating mode */
2388 switch (control->type) {
2389 case WM8958:
2390 case WM1811:
2391 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2392 WM8958_MICB1_MODE, 0);
2393 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2394 WM8958_MICB2_MODE, 0);
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2401 active_reference(codec);
2402 break;
2403
2404 case SND_SOC_BIAS_STANDBY:
2405 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2406 switch (control->type) {
2407 case WM8958:
2408 if (wm8994->revision == 0) {
2409 /* Optimise performance for rev A */
2410 snd_soc_update_bits(codec,
2411 WM8958_CHARGE_PUMP_2,
2412 WM8958_CP_DISCH,
2413 WM8958_CP_DISCH);
2414 }
2415 break;
2416
2417 default:
2418 break;
2419 }
2420
2421 /* Discharge LINEOUT1 & 2 */
2422 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2423 WM8994_LINEOUT1_DISCH |
2424 WM8994_LINEOUT2_DISCH,
2425 WM8994_LINEOUT1_DISCH |
2426 WM8994_LINEOUT2_DISCH);
2427 }
2428
2429 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2430 active_dereference(codec);
2431
2432 /* MICBIAS into bypass mode on newer devices */
2433 switch (control->type) {
2434 case WM8958:
2435 case WM1811:
2436 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2437 WM8958_MICB1_MODE,
2438 WM8958_MICB1_MODE);
2439 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2440 WM8958_MICB2_MODE,
2441 WM8958_MICB2_MODE);
2442 break;
2443 default:
2444 break;
2445 }
2446 break;
2447
2448 case SND_SOC_BIAS_OFF:
2449 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2450 wm8994->cur_fw = NULL;
2451 break;
2452 }
2453
2454 codec->dapm.bias_level = level;
2455
2456 return 0;
2457}
2458
2459int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2460{
2461 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2462
2463 switch (mode) {
2464 case WM8994_VMID_NORMAL:
2465 if (wm8994->hubs.lineout1_se) {
2466 snd_soc_dapm_disable_pin(&codec->dapm,
2467 "LINEOUT1N Driver");
2468 snd_soc_dapm_disable_pin(&codec->dapm,
2469 "LINEOUT1P Driver");
2470 }
2471 if (wm8994->hubs.lineout2_se) {
2472 snd_soc_dapm_disable_pin(&codec->dapm,
2473 "LINEOUT2N Driver");
2474 snd_soc_dapm_disable_pin(&codec->dapm,
2475 "LINEOUT2P Driver");
2476 }
2477
2478 /* Do the sync with the old mode to allow it to clean up */
2479 snd_soc_dapm_sync(&codec->dapm);
2480 wm8994->vmid_mode = mode;
2481 break;
2482
2483 case WM8994_VMID_FORCE:
2484 if (wm8994->hubs.lineout1_se) {
2485 snd_soc_dapm_force_enable_pin(&codec->dapm,
2486 "LINEOUT1N Driver");
2487 snd_soc_dapm_force_enable_pin(&codec->dapm,
2488 "LINEOUT1P Driver");
2489 }
2490 if (wm8994->hubs.lineout2_se) {
2491 snd_soc_dapm_force_enable_pin(&codec->dapm,
2492 "LINEOUT2N Driver");
2493 snd_soc_dapm_force_enable_pin(&codec->dapm,
2494 "LINEOUT2P Driver");
2495 }
2496
2497 wm8994->vmid_mode = mode;
2498 snd_soc_dapm_sync(&codec->dapm);
2499 break;
2500
2501 default:
2502 return -EINVAL;
2503 }
2504
2505 return 0;
2506}
2507
2508static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2509{
2510 struct snd_soc_codec *codec = dai->codec;
2511 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2512 struct wm8994 *control = wm8994->wm8994;
2513 int ms_reg;
2514 int aif1_reg;
2515 int ms = 0;
2516 int aif1 = 0;
2517
2518 switch (dai->id) {
2519 case 1:
2520 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2521 aif1_reg = WM8994_AIF1_CONTROL_1;
2522 break;
2523 case 2:
2524 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2525 aif1_reg = WM8994_AIF2_CONTROL_1;
2526 break;
2527 default:
2528 return -EINVAL;
2529 }
2530
2531 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2532 case SND_SOC_DAIFMT_CBS_CFS:
2533 break;
2534 case SND_SOC_DAIFMT_CBM_CFM:
2535 ms = WM8994_AIF1_MSTR;
2536 break;
2537 default:
2538 return -EINVAL;
2539 }
2540
2541 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2542 case SND_SOC_DAIFMT_DSP_B:
2543 aif1 |= WM8994_AIF1_LRCLK_INV;
2544 case SND_SOC_DAIFMT_DSP_A:
2545 aif1 |= 0x18;
2546 break;
2547 case SND_SOC_DAIFMT_I2S:
2548 aif1 |= 0x10;
2549 break;
2550 case SND_SOC_DAIFMT_RIGHT_J:
2551 break;
2552 case SND_SOC_DAIFMT_LEFT_J:
2553 aif1 |= 0x8;
2554 break;
2555 default:
2556 return -EINVAL;
2557 }
2558
2559 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2560 case SND_SOC_DAIFMT_DSP_A:
2561 case SND_SOC_DAIFMT_DSP_B:
2562 /* frame inversion not valid for DSP modes */
2563 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2564 case SND_SOC_DAIFMT_NB_NF:
2565 break;
2566 case SND_SOC_DAIFMT_IB_NF:
2567 aif1 |= WM8994_AIF1_BCLK_INV;
2568 break;
2569 default:
2570 return -EINVAL;
2571 }
2572 break;
2573
2574 case SND_SOC_DAIFMT_I2S:
2575 case SND_SOC_DAIFMT_RIGHT_J:
2576 case SND_SOC_DAIFMT_LEFT_J:
2577 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2578 case SND_SOC_DAIFMT_NB_NF:
2579 break;
2580 case SND_SOC_DAIFMT_IB_IF:
2581 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2582 break;
2583 case SND_SOC_DAIFMT_IB_NF:
2584 aif1 |= WM8994_AIF1_BCLK_INV;
2585 break;
2586 case SND_SOC_DAIFMT_NB_IF:
2587 aif1 |= WM8994_AIF1_LRCLK_INV;
2588 break;
2589 default:
2590 return -EINVAL;
2591 }
2592 break;
2593 default:
2594 return -EINVAL;
2595 }
2596
2597 /* The AIF2 format configuration needs to be mirrored to AIF3
2598 * on WM8958 if it's in use so just do it all the time. */
2599 switch (control->type) {
2600 case WM1811:
2601 case WM8958:
2602 if (dai->id == 2)
2603 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2604 WM8994_AIF1_LRCLK_INV |
2605 WM8958_AIF3_FMT_MASK, aif1);
2606 break;
2607
2608 default:
2609 break;
2610 }
2611
2612 snd_soc_update_bits(codec, aif1_reg,
2613 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2614 WM8994_AIF1_FMT_MASK,
2615 aif1);
2616 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2617 ms);
2618
2619 return 0;
2620}
2621
2622static struct {
2623 int val, rate;
2624} srs[] = {
2625 { 0, 8000 },
2626 { 1, 11025 },
2627 { 2, 12000 },
2628 { 3, 16000 },
2629 { 4, 22050 },
2630 { 5, 24000 },
2631 { 6, 32000 },
2632 { 7, 44100 },
2633 { 8, 48000 },
2634 { 9, 88200 },
2635 { 10, 96000 },
2636};
2637
2638static int fs_ratios[] = {
2639 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2640};
2641
2642static int bclk_divs[] = {
2643 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2644 640, 880, 960, 1280, 1760, 1920
2645};
2646
2647static int wm8994_hw_params(struct snd_pcm_substream *substream,
2648 struct snd_pcm_hw_params *params,
2649 struct snd_soc_dai *dai)
2650{
2651 struct snd_soc_codec *codec = dai->codec;
2652 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2653 int aif1_reg;
2654 int aif2_reg;
2655 int bclk_reg;
2656 int lrclk_reg;
2657 int rate_reg;
2658 int aif1 = 0;
2659 int aif2 = 0;
2660 int bclk = 0;
2661 int lrclk = 0;
2662 int rate_val = 0;
2663 int id = dai->id - 1;
2664
2665 int i, cur_val, best_val, bclk_rate, best;
2666
2667 switch (dai->id) {
2668 case 1:
2669 aif1_reg = WM8994_AIF1_CONTROL_1;
2670 aif2_reg = WM8994_AIF1_CONTROL_2;
2671 bclk_reg = WM8994_AIF1_BCLK;
2672 rate_reg = WM8994_AIF1_RATE;
2673 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2674 wm8994->lrclk_shared[0]) {
2675 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2676 } else {
2677 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2678 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2679 }
2680 break;
2681 case 2:
2682 aif1_reg = WM8994_AIF2_CONTROL_1;
2683 aif2_reg = WM8994_AIF2_CONTROL_2;
2684 bclk_reg = WM8994_AIF2_BCLK;
2685 rate_reg = WM8994_AIF2_RATE;
2686 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2687 wm8994->lrclk_shared[1]) {
2688 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2689 } else {
2690 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2691 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2692 }
2693 break;
2694 default:
2695 return -EINVAL;
2696 }
2697
2698 bclk_rate = params_rate(params) * 4;
2699 switch (params_format(params)) {
2700 case SNDRV_PCM_FORMAT_S16_LE:
2701 bclk_rate *= 16;
2702 break;
2703 case SNDRV_PCM_FORMAT_S20_3LE:
2704 bclk_rate *= 20;
2705 aif1 |= 0x20;
2706 break;
2707 case SNDRV_PCM_FORMAT_S24_LE:
2708 bclk_rate *= 24;
2709 aif1 |= 0x40;
2710 break;
2711 case SNDRV_PCM_FORMAT_S32_LE:
2712 bclk_rate *= 32;
2713 aif1 |= 0x60;
2714 break;
2715 default:
2716 return -EINVAL;
2717 }
2718
2719 /* Try to find an appropriate sample rate; look for an exact match. */
2720 for (i = 0; i < ARRAY_SIZE(srs); i++)
2721 if (srs[i].rate == params_rate(params))
2722 break;
2723 if (i == ARRAY_SIZE(srs))
2724 return -EINVAL;
2725 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2726
2727 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2728 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2729 dai->id, wm8994->aifclk[id], bclk_rate);
2730
2731 if (params_channels(params) == 1 &&
2732 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2733 aif2 |= WM8994_AIF1_MONO;
2734
2735 if (wm8994->aifclk[id] == 0) {
2736 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2737 return -EINVAL;
2738 }
2739
2740 /* AIFCLK/fs ratio; look for a close match in either direction */
2741 best = 0;
2742 best_val = abs((fs_ratios[0] * params_rate(params))
2743 - wm8994->aifclk[id]);
2744 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2745 cur_val = abs((fs_ratios[i] * params_rate(params))
2746 - wm8994->aifclk[id]);
2747 if (cur_val >= best_val)
2748 continue;
2749 best = i;
2750 best_val = cur_val;
2751 }
2752 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2753 dai->id, fs_ratios[best]);
2754 rate_val |= best;
2755
2756 /* We may not get quite the right frequency if using
2757 * approximate clocks so look for the closest match that is
2758 * higher than the target (we need to ensure that there enough
2759 * BCLKs to clock out the samples).
2760 */
2761 best = 0;
2762 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2763 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2764 if (cur_val < 0) /* BCLK table is sorted */
2765 break;
2766 best = i;
2767 }
2768 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2769 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2770 bclk_divs[best], bclk_rate);
2771 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2772
2773 lrclk = bclk_rate / params_rate(params);
2774 if (!lrclk) {
2775 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2776 bclk_rate);
2777 return -EINVAL;
2778 }
2779 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2780 lrclk, bclk_rate / lrclk);
2781
2782 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2783 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2784 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2785 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2786 lrclk);
2787 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2788 WM8994_AIF1CLK_RATE_MASK, rate_val);
2789
2790 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2791 switch (dai->id) {
2792 case 1:
2793 wm8994->dac_rates[0] = params_rate(params);
2794 wm8994_set_retune_mobile(codec, 0);
2795 wm8994_set_retune_mobile(codec, 1);
2796 break;
2797 case 2:
2798 wm8994->dac_rates[1] = params_rate(params);
2799 wm8994_set_retune_mobile(codec, 2);
2800 break;
2801 }
2802 }
2803
2804 return 0;
2805}
2806
2807static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2808 struct snd_pcm_hw_params *params,
2809 struct snd_soc_dai *dai)
2810{
2811 struct snd_soc_codec *codec = dai->codec;
2812 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2813 struct wm8994 *control = wm8994->wm8994;
2814 int aif1_reg;
2815 int aif1 = 0;
2816
2817 switch (dai->id) {
2818 case 3:
2819 switch (control->type) {
2820 case WM1811:
2821 case WM8958:
2822 aif1_reg = WM8958_AIF3_CONTROL_1;
2823 break;
2824 default:
2825 return 0;
2826 }
2827 break;
2828 default:
2829 return 0;
2830 }
2831
2832 switch (params_format(params)) {
2833 case SNDRV_PCM_FORMAT_S16_LE:
2834 break;
2835 case SNDRV_PCM_FORMAT_S20_3LE:
2836 aif1 |= 0x20;
2837 break;
2838 case SNDRV_PCM_FORMAT_S24_LE:
2839 aif1 |= 0x40;
2840 break;
2841 case SNDRV_PCM_FORMAT_S32_LE:
2842 aif1 |= 0x60;
2843 break;
2844 default:
2845 return -EINVAL;
2846 }
2847
2848 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2849}
2850
2851static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2852 struct snd_soc_dai *dai)
2853{
2854 struct snd_soc_codec *codec = dai->codec;
2855 int rate_reg = 0;
2856
2857 switch (dai->id) {
2858 case 1:
2859 rate_reg = WM8994_AIF1_RATE;
2860 break;
2861 case 2:
2862 rate_reg = WM8994_AIF2_RATE;
2863 break;
2864 default:
2865 break;
2866 }
2867
2868 /* If the DAI is idle then configure the divider tree for the
2869 * lowest output rate to save a little power if the clock is
2870 * still active (eg, because it is system clock).
2871 */
2872 if (rate_reg && !dai->playback_active && !dai->capture_active)
2873 snd_soc_update_bits(codec, rate_reg,
2874 WM8994_AIF1_SR_MASK |
2875 WM8994_AIF1CLK_RATE_MASK, 0x9);
2876}
2877
2878static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2879{
2880 struct snd_soc_codec *codec = codec_dai->codec;
2881 int mute_reg;
2882 int reg;
2883
2884 switch (codec_dai->id) {
2885 case 1:
2886 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2887 break;
2888 case 2:
2889 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2890 break;
2891 default:
2892 return -EINVAL;
2893 }
2894
2895 if (mute)
2896 reg = WM8994_AIF1DAC1_MUTE;
2897 else
2898 reg = 0;
2899
2900 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2901
2902 return 0;
2903}
2904
2905static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2906{
2907 struct snd_soc_codec *codec = codec_dai->codec;
2908 int reg, val, mask;
2909
2910 switch (codec_dai->id) {
2911 case 1:
2912 reg = WM8994_AIF1_MASTER_SLAVE;
2913 mask = WM8994_AIF1_TRI;
2914 break;
2915 case 2:
2916 reg = WM8994_AIF2_MASTER_SLAVE;
2917 mask = WM8994_AIF2_TRI;
2918 break;
2919 case 3:
2920 reg = WM8994_POWER_MANAGEMENT_6;
2921 mask = WM8994_AIF3_TRI;
2922 break;
2923 default:
2924 return -EINVAL;
2925 }
2926
2927 if (tristate)
2928 val = mask;
2929 else
2930 val = 0;
2931
2932 return snd_soc_update_bits(codec, reg, mask, val);
2933}
2934
2935static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2936{
2937 struct snd_soc_codec *codec = dai->codec;
2938
2939 /* Disable the pulls on the AIF if we're using it to save power. */
2940 snd_soc_update_bits(codec, WM8994_GPIO_3,
2941 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2942 snd_soc_update_bits(codec, WM8994_GPIO_4,
2943 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2944 snd_soc_update_bits(codec, WM8994_GPIO_5,
2945 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2946
2947 return 0;
2948}
2949
2950#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2951
2952#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2953 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2954
2955static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2956 .set_sysclk = wm8994_set_dai_sysclk,
2957 .set_fmt = wm8994_set_dai_fmt,
2958 .hw_params = wm8994_hw_params,
2959 .shutdown = wm8994_aif_shutdown,
2960 .digital_mute = wm8994_aif_mute,
2961 .set_pll = wm8994_set_fll,
2962 .set_tristate = wm8994_set_tristate,
2963};
2964
2965static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2966 .set_sysclk = wm8994_set_dai_sysclk,
2967 .set_fmt = wm8994_set_dai_fmt,
2968 .hw_params = wm8994_hw_params,
2969 .shutdown = wm8994_aif_shutdown,
2970 .digital_mute = wm8994_aif_mute,
2971 .set_pll = wm8994_set_fll,
2972 .set_tristate = wm8994_set_tristate,
2973};
2974
2975static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2976 .hw_params = wm8994_aif3_hw_params,
2977 .set_tristate = wm8994_set_tristate,
2978};
2979
2980static struct snd_soc_dai_driver wm8994_dai[] = {
2981 {
2982 .name = "wm8994-aif1",
2983 .id = 1,
2984 .playback = {
2985 .stream_name = "AIF1 Playback",
2986 .channels_min = 1,
2987 .channels_max = 2,
2988 .rates = WM8994_RATES,
2989 .formats = WM8994_FORMATS,
2990 .sig_bits = 24,
2991 },
2992 .capture = {
2993 .stream_name = "AIF1 Capture",
2994 .channels_min = 1,
2995 .channels_max = 2,
2996 .rates = WM8994_RATES,
2997 .formats = WM8994_FORMATS,
2998 .sig_bits = 24,
2999 },
3000 .ops = &wm8994_aif1_dai_ops,
3001 },
3002 {
3003 .name = "wm8994-aif2",
3004 .id = 2,
3005 .playback = {
3006 .stream_name = "AIF2 Playback",
3007 .channels_min = 1,
3008 .channels_max = 2,
3009 .rates = WM8994_RATES,
3010 .formats = WM8994_FORMATS,
3011 .sig_bits = 24,
3012 },
3013 .capture = {
3014 .stream_name = "AIF2 Capture",
3015 .channels_min = 1,
3016 .channels_max = 2,
3017 .rates = WM8994_RATES,
3018 .formats = WM8994_FORMATS,
3019 .sig_bits = 24,
3020 },
3021 .probe = wm8994_aif2_probe,
3022 .ops = &wm8994_aif2_dai_ops,
3023 },
3024 {
3025 .name = "wm8994-aif3",
3026 .id = 3,
3027 .playback = {
3028 .stream_name = "AIF3 Playback",
3029 .channels_min = 1,
3030 .channels_max = 2,
3031 .rates = WM8994_RATES,
3032 .formats = WM8994_FORMATS,
3033 .sig_bits = 24,
3034 },
3035 .capture = {
3036 .stream_name = "AIF3 Capture",
3037 .channels_min = 1,
3038 .channels_max = 2,
3039 .rates = WM8994_RATES,
3040 .formats = WM8994_FORMATS,
3041 .sig_bits = 24,
3042 },
3043 .ops = &wm8994_aif3_dai_ops,
3044 }
3045};
3046
3047#ifdef CONFIG_PM
3048static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3049{
3050 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3051 struct wm8994 *control = wm8994->wm8994;
3052 int i, ret;
3053
3054 switch (control->type) {
3055 case WM8994:
3056 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
3057 break;
3058 case WM1811:
3059 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3060 WM1811_JACKDET_MODE_MASK, 0);
3061 /* Fall through */
3062 case WM8958:
3063 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3064 WM8958_MICD_ENA, 0);
3065 break;
3066 }
3067
3068 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3069 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3070 sizeof(struct wm8994_fll_config));
3071 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3072 if (ret < 0)
3073 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3074 i + 1, ret);
3075 }
3076
3077 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3078
3079 return 0;
3080}
3081
3082static int wm8994_codec_resume(struct snd_soc_codec *codec)
3083{
3084 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3085 struct wm8994 *control = wm8994->wm8994;
3086 int i, ret;
3087 unsigned int val, mask;
3088
3089 if (wm8994->revision < 4) {
3090 /* force a HW read */
3091 ret = regmap_read(control->regmap,
3092 WM8994_POWER_MANAGEMENT_5, &val);
3093
3094 /* modify the cache only */
3095 codec->cache_only = 1;
3096 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3097 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3098 val &= mask;
3099 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3100 mask, val);
3101 codec->cache_only = 0;
3102 }
3103
3104 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3105 if (!wm8994->fll_suspend[i].out)
3106 continue;
3107
3108 ret = _wm8994_set_fll(codec, i + 1,
3109 wm8994->fll_suspend[i].src,
3110 wm8994->fll_suspend[i].in,
3111 wm8994->fll_suspend[i].out);
3112 if (ret < 0)
3113 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3114 i + 1, ret);
3115 }
3116
3117 switch (control->type) {
3118 case WM8994:
3119 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3120 snd_soc_update_bits(codec, WM8994_MICBIAS,
3121 WM8994_MICD_ENA, WM8994_MICD_ENA);
3122 break;
3123 case WM1811:
3124 if (wm8994->jackdet && wm8994->jack_cb) {
3125 /* Restart from idle */
3126 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3127 WM1811_JACKDET_MODE_MASK,
3128 WM1811_JACKDET_MODE_JACK);
3129 break;
3130 }
3131 break;
3132 case WM8958:
3133 if (wm8994->jack_cb)
3134 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3135 WM8958_MICD_ENA, WM8958_MICD_ENA);
3136 break;
3137 }
3138
3139 return 0;
3140}
3141#else
3142#define wm8994_codec_suspend NULL
3143#define wm8994_codec_resume NULL
3144#endif
3145
3146static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3147{
3148 struct snd_soc_codec *codec = wm8994->codec;
3149 struct wm8994_pdata *pdata = wm8994->pdata;
3150 struct snd_kcontrol_new controls[] = {
3151 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3152 wm8994->retune_mobile_enum,
3153 wm8994_get_retune_mobile_enum,
3154 wm8994_put_retune_mobile_enum),
3155 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3156 wm8994->retune_mobile_enum,
3157 wm8994_get_retune_mobile_enum,
3158 wm8994_put_retune_mobile_enum),
3159 SOC_ENUM_EXT("AIF2 EQ Mode",
3160 wm8994->retune_mobile_enum,
3161 wm8994_get_retune_mobile_enum,
3162 wm8994_put_retune_mobile_enum),
3163 };
3164 int ret, i, j;
3165 const char **t;
3166
3167 /* We need an array of texts for the enum API but the number
3168 * of texts is likely to be less than the number of
3169 * configurations due to the sample rate dependency of the
3170 * configurations. */
3171 wm8994->num_retune_mobile_texts = 0;
3172 wm8994->retune_mobile_texts = NULL;
3173 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3174 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3175 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3176 wm8994->retune_mobile_texts[j]) == 0)
3177 break;
3178 }
3179
3180 if (j != wm8994->num_retune_mobile_texts)
3181 continue;
3182
3183 /* Expand the array... */
3184 t = krealloc(wm8994->retune_mobile_texts,
3185 sizeof(char *) *
3186 (wm8994->num_retune_mobile_texts + 1),
3187 GFP_KERNEL);
3188 if (t == NULL)
3189 continue;
3190
3191 /* ...store the new entry... */
3192 t[wm8994->num_retune_mobile_texts] =
3193 pdata->retune_mobile_cfgs[i].name;
3194
3195 /* ...and remember the new version. */
3196 wm8994->num_retune_mobile_texts++;
3197 wm8994->retune_mobile_texts = t;
3198 }
3199
3200 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3201 wm8994->num_retune_mobile_texts);
3202
3203 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3204 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3205
3206 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3207 ARRAY_SIZE(controls));
3208 if (ret != 0)
3209 dev_err(wm8994->codec->dev,
3210 "Failed to add ReTune Mobile controls: %d\n", ret);
3211}
3212
3213static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3214{
3215 struct snd_soc_codec *codec = wm8994->codec;
3216 struct wm8994_pdata *pdata = wm8994->pdata;
3217 int ret, i;
3218
3219 if (!pdata)
3220 return;
3221
3222 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3223 pdata->lineout2_diff,
3224 pdata->lineout1fb,
3225 pdata->lineout2fb,
3226 pdata->jd_scthr,
3227 pdata->jd_thr,
3228 pdata->micbias1_lvl,
3229 pdata->micbias2_lvl);
3230
3231 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3232
3233 if (pdata->num_drc_cfgs) {
3234 struct snd_kcontrol_new controls[] = {
3235 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3236 wm8994_get_drc_enum, wm8994_put_drc_enum),
3237 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3238 wm8994_get_drc_enum, wm8994_put_drc_enum),
3239 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3240 wm8994_get_drc_enum, wm8994_put_drc_enum),
3241 };
3242
3243 /* We need an array of texts for the enum API */
3244 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3245 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3246 if (!wm8994->drc_texts) {
3247 dev_err(wm8994->codec->dev,
3248 "Failed to allocate %d DRC config texts\n",
3249 pdata->num_drc_cfgs);
3250 return;
3251 }
3252
3253 for (i = 0; i < pdata->num_drc_cfgs; i++)
3254 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3255
3256 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3257 wm8994->drc_enum.texts = wm8994->drc_texts;
3258
3259 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3260 ARRAY_SIZE(controls));
3261 if (ret != 0)
3262 dev_err(wm8994->codec->dev,
3263 "Failed to add DRC mode controls: %d\n", ret);
3264
3265 for (i = 0; i < WM8994_NUM_DRC; i++)
3266 wm8994_set_drc(codec, i);
3267 }
3268
3269 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3270 pdata->num_retune_mobile_cfgs);
3271
3272 if (pdata->num_retune_mobile_cfgs)
3273 wm8994_handle_retune_mobile_pdata(wm8994);
3274 else
3275 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3276 ARRAY_SIZE(wm8994_eq_controls));
3277
3278 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3279 if (pdata->micbias[i]) {
3280 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3281 pdata->micbias[i] & 0xffff);
3282 }
3283 }
3284}
3285
3286/**
3287 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3288 *
3289 * @codec: WM8994 codec
3290 * @jack: jack to report detection events on
3291 * @micbias: microphone bias to detect on
3292 *
3293 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3294 * being used to bring out signals to the processor then only platform
3295 * data configuration is needed for WM8994 and processor GPIOs should
3296 * be configured using snd_soc_jack_add_gpios() instead.
3297 *
3298 * Configuration of detection levels is available via the micbias1_lvl
3299 * and micbias2_lvl platform data members.
3300 */
3301int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3302 int micbias)
3303{
3304 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3305 struct wm8994_micdet *micdet;
3306 struct wm8994 *control = wm8994->wm8994;
3307 int reg, ret;
3308
3309 if (control->type != WM8994) {
3310 dev_warn(codec->dev, "Not a WM8994\n");
3311 return -EINVAL;
3312 }
3313
3314 switch (micbias) {
3315 case 1:
3316 micdet = &wm8994->micdet[0];
3317 if (jack)
3318 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3319 "MICBIAS1");
3320 else
3321 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3322 "MICBIAS1");
3323 break;
3324 case 2:
3325 micdet = &wm8994->micdet[1];
3326 if (jack)
3327 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3328 "MICBIAS1");
3329 else
3330 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3331 "MICBIAS1");
3332 break;
3333 default:
3334 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3335 return -EINVAL;
3336 }
3337
3338 if (ret != 0)
3339 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3340 micbias, ret);
3341
3342 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3343 micbias, jack);
3344
3345 /* Store the configuration */
3346 micdet->jack = jack;
3347 micdet->detecting = true;
3348
3349 /* If either of the jacks is set up then enable detection */
3350 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3351 reg = WM8994_MICD_ENA;
3352 else
3353 reg = 0;
3354
3355 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3356
3357 snd_soc_dapm_sync(&codec->dapm);
3358
3359 return 0;
3360}
3361EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3362
3363static irqreturn_t wm8994_mic_irq(int irq, void *data)
3364{
3365 struct wm8994_priv *priv = data;
3366 struct snd_soc_codec *codec = priv->codec;
3367 int reg;
3368 int report;
3369
3370#ifndef CONFIG_SND_SOC_WM8994_MODULE
3371 trace_snd_soc_jack_irq(dev_name(codec->dev));
3372#endif
3373
3374 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3375 if (reg < 0) {
3376 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3377 reg);
3378 return IRQ_HANDLED;
3379 }
3380
3381 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3382
3383 report = 0;
3384 if (reg & WM8994_MIC1_DET_STS) {
3385 if (priv->micdet[0].detecting)
3386 report = SND_JACK_HEADSET;
3387 }
3388 if (reg & WM8994_MIC1_SHRT_STS) {
3389 if (priv->micdet[0].detecting)
3390 report = SND_JACK_HEADPHONE;
3391 else
3392 report |= SND_JACK_BTN_0;
3393 }
3394 if (report)
3395 priv->micdet[0].detecting = false;
3396 else
3397 priv->micdet[0].detecting = true;
3398
3399 snd_soc_jack_report(priv->micdet[0].jack, report,
3400 SND_JACK_HEADSET | SND_JACK_BTN_0);
3401
3402 report = 0;
3403 if (reg & WM8994_MIC2_DET_STS) {
3404 if (priv->micdet[1].detecting)
3405 report = SND_JACK_HEADSET;
3406 }
3407 if (reg & WM8994_MIC2_SHRT_STS) {
3408 if (priv->micdet[1].detecting)
3409 report = SND_JACK_HEADPHONE;
3410 else
3411 report |= SND_JACK_BTN_0;
3412 }
3413 if (report)
3414 priv->micdet[1].detecting = false;
3415 else
3416 priv->micdet[1].detecting = true;
3417
3418 snd_soc_jack_report(priv->micdet[1].jack, report,
3419 SND_JACK_HEADSET | SND_JACK_BTN_0);
3420
3421 return IRQ_HANDLED;
3422}
3423
3424/* Default microphone detection handler for WM8958 - the user can
3425 * override this if they wish.
3426 */
3427static void wm8958_default_micdet(u16 status, void *data)
3428{
3429 struct snd_soc_codec *codec = data;
3430 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3431 int report;
3432
3433 dev_dbg(codec->dev, "MICDET %x\n", status);
3434
3435 /* Either nothing present or just starting detection */
3436 if (!(status & WM8958_MICD_STS)) {
3437 if (!wm8994->jackdet) {
3438 /* If nothing present then clear our statuses */
3439 dev_dbg(codec->dev, "Detected open circuit\n");
3440 wm8994->jack_mic = false;
3441 wm8994->mic_detecting = true;
3442
3443 wm8958_micd_set_rate(codec);
3444
3445 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3446 wm8994->btn_mask |
3447 SND_JACK_HEADSET);
3448 }
3449 return;
3450 }
3451
3452 /* If the measurement is showing a high impedence we've got a
3453 * microphone.
3454 */
3455 if (wm8994->mic_detecting && (status & 0x600)) {
3456 dev_dbg(codec->dev, "Detected microphone\n");
3457
3458 wm8994->mic_detecting = false;
3459 wm8994->jack_mic = true;
3460
3461 wm8958_micd_set_rate(codec);
3462
3463 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3464 SND_JACK_HEADSET);
3465 }
3466
3467
3468 if (wm8994->mic_detecting && status & 0xfc) {
3469 dev_dbg(codec->dev, "Detected headphone\n");
3470 wm8994->mic_detecting = false;
3471
3472 wm8958_micd_set_rate(codec);
3473
3474 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3475 SND_JACK_HEADSET);
3476
3477 /* If we have jackdet that will detect removal */
3478 if (wm8994->jackdet) {
3479 mutex_lock(&wm8994->accdet_lock);
3480
3481 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3482 WM8958_MICD_ENA, 0);
3483
3484 wm1811_jackdet_set_mode(codec,
3485 WM1811_JACKDET_MODE_JACK);
3486
3487 mutex_unlock(&wm8994->accdet_lock);
3488
3489 if (wm8994->pdata->jd_ext_cap) {
3490 mutex_lock(&codec->mutex);
3491 snd_soc_dapm_disable_pin(&codec->dapm,
3492 "MICBIAS2");
3493 snd_soc_dapm_sync(&codec->dapm);
3494 mutex_unlock(&codec->mutex);
3495 }
3496 }
3497 }
3498
3499 /* Report short circuit as a button */
3500 if (wm8994->jack_mic) {
3501 report = 0;
3502 if (status & 0x4)
3503 report |= SND_JACK_BTN_0;
3504
3505 if (status & 0x8)
3506 report |= SND_JACK_BTN_1;
3507
3508 if (status & 0x10)
3509 report |= SND_JACK_BTN_2;
3510
3511 if (status & 0x20)
3512 report |= SND_JACK_BTN_3;
3513
3514 if (status & 0x40)
3515 report |= SND_JACK_BTN_4;
3516
3517 if (status & 0x80)
3518 report |= SND_JACK_BTN_5;
3519
3520 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3521 wm8994->btn_mask);
3522 }
3523}
3524
3525static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3526{
3527 struct wm8994_priv *wm8994 = data;
3528 struct snd_soc_codec *codec = wm8994->codec;
3529 int reg;
3530 bool present;
3531
3532 mutex_lock(&wm8994->accdet_lock);
3533
3534 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3535 if (reg < 0) {
3536 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3537 mutex_unlock(&wm8994->accdet_lock);
3538 return IRQ_NONE;
3539 }
3540
3541 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3542
3543 present = reg & WM1811_JACKDET_LVL;
3544
3545 if (present) {
3546 dev_dbg(codec->dev, "Jack detected\n");
3547
3548 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3549 WM8958_MICB2_DISCH, 0);
3550
3551 /* Disable debounce while inserted */
3552 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3553 WM1811_JACKDET_DB, 0);
3554
3555 /*
3556 * Start off measument of microphone impedence to find
3557 * out what's actually there.
3558 */
3559 wm8994->mic_detecting = true;
3560 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3561
3562 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3563 WM8958_MICD_ENA, WM8958_MICD_ENA);
3564 } else {
3565 dev_dbg(codec->dev, "Jack not detected\n");
3566
3567 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3568 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3569
3570 /* Enable debounce while removed */
3571 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3572 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3573
3574 wm8994->mic_detecting = false;
3575 wm8994->jack_mic = false;
3576 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3577 WM8958_MICD_ENA, 0);
3578 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3579 }
3580
3581 mutex_unlock(&wm8994->accdet_lock);
3582
3583 /* If required for an external cap force MICBIAS on */
3584 if (wm8994->pdata->jd_ext_cap) {
3585 mutex_lock(&codec->mutex);
3586
3587 if (present)
3588 snd_soc_dapm_force_enable_pin(&codec->dapm,
3589 "MICBIAS2");
3590 else
3591 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3592
3593 snd_soc_dapm_sync(&codec->dapm);
3594 mutex_unlock(&codec->mutex);
3595 }
3596
3597 if (present)
3598 snd_soc_jack_report(wm8994->micdet[0].jack,
3599 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3600 else
3601 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3602 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3603 wm8994->btn_mask);
3604
3605 return IRQ_HANDLED;
3606}
3607
3608/**
3609 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3610 *
3611 * @codec: WM8958 codec
3612 * @jack: jack to report detection events on
3613 *
3614 * Enable microphone detection functionality for the WM8958. By
3615 * default simple detection which supports the detection of up to 6
3616 * buttons plus video and microphone functionality is supported.
3617 *
3618 * The WM8958 has an advanced jack detection facility which is able to
3619 * support complex accessory detection, especially when used in
3620 * conjunction with external circuitry. In order to provide maximum
3621 * flexiblity a callback is provided which allows a completely custom
3622 * detection algorithm.
3623 */
3624int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3625 wm8958_micdet_cb cb, void *cb_data)
3626{
3627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3628 struct wm8994 *control = wm8994->wm8994;
3629 u16 micd_lvl_sel;
3630
3631 switch (control->type) {
3632 case WM1811:
3633 case WM8958:
3634 break;
3635 default:
3636 return -EINVAL;
3637 }
3638
3639 if (jack) {
3640 if (!cb) {
3641 dev_dbg(codec->dev, "Using default micdet callback\n");
3642 cb = wm8958_default_micdet;
3643 cb_data = codec;
3644 }
3645
3646 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3647 snd_soc_dapm_sync(&codec->dapm);
3648
3649 wm8994->micdet[0].jack = jack;
3650 wm8994->jack_cb = cb;
3651 wm8994->jack_cb_data = cb_data;
3652
3653 wm8994->mic_detecting = true;
3654 wm8994->jack_mic = false;
3655
3656 wm8958_micd_set_rate(codec);
3657
3658 /* Detect microphones and short circuits by default */
3659 if (wm8994->pdata->micd_lvl_sel)
3660 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3661 else
3662 micd_lvl_sel = 0x41;
3663
3664 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3665 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3666 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3667
3668 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3669 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3670
3671 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3672
3673 /*
3674 * If we can use jack detection start off with that,
3675 * otherwise jump straight to microphone detection.
3676 */
3677 if (wm8994->jackdet) {
3678 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3679 WM8958_MICB2_DISCH,
3680 WM8958_MICB2_DISCH);
3681 snd_soc_update_bits(codec, WM8994_LDO_1,
3682 WM8994_LDO1_DISCH, 0);
3683 wm1811_jackdet_set_mode(codec,
3684 WM1811_JACKDET_MODE_JACK);
3685 } else {
3686 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3687 WM8958_MICD_ENA, WM8958_MICD_ENA);
3688 }
3689
3690 } else {
3691 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3692 WM8958_MICD_ENA, 0);
3693 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3694 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3695 snd_soc_dapm_sync(&codec->dapm);
3696 }
3697
3698 return 0;
3699}
3700EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3701
3702static irqreturn_t wm8958_mic_irq(int irq, void *data)
3703{
3704 struct wm8994_priv *wm8994 = data;
3705 struct snd_soc_codec *codec = wm8994->codec;
3706 int reg, count;
3707
3708 /*
3709 * Jack detection may have detected a removal simulataneously
3710 * with an update of the MICDET status; if so it will have
3711 * stopped detection and we can ignore this interrupt.
3712 */
3713 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3714 return IRQ_HANDLED;
3715
3716 /* We may occasionally read a detection without an impedence
3717 * range being provided - if that happens loop again.
3718 */
3719 count = 10;
3720 do {
3721 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3722 if (reg < 0) {
3723 dev_err(codec->dev,
3724 "Failed to read mic detect status: %d\n",
3725 reg);
3726 return IRQ_NONE;
3727 }
3728
3729 if (!(reg & WM8958_MICD_VALID)) {
3730 dev_dbg(codec->dev, "Mic detect data not valid\n");
3731 goto out;
3732 }
3733
3734 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3735 break;
3736
3737 msleep(1);
3738 } while (count--);
3739
3740 if (count == 0)
3741 dev_warn(codec->dev, "No impedence range reported for jack\n");
3742
3743#ifndef CONFIG_SND_SOC_WM8994_MODULE
3744 trace_snd_soc_jack_irq(dev_name(codec->dev));
3745#endif
3746
3747 if (wm8994->jack_cb)
3748 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3749 else
3750 dev_warn(codec->dev, "Accessory detection with no callback\n");
3751
3752out:
3753 return IRQ_HANDLED;
3754}
3755
3756static irqreturn_t wm8994_fifo_error(int irq, void *data)
3757{
3758 struct snd_soc_codec *codec = data;
3759
3760 dev_err(codec->dev, "FIFO error\n");
3761
3762 return IRQ_HANDLED;
3763}
3764
3765static irqreturn_t wm8994_temp_warn(int irq, void *data)
3766{
3767 struct snd_soc_codec *codec = data;
3768
3769 dev_err(codec->dev, "Thermal warning\n");
3770
3771 return IRQ_HANDLED;
3772}
3773
3774static irqreturn_t wm8994_temp_shut(int irq, void *data)
3775{
3776 struct snd_soc_codec *codec = data;
3777
3778 dev_crit(codec->dev, "Thermal shutdown\n");
3779
3780 return IRQ_HANDLED;
3781}
3782
3783static int wm8994_codec_probe(struct snd_soc_codec *codec)
3784{
3785 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3786 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3787 struct snd_soc_dapm_context *dapm = &codec->dapm;
3788 unsigned int reg;
3789 int ret, i;
3790
3791 wm8994->codec = codec;
3792 codec->control_data = control->regmap;
3793
3794 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3795
3796 wm8994->codec = codec;
3797
3798 mutex_init(&wm8994->accdet_lock);
3799
3800 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3801 init_completion(&wm8994->fll_locked[i]);
3802
3803 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3804 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3805 else if (wm8994->pdata && wm8994->pdata->irq_base)
3806 wm8994->micdet_irq = wm8994->pdata->irq_base +
3807 WM8994_IRQ_MIC1_DET;
3808
3809 pm_runtime_enable(codec->dev);
3810 pm_runtime_idle(codec->dev);
3811
3812 /* By default use idle_bias_off, will override for WM8994 */
3813 codec->dapm.idle_bias_off = 1;
3814
3815 /* Set revision-specific configuration */
3816 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3817 switch (control->type) {
3818 case WM8994:
3819 /* Single ended line outputs should have VMID on. */
3820 if (!wm8994->pdata->lineout1_diff ||
3821 !wm8994->pdata->lineout2_diff)
3822 codec->dapm.idle_bias_off = 0;
3823
3824 switch (wm8994->revision) {
3825 case 2:
3826 case 3:
3827 wm8994->hubs.dcs_codes_l = -5;
3828 wm8994->hubs.dcs_codes_r = -5;
3829 wm8994->hubs.hp_startup_mode = 1;
3830 wm8994->hubs.dcs_readback_mode = 1;
3831 wm8994->hubs.series_startup = 1;
3832 break;
3833 default:
3834 wm8994->hubs.dcs_readback_mode = 2;
3835 break;
3836 }
3837 break;
3838
3839 case WM8958:
3840 wm8994->hubs.dcs_readback_mode = 1;
3841 wm8994->hubs.hp_startup_mode = 1;
3842 break;
3843
3844 case WM1811:
3845 wm8994->hubs.dcs_readback_mode = 2;
3846 wm8994->hubs.no_series_update = 1;
3847 wm8994->hubs.hp_startup_mode = 1;
3848 wm8994->hubs.no_cache_class_w = true;
3849
3850 switch (wm8994->revision) {
3851 case 0:
3852 case 1:
3853 case 2:
3854 case 3:
3855 wm8994->hubs.dcs_codes_l = -9;
3856 wm8994->hubs.dcs_codes_r = -7;
3857 break;
3858 default:
3859 break;
3860 }
3861
3862 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3863 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3864 break;
3865
3866 default:
3867 break;
3868 }
3869
3870 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3871 wm8994_fifo_error, "FIFO error", codec);
3872 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3873 wm8994_temp_warn, "Thermal warning", codec);
3874 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3875 wm8994_temp_shut, "Thermal shutdown", codec);
3876
3877 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3878 wm_hubs_dcs_done, "DC servo done",
3879 &wm8994->hubs);
3880 if (ret == 0)
3881 wm8994->hubs.dcs_done_irq = true;
3882
3883 switch (control->type) {
3884 case WM8994:
3885 if (wm8994->micdet_irq) {
3886 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3887 wm8994_mic_irq,
3888 IRQF_TRIGGER_RISING,
3889 "Mic1 detect",
3890 wm8994);
3891 if (ret != 0)
3892 dev_warn(codec->dev,
3893 "Failed to request Mic1 detect IRQ: %d\n",
3894 ret);
3895 }
3896
3897 ret = wm8994_request_irq(wm8994->wm8994,
3898 WM8994_IRQ_MIC1_SHRT,
3899 wm8994_mic_irq, "Mic 1 short",
3900 wm8994);
3901 if (ret != 0)
3902 dev_warn(codec->dev,
3903 "Failed to request Mic1 short IRQ: %d\n",
3904 ret);
3905
3906 ret = wm8994_request_irq(wm8994->wm8994,
3907 WM8994_IRQ_MIC2_DET,
3908 wm8994_mic_irq, "Mic 2 detect",
3909 wm8994);
3910 if (ret != 0)
3911 dev_warn(codec->dev,
3912 "Failed to request Mic2 detect IRQ: %d\n",
3913 ret);
3914
3915 ret = wm8994_request_irq(wm8994->wm8994,
3916 WM8994_IRQ_MIC2_SHRT,
3917 wm8994_mic_irq, "Mic 2 short",
3918 wm8994);
3919 if (ret != 0)
3920 dev_warn(codec->dev,
3921 "Failed to request Mic2 short IRQ: %d\n",
3922 ret);
3923 break;
3924
3925 case WM8958:
3926 case WM1811:
3927 if (wm8994->micdet_irq) {
3928 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3929 wm8958_mic_irq,
3930 IRQF_TRIGGER_RISING,
3931 "Mic detect",
3932 wm8994);
3933 if (ret != 0)
3934 dev_warn(codec->dev,
3935 "Failed to request Mic detect IRQ: %d\n",
3936 ret);
3937 }
3938 }
3939
3940 switch (control->type) {
3941 case WM1811:
3942 if (wm8994->revision > 1) {
3943 ret = wm8994_request_irq(wm8994->wm8994,
3944 WM8994_IRQ_GPIO(6),
3945 wm1811_jackdet_irq, "JACKDET",
3946 wm8994);
3947 if (ret == 0)
3948 wm8994->jackdet = true;
3949 }
3950 break;
3951 default:
3952 break;
3953 }
3954
3955 wm8994->fll_locked_irq = true;
3956 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3957 ret = wm8994_request_irq(wm8994->wm8994,
3958 WM8994_IRQ_FLL1_LOCK + i,
3959 wm8994_fll_locked_irq, "FLL lock",
3960 &wm8994->fll_locked[i]);
3961 if (ret != 0)
3962 wm8994->fll_locked_irq = false;
3963 }
3964
3965 /* Make sure we can read from the GPIOs if they're inputs */
3966 pm_runtime_get_sync(codec->dev);
3967
3968 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3969 * configured on init - if a system wants to do this dynamically
3970 * at runtime we can deal with that then.
3971 */
3972 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3973 if (ret < 0) {
3974 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3975 goto err_irq;
3976 }
3977 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3978 wm8994->lrclk_shared[0] = 1;
3979 wm8994_dai[0].symmetric_rates = 1;
3980 } else {
3981 wm8994->lrclk_shared[0] = 0;
3982 }
3983
3984 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3985 if (ret < 0) {
3986 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3987 goto err_irq;
3988 }
3989 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3990 wm8994->lrclk_shared[1] = 1;
3991 wm8994_dai[1].symmetric_rates = 1;
3992 } else {
3993 wm8994->lrclk_shared[1] = 0;
3994 }
3995
3996 pm_runtime_put(codec->dev);
3997
3998 /* Latch volume update bits */
3999 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4000 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4001 wm8994_vu_bits[i].mask,
4002 wm8994_vu_bits[i].mask);
4003
4004 /* Set the low bit of the 3D stereo depth so TLV matches */
4005 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4006 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4007 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4008 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4009 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4010 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4011 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4012 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4013 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4014
4015 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4016 * use this; it only affects behaviour on idle TDM clock
4017 * cycles. */
4018 switch (control->type) {
4019 case WM8994:
4020 case WM8958:
4021 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4022 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4023 break;
4024 default:
4025 break;
4026 }
4027
4028 /* Put MICBIAS into bypass mode by default on newer devices */
4029 switch (control->type) {
4030 case WM8958:
4031 case WM1811:
4032 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4033 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4034 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4035 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4036 break;
4037 default:
4038 break;
4039 }
4040
4041 wm8994_update_class_w(codec);
4042
4043 wm8994_handle_pdata(wm8994);
4044
4045 wm_hubs_add_analogue_controls(codec);
4046 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4047 ARRAY_SIZE(wm8994_snd_controls));
4048 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4049 ARRAY_SIZE(wm8994_dapm_widgets));
4050
4051 switch (control->type) {
4052 case WM8994:
4053 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4054 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4055 if (wm8994->revision < 4) {
4056 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4057 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4058 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4059 ARRAY_SIZE(wm8994_adc_revd_widgets));
4060 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4061 ARRAY_SIZE(wm8994_dac_revd_widgets));
4062 } else {
4063 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4064 ARRAY_SIZE(wm8994_lateclk_widgets));
4065 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4066 ARRAY_SIZE(wm8994_adc_widgets));
4067 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4068 ARRAY_SIZE(wm8994_dac_widgets));
4069 }
4070 break;
4071 case WM8958:
4072 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4073 ARRAY_SIZE(wm8958_snd_controls));
4074 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4075 ARRAY_SIZE(wm8958_dapm_widgets));
4076 if (wm8994->revision < 1) {
4077 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4078 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4079 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4080 ARRAY_SIZE(wm8994_adc_revd_widgets));
4081 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4082 ARRAY_SIZE(wm8994_dac_revd_widgets));
4083 } else {
4084 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4085 ARRAY_SIZE(wm8994_lateclk_widgets));
4086 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4087 ARRAY_SIZE(wm8994_adc_widgets));
4088 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4089 ARRAY_SIZE(wm8994_dac_widgets));
4090 }
4091 break;
4092
4093 case WM1811:
4094 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4095 ARRAY_SIZE(wm8958_snd_controls));
4096 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4097 ARRAY_SIZE(wm8958_dapm_widgets));
4098 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4099 ARRAY_SIZE(wm8994_lateclk_widgets));
4100 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4101 ARRAY_SIZE(wm8994_adc_widgets));
4102 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4103 ARRAY_SIZE(wm8994_dac_widgets));
4104 break;
4105 }
4106
4107
4108 wm_hubs_add_analogue_routes(codec, 0, 0);
4109 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4110
4111 switch (control->type) {
4112 case WM8994:
4113 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4114 ARRAY_SIZE(wm8994_intercon));
4115
4116 if (wm8994->revision < 4) {
4117 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4118 ARRAY_SIZE(wm8994_revd_intercon));
4119 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4120 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4121 } else {
4122 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4123 ARRAY_SIZE(wm8994_lateclk_intercon));
4124 }
4125 break;
4126 case WM8958:
4127 if (wm8994->revision < 1) {
4128 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4129 ARRAY_SIZE(wm8994_revd_intercon));
4130 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4131 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4132 } else {
4133 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4134 ARRAY_SIZE(wm8994_lateclk_intercon));
4135 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4136 ARRAY_SIZE(wm8958_intercon));
4137 }
4138
4139 wm8958_dsp2_init(codec);
4140 break;
4141 case WM1811:
4142 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4143 ARRAY_SIZE(wm8994_lateclk_intercon));
4144 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4145 ARRAY_SIZE(wm8958_intercon));
4146 break;
4147 }
4148
4149 return 0;
4150
4151err_irq:
4152 if (wm8994->jackdet)
4153 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4154 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4155 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4156 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4157 if (wm8994->micdet_irq)
4158 free_irq(wm8994->micdet_irq, wm8994);
4159 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4160 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4161 &wm8994->fll_locked[i]);
4162 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4163 &wm8994->hubs);
4164 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4165 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4166 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4167
4168 return ret;
4169}
4170
4171static int wm8994_codec_remove(struct snd_soc_codec *codec)
4172{
4173 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4174 struct wm8994 *control = wm8994->wm8994;
4175 int i;
4176
4177 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4178
4179 pm_runtime_disable(codec->dev);
4180
4181 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4182 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4183 &wm8994->fll_locked[i]);
4184
4185 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4186 &wm8994->hubs);
4187 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4188 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4189 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4190
4191 if (wm8994->jackdet)
4192 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4193
4194 switch (control->type) {
4195 case WM8994:
4196 if (wm8994->micdet_irq)
4197 free_irq(wm8994->micdet_irq, wm8994);
4198 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4199 wm8994);
4200 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4201 wm8994);
4202 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4203 wm8994);
4204 break;
4205
4206 case WM1811:
4207 case WM8958:
4208 if (wm8994->micdet_irq)
4209 free_irq(wm8994->micdet_irq, wm8994);
4210 break;
4211 }
4212 if (wm8994->mbc)
4213 release_firmware(wm8994->mbc);
4214 if (wm8994->mbc_vss)
4215 release_firmware(wm8994->mbc_vss);
4216 if (wm8994->enh_eq)
4217 release_firmware(wm8994->enh_eq);
4218 kfree(wm8994->retune_mobile_texts);
4219
4220 return 0;
4221}
4222
4223static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4224 .probe = wm8994_codec_probe,
4225 .remove = wm8994_codec_remove,
4226 .suspend = wm8994_codec_suspend,
4227 .resume = wm8994_codec_resume,
4228 .set_bias_level = wm8994_set_bias_level,
4229};
4230
4231static int __devinit wm8994_probe(struct platform_device *pdev)
4232{
4233 struct wm8994_priv *wm8994;
4234
4235 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4236 GFP_KERNEL);
4237 if (wm8994 == NULL)
4238 return -ENOMEM;
4239 platform_set_drvdata(pdev, wm8994);
4240
4241 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4242 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4243
4244 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4245 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4246}
4247
4248static int __devexit wm8994_remove(struct platform_device *pdev)
4249{
4250 snd_soc_unregister_codec(&pdev->dev);
4251 return 0;
4252}
4253
4254#ifdef CONFIG_PM_SLEEP
4255static int wm8994_suspend(struct device *dev)
4256{
4257 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4258
4259 /* Drop down to power saving mode when system is suspended */
4260 if (wm8994->jackdet && !wm8994->active_refcount)
4261 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4262 WM1811_JACKDET_MODE_MASK,
4263 wm8994->jackdet_mode);
4264
4265 return 0;
4266}
4267
4268static int wm8994_resume(struct device *dev)
4269{
4270 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4271
4272 if (wm8994->jackdet && wm8994->jack_cb)
4273 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4274 WM1811_JACKDET_MODE_MASK,
4275 WM1811_JACKDET_MODE_AUDIO);
4276
4277 return 0;
4278}
4279#endif
4280
4281static const struct dev_pm_ops wm8994_pm_ops = {
4282 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4283};
4284
4285static struct platform_driver wm8994_codec_driver = {
4286 .driver = {
4287 .name = "wm8994-codec",
4288 .owner = THIS_MODULE,
4289 .pm = &wm8994_pm_ops,
4290 },
4291 .probe = wm8994_probe,
4292 .remove = __devexit_p(wm8994_remove),
4293};
4294
4295module_platform_driver(wm8994_codec_driver);
4296
4297MODULE_DESCRIPTION("ASoC WM8994 driver");
4298MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4299MODULE_LICENSE("GPL");
4300MODULE_ALIAS("platform:wm8994-codec");