[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/dramk_2731/emi.c b/src/bsp/dramk_2731/emi.c
new file mode 100755
index 0000000..f263026
--- /dev/null
+++ b/src/bsp/dramk_2731/emi.c
@@ -0,0 +1,3575 @@
+//=============================================================================
+// Include Files
+//=============================================================================
+#include <dramc_common.h>
+
+#if !__FLASH_TOOL_DA__ && (FOR_DV_SIMULATION_USED==0)
+ #include <emi_hw.h>
+#endif
+
+#if defined(DEF_LAST_DRAMC)
+#include <platform/plat_dbg_info.h>
+#endif
+
+#include <emi.h>
+
+#if !__FLASH_TOOL_DA__ && !__ETT__
+#include <custom_emi.h>
+#endif
+
+#if __ETT__
+#include "ett_common.h"
+#include "emi.h"
+#endif
+
+#if CFG_BOOT_ARGUMENT
+#define bootarg g_dram_buf->bootarg
+#endif
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if __ETT__
+#include <pmic.h>
+#else
+#include <platform/pmic.h>
+#include <platform/mtk_drm.h>
+#endif
+//#include <rt5738.h>
+/* now we can use definition MTK_PMIC_CHIP_MT6356 */
+#if __ETT__
+//#undef MTK_PMIC_CHIP_MT6356
+#undef MTK_PMIC_CHIP_RT5738 //sagy
+#else
+
+#ifdef PMIC_CHIP_MT6356
+#define MTK_PMIC_CHIP_MT6356
+#define MTK_PMIC_CHIP_RT5738
+#endif
+
+#ifdef PMIC_CHIP_MT6389
+#define MTK_PMIC_CHIP_MT6389
+#endif
+
+#endif
+#endif
+
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+#if __ETT__
+#include <regulator/mtk_regulator.h>
+#else
+#include <platform/regulator/mtk_regulator.h>
+#endif
+#endif
+
+#ifdef MTK_PMIC_CHIP_RT5738
+#if !__ETT__
+#include <platform/rt5738.h>
+#endif
+#endif
+
+#if !__ETT__
+#define CQ_DMA_BASE (IO_PHYS+0x212000)
+#endif
+
+//=============================================================================
+// Definition
+//=============================================================================
+static unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
+
+//=============================================================================
+// Global Variables
+//=============================================================================
+#ifdef DRAM_ADAPTIVE
+static unsigned char auto_detect_done;
+#endif
+int emi_setting_index = -1;
+static unsigned int mr5;
+static unsigned int rank_swap;
+extern DRAMC_CTX_T *psCurrDramCtx;
+#ifdef DRAM_ADAPTIVE
+extern EMI_SETTINGS g_default_emi_setting;
+#else
+extern EMI_SETTINGS default_emi_setting;
+#endif
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+static struct mtk_regulator reg_vdram, reg_vcore, reg_vddq;
+#endif
+
+#ifdef LAST_DRAMC
+static LAST_DRAMC_INFO_T* last_dramc_info_ptr;
+#endif
+
+#ifdef LAST_EMI
+static LAST_EMI_INFO_T* last_emi_info_ptr;
+#endif
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+extern u64 get_part_addr(const char *name);
+static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
+static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
+#if !__ETT__ && (FOR_DV_SIMULATION_USED == 0)
+static u64 part_dram_data_addr = 0;
+static unsigned int dram_offline_data_flags = 0;
+#endif
+#endif
+//=============================================================================
+// External references
+//=============================================================================
+extern DRAMC_CTX_T *psCurrDramCtx;
+extern char* opt_dle_value;
+
+void print_DBG_info(DRAMC_CTX_T *p);
+void Dump_EMIRegisters(DRAMC_CTX_T *p);
+
+#define EMI_APB_BASE ((volatile void *)EMI_BASE)
+#define EMI_CHANNEL_APB_BASE ((volatile void *)CHN0_EMI_BASE)
+#define INFRA_DRAMC_REG_CONFIG ((volatile void *)0x100010b4)
+
+#define CHN_EMI_CONA(base) ((volatile unsigned int *)(base + 0x000))
+#define CHN_EMI_CONC(base) ((volatile unsigned int *)(base + 0x010))
+
+unsigned int mt_get_dram_type_from_hw_trap(void);
+
+static void emi_cen_config_lp4(unsigned long cfg_base_addr)
+{
+ #ifdef RANK_512MB // => 1channel , one rank , total= 512MB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103016);
+ #else //RANK_1G => 1channel , one rank , total= 1GB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103014);
+ #endif
+ mt_reg_sync_write(EMI_APB_BASE+0x00000004,0x0e290e28); //800 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000008,0x091e1322); //800 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000000c,0x0f29112a); //800 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000010,0x0c240a1f); //800 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b0,0x071b1222); //1200 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b4,0x0a21091e); //1200 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000001c,0x0e250c23); //1200 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000024,0x11291127); //1200 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000034,0x081c1423); //1600 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000006c,0x0a21091d); //1600 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000013c,0x0e260d24); //1600 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000640,0x12291128); //1600 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1600 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1600 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1600 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1600 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000004c,0x1024202c); //2400 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000084,0x0b210c21); //2400 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e4,0x0f250d23); //2400 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000648,0x152b1228); //2400 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000054,0x182e2d33); //3200 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000008c,0x0f251025); //3200 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e8,0x122a1027); //3200 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000064c,0x1a31162d); //3200 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000005c,0x182e2d33); //3733 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000094,0x0f251025); //3733 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001c8,0x122a1027); //3733 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000660,0x1a31162d); //3733 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000064,0x182e2d33); //4266 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000009c,0x0f251025); //4266 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001f4,0x122a1027); //4266 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000664,0x1a31162d); //4266 (1:8) r16 - r13 overhead
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000030,0x37333034); //800 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000014,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b8,0x33313035); //1200 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000002c,0x38383735); //1200 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000c4,0x34322e33); //1600 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000668,0x38383735); //1600 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000cc,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000694,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000e4,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000708,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f4,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000070c,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000012c,0x37373a57); //4266 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000748,0x3f3f3c39); //4266 (1:8) r16 - r10 non-align overhead
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000038,0x88220003);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
+ mt_reg_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
+ mt_reg_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f0,0x384a0034);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
+#ifdef SCN_ICFP
+ mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
+#else //SCN_UI
+ mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107250);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107050);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x30306050); // [31:24]: MDHW {w,r} age
+ mt_reg_sync_write(EMI_APB_BASE+0x00000124,0x00000034);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837048);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837048);
+#endif
+ mt_reg_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000400,0x00ff0000); //[27:20] enable monitor
+ mt_reg_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000808,0x0a0a0a0a);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000080c,0x0a0a0a0a);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000820,0x24240000); //wostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000824,0x00002424); //wostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000828,0x50500000); //rostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x0000082c,0x00005050); //rostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a70);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000083c,0x3c785a3c);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000840,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000844,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000848,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000084c,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000858,0x02533c15);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000874,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000878,0x005a0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000087c,0x0250250f);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c0,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c4,0x00780000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c8,0x000036b0);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008cc,0x008c0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008d0,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008d4,0x00a00000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f0,0x32644b32);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f4,0x8574644b);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f8,0x00001770);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009fc,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b00,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b04,0x00001770);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b08,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b0c,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b10,0x000036b0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b14,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b28,0x1e3c2d1e);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b2c,0x4b463c2d);
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b60,0x14281e14);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b64,0x352e281e);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b98,0x64c89664);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b9c,0xffe9c896);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c08,0x64c89664);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c0c,0xffe9c896);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c4c,0x00000025);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c80,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c84,0x00005dc0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c88,0x00007d00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c8c,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c90,0x00005dc0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c94,0x00007d00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c98,0x000091d5);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c9c,0x0000a6aa);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cb0,0x50a07850);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cb4,0xd5baa078);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d3c,0x00000100); //APR shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d50,0x00001000); //APW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
+ mt_reg_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
+}
+
+static void emi_cen_config_lp2(unsigned long cfg_base_addr)
+{
+#ifndef ONE_CH
+ #ifdef RANK_512MB // => 1channel , one rank , total= 512MB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103016);
+ #else //RANK_1G => 2channel , dual rank , total=4G
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
+ #endif
+#else
+ #ifdef RANK_512MB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xa053a054);
+ #else
+ mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xf053f054);
+ #endif
+#endif
+ mt_reg_sync_write(EMI_APB_BASE+0x00000004,0x0e290e28); //800 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000008,0x091e1322); //800 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000000c,0x0f29112a); //800 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000010,0x0c240a1f); //800 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b0,0x071b1222); //1200 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b4,0x0a21091e); //1200 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000001c,0x0e250c23); //1200 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000024,0x11291127); //1200 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000034,0x081c1423); //1600 (1:4) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000006c,0x0a21091d); //1600 (1:4) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000013c,0x0e260d24); //1600 (1:4) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000640,0x12291128); //1600 (1:4) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1600 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1600 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1600 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1600 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000004c,0x1024202c); //2400 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000084,0x0b210c21); //2400 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e4,0x0f250d23); //2400 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000648,0x152b1228); //2400 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000054,0x182e2d33); //3200 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000008c,0x0f251025); //3200 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001e8,0x122a1027); //3200 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000064c,0x1a31162d); //3200 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000005c,0x182e2d33); //3733 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000094,0x0f251025); //3733 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001c8,0x122a1027); //3733 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000660,0x1a31162d); //3733 (1:8) r16 - r13 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000064,0x182e2d33); //4266 (1:8) r4 - r1 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000009c,0x0f251025); //4266 (1:8) r8 - r5 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000001f4,0x122a1027); //4266 (1:8) r12 - r9 overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000664,0x1a31162d); //4266 (1:8) r16 - r13 overhead
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000030,0x37333034); //800 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000014,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000008b8,0x33313035); //1200 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000002c,0x38383735); //1200 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000c4,0x34322e33); //1600 (1:4) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000668,0x38383735); //1600 (1:4) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000cc,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000694,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000e4,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000708,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f4,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000070c,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x0000012c,0x37373a57); //4266 (1:8) r8 - r2 non-align overhead
+ mt_reg_sync_write(EMI_APB_BASE+0x00000748,0x3f3f3c39); //4266 (1:8) r16 - r10 non-align overhead
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000038,0x88220003);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
+ mt_reg_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
+ mt_reg_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f0,0x384a0034);
+ mt_reg_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
+#ifdef SCN_ICFP
+ mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
+#else //SCN_UI
+ mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107250);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107050);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106050);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000124,0x00000034);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837048);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837048);
+#endif
+ mt_reg_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000400,0x00ff0000); //[27:20] enable monitor
+ mt_reg_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000808,0x0a0a0a0a);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000080c,0x0a0a0a0a);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000820,0x24240101); //wostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000824,0x01012424); //wostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000828,0x50500101); //rostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x0000082c,0x01015050); //rostd throttle
+ mt_reg_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a70);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000083c,0x3c785a3c);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000840,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000844,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000848,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000084c,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000858,0x02533c15);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000874,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000878,0x005a0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x0000087c,0x0250250f);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c0,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c4,0x00780000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008c8,0x000036b0);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008cc,0x008c0000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008d0,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008d4,0x00a00000);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f0,0x32644b32);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f4,0x8574644b);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009f8,0x00001770);
+ mt_reg_sync_write(EMI_APB_BASE+0x000009fc,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b00,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b04,0x00001770);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b08,0x00002328);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b0c,0x00002ee0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b10,0x000036b0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b14,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b28,0x1e3c2d1e);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b2c,0x4b463c2d);
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b60,0x14281e14);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b64,0x352e281e);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b98,0x64c89664);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000b9c,0xffe9c896);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c08,0x64c89664);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c0c,0xffe9c896);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c4c,0x00000025);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c80,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c84,0x00005dc0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c88,0x00007d00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c8c,0x00003e80);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c90,0x00005dc0);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c94,0x00007d00);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c98,0x000091d5);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000c9c,0x0000a6aa);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cb0,0x50a07850);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cb4,0xd5baa078);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
+
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d3c,0x00000100); //APR shf1 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d50,0x00001000); //APW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
+// mt_reg_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
+ mt_reg_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
+ mt_reg_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
+// mt_reg_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
+ mt_reg_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
+ mt_reg_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
+ mt_reg_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
+}
+
+ void emi_cen_config(unsigned long cfg_base_addr) {
+ unsigned int type = mt_get_dram_type_from_hw_trap();
+
+ if (type == TYPE_LPDDR4X) {
+ emi_cen_config_lp4(cfg_base_addr);
+ } else if (type == TYPE_LPDDR2) {
+ emi_cen_config_lp2(cfg_base_addr);
+ } else {
+ dramc_debug("no dram type for init %u\n", type);
+ ASSERT(0);
+ }
+ }//void emi_cen_config()
+
+static void emi_chn_config_lp4(unsigned long cfg_base_addr)
+{
+#ifdef RANK_512MB // => 1channel , one rank , total= 512MB
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x00223012);
+#else //RANK_1G => 1channel , one rank , total= 1GB
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x04242010);
+#endif
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003101);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x91fff928); // continous read/write service count and post_wr settings
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x91fff928); // continous read/write service count and post_wr settings
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3fc79);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3fc79);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
+#ifdef SCN_ICFP
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x884102a2); // Stop urgent read first when write command buffer remain < 8
+#else //SCN_UI
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x024102a2); // disable all exception read events
+#endif
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c822f); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff); // MD BANK_MASK : disable exception read events
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa616cff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa4178ff); // MD BANK_MASK shuffle 0 (MDR urgent): disable exception read events
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
+}
+
+static void emi_chn_config_lp2(unsigned long cfg_base_addr)
+{
+#ifdef RANK_512MB // => 1channel , one rank , total= 512MB
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x00223012);
+#else //RANK_1G => 2channel , dual rank , total=4G
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
+#endif
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003101);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x0719595e);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x0719595e);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3fc79);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3fc79);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
+#ifdef SCN_ICFP
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x884102a2); // Stop urgent read first when write command buffer remain < 8
+#else //SCN_UI
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x824102a2); // Stop urgent read first when write command buffer remain < 2
+#endif
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c822f); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa616cff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa417eff);
+ mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
+}
+
+void emi_chn_config(unsigned long cfg_base_addr) {
+ unsigned int type = mt_get_dram_type_from_hw_trap();
+
+ if (type == TYPE_LPDDR4X) {
+ emi_chn_config_lp4(cfg_base_addr);
+ } else if (type == TYPE_LPDDR2) {
+ emi_chn_config_lp2(cfg_base_addr);
+ } else {
+ dramc_debug("no dram type for init %u\n", type);
+ ASSERT(0);
+ }
+ }//void emi_chn_config()
+
+ //This is for Chip, Please don't remove it.
+ //This is for Chip, Please don't remove it.
+ //#define EMI_APB_BASE 0x10219000
+ //#define EMI_CHANNEL_APB_BASE 0x10235000
+
+ void emi_init(void)
+ {
+ //Broadcast on
+ //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG,0x0000007f);
+
+ emi_cen_config(EMI_BASE);
+ emi_chn_config(CHN0_EMI_BASE);
+
+ //Broadcast off
+ //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG,0x00000000);
+ }
+
+void emi_init2(void)
+ {
+ //Broadcast on
+ //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG, 0x0000007f);
+
+ mt_reg_sync_write(CHN0_EMI_BASE+0x00000010, 0x00000005);
+ mt_reg_sync_write(EMI_BASE+0x00000060, 0x007815ff);
+
+ //Broadcast off
+ //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000);
+ }
+
+
+void EMI_ESL_Setting1(void)
+{
+ emi_init();
+}
+
+void EMI_ESL_Setting2(void)
+{
+ emi_init2();
+}
+
+
+void EMI_Patch(void)
+{
+ //The following is EMI patch
+
+#if !__ETT__
+ // Enable MPU violation interrupt to MD for D1 and D7
+ *((volatile unsigned int *)EMI_MPU_CTRL_D(1)) |= 0x10;
+ *((volatile unsigned int *)EMI_MPU_CTRL_D(7)) |= 0x10;
+
+ // DVFS threshold
+ if (u1IsLP4Family(mt_get_dram_type_from_hw_trap())){
+ /*LP4*/
+ *((volatile unsigned int *)EMI_BWCT0) = 0x0a000705;
+ *((volatile unsigned int *)EMI_BWCT0_3RD) = 0x0;
+ } else {
+ *((volatile unsigned int *)EMI_BWCT0) = 0x07000505; //total BW setting for VcoreDVFS
+ *((volatile unsigned int *)EMI_BWCT0_3RD) = 0x0;
+ }
+
+ // EMI QoS0.5
+ *((volatile unsigned int *) EMI_BWCT0_2ND) = 0x00030023; // monitor AP
+ *((volatile unsigned int *) EMI_BWCT0_4TH) = 0x00C00023; // monitor GPU
+ *((volatile unsigned int *) EMI_BWCT0_5TH) = 0x00240023; // monitor MM
+
+#ifdef LAST_EMI
+ last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
+ last_emi_info_ptr->decs_magic = LAST_EMI_MAGIC_PATTERN;
+#if CFG_LAST_EMI_BW_DUMP
+ last_emi_info_ptr->decs_ctrl = 0xDECDDECD;
+#else
+ last_emi_info_ptr->decs_ctrl = 0xDEC8DEC8;
+#endif
+ last_emi_info_ptr->decs_dram_type = 0;
+ last_emi_info_ptr->decs_diff_us = 0;
+#endif
+#endif
+}
+
+#if !__ETT__
+void reserve_emi_mbw_buf(void)
+{
+#if 0//def LAST_EMI
+ unsigned long long rsv_start;
+ dram_addr_t dram_addr;
+
+ dram_addr.ch = 0;
+ dram_addr.rk = 0;
+ get_dramc_addr(&dram_addr, 0x0);
+
+ if (dram_addr.full_sys_addr > 0xFFFFFFFF)
+ rsv_start = mblock_reserve_ext(&bootarg.mblock_info, 0x800000, 0x800000, 0x100000000, 0, "emi_mbw_buf");
+ else
+ rsv_start = mblock_reserve_ext(&bootarg.mblock_info, 0x800000, 0x800000, dram_addr.full_sys_addr, 0, "emi_mbw_buf");
+
+ last_emi_info_ptr->mbw_buf_l = (unsigned int) (rsv_start & 0xFFFFFFFF);
+ last_emi_info_ptr->mbw_buf_h = (unsigned int) (rsv_start >> 32);
+#endif
+}
+#endif
+
+static void EMI_rank_swap_emi_setting(EMI_SETTINGS *emi_set)
+{
+ static unsigned int temp;
+
+ if (emi_set->EMI_CONA_VAL & 0x20000) {
+ temp = emi_set->EMI_CONA_VAL;
+ emi_set->EMI_CONA_VAL &= ~(0xF3F0F0F0);
+ emi_set->EMI_CONA_VAL |= (temp & 0xC0C0C0C0) >> 2;
+ emi_set->EMI_CONA_VAL |= (temp & 0x30303030) << 2;
+ emi_set->EMI_CONA_VAL |= (temp & 0x02000000) >> 1;
+ emi_set->EMI_CONA_VAL |= (temp & 0x01000000) << 1;
+
+ temp = emi_set->EMI_CONH_VAL;
+ emi_set->EMI_CONH_VAL &= ~(0xFFFF0030);
+ emi_set->EMI_CONH_VAL |= (temp & 0xF0F00000) >> 4;
+ emi_set->EMI_CONH_VAL |= (temp & 0x0F0F0000) << 4;
+ emi_set->EMI_CONH_VAL |= (temp & 0x00000020) >> 1;
+ emi_set->EMI_CONH_VAL |= (temp & 0x00000010) << 1;
+
+ temp = emi_set->CHN0_EMI_CONA_VAL;
+ emi_set->CHN0_EMI_CONA_VAL &= ~(0x00FFF0FC);
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00F00000) >> 4;
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x000F0000) << 4;
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x0000C0C0) >> 2;
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00003030) << 2;
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000008) >> 1;
+ emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000004) << 1;
+
+ emi_set->CHN0_EMI_CONA_VAL |= 0x80000000;
+
+ temp = emi_set->DRAM_RANK_SIZE[0];
+ emi_set->DRAM_RANK_SIZE[0] = emi_set->DRAM_RANK_SIZE[1];
+ emi_set->DRAM_RANK_SIZE[1] = temp;
+
+ if (emi_set->dram_cbt_mode_extern == CBT_R0_NORMAL_R1_BYTE)
+ emi_set->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
+ else if (emi_set->dram_cbt_mode_extern == CBT_R0_BYTE_R1_NORMAL)
+ emi_set->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
+ }
+}
+
+#ifdef DRAM_ADAPTIVE
+void EMI_rank_swap_handle(void)
+{
+ static unsigned int handled = 0;
+ int i;
+
+ if (!handled) {
+ EMI_rank_swap_emi_setting(&g_default_emi_setting);
+ handled = 1;
+ }
+}
+#else
+static void EMI_rank_swap_handle(void)
+{
+ static unsigned int handled = 0;
+ int i;
+
+ if (!handled) {
+ EMI_rank_swap_emi_setting(&default_emi_setting);
+
+ for (i = 0 ; i < num_of_emi_records; i++)
+ EMI_rank_swap_emi_setting(&emi_settings[i]);
+
+ handled = 1;
+ }
+}
+#endif
+
+void EMI_set_rank_swap(unsigned int enable)
+{
+ rank_swap = (enable) ? 1 : 0;
+}
+
+void EMI_Init(DRAMC_CTX_T *p)
+{
+ EMI_SETTINGS *emi_set;
+
+ emi_set = get_emi_setting();
+
+ if (rank_swap)
+ EMI_rank_swap_handle();
+
+ EMI_ESL_Setting1(); //Copy Paste from DE
+
+ //The following is MDL settings
+ *(volatile unsigned *)EMI_CONA = emi_set->EMI_CONA_VAL;
+ *(volatile unsigned *)EMI_CONH = emi_set->EMI_CONH_VAL;
+
+ // CHNA and CHNB uses the same CH0 setting
+ *(volatile unsigned *)CHN_EMI_CONA(CHN0_EMI_BASE) = emi_set->CHN0_EMI_CONA_VAL;
+
+//#if CHANNEL_NUM == 1
+// *(volatile unsigned *)EMI_CONF = 0x0;
+//#else
+ *(volatile unsigned *)EMI_CONF = emi_set->EMI_CONF_VAL;
+ if (u1IsLP4Family(p->dram_type))
+ {
+ *(volatile unsigned *)CHN_EMI_CONC(CHN0_EMI_BASE) = 0x0;
+ } else {
+ *(volatile unsigned *)CHN_EMI_CONC(CHN0_EMI_BASE) = emi_set->EMI_CONF_VAL;
+ }
+//#endif
+
+#if 0
+#if __ETT__ && !defined(__LPAE__)
+ /*
+ * special emi mapping w/o LPAE support
+ * RANK0_MAX_SIZE_ETT = 0x40000000 --> RANK0 @0x4000_0000~0x7fff_ffff
+ * RANK1_MAX_SIZE_ETT = 0x40000000 --> RANK1 @0x8000_0000~0xbfff_ffff
+ */
+ /* set all the rank size of all the channels to the minimum value */
+ *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x11110000));
+
+ /* set all the rank size of all channel-0 to the minimum value */
+ *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
+ = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00110000));
+
+#endif
+#endif
+
+ dsb();
+}
+
+void EMI_Init2(void)
+{
+ EMI_ESL_Setting2(); //Copy Paste from DE
+
+ EMI_Patch(); //Please add the EMI patch here
+}
+
+static unsigned int emi_conh = 0;
+static unsigned int chn_emi_cona[2] = {0, 0};
+
+/* return the start address of rank1 */
+unsigned int set_emi_before_rank1_mem_test(void)
+{
+
+ unsigned int emi_cona;
+
+ emi_cona = *(volatile unsigned int*)EMI_CONA;
+ emi_conh = *(volatile unsigned int*)EMI_CONH;
+ chn_emi_cona[0] = *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE);
+#if 0
+ if (emi_cona & 0x100) {
+ /* set all the rank size of all the channels to the minimum value */
+ *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x22220000));
+
+ /* set all the rank size of all channel-0 to the minimum value */
+ *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
+ = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00220000));
+ } else {
+ /* set all the rank size of all the channels to the minimum value */
+ *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x44440000));
+
+ /* set all the rank size of all channel-0 to the minimum value */
+ *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
+ = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00440000));
+ }
+
+ dsb();
+#endif
+ return 0x20000000;
+
+}
+
+void restore_emi_after_rank1_mem_test(void)
+{
+ *(volatile unsigned int*)EMI_CONH = emi_conh;
+ *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) = chn_emi_cona[0];
+ dsb();
+}
+
+unsigned int check_gating_error(void)
+{
+ unsigned int ret = 0;
+
+#ifdef LAST_DRAMC
+ unsigned long phy_base;
+ unsigned int i, err_code = 0;
+ unsigned int misc_stberr_rk0_r, misc_stberr_rk0_f, misc_stberr_rk1_r, misc_stberr_rk1_f;
+
+ phy_base = Channel_B_PHY_AO_BASE_ADDRESS;
+
+ for (i = 0; i < CHANNEL_NUM; ++i, phy_base += 0x8000, err_code = 0) {
+ misc_stberr_rk0_r = *(volatile unsigned int*)(phy_base + 0x510);
+ misc_stberr_rk0_f = *(volatile unsigned int*)(phy_base + 0x514);
+ misc_stberr_rk1_r = *(volatile unsigned int*)(phy_base + 0x518);
+ misc_stberr_rk1_f = *(volatile unsigned int*)(phy_base + 0x51c);
+ if (misc_stberr_rk0_r & (1 << 16)) {
+ ret |= (1 << i);
+ if ((misc_stberr_rk0_r & 0xffff) != 0) {
+ err_code |= ERR_DRAM_GATING_RK0_R;
+ }
+ if ((misc_stberr_rk0_f & 0xffff) != 0) {
+ err_code |= ERR_DRAM_GATING_RK0_F;
+ }
+ if ((misc_stberr_rk1_r & 0xffff) != 0) {
+ err_code |= ERR_DRAM_GATING_RK1_R;
+ }
+ if ((misc_stberr_rk1_f & 0xffff) != 0) {
+ err_code |= ERR_DRAM_GATING_RK1_F;
+ }
+ dram_fatal_set_gating_err(i, err_code);
+ dram_fatal_set_stberr(i, 0, (misc_stberr_rk0_r & 0xffff) | ((misc_stberr_rk0_f & 0xffff) << 16));
+ dram_fatal_set_stberr(i, 1, (misc_stberr_rk1_r & 0xffff) | ((misc_stberr_rk1_f & 0xffff) << 16));
+ } else {
+ dram_fatal_set_gating_err(i, 0);
+ dram_fatal_set_stberr(i, 0, 0);
+ dram_fatal_set_stberr(i, 1, 0);
+ }
+ }
+#endif
+
+ return ret;
+}
+
+#if 0
+void CHA_HWGW_Print(DRAMC_CTX_T *p)
+{
+ U8 u1RefreshRate;
+ U32 backup_channel, chIdx;
+
+ backup_channel = p->channel;
+
+#if (FOR_DV_SIMULATION_USED==0)
+ // Read HW gating tracking
+#ifdef HW_GATING
+ for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
+ {
+ DramcPrintHWGatingStatus(p, chIdx);
+ }
+#endif
+
+#if ENABLE_RX_TRACKING_LP4
+ for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
+ {
+ DramcPrintRXDQDQSStatus(p, chIdx);
+ }
+#endif
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+ if(u1IsLP4Family(p->dram_type))
+ {
+ DramcPrintIMPTrackingStatus(p, CHANNEL_A);
+//CH_B HW Fail, can't use DramcPrintIMPTrackingStatus(p, CHANNEL_B);
+ }
+#endif
+
+#ifdef TEMP_SENSOR_ENABLE
+ for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
+ {
+ u1RefreshRate = u1GetMR4RefreshRate(p, chIdx);
+ mcSHOW_ERR_MSG(("[CH%d] MRR(MR4) [10:8]=%x\n", chIdx, u1RefreshRate));
+ }
+#endif
+#endif
+
+ vSetPHY2ChannelMapping(p, backup_channel);
+}
+#endif
+
+void Dump_EMIRegisters(DRAMC_CTX_T *p)
+{
+#ifndef OLYMPUS_TO_BE_PORTING
+
+ U8 ucstatus = 0;
+ U32 uiAddr;
+ U32 u4value;
+
+ for (uiAddr=0; uiAddr<0x160; uiAddr+=4)
+ {
+ mcSHOW_DBG_MSG(("EMI offset:%x, value:%x\n", uiAddr, *(volatile unsigned *)(EMI_APB_BASE+uiAddr)));
+ }
+#endif
+}
+
+void print_DBG_info(DRAMC_CTX_T *p)
+{
+#ifndef OLYMPUS_TO_BE_PORTING
+
+ unsigned int addr = 0x0;
+ U32 u4value;
+
+#ifdef DDR_INIT_TIME_PROFILING
+ return;
+#endif
+
+ mcSHOW_DBG_MSG(("EMI_CONA=%x\n",*(volatile unsigned *)(EMI_APB_BASE+0x00000000)));
+ mcSHOW_DBG_MSG(("EMI_CONH=%x\n",*(volatile unsigned *)(EMI_APB_BASE+0x00000038)));
+
+ //RISCReadAll();
+#endif
+}
+
+int mt_get_dram_type(void)
+{
+#if (fcFOR_CHIP_ID == fcLaurel)
+ return (*((volatile unsigned *)(Channel_A_DRAMC_AO_BASE_ADDRESS+0x10)) >> 10) & 0x7;
+#else
+ #error No defined mt_get_dram_type for your chip !!!
+#endif
+}
+
+int mt_get_freq_setting(DRAMC_CTX_T *p)
+{
+ return p->frequency;
+}
+
+#ifdef DDR_RESERVE_MODE
+extern u32 g_ddr_reserve_enable;
+extern u32 g_ddr_reserve_success;
+#define TIMEOUT 3
+extern void before_Dramc_DDR_Reserved_Mode_setting(void);
+#endif
+
+#ifdef DDR_RESERVE_MODE
+
+#define CHAN_DRAMC_NAO_MISC_STATUSA(base) (base + 0x80)
+#define SREF_STATE (1 << 16)
+
+static unsigned int is_dramc_exit_slf(void)
+{
+ unsigned int ret;
+ U32 u4DramType = 0;
+
+ u4DramType = (*((volatile unsigned int *)(IO_PHYS + 0x22A010)) >> 10 & 0x7);
+ if(u4DramType >=2) //LP3:1, LP4:2, LP4X:3
+ {
+ ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_B_DRAMC_NAO_BASE_ADDRESS);
+ if ((ret & SREF_STATE) != 0) {
+ dramc_crit("DRAM CHAN-B is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+ return 0;
+ }
+ }
+ else
+ {
+ ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_A_DRAMC_NAO_BASE_ADDRESS);
+ if ((ret & SREF_STATE) != 0) {
+ dramc_crit("DRAM CHAN-A is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+ return 0;
+ }
+ }
+ dramc_crit("ALL DRAM CHAN is not in self-refresh\n");
+ return 1;
+}
+
+#endif
+
+unsigned int dramc_set_vcore_voltage(unsigned int vcore)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ return mtk_regulator_set_voltage(®_vcore, vcore, MAX_VCORE);
+#endif
+ return 0;
+}
+
+unsigned int dramc_get_vcore_voltage(void)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ return mtk_regulator_get_voltage(®_vcore);
+#else
+ return 0;
+#endif
+}
+
+unsigned int dramc_set_vdd1_voltage(unsigned int ddr_type, unsigned int vdd1)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ unsigned int vio18_vocal;
+ unsigned int vio18_votrim;
+
+ if (vdd1 > 1980000)
+ vdd1 = 188;
+ else if (vdd1 < 1730000)
+ vdd1 = 173;
+ else
+ vdd1 = vdd1 / 10000;
+
+ if (vdd1 > 190) {
+ vio18_vocal = 0xa;
+ vio18_votrim = (198 - vdd1);
+ vio18_votrim |= 0x8;
+ } else if (vdd1 < 180) {
+ vio18_vocal = 0x0;
+ vio18_votrim = (180 - vdd1);
+ } else {
+ vio18_vocal = (vdd1 - 180);
+ vio18_votrim = 0x0;
+ }
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9C76, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+#endif
+ pmic_config_interface(PMIC_RG_VIO18_VOCAL_ADDR, vio18_vocal, PMIC_RG_VIO18_VOCAL_MASK, PMIC_RG_VIO18_VOCAL_SHIFT);
+ pmic_config_interface(PMIC_RG_VIO18_VOTRIM_ADDR, vio18_votrim, PMIC_RG_VIO18_VOTRIM_MASK, PMIC_RG_VIO18_VOTRIM_SHIFT);
+#ifdef MTK_PMIC_CHIP_MT6389
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+#endif
+#endif
+
+ return 0;
+}
+
+unsigned int dramc_get_vdd1_voltage(void)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ unsigned int vio18_vocal;
+ unsigned int vio18_votrim;
+ unsigned int vio18 = 0;
+
+ pmic_read_interface(PMIC_RG_VIO18_VOCAL_ADDR, &vio18_vocal, PMIC_RG_VIO18_VOCAL_MASK, PMIC_RG_VIO18_VOCAL_SHIFT);
+ pmic_read_interface(PMIC_RG_VIO18_VOTRIM_ADDR, &vio18_votrim, PMIC_RG_VIO18_VOTRIM_MASK, PMIC_RG_VIO18_VOTRIM_SHIFT);
+
+ vio18 = (180 + vio18_vocal + (vio18_votrim & 0x8) - (vio18_votrim & 0x7)) * 10000;
+
+ return vio18;
+#else
+ return 0;
+#endif
+}
+
+#ifdef MTK_PMIC_CHIP_MT6356
+static unsigned int lp2_vdram_base[] = {1100000, 1200000};
+static unsigned int lp2_vdram_ofs[] = {20000, 40000};
+#endif
+
+unsigned int dramc_set_vdd2_voltage(unsigned int ddr_type, unsigned int vdd2)
+{
+#ifdef MTK_PMIC_CHIP_MT6356
+ int ret;
+ int mvdd2;
+
+ pmic_config_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, 0, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
+ if (vdd2 < lp2_vdram_base[0]) {
+ ret = 0;
+ mvdd2 = lp2_vdram_base[ret] + lp2_vdram_ofs[ret] - vdd2;
+ if (mvdd2 > 70000) {
+ mvdd2 = 70000;
+ dramc_debug("voltage too low, reset to lowest=%u\n", mvdd2);
+ }
+
+ mvdd2 /= 10000;
+ mtk_regulator_set_voltage(®_vdram, lp2_vdram_base[ret] + lp2_vdram_ofs[ret], 1300000);
+ pmic_config_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, mvdd2, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
+ return 0;
+ }
+
+ for (ret = 0;(unsigned int)ret < (sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base));ret++) {
+ if (vdd2 < lp2_vdram_base[ret]) {
+ ret -= 1;
+ break;
+ }
+ }
+
+ if (ret == sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base))
+ ret -= 1;
+
+ vdd2 -= lp2_vdram_base[ret];
+ if (vdd2 > 100000) {
+ vdd2 = 100000;
+ dramc_debug("voltage offset too high, reset to highest=%u\n", vdd2);
+ }
+
+ vdd2 /= 10000;
+
+ mtk_regulator_set_voltage(®_vdram, lp2_vdram_base[ret] + lp2_vdram_ofs[ret], 1300000);
+ pmic_config_interface(PMIC_RG_VDRAM_VOCAL_ADDR, vdd2, PMIC_RG_VDRAM_VOCAL_MASK, PMIC_RG_VDRAM_VOCAL_SHIFT);
+#endif
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ mtk_regulator_set_voltage(®_vdram, vdd2, 1493750);
+
+#endif
+ return 0;
+}
+
+unsigned int dramc_get_vdd2_voltage(unsigned int ddr_type)
+{
+ unsigned int sum = 0;
+#ifdef MTK_PMIC_CHIP_MT6356
+ unsigned int min = 0;
+
+ sum = mtk_regulator_get_voltage(®_vdram);
+ int ret;
+
+ for (ret = 0;(unsigned int)ret < sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base);ret++) {
+ if (sum == lp2_vdram_base[ret] + lp2_vdram_ofs[ret]) {
+ break;
+ }
+ }
+
+ pmic_read_interface(PMIC_RG_VDRAM_VOCAL_ADDR, &sum, PMIC_RG_VDRAM_VOCAL_MASK, PMIC_RG_VDRAM_VOCAL_SHIFT);
+
+ sum = lp2_vdram_base[ret] + (sum * 10000);
+
+ pmic_read_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, &min, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
+
+ sum -= (min * 10000);
+#endif
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ sum = mtk_regulator_get_voltage(®_vdram);
+#endif
+ return sum;
+}
+
+#ifdef MTK_PMIC_CHIP_MT6389
+static unsigned int vdram2_base[] = {600000, 1800000};
+#endif
+unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq)
+{
+#ifdef MTK_PMIC_CHIP_MT6356
+#if __ETT__
+ mtk_regulator_get("ext_buck_vddq", ®_vddq);
+ if (ddr_type == TYPE_LPDDR4X)
+ mtk_regulator_set_voltage(®_vddq, vddq, 1300000);
+#endif
+#endif
+
+#ifdef MTK_PMIC_CHIP_RT5738
+ if (ddr_type == TYPE_LPDDR4X)
+ rt5738_set_voltage(RT5738_VDDQ, vddq);
+#endif
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ mtk_regulator_get("vdram2", ®_vddq);
+ if (ddr_type == TYPE_LPDDR4X)
+ mtk_regulator_set_voltage(®_vddq, vddq, 1300000);
+
+ unsigned int add = 0;
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9C76, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+ pmic_config_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, 0, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
+ pmic_config_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, 0, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
+ if (vddq > vdram2_base[0])
+ {
+ vddq = vddq - vdram2_base[0];
+ vddq /= 10000;
+ pmic_config_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, vddq, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
+ pmic_read_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, &add, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+ return 0;
+ }
+
+ if (vddq < vdram2_base[0])
+ {
+ vddq = vdram2_base[0] - vddq;
+ vddq /= 10000;
+ pmic_config_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, vddq, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+ }
+#endif
+ return 0;
+}
+
+unsigned int dramc_get_vddq_voltage(unsigned int ddr_type)
+{
+#ifdef MTK_PMIC_CHIP_MT6356
+#if __ETT__
+ unsigned int sum = 0;
+
+ sum = mtk_regulator_get_voltage(®_vddq);
+ return sum;
+#endif
+#endif
+
+#ifdef MTK_PMIC_CHIP_RT5738
+ unsigned int sum = 0;
+ if (ddr_type == TYPE_LPDDR4X)
+ sum = rt5738_get_voltage(RT5738_VDDQ);
+ return sum;
+#endif
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ unsigned int sum = 0;
+
+ sum = mtk_regulator_get_voltage(®_vddq);
+ unsigned int add = 0;
+ pmic_read_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, &add, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
+ sum += add*10000;
+ pmic_read_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, &add, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
+ sum -= add*10000;
+
+ return sum;
+#endif
+}
+
+unsigned int mt_get_dram_type_from_hw_trap(void)
+{
+ static unsigned int ddr_type_detected = 0;
+ static unsigned int pmic_trap_ddr_type = TYPE_LPDDR2;
+
+ if (!ddr_type_detected) {
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ unsigned int hw_trap;
+ hw_trap = get_dram_type();
+
+ switch (hw_trap) {
+ case 0:
+ pmic_trap_ddr_type = TYPE_LPDDR2;
+ break;
+ case 2:
+ pmic_trap_ddr_type = TYPE_LPDDR4X;
+ break;
+ default:
+ dramc_crit("[dramc] Wrong HW TRAP\n");
+ ASSERT(0);
+ break;
+ }
+ dramc_debug("PMIC TRAP GET DDR TYPE: 0x%x\n", pmic_trap_ddr_type);
+#endif
+ ddr_type_detected = 1;
+ }
+
+ return pmic_trap_ddr_type;
+}
+
+void setup_dramc_voltage_by_pmic(void)
+{
+#ifdef MTK_PMIC_CHIP_MT6356
+ unsigned int ddr_type = TYPE_LPDDR4X;//mt_get_dram_type_from_hw_trap();
+#endif
+
+#ifdef MTK_PMIC_CHIP_MT6389
+ unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
+#endif
+
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ int ret;
+
+ ret = mtk_regulator_get("vcore", ®_vcore);
+ if (ret)
+ dramc_crit("mtk_regulator_get vcore fail\n");
+
+#ifdef MTK_PMIC_CHIP_MT6356
+ ret = mtk_regulator_get("vdram", ®_vdram);
+#endif
+#ifdef MTK_PMIC_CHIP_MT6389
+ ret = mtk_regulator_get("vdram1", ®_vdram);
+#endif
+ if (ret)
+ dramc_crit("mtk_regulator_get vdram fail\n");
+
+ mtk_regulator_set_mode(®_vcore, 0x1);
+#endif
+
+ if (u1IsLP4Family(ddr_type)) {
+ dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP4));
+ dramc_set_vddq_voltage(ddr_type, SEL_PREFIX_VDDQ);
+
+#ifdef VCORE_BIN
+ dramc_set_vcore_voltage(get_vcore_uv_table(0));
+#else
+ dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KOPP0));
+#endif
+ } else {
+ /* LPDDR2 */
+#ifdef VCORE_BIN
+ dramc_set_vcore_voltage(get_vcore_uv_table(0));
+#else
+ dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP2, KOPP0));
+#endif
+ dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP2));
+ }
+
+ dramc_crit("Vcore = %d\n", dramc_get_vcore_voltage());
+ dramc_crit("Vdram = %d\n", dramc_get_vdd2_voltage(ddr_type));
+ dramc_crit("Vdd1 = %d\n", dramc_get_vdd1_voltage());
+ if (ddr_type == TYPE_LPDDR4X)
+ dramc_crit("Vddq = %d\n", dramc_get_vddq_voltage(ddr_type));
+}
+
+static void restore_vcore_setting(void)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ int ret;
+
+ ret = mtk_regulator_get("vcore", ®_vcore);
+ if (ret)
+ dramc_crit("mtk_regulator_get vcore fail\n");
+#endif
+
+#ifdef VCORE_BIN
+ dramc_set_vcore_voltage(get_vcore_uv_table(0));
+#else
+ if (u1IsLP4Family(mt_get_dram_type_from_hw_trap()))
+ dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KOPP0));
+ else
+ dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP2, KOPP0));
+#endif
+
+ dramc_crit("Vcore = %d\n", dramc_get_vcore_voltage());
+}
+
+static void restore_pmic_setting(void)
+{
+ unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
+
+ restore_vcore_setting();
+
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ int ret;
+
+#ifdef MTK_PMIC_CHIP_MT6356
+ ret = mtk_regulator_get("vdram", ®_vdram);
+#endif
+#ifdef MTK_PMIC_CHIP_MT6389
+ ret = mtk_regulator_get("vdram1", ®_vdram);
+#endif
+ if (ret) {
+ dramc_crit("mtk_regulator_get vdram fail\n");
+ return;
+ }
+#endif
+
+ if (u1IsLP4Family(ddr_type)) {
+ /* LPDDR4 */
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ ret = mtk_regulator_enable(®_vdram, 1);
+ if (ret)
+ dramc_crit("disable reg_vdram failed\n");
+#endif
+ dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP4));
+ dramc_set_vddq_voltage(ddr_type, SEL_PREFIX_VDDQ);
+ } else
+ dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP2));
+
+ dramc_crit("Vdram = %d\n", dramc_get_vdd2_voltage(ddr_type));
+ if (ddr_type == TYPE_LPDDR4X)
+ dramc_crit("Vddq = %d\n", dramc_get_vddq_voltage(ddr_type));
+}
+
+void switch_dramc_voltage_to_auto_mode(void)
+{
+#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
+ mtk_regulator_set_mode(®_vcore, 0x0);
+#endif
+
+#if 0//def MTK_PMIC_CHIP_RT5738
+ if (u1IsLP4Family(mt_get_dram_type_from_hw_trap())) {
+ rt5738_set_mode(RT5738_VDD2, 0x0);
+ rt5738_set_mode(RT5738_VDDQ, 0x0);
+ }
+#endif
+}
+
+void release_dram(void)
+{
+#ifdef DDR_RESERVE_MODE
+ int i;
+ int counter = TIMEOUT;
+
+ // scy: restore pmic setting (VCORE, VDRAM, VSRAM, VDDQ)
+ restore_pmic_setting();
+ drm_release_rg_dramc_conf_iso();//Release DRAMC/PHY conf ISO
+ Dramc_DDR_Reserved_Mode_setting();
+ drm_release_rg_dramc_iso();//Release PHY IO ISO
+ drm_release_rg_dramc_sref();//Let DRAM Leave SR
+
+ // setup for EMI: touch center EMI and channel EMI to enable CLK
+ dramc_crit("[DDR reserve] EMI CONA: %x\n", *(volatile unsigned int*)EMI_CONA);
+ dramc_crit("[DDR reserve] EMI CHA CONA: %x\n", *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE));
+ for (i=0;i<10;i++);
+
+ while(counter)
+ {
+ if(is_dramc_exit_slf() == 1) /* expect to exit dram-self-refresh */
+ break;
+ counter--;
+ }
+
+ if(counter == 0)
+ {
+ if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+ {
+ dramc_crit("[DDR Reserve] release dram from self-refresh FAIL!\n");
+ g_ddr_reserve_success = 0;
+ }
+ }
+ else
+ {
+ dramc_crit("[DDR Reserve] release dram from self-refresh PASS!\n");
+ }
+ Dramc_DDR_Reserved_Mode_AfterSR();
+ //Expect to Use LPDDR3200 and PHYPLL as output, so no need to handle
+ //shuffle status since the status will be reset by system reset
+ //There is an PLLL_SHU_GP in SPM which will reset by system reset
+ return;
+#endif
+}
+
+void check_ddr_reserve_status(void)
+{
+#ifdef DDR_RESERVE_MODE
+ /* get status of DCS and DVFSRC */
+ int dvfsrc_success = drm_is_dvfsrc_success();
+ int dvfsrc_en = drm_is_dvfsrc_enable();
+ int counter = TIMEOUT;
+
+ if(drm_is_reserve_ddr_enabled())
+ {
+ g_ddr_reserve_enable = 1;
+#ifdef LAST_DRAMC
+ dram_fatal_set_ddr_rsv_mode_flow();
+#endif
+
+ if(drm_is_reserve_ddr_mode_success())
+ {
+ while(counter)
+ {
+ if(drm_is_dram_slf())
+ {
+ g_ddr_reserve_success = 1;
+ break;
+ }
+ counter--;
+ }
+ if(counter == 0)
+ {
+ dramc_crit("[DDR Reserve] ddr reserve mode success but DRAM not in self-refresh!\n");
+ g_ddr_reserve_success = 0;
+#ifdef LAST_DRAMC
+ dram_fatal_set_ddr_rsv_mode_err();
+#endif
+ }
+ }
+ else
+ {
+ dramc_crit("[DDR Reserve] ddr reserve mode FAIL!\n");
+ g_ddr_reserve_success = 0;
+#ifdef LAST_DRAMC
+ dram_fatal_set_ddr_rsv_mode_err();
+#endif
+ }
+ /* Disable DDR-reserve mode in pre-loader stage then enable it again in kernel stage */
+ //drm_dram_reserved(0);
+
+ /* overwrite g_ddr_reserve_success if some of dvfsrc/drs failed */
+ /* TODO: check DRS status */
+ if (dvfsrc_en == 1 && dvfsrc_success == 0) {
+ dramc_crit("[DDR Reserve] DRAM content might be corrupted -> clear g_ddr_reserve_success\n");
+ g_ddr_reserve_success = 0;
+
+ if (dvfsrc_en == 1 && dvfsrc_success == 0) {
+ dramc_crit("[DDR Reserve] DVFSRC fail!\n");
+#if 0//def LAST_DRAMC
+ dram_fatal_set_dvfsrc_err();
+#endif
+ }
+ } else {
+ dramc_crit("[DDR Reserve] DCS/DVFSRC success! (dvfsrc_en=%d)\n", dvfsrc_en);
+ }
+ /* release dram, no matter success or failed */
+ release_dram();
+ }
+ else
+ {
+ dramc_crit("[DDR Reserve] ddr reserve mode not be enabled yet\n");
+ g_ddr_reserve_enable = 0;
+ }
+#endif
+}
+
+unsigned int DRAM_MRR(int MRR_num)
+{
+ u16 MRR_value = 0x0;
+ DRAMC_CTX_T *p = psCurrDramCtx;
+
+ DramcModeRegRead(p, MRR_num, &MRR_value);
+ return MRR_value;
+}
+
+static int mt_get_dram_type_for_dis(void)
+{
+ return mt_get_dram_type_from_hw_trap();
+}
+
+#ifndef DRAM_ADAPTIVE
+#ifdef COMBO_MCP
+static char id[22];
+static int enable_combo_dis = 0;
+static int emmc_nand_id_len=8;
+static int fw_id_len;
+static int mt_get_mdl_number(void)
+{
+ static int found = 0;
+ static int mdl_number = -1;
+ int i;
+ int j;
+ int has_emmc_nand = 0;
+ int discrete_dram_num = 0;
+ int mcp_dram_num = 0;
+ u64 rank0_size=0, rank1_size=0;
+
+ extern int platform_get_mcp_id(u8 *id, u32 len, u32 *fw_id_len);
+ unsigned int dram_type;
+ DRAM_INFO_BY_MRR_T DramInfo;
+ DRAM_DRAM_TYPE_T Dis_DramType;
+ DRAM_CBT_MODE_EXTERN_T DramMode;
+
+ if (!(found)) {
+ int result=0;
+
+ for (i = 0 ; i < num_of_emi_records; i++) {
+ if ((emi_settings[i].type & 0x0F00) == 0x0000)
+ discrete_dram_num ++;
+ else
+ mcp_dram_num ++;
+ }
+
+ /*If the number >=2 &&
+ * one of them is discrete DRAM
+ * enable combo discrete dram parse flow
+ * */
+ if ((discrete_dram_num > 0) && (num_of_emi_records >= 2))
+ enable_combo_dis = 1;
+
+ dramc_crit("[EMI] mcp_dram_num:%d,discrete_dram_num:%d,enable_combo_dis:%d\r\n",mcp_dram_num,discrete_dram_num,enable_combo_dis);
+
+ Dis_DramType = mt_get_dram_type_for_dis();
+ /* resetting dram type */
+ if (Dis_DramType == TYPE_LPDDR2)
+ Dis_DramType = TYPE_LPDDR3;
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+ if (!u1IsLP4Family(Dis_DramType) || read_offline_dram_mdl_data(&DramInfo)) {
+#endif
+ if (u1IsLP4Family(Dis_DramType))
+ DramMode = CBT_BYTE_MODE1;
+ else
+ DramMode = CBT_NORMAL_MODE;
+
+ Init_DRAM(Dis_DramType, DramMode, &DramInfo, GET_MDL_USED);
+ DramInfo.u2MR5VendorID &= 0xFF;
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+ if (u1IsLP4Family(Dis_DramType))
+ write_offline_dram_mdl_data(&DramInfo);
+ }
+#endif
+
+
+ if (u1IsLP4Family(Dis_DramType)) {
+ rank0_size = (u64) DramInfo.u8MR8Density[1][0]; //now only K CHB to save time
+ rank1_size = (u64) DramInfo.u8MR8Density[1][1]; //now only K CHB to save time
+ } else {
+ rank0_size = (u64) DramInfo.u8MR8Density[0][0]; //now only K CHA to save time
+ rank1_size = (u64) DramInfo.u8MR8Density[0][1]; //now only K CHA to save time
+ }
+
+ /*
+ *
+ * 0. if there is only one discrete dram, use index=0 emi setting and boot it.
+ * */
+ if ((0 == mcp_dram_num) && (1 == discrete_dram_num)) {
+ mdl_number = 0;
+ found = 1;
+
+ //K first frequency (1066MHz)
+
+ return mdl_number;
+ }
+
+ /* 1.
+ * if there is MCP dram in the list, we try to find emi setting by emmc ID
+ * */
+ if (mcp_dram_num > 0) {
+ result = platform_get_mcp_id(id, emmc_nand_id_len,&fw_id_len);
+ for (i = 0; i < num_of_emi_records; i++) {
+ if ((emi_settings[i].type & 0xF) != Dis_DramType)
+ continue;
+
+ if (emi_settings[i].type != 0) {
+ if ((emi_settings[i].type & 0xF00) != 0x000) {
+ /* valid ID */
+ if (result == 0
+#if 0//SUPPORT_SAVE_TIME_FOR_CALIBRATION
+ && (emi_settings[i].DRAM_RANK_SIZE[0] == rank0_size) &&
+ (emi_settings[i].DRAM_RANK_SIZE[1] == rank1_size)
+#endif
+ ) {
+ if ((emi_settings[i].type & 0xF00) == 0x200) {
+ /* eMMC */
+ if (memcmp(id, emi_settings[i].ID, emi_settings[i].id_length) == 0) {
+ mdl_number = i;
+ found = 1;
+ break;
+ } else {
+ dramc_crit("[MDL] index(%d) emmc id match failed\n",i);
+ }
+ }
+ else if ((emi_settings[i].type & 0xF00) == 0x100)
+ {
+ /* nand */
+ if (memcmp(id, emi_settings[i].ID, emi_settings[i].id_length) == 0){
+ mdl_number = i;
+ found = 1;
+ break;
+ } else {
+ dramc_crit("[MDL] index(%d) nand id match failed\n",i);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* 2. find emi setting by MODE register 5
+ * */
+ // if we have found the index from by eMMC ID checking, we can boot android by the setting
+ // if not, we try by vendor ID
+ if ((0 == found) && (1 == enable_combo_dis))
+ {
+ EMI_SETTINGS *emi_set;
+
+ // try to find discrete dram by MR5 (vendor ID)
+ for (i = 0; i < num_of_emi_records; i++) {
+ dramc_crit("[MDL]index:%d, MR5:%x, type:%x, vender_id:%x\n", i, emi_settings[i].iLPDDR3_MODE_REG_5, emi_settings[i].type, DramInfo.u2MR5VendorID);
+ // only check discrete dram type
+ if ((emi_settings[i].type & 0xF) == Dis_DramType && (emi_settings[i].type & 0x0F00) == 0x0000) {
+ // support for combo discrete dram
+ if (emi_settings[i].iLPDDR3_MODE_REG_5 == DramInfo.u2MR5VendorID) {
+ dramc_debug("[MDL] index:%d, rank0_size:0x%llx(0x%llx), rank1_size:0x%llx(0x%llx)\n", i,
+ rank0_size, emi_settings[i].DRAM_RANK_SIZE[0],
+ rank1_size, emi_settings[i].DRAM_RANK_SIZE[1]);
+ if((emi_settings[i].DRAM_RANK_SIZE[0] == rank0_size) && (emi_settings[i].DRAM_RANK_SIZE[1] == rank1_size)) {
+ mdl_number = i;
+ found = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ dramc_crit("found:%d,i:%d\n",found,i);
+ }
+
+ return mdl_number;
+}
+#endif
+
+int get_dram_channel_nr(void)
+{
+ int channel_nr;
+
+ channel_nr = (*((volatile unsigned int*)(EMI_CONA)) >> 8) & 0x3;
+
+ return (0x1 << channel_nr);
+}
+
+int get_dram_rank_nr(void)
+{
+ int emi_cona;
+
+#ifdef COMBO_MCP
+ int index;
+#ifdef DDR_RESERVE_MODE
+ if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+ {
+ emi_cona = *(volatile unsigned int*)(EMI_CONA);
+ }
+ else
+#endif
+ {
+ index = mt_get_mdl_number();
+ if (index < 0 || index >= num_of_emi_records)
+ {
+ return -1;
+ }
+
+ emi_cona = emi_settings[index].EMI_CONA_VAL;
+ }
+#else
+ emi_cona = default_emi_setting.EMI_CONA_VAL;
+#if CFG_FPGA_PLATFORM
+ return 1;
+#endif
+#endif
+
+ if ((emi_cona & (1 << 17)) != 0 || //for channel 0
+ (emi_cona & (1 << 16)) != 0 ) //for channel 1
+ return 2;
+ else
+ return 1;
+}
+
+unsigned int get_dram_mr(unsigned int index)
+{
+ switch (index) {
+ case 5:
+ return mr5;
+ default:
+ return 0;
+ }
+}
+
+void get_dram_rank_size_by_EMI_CONA (u64 dram_rank_size[])
+{
+ unsigned col_bit, row_bit;
+ u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size;
+#ifndef COMBO_MCP
+ unsigned emi_cona = default_emi_setting.EMI_CONA_VAL;
+ unsigned emi_conh = default_emi_setting.EMI_CONH_VAL;
+#else
+ unsigned emi_cona = *(volatile unsigned int*)(EMI_CONA);
+ unsigned emi_conh = *(volatile unsigned int*)(EMI_CONH);
+#endif
+ unsigned nr_chan_enabled = 1;
+ u64 per_chan_rank0_size = 0, per_chan_rank1_size = 0;
+ unsigned shift_for_16bit = 1; // data width = 2 bytes
+
+ if (emi_cona & 0x2)
+ shift_for_16bit = 0; // data width = 4 bytes
+
+ dram_rank_size[0] = 0;
+ dram_rank_size[1] = 0;
+
+ ch0_rank0_size = (emi_conh >> 16) & 0xf;
+ ch0_rank1_size = (emi_conh >> 20) & 0xf;
+ ch1_rank0_size = (emi_conh >> 24) & 0xf;
+ ch1_rank1_size = (emi_conh >> 28) & 0xf;
+
+ switch ((emi_cona >> 8) & 0x3) {
+ case 0:
+ nr_chan_enabled = 1;
+ break;
+ case 1:
+ nr_chan_enabled = 2;
+ break;
+ case 2:
+ nr_chan_enabled = 4;
+ break;
+ case 3:
+ default:
+ dramc_crit("invalid CHN_EN field in EMI_CONA (0x%x)\n", emi_cona);
+ // assume 4 channel by default
+ nr_chan_enabled = 2;
+ break;
+ }
+
+ // CH0 EMI
+ {
+ if(ch0_rank0_size == 0)
+ {
+ //rank 0 setting
+ col_bit = ((emi_cona >> 4) & 0x03) + 9;
+ row_bit = ((((emi_cona >> 24) & 0x01) << 2) + ((emi_cona >> 12) & 0x03)) + 13;
+ per_chan_rank0_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
+ }
+ else
+ {
+ per_chan_rank0_size = (ch0_rank0_size * 256 << 20);
+ }
+
+ if (0 != (emi_cona & (1 << 17))) //rank 1 exist
+ {
+ if(ch0_rank1_size == 0)
+ {
+ col_bit = ((emi_cona >> 6) & 0x03) + 9;
+ row_bit = ((((emi_cona >> 25) & 0x01) << 2) + ((emi_cona >> 14) & 0x03)) + 13;
+ per_chan_rank1_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
+ }
+ else
+ {
+ per_chan_rank1_size = (ch0_rank1_size * 256 << 20);
+ }
+ }
+
+ if (nr_chan_enabled > 2) {
+ // CH0 EMI have CHA+CHB
+ dram_rank_size[0] = per_chan_rank0_size * 2;
+ dram_rank_size[1] = per_chan_rank1_size * 2;
+ } else {
+ // CH0 EMI is CHA
+ dram_rank_size[0] = per_chan_rank0_size;
+ dram_rank_size[1] = per_chan_rank1_size;
+ }
+ }
+
+ // CH1 EMI
+ if(nr_chan_enabled >= 2)
+ {
+ if(ch1_rank0_size == 0)
+ {
+ //rank0 setting
+ col_bit = ((emi_cona >> 20) & 0x03) + 9;
+ row_bit = ((((emi_conh >> 4) & 0x01) << 2) + ((emi_cona >> 28) & 0x03)) + 13;
+ per_chan_rank0_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
+ }
+ else
+ {
+ per_chan_rank0_size = (ch1_rank0_size * 256 << 20);
+ }
+
+ if (0 != (emi_cona & (1 << 16))) //rank 1 exist
+ {
+ if(ch1_rank1_size == 0)
+ {
+ col_bit = ((emi_cona >> 22) & 0x03) + 9;
+ row_bit = ((((emi_conh >> 5) & 0x01) << 2) + ((emi_cona >> 30) & 0x03)) + 13;
+ per_chan_rank1_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
+ }
+ else
+ {
+ per_chan_rank1_size = (ch1_rank1_size * 256 << 20);
+ }
+ }
+ if (nr_chan_enabled > 2) {
+ // CH1 EMI have CHC+CHD
+ dram_rank_size[0] += per_chan_rank0_size * 2;
+ dram_rank_size[1] += per_chan_rank1_size * 2;
+ } else {
+ // CH1 EMI is CHB
+ dram_rank_size[0] += per_chan_rank0_size;
+ dram_rank_size[1] += per_chan_rank1_size;
+ }
+ }
+
+ //dramc_debug("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n", dram_rank_size[0], dram_rank_size[1]);
+}
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if !__FLASH_TOOL_DA__ && !__ETT__
+void get_dram_rank_size(u64 dram_rank_size[])
+{
+#ifdef COMBO_MCP
+ int index, rank_nr, i;
+
+#ifdef DDR_RESERVE_MODE
+ if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+ {
+ get_dram_rank_size_by_EMI_CONA(dram_rank_size);
+ }
+ else
+#endif
+ {
+ index = mt_get_mdl_number();
+
+ if (index < 0 || index >= num_of_emi_records)
+ {
+ return;
+ }
+
+ rank_nr = get_dram_rank_nr();
+
+ for(i = 0; i < rank_nr; i++){
+ dram_rank_size[i] = emi_settings[index].DRAM_RANK_SIZE[i];
+
+ dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
+ }
+ }
+ return;
+#else
+ get_dram_rank_size_by_EMI_CONA(dram_rank_size);
+ return;
+#endif
+}
+
+void reserve_dramc_dummy_read(void)
+{
+#if 0//def LAST_DRAMC
+ unsigned long long reserve_start;
+ char *reserve_name[4] = {"dramc-rk0", "dramc-rk1", "dramc-rk2", "dramc-rk3"};
+ unsigned int i;
+ int rank_nr;
+ dram_addr_t dram_addr;
+
+ dram_addr.ch = 0;
+
+ rank_nr = get_dram_rank_nr();
+ if (rank_nr <= 0) {
+ dramc_crit("[DRAMC] reserve dummy read fail\n");
+ ASSERT(0);
+ }
+
+ for (i = 0; i < (unsigned int)rank_nr; i++) {
+ dram_addr.rk = i;
+ get_dramc_addr(&dram_addr, 0x0);
+#ifdef CUSTOM_CONFIG_MAX_DRAM_SIZE
+ if (dram_addr.full_sys_addr > (unsigned long long)CUSTOM_CONFIG_MAX_DRAM_SIZE + 0x40000000LL)
+ break;
+#endif
+ reserve_start = mblock_reserve_ext(&bootarg.mblock_info, 0x1000, 0x1000, dram_addr.full_sys_addr, 0, reserve_name[i]);
+ if (reserve_start != (dram_addr.full_sys_addr - 0x1000)) {
+ dramc_crit("[DRAMC] dummy read fail (0x%llx)\n", reserve_start);
+ ASSERT(0);
+ }
+ }
+#endif
+}
+#endif //#if !__FLASH_TOOL_DA__ && !__ETT__
+#endif
+#endif //DRAM_ADAPTIVE
+
+#ifdef DRAM_ADAPTIVE
+void get_rank_size_by_emi(u64 dram_rank_size[]);
+int get_dram_channel_nr(void)
+{
+ int channel_nr;
+
+ channel_nr = (*((volatile unsigned int*)(EMI_CONA)) >> 8) & 0x3;
+
+ return (0x1 << channel_nr);
+}
+
+int get_rank_nr_by_emi(void)
+{
+ unsigned int cen_emi_cona = *(volatile unsigned int*)(EMI_CONA);
+
+ if (cen_emi_cona & (0x3 << 16))
+ return 2;
+ else
+ return 1;
+}
+
+int get_dram_rank_nr(void)
+{
+ int cen_emi_cona;
+
+#ifdef DDR_RESERVE_MODE
+ if (g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+ return get_rank_nr_by_emi();
+#endif
+
+#ifdef DRAM_ADAPTIVE
+ if (!auto_detect_done)
+ ASSERT(0);
+#endif
+
+ cen_emi_cona = g_default_emi_setting.EMI_CONA_VAL;
+
+ if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0
+ (cen_emi_cona & (1 << 16)) != 0 ) //for channel 1
+ return 2;
+ else
+ return 1;
+}
+
+void get_rank_size_by_emi(u64 dram_rank_size[])
+{
+ int i;
+ unsigned int quad_ch_ratio;
+ unsigned int col_bit, row_bit;
+ unsigned long long ch0_rank0_size, ch0_rank1_size;
+ unsigned long long ch1_rank0_size, ch1_rank1_size;
+ unsigned int cen_emi_conh = *(volatile unsigned int*)(EMI_CONH);
+ unsigned long long dq_width;
+
+ switch (mt_get_dram_type_from_hw_trap()) {
+ case TYPE_LPDDR4X:
+ case TYPE_LPDDR2:
+ dq_width = 1;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ dram_rank_size[0] = 0;
+ dram_rank_size[1] = 0;
+
+ ch0_rank0_size = (cen_emi_conh >> 16) & 0xF;
+ ch0_rank1_size = (cen_emi_conh >> 20) & 0xF;
+ ch1_rank0_size = (cen_emi_conh >> 24) & 0xF;
+ ch1_rank1_size = (cen_emi_conh >> 28) & 0xF;
+
+ quad_ch_ratio = (get_rank_nr_by_emi() == 4)? 2 : 1;
+ ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28;
+ ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28;
+ ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28;
+ ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28;
+
+ if(ch0_rank0_size == 0) {
+ dramc_crit("[EMI] undefined CONH for CH0 RANK0\n");
+ ASSERT(0);
+ }
+ dram_rank_size[0] += ch0_rank0_size;
+
+ if (get_rank_nr_by_emi() > 1) {
+ if(ch0_rank1_size == 0) {
+ dramc_crit("[EMI] undefined CONH for CH0 RANK1\n");
+ ASSERT(0);
+ }
+ dram_rank_size[1] += ch0_rank1_size;
+ }
+
+ if(get_dram_channel_nr() > 1) {
+ if(ch1_rank0_size == 0) {
+ dramc_crit("[EMI] undefined CONH for CH1 RANK0\n");
+ ASSERT(0);
+ }
+ dram_rank_size[0] += ch1_rank0_size;
+
+ if (get_rank_nr_by_emi() > 1) {
+ if(ch1_rank1_size == 0) {
+ dramc_crit("[EMI] undefined CONH for CH1 RANK1\n");
+ ASSERT(0);
+ }
+ dram_rank_size[1] += ch1_rank1_size;
+ }
+ }
+
+ dramc_crit("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n",
+ dram_rank_size[0], dram_rank_size[1]);
+}
+
+
+unsigned int get_dram_mr(unsigned int index)
+{
+ switch (index) {
+ case 5:
+ return mr5;
+ default:
+ return 0;
+ }
+}
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if !__FLASH_TOOL_DA__ && !__ETT__
+void get_dram_rank_size(u64 dram_rank_size[])
+{
+ int rank_nr, i;
+
+#ifdef DDR_RESERVE_MODE
+ if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+ return get_rank_size_by_emi(dram_rank_size);
+#endif
+
+#ifdef DRAM_ADAPTIVE
+ if (!auto_detect_done)
+ ASSERT(0);
+#endif
+
+ rank_nr = get_dram_rank_nr();
+
+ for(i = 0; i < rank_nr; i++) {
+ dram_rank_size[i] = g_default_emi_setting.DRAM_RANK_SIZE[i];
+ dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
+ }
+}
+
+#endif //#if !__FLASH_TOOL_DA__ && !__ETT__
+#endif
+
+static int update_dram_setting(EMI_SETTINGS *default_emi_setting, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
+{
+ default_emi_setting->type = dram_type;
+
+ if (dram_info != NULL) {
+ default_emi_setting->DRAM_RANK_SIZE[0] = (u64)(dram_info->u8MR8Density[0][0] + dram_info->u8MR8Density[1][0]);
+ default_emi_setting->DRAM_RANK_SIZE[1] = (u64)(dram_info->u8MR8Density[1][0] + dram_info->u8MR8Density[1][1]);
+
+ default_emi_setting->iLPDDR3_MODE_REG_5 = dram_info->u2MR5VendorID;
+
+ if (dram_info->u4RankNum == 1) { // single rank
+ if (dram_info->u1DieNum[RANK_0] == 1)
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
+ else if (dram_info->u1DieNum[RANK_0] == 2)
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
+ else
+ return -1;
+ } else if (dram_info->u4RankNum == 2) { // dual rank
+ if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 1))
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
+ else if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 2))
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
+ else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 1))
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
+ else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 2))
+ default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
+ else
+ return -2;
+ } else
+ return -3;
+ } else
+ return -4;
+
+ return 0;
+}
+
+int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info)
+{
+ unsigned int ddr_type;
+ unsigned int cen_cona_val, cen_conf_val, cen_conh_val;
+ unsigned int chn_cona_val;
+ unsigned int cen_conf_shf;
+ unsigned int col, row, row_ext, rk_size, rk_size_ext, rk_size_chn_ext;
+ unsigned int temp_val;
+ int i;
+
+ ddr_type = default_emi_setting->type & 0xFF;
+ cen_conh_val = 0x00000003;
+ if (u1IsLP4Family(ddr_type)) {
+ cen_cona_val = 0x00000004;
+ chn_cona_val = 0x04000000;
+ } else {
+ cen_cona_val = 0x00000006;
+ if (emi_info->bank_width[0] == 3)
+ chn_cona_val = 0x00000002;
+ else
+ chn_cona_val = 0x03000002;
+ }
+
+ for (i = 0; i < emi_info->rk_num; i++) {
+ row = emi_info->row_width[i] - 13;
+ row_ext = row >> 2;
+ row &= 0x3;
+
+ col = emi_info->col_width[i] - 9;
+
+ rk_size = emi_info->rank_size[i] >> 28;
+ if (u1IsLP4Family(ddr_type))
+ rk_size >>= 1;
+ rk_size_ext = rk_size >> 4;
+ rk_size_chn_ext = rk_size_ext & 0x1;
+ rk_size &= 0xF;
+
+ if (i == 1) {
+ col <<= 2;
+ row <<= 2;
+ row_ext <<= 1;
+ rk_size <<= 4;
+ rk_size_ext <<= 4;
+ rk_size_chn_ext <<= 1;
+ cen_cona_val |= 0x00030000;
+ chn_cona_val |= 0x00000001;
+ }
+
+ cen_cona_val |=
+ (col << 4) | (row << 12) | (col << 20) |
+ (row_ext << 24) | (row << 28);
+ cen_conh_val |=
+ (row_ext << 4) | (rk_size << 16);
+ chn_cona_val |=
+ (row_ext << 2) | (col << 4) | (row << 12) |
+ (rk_size << 16) | (rk_size_chn_ext << 8);
+ }
+
+ cen_conf_shf = 0;
+ for (i = 0; i < emi_info->rk_num; i++) {
+ temp_val = 2 + emi_info->col_width[i];
+ if (cen_conf_shf < temp_val)
+ cen_conf_shf = temp_val;
+ }
+ if (u1IsLP4Family(ddr_type))
+ cen_conf_val = 0x421 << ((cen_conf_shf - 9) * 4);
+ else
+ {
+ if (emi_info->bank_width[0] == 3)
+ cen_conf_val = 0x421 << ((cen_conf_shf - 8) * 4);
+ else
+ cen_conf_val = 0x21 << ((cen_conf_shf - 8) * 4);
+ }
+
+ while(cen_conf_val & 0xFFF) {
+ cen_conf_val <<= 4;
+ }
+
+ dramc_crit("[EMI] %s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x)\n",
+ "CEN_CONA", cen_cona_val,
+ "CEN_CONF", cen_conf_val,
+ "CEN_CONH", cen_conh_val,
+ "CHN_CONA", chn_cona_val);
+
+ default_emi_setting->EMI_CONA_VAL = cen_cona_val;
+ default_emi_setting->EMI_CONF_VAL = cen_conf_val;
+ default_emi_setting->EMI_CONH_VAL = cen_conh_val;
+ default_emi_setting->CHN0_EMI_CONA_VAL = chn_cona_val;
+ default_emi_setting->CHN1_EMI_CONA_VAL = chn_cona_val;
+
+ return 0;
+}
+
+static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
+{
+ unsigned int i;
+ unsigned long long die_size;
+
+ emi_info->dram_type = dram_type;
+ emi_info->ch_num = 1;
+ if (dram_info->u4BankMode == BANK_TYPE_S2) {
+ emi_info->bank_width[0] = 2;
+ emi_info->bank_width[1] = 2;
+ }
+ else {
+ emi_info->bank_width[0] = 3;
+ emi_info->bank_width[1] = 3;
+ }
+ emi_info->col_width[0] = 10;
+ emi_info->col_width[1] = 10;
+
+ if (dram_info != NULL) {
+ emi_info->rank_size[0] = (u64)(dram_info->u8MR8Density[0][0] + dram_info->u8MR8Density[1][0]);
+ emi_info->rank_size[1] = (u64)(dram_info->u8MR8Density[1][0] + dram_info->u8MR8Density[1][1]);
+
+ emi_info->rk_num = dram_info->u4RankNum;
+
+ for (i = 0; i < emi_info->rk_num; i++) {
+ die_size = emi_info->rank_size[i] / dram_info->u1DieNum[i];
+ switch (die_size | (dram_info->u1DieNum[i] << 4) | u1IsLP4Family(dram_type)) {
+ case 0x20000011ULL: // 4Gb, x16, LP4
+ emi_info->row_width[i] = 14;
+ break;
+ case 0x20000021ULL: // 4Gb, x8, LP4
+ case 0x40000021ULL: // 8Gb, x8, LP4
+ case 0x30000011ULL: // 6Gb, x16, LP4
+ case 0x40000011ULL: // 8Gb, x16, LP4
+ emi_info->row_width[i] = 15;
+ break;
+ case 0x30000021ULL: // 6Gb, x8, LP4
+ case 0x60000011ULL: // 12Gb, x16, LP4
+ case 0x80000011ULL: // 16Gb, x16, LP4
+ emi_info->row_width[i] = 16;
+ break;
+ case 0x060000021ULL: // 12Gb, x8, LP4
+ case 0x080000021ULL: // 16Gb, x8, LP4
+ case 0x0C0000011ULL: // 24Gb, x16, LP4
+ case 0x100000011ULL: // 32Gb, x16, LP4
+ emi_info->row_width[i] = 17;
+ break;
+ case 0x0C0000021ULL: // 24Gb, x8, LP4
+ case 0x100000021ULL: // 32Gb, x8, LP4
+ emi_info->row_width[i] = 18;
+ break;
+ //FOR LP2 Decode
+ #if 0
+ case 0x800010ULL: // 64Mb, x32, LP2
+ emi_info->col_width[i] = 7;
+ emi_info->row_width[i] = 12;
+ emi_info->bank_width[i] = 2;
+ break;
+ case 0x800020ULL: // 64Mb, x16, LP2
+ case 0x1000010ULL: // 128Mb, x32, LP2
+ emi_info->col_width[i] = 8;
+ emi_info->row_width[i] = 12;
+ emi_info->bank_width[i] = 2;
+ break;
+ case 0x1000020ULL: // 128Mb, x16, LP2
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 12;
+ emi_info->bank_width[i] = 2;
+ break;
+ case 0x2000010ULL: // 256Mb, x32, LP2
+ emi_info->col_width[i] = 8;
+ emi_info->row_width[i] = 13;
+ emi_info->bank_width[i] = 2;
+ break;
+ case 0x2000020ULL: // 256Mb, x16, LP2
+ case 0x4000010ULL: // 512Mb, x32, LP2
+ emi_info->bank_width[i] = 2;
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 13;
+ break;
+ case 0x4000020ULL: // 512Mb, x16, LP2
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 13;
+ emi_info->bank_width[i] = 2;
+ break;
+ #endif
+ case 0x8000010ULL: // 1Gb, x32, LP2
+ if (dram_info->u4BankMode == BANK_TYPE_S2) {
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 14;
+ } else {
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 13;
+ }
+ break;
+ case 0x8000020ULL: // 1Gb, x16, LP2
+ if (dram_info->u4BankMode == BANK_TYPE_S2) {
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 14;
+ } else {
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 13;
+ }
+ break;
+ case 0x10000010ULL: // 2Gb, x32, LP2
+ if (dram_info->u4BankMode == BANK_TYPE_S2) {
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 15;
+ } else {
+ emi_info->col_width[i] = 9;
+ emi_info->row_width[i] = 14;
+ }
+ break;
+ case 0x10000020ULL: // 2Gb, x16, LP2
+ if (dram_info->u4BankMode == BANK_TYPE_S2) {
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 15;
+ } else {
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 14;
+ }
+ break;
+ case 0x20000010ULL: // 4Gb, x32, LP2
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 14;
+ break;
+ case 0x20000020ULL: // 4Gb, x16, LP2
+ emi_info->col_width[i] = 11;
+ emi_info->row_width[i] = 14;
+ break;
+ case 0x40000010ULL: // 8Gb, x32, LP2
+ emi_info->col_width[i] = 10;
+ emi_info->row_width[i] = 15;
+ break;
+ case 0x40000020ULL: // 8Gb, x16, LP2
+ emi_info->col_width[i] = 11;
+ emi_info->row_width[i] = 15;
+ break;
+ default:
+ return -1;
+ }
+ }
+ } else
+ return -1;
+
+ return 0;
+}
+#endif
+
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if !__ETT__
+#ifdef DRAM_ADAPTIVE
+void dram_auto_detection(void)
+{
+ DRAM_INFO_BY_MRR_T dram_info = {0};
+ EMI_INFO_T emi_info = {0};
+ DRAM_CBT_MODE_EXTERN_T dram_mode;
+ unsigned int dram_type;
+ int ret;
+
+ dram_type = (unsigned int)mt_get_dram_type_for_dis();
+ if (dram_type == TYPE_LPDDR2)
+ dram_type = TYPE_LPDDR3;
+ g_default_emi_setting.type &= ~0xFF;
+ g_default_emi_setting.type |= (dram_type & 0xFF);
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+ if (!u1IsLP4Family(dram_type) ||
+ read_offline_dram_mdl_data(&dram_info) < 0) {
+#endif
+ dram_mode = (u1IsLP4Family(dram_type))?
+ CBT_BYTE_MODE1 : CBT_NORMAL_MODE;
+
+ dramc_crit("[DRAMC] Init_DRAM GET_MDL_USED start\n");
+ Init_DRAM(dram_type, dram_mode, &dram_info, GET_MDL_USED);
+ dramc_crit("[DRAMC] Init_DRAM GET_MDL_USED end\n");
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+ if (u1IsLP4Family(dram_type))
+ write_offline_dram_mdl_data(&dram_info);
+ }
+#endif
+
+
+ ret = update_dram_setting(&g_default_emi_setting, dram_type, &dram_info);
+ if (ret) {
+ dramc_crit("[DRAMC] update_dram_setting err %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = decode_emi_info(&emi_info, dram_type, &dram_info);
+ if (ret) {
+ dramc_crit("[DRAMC] decode_emi_info err %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = update_emi_setting(&g_default_emi_setting, &emi_info);
+ if (ret) {
+ dramc_crit("[DRAMC] update_emi_setting err %d\n", ret);
+ ASSERT(0);
+ }
+
+ auto_detect_done = 1;
+}
+#endif
+
+void mt_set_emi(void)
+{
+ /*unsigned int SW_CTRL_VC, HW_CTRL_VC;*/
+ EMI_SETTINGS *emi_set;
+
+ // set voltage and hw trapping before mdl
+ setup_dramc_voltage_by_pmic();
+
+#ifdef VCORE_BIN
+ dvfsrc_opp_level_mapping();
+#endif
+
+#ifndef DRAM_ADAPTIVE
+#ifdef COMBO_MCP
+ int index;
+
+ index = mt_get_mdl_number();
+ dramc_crit("[EMI] MDL number = %d\r\n", index);
+ if (index < 0 || index >= num_of_emi_records)
+ {
+ dramc_crit("[EMI] setting failed 0x%x\r\n", index);
+ ASSERT(0);
+ }
+ else
+ {
+ emi_setting_index = index;
+ emi_set = &emi_settings[emi_setting_index];
+ }
+#else
+ dramc_crit("[EMI] ComboMCP not ready, using default setting\n");
+ emi_setting_index = -1;
+ emi_set = &default_emi_setting;
+#endif
+ mr5 = emi_set->iLPDDR3_MODE_REG_5;
+#else
+ dram_auto_detection();
+ emi_set = &g_default_emi_setting;
+#endif
+
+#ifdef DDR_RESERVE_MODE
+ if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==0)
+ Before_Init_DRAM_While_Reserve_Mode_fail(emi_set->type & 0xF);
+#endif
+
+ Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
+ switch_dramc_voltage_to_auto_mode();
+ restore_vcore_setting();
+
+#if 0
+ {
+ DRAMC_CTX_T * p = psCurrDramCtx;
+ DramcRegDump(p);
+ }
+#endif
+}
+#endif
+#endif
+
+#define DRAMC_ADDR_SHIFT_CHN(addr, channel) (addr + (channel * 0x10000))
+
+void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
+{
+ unsigned int emi_cona, emi_conf;
+ unsigned long long rank_size[4];
+ unsigned int channel_num, rank_num;
+ unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width;
+ unsigned int temp;
+ unsigned int index;
+ unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
+
+ emi_cona = *((volatile unsigned int *)EMI_CONA);
+ emi_conf = *((volatile unsigned int *)EMI_CONF) >> 8;
+ #ifdef DRAM_ADAPTIVE
+ get_rank_size_by_emi(rank_size);
+ #else
+ get_dram_rank_size_by_EMI_CONA(rank_size);
+ #endif
+ rank_num = (unsigned int) get_dram_rank_nr();
+ channel_num = (unsigned int) get_dram_channel_nr();
+
+ if (rank_num >= sizeof(rank_size) / sizeof(*rank_size)) {
+ dramc_crit("[Dramc] Wrong rank_num: %u\n", rank_num);
+ ASSERT(0);
+ }
+
+ phy_addr -= 0x40000000;
+ for (index = 0; index < rank_num; index++) {
+ if (phy_addr >= rank_size[index])
+ phy_addr -= rank_size[index];
+ else
+ break;
+ }
+
+ for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
+ bit_xor = (emi_conf >> (4 * (bit_scramble - 11))) & 0xf;
+ bit_xor &= phy_addr >> 16;
+ for (bit_shift = 0; bit_shift < 4; bit_shift++)
+ phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble;
+ }
+
+ if (channel_num > 1) {
+ channel_pos = ((emi_cona >> 2) & 0x3) + 7;
+
+ for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) {
+ if ((unsigned int)(1 << bit_shift) >= channel_num)
+ break;
+ channel_width++;
+ }
+
+ switch (channel_width) {
+ case 2:
+ dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2);
+ break;
+ default:
+ dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1);
+ break;
+ }
+ dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1));
+ } else {
+ dram_addr->addr = phy_addr;
+ }
+
+ if (u1IsLP4Family(ddr_type))
+ dram_addr->addr >>= 1;
+ else
+ dram_addr->addr >>= 2;
+
+ temp = dram_addr->addr;
+ switch ((emi_cona >> 4) & 0x3) {
+ case 0:
+ dram_addr->col = temp & 0x1FF;
+ temp = temp >> 9;
+ break;
+ case 1:
+ dram_addr->col = temp & 0x3FF;
+ temp = temp >> 10;
+ break;
+ case 2:
+ default:
+ dram_addr->col = temp & 0x7FF;
+ temp = temp >> 11;
+ break;
+ }
+ dram_addr->bk = temp & 0x7;
+ temp = temp >> 3;
+
+ dram_addr->row = temp;
+
+ //mcSHOW_DBG_MSG(("ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr));
+ //mcSHOW_DBG_MSG(("bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col));
+}
+
+void put_dummy_read_pattern(unsigned long long dst_pa, unsigned long src_pa, unsigned int len)
+{
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x018)) = 7 << 16;
+
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x01c)) = src_pa & 0xffffffff;
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x060)) = 0;
+
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x020)) = dst_pa & 0xffffffff;
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x064)) = dst_pa >> 32;
+
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x024)) = len;
+ dsb();
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x008)) = 0x1;
+
+ while(*((volatile unsigned int *)(CQ_DMA_BASE + 0x008)));
+
+ *((volatile unsigned int *)(CQ_DMA_BASE + 0x064)) = 0;
+}
+
+static unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset)
+{
+ unsigned int channel_num, rank_num;
+ unsigned long long dummy_read_addr;
+ unsigned long long rank_size[4];
+ unsigned int index;
+ unsigned int *src_addr;
+
+ channel_num = (unsigned int) get_dram_channel_nr();
+ rank_num = (unsigned int) get_dram_rank_nr();
+ #ifdef DRAM_ADAPTIVE
+ get_rank_size_by_emi(rank_size);
+ #else
+ get_dram_rank_size_by_EMI_CONA(rank_size);
+ #endif
+ dummy_read_addr = 0x40000000;
+ src_addr = (unsigned int *) 0x40000000;
+
+ if (dram_addr->ch >= channel_num) {
+ mcSHOW_DBG_MSG(("[DRAMC] invalid channel: %d\n", dram_addr->ch));
+ return 0;
+ }
+
+ if (dram_addr->rk >= rank_num) {
+ mcSHOW_DBG_MSG(("[DRAMC] invalid rank: %d\n", dram_addr->rk));
+ return 0;
+ }
+
+ for (index = 0; index <= dram_addr->rk; index++)
+ dummy_read_addr += rank_size[index];
+ dummy_read_addr -= offset;
+ if (dram_addr->ch == 0)
+ dummy_read_addr &= ~(0x100);
+
+ if (offset == 0x20) {
+ for (index = 0; index < 4; index++)
+ *(src_addr + index) = 0xAAAA5555;
+ put_dummy_read_pattern(dummy_read_addr, (unsigned long)src_addr, 16);
+ }
+
+ dram_addr->full_sys_addr = dummy_read_addr;
+ phy_addr_to_dram_addr(dram_addr, dummy_read_addr);
+
+ return dram_addr->addr;
+}
+
+unsigned int get_dummy_read_addr(dram_addr_t *dram_addr)
+{
+ return get_dramc_addr(dram_addr, 0x20); // 32-byte align for dummy RW pattern
+}
+
+unsigned int get_ta2_addr(dram_addr_t *dram_addr)
+{
+ unsigned int addr = get_dramc_addr(dram_addr, 0x1000);
+
+ if (!u1IsLP4Family(mt_get_dram_type_from_hw_trap()))
+ addr <<= 2;
+
+ return addr & 0xFFFFFFF0;
+}
+
+void init_ta2_single_channel(unsigned int channel)
+{
+ unsigned int temp;
+ unsigned int matype[2];
+ unsigned int col_shf[2] = {0, 0};
+ dram_addr_t dram_addr;
+ DRAMC_CTX_T *p = psCurrDramCtx;
+ int rank_nr;
+
+ // mt6771: CHN0_EMI for CHN-A; CHN1_EMI for CHN-B
+ if(channel < 2) {
+ matype[0] = (*(volatile unsigned *)EMI_CONA >> 4) & 0x3;
+ matype[1] = (*(volatile unsigned *)EMI_CONA >> 6) & 0x3;
+ } else {
+ matype[0] = (*(volatile unsigned *)EMI_CONA >> 20) & 0x3;
+ matype[1] = (*(volatile unsigned *)EMI_CONA >> 22) & 0x3;
+ }
+
+ rank_nr = get_dram_rank_nr();
+ if (rank_nr > 1) {
+ if (matype[0] < matype[1]) {
+ col_shf[0] = matype[1] - matype[0];
+ matype[0] = matype[1];
+ } else if (matype[1] < matype[0])
+ col_shf[1] = matype[0] - matype[1];
+ }
+
+ matype[0] = (matype[0] + 1) << 30;
+
+ // disable self test engine1 and self test engine2
+ temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel)) & 0x1FFFFFFF;
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel), temp);
+
+ // set MATYPE
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU_CONF0, channel), temp);
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU2_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU2_CONF0, channel), temp);
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU3_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU3_CONF0, channel), temp);
+
+ if (rank_nr > 1) {
+ // set rank address for test agent to auto
+ temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_4, channel)) & 0x8FFFFFFF;
+ temp |= (0x4 << 28);
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_4, channel), temp);
+
+ // set test for both rank0 and rank1
+ temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel)) & 0xFFFFFFF0;
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel), temp | 0x1);
+ }
+
+ // set base address for test agent to reserved space
+ dram_addr.ch = channel;
+ dram_addr.rk = 0;
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_1, channel)) & 0x0000000F);
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_1, channel), temp | (get_ta2_addr(&dram_addr) << col_shf[0]));
+ dram_addr.rk = 1;
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_5, channel)) & 0x0000000F);
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_5, channel), temp | (get_ta2_addr(&dram_addr) << col_shf[1]));
+
+ // set test length (offset) to 0x20
+ temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_2, channel)) & 0x0000000F) | (0x20 << 4);
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_2, channel), temp);
+
+ return;
+}
+
+#ifdef LAST_DRAMC
+
+static unsigned int is_last_dramc_initialized(void)
+{
+ if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+void update_last_dramc_info(void)
+{
+ unsigned int chn;
+ unsigned int latch_result = 0;
+ unsigned int temp;
+ unsigned int *curr;
+ DRAMC_CTX_T *p = psCurrDramCtx;
+
+ // init checksum and magic pattern
+ if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
+ last_dramc_info_ptr->ta2_result_magic = LAST_DRAMC_MAGIC_PATTERN;
+ last_dramc_info_ptr->ta2_result_last = 0;
+ last_dramc_info_ptr->ta2_result_past = 0;
+ last_dramc_info_ptr->ta2_result_checksum = LAST_DRAMC_MAGIC_PATTERN;
+ last_dramc_info_ptr->reboot_count = 0;
+ } else {
+ last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
+ last_dramc_info_ptr->reboot_count++;
+ last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
+ }
+
+ // TODO: check DCS status
+
+ // read data from latch register and reset
+ for (chn = 0; chn < CHANNEL_NUM; ++chn) {
+ //dramc_crit("[LastDRAMC] latch result before RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+ latch_result = (latch_result << 16) | u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0xFFFF;
+ temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn));
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn), temp | 0x00000004);
+ vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn), temp & 0xFFFFFFFB);
+ //dramc_crit("[LastDRAMC] latch result after RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+ }
+
+ last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->ta2_result_past ^ latch_result;
+ last_dramc_info_ptr->ta2_result_past = last_dramc_info_ptr->ta2_result_last;
+ last_dramc_info_ptr->ta2_result_last = latch_result;
+ for (temp = 0; temp < sizeof(LAST_DRAMC_INFO_T) / sizeof(temp); temp++) {
+ curr = (unsigned int *)last_dramc_info_ptr + temp;
+ dramc_crit("[LastDRAMC] 0x%x: 0x%x\n", curr, *curr);
+ }
+
+ return;
+}
+
+void update_last_dramc_k_voltage(DRAMC_CTX_T *p, unsigned int voltage)
+{
+ unsigned int shu_type;
+
+ shu_type = get_shuffleIndex_by_Freq(p);
+
+ last_dramc_info_ptr->k_voltage[shu_type] = voltage;
+}
+
+void init_ta2_all_channel(void)
+{
+ unsigned int chn;
+
+ update_last_dramc_info();
+
+ // TODO: consider DCS
+ for (chn = 0; chn < CHANNEL_NUM; ++chn)
+ init_ta2_single_channel(chn);
+}
+
+
+unsigned int check_gating_err_in_dramc_latch(void)
+{
+ unsigned int chn, ret = 0;
+ DRAMC_CTX_T *p = psCurrDramCtx;
+
+ if (/*(g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
+ || mtk_wdt_is_pmic_full_reset() ||*/ (is_last_dramc_initialized() == 0)){
+ dramc_crit("for cold boot, always return 0\n");
+ return 0;
+ }
+
+ for (chn = 0; chn <= 3; ++chn) {
+ if (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0x80) {
+ dramc_crit("[dramc] found gating error in channel %d (0x%x)\n",
+ chn, u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+ ret |= (1 << chn);
+ }
+ }
+
+ return ret;
+}
+
+void dram_fatal_exception_detection_start(void)
+{
+ last_dramc_info_ptr = (LAST_DRAMC_INFO_T *) get_dbg_info_base(KEY_LAST_DRAMC);
+
+ if (/*(g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
+ || mtk_wdt_is_pmic_full_reset() ||*/ (is_last_dramc_initialized() == 0)){
+ /* cold boot: initialize last_dram_fatal_err_flag and dram_fatal_err_flag */
+ dramc_crit("[dramc] init SRAM region for DRAM exception detection\n");
+ last_dramc_info_ptr->last_fatal_err_flag = 0x0;
+ last_dramc_info_ptr->storage_api_err_flag = 0x0;
+ dram_fatal_init_stberr();
+ } else {
+ last_dramc_info_ptr->last_fatal_err_flag = last_dramc_info_ptr->fatal_err_flag;
+ last_dramc_info_ptr->storage_api_err_flag = 0x0;
+ dram_fatal_backup_stberr();
+ dram_fatal_init_stberr();
+ }
+
+ last_dramc_info_ptr->fatal_err_flag = 1 << OFFSET_DRAM_FATAL_ERR;
+ dsb();
+}
+
+void dram_fatal_exception_detection_end(void)
+{
+ last_dramc_info_ptr->fatal_err_flag = 0x0;
+ dsb();
+}
+
+unsigned int check_dram_fatal_exception(void)
+{
+ dramc_crit("[dramc] DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->fatal_err_flag);
+
+ return ((last_dramc_info_ptr->fatal_err_flag & ~((1 << OFFSET_DRAM_FATAL_ERR)|DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
+}
+
+unsigned int check_last_dram_fatal_exception(void)
+{
+ dramc_crit("[dramc] LAST_DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->last_fatal_err_flag);
+
+ return ((last_dramc_info_ptr->last_fatal_err_flag & ~(DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
+}
+
+void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code)
+{
+ unsigned int shift = OFFSET_DRAM_TA2_ERR + 2 * chn, ret;
+
+ if (chn > 3)
+ return;
+
+ ret = last_dramc_info_ptr->fatal_err_flag & ~(0x7 << shift);
+ last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0x7) << shift);
+ dsb();
+}
+
+void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code)
+{
+ unsigned int shift = OFFSET_DRAM_GATING_ERR + 4 * chn, ret;
+
+ if (chn > 3)
+ return;
+
+ ret = last_dramc_info_ptr->fatal_err_flag & ~(0xf << shift);
+ last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0xf) << shift);
+ dsb();
+}
+
+void dram_fatal_init_stberr(void)
+{
+ last_dramc_info_ptr->gating_err[0][0] = 0x0;
+ last_dramc_info_ptr->gating_err[0][1] = 0x0;
+ last_dramc_info_ptr->gating_err[1][0] = 0x0;
+ last_dramc_info_ptr->gating_err[1][1] = 0x0;
+
+ dsb();
+}
+
+void dram_fatal_backup_stberr(void)
+{
+ last_dramc_info_ptr->last_gating_err[0][0] = last_dramc_info_ptr->gating_err[0][0];
+ last_dramc_info_ptr->last_gating_err[0][1] = last_dramc_info_ptr->gating_err[0][1];
+ last_dramc_info_ptr->last_gating_err[1][0] = last_dramc_info_ptr->gating_err[1][0];
+ last_dramc_info_ptr->last_gating_err[1][1] = last_dramc_info_ptr->gating_err[1][1];
+
+ dsb();
+}
+
+void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code)
+{
+ if ((chn > 1) || (rk > 1))
+ return;
+
+ last_dramc_info_ptr->gating_err[chn][rk] = err_code;
+
+ dsb();
+}
+
+void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset)
+{
+ unsigned int ret;
+
+ ret = last_dramc_info_ptr->fatal_err_flag & ~(mask << offset);
+ last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & mask) << offset);
+ dsb();
+}
+
+#endif
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+
+#if !__ETT__
+#include <lib/bio.h>
+//#include <partition.h>
+#include <pl_version.h>
+#endif
+
+u32 g_dram_storage_api_err_code;
+
+static u16 crc16(const u8* data, u32 length){
+ u8 x;
+ u16 crc = 0xFFFF;
+
+ while (length--) {
+ x = crc >> 8 ^ *data++;
+ x ^= x >> 4;
+ crc = (crc << 8) ^ ((u8)(x << 12)) ^ ((u8)(x <<5)) ^ ((u8)x);
+ }
+ return crc;
+}
+
+static void assign_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
+{
+ /* need to initialize checksum to 0 before calculation */
+ shu_data->checksum = 0;
+ shu_data->checksum = crc16((u8*)shu_data, sizeof(*shu_data));
+}
+
+static int check_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
+{
+ u16 checksum_in_storage = shu_data->checksum;
+
+ assign_checksum_for_dram_data(shu_data);
+
+ return (shu_data->checksum == checksum_in_storage) ? 1 : 0;
+}
+
+#ifdef COMBO_MCP
+static void assign_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
+{
+ /* need to initialize checksum to 0 before calculation */
+ mrr_info->checksum = 0;
+ mrr_info->checksum = crc16((u8*)mrr_info, sizeof(*mrr_info));
+}
+
+static int check_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
+{
+ u16 checksum_in_storage = mrr_info->checksum;
+
+ assign_checksum_for_mdl_data(mrr_info);
+
+ return (mrr_info->checksum == checksum_in_storage) ? 1 : 0;
+}
+#endif
+
+#if !__ETT__
+#ifdef COMBO_MCP
+static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+ int i, ret;
+ u16 emi_checksum;
+ bdev_t *bootdev = NULL;
+ DRAM_CALIBRATION_HEADER_T hdr;
+ DRAM_CALIBRATION_MRR_DATA_T mrr_info;
+ DRAM_CALIBRATION_SHU_DATA_T shu_data;
+ DRAM_CALIBRATION_DATA_T *datap = NULL;
+
+ if (dram_offline_data_flags)
+ goto exit;
+
+ if (DramInfo == NULL) {
+ dramc_crit("[dramc] DramInfo == NULL, skip\n");
+ dram_offline_data_flags = ERR_NULL_POINTER;
+ goto exit;
+ }
+
+ bootdev = bio_open_by_label("bootpara");
+ if (!bootdev) {
+ bootdev = bio_open("bootpara");
+ if (!bootdev) {
+ dramc_crit("bootpara is not exist.");
+ dram_offline_data_flags = ERR_BLKDEV_NO_PART;
+ goto exit;
+ }
+ }
+
+ ret = bio_read(bootdev, (u8*)&hdr, 0, sizeof(hdr));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_read %s failed\n", "hdr");
+ dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
+ goto exit;
+ }
+
+ if (hdr.pl_version != PL_VERSION) {
+ /* current preloader version does not match the calibration hdr in storage -> erase the partition */
+ dramc_crit("[dramc] PL_VERSION is updated, erase the DRAM shu_data\n");
+
+ shu_data.checksum = 0;
+
+ /* clear each shuffle */
+ for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
+ ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ dram_offline_data_flags = ERR_BLKDEV_WRITE_FAIL;
+ goto exit;
+ }
+ }
+
+ dram_offline_data_flags = ERR_PL_UPDATED;
+ goto exit;
+ }
+
+ /* check magic number */
+ if (hdr.magic_number != DRAM_CALIBRATION_DATA_MAGIC) {
+ dramc_crit("[dramc] magic number mismatch\n");
+ dram_offline_data_flags = ERR_MAGIC_NUMBER;
+ goto exit;
+ }
+
+ ret = bio_read(bootdev, (u8*)&mrr_info, ((unsigned long) &datap->mrr_info), sizeof(mrr_info));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_read %s failed\n", "data");
+ dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
+ goto exit;
+ }
+
+ /* check checksum */
+ if (check_checksum_for_mdl_data(&mrr_info) != 1) {
+ dramc_crit("[dramc] checksum failed\n");
+ dram_offline_data_flags = ERR_CHECKSUM;
+
+ goto exit;
+ }
+
+ emi_checksum = crc16((u8*)emi_settings, sizeof(emi_settings));
+
+ if (emi_checksum != mrr_info.emi_checksum) {
+ dramc_crit("[dramc] emi checksum failed\n");
+ dram_offline_data_flags = ERR_CHECKSUM;
+
+ goto exit;
+ }
+
+ /* copy the data stored in storage to the data structure for calibration */
+ memcpy(DramInfo, &(mrr_info.DramInfo), sizeof(*DramInfo));
+
+exit:
+ if (dram_offline_data_flags)
+ SET_DRAM_STORAGE_API_ERR(dram_offline_data_flags, DRAM_STORAGE_API_READ);
+
+ return 0 - dram_offline_data_flags;
+}
+
+static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+ int ret;
+ bdev_t *bootdev = NULL;
+ DRAM_CALIBRATION_HEADER_T hdr;
+ DRAM_CALIBRATION_MRR_DATA_T mrr_info;
+ DRAM_CALIBRATION_DATA_T *datap = NULL;
+
+ if (DramInfo == NULL) {
+ dramc_crit("[dramc] DramInfo == NULL, skip\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_NULL_POINTER, DRAM_STORAGE_API_WRITE);
+ return -ERR_NULL_POINTER;
+ }
+
+ bootdev = bio_open_by_label("bootpara");
+ if (!bootdev) {
+ bootdev = bio_open("bootpara");
+ if (!bootdev) {
+ dramc_crit("bootpara is not exist.");
+ return -ERR_BLKDEV_NO_PART;
+ }
+ }
+
+ memcpy(&(mrr_info.DramInfo), DramInfo, sizeof(*DramInfo));
+
+#if 0
+ /* assign PL version */
+ hdr.pl_version = PL_VERSION;
+
+ /* assign magic number */
+ hdr.magic_number = DRAM_CALIBRATION_DATA_MAGIC;
+
+ /* assign api error code */
+ hdr.calib_err_code = g_dram_storage_api_err_code;
+
+ ret = blkdev_write(bootdev, part_dram_data_addr, sizeof(hdr), (u8*)&hdr, PART_ID_DRAM_DATA);
+ if (ret != 0) {
+ dramc_crit("[dramc] blkdev_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+#endif
+
+ /* calculate and assign checksum */
+ mrr_info.emi_checksum = crc16((u8*)emi_settings, sizeof(emi_settings));
+ assign_checksum_for_mdl_data(&mrr_info);
+
+ ret = bio_write(bootdev, (u8*)&mrr_info, ((unsigned long) &datap->mrr_info), sizeof(mrr_info));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+
+ return 0;
+}
+#endif
+
+int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+ int i, ret;
+ bdev_t *bootdev = NULL;
+ DRAM_CALIBRATION_HEADER_T hdr;
+ DRAM_CALIBRATION_SHU_DATA_T shu_data;
+ DRAM_CALIBRATION_DATA_T *datap = NULL;
+ unsigned char *ch;
+
+ if (dram_offline_data_flags)
+ goto exit;
+
+ if (offLine_SaveData == NULL) {
+ dramc_crit("[dramc] offLine_SaveData == NULL, skip\n");
+ dram_offline_data_flags = ERR_NULL_POINTER;
+ goto exit;
+ }
+
+ bootdev = bio_open_by_label("bootpara");
+ if (!bootdev) {
+ bootdev = bio_open("bootpara");
+ if (!bootdev) {
+ dramc_crit("bootpara is not exist.");
+ goto exit;
+ }
+ }
+
+ if (!part_dram_data_addr) {
+ dram_offline_data_flags = ERR_BLKDEV_NO_PART;
+ goto exit;
+ }
+
+ ret = bio_read(bootdev, (u8*)&hdr, 0, sizeof(hdr));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_read %s failed\n", "hdr");
+ dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
+ goto exit;
+ }
+
+ /* check preloader version */
+ if (hdr.pl_version != PL_VERSION) {
+ /* current preloader version does not match the calibration hdr in storage -> erase the partition */
+ dramc_crit("[dramc] PL_VERSION is updated, erase the DRAM shu_data\n");
+
+ shu_data.checksum = 0;
+
+ /* clear each shuffle */
+ for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
+ ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ dram_offline_data_flags = ERR_BLKDEV_WRITE_FAIL;
+ goto exit;
+ }
+ }
+
+ dram_offline_data_flags = ERR_PL_UPDATED;
+ goto exit;
+ }
+
+ /* check magic number */
+ if (hdr.magic_number != DRAM_CALIBRATION_DATA_MAGIC) {
+ dramc_crit("[dramc] magic number mismatch\n");
+ dram_offline_data_flags = ERR_MAGIC_NUMBER;
+ goto exit;
+ }
+
+ ret = bio_read(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[shuffle]), sizeof(shu_data));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_read %s failed\n", "data");
+ dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
+ goto exit;
+ }
+
+ /* check checksum */
+ if (check_checksum_for_dram_data(&shu_data) != 1) {
+ dramc_crit("[dramc] checksum failed\n");
+ dram_offline_data_flags = ERR_CHECKSUM;
+ goto exit;
+ }
+
+ /* copy the data stored in storage to the data structure for calibration */
+ memcpy(offLine_SaveData, &(shu_data.calibration_data), sizeof(*offLine_SaveData));
+
+exit:
+ if (dram_offline_data_flags)
+ SET_DRAM_STORAGE_API_ERR(dram_offline_data_flags, DRAM_STORAGE_API_READ);
+
+ return 0 - dram_offline_data_flags;
+}
+
+int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+ int ret;
+ bdev_t *bootdev = NULL;
+ DRAM_CALIBRATION_HEADER_T hdr;
+ DRAM_CALIBRATION_SHU_DATA_T shu_data;
+ DRAM_CALIBRATION_DATA_T *datap = NULL;
+
+ if (offLine_SaveData == NULL) {
+ dramc_crit("[dramc] offLine_SaveData == NULL, skip\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_NULL_POINTER, DRAM_STORAGE_API_WRITE);
+ return -ERR_NULL_POINTER;
+ }
+
+ bootdev = bio_open_by_label("bootpara");
+ if (!bootdev) {
+ bootdev = bio_open("bootpara");
+ if (!bootdev) {
+ dramc_crit("bootpara is not exist.");
+ return -ERR_BLKDEV_NO_PART;
+ }
+ }
+
+ memcpy(&(shu_data.calibration_data), offLine_SaveData, sizeof(*offLine_SaveData));
+
+ /* assign PL version */
+ hdr.pl_version = PL_VERSION;
+
+ /* assign magic number */
+ hdr.magic_number = DRAM_CALIBRATION_DATA_MAGIC;
+
+ /* assign api error code */
+ hdr.calib_err_code = g_dram_storage_api_err_code;
+
+ ret = bio_write(bootdev, (u8*)&hdr, 0, sizeof(hdr));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+
+ /* calculate and assign checksum */
+ assign_checksum_for_dram_data(&shu_data);
+
+ ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[shuffle]), sizeof(shu_data));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+
+ return 0;
+}
+
+int clean_dram_calibration_data(void)
+{
+ int i, ret;
+ bdev_t *bootdev = NULL;
+ DRAM_CALIBRATION_HEADER_T hdr;
+ DRAM_CALIBRATION_SHU_DATA_T shu_data;
+ DRAM_CALIBRATION_DATA_T *datap = NULL;
+
+ bootdev = bio_open_by_label("bootpara");
+ if (!bootdev) {
+ bootdev = bio_open("bootpara");
+ if (!bootdev) {
+ dramc_crit("bootpara is not exist.");
+ return -ERR_BLKDEV_NO_PART;
+ }
+ }
+
+ memset(&hdr, 0, sizeof(hdr));
+
+ ret = bio_write(bootdev, (u8*)&hdr, 0, sizeof(hdr));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_CLEAN);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+
+ shu_data.checksum = 0;
+
+ /* clear each shuffle */
+ for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
+ ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
+ if (ret != 0) {
+ dramc_crit("[dramc] bio_write failed\n");
+ SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
+ return -ERR_BLKDEV_WRITE_FAIL;
+ }
+ }
+
+ return 0;
+}
+
+#else
+
+DRAM_CALIBRATION_DATA_T dram_data; // using global variable to avoid stack overflow
+
+int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+ return 0;
+}
+
+int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+ return 0;
+}
+
+int clean_dram_calibration_data(void)
+{
+ return;
+}
+#endif
+
+
+void set_err_code_for_storage_api(void)
+{
+#ifdef LAST_DRAMC
+ last_dramc_info_ptr->storage_api_err_flag = g_dram_storage_api_err_code;
+ dsb();
+#endif
+}
+
+#endif
+
+#if __ETT__
+#define FHCTL_HP_EN (FHCTL_BASE + 0x004)
+#define MPLL_FHCTL_CFG (FHCTL_BASE + 0x0A0)
+#define MPLL_FHCTL_LMT (FHCTL_BASE + 0x0A4)
+#define MPLL_FHCTL_DDS (FHCTL_BASE + 0x0A8)
+#define MPLL_CON1 (APMIXED_BASE + 0x2A4)
+#define MPLL_ID 5
+#define SETTING_DF 9
+#define SETTING_DT 0
+#define SETTING_LOWBND 1 // ssc ratio
+#define PERCENT_TO_DDSLMT(dDS, pERCENT_M10) (((dDS * pERCENT_M10) >> 5) / 100)
+
+void en_mpll_ssc(void)
+{
+ unsigned int reg_val;
+
+ *((volatile unsigned int *)0x1000CE08) = 0x1FF;
+ *((volatile unsigned int *)0x1000CE0C) = 0x1FF;
+
+ reg_val = *((volatile unsigned int *)MPLL_FHCTL_CFG);
+ reg_val &= ~0xFF0000;
+ *((volatile unsigned int *)MPLL_FHCTL_CFG) = reg_val | (SETTING_DF << 20) | (SETTING_DT << 16);
+
+ reg_val = (*((volatile unsigned int *)MPLL_CON1) & 0x3FFFFF) | 0x80000000;
+ *((volatile unsigned int *)MPLL_FHCTL_DDS) = reg_val;
+
+ reg_val &= 0x3FFFFF;
+ reg_val = PERCENT_TO_DDSLMT(reg_val, SETTING_LOWBND) << 16;
+ *((volatile unsigned int *)MPLL_FHCTL_LMT) = reg_val;
+
+ *((volatile unsigned int *)FHCTL_HP_EN) |= (1 << MPLL_ID);
+ dsb();
+ *((volatile unsigned int *)MPLL_FHCTL_CFG) |= 0x2;
+ dsb();
+ *((volatile unsigned int *)MPLL_FHCTL_CFG) |= 0x1;
+ dsb();
+}
+
+void dis_mpll_ssc(void)
+{
+ *((volatile unsigned int *)MPLL_FHCTL_CFG) &= ~0x2;
+ dsb();
+ *((volatile unsigned int *)MPLL_FHCTL_CFG) &= ~0x1;
+ dsb();
+ *((volatile unsigned int *)FHCTL_HP_EN) &= ~(1 << MPLL_ID);
+ dsb();
+}
+#endif