[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/lk/platform/mt2731/bl2_bl33_options.mk b/src/bsp/lk/platform/mt2731/bl2_bl33_options.mk
new file mode 100644
index 0000000..5f22323
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/bl2_bl33_options.mk
@@ -0,0 +1,117 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ifeq ($(LK_AS_BL33),1)
+# LK build as BL33
+
+# memory setting
+MEMBASE ?= 0x42110000
+KERNEL_LOAD_OFFSET ?= 0x0
+MEMSIZE ?= 0x100000 # 1MB
+
+ifeq ($(WITH_KERNEL_VM),1)
+KERNEL_BASE ?= 0xfffffff042110000 # KERNEL_ASPACE_BASE + MEMBASE
+else
+KERNEL_BASE ?= 0x42110000
+endif
+
+# dram size setting
+BL33_DRAM_SZ_MB ?= 512
+
+# image load options
+ENABLE_TZ_LOAD := 0 # bl33 doesnt' load tz
+ENABLE_BL33_LOAD := 0 # bl33 doesn't load itself
+ENABLE_KERNEL_LOAD := 1 # loads kernel and dtbo
+ENABLE_SPM_FW_LOAD := 0 # bl33 doesn't load spm fw
+ENABLE_MODEM_LOAD := 1 # loads modem
+ENABLE_HSM_OS_LOAD := 0 # bl33 doesn't load hsm os
+
+# bl33 boot options
+BL33_BOOT_NEXT_64BITS ?= 0 # boot stage after bl33 is 32 bits
+
+# fastboot mode option
+OPTION_CLEAR_FASTBOOT_FLAG ?= 1
+
+# recovery mode option
+OPTION_CLEAR_RECOVERY_FLAG ?= 1
+
+# HSM reserve memory
+ifeq ($(strip $(HSM_OS_SUPPORT)),yes)
+OPTION_RESERVE_HSM_MEMORY_FLAG := 1
+else
+OPTION_RESERVE_HSM_MEMORY_FLAG := 0
+endif
+
+MODULE_SRCS += $(LOCAL_DIR)/platform_bl33.c
+
+ifneq (, $(filter yes, $(MTK_MRDUMP_SUPPORT) $(MTK_KEDUMP_MINI_SUPPORT) $(MTK_BOOT_REASON_SUPPORT)))
+MODULE_DEPS += lib/aee
+endif
+
+GLOBAL_DEFINES += \
+ BL33_DRAM_SZ_MB=$(BL33_DRAM_SZ_MB) \
+ BL33_BOOT_NEXT_64BITS=$(BL33_BOOT_NEXT_64BITS) \
+ ENABLE_MODEM_LOAD=$(ENABLE_MODEM_LOAD)
+
+else
+
+# LK build as BL2
+
+# memory setting
+MEMBASE ?= 0x200000
+KERNEL_LOAD_OFFSET ?= 0x1000
+MEMSIZE ?= 0x40000 # 256KB
+
+ifeq ($(WITH_KERNEL_VM),1)
+ifeq ($(ARCH),arm64)
+KERNEL_BASE ?= 0xfffffff000200000 # KERNEL_ASPACE_BASE + MEMBASE
+endif
+ifeq ($(ARCH),arm)
+KERNEL_BASE ?= 0x200000
+endif
+else
+KERNEL_BASE ?= 0x200000
+endif
+
+# image load options
+ENABLE_TZ_LOAD := 1 # loads tz
+ENABLE_BL33_LOAD := 1
+ENABLE_BUILTIN_BL33 ?= 1 # default use builtin 'do-nothing-but-jump' bl33
+ifeq ($(ENABLE_BUILTIN_BL33),1)
+ENABLE_KERNEL_LOAD := 1 # if builtin bl33, bl2 also loads kernel (& dtbo)
+OPTION_CLEAR_FASTBOOT_FLAG ?= 1
+OPTION_CLEAR_RECOVERY_FLAG ?= 1
+else
+ENABLE_KERNEL_LOAD := 0
+OPTION_CLEAR_FASTBOOT_FLAG ?= 0
+OPTION_CLEAR_RECOVERY_FLAG ?= 0
+endif
+ENABLE_SPM_FW_LOAD := 1 # loads spm fw for atf
+ifeq ($(strip $(HSM_OS_SUPPORT)),yes)
+ENABLE_HSM_OS_LOAD := 1 # loads HSM OS
+else
+ENABLE_HSM_OS_LOAD := 0 # not load HSM OS
+endif
+OPTION_RESERVE_HSM_MEMORY_FLAG := 0
+
+# bl2 boot options
+BL2_BOOT_NEXT_64BITS ?= 1 # boot stage after bl2 is 64 bits
+
+MODULE_SRCS += $(LOCAL_DIR)/platform_bl2.c
+
+GLOBAL_DEFINES += \
+ ENABLE_BUILTIN_BL33=$(ENABLE_BUILTIN_BL33) \
+ BL2_BOOT_NEXT_64BITS=$(BL2_BOOT_NEXT_64BITS)
+
+endif
+
+GLOBAL_DEFINES += \
+ MEMBASE=$(MEMBASE) \
+ MEMSIZE=$(MEMSIZE) \
+ ENABLE_TZ_LOAD=$(ENABLE_TZ_LOAD) \
+ ENABLE_BL33_LOAD=$(ENABLE_BL33_LOAD) \
+ ENABLE_KERNEL_LOAD=$(ENABLE_KERNEL_LOAD) \
+ OPTION_CLEAR_FASTBOOT_FLAG=$(OPTION_CLEAR_FASTBOOT_FLAG) \
+ OPTION_CLEAR_RECOVERY_FLAG=$(OPTION_CLEAR_RECOVERY_FLAG) \
+ ENABLE_SPM_FW_LOAD=$(ENABLE_SPM_FW_LOAD) \
+ ENABLE_HSM_OS_LOAD=$(ENABLE_HSM_OS_LOAD) \
+ OPTION_RESERVE_HSM_MEMORY_FLAG=$(OPTION_RESERVE_HSM_MEMORY_FLAG) \
diff --git a/src/bsp/lk/platform/mt2731/debug.c b/src/bsp/lk/platform/mt2731/debug.c
new file mode 100644
index 0000000..cbcf7b7
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/debug.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dev/uart.h>
+#include <platform/debug.h>
+#include <target/debugconfig.h>
+
+/* DEBUG_UART must be defined to 0 or 1 */
+#if defined(DEBUG_UART) && DEBUG_UART == 0
+#define DEBUG_UART_BASE UART0_BASE
+#elif defined(DEBUG_UART) && DEBUG_UART == 1
+#define DEBUG_UART_BASE UART1_BASE
+#else
+#error define DEBUG_UART to something valid
+#endif
+
+void platform_dputc(char c)
+{
+ if (c == '\n')
+ uart_putc(DEBUG_UART, '\r');
+ uart_putc(DEBUG_UART, c);
+}
+
+int platform_dgetc(char *c, bool wait)
+{
+ int ret = uart_getc(DEBUG_UART, wait);
+ if (ret == -1)
+ return -1;
+ *c = ret;
+ return 0;
+}
+
+void platform_pputc(char c)
+{
+ if (c == '\n')
+ uart_pputc(DEBUG_UART, '\r');
+ uart_pputc(DEBUG_UART, c);
+}
+
+int platform_pgetc(char *c, bool wait)
+{
+ int ret = uart_pgetc(DEBUG_UART);
+ if (ret < 0)
+ return ret;
+ *c = ret;
+ return 0;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/audio/audio_clk_enable.c b/src/bsp/lk/platform/mt2731/drivers/audio/audio_clk_enable.c
new file mode 100644
index 0000000..290d7f1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/audio/audio_clk_enable.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <reg.h>
+#include <platform/audio_clk_enable.h>
+#include <platform/pll.h>
+
+#ifndef LK_ENABLE_AUDIO_CLK
+
+void mt_audio_clk_enable(void)
+{
+ return;
+}
+
+#else
+
+static uintptr_t g_afe_enable_reg[] = {
+ ASYS_TOP_CON,
+ AFE_DAC_CON0
+};
+
+static uint32_t g_afe_enable_val[] = {
+ 0x00000003U,
+ 0x00000001U,
+};
+
+static uintptr_t g_clk_enable_reg[] = {
+ AUDIO_TOP_CON4,
+};
+
+static uint32_t g_clk_enable_val[] = {
+#if LK_ENABLE_I2S_SEP_CLK
+ 0xff1fffbfU,
+#elif LK_ENABLE_I2S_COCLK
+ 0xff1fffbeU,
+#else
+ 0xff1fffffU,
+#endif
+};
+
+#if ENABLE_TDM_CLK
+#if LK_ENABLE_TDM_SEP_CLK
+static uintptr_t g_tdm_enable_reg[] = {
+ AUDIO_TOP_CON1,
+ AUDIO_TOP_CON2,
+ AFE_TDM_G1_CON1,
+ AFE_TDM_G1_CON2,
+ AFE_TDM_G1_CON1
+};
+static uint32_t g_tdm_enable_val[] = {
+ 0x0f000000U,
+ 0x00000f02U,
+ 0x0fbfab1aU,
+ 0xa500ff40U,
+ 0x0fbfab1bU
+};
+#elif LK_ENABLE_TDM_COCLK
+static uintptr_t g_tdm_enable_reg[] = {
+ AUDIO_TOP_CON1,
+ AUDIO_TOP_CON2,
+ AFE_TDM_G1_CON1,
+ AFE_TDM_G1_CON2,
+ AFE_TDM_IN_CON1,
+ AFE_TDM_IN_CON2,
+ AFE_TDM_G1_CON1,
+ AFE_TDM_IN_CON1
+};
+static uint32_t g_tdm_enable_val[] = {
+ 0x0f000000U,
+ 0x00000f02U,
+ 0x0fbfab0aU,
+ 0xa500ff40U,
+ 0x0fa6230aU,
+ 0x00000000U,
+ 0x0fbfab0bU,
+ 0x0fa6230bU
+};
+#endif
+#endif
+
+#if ENABLE_I2S_CLK
+#if LK_ENABLE_I2S_SEP_CLK
+static uintptr_t g_i2s_enable_reg[] = {
+ ASYS_I2SO1_CON,
+ ASMO_TIMING_CON1,
+ ASYS_I2SO1_CON
+};
+
+static uint32_t g_i2s_enable_val[] = {
+ 0x0000050aU,
+ 0x00000005U,
+ 0x0000050bU
+};
+#elif LK_ENABLE_I2S_COCLK
+static uintptr_t g_i2s_enable_reg[] = {
+ ASYS_I2SO1_CON,
+ ASMO_TIMING_CON1,
+ ASYS_I2SIN1_CON,
+ ASMI_TIMING_CON1,
+ ASYS_I2SO1_CON,
+ ASYS_I2SIN1_CON
+};
+
+static uint32_t g_i2s_enable_val[] = {
+ 0x0000050aU,
+ 0x00000005U,
+ 0x8000850aU,
+ 0x00000005U,
+ 0x0000050bU,
+ 0x8000850bU,
+};
+#endif
+#endif
+
+#ifdef LK_AUDIO_USE_EXT_CLK
+static uintptr_t g_set_apll_src_reg[] = {
+ PLL_TEST_CON0,
+ AP_PLL_CON5,
+ APLL1_CON0,
+ APLL1_CON1,
+ APLL1_CON2,
+ APLL1_CON1,
+ APLL2_CON0,
+ APLL2_CON1,
+ APLL2_CON2,
+ APLL2_CON1,
+ AP_PLL_CON5,
+};
+
+static uint32_t g_set_apll_src_val[] = {
+ 0x00060000U,
+ 0x00000000U,
+ 0x00000030U,
+ 0x40000000U,
+ 0x40000001U,
+ 0x80000000U,
+ 0x00000030U,
+ 0x3ACCCCCCU,
+ 0x3ACCCCCDU,
+ 0x80000000U,
+ 0x00000003U,
+};
+
+static uint32_t g_set_apll_src_mask[] = {
+ 0x00060000U,
+ 0x00000003U,
+ 0x00000070U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x80000000U,
+ 0x00000070U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x80000000U,
+ 0x00000003U,
+};
+#endif
+
+void audio_set_reg_addr_val_mask(uintptr_t addr, uint32_t val, uint32_t mask)
+{
+ volatile uint32_t val_orig = audio_get_reg(addr);
+ volatile uint32_t val_to_write = (val_orig & (~mask)) | (val & mask);
+
+ audio_set_reg_addr_val(addr, val_to_write);
+}
+
+void write_reg_seq(uintptr_t *reg_arr, uint32_t *val_arr, size_t size)
+{
+ size_t i;
+ for (i=0; i<size; ++i) {
+ audio_set_reg_addr_val(reg_arr[i], val_arr[i]);
+ }
+}
+
+void write_reg_seq_with_mask(uintptr_t *reg_arr, uint32_t *val_arr,
+ uint32_t *mask_arr, size_t size)
+{
+ size_t i;
+ for (i=0; i<size; ++i) {
+ audio_set_reg_addr_val_mask(reg_arr[i], val_arr[i], mask_arr[i]);
+ }
+}
+
+void mt_audio_clk_enable(void)
+{
+
+ dprintf(INFO, "open clk start time tag %u\n",
+ audio_get_reg(IO_PHYS + 0x0000c008));
+
+#ifdef LK_AUDIO_USE_EXT_CLK
+ /* Set gpio here (GPIO186 set to mode 1) for EXT_CLK 1 */
+ dprintf(INFO, "Set gpio (GPIO186 set to mode 1) for EXT_CLK 1\n");
+ audio_set_reg_addr_val_mask(IO_PHYS + 0x00005750, 0x00000008, 0x00000038);
+
+ /* Set rate & external source for apll1/apll2 */
+ write_reg_seq_with_mask(g_set_apll_src_reg,
+ g_set_apll_src_val, g_set_apll_src_mask,
+ sizeof(g_set_apll_src_reg) / sizeof(g_set_apll_src_reg[0]));
+
+#endif
+
+ /* set ccf clk to right value which is not the same with default */
+ audio_set_reg_addr_val_mask(CLK_CFG_12, 0x01000001, 0x03000003);
+ audio_set_reg_addr_val_mask(CLK_AUDDIV_1, 0x0F00003F, 0xFF0000FF);
+ audio_set_reg_addr_val_mask(CLK_CFG_10, 0x03000000, 0x07000000);
+ audio_set_reg_addr_val_mask(CLK_CFG_11, 0x00000003, 0x00000007);
+
+ /* enable clks in ccf */
+ audio_set_reg_addr_val_mask(CLK_CFG_12, 0x0, 0x80000008);
+ audio_set_reg_addr_val_mask(CLK_CFG_10, 0x0, 0x80808000);
+ audio_set_reg_addr_val_mask(CLK_CFG_11, 0x0, 0x00000080);
+ audio_set_reg_addr_val_mask(CLK_CFG_4, 0x0, 0x80000000);
+
+#if ENABLE_TDM_CLK
+ /* Set gpio here (GPIO200~GPIO203 set to mode 1) for TDM out */
+ dprintf(INFO, "Set gpio (GPIO200~GPIO203 set to mode 1) for TDM out\n");
+ audio_set_reg_addr_val_mask(IO_PHYS + 0x00005780, 0x00000249, 0x00000FFF);
+#endif
+
+#if ENABLE_I2S_CLK
+ /* Set gpio here (GPIO192~GPIO195 set to mode 1) for I2S out */
+ dprintf(INFO, "Set gpio (GPIO192~GPIO195 set to mode 1) for I2S out\n");
+ audio_set_reg_addr_val_mask(IO_PHYS + 0x00005760, 0x00001240, 0x00007FC0);
+ audio_set_reg_addr_val_mask(IO_PHYS + 0x00005770, 0x00000001, 0x00000007);
+#endif
+
+ write_reg_seq(g_afe_enable_reg, g_afe_enable_val,
+ sizeof(g_afe_enable_reg) / sizeof(g_afe_enable_reg[0]));
+ write_reg_seq(g_clk_enable_reg, g_clk_enable_val,
+ sizeof(g_clk_enable_reg) / sizeof(g_clk_enable_reg[0]));
+#if ENABLE_TDM_CLK
+ write_reg_seq(g_tdm_enable_reg, g_tdm_enable_val,
+ sizeof(g_tdm_enable_reg) / sizeof(g_tdm_enable_reg[0]));
+#endif
+
+#if ENABLE_I2S_CLK
+ write_reg_seq(g_i2s_enable_reg, g_i2s_enable_val,
+ sizeof(g_i2s_enable_reg) / sizeof(g_i2s_enable_reg[0]));
+#endif
+ dprintf(INFO, "open clk end time tag %u\n",
+ audio_get_reg(IO_PHYS + 0x0000c008));
+}
+
+#endif //LK_ENABLE_AUDIO_CLK
diff --git a/src/bsp/lk/platform/mt2731/drivers/audio/include/platform/audio_clk_enable.h b/src/bsp/lk/platform/mt2731/drivers/audio/include/platform/audio_clk_enable.h
new file mode 100644
index 0000000..27b3ab8
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/audio/include/platform/audio_clk_enable.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <platform/mt_reg_base.h>
+#define AFE_REG_BASE (IO_PHYS + 0x01220000)
+
+#define AUDIO_TOP_CON0 (AFE_REG_BASE + 0x0000U)
+#define AUDIO_TOP_CON1 (AFE_REG_BASE + 0x0004U)
+#define AUDIO_TOP_CON2 (AFE_REG_BASE + 0x0008U)
+#define AUDIO_TOP_CON4 (AFE_REG_BASE + 0x0010U)
+#define ASMI_TIMING_CON1 (AFE_REG_BASE + 0x0100U)
+#define ASMO_TIMING_CON1 (AFE_REG_BASE + 0x0104U)
+#define AFE_TDM_G1_CON1 (AFE_REG_BASE + 0x0290U)
+#define AFE_TDM_G1_CON2 (AFE_REG_BASE + 0x0294U)
+#define AFE_TDM_G2_CON1 (AFE_REG_BASE + 0x02a0U)
+#define AFE_TDM_G2_CON2 (AFE_REG_BASE + 0x02a4U)
+#define AFE_TDM_IN_CON1 (AFE_REG_BASE + 0x02b8U)
+#define AFE_TDM_IN_CON2 (AFE_REG_BASE + 0x02bcU)
+#define ASYS_TOP_CON (AFE_REG_BASE + 0x0600U)
+#define ASYS_I2SIN1_CON (AFE_REG_BASE + 0x0604U)
+#define ASYS_I2SO1_CON (AFE_REG_BASE + 0x061cU)
+#define AFE_DAC_CON0 (AFE_REG_BASE + 0x1200U)
+
+#define AFE_SGEN_CON0 (AFE_REG_BASE + 0x01f0U)
+
+#define audio_get_reg(addr) readl(addr)
+#define audio_set_reg_addr_val(addr, val) writel(val, addr)
+
+#define ENABLE_TDM_CLK (LK_ENABLE_TDM_SEP_CLK || LK_ENABLE_TDM_COCLK)
+#define ENABLE_I2S_CLK (LK_ENABLE_I2S_SEP_CLK || LK_ENABLE_I2S_COCLK)
+
+void mt_audio_clk_enable(void);
diff --git a/src/bsp/lk/platform/mt2731/drivers/audio/rules.mk b/src/bsp/lk/platform/mt2731/drivers/audio/rules.mk
new file mode 100644
index 0000000..1b915ea
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/audio/rules.mk
@@ -0,0 +1,43 @@
+# define build parameters to enable "lk open clock feature"
+# you may define the parameters in project/XXX.mk for XXX project
+# ENABLE_AUDIO_CLK := 1 -> enable the feature
+# AUDIO_USE_EXT_CLK := 1 -> apll1/apll2 use external clk
+# ENABLE_TDM_CLK_MODE := 1 -> enable the TDM out 0 with non-coclk setting
+# ENABLE_TDM_CLK_MODE := 2 -> enable the TDM out 0 with coclk setting
+# ENABLE_I2S_CLK_MODE := 1 -> enable the I2S out 0 with non-coclk setting
+# ENABLE_I2S_CLK_MODE := 2 -> enable the I2S out 0 with coclk setting
+#
+# Note: The TDM/I2S out format will be fixed once you enable the feature.
+# If you want to change the setting there is some parameter you need to change:
+# TDM Sample rate: AUDIO_TOP_CON1 bit 31:24, AUDIO_TOP_CON2 bit 15:8
+# TDM data/clk format: AFE_TDM_G1_CON1, AFE_TDM_IN_CON1
+# I2S Sample rate: ASMO_TIMING_CON1, ASMI_TIMING_CON1
+# I2S format: ASYS_I2SO1_CON, ASYS_I2SIN1_CON
+LOCAL_DIR := $(GET_LOCAL_DIR)
+MODULE := $(LOCAL_DIR)
+
+ifeq ($(strip $(ENABLE_AUDIO_CLK)),1)
+MODULE_DEFINES += LK_ENABLE_AUDIO_CLK
+
+ifeq ($(strip $(AUDIO_USE_EXT_CLK)),1)
+MODULE_DEFINES += LK_AUDIO_USE_EXT_CLK
+endif
+
+ifeq ($(strip $(ENABLE_TDM_CLK_MODE)),1)
+MODULE_DEFINES += LK_ENABLE_TDM_SEP_CLK=1
+else ifeq ($(strip $(ENABLE_TDM_CLK_MODE)),2)
+MODULE_DEFINES += LK_ENABLE_TDM_COCLK=1
+endif
+
+ifeq ($(strip $(ENABLE_I2S_CLK_MODE)),1)
+MODULE_DEFINES += LK_ENABLE_I2S_SEP_CLK=1
+else ifeq ($(strip $(ENABLE_I2S_CLK_MODE)),2)
+MODULE_DEFINES += LK_ENABLE_I2S_COCLK=1
+endif
+
+endif
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/audio_clk_enable.c \
+
+include make/module.mk
diff --git a/src/bsp/lk/platform/mt2731/drivers/bgr/bgr.c b/src/bsp/lk/platform/mt2731/drivers/bgr/bgr.c
new file mode 100644
index 0000000..90bddd9
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/bgr/bgr.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/bgr.h>
+#include <platform/mt_reg_base.h>
+
+#define BGR_RSEL (BGR_BASE + 0x0)
+
+extern int read_efuse(unsigned int index, unsigned char *data, unsigned int len)__attribute__((weak));
+
+void bgr_init(void)
+{
+ int ret = 0;
+ size_t bgr_value, temp;
+
+ // Read eFuse
+ if (!read_efuse) {
+ dprintf(CRITICAL, "eFuse read is not supported\n");
+ return;
+ }
+
+ ret = read_efuse(72, &bgr_value, 4);
+ if (!ret) {
+ bgr_value &= 0xf;
+ dprintf(CRITICAL, "eFuse BGR value: %x\n", bgr_value);
+ } else {
+ dprintf(CRITICAL, "eFuse BGR read fail\n");
+ return;
+ }
+
+ // Write to BGR register
+ temp = readl(BGR_RSEL);
+ temp = temp & 0xFFFFFFC3;
+ temp |= (bgr_value<<2);
+ temp |= (1<<15);
+ writel(temp, BGR_RSEL);
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/clkbuf/clkbuf_ctl.c b/src/bsp/lk/platform/mt2731/drivers/clkbuf/clkbuf_ctl.c
new file mode 100644
index 0000000..26ea54c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/clkbuf/clkbuf_ctl.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <platform/clkbuf_ctl.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_typedefs.h>
+#include <platform/pmic.h>
+
+#define clk_buf_warn(fmt, args...) printf(fmt, ##args)
+
+#define clkbuf_readl(addr) DRV_Reg32(addr)
+#define clkbuf_writel(addr, val) DRV_WriteReg32(addr, val)
+
+#define PWRAP_REG(ofs) (PWRAP_BASE + ofs)
+/* PMICWRAP Reg */
+#define DCXO_ENABLE PWRAP_REG(0x190)
+#define DCXO_CONN_ADR0 PWRAP_REG(0x194)
+#define DCXO_CONN_WDATA0 PWRAP_REG(0x198)
+#define DCXO_CONN_ADR1 PWRAP_REG(0x19C)
+#define DCXO_CONN_WDATA1 PWRAP_REG(0x1A0)
+#define DCXO_NFC_ADR0 PWRAP_REG(0x1A4)
+#define DCXO_NFC_WDATA0 PWRAP_REG(0x1A8)
+#define DCXO_NFC_ADR1 PWRAP_REG(0x1AC)
+#define DCXO_NFC_WDATA1 PWRAP_REG(0x1B0)
+
+#define SPM_REG(ofs) (SPM_BASE + ofs)
+/* SPM Reg */
+#define RC_M12_SRCLKEN_CFG SPM_REG(0x550)
+
+#define DCXO_CONN_ENABLE (0x1 << 1)
+//#define DCXO_NFC_ENABLE (0x1 << 0)
+
+#define PMIC_REG_MASK 0xFFFF
+#define PMIC_REG_SHIFT 0
+
+enum MTK_CLK_BUF_STATUS {
+ CLOCK_BUFFER_DISABLE,
+ CLOCK_BUFFER_SW_CONTROL,
+ CLOCK_BUFFER_HW_CONTROL,
+};
+
+static unsigned int CLK_BUF1_STATUS_PMIC = CLOCK_BUFFER_HW_CONTROL,
+ CLK_BUF2_STATUS_PMIC = CLOCK_BUFFER_SW_CONTROL,
+ //CLK_BUF3_STATUS_PMIC = CLOCK_BUFFER_DISABLE,
+ CLK_BUF4_STATUS_PMIC = CLOCK_BUFFER_HW_CONTROL,
+ //CLK_BUF5_STATUS_PMIC = CLOCK_BUFFER_DISABLE,
+ //CLK_BUF6_STATUS_PMIC = CLOCK_BUFFER_DISABLE,
+ CLK_BUF7_STATUS_PMIC = CLOCK_BUFFER_SW_CONTROL;
+
+static unsigned int PMIC_CLK_BUF1_OUTPUT_IMPEDANCE = 6,
+ PMIC_CLK_BUF2_OUTPUT_IMPEDANCE = 4,
+ PMIC_CLK_BUF3_OUTPUT_IMPEDANCE = 6,
+ PMIC_CLK_BUF4_OUTPUT_IMPEDANCE = 4,
+ PMIC_CLK_BUF7_OUTPUT_IMPEDANCE = 6;
+static unsigned int PMIC_CLK_BUF2_CONTROLS_FOR_DESENSE = 4,
+ PMIC_CLK_BUF3_CONTROLS_FOR_DESENSE = 0,
+ PMIC_CLK_BUF4_CONTROLS_FOR_DESENSE = 4;
+
+#if MTK_SRCLKEN_RC_FULL_SET
+#define PMIC_CW00_INIT_VAL 0x4A4D
+#define PMIC_CW09_INIT_VAL 0x51F0
+#else
+#define PMIC_CW00_INIT_VAL 0x4E1D
+#define PMIC_CW09_INIT_VAL 0x41F0
+#endif
+
+static void clk_buf_dump_clkbuf_log(void)
+{
+#ifndef CLKBUF_BRINGUP
+ u32 pmic_cw00 = 0, pmic_cw09 = 0, pmic_cw12 = 0, pmic_cw13 = 0,
+ pmic_cw15 = 0, pmic_cw19 = 0, top_spi_con1 = 0,
+ ldo_vrfck_op_en = 0, ldo_vbbck_op_en = 0, ldo_vrfck_en = 0,
+ ldo_vbbck_en = 0;
+
+ pmic_read_interface(PMIC_XO_EXTBUF1_MODE_ADDR, &pmic_cw00,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_XO_EXTBUF7_MODE_ADDR, &pmic_cw09,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR, &pmic_cw12,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_RG_XO_EXTBUF2_SRSEL_ADDR, &pmic_cw13,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_RG_XO_RESERVED1_ADDR, &pmic_cw15,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_RG_XO_EXTBUF2_RSEL_ADDR, &pmic_cw19,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_read_interface(PMIC_RG_SRCLKEN_IN3_EN_ADDR, &top_spi_con1,
+ PMIC_RG_SRCLKEN_IN3_EN_MASK, PMIC_RG_SRCLKEN_IN3_EN_SHIFT);
+
+ pmic_read_interface(PMIC_RG_LDO_VRFCK_EN_ADDR, &ldo_vrfck_en,
+ PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT);
+ pmic_read_interface(PMIC_RG_LDO_VBBCK_EN_ADDR, &ldo_vbbck_en,
+ PMIC_RG_LDO_VBBCK_EN_MASK, PMIC_RG_LDO_VBBCK_EN_SHIFT);
+ clk_buf_warn("%s DCXO_CW00/09/12/13/15/19=0x%x %x %x %x %x %x\n",
+ __func__, pmic_cw00, pmic_cw09, pmic_cw12, pmic_cw13, pmic_cw15, pmic_cw19);
+ clk_buf_warn("%s spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x%x %x %x %x %x\n",
+ __func__, top_spi_con1, ldo_vrfck_op_en, ldo_vbbck_op_en, ldo_vrfck_en, ldo_vbbck_en);
+#endif
+}
+
+static void clk_buf_init_pmic_clkbuf(void)
+{
+#ifndef CLKBUF_BRINGUP
+ /* Dump registers before setting */
+ clk_buf_dump_clkbuf_log();
+
+ /* enable XO LDO */
+ pmic_config_interface(PMIC_RG_LDO_VRFCK_HW3_OP_EN_ADDR, 0x1,
+ PMIC_RG_LDO_VRFCK_HW3_OP_EN_MASK, PMIC_RG_LDO_VRFCK_HW3_OP_EN_SHIFT);
+ pmic_config_interface(PMIC_RG_LDO_VBBCK_HW3_OP_EN_ADDR, 0x1,
+ PMIC_RG_LDO_VBBCK_HW3_OP_EN_MASK, PMIC_RG_LDO_VBBCK_HW3_OP_EN_SHIFT);
+
+ pmic_config_interface(PMIC_RG_LDO_VRFCK_EN_ADDR, 0x0,
+ PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT);
+ pmic_config_interface(PMIC_RG_LDO_VBBCK_EN_ADDR, 0x0,
+ PMIC_RG_LDO_VBBCK_EN_MASK, PMIC_RG_LDO_VBBCK_EN_SHIFT);
+
+ /* Setup initial PMIC clock buffer setting */
+ /* 1.1 Buffer de-sense setting */
+ /* FIXME: read dts and set to SRSEL and HD */
+ pmic_config_interface(PMIC_RG_XO_EXTBUF2_SRSEL_ADDR, PMIC_CLK_BUF2_CONTROLS_FOR_DESENSE,
+ PMIC_RG_XO_EXTBUF2_SRSEL_MASK, PMIC_RG_XO_EXTBUF2_SRSEL_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF3_HD_ADDR, PMIC_CLK_BUF3_CONTROLS_FOR_DESENSE,
+ PMIC_RG_XO_EXTBUF3_HD_MASK, PMIC_RG_XO_EXTBUF3_HD_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF4_SRSEL_ADDR, PMIC_CLK_BUF4_CONTROLS_FOR_DESENSE,
+ PMIC_RG_XO_EXTBUF4_SRSEL_MASK, PMIC_RG_XO_EXTBUF4_SRSEL_SHIFT);
+
+ /* 1.2 Buffer setting for trace impedance */
+ /* FIXME: read dts and set to RSEL .*/
+ pmic_config_interface(PMIC_RG_XO_EXTBUF1_RSEL_ADDR, PMIC_CLK_BUF1_OUTPUT_IMPEDANCE,
+ PMIC_RG_XO_EXTBUF1_RSEL_MASK, PMIC_RG_XO_EXTBUF1_RSEL_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF2_RSEL_ADDR, PMIC_CLK_BUF2_OUTPUT_IMPEDANCE,
+ PMIC_RG_XO_EXTBUF2_RSEL_MASK, PMIC_RG_XO_EXTBUF2_RSEL_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF3_RSEL_ADDR, PMIC_CLK_BUF3_OUTPUT_IMPEDANCE,
+ PMIC_RG_XO_EXTBUF3_RSEL_MASK, PMIC_RG_XO_EXTBUF3_RSEL_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF4_RSEL_ADDR, PMIC_CLK_BUF4_OUTPUT_IMPEDANCE,
+ PMIC_RG_XO_EXTBUF4_RSEL_MASK, PMIC_RG_XO_EXTBUF4_RSEL_SHIFT);
+ pmic_config_interface(PMIC_RG_XO_EXTBUF7_RSEL_ADDR, PMIC_CLK_BUF7_OUTPUT_IMPEDANCE,
+ PMIC_RG_XO_EXTBUF7_RSEL_MASK, PMIC_RG_XO_EXTBUF7_RSEL_SHIFT);
+
+ /* 1.3 XO_WCN/XO_CEL phase delay */
+ pmic_config_interface(PMIC_RG_XO_RESERVED1_ADDR, 0xF,
+ PMIC_RG_XO_RESERVED1_MASK, PMIC_RG_XO_RESERVED1_SHIFT);
+
+ /* 1.4 26M enable control */
+#ifndef MTK_SRCLKEN_RC_SUPPORT
+
+ /*Legacy co-clock mode */
+#ifdef CLKBUF_CONN_SUPPORT_CTRL_FROM_I1
+ pmic_config_interface(PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR, 0x1,
+ PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK, PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT);
+#else
+ pmic_config_interface(PMIC_RG_SRCLKEN_IN3_EN_ADDR, 0,
+ PMIC_RG_SRCLKEN_IN3_EN_MASK, PMIC_RG_SRCLKEN_IN3_EN_SHIFT);
+#endif
+ pmic_config_interface(PMIC_XO_EXTBUF1_MODE_ADDR, PMIC_CW00_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_config_interface(PMIC_XO_EXTBUF7_MODE_ADDR, PMIC_CW09_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+
+#else /* MTK_SRCLKEN_RC_SUPPORT */
+
+#if MTK_SRCLKEN_RC_BT_ONLY
+
+ /* only PMRC_EN[5] to control MODE and XO */
+#ifdef CLKBUF_CONN_SUPPORT_CTRL_FROM_I1
+ pmic_config_interface(PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR, 0x1,
+ PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK, PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT);
+#else
+ pmic_config_interface(PMIC_RG_SRCLKEN_IN3_EN_ADDR, 0,
+ PMIC_RG_SRCLKEN_IN3_EN_MASK, PMIC_RG_SRCLKEN_IN3_EN_SHIFT);
+#endif
+ pmic_config_interface(PMIC_XO_EXTBUF1_MODE_ADDR, PMIC_CW00_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_config_interface(PMIC_XO_EXTBUF7_MODE_ADDR, PMIC_CW09_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+
+ /*
+ * XO_PMIC_TOP_DIG_SW=1
+ * XO_MODE_CONN_BT_MASK=1
+ * XO_BUF_CONN_BT_MASK=1
+ */
+ pmic_config_interface(PMIC_XO_PMIC_TOP_DIG_SW_ADDR, 0x1,
+ PMIC_XO_PMIC_TOP_DIG_SW_MASK, PMIC_XO_PMIC_TOP_DIG_SW_SHIFT);
+ pmic_config_interface(PMIC_XO_MODE_CONN_BT_MASK_ADDR, 0x1,
+ PMIC_XO_MODE_CONN_BT_MASK_MASK, PMIC_XO_MODE_CONN_BT_MASK_SHIFT);
+ pmic_config_interface(PMIC_XO_BUF_CONN_BT_MASK_ADDR, 0x1,
+ PMIC_XO_BUF_CONN_BT_MASK_MASK, PMIC_XO_BUF_CONN_BT_MASK_SHIFT);
+
+#elif MTK_SRCLKEN_RC_FULL_SET
+
+ /* fully new co-clock mode */
+
+ /* All XO mode should set to 2'b01 */
+ pmic_config_interface(PMIC_XO_EXTBUF1_MODE_ADDR, PMIC_CW00_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+ pmic_config_interface(PMIC_XO_EXTBUF7_MODE_ADDR, PMIC_CW09_INIT_VAL,
+ PMIC_REG_MASK, PMIC_REG_SHIFT);
+
+ /* 1.switch to new control mode */
+ /*
+ * XO_PMIC_TOP_DIG_SW=0
+ * XO_MODE_CONN_BT_MASK=0
+ * XO_BUF_CONN_BT_MASK=0
+ */
+ pmic_config_interface(PMIC_XO_PMIC_TOP_DIG_SW_ADDR, 0x0,
+ PMIC_XO_PMIC_TOP_DIG_SW_MASK, PMIC_XO_PMIC_TOP_DIG_SW_SHIFT);
+ pmic_config_interface(PMIC_XO_MODE_CONN_BT_MASK_ADDR, 0x0,
+ PMIC_XO_MODE_CONN_BT_MASK_MASK, PMIC_XO_MODE_CONN_BT_MASK_SHIFT);
+ pmic_config_interface(PMIC_XO_BUF_CONN_BT_MASK_ADDR, 0x0,
+ PMIC_XO_BUF_CONN_BT_MASK_MASK, PMIC_XO_BUF_CONN_BT_MASK_SHIFT);
+
+ /* 2.update control mapping table */
+ /*
+ * XO_SOC_VOTE=11'h006(default) --> too old, need modify
+ * XO_WCN_VOTE=11'h078(default) --> too old, need modify
+ * XO_NFC_VOTE=11'h100(default) --> too old, need modify
+ * XO_CEL_VOTE=11'h001(default) --> too old, need modify
+ * XO_EXT_VOTE=11'h200(default) --> too old, need modify
+ */
+ pmic_config_interface(PMIC_XO_SOC_VOTE_ADDR, 0x00d,
+ PMIC_XO_SOC_VOTE_MASK, PMIC_XO_SOC_VOTE_SHIFT);
+ pmic_config_interface(PMIC_XO_WCN_VOTE_ADDR, 0x0f0,
+ PMIC_XO_WCN_VOTE_MASK, PMIC_XO_WCN_VOTE_SHIFT);
+ //pmic_config_interface(PMIC_XO_NFC_VOTE_ADDR, 0x200,
+ // PMIC_XO_NFC_VOTE_MASK, PMIC_XO_NFC_VOTE_SHIFT);
+ pmic_config_interface(PMIC_XO_CEL_VOTE_ADDR, 0x002,
+ PMIC_XO_CEL_VOTE_MASK, PMIC_XO_CEL_VOTE_SHIFT);
+ pmic_config_interface(PMIC_XO_EXT_VOTE_ADDR, 0x400,
+ PMIC_XO_EXT_VOTE_MASK, PMIC_XO_EXT_VOTE_SHIFT);
+#endif
+#endif /* MTK_SRCLKEN_RC_SUPPORT */
+
+ /* disable clock buffer by DCT setting */
+ if (CLK_BUF2_STATUS_PMIC == CLOCK_BUFFER_DISABLE) {
+ pmic_config_interface(PMIC_DCXO_CW00_CLR_ADDR,
+ PMIC_XO_EXTBUF2_MODE_MASK,
+ PMIC_XO_EXTBUF2_MODE_MASK,
+ PMIC_XO_EXTBUF2_MODE_SHIFT);
+ pmic_config_interface(PMIC_DCXO_CW00_CLR_ADDR,
+ PMIC_XO_EXTBUF2_EN_M_MASK,
+ PMIC_XO_EXTBUF2_EN_M_MASK,
+ PMIC_XO_EXTBUF2_EN_M_SHIFT);
+ }
+
+ if (CLK_BUF4_STATUS_PMIC == CLOCK_BUFFER_DISABLE) {
+ pmic_config_interface(PMIC_DCXO_CW00_CLR_ADDR,
+ PMIC_XO_EXTBUF4_MODE_MASK,
+ PMIC_XO_EXTBUF4_MODE_MASK,
+ PMIC_XO_EXTBUF4_MODE_SHIFT);
+ pmic_config_interface(PMIC_DCXO_CW00_CLR_ADDR,
+ PMIC_XO_EXTBUF4_EN_M_MASK,
+ PMIC_XO_EXTBUF4_EN_M_MASK,
+ PMIC_XO_EXTBUF4_EN_M_SHIFT);
+ }
+
+ if (CLK_BUF7_STATUS_PMIC == CLOCK_BUFFER_DISABLE) {
+ pmic_config_interface(PMIC_DCXO_CW09_CLR_ADDR,
+ PMIC_XO_EXTBUF7_MODE_MASK,
+ PMIC_XO_EXTBUF7_MODE_MASK,
+ PMIC_XO_EXTBUF7_MODE_SHIFT);
+ pmic_config_interface(PMIC_DCXO_CW09_CLR_ADDR,
+ PMIC_XO_EXTBUF7_EN_M_MASK,
+ PMIC_XO_EXTBUF7_EN_M_MASK,
+ PMIC_XO_EXTBUF7_EN_M_SHIFT);
+ }
+
+ /* Check if the setting is ok */
+ clk_buf_dump_clkbuf_log();
+#endif
+}
+
+static void clk_buf_init_pmic_wrap(void)
+{
+#ifndef CLKBUF_BRINGUP
+ u32 dcxo_en_flag = 0;
+
+ /* Setup PMIC_WRAP setting for XO2 & XO3 */
+ if (CLK_BUF2_STATUS_PMIC != CLOCK_BUFFER_DISABLE) {
+#ifdef CLKBUF_CONN_SUPPORT_CTRL_FROM_I1
+ clkbuf_writel(DCXO_CONN_ADR0, PMIC_DCXO_CW00_CLR_ADDR);
+ clkbuf_writel(DCXO_CONN_WDATA0,
+ PMIC_XO_EXTBUF2_EN_M_MASK << PMIC_XO_EXTBUF2_EN_M_SHIFT); /* bit5 = 0 */
+ clkbuf_writel(DCXO_CONN_ADR1, PMIC_DCXO_CW00_SET_ADDR);
+ clkbuf_writel(DCXO_CONN_WDATA1,
+ PMIC_XO_EXTBUF2_EN_M_MASK << PMIC_XO_EXTBUF2_EN_M_SHIFT); /* bit5 = 1 */
+#else
+ clkbuf_writel(DCXO_CONN_ADR0, PMIC_RG_SRCLKEN_IN3_EN_ADDR);
+ clkbuf_writel(DCXO_CONN_WDATA0,
+ 0 << PMIC_RG_SRCLKEN_IN3_EN_SHIFT); /* bit0 = 0 */
+ clkbuf_writel(DCXO_CONN_ADR1, PMIC_RG_SRCLKEN_IN3_EN_ADDR);
+ clkbuf_writel(DCXO_CONN_WDATA1,
+ 1 << PMIC_RG_SRCLKEN_IN3_EN_SHIFT); /* bit0 = 1 */
+#endif
+ dcxo_en_flag |= DCXO_CONN_ENABLE;
+ }
+
+ clkbuf_writel(DCXO_ENABLE, dcxo_en_flag);
+
+ clk_buf_warn("%s: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x%x/%x/%x/%x: dxco_en:%x\n",
+ __func__, clkbuf_readl(DCXO_CONN_ADR0),
+ clkbuf_readl(DCXO_CONN_WDATA0),
+ clkbuf_readl(DCXO_CONN_ADR1),
+ clkbuf_readl(DCXO_CONN_WDATA1),
+ clkbuf_readl(DCXO_ENABLE));
+#endif /* #ifndef CLKBUF_BRINGUP */
+}
+
+void mt_clkbuf_init(void)
+{
+ /* Co-TSX @PMIC */
+ clk_buf_init_pmic_clkbuf();
+#if MTK_SRCLKEN_RC_BT_ONLY || !defined(MTK_SRCLKEN_RC_SUPPORT)
+ clk_buf_init_pmic_wrap();
+#endif
+
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/dcm/dcm.c b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm.c
new file mode 100644
index 0000000..a44c890
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <debug.h>
+#include <platform/dcm.h>
+
+#include "dcm_ctrl.h"
+
+void mt_dcm_init(void)
+{
+ /* Return here when bringup to avoid all the DCM ctrl. */
+
+ dcm_infracfg_ao_infra_bus_dcm(true);
+ dcm_bcrm_infra_ao_infra_ao_bus_dcm(true);
+ dcm_security_ao_security_ao_dcm(true);
+ dcm_mp0_cpucfg_mcucfg_dcm(true);
+ dcm_misccfg_mcucfg_dcm(true);
+ dcm_misc1cfg_mcucfg_dcm(true);
+
+ /*
+ * Dram/GCE/AUDIO control their DCM themselves.
+ */
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.c b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.c
new file mode 100644
index 0000000..ad67dbb
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.c
@@ -0,0 +1,1041 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+/*
+ * This file is autogened from DE@0419.
+ */
+
+#include <platform/mt_typedefs.h>
+
+#include "dcm_ctrl.h"
+
+#define reg_read DRV_Reg32
+#define reg_write DRV_WriteReg32
+
+#if 0
+//TOPCKGEN don't have DCM
+#define TOPCKGEN_TOPCKGEN_DCM_REG0_MASK ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 2) | \
+ (0x1 << 5) | \
+ (0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x1 << 9))
+#define TOPCKGEN_TOPCKGEN_DCM_REG0_ON ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 5) | \
+ (0x0 << 6) | \
+ (0x0 << 7) | \
+ (0x0 << 8) | \
+ (0x0 << 9))
+#define TOPCKGEN_TOPCKGEN_DCM_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 5) | \
+ (0x0 << 6) | \
+ (0x0 << 7) | \
+ (0x0 << 8) | \
+ (0x0 << 9))
+
+bool dcm_topckgen_topckgen_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(CLK_SCP_CFG_0) &
+ TOPCKGEN_TOPCKGEN_DCM_REG0_MASK) ==
+ (unsigned int) TOPCKGEN_TOPCKGEN_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_topckgen_topckgen_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'topckgen_topckgen_dcm'" */
+ reg_write(CLK_SCP_CFG_0,
+ (reg_read(CLK_SCP_CFG_0) &
+ ~TOPCKGEN_TOPCKGEN_DCM_REG0_MASK) |
+ TOPCKGEN_TOPCKGEN_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'topckgen_topckgen_dcm'" */
+ reg_write(CLK_SCP_CFG_0,
+ (reg_read(CLK_SCP_CFG_0) &
+ ~TOPCKGEN_TOPCKGEN_DCM_REG0_MASK) |
+ TOPCKGEN_TOPCKGEN_DCM_REG0_OFF);
+ }
+}
+#endif
+
+#define INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK ((0x1 << 0) | \
+ (0x1 << 2))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG1_MASK ((0x1 << 0) | \
+ (0x1 << 21) | \
+ (0x1 << 22) | \
+ (0x1f << 23) | \
+ (0x1 << 28) | \
+ (0x1 << 29) | \
+ (0x1 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG2_MASK ((0x1 << 0) | \
+ (0x1f << 1) | \
+ (0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x7f << 9) | \
+ (0x1f << 16) | \
+ (0x1f << 21) | \
+ (0x1 << 26) | \
+ (0x1 << 27) | \
+ (0x1 << 28) | \
+ (0x1 << 29) | \
+ (0x1 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG3_MASK ((0x1 << 0) | \
+ (0x1f << 1) | \
+ (0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x1f << 16) | \
+ (0x1f << 21) | \
+ (0x1 << 26))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG4_MASK ((0xf << 0))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG5_MASK ((0x1 << 28))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG0_ON ((0x1 << 0) | \
+ (0x0 << 2))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG1_ON ((0x1 << 0) | \
+ (0x1 << 21) | \
+ (0x1 << 22) | \
+ (0x0 << 23) | \
+ (0x1 << 28) | \
+ (0x1 << 29) | \
+ (0x1 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG2_ON ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x0 << 9) | \
+ (0x0 << 16) | \
+ (0x1f << 21) | \
+ (0x0 << 26) | \
+ (0x1 << 27) | \
+ (0x0 << 28) | \
+ (0x0 << 29) | \
+ (0x0 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG3_ON ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x0 << 16) | \
+ (0x1f << 21) | \
+ (0x0 << 26))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG4_ON ((0x0 << 0))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG5_ON ((0x1 << 28))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 2))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG1_OFF ((0x0 << 0) | \
+ (0x0 << 21) | \
+ (0x0 << 22) | \
+ (0x0 << 23) | \
+ (0x0 << 28) | \
+ (0x0 << 29) | \
+ (0x0 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG2_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x0 << 9) | \
+ (0x0 << 16) | \
+ (0x1f << 21) | \
+ (0x0 << 26) | \
+ (0x1 << 27) | \
+ (0x0 << 28) | \
+ (0x0 << 29) | \
+ (0x0 << 31))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG3_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 6) | \
+ (0x1 << 7) | \
+ (0x1 << 8) | \
+ (0x0 << 16) | \
+ (0x1f << 21) | \
+ (0x0 << 26))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG4_OFF ((0x0 << 0))
+#define INFRACFG_AO_INFRA_BUS_DCM_REG5_OFF ((0x0 << 28))
+
+bool dcm_infracfg_ao_infra_bus_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(INFRA_BUS_DCM_CTRL) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
+ ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG1_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG1_ON);
+ ret &= ((reg_read(MEM_DCM_CTRL) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG2_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG2_ON);
+ ret &= ((reg_read(DFS_MEM_DCM_CTRL) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG3_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG3_ON);
+ ret &= ((reg_read(P2P_RX_CLK_ON) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG4_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG4_ON);
+ ret &= ((reg_read(INFRA_MISC) &
+ INFRACFG_AO_INFRA_BUS_DCM_REG5_MASK) ==
+ (unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG5_ON);
+
+ return ret;
+}
+
+void dcm_infracfg_ao_infra_bus_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'infracfg_ao_infra_bus_dcm'" */
+ reg_write(INFRA_BUS_DCM_CTRL,
+ (reg_read(INFRA_BUS_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
+ reg_write(PERI_BUS_DCM_CTRL,
+ (reg_read(PERI_BUS_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG1_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG1_ON);
+ reg_write(MEM_DCM_CTRL,
+ (reg_read(MEM_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG2_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG2_ON);
+ reg_write(DFS_MEM_DCM_CTRL,
+ (reg_read(DFS_MEM_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG3_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG3_ON);
+ reg_write(P2P_RX_CLK_ON,
+ (reg_read(P2P_RX_CLK_ON) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG4_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG4_ON);
+ reg_write(INFRA_MISC,
+ (reg_read(INFRA_MISC) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG5_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG5_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'infracfg_ao_infra_bus_dcm'" */
+ reg_write(INFRA_BUS_DCM_CTRL,
+ (reg_read(INFRA_BUS_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF);
+ reg_write(PERI_BUS_DCM_CTRL,
+ (reg_read(PERI_BUS_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG1_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG1_OFF);
+ reg_write(MEM_DCM_CTRL,
+ (reg_read(MEM_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG2_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG2_OFF);
+ reg_write(DFS_MEM_DCM_CTRL,
+ (reg_read(DFS_MEM_DCM_CTRL) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG3_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG3_OFF);
+ reg_write(P2P_RX_CLK_ON,
+ (reg_read(P2P_RX_CLK_ON) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG4_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG4_OFF);
+ reg_write(INFRA_MISC,
+ (reg_read(INFRA_MISC) &
+ ~INFRACFG_AO_INFRA_BUS_DCM_REG5_MASK) |
+ INFRACFG_AO_INFRA_BUS_DCM_REG5_OFF);
+ }
+}
+
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_MASK ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 19))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_MASK ((0x1f << 0) | \
+ (0x1 << 6) | \
+ (0x1 << 21))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_MASK ((0x1f << 0))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_MASK ((0x1 << 0) | \
+ (0x1 << 26))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_ON ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 19))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_ON ((0x0 << 0) | \
+ (0x1 << 6) | \
+ (0x1 << 21))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_ON ((0x0 << 0))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_ON ((0x1 << 0) | \
+ (0x1 << 26))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_OFF ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x0 << 19))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_OFF ((0x0 << 0) | \
+ (0x0 << 6) | \
+ (0x0 << 21))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_OFF ((0x0 << 0))
+#define BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_OFF ((0x0 << 0) | \
+ (0x0 << 26))
+
+bool dcm_bcrm_infra_ao_infra_ao_bus_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_MASK) ==
+ (unsigned int) BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_ON);
+ ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_MASK) ==
+ (unsigned int) BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_ON);
+ ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_MASK) ==
+ (unsigned int) BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_ON);
+ ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6) &
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_MASK) ==
+ (unsigned int) BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_ON);
+
+ return ret;
+}
+
+void dcm_bcrm_infra_ao_infra_ao_bus_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'bcrm_infra_ao_infra_ao_bus_dcm'" */
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_ON);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_ON);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_ON);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'bcrm_infra_ao_infra_ao_bus_dcm'" */
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG0_OFF);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG1_OFF);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG2_OFF);
+ reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6,
+ (reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6) &
+ ~BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_MASK) |
+ BCRM_INFRA_AO_INFRA_AO_BUS_DCM_REG3_OFF);
+ }
+}
+
+#define SECURITY_AO_SECURITY_AO_DCM_REG0_MASK ((0xffff << 0))
+#define SECURITY_AO_SECURITY_AO_DCM_REG1_MASK ((0x1 << 0))
+#define SECURITY_AO_SECURITY_AO_DCM_REG0_ON ((0xffff << 0))
+#define SECURITY_AO_SECURITY_AO_DCM_REG1_ON ((0x1 << 0))
+#define SECURITY_AO_SECURITY_AO_DCM_REG0_OFF ((0xffff << 0))
+#define SECURITY_AO_SECURITY_AO_DCM_REG1_OFF ((0x0 << 0))
+
+bool dcm_security_ao_security_ao_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(DXCC_NEW_HWDCM_CFG) &
+ SECURITY_AO_SECURITY_AO_DCM_REG0_MASK) ==
+ (unsigned int) SECURITY_AO_SECURITY_AO_DCM_REG0_ON);
+ ret &= ((reg_read(MCU_LOCAL_DCM_CTL) &
+ SECURITY_AO_SECURITY_AO_DCM_REG1_MASK) ==
+ (unsigned int) SECURITY_AO_SECURITY_AO_DCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_security_ao_security_ao_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'security_ao_security_ao_dcm'" */
+ reg_write(DXCC_NEW_HWDCM_CFG,
+ (reg_read(DXCC_NEW_HWDCM_CFG) &
+ ~SECURITY_AO_SECURITY_AO_DCM_REG0_MASK) |
+ SECURITY_AO_SECURITY_AO_DCM_REG0_ON);
+ reg_write(MCU_LOCAL_DCM_CTL,
+ (reg_read(MCU_LOCAL_DCM_CTL) &
+ ~SECURITY_AO_SECURITY_AO_DCM_REG1_MASK) |
+ SECURITY_AO_SECURITY_AO_DCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'security_ao_security_ao_dcm'" */
+ reg_write(DXCC_NEW_HWDCM_CFG,
+ (reg_read(DXCC_NEW_HWDCM_CFG) &
+ ~SECURITY_AO_SECURITY_AO_DCM_REG0_MASK) |
+ SECURITY_AO_SECURITY_AO_DCM_REG0_OFF);
+ reg_write(MCU_LOCAL_DCM_CTL,
+ (reg_read(MCU_LOCAL_DCM_CTL) &
+ ~SECURITY_AO_SECURITY_AO_DCM_REG1_MASK) |
+ SECURITY_AO_SECURITY_AO_DCM_REG1_OFF);
+ }
+}
+
+#define MP0_CPUCFG_MCUCFG_DCM_REG0_MASK ((0xf << 0))
+#define MP0_CPUCFG_MCUCFG_DCM_REG1_MASK ((0x3 << 0))
+#define MP0_CPUCFG_MCUCFG_DCM_REG0_ON ((0x0 << 0))
+#define MP0_CPUCFG_MCUCFG_DCM_REG1_ON ((0x1 << 0))
+#define MP0_CPUCFG_MCUCFG_DCM_REG0_OFF ((0xf << 0))
+#define MP0_CPUCFG_MCUCFG_DCM_REG1_OFF ((0x0 << 0))
+
+bool dcm_mp0_cpucfg_mcucfg_dcm_is_on(void)
+{
+ bool ret = true;
+
+ /* ret &= ((reg_read(DBG_PWR_CTRL) &
+ MP0_CPUCFG_MCUCFG_DCM_REG0_MASK) ==
+ (unsigned int) MP0_CPUCFG_MCUCFG_DCM_REG0_ON); */
+ ret &= ((reg_read(CPUSYS_RGU_SYNC_DCM) &
+ MP0_CPUCFG_MCUCFG_DCM_REG1_MASK) ==
+ (unsigned int) MP0_CPUCFG_MCUCFG_DCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_mp0_cpucfg_mcucfg_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp0_cpucfg_mcucfg_dcm'" */
+ /* reg_write(DBG_PWR_CTRL,
+ (reg_read(DBG_PWR_CTRL) &
+ ~MP0_CPUCFG_MCUCFG_DCM_REG0_MASK) |
+ MP0_CPUCFG_MCUCFG_DCM_REG0_ON); */
+ reg_write(CPUSYS_RGU_SYNC_DCM,
+ (reg_read(CPUSYS_RGU_SYNC_DCM) &
+ ~MP0_CPUCFG_MCUCFG_DCM_REG1_MASK) |
+ MP0_CPUCFG_MCUCFG_DCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp0_cpucfg_mcucfg_dcm'" */
+ /*reg_write(DBG_PWR_CTRL,
+ (reg_read(DBG_PWR_CTRL) &
+ ~MP0_CPUCFG_MCUCFG_DCM_REG0_MASK) |
+ MP0_CPUCFG_MCUCFG_DCM_REG0_OFF);*/
+ reg_write(CPUSYS_RGU_SYNC_DCM,
+ (reg_read(CPUSYS_RGU_SYNC_DCM) &
+ ~MP0_CPUCFG_MCUCFG_DCM_REG1_MASK) |
+ MP0_CPUCFG_MCUCFG_DCM_REG1_OFF);
+ }
+}
+
+#define MISCCFG_MCUCFG_DCM_REG0_MASK ((0x1 << 0))
+#define MISCCFG_MCUCFG_DCM_REG1_MASK ((0x1 << 8))
+#define MISCCFG_MCUCFG_DCM_REG2_MASK ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 3) | \
+ (0x1 << 4) | \
+ (0x1 << 5) | \
+ (0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 16) | \
+ (0x1 << 18) | \
+ (0x1 << 21) | \
+ (0x1 << 23) | \
+ (0x1 << 24) | \
+ (0x1 << 25))
+#define MISCCFG_MCUCFG_DCM_REG3_MASK ((0x1 << 0))
+#define MISCCFG_MCUCFG_DCM_REG4_MASK ((0x1 << 0) | \
+ (0x1 << 1))
+#define MISCCFG_MCUCFG_DCM_REG0_ON ((0x1 << 0))
+#define MISCCFG_MCUCFG_DCM_REG1_ON ((0x1 << 8))
+#define MISCCFG_MCUCFG_DCM_REG2_ON ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 3) | \
+ (0x1 << 4) | \
+ (0x1 << 5) | \
+ (0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 16) | \
+ (0x1 << 18) | \
+ (0x1 << 21) | \
+ (0x1 << 23) | \
+ (0x1 << 24) | \
+ (0x1 << 25))
+#define MISCCFG_MCUCFG_DCM_REG3_ON ((0x1 << 0))
+#define MISCCFG_MCUCFG_DCM_REG4_ON ((0x1 << 0) | \
+ (0x1 << 1))
+#define MISCCFG_MCUCFG_DCM_REG0_OFF ((0x0 << 0))
+#define MISCCFG_MCUCFG_DCM_REG1_OFF ((0x0 << 8))
+#define MISCCFG_MCUCFG_DCM_REG2_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 3) | \
+ (0x0 << 4) | \
+ (0x0 << 5) | \
+ (0x0 << 8) | \
+ (0x0 << 9) | \
+ (0x0 << 11) | \
+ (0x0 << 12) | \
+ (0x0 << 16) | \
+ (0x0 << 18) | \
+ (0x0 << 21) | \
+ (0x0 << 23) | \
+ (0x0 << 24) | \
+ (0x0 << 25))
+#define MISCCFG_MCUCFG_DCM_REG3_OFF ((0x0 << 0))
+#define MISCCFG_MCUCFG_DCM_REG4_OFF ((0x0 << 0) | \
+ (0x0 << 1))
+
+bool dcm_misccfg_mcucfg_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(L2C_SRAM_CTRL) &
+ MISCCFG_MCUCFG_DCM_REG0_MASK) ==
+ (unsigned int) MISCCFG_MCUCFG_DCM_REG0_ON);
+ ret &= ((reg_read(CCI_CLK_CTRL) &
+ MISCCFG_MCUCFG_DCM_REG1_MASK) ==
+ (unsigned int) MISCCFG_MCUCFG_DCM_REG1_ON);
+ ret &= ((reg_read(BUS_FABRIC_DCM_CTRL) &
+ MISCCFG_MCUCFG_DCM_REG2_MASK) ==
+ (unsigned int) MISCCFG_MCUCFG_DCM_REG2_ON);
+ ret &= ((reg_read(MCU_MISC_DCM_CTRL) &
+ MISCCFG_MCUCFG_DCM_REG3_MASK) ==
+ (unsigned int) MISCCFG_MCUCFG_DCM_REG3_ON);
+ ret &= ((reg_read(MP_GIC_RGU_SYNC_DCM) &
+ MISCCFG_MCUCFG_DCM_REG4_MASK) ==
+ (unsigned int) MISCCFG_MCUCFG_DCM_REG4_ON);
+
+ return ret;
+}
+
+void dcm_misccfg_mcucfg_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'misccfg_mcucfg_dcm'" */
+ reg_write(L2C_SRAM_CTRL,
+ (reg_read(L2C_SRAM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG0_MASK) |
+ MISCCFG_MCUCFG_DCM_REG0_ON);
+ reg_write(CCI_CLK_CTRL,
+ (reg_read(CCI_CLK_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG1_MASK) |
+ MISCCFG_MCUCFG_DCM_REG1_ON);
+ reg_write(BUS_FABRIC_DCM_CTRL,
+ (reg_read(BUS_FABRIC_DCM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG2_MASK) |
+ MISCCFG_MCUCFG_DCM_REG2_ON);
+ reg_write(MCU_MISC_DCM_CTRL,
+ (reg_read(MCU_MISC_DCM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG3_MASK) |
+ MISCCFG_MCUCFG_DCM_REG3_ON);
+ reg_write(MP_GIC_RGU_SYNC_DCM,
+ (reg_read(MP_GIC_RGU_SYNC_DCM) &
+ ~MISCCFG_MCUCFG_DCM_REG4_MASK) |
+ MISCCFG_MCUCFG_DCM_REG4_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'misccfg_mcucfg_dcm'" */
+ reg_write(L2C_SRAM_CTRL,
+ (reg_read(L2C_SRAM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG0_MASK) |
+ MISCCFG_MCUCFG_DCM_REG0_OFF);
+ reg_write(CCI_CLK_CTRL,
+ (reg_read(CCI_CLK_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG1_MASK) |
+ MISCCFG_MCUCFG_DCM_REG1_OFF);
+ reg_write(BUS_FABRIC_DCM_CTRL,
+ (reg_read(BUS_FABRIC_DCM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG2_MASK) |
+ MISCCFG_MCUCFG_DCM_REG2_OFF);
+ reg_write(MCU_MISC_DCM_CTRL,
+ (reg_read(MCU_MISC_DCM_CTRL) &
+ ~MISCCFG_MCUCFG_DCM_REG3_MASK) |
+ MISCCFG_MCUCFG_DCM_REG3_OFF);
+ reg_write(MP_GIC_RGU_SYNC_DCM,
+ (reg_read(MP_GIC_RGU_SYNC_DCM) &
+ ~MISCCFG_MCUCFG_DCM_REG4_MASK) |
+ MISCCFG_MCUCFG_DCM_REG4_OFF);
+ }
+}
+
+#define MISC1CFG_MCUCFG_DCM_REG0_MASK ((0xffff << 16))
+#define MISC1CFG_MCUCFG_DCM_REG0_ON ((0xffff << 16))
+#define MISC1CFG_MCUCFG_DCM_REG0_OFF ((0x0 << 16))
+
+bool dcm_misc1cfg_mcucfg_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(MCSIA_DCM_EN) &
+ MISC1CFG_MCUCFG_DCM_REG0_MASK) ==
+ (unsigned int) MISC1CFG_MCUCFG_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_misc1cfg_mcucfg_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'misc1cfg_mcucfg_dcm'" */
+ reg_write(MCSIA_DCM_EN,
+ (reg_read(MCSIA_DCM_EN) &
+ ~MISC1CFG_MCUCFG_DCM_REG0_MASK) |
+ MISC1CFG_MCUCFG_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'misc1cfg_mcucfg_dcm'" */
+ reg_write(MCSIA_DCM_EN,
+ (reg_read(MCSIA_DCM_EN) &
+ ~MISC1CFG_MCUCFG_DCM_REG0_MASK) |
+ MISC1CFG_MCUCFG_DCM_REG0_OFF);
+ }
+}
+
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_MASK ((0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 10) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 13) | \
+ (0x1 << 14) | \
+ (0x1 << 15) | \
+ (0x1 << 16) | \
+ (0x1 << 17) | \
+ (0x1 << 19))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_MASK ((0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x1f << 21) | \
+ (0x1 << 26))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_MASK ((0x1 << 26) | \
+ (0x1 << 27))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_ON ((0x0 << 8) | \
+ (0x0 << 9) | \
+ (0x0 << 10) | \
+ (0x0 << 11) | \
+ (0x0 << 12) | \
+ (0x0 << 13) | \
+ (0x0 << 14) | \
+ (0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 19))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_ON ((0x0 << 6) | \
+ (0x0 << 7) | \
+ (0x8 << 21) | \
+ (0x0 << 26))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_ON ((0x0 << 26) | \
+ (0x0 << 27))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_OFF ((0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 10) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 13) | \
+ (0x1 << 14) | \
+ (0x1 << 15) | \
+ (0x1 << 16) | \
+ (0x1 << 17) | \
+ (0x1 << 19))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_OFF ((0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x0 << 21) | \
+ (0x0 << 26))
+#define DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_OFF ((0x1 << 26) | \
+ (0x1 << 27))
+
+bool dcm_dramc_ch0_top0_ddrphy_wo_pll_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_MASK) ==
+ (unsigned int) DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_ON);
+ ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_MASK) ==
+ (unsigned int) DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_ON);
+ ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_MASK) ==
+ (unsigned int) DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_dramc_ch0_top0_ddrphy_wo_pll_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'dramc_ch0_top0_ddrphy_wo_pll_dcm'" */
+ reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL0,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_ON);
+ reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL2,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_ON);
+ reg_write(DRAMC_CH0_TOP0_MISC_CTRL3,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'dramc_ch0_top0_ddrphy_wo_pll_dcm'" */
+ reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL0,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG0_OFF);
+ reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL2,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG1_OFF);
+ reg_write(DRAMC_CH0_TOP0_MISC_CTRL3,
+ (reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
+ ~DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_MASK) |
+ DRAMC_CH0_TOP0_DDRPHY_WO_PLL_DCM_REG2_OFF);
+ }
+}
+
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_MASK ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 2) | \
+ (0x1 << 26) | \
+ (0x1 << 30) | \
+ (0x1 << 31))
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_MASK ((0x1 << 31))
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_ON ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 2) | \
+ (0x0 << 26) | \
+ (0x1 << 30) | \
+ (0x1 << 31))
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_ON ((0x1 << 31))
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x1 << 26) | \
+ (0x0 << 30) | \
+ (0x0 << 31))
+#define DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_OFF ((0x0 << 31))
+
+bool dcm_dramc_ch0_top1_dramc_ch0_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_MASK) ==
+ (unsigned int) DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_ON);
+ ret &= ((reg_read(DRAMC_CH0_TOP1_CLKAR) &
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_MASK) ==
+ (unsigned int) DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_dramc_ch0_top1_dramc_ch0_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'dramc_ch0_top1_dramc_ch0_dcm'" */
+ reg_write(DRAMC_CH0_TOP1_DRAMC_PD_CTRL,
+ (reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
+ ~DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_MASK) |
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_ON);
+ reg_write(DRAMC_CH0_TOP1_CLKAR,
+ (reg_read(DRAMC_CH0_TOP1_CLKAR) &
+ ~DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_MASK) |
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'dramc_ch0_top1_dramc_ch0_dcm'" */
+ reg_write(DRAMC_CH0_TOP1_DRAMC_PD_CTRL,
+ (reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
+ ~DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_MASK) |
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG0_OFF);
+ reg_write(DRAMC_CH0_TOP1_CLKAR,
+ (reg_read(DRAMC_CH0_TOP1_CLKAR) &
+ ~DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_MASK) |
+ DRAMC_CH0_TOP1_DRAMC_CH0_DCM_REG1_OFF);
+ }
+}
+
+#define CHN0_EMI_CHN0_EMI_DCM_REG0_MASK ((0xff << 24))
+#define CHN0_EMI_CHN0_EMI_DCM_REG0_ON ((0x0 << 24))
+#define CHN0_EMI_CHN0_EMI_DCM_REG0_OFF ((0xff << 24))
+
+bool dcm_chn0_emi_chn0_emi_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(CHN0_EMI_CHN_EMI_CONB) &
+ CHN0_EMI_CHN0_EMI_DCM_REG0_MASK) ==
+ (unsigned int) CHN0_EMI_CHN0_EMI_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_chn0_emi_chn0_emi_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'chn0_emi_chn0_emi_dcm'" */
+ reg_write(CHN0_EMI_CHN_EMI_CONB,
+ (reg_read(CHN0_EMI_CHN_EMI_CONB) &
+ ~CHN0_EMI_CHN0_EMI_DCM_REG0_MASK) |
+ CHN0_EMI_CHN0_EMI_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'chn0_emi_chn0_emi_dcm'" */
+ reg_write(CHN0_EMI_CHN_EMI_CONB,
+ (reg_read(CHN0_EMI_CHN_EMI_CONB) &
+ ~CHN0_EMI_CHN0_EMI_DCM_REG0_MASK) |
+ CHN0_EMI_CHN0_EMI_DCM_REG0_OFF);
+ }
+}
+
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_MASK ((0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 10) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 13) | \
+ (0x1 << 14) | \
+ (0x1 << 15) | \
+ (0x1 << 16) | \
+ (0x1 << 17) | \
+ (0x1 << 19))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_MASK ((0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x1f << 21) | \
+ (0x1 << 26))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_MASK ((0x1 << 26) | \
+ (0x1 << 27))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_ON ((0x0 << 8) | \
+ (0x0 << 9) | \
+ (0x0 << 10) | \
+ (0x0 << 11) | \
+ (0x0 << 12) | \
+ (0x0 << 13) | \
+ (0x0 << 14) | \
+ (0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 19))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_ON ((0x0 << 6) | \
+ (0x0 << 7) | \
+ (0x8 << 21) | \
+ (0x0 << 26))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_ON ((0x0 << 26) | \
+ (0x0 << 27))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_OFF ((0x1 << 8) | \
+ (0x1 << 9) | \
+ (0x1 << 10) | \
+ (0x1 << 11) | \
+ (0x1 << 12) | \
+ (0x1 << 13) | \
+ (0x1 << 14) | \
+ (0x1 << 15) | \
+ (0x1 << 16) | \
+ (0x1 << 17) | \
+ (0x1 << 19))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_OFF ((0x1 << 6) | \
+ (0x1 << 7) | \
+ (0x0 << 21) | \
+ (0x0 << 26))
+#define DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_OFF ((0x1 << 26) | \
+ (0x1 << 27))
+
+bool dcm_dramc_ch1_top0_ddrphy_wo_pll_chb_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB) &
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_MASK) ==
+ (unsigned int) DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_ON);
+ ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB) &
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_MASK) ==
+ (unsigned int) DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_ON);
+ ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CTRL3_CHB) &
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_MASK) ==
+ (unsigned int) DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_dramc_ch1_top0_ddrphy_wo_pll_chb_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'dramc_ch1_top0_ddrphy_wo_pll_chb_dcm'" */
+ reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_ON);
+ reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_ON);
+ reg_write(DRAMC_CH1_TOP0_MISC_CTRL3_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CTRL3_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'dramc_ch1_top0_ddrphy_wo_pll_chb_dcm'" */
+ reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG0_OFF);
+ reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG1_OFF);
+ reg_write(DRAMC_CH1_TOP0_MISC_CTRL3_CHB,
+ (reg_read(DRAMC_CH1_TOP0_MISC_CTRL3_CHB) &
+ ~DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_MASK) |
+ DRAMC_CH1_TOP0_DDRPHY_WO_PLL_CHB_DCM_REG2_OFF);
+ }
+}
+
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_MASK ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 2) | \
+ (0x1 << 26) | \
+ (0x1 << 30) | \
+ (0x1 << 31))
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_MASK ((0x1 << 31))
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_ON ((0x1 << 0) | \
+ (0x1 << 1) | \
+ (0x1 << 2) | \
+ (0x0 << 26) | \
+ (0x1 << 30) | \
+ (0x1 << 31))
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_ON ((0x1 << 31))
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x1 << 26) | \
+ (0x0 << 30) | \
+ (0x0 << 31))
+#define DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_OFF ((0x0 << 31))
+
+bool dcm_dramc_ch1_top1_dramc_ch1_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB) &
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_MASK) ==
+ (unsigned int) DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_ON);
+ ret &= ((reg_read(DRAMC_CH1_TOP1_CLKAR_CHB) &
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_MASK) ==
+ (unsigned int) DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_dramc_ch1_top1_dramc_ch1_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'dramc_ch1_top1_dramc_ch1_dcm'" */
+ reg_write(DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB,
+ (reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB) &
+ ~DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_MASK) |
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_ON);
+ reg_write(DRAMC_CH1_TOP1_CLKAR_CHB,
+ (reg_read(DRAMC_CH1_TOP1_CLKAR_CHB) &
+ ~DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_MASK) |
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'dramc_ch1_top1_dramc_ch1_dcm'" */
+ reg_write(DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB,
+ (reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB) &
+ ~DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_MASK) |
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG0_OFF);
+ reg_write(DRAMC_CH1_TOP1_CLKAR_CHB,
+ (reg_read(DRAMC_CH1_TOP1_CLKAR_CHB) &
+ ~DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_MASK) |
+ DRAMC_CH1_TOP1_DRAMC_CH1_DCM_REG1_OFF);
+ }
+}
+
+#if 0
+#define GCE_GCE_DCM_REG0_MASK ((0xffff << 0))
+#define GCE_GCE_DCM_REG0_ON ((0xffff << 0))
+#define GCE_GCE_DCM_REG0_OFF ((0xffff << 0))
+
+bool dcm_gce_gce_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(GCE_CTL_INT0) &
+ GCE_GCE_DCM_REG0_MASK) ==
+ (unsigned int) GCE_GCE_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_gce_gce_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'gce_gce_dcm'" */
+ reg_write(GCE_CTL_INT0,
+ (reg_read(GCE_CTL_INT0) &
+ ~GCE_GCE_DCM_REG0_MASK) |
+ GCE_GCE_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'gce_gce_dcm'" */
+ reg_write(GCE_CTL_INT0,
+ (reg_read(GCE_CTL_INT0) &
+ ~GCE_GCE_DCM_REG0_MASK) |
+ GCE_GCE_DCM_REG0_OFF);
+ }
+}
+
+#define AUDIO_AFE_DCM_REG0_MASK ((0x1 << 29) | \
+ (0x1 << 30))
+#define AUDIO_AFE_DCM_REG0_ON ((0x1 << 29) | \
+ (0x1 << 30))
+#define AUDIO_AFE_DCM_REG0_OFF ((0x0 << 29) | \
+ (0x0 << 30))
+
+bool dcm_audio_afe_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((reg_read(AUDIO_TOP_CON0) &
+ AUDIO_AFE_DCM_REG0_MASK) ==
+ (unsigned int) AUDIO_AFE_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_audio_afe_dcm(int on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'audio_afe_dcm'" */
+ reg_write(AUDIO_TOP_CON0,
+ (reg_read(AUDIO_TOP_CON0) &
+ ~AUDIO_AFE_DCM_REG0_MASK) |
+ AUDIO_AFE_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'audio_afe_dcm'" */
+ reg_write(AUDIO_TOP_CON0,
+ (reg_read(AUDIO_TOP_CON0) &
+ ~AUDIO_AFE_DCM_REG0_MASK) |
+ AUDIO_AFE_DCM_REG0_OFF);
+ }
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.h b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.h
new file mode 100644
index 0000000..cb2ea56
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/dcm/dcm_ctrl.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+/*
+ * This file is autogened from DE@0419.
+ */
+#ifndef _DCM_CTRL_H_
+#define _DCM_CTRL_H_
+
+#include <stdbool.h> /* For true/false. */
+#include "platform/mt_reg_base.h"
+
+/* Base */
+#define INFRACFG_AO_BASE INFRACFG_BASE//0x10001000
+#define BCRM_INFRA_AO_BASE bcrm_INFRA_AO_wrapper_base //0x10015000
+#define SECURITY_AO_BASE (IO_PHYS + 0x1a000) //0x1001a000
+#define MP0_CPUCFG_BASE MCUSYS_CFGREG_BASE //0x10200000
+#define MISCCFG_BASE (IO_PHYS + 0x200400)//0x10200400
+#define MISC1CFG_BASE (IO_PHYS + 0x200800) //0x10200800
+#define DRAMC_CH0_TOP0_BASE (IO_PHYS + 0x228000)//0x10228000
+#define DRAMC_CH0_TOP1_BASE (IO_PHYS + 0x22a000)//0x1022a000
+#define CHN0_EMI_BASE (IO_PHYS + 0x22d000)//0x1022d000
+#define DRAMC_CH1_TOP0_BASE (IO_PHYS + 0x230000)//0x10230000
+#define DRAMC_CH1_TOP1_BASE (IO_PHYS + 0x232000)//0x10232000
+//#define GCE_BASE (IO_PHYS + 0x238000)//0x10238000
+//#define AUDIO_BASE (IO_PHYS + 0x1220000)//0x11220000
+//#define TOPCKGEN_BASE CKSYS_BASE
+
+/* Register Definition */
+#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70)
+#define PERI_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x74)
+#define MEM_DCM_CTRL (INFRACFG_AO_BASE + 0x78)
+#define DFS_MEM_DCM_CTRL (INFRACFG_AO_BASE + 0x7c)
+#define P2P_RX_CLK_ON (INFRACFG_AO_BASE + 0xa0)
+#define INFRA_MISC (INFRACFG_AO_BASE + 0xf00)
+#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0 (BCRM_INFRA_AO_BASE + 0x7c)
+#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1 (BCRM_INFRA_AO_BASE + 0x80)
+#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2 (BCRM_INFRA_AO_BASE + 0x84)
+#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_6 (BCRM_INFRA_AO_BASE + 0x94)
+#define DXCC_NEW_HWDCM_CFG (SECURITY_AO_BASE + 0x208)
+#define MCU_LOCAL_DCM_CTL (SECURITY_AO_BASE + 0x634)
+#define DBG_PWR_CTRL (MP0_CPUCFG_BASE + 0x68)
+#define CPUSYS_RGU_SYNC_DCM (MP0_CPUCFG_BASE + 0x88)
+#define L2C_SRAM_CTRL (MISCCFG_BASE + 0x248)
+#define CCI_CLK_CTRL (MISCCFG_BASE + 0x260)
+#define BUS_FABRIC_DCM_CTRL (MISCCFG_BASE + 0x268)
+#define MCU_MISC_DCM_CTRL (MISCCFG_BASE + 0x26c)
+#define MP_GIC_RGU_SYNC_DCM (MISCCFG_BASE + 0x358)
+#define MCSIA_DCM_EN (MISC1CFG_BASE + 0x360)
+#define DRAMC_CH0_TOP0_MISC_CG_CTRL0 (DRAMC_CH0_TOP0_BASE + 0x284)
+#define DRAMC_CH0_TOP0_MISC_CG_CTRL2 (DRAMC_CH0_TOP0_BASE + 0x28c)
+#define DRAMC_CH0_TOP0_MISC_CTRL3 (DRAMC_CH0_TOP0_BASE + 0x2a8)
+#define DRAMC_CH0_TOP1_DRAMC_PD_CTRL (DRAMC_CH0_TOP1_BASE + 0x38)
+#define DRAMC_CH0_TOP1_CLKAR (DRAMC_CH0_TOP1_BASE + 0x3c)
+#define CHN0_EMI_CHN_EMI_CONB (CHN0_EMI_BASE + 0x8)
+#define DRAMC_CH1_TOP0_MISC_CG_CTRL0_CHB (DRAMC_CH1_TOP0_BASE + 0x284)
+#define DRAMC_CH1_TOP0_MISC_CG_CTRL2_CHB (DRAMC_CH1_TOP0_BASE + 0x28c)
+#define DRAMC_CH1_TOP0_MISC_CTRL3_CHB (DRAMC_CH1_TOP0_BASE + 0x2a8)
+#define DRAMC_CH1_TOP1_DRAMC_PD_CTRL_CHB (DRAMC_CH1_TOP1_BASE + 0x38)
+#define DRAMC_CH1_TOP1_CLKAR_CHB (DRAMC_CH1_TOP1_BASE + 0x3c)
+//#define GCE_CTL_INT0 (GCE_BASE + 0xf0)
+//#define AUDIO_TOP_CON0 (AUDIO_BASE + 0x0)
+//#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
+
+/* TOPCKGEN */
+//bool dcm_topckgen_topckgen_dcm_is_on(void);
+//void dcm_topckgen_topckgen_dcm(int on);
+/* INFRACFG_AO */
+bool dcm_infracfg_ao_infra_bus_dcm_is_on(void);
+void dcm_infracfg_ao_infra_bus_dcm(int on);
+/* BCRM_INFRA_AO */
+bool dcm_bcrm_infra_ao_infra_ao_bus_dcm_is_on(void);
+void dcm_bcrm_infra_ao_infra_ao_bus_dcm(int on);
+/* SECURITY_AO */
+bool dcm_security_ao_security_ao_dcm_is_on(void);
+void dcm_security_ao_security_ao_dcm(int on);
+/* MP0_CPUCFG */
+bool dcm_mp0_cpucfg_mcucfg_dcm_is_on(void);
+void dcm_mp0_cpucfg_mcucfg_dcm(int on);
+/* MISCCFG */
+bool dcm_misccfg_mcucfg_dcm_is_on(void);
+void dcm_misccfg_mcucfg_dcm(int on);
+/* MISC1CFG */
+bool dcm_misc1cfg_mcucfg_dcm_is_on(void);
+void dcm_misc1cfg_mcucfg_dcm(int on);
+/* DRAMC_CH0_TOP0 */
+bool dcm_dramc_ch0_top0_ddrphy_wo_pll_dcm_is_on(void);
+void dcm_dramc_ch0_top0_ddrphy_wo_pll_dcm(int on);
+/* DRAMC_CH0_TOP1 */
+bool dcm_dramc_ch0_top1_dramc_ch0_dcm_is_on(void);
+void dcm_dramc_ch0_top1_dramc_ch0_dcm(int on);
+/* CHN0_EMI */
+bool dcm_chn0_emi_chn0_emi_dcm_is_on(void);
+void dcm_chn0_emi_chn0_emi_dcm(int on);
+/* DRAMC_CH1_TOP0 */
+bool dcm_dramc_ch1_top0_ddrphy_wo_pll_chb_dcm_is_on(void);
+void dcm_dramc_ch1_top0_ddrphy_wo_pll_chb_dcm(int on);
+/* DRAMC_CH1_TOP1 */
+bool dcm_dramc_ch1_top1_dramc_ch1_dcm_is_on(void);
+void dcm_dramc_ch1_top1_dramc_ch1_dcm(int on);
+#if 0
+/* GCE */
+bool dcm_gce_gce_dcm_is_on(void);
+void dcm_gce_gce_dcm(int on);
+/* AUDIO */
+bool dcm_audio_afe_dcm_is_on(void);
+void dcm_audio_afe_dcm(int on);
+#endif
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/emi/emi_mpu_v1.c b/src/bsp/lk/platform/mt2731/drivers/emi/emi_mpu_v1.c
new file mode 100644
index 0000000..883afe3
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/emi/emi_mpu_v1.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <debug.h>
+#include <platform/emi_mpu_v1.h>
+#include <platform/emi_hw.h>
+#include <sys/types.h>
+
+#if ARCH_ARM64
+#define MTK_SIP_SMC_AARCH_BIT 0x40000000
+#else
+#define MTK_SIP_SMC_AARCH_BIT 0x00000000
+#endif
+
+#define MTK_SIP_KERNEL_EMIMPU_SET \
+ (0x82000262 | MTK_SIP_SMC_AARCH_BIT)
+#define MTK_SIP_KERNEL_EMIMPU_CLEAR \
+ (0x82000263 | MTK_SIP_SMC_AARCH_BIT)
+
+#if ARCH_ARM64
+#define LOCAL_REG_SET_DECLARE \
+ register size_t reg0 __asm__("x0") = function_id; \
+ register size_t reg1 __asm__("x1") = arg0; \
+ register size_t reg2 __asm__("x2") = arg1; \
+ register size_t reg3 __asm__("x3") = arg2; \
+ register size_t reg4 __asm__("x4") = arg3; \
+ size_t ret
+#else
+#define LOCAL_REG_SET_DECLARE \
+ register size_t reg0 __asm__("r0") = function_id; \
+ register size_t reg1 __asm__("r1") = arg0; \
+ register size_t reg2 __asm__("r2") = arg1; \
+ register size_t reg3 __asm__("r3") = arg2; \
+ register size_t reg4 __asm__("r4") = arg3; \
+ size_t ret
+#endif
+
+static size_t _mt_secure_call_all(size_t function_id,
+ size_t arg0, size_t arg1, size_t arg2,
+ size_t arg3, size_t *r1, size_t *r2, size_t *r3)
+{
+ LOCAL_REG_SET_DECLARE;
+
+#if ARCH_ARM64
+ __asm__ volatile ("smc #0x0\n" : "+r"(reg0),
+ "+r"(reg1), "+r"(reg2), "+r"(reg3), "+r"(reg4));
+#else
+ __asm__ volatile ("smc #0x0\n" : "+r"(reg0),
+ "+r"(reg1), "+r"(reg2), "+r"(reg3), "+r"(reg4));
+#endif
+ ret = reg0;
+ if (r1 != NULL)
+ *r1 = reg1;
+ if (r2 != NULL)
+ *r2 = reg2;
+ if (r3 != NULL)
+ *r3 = reg3;
+ return ret;
+}
+
+#define emi_mpu_smc_set(start, end, apc, r1, r2, r3) \
+ _mt_secure_call_all(MTK_SIP_KERNEL_EMIMPU_SET, start, end, apc, 0, r1, r2, r3)
+#define emi_mpu_smc_clear(region, r1, r2, r3) \
+ _mt_secure_call_all(MTK_SIP_KERNEL_EMIMPU_CLEAR, region, 0, 0, 0, r1, r2, r3)
+
+int emi_mpu_set_protection(struct emi_region_info_t *region_info)
+{
+ unsigned int start, end;
+ int dgroup, i, ret;
+ size_t r1, r2, r3;
+
+ start = (unsigned int)(region_info->start >> EMI_MPU_ALIGN_BITS) |
+ (region_info->region << 24);
+
+ dprintf(ALWAYS, "LK emi_mpu_set_protection start:%llx end=%llx region=%u ",
+ region_info->start, region_info->end, region_info->region);
+
+ for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
+ end = (unsigned int)(region_info->end >> EMI_MPU_ALIGN_BITS) |
+ (i << 24);
+ ret = emi_mpu_smc_set(start, end, region_info->apc[i], &r1, &r2, &r3);
+ dprintf(ALWAYS, "EMI MPU ret = %d\n", ret);
+ }
+ return 0;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/gce/mtk_gce.c b/src/bsp/lk/platform/mt2731/drivers/gce/mtk_gce.c
new file mode 100644
index 0000000..ee16afb
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/gce/mtk_gce.c
@@ -0,0 +1,114 @@
+#include <debug.h>
+#include <err.h>
+#include <reg.h>
+#include <string.h>
+#if WITH_KERNEL_VM
+#include <kernel/vm.h>
+#else
+#include <kernel/novm.h>
+#endif
+#include <platform.h>
+#include <platform/mt2731.h>
+#include <platform/mtk_gce.h>
+
+static unsigned char gce_instruction[744] = {
+ 0xF8,0x00,0x00,0x00,0x01,0x80,0x80,0xA0,0x40,0x00,0x00,0x00,0x04,0x80,0x80,0xA0,
+ 0x10,0x00,0x00,0x00,0x06,0x80,0x80,0xA0,0x88,0x80,0x23,0x10,0x08,0x80,0x80,0xA0,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,
+ 0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,
+ 0x00,0x00,0x00,0x00,0x00,0x80,0x80,0xA0,0x03,0x00,0x00,0x80,0x01,0x80,0xC2,0xB1,
+ 0x14,0x80,0x01,0x10,0x00,0x00,0x80,0xA0,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x80,
+ 0xFF,0xFF,0x00,0x00,0x02,0x00,0x80,0xA0,0x02,0x00,0x01,0x00,0x02,0x80,0xEB,0xA0,
+ 0x00,0x00,0x00,0x00,0x03,0x80,0x80,0xA0,0x00,0x80,0x03,0x80,0x04,0x80,0xE2,0xB1,
+ 0x04,0x00,0x03,0x80,0x05,0x80,0xC3,0xA0,0x05,0x80,0x08,0x80,0x05,0x80,0xE1,0xA0,
+ 0x00,0x00,0x05,0x80,0x07,0x80,0xC0,0x80,0x02,0x80,0x07,0x80,0x06,0x80,0xE1,0xB1,
+ 0xA0,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x01,0x00,0x03,0x80,0x03,0x80,0xC1,0xA0,
+ 0xC8,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x10,0x04,0x00,0x00,0x80,0x05,0x80,0xC3,0xA0,
+ 0x05,0x80,0x08,0x80,0x05,0x80,0xE1,0xA0,0x00,0x00,0x02,0x80,0x05,0x80,0xC0,0x90,
+ 0x40,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,0xD0,0x80,0x23,0x10,0x01,0x00,0x80,0xA0,
+ 0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x90,0x01,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,
+ 0x29,0x00,0x00,0x00,0x01,0x00,0x80,0xA0,0xF0,0xFF,0xFF,0xFF,0x02,0x00,0x80,0xA0,
+ 0x01,0x80,0x00,0x80,0xC8,0x03,0x00,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0xC1,0xA0,
+ 0x01,0x00,0x00,0x00,0x02,0x00,0xE3,0xB1,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,
+ 0xD0,0x80,0x23,0x10,0x01,0x00,0x80,0xA0,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x90,
+ 0x01,0x00,0x00,0x80,0x00,0x80,0xC1,0xA0,0x10,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x10,
+ 0x00,0x00,0x02,0x80,0x02,0x80,0xCC,0xA0,0xE0,0xD3,0x00,0x10,0x00,0x00,0x80,0xA0,
+ 0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x80,0x00,0x00,0xC0,0x91,
+ 0x30,0x00,0x00,0x00,0x09,0x80,0x80,0xA0,0x01,0x00,0x00,0x80,0x09,0x80,0xC4,0xB1,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x80,0xA0,0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,
+ 0xFF,0xFF,0xFE,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,
+ 0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0xB0,0x00,0x00,0x00,0x09,0x80,0x80,0xA0,
+ 0x02,0x00,0x00,0x80,0x09,0x80,0xC4,0xB1,0x23,0x00,0x22,0x00,0x01,0x00,0xE2,0xA0,
+ 0x30,0x00,0x00,0x00,0x09,0x80,0x80,0xA0,0x01,0x00,0x01,0x00,0x09,0x80,0xC1,0xB1,
+ 0x00,0x00,0x02,0x00,0x00,0x00,0x80,0xA0,0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,
+ 0xFF,0xFF,0xFD,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,
+ 0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x22,0x00,0x23,0x00,0x01,0x00,0xE2,0xA0,
+ 0x30,0x00,0x00,0x00,0x09,0x80,0x80,0xA0,0x01,0x00,0x01,0x00,0x09,0x80,0xC1,0xB1,
+ 0x00,0x00,0x02,0x00,0x00,0x00,0x80,0xA0,0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,
+ 0xFF,0xFF,0xFD,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,
+ 0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x04,0x00,0x00,0x00,0x80,0xA0,
+ 0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,0xFF,0xFF,0xFB,0xFF,0x00,0x00,0x00,0x02,
+ 0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x10,
+ 0x00,0x00,0x08,0x00,0x00,0x00,0x80,0xA0,0xE0,0xD3,0x00,0x10,0x01,0x00,0x80,0xA0,
+ 0xFF,0xFF,0xF7,0xFF,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x91,
+ 0x00,0x01,0x00,0x00,0x00,0x00,0x80,0xA0,0xD0,0x80,0x23,0x10,0x01,0x00,0x80,0xA0,
+ 0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x90,0x01,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,
+ 0x62,0x02,0x00,0x00,0x01,0x00,0x80,0xA0,0xF0,0xFF,0xFF,0xFF,0x02,0x00,0x80,0xA0,
+ 0x01,0x80,0x00,0x80,0xCA,0x03,0x00,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0xC1,0xA0,
+ 0x01,0x00,0x00,0x00,0x02,0x00,0xE3,0xB1,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xA0,
+ 0xD0,0x80,0x23,0x10,0x01,0x00,0x80,0xA0,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x90,
+ 0x70,0xFD,0xFF,0xFF,0x00,0x00,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x40,
+ 0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x10,
+};
+
+static void load_gce_ins_to_sram(void)
+{
+ vaddr_t gce_ins_va;
+
+ gce_ins_va = (vaddr_t)paddr_to_kvaddr((paddr_t)GCE_INS_SRAM_ADDR);
+ memcpy((void *)gce_ins_va, (void *)gce_instruction, sizeof(gce_instruction));
+
+ dprintf(CRITICAL,"[GCE_INS] va: 0x%lx gce: 0x%lx size_ins 0x%lx pc: 0x%x\n",
+ gce_ins_va,
+ (unsigned long)gce_instruction,
+ sizeof(gce_instruction), GCE_INS_SRAM_ADDR);
+}
+
+static void cmdq_exec(void)
+{
+ writel(CMDQ_INS_CYCLE_TIMEOUT,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THRAD_INS_CYCLES);
+
+ writel(CMDQ_THR_DO_WARM_RESET,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE + CMDQ_THR_WARM_RESET);
+ while(readl(GCE_CMDQ_BASE + CMDQ_THREAD_BASE + CMDQ_THR_WARM_RESET)
+ & CMDQ_THR_DO_WARM_RESET);
+
+ writel(CMDQ_THREAD_PRIO_HIGHEST & CMDQ_THREAD_PRIORITY,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THREAD_CFG);
+
+ writel(GCE_INS_SRAM_ADDR,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THREAD_CURR_ADDR);
+
+ writel(GCE_INS_SRAM_ADDR + sizeof(gce_instruction),
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THREAD_END_ADDR);
+
+ writel(CMDQ_THREAD_IRQ_EN,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THREAD_IRQ_ENABLE);
+
+ writel(CMDQ_THREAD_ENABLED,
+ GCE_CMDQ_BASE + CMDQ_THREAD_BASE +
+ CMDQ_THREAD_ENABLE_TASK);
+}
+
+int mtk_gce_start(void)
+{
+ load_gce_ins_to_sram();
+ cmdq_exec();
+ return 0;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/gpio/mt_gpio.c b/src/bsp/lk/platform/mt2731/drivers/gpio/mt_gpio.c
new file mode 100644
index 0000000..c0b9408
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/gpio/mt_gpio.c
@@ -0,0 +1,1120 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <debug.h>
+#include <platform/mt_gpio.h>
+#include <platform/mt_reg_base.h>
+#include <reg.h>
+#include <string.h>
+#include <target/io_pwr.h>
+
+
+#include <platform/cust_gpio_boot.h>
+
+/*
+ * GPIOX_PULL: GPIO_PULL_UP or GPIO_PULL_DOWN
+ *
+ * map GPIOX_PULL setting to
+ * GPIOX_PUPD register setting
+ *
+ * register setting
+ * PUPD=0: pull up
+ * PUPD=1: pull down
+ */
+#define GPIO30_PUPD (!GPIO30_PULL)
+#define GPIO31_PUPD (!GPIO31_PULL)
+#define GPIO32_PUPD (!GPIO32_PULL)
+#define GPIO33_PUPD (!GPIO33_PULL)
+#define GPIO34_PUPD (!GPIO34_PULL)
+#define GPIO35_PUPD (!GPIO35_PULL)
+#define GPIO36_PUPD (!GPIO36_PULL)
+#define GPIO59_PUPD (!GPIO59_PULL)
+#define GPIO60_PUPD (!GPIO60_PULL)
+#define GPIO61_PUPD (!GPIO61_PULL)
+#define GPIO62_PUPD (!GPIO62_PULL)
+#define GPIO63_PUPD (!GPIO63_PULL)
+#define GPIO64_PUPD (!GPIO64_PULL)
+#define GPIO110_PUPD (!GPIO110_PULL)
+#define GPIO111_PUPD (!GPIO111_PULL)
+#define GPIO112_PUPD (!GPIO112_PULL)
+#define GPIO113_PUPD (!GPIO113_PULL)
+#define GPIO114_PUPD (!GPIO114_PULL)
+#define GPIO115_PUPD (!GPIO115_PULL)
+#define GPIO134_PUPD (!GPIO134_PULL)
+#define GPIO135_PUPD (!GPIO135_PULL)
+#define GPIO136_PUPD (!GPIO136_PULL)
+#define GPIO137_PUPD (!GPIO137_PULL)
+#define GPIO138_PUPD (!GPIO138_PULL)
+#define GPIO139_PUPD (!GPIO139_PULL)
+#define GPIO140_PUPD (!GPIO140_PULL)
+#define GPIO141_PUPD (!GPIO141_PULL)
+#define GPIO142_PUPD (!GPIO142_PULL)
+#define GPIO143_PUPD (!GPIO143_PULL)
+#define GPIO144_PUPD (!GPIO144_PULL)
+#define GPIO145_PUPD (!GPIO145_PULL)
+
+/*
+ * GPIOXX_R0: internal 10k resistor (set 1 to enable)
+ * GPIOXX_R1: internal 50k resistor (set 1 to enable)
+ *
+ * use R0 as default resistor when pull enable set
+ *
+ */
+#define GPIO30_R0 GPIO30_PULLEN
+#define GPIO31_R0 GPIO31_PULLEN
+#define GPIO32_R0 GPIO32_PULLEN
+#define GPIO33_R0 GPIO33_PULLEN
+#define GPIO34_R0 GPIO34_PULLEN
+#define GPIO35_R0 GPIO35_PULLEN
+#define GPIO36_R0 GPIO36_PULLEN
+#define GPIO59_R0 GPIO59_PULLEN
+#define GPIO60_R0 GPIO60_PULLEN
+#define GPIO61_R0 GPIO61_PULLEN
+#define GPIO62_R0 GPIO62_PULLEN
+#define GPIO63_R0 GPIO63_PULLEN
+#define GPIO64_R0 GPIO64_PULLEN
+#define GPIO110_R0 GPIO110_PULLEN
+#define GPIO111_R0 GPIO111_PULLEN
+#define GPIO112_R0 GPIO112_PULLEN
+#define GPIO113_R0 GPIO113_PULLEN
+#define GPIO114_R0 GPIO114_PULLEN
+#define GPIO115_R0 GPIO115_PULLEN
+#define GPIO134_R0 GPIO134_PULLEN
+#define GPIO135_R0 GPIO135_PULLEN
+#define GPIO136_R0 GPIO136_PULLEN
+#define GPIO137_R0 GPIO137_PULLEN
+#define GPIO138_R0 GPIO138_PULLEN
+#define GPIO139_R0 GPIO139_PULLEN
+#define GPIO140_R0 GPIO140_PULLEN
+#define GPIO141_R0 GPIO141_PULLEN
+#define GPIO142_R0 GPIO142_PULLEN
+#define GPIO143_R0 GPIO143_PULLEN
+#define GPIO144_R0 GPIO144_PULLEN
+#define GPIO145_R0 GPIO145_PULLEN
+
+#define GPIO30_R1 0
+#define GPIO31_R1 0
+#define GPIO32_R1 0
+#define GPIO33_R1 0
+#define GPIO34_R1 0
+#define GPIO35_R1 0
+#define GPIO36_R1 0
+#define GPIO59_R1 0
+#define GPIO60_R1 0
+#define GPIO61_R1 0
+#define GPIO62_R1 0
+#define GPIO63_R1 0
+#define GPIO64_R1 0
+#define GPIO110_R1 0
+#define GPIO111_R1 0
+#define GPIO112_R1 0
+#define GPIO113_R1 0
+#define GPIO114_R1 0
+#define GPIO115_R1 0
+#define GPIO134_R1 0
+#define GPIO135_R1 0
+#define GPIO136_R1 0
+#define GPIO137_R1 0
+#define GPIO138_R1 0
+#define GPIO139_R1 0
+#define GPIO140_R1 0
+#define GPIO141_R1 0
+#define GPIO142_R1 0
+#define GPIO143_R1 0
+#define GPIO144_R1 0
+#define GPIO145_R1 0
+
+/* i2c GPIO EH and PU settint */
+#define EH_CFG 0x20
+#define PU_CFG 0x50
+#define RSEL_CFG 0x90
+/*****************************/
+
+const gpio_reg_init gpio_init_value[] = {
+ {
+ IO_CFG_LM_BASE + 0x00B0,
+ (GPIO57_SMT << 17) | (GPIO56_SMT << 18) | (GPIO36_SMT << 8) |
+ (GPIO35_SMT << 9) | (GPIO34_SMT << 10) | (GPIO33_SMT << 11) |
+ (GPIO32_SMT << 7) | (GPIO31_SMT << 6) | (GPIO30_SMT << 12) |
+ (GPIO29_SMT << 0) | (GPIO28_SMT << 19) | (GPIO27_SMT << 20) |
+ (GPIO26_SMT << 21) | (GPIO25_SMT << 5) | (GPIO24_SMT << 1) |
+ (GPIO23_SMT << 15) | (GPIO22_SMT << 14) | (GPIO21_SMT << 13) |
+ (GPIO20_SMT << 16) | (GPIO19_SMT << 25) | (GPIO18_SMT << 23) |
+ (GPIO17_SMT << 24) | (GPIO16_SMT << 22) | (GPIO2_SMT << 4) |
+ (GPIO1_SMT << 3) | (GPIO0_SMT << 2),
+ (0x1 << 17) | (0x1 << 18) | (0x1 << 8) |
+ (0x1 << 9) | (0x1 << 10) | (0x1 << 11) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 12) |
+ (0x1 << 0) | (0x1 << 19) | (0x1 << 20) |
+ (0x1 << 21) | (0x1 << 5) | (0x1 << 1) |
+ (0x1 << 15) | (0x1 << 14) | (0x1 << 13) |
+ (0x1 << 16) | (0x1 << 25) | (0x1 << 23) |
+ (0x1 << 24) | (0x1 << 22) | (0x1 << 4) |
+ (0x1 << 3) | (0x1 << 2)
+ },
+ {
+ IO_CFG_BL_BASE + 0x00B0,
+ (GPIO72_SMT << 22) | (GPIO71_SMT << 18) | (GPIO70_SMT << 21) |
+ (GPIO69_SMT << 20) | (GPIO68_SMT << 19) | (GPIO67_SMT << 1) |
+ (GPIO66_SMT << 2) | (GPIO65_SMT << 0) | (GPIO64_SMT << 12) |
+ (GPIO63_SMT << 14) | (GPIO62_SMT << 15) | (GPIO61_SMT << 16) |
+ (GPIO60_SMT << 17) | (GPIO59_SMT << 13) | (GPIO58_SMT << 11) |
+ (GPIO55_SMT << 10) | (GPIO54_SMT << 8) | (GPIO53_SMT << 7) |
+ (GPIO52_SMT << 6) | (GPIO51_SMT << 9) | (GPIO9_SMT << 5) |
+ (GPIO8_SMT << 4) | (GPIO3_SMT << 3),
+ (0x1 << 22) | (0x1 << 18) | (0x1 << 21) |
+ (0x1 << 20) | (0x1 << 19) | (0x1 << 1) |
+ (0x1 << 2) | (0x1 << 0) | (0x1 << 12) |
+ (0x1 << 14) | (0x1 << 15) | (0x1 << 16) |
+ (0x1 << 17) | (0x1 << 13) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 8) | (0x1 << 7) |
+ (0x1 << 6) | (0x1 << 9) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3)
+ },
+ {
+ IO_CFG_LB_BASE + 0x00A0,
+ (GPIO50_SMT << 14) | (GPIO49_SMT << 11) | (GPIO48_SMT << 13) |
+ (GPIO47_SMT << 12) | (GPIO43_SMT << 4) | (GPIO42_SMT << 5) |
+ (GPIO41_SMT << 8) | (GPIO40_SMT << 7) | (GPIO39_SMT << 10) |
+ (GPIO38_SMT << 6) | (GPIO37_SMT << 9) | (GPIO15_SMT << 16) |
+ (GPIO14_SMT << 15) | (GPIO13_SMT << 17) | (GPIO7_SMT<< 3) |
+ (GPIO6_SMT << 2) | (GPIO5_SMT << 1) | (GPIO4_SMT << 0),
+ (0x1 << 14) | (0x1 << 11) | (0x1 << 13) |
+ (0x1 << 12) | (0x1 << 4) | (0x1 << 5) |
+ (0x1 << 8) | (0x1 << 7) | (0x1 << 10) |
+ (0x1 << 6) | (0x1 << 9) | (0x1 << 16) |
+ (0x1 << 15) | (0x1 << 17) | (0x1 << 3) |
+ (0x1 << 2) | (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ IO_CFG_RB_BASE + 0x0080,
+ (GPIO109_SMT << 12) | (GPIO108_SMT << 10) | (GPIO107_SMT << 3) |
+ (GPIO106_SMT << 13) | (GPIO105_SMT << 19) | (GPIO104_SMT << 18) |
+ (GPIO103_SMT << 2) | (GPIO102_SMT << 5) | (GPIO101_SMT << 11) |
+ (GPIO100_SMT << 0) | (GPIO99_SMT << 6) | (GPIO98_SMT << 4) |
+ (GPIO97_SMT << 1) | (GPIO96_SMT << 17) | (GPIO95_SMT << 16) |
+ (GPIO94_SMT << 14) | (GPIO93_SMT << 15) | (GPIO12_SMT << 9) |
+ (GPIO11_SMT << 8) | (GPIO10_SMT << 7),
+ (0x1 << 12) | (0x1 << 10) | (0x1 << 3) |
+ (0x1 << 13) | (0x1 << 19) | (0x1 << 18) |
+ (0x1 << 2) | (0x1 << 5) | (0x1 << 11) |
+ (0x1 << 0) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 17) | (0x1 << 16) |
+ (0x1 << 14) | (0x1 << 15) | (0x1 << 9) |
+ (0x1 << 8) | (0x1 << 7)
+ },
+ {
+ IO_CFG_TL_BASE + 0x0080,
+ (GPIO160_SMT << 9) | (GPIO159_SMT << 11) | (GPIO158_SMT << 13) |
+ (GPIO157_SMT << 12) | (GPIO156_SMT << 10) | (GPIO155_SMT << 8) |
+ (GPIO154_SMT << 7) | (GPIO153_SMT << 6) | (GPIO152_SMT << 5) |
+ (GPIO151_SMT << 4) | (GPIO150_SMT << 3) | (GPIO149_SMT << 2) |
+ (GPIO148_SMT << 1) | (GPIO147_SMT << 0) | (GPIO46_SMT << 15) |
+ (GPIO45_SMT << 16) | (GPIO44_SMT << 14),
+ (0x1 << 9) | (0x1 << 11) | (0x1 << 13) |
+ (0x1 << 12) | (0x1 << 10) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0) | (0x1 << 15) |
+ (0x1 << 16) | (0x1 << 14)
+ },
+ {
+ IO_CFG_BR_BASE + 0x0090,
+ (GPIO92_SMT << 19) | (GPIO91_SMT << 18) | (GPIO90_SMT << 17) |
+ (GPIO89_SMT << 16) | (GPIO88_SMT << 8) | (GPIO87_SMT << 9) |
+ (GPIO86_SMT << 0) | (GPIO85_SMT << 1) | (GPIO84_SMT << 2) |
+ (GPIO83_SMT << 3) | (GPIO82_SMT << 4) | (GPIO81_SMT << 5) |
+ (GPIO80_SMT << 7) | (GPIO79_SMT << 6) | (GPIO78_SMT << 15) |
+ (GPIO77_SMT << 12) | (GPIO76_SMT << 10) | (GPIO75_SMT << 13) |
+ (GPIO74_SMT << 11) | (GPIO73_SMT << 14),
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 8) | (0x1 << 9) |
+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2) |
+ (0x1 << 3) | (0x1 << 4) | (0x1 << 5) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 15) |
+ (0x1 << 12) | (0x1 << 10) | (0x1 << 13) | (0x1 << 11) | (0x1 << 14)
+ },
+ {
+ IO_CFG_RM_BASE + 0x00E0,
+ (GPIO146_SMT << 18) | (GPIO133_SMT << 1) | (GPIO132_SMT << 0) |
+ (GPIO131_SMT << 10) | (GPIO130_SMT << 17) | (GPIO129_SMT << 3) |
+ (GPIO128_SMT << 2) | (GPIO127_SMT << 16) | (GPIO126_SMT << 9) |
+ (GPIO125_SMT << 4) | (GPIO124_SMT << 11) | (GPIO123_SMT << 5) |
+ (GPIO122_SMT << 6) | (GPIO121_SMT << 7) | (GPIO120_SMT << 8) |
+ (GPIO119_SMT << 12) | (GPIO118_SMT << 13) | (GPIO117_SMT << 14) |
+ (GPIO116_SMT << 15) | (GPIO115_SMT << 19) | (GPIO114_SMT << 21) |
+ (GPIO113_SMT << 20) | (GPIO112_SMT << 22) | (GPIO111_SMT << 24) |
+ (GPIO110_SMT << 23),
+ (0x1 << 18) | (0x1 << 1) | (0x1 << 0) |
+ (0x1 << 10) | (0x1 << 17) | (0x1 << 3) |
+ (0x1 << 2) | (0x1 << 16) | (0x1 << 9) |
+ (0x1 << 4) | (0x1 << 11) | (0x1 << 5) |
+ (0x1 << 6) | (0x1 << 7) | (0x1 << 8) |
+ (0x1 << 12) | (0x1 << 13) | (0x1 << 14) |
+ (0x1 << 15) | (0x1 << 19) | (0x1 << 21) |
+ (0x1 << 20) | (0x1 << 22) | (0x1 << 24) |
+ (0x1 << 23)
+ },
+ {
+ IO_CFG_TR_BASE + 0x0080,
+ (GPIO145_SMT << 3) | (GPIO144_SMT << 6) | (GPIO143_SMT << 4) |
+ (GPIO142_SMT << 1) | (GPIO141_SMT << 2) | (GPIO140_SMT << 11) |
+ (GPIO139_SMT << 5) | (GPIO138_SMT << 0) | (GPIO137_SMT << 10) |
+ (GPIO136_SMT << 9) | (GPIO135_SMT << 7) | (GPIO134_SMT << 8),
+ (0x1 << 3) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 2) | (0x1 << 11) |
+ (0x1 << 5) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 9) | (0x1 << 7) | (0x1 << 8)
+ },
+ {
+ IO_CFG_LM_BASE + 0x0060,
+ ((GPIO57_PULLEN&GPIO57_PULL) << 10) | ((GPIO56_PULLEN&GPIO56_PULL) << 11) |
+ ((GPIO29_PULLEN&GPIO29_PULL) << 0) | ((GPIO28_PULLEN&GPIO28_PULL) << 12) |
+ ((GPIO27_PULLEN&GPIO27_PULL) << 13) | ((GPIO26_PULLEN&GPIO26_PULL) << 14) |
+ ((GPIO25_PULLEN&GPIO25_PULL) << 5) | ((GPIO24_PULLEN&GPIO24_PULL) << 1) |
+ ((GPIO23_PULLEN&GPIO23_PULL) << 8) | ((GPIO22_PULLEN&GPIO22_PULL) << 7) |
+ ((GPIO21_PULLEN&GPIO21_PULL) << 6) | ((GPIO20_PULLEN&GPIO20_PULL) << 9) |
+ ((GPIO19_PULLEN&GPIO19_PULL) << 18) | ((GPIO18_PULLEN&GPIO18_PULL) << 16) |
+ ((GPIO17_PULLEN&GPIO17_PULL) << 17) | ((GPIO16_PULLEN&GPIO16_PULL) << 15) |
+ ((GPIO2_PULLEN&GPIO2_PULL) << 4) | ((GPIO1_PULLEN&GPIO1_PULL) << 3) |
+ ((GPIO0_PULLEN&GPIO0_PULL) << 2),
+ (0x1 << 10) | (0x1 << 11) | (0x1 << 0) | (0x1 << 12) |
+ (0x1 << 13) | (0x1 << 14) | (0x1 << 5) | (0x1 << 1) |
+ (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 9) |
+ (0x1 << 18) | (0x1 << 16) | (0x1 << 17) | (0x1 << 15) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2)
+ },
+ {
+ IO_CFG_BL_BASE + 0x0060,
+ ((GPIO72_PULLEN&GPIO72_PULL) << 16) | ((GPIO71_PULLEN&GPIO71_PULL) << 12) |
+ ((GPIO70_PULLEN&GPIO70_PULL) << 15) | ((GPIO69_PULLEN&GPIO69_PULL) << 14) |
+ ((GPIO68_PULLEN&GPIO68_PULL) << 13) | ((GPIO67_PULLEN&GPIO67_PULL) << 1) |
+ ((GPIO66_PULLEN&GPIO66_PULL) << 2) | ((GPIO65_PULLEN&GPIO65_PULL) << 0) |
+ ((GPIO58_PULLEN&GPIO58_PULL) << 11) | ((GPIO55_PULLEN&GPIO55_PULL) << 10) |
+ ((GPIO54_PULLEN&GPIO54_PULL) << 8) | ((GPIO53_PULLEN&GPIO53_PULL) << 7) |
+ ((GPIO52_PULLEN&GPIO52_PULL) << 6) | ((GPIO51_PULLEN&GPIO51_PULL) << 9) |
+ ((GPIO9_PULLEN&GPIO9_PULL) << 5) | ((GPIO8_PULLEN&GPIO8_PULL) << 4) |
+ ((GPIO3_PULLEN&GPIO3_PULL) << 3),
+ (0x1 << 16) | (0x1 << 12) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 1) | (0x1 << 2) | (0x1 << 0) |
+ (0x1 << 11) | (0x1 << 10) | (0x1 << 8) | (0x1 << 7) |
+ (0x1 << 6) | (0x1 << 9) | (0x1 << 5) | (0x1 << 4) |
+ (0x1 << 3)
+ },
+ {
+ IO_CFG_LB_BASE + 0x0050,
+ ((GPIO50_PULLEN&GPIO50_PULL) << 14) | ((GPIO49_PULLEN&GPIO49_PULL) << 11) |
+ ((GPIO48_PULLEN&GPIO48_PULL) << 13) | ((GPIO47_PULLEN&GPIO47_PULL) << 12) |
+ ((GPIO43_PULLEN&GPIO43_PULL) << 4) | ((GPIO42_PULLEN&GPIO42_PULL) << 5) |
+ ((GPIO41_PULLEN&GPIO41_PULL) << 8) | ((GPIO40_PULLEN&GPIO40_PULL) << 7) |
+ ((GPIO39_PULLEN&GPIO39_PULL) << 10) | ((GPIO38_PULLEN&GPIO38_PULL) << 6) |
+ ((GPIO37_PULLEN&GPIO37_PULL) << 9) | ((GPIO15_PULLEN&GPIO15_PULL) << 16) |
+ ((GPIO14_PULLEN&GPIO14_PULL) << 15) | ((GPIO13_PULLEN&GPIO13_PULL) << 17) |
+ ((GPIO7_PULLEN&GPIO7_PULL) << 3) | ((GPIO6_PULLEN&GPIO6_PULL) << 2) |
+ ((GPIO5_PULLEN&GPIO5_PULL) << 1) | ((GPIO4_PULLEN&GPIO4_PULL) << 0),
+ (0x1 << 14) | (0x1 << 11) | (0x1 << 13) | (0x1 << 12) |
+ (0x1 << 4) | (0x1 << 5) | (0x1 << 8) | (0x1 << 7) |
+ (0x1 << 10) | (0x1 << 6) | (0x1 << 9) | (0x1 << 16) |
+ (0x1 << 15) | (0x1 << 17) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ IO_CFG_RB_BASE + 0x0050,
+ ((GPIO109_PULLEN&GPIO109_PULL) << 12) | ((GPIO108_PULLEN&GPIO108_PULL) << 10) |
+ ((GPIO107_PULLEN&GPIO107_PULL) << 3) | ((GPIO106_PULLEN&GPIO106_PULL) << 13) |
+ ((GPIO105_PULLEN&GPIO105_PULL) << 19) | ((GPIO104_PULLEN&GPIO104_PULL) << 18) |
+ ((GPIO103_PULLEN&GPIO103_PULL) << 2) | ((GPIO102_PULLEN&GPIO102_PULL) << 5) |
+ ((GPIO101_PULLEN&GPIO101_PULL) << 11) | ((GPIO100_PULLEN&GPIO100_PULL) << 0) |
+ ((GPIO99_PULLEN&GPIO99_PULL) << 6) | ((GPIO98_PULLEN&GPIO98_PULL) << 4) |
+ ((GPIO97_PULLEN&GPIO97_PULL) << 1) | ((GPIO96_PULLEN&GPIO96_PULL) << 17) |
+ ((GPIO95_PULLEN&GPIO95_PULL) << 16) | ((GPIO94_PULLEN&GPIO94_PULL) << 14) |
+ ((GPIO93_PULLEN&GPIO93_PULL) << 15) | ((GPIO12_PULLEN&GPIO12_PULL) << 9) |
+ ((GPIO11_PULLEN&GPIO11_PULL) << 8) | ((GPIO10_PULLEN&GPIO10_PULL) << 7),
+ (0x1 << 12) | (0x1 << 10) | (0x1 << 3) | (0x1 << 13) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 2) | (0x1 << 5) |
+ (0x1 << 11) | (0x1 << 0) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 17) | (0x1 << 16) | (0x1 << 14) |
+ (0x1 << 15) | (0x1 << 9) | (0x1 << 8) | (0x1 << 7)
+ },
+ {
+ IO_CFG_TL_BASE + 0x0050,
+ ((GPIO160_PULLEN&GPIO160_PULL) << 9) | ((GPIO159_PULLEN&GPIO159_PULL) << 11) |
+ ((GPIO158_PULLEN&GPIO158_PULL) << 13) | ((GPIO157_PULLEN&GPIO157_PULL) << 12) |
+ ((GPIO156_PULLEN&GPIO156_PULL) << 10) | ((GPIO155_PULLEN&GPIO155_PULL) << 8) |
+ ((GPIO154_PULLEN&GPIO154_PULL) << 7) | ((GPIO153_PULLEN&GPIO153_PULL) << 6) |
+ ((GPIO152_PULLEN&GPIO152_PULL) << 5) | ((GPIO151_PULLEN&GPIO151_PULL) << 4) |
+ ((GPIO150_PULLEN&GPIO150_PULL) << 3) | ((GPIO149_PULLEN&GPIO149_PULL) << 2) |
+ ((GPIO148_PULLEN&GPIO148_PULL) << 1) | ((GPIO147_PULLEN&GPIO147_PULL) << 0) |
+ ((GPIO46_PULLEN&GPIO46_PULL) << 15) | ((GPIO45_PULLEN&GPIO45_PULL) << 16) |
+ ((GPIO44_PULLEN&GPIO44_PULL) << 14),
+ (0x1 << 9) | (0x1 << 11) | (0x1 << 13) | (0x1 << 12) |
+ (0x1 << 10) | (0x1 <<8) | (0x1 << 7) | (0x1 << 6) |
+ (0x1 << 5) | (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0) | (0x1 << 15) | (0x1 << 16) |
+ (0x1 << 14)
+ },
+ {
+ IO_CFG_BR_BASE + 0x0060,
+ ((GPIO92_PULLEN&GPIO92_PULL) << 19) | ((GPIO91_PULLEN&GPIO91_PULL) << 18) |
+ ((GPIO90_PULLEN&GPIO90_PULL) << 17) | ((GPIO89_PULLEN&GPIO89_PULL) << 16) |
+ ((GPIO88_PULLEN&GPIO88_PULL) << 8) | ((GPIO87_PULLEN&GPIO87_PULL) << 9) |
+ ((GPIO86_PULLEN&GPIO86_PULL) << 0) | ((GPIO85_PULLEN&GPIO85_PULL) << 1) |
+ ((GPIO84_PULLEN&GPIO84_PULL) << 2) | ((GPIO83_PULLEN&GPIO83_PULL) << 3) |
+ ((GPIO82_PULLEN&GPIO82_PULL) << 4) | ((GPIO81_PULLEN&GPIO81_PULL) << 5) |
+ ((GPIO80_PULLEN&GPIO80_PULL) << 7) | ((GPIO79_PULLEN&GPIO79_PULL) << 6) |
+ ((GPIO78_PULLEN&GPIO78_PULL) << 15) | ((GPIO77_PULLEN&GPIO77_PULL) << 12) |
+ ((GPIO76_PULLEN&GPIO76_PULL) << 10) | ((GPIO75_PULLEN&GPIO75_PULL) << 13) |
+ ((GPIO74_PULLEN&GPIO74_PULL) << 11) | ((GPIO73_PULLEN&GPIO73_PULL) << 14),
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) | (0x1 << 16) |
+ (0x1 << 8) | (0x1 << 9) | (0x1 << 0) | (0x1 << 1) |
+ (0x1 << 2) | (0x1 << 3) | (0x1 << 4) | (0x1 << 5) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 15) | (0x1 << 12) |
+ (0x1 << 10) | (0x1 << 13) | (0x1 << 11) | (0x1 << 14)
+ },
+ {
+ IO_CFG_RM_BASE + 0x0070,
+ ((GPIO146_PULLEN&GPIO146_PULL) << 18) | ((GPIO133_PULLEN&GPIO133_PULL) << 1) |
+ ((GPIO132_PULLEN&GPIO132_PULL) << 0) | ((GPIO131_PULLEN&GPIO131_PULL) << 10) |
+ ((GPIO130_PULLEN&GPIO130_PULL) << 17) | ((GPIO129_PULLEN&GPIO129_PULL) << 3) |
+ ((GPIO128_PULLEN&GPIO128_PULL) << 2) | ((GPIO127_PULLEN&GPIO127_PULL) << 16) |
+ ((GPIO126_PULLEN&GPIO126_PULL) << 9) | ((GPIO125_PULLEN&GPIO125_PULL) << 4) |
+ ((GPIO124_PULLEN&GPIO124_PULL) << 11) | ((GPIO123_PULLEN&GPIO123_PULL) << 5) |
+ ((GPIO122_PULLEN&GPIO122_PULL) << 6) | ((GPIO121_PULLEN&GPIO121_PULL) << 7) |
+ ((GPIO120_PULLEN&GPIO120_PULL) << 8) | ((GPIO119_PULLEN&GPIO119_PULL) << 12) |
+ ((GPIO118_PULLEN&GPIO118_PULL) << 13) | ((GPIO117_PULLEN&GPIO117_PULL) << 14) |
+ ((GPIO116_PULLEN&GPIO116_PULL) << 15),
+ (0x1 << 18) | (0x1 << 1) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 17) | (0x1 << 3) | (0x1 << 2) | (0x1 << 16) |
+ (0x1 << 9) | (0x1 << 4) | (0x1 << 11) | (0x1 << 5) |
+ (0x1 << 6) | (0x1 << 7) | (0x1 << 8) | (0x1 << 12) |
+ (0x1 << 13) | (0x1 << 14) | (0x1 << 15)
+ },
+ {
+ IO_CFG_LM_BASE + 0x0040,
+ ((GPIO57_PULLEN&~GPIO57_PULL) << 10) | ((GPIO56_PULLEN&~GPIO56_PULL) << 11) |
+ ((GPIO29_PULLEN&~GPIO29_PULL) << 0) | ((GPIO28_PULLEN&~GPIO28_PULL) << 12) |
+ ((GPIO27_PULLEN&~GPIO27_PULL) << 13) | ((GPIO26_PULLEN&~GPIO26_PULL) << 14) |
+ ((GPIO25_PULLEN&~GPIO25_PULL) << 5) | ((GPIO24_PULLEN&~GPIO24_PULL) << 1) |
+ ((GPIO23_PULLEN&~GPIO23_PULL) << 8) | ((GPIO22_PULLEN&~GPIO22_PULL) << 7) |
+ ((GPIO21_PULLEN&~GPIO21_PULL) << 6) | ((GPIO20_PULLEN&~GPIO20_PULL) << 9) |
+ ((GPIO19_PULLEN&~GPIO19_PULL) << 18) | ((GPIO18_PULLEN&~GPIO18_PULL) << 16) |
+ ((GPIO17_PULLEN&~GPIO17_PULL) << 17) | ((GPIO16_PULLEN&~GPIO16_PULL) << 15) |
+ ((GPIO2_PULLEN&~GPIO2_PULL) << 4) | ((GPIO1_PULLEN&~GPIO1_PULL) << 3) |
+ ((GPIO0_PULLEN&~GPIO0_PULL) << 2),
+ (0x1 << 10) | (0x1 << 11) | (0x1 << 0) | (0x1 << 12) |
+ (0x1 << 13) | (0x1 << 14) | (0x1 << 5) | (0x1 << 1) |
+ (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1<< 9) |
+ (0x1 << 18) | (0x1 << 16) | (0x1 << 17) | (0x1 << 15) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2)
+ },
+ {
+ IO_CFG_BL_BASE + 0x0040,
+ ((GPIO72_PULLEN&~GPIO72_PULL) << 16) | ((GPIO71_PULLEN&~GPIO71_PULL) << 12) |
+ ((GPIO70_PULLEN&~GPIO70_PULL) << 15) | ((GPIO69_PULLEN&~GPIO69_PULL) << 14) |
+ ((GPIO68_PULLEN&~GPIO68_PULL) << 13) | ((GPIO67_PULLEN&~GPIO67_PULL) << 1) |
+ ((GPIO66_PULLEN&~GPIO66_PULL) << 2) | ((GPIO65_PULLEN&~GPIO65_PULL) << 0) |
+ ((GPIO58_PULLEN&~GPIO58_PULL) << 11) | ((GPIO55_PULLEN&~GPIO55_PULL) << 10) |
+ ((GPIO54_PULLEN&~GPIO54_PULL) << 8) | ((GPIO53_PULLEN&~GPIO53_PULL) << 7) |
+ ((GPIO52_PULLEN&~GPIO52_PULL) << 6) | ((GPIO51_PULLEN&~GPIO51_PULL) << 9) |
+ ((GPIO9_PULLEN&~GPIO9_PULL) << 5) | ((GPIO8_PULLEN&~GPIO8_PULL) << 4) |
+ ((GPIO3_PULLEN&~GPIO3_PULL) << 3),
+ (0x1 << 16) | (0x1 << 12) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 1) | (0x1 << 2) | (0x1 << 0) |
+ (0x1 << 11) | (0x1 << 10) | (0x1 << 8) | (0x1 << 7) |
+ (0x1 << 6) | (0x1 << 9) | (0x1 << 5) | (0x1 << 4) |
+ (0x1 << 3)
+ },
+ {
+ IO_CFG_LB_BASE + 0x0040,
+ ((GPIO50_PULLEN&~GPIO50_PULL) << 14) | ((GPIO49_PULLEN&~GPIO49_PULL) << 11) |
+ ((GPIO48_PULLEN&~GPIO48_PULL) << 13) | ((GPIO47_PULLEN&~GPIO47_PULL) << 12) |
+ ((GPIO43_PULLEN&~GPIO43_PULL) << 4) | ((GPIO42_PULLEN&~GPIO42_PULL) << 5) |
+ ((GPIO41_PULLEN&~GPIO41_PULL) << 8) | ((GPIO40_PULLEN&~GPIO40_PULL) << 7) |
+ ((GPIO39_PULLEN&~GPIO39_PULL) << 10) | ((GPIO38_PULLEN&~GPIO38_PULL) << 6) |
+ ((GPIO37_PULLEN&~GPIO37_PULL) << 9) | ((GPIO15_PULLEN&~GPIO15_PULL) << 16) |
+ ((GPIO14_PULLEN&~GPIO14_PULL) << 15) | ((GPIO13_PULLEN&~GPIO13_PULL) << 17) |
+ ((GPIO7_PULLEN&~GPIO7_PULL) << 3) | ((GPIO6_PULLEN&~GPIO6_PULL) << 2) |
+ ((GPIO5_PULLEN&~GPIO5_PULL) << 1) | ((GPIO4_PULLEN&~GPIO4_PULL) << 0),
+ (0x1 << 14) | (0x1 << 11) | (0x1 << 13) | (0x1 << 12) |
+ (0x1 << 4) | (0x1 << 5) | (0x1 << 8) | (0x1 << 7) |
+ (0x1 << 10) | (0x1 << 6) | (0x1 << 9) | (0x1 << 16) |
+ (0x1 << 15) | (0x1 << 17) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ IO_CFG_RB_BASE + 0x0040,
+ ((GPIO109_PULLEN&~GPIO109_PULL) << 12) | ((GPIO108_PULLEN&~GPIO108_PULL) << 10) |
+ ((GPIO107_PULLEN&~GPIO107_PULL) << 3) | ((GPIO106_PULLEN&~GPIO106_PULL) << 13) |
+ ((GPIO105_PULLEN&~GPIO105_PULL) << 19) | ((GPIO104_PULLEN&~GPIO104_PULL) << 18) |
+ ((GPIO103_PULLEN&~GPIO103_PULL) << 2) | ((GPIO102_PULLEN&~GPIO102_PULL) << 5) |
+ ((GPIO101_PULLEN&~GPIO101_PULL) << 11) | ((GPIO100_PULLEN&~GPIO100_PULL) << 0) |
+ ((GPIO99_PULLEN&~GPIO99_PULL) << 6) | ((GPIO98_PULLEN&~GPIO98_PULL) << 4) |
+ ((GPIO97_PULLEN&~GPIO97_PULL) << 1) | ((GPIO96_PULLEN&~GPIO96_PULL) << 17) |
+ ((GPIO95_PULLEN&~GPIO95_PULL) << 16) | ((GPIO94_PULLEN&~GPIO94_PULL) << 14) |
+ ((GPIO93_PULLEN&~GPIO93_PULL) << 15) | ((GPIO12_PULLEN&~GPIO12_PULL) << 9) |
+ ((GPIO11_PULLEN&~GPIO11_PULL) << 8) | ((GPIO10_PULLEN&~GPIO10_PULL) << 7),
+ (0x1 << 12) | (0x1 << 10) | (0x1 << 3) | (0x1 << 13) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 2) | (0x1 << 5) |
+ (0x1 << 11) | (0x1 << 0) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 17) | (0x1 << 16) | (0x1 << 14) |
+ (0x1 << 15) | (0x1 << 9) | (0x1 << 8) | (0x1 << 7)
+ },
+ {
+ IO_CFG_TL_BASE + 0x0040,
+ ((GPIO160_PULLEN&~GPIO160_PULL) << 9) | ((GPIO159_PULLEN&~GPIO159_PULL) << 11) |
+ ((GPIO158_PULLEN&~GPIO158_PULL) << 13) | ((GPIO157_PULLEN&~GPIO157_PULL) << 12) |
+ ((GPIO156_PULLEN&~GPIO156_PULL) << 10) | ((GPIO155_PULLEN&~GPIO155_PULL) << 8) |
+ ((GPIO154_PULLEN&~GPIO154_PULL) << 7) | ((GPIO153_PULLEN&~GPIO153_PULL) << 6) |
+ ((GPIO152_PULLEN&~GPIO152_PULL) << 5) | ((GPIO151_PULLEN&~GPIO151_PULL) << 4) |
+ ((GPIO150_PULLEN&~GPIO150_PULL) << 3) | ((GPIO149_PULLEN&~GPIO149_PULL) << 2) |
+ ((GPIO148_PULLEN&~GPIO148_PULL) << 1) | ((GPIO147_PULLEN&~GPIO147_PULL) << 0) |
+ ((GPIO46_PULLEN&~GPIO46_PULL) << 15) | ((GPIO45_PULLEN&~GPIO45_PULL) << 16) |
+ ((GPIO44_PULLEN&~GPIO44_PULL) << 14),
+ (0x1 << 9) | (0x1 << 11) | (0x1 << 13) | (0x1 << 12) |
+ (0x1 << 10) | (0x1 << 8) | (0x1 << 7) | (0x1 << 6) |
+ (0x1 << 5) | (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0) | (0x1 << 15) | (0x1 << 16) |
+ (0x1 << 14)
+ },
+ {
+ IO_CFG_BR_BASE + 0x0050,
+ ((GPIO92_PULLEN&~GPIO92_PULL) << 19) | ((GPIO91_PULLEN&~GPIO91_PULL) << 18) |
+ ((GPIO90_PULLEN&~GPIO90_PULL) << 17) | ((GPIO89_PULLEN&~GPIO89_PULL) << 16) |
+ ((GPIO88_PULLEN&~GPIO88_PULL) << 8) | ((GPIO87_PULLEN&~GPIO87_PULL) << 9) |
+ ((GPIO86_PULLEN&~GPIO86_PULL) << 0) | ((GPIO85_PULLEN&~GPIO85_PULL) << 1) |
+ ((GPIO84_PULLEN&~GPIO84_PULL) << 2) | ((GPIO83_PULLEN&~GPIO83_PULL) << 3) |
+ ((GPIO82_PULLEN&~GPIO82_PULL) << 4) | ((GPIO81_PULLEN&~GPIO81_PULL) << 5) |
+ ((GPIO80_PULLEN&~GPIO80_PULL) << 7) | ((GPIO79_PULLEN&~GPIO79_PULL) << 6) |
+ ((GPIO78_PULLEN&~GPIO78_PULL) << 15) | ((GPIO77_PULLEN&~GPIO77_PULL) << 12) |
+ ((GPIO76_PULLEN&~GPIO76_PULL) << 10) | ((GPIO75_PULLEN&~GPIO75_PULL) << 13) |
+ ((GPIO74_PULLEN&~GPIO74_PULL) << 11) | ((GPIO73_PULLEN&~GPIO73_PULL) << 14),
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) | (0x1 << 16) |
+ (0x1 << 8) | (0x1 << 9) | (0x1 << 0) | (0x1 << 1) |
+ (0x1 << 2) | (0x1 << 3) | (0x1 << 4) | (0x1 <<5) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 15) | (0x1 << 12) |
+ (0x1 << 10) | (0x1 << 13) | (0x1 << 11) | (0x1 << 14)
+ },
+ {
+ IO_CFG_RM_BASE + 0x0050,
+ ((GPIO146_PULLEN&~GPIO146_PULL) << 18) | ((GPIO133_PULLEN&~GPIO133_PULL) << 1) |
+ ((GPIO132_PULLEN&~GPIO132_PULL) << 0) | ((GPIO131_PULLEN&~GPIO131_PULL) << 10) |
+ ((GPIO130_PULLEN&~GPIO130_PULL) << 17) | ((GPIO129_PULLEN&~GPIO129_PULL) << 3) |
+ ((GPIO128_PULLEN&~GPIO128_PULL) << 2) | ((GPIO127_PULLEN&~GPIO127_PULL) << 16) |
+ ((GPIO126_PULLEN&~GPIO126_PULL) << 9) | ((GPIO125_PULLEN&~GPIO125_PULL) << 4) |
+ ((GPIO124_PULLEN&~GPIO124_PULL) <<11) | ((GPIO123_PULLEN&~GPIO123_PULL) << 5) |
+ ((GPIO122_PULLEN&~GPIO122_PULL) << 6) | ((GPIO121_PULLEN&~GPIO121_PULL) << 7) |
+ ((GPIO120_PULLEN&~GPIO120_PULL) << 8) | ((GPIO119_PULLEN&~GPIO119_PULL) << 12) |
+ ((GPIO118_PULLEN&~GPIO118_PULL) << 13) | ((GPIO117_PULLEN&~GPIO117_PULL) << 14) |
+ ((GPIO116_PULLEN&~GPIO116_PULL) << 15),
+ (0x1 << 18) | (0x1 << 1) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 17) | (0x1 << 3) | (0x1 << 2) | (0x1 << 16) |
+ (0x1 << 9) | (0x1 << 4) | (0x1 << 11) | (0x1 << 5) |
+ (0x1 << 6) | (0x1 << 7) | (0x1 << 8) | (0x1 << 12) |
+ (0x1 << 13) | (0x1 << 14) | (0x1 << 15)
+ },
+ {
+ GPIO_BASE + 0x0300,
+ (GPIO7_MODE << 28) | (GPIO6_MODE << 24) | (GPIO5_MODE << 20) |
+ (GPIO4_MODE << 16) | (GPIO3_MODE << 12) | (GPIO2_MODE << 8) |
+ (GPIO1_MODE << 4) | (GPIO0_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) | (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0310,
+ (GPIO15_MODE << 28) | (GPIO14_MODE << 24) | (GPIO13_MODE << 20) |
+ (GPIO12_MODE << 16) | (GPIO11_MODE << 12) | (GPIO10_MODE << 8) |
+ (GPIO9_MODE << 4) | (GPIO8_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0320,
+ (GPIO23_MODE << 28) | (GPIO22_MODE << 24) | (GPIO21_MODE << 20) |
+ (GPIO20_MODE << 16) | (GPIO19_MODE << 12) | (GPIO18_MODE << 8) |
+ (GPIO17_MODE << 4) | (GPIO16_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0330,
+ (GPIO31_MODE << 28) | (GPIO30_MODE << 24) | (GPIO29_MODE << 20) |
+ (GPIO28_MODE << 16) | (GPIO27_MODE << 12) | (GPIO26_MODE << 8) |
+ (GPIO25_MODE << 4) | (GPIO24_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0340,
+ (GPIO39_MODE << 28) | (GPIO38_MODE << 24) | (GPIO37_MODE << 20) |
+ (GPIO36_MODE << 16) | (GPIO35_MODE << 12) | (GPIO34_MODE << 8) |
+ (GPIO33_MODE << 4) | (GPIO32_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0350,
+ (GPIO47_MODE << 28) | (GPIO46_MODE << 24) | (GPIO45_MODE << 20) |
+ (GPIO44_MODE << 16) | (GPIO43_MODE << 12) | (GPIO42_MODE << 8) |
+ (GPIO41_MODE << 4) | (GPIO40_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0360,
+ (GPIO55_MODE << 28) | (GPIO54_MODE << 24) | (GPIO53_MODE << 20) |
+ (GPIO52_MODE << 16) | (GPIO51_MODE << 12) | (GPIO50_MODE << 8) |
+ (GPIO49_MODE << 4) | (GPIO48_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0370,
+ (GPIO63_MODE << 28) | (GPIO62_MODE << 24) | (GPIO61_MODE << 20) |
+ (GPIO60_MODE << 16) | (GPIO59_MODE << 12) | (GPIO58_MODE << 8) |
+ (GPIO57_MODE << 4) | (GPIO56_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0380,
+ (GPIO71_MODE << 28) | (GPIO70_MODE << 24) | (GPIO69_MODE << 20) |
+ (GPIO68_MODE << 16) | (GPIO67_MODE << 12) | (GPIO66_MODE << 8) |
+ (GPIO65_MODE << 4) | (GPIO64_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0390,
+ (GPIO79_MODE << 28) | (GPIO78_MODE << 24) | (GPIO77_MODE << 20) |
+ (GPIO76_MODE << 16) | (GPIO75_MODE << 12) | (GPIO74_MODE << 8) |
+ (GPIO73_MODE << 4) | (GPIO72_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03A0,
+ (GPIO87_MODE << 28) | (GPIO86_MODE << 24) | (GPIO85_MODE << 20) |
+ (GPIO84_MODE << 16) | (GPIO83_MODE << 12) | (GPIO82_MODE << 8) |
+ (GPIO81_MODE << 4) | (GPIO80_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03B0,
+ (GPIO95_MODE << 28) | (GPIO94_MODE << 24) | (GPIO93_MODE << 20) |
+ (GPIO92_MODE << 16) | (GPIO91_MODE << 12) | (GPIO90_MODE << 8) |
+ (GPIO89_MODE << 4) | (GPIO88_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03C0,
+ (GPIO103_MODE << 28) | (GPIO102_MODE << 24) | (GPIO101_MODE << 20) |
+ (GPIO100_MODE << 16) | (GPIO99_MODE << 12) | (GPIO98_MODE << 8) |
+ (GPIO97_MODE << 4) | (GPIO96_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03D0,
+ (GPIO111_MODE << 28) | (GPIO110_MODE << 24) | (GPIO109_MODE << 20) |
+ (GPIO108_MODE << 16) | (GPIO107_MODE << 12) | (GPIO106_MODE << 8) |
+ (GPIO105_MODE << 4) | (GPIO104_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03E0,
+ (GPIO119_MODE << 28) | (GPIO118_MODE << 24) | (GPIO117_MODE << 20) |
+ (GPIO116_MODE << 16) | (GPIO115_MODE << 12) | (GPIO114_MODE << 8) |
+ (GPIO113_MODE << 4) | (GPIO112_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x03F0,
+ (GPIO127_MODE << 28) | (GPIO126_MODE << 24) | (GPIO125_MODE << 20) |
+ (GPIO124_MODE << 16) | (GPIO123_MODE << 12) | (GPIO122_MODE << 8) |
+ (GPIO121_MODE << 4) | (GPIO120_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0400,
+ (GPIO135_MODE << 28) | (GPIO134_MODE << 24) | (GPIO133_MODE << 20) |
+ (GPIO132_MODE << 16) | (GPIO131_MODE << 12) | (GPIO130_MODE << 8) |
+ (GPIO129_MODE << 4) | (GPIO128_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0410,
+ (GPIO143_MODE << 28) | (GPIO142_MODE << 24) | (GPIO141_MODE << 20) |
+ (GPIO140_MODE << 16) | (GPIO139_MODE << 12) | (GPIO138_MODE << 8) |
+ (GPIO137_MODE << 4) | (GPIO136_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0420,
+ (GPIO151_MODE << 28) | (GPIO150_MODE << 24) | (GPIO149_MODE << 20) |
+ (GPIO148_MODE << 16) | (GPIO147_MODE << 12) | (GPIO146_MODE << 8) |
+ (GPIO145_MODE << 4) | (GPIO144_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0430,
+ (GPIO159_MODE << 28) | (GPIO158_MODE << 24) | (GPIO157_MODE << 20) |
+ (GPIO156_MODE << 16) | (GPIO155_MODE << 12) | (GPIO154_MODE << 8) |
+ (GPIO153_MODE << 4) | (GPIO152_MODE << 0),
+ (0xF << 28) | (0xF << 24) | (0xF << 20) |
+ (0xF << 16) | (0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0440,
+ (GPIO160_MODE << 0),
+ (0xF << 0)
+ },
+ {
+ GPIO_BASE + 0x0100,
+ (GPIO31_DATAOUT << 31) | (GPIO30_DATAOUT << 30) | (GPIO29_DATAOUT << 29) |
+ (GPIO28_DATAOUT << 28) | (GPIO27_DATAOUT << 27) | (GPIO26_DATAOUT << 26) |
+ (GPIO25_DATAOUT << 25) | (GPIO24_DATAOUT << 24) | (GPIO23_DATAOUT << 23) |
+ (GPIO22_DATAOUT << 22) | (GPIO21_DATAOUT << 21) | (GPIO20_DATAOUT << 20) |
+ (GPIO19_DATAOUT << 19) | (GPIO18_DATAOUT << 18) | (GPIO17_DATAOUT << 17) |
+ (GPIO16_DATAOUT << 16) | (GPIO15_DATAOUT << 15) | (GPIO14_DATAOUT << 14) |
+ (GPIO13_DATAOUT << 13) | (GPIO12_DATAOUT << 12) | (GPIO11_DATAOUT << 11) |
+ (GPIO10_DATAOUT << 10) | (GPIO9_DATAOUT << 9) | (GPIO8_DATAOUT << 8) |
+ (GPIO7_DATAOUT << 7) | (GPIO6_DATAOUT << 6) | (GPIO5_DATAOUT << 5) |
+ (GPIO4_DATAOUT << 4) | (GPIO3_DATAOUT << 3) | (GPIO2_DATAOUT << 2) |
+ (GPIO1_DATAOUT << 1) | (GPIO0_DATAOUT << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0110,
+ (GPIO63_DATAOUT << 31) | (GPIO62_DATAOUT << 30) | (GPIO61_DATAOUT << 29) |
+ (GPIO60_DATAOUT << 28) | (GPIO59_DATAOUT << 27) | (GPIO58_DATAOUT << 26) |
+ (GPIO57_DATAOUT << 25) | (GPIO56_DATAOUT << 24) | (GPIO55_DATAOUT << 23) |
+ (GPIO54_DATAOUT << 22) | (GPIO53_DATAOUT << 21) | (GPIO52_DATAOUT << 20) |
+ (GPIO51_DATAOUT << 19) | (GPIO50_DATAOUT << 18) | (GPIO49_DATAOUT << 17) |
+ (GPIO48_DATAOUT << 16) | (GPIO47_DATAOUT << 15) | (GPIO46_DATAOUT << 14) |
+ (GPIO45_DATAOUT << 13) | (GPIO44_DATAOUT << 12) | (GPIO43_DATAOUT << 11) |
+ (GPIO42_DATAOUT << 10) | (GPIO41_DATAOUT << 9) | (GPIO40_DATAOUT << 8) |
+ (GPIO39_DATAOUT << 7) | (GPIO38_DATAOUT << 6) | (GPIO37_DATAOUT << 5) |
+ (GPIO36_DATAOUT << 4) | (GPIO35_DATAOUT << 3) | (GPIO34_DATAOUT << 2) |
+ (GPIO33_DATAOUT << 1) | (GPIO32_DATAOUT << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0120,
+ (GPIO95_DATAOUT << 31) | (GPIO94_DATAOUT << 30) | (GPIO93_DATAOUT << 29) |
+ (GPIO92_DATAOUT << 28) | (GPIO91_DATAOUT << 27) | (GPIO90_DATAOUT << 26) |
+ (GPIO89_DATAOUT << 25) | (GPIO88_DATAOUT << 24) | (GPIO87_DATAOUT << 23) |
+ (GPIO86_DATAOUT << 22) | (GPIO85_DATAOUT << 21) | (GPIO84_DATAOUT << 20) |
+ (GPIO83_DATAOUT << 19) | (GPIO82_DATAOUT << 18) | (GPIO81_DATAOUT << 17) |
+ (GPIO80_DATAOUT << 16) | (GPIO79_DATAOUT << 15) | (GPIO78_DATAOUT << 14) |
+ (GPIO77_DATAOUT << 13) | (GPIO76_DATAOUT << 12) | (GPIO75_DATAOUT << 11) |
+ (GPIO74_DATAOUT << 10) | (GPIO73_DATAOUT << 9) | (GPIO72_DATAOUT << 8) |
+ (GPIO71_DATAOUT << 7) | (GPIO70_DATAOUT << 6) | (GPIO69_DATAOUT << 5) |
+ (GPIO68_DATAOUT << 4) | (GPIO67_DATAOUT << 3) | (GPIO66_DATAOUT << 2) |
+ (GPIO65_DATAOUT << 1) | (GPIO64_DATAOUT << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0130,
+ (GPIO127_DATAOUT << 31) | (GPIO126_DATAOUT << 30) | (GPIO125_DATAOUT << 29) |
+ (GPIO124_DATAOUT << 28) | (GPIO123_DATAOUT << 27) | (GPIO122_DATAOUT << 26) |
+ (GPIO121_DATAOUT << 25) | (GPIO120_DATAOUT << 24) | (GPIO119_DATAOUT << 23) |
+ (GPIO118_DATAOUT << 22) | (GPIO117_DATAOUT << 21) | (GPIO116_DATAOUT << 20) |
+ (GPIO115_DATAOUT << 19) | (GPIO114_DATAOUT << 18) | (GPIO113_DATAOUT << 17) |
+ (GPIO112_DATAOUT << 16) | (GPIO111_DATAOUT << 15) | (GPIO110_DATAOUT << 14) |
+ (GPIO109_DATAOUT << 13) | (GPIO108_DATAOUT << 12) | (GPIO107_DATAOUT << 11) |
+ (GPIO106_DATAOUT << 10) | (GPIO105_DATAOUT << 9) | (GPIO104_DATAOUT << 8) |
+ (GPIO103_DATAOUT << 7) | (GPIO102_DATAOUT << 6) | (GPIO101_DATAOUT << 5) |
+ (GPIO100_DATAOUT << 4) | (GPIO99_DATAOUT << 3) | (GPIO98_DATAOUT << 2) |
+ (GPIO97_DATAOUT << 1) | (GPIO96_DATAOUT << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0140,
+ (GPIO159_DATAOUT << 31) | (GPIO158_DATAOUT << 30) | (GPIO157_DATAOUT << 29) |
+ (GPIO156_DATAOUT << 28) | (GPIO155_DATAOUT << 27) | (GPIO154_DATAOUT << 26) |
+ (GPIO153_DATAOUT << 25) | (GPIO152_DATAOUT << 24) | (GPIO151_DATAOUT << 23) |
+ (GPIO150_DATAOUT << 22) | (GPIO149_DATAOUT << 21) | (GPIO148_DATAOUT << 20) |
+ (GPIO147_DATAOUT << 19) | (GPIO146_DATAOUT << 18) | (GPIO145_DATAOUT << 17) |
+ (GPIO144_DATAOUT << 16) | (GPIO143_DATAOUT << 15) | (GPIO142_DATAOUT << 14) |
+ (GPIO141_DATAOUT << 13) | (GPIO140_DATAOUT << 12) | (GPIO139_DATAOUT << 11) |
+ (GPIO138_DATAOUT << 10) | (GPIO137_DATAOUT << 9) | (GPIO136_DATAOUT << 8) |
+ (GPIO135_DATAOUT << 7) | (GPIO134_DATAOUT << 6) | (GPIO133_DATAOUT << 5) |
+ (GPIO132_DATAOUT << 4) | (GPIO131_DATAOUT << 3) | (GPIO130_DATAOUT << 2) |
+ (GPIO129_DATAOUT << 1) | (GPIO128_DATAOUT << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4)| (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0150,
+ (GPIO160_DATAOUT << 0),
+ (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0000,
+ (GPIO31_DIR << 31) | (GPIO30_DIR << 30) | (GPIO29_DIR << 29) |
+ (GPIO28_DIR << 28) | (GPIO27_DIR << 27) | (GPIO26_DIR << 26) |
+ (GPIO25_DIR << 25) | (GPIO24_DIR << 24) | (GPIO23_DIR << 23) |
+ (GPIO22_DIR << 22) | (GPIO21_DIR << 21) | (GPIO20_DIR << 20) |
+ (GPIO19_DIR << 19) | (GPIO18_DIR << 18) | (GPIO17_DIR << 17) |
+ (GPIO16_DIR << 16) | (GPIO15_DIR << 15) | (GPIO14_DIR << 14) |
+ (GPIO13_DIR << 13) | (GPIO12_DIR << 12) | (GPIO11_DIR << 11) |
+ (GPIO10_DIR << 10) | (GPIO9_DIR << 9) | (GPIO8_DIR << 8) |
+ (GPIO7_DIR << 7) | (GPIO6_DIR << 6) | (GPIO5_DIR << 5) |
+ (GPIO4_DIR << 4) | (GPIO3_DIR << 3) | (GPIO2_DIR << 2) |
+ (GPIO1_DIR << 1) | (GPIO0_DIR << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0010,
+ (GPIO63_DIR << 31) | (GPIO62_DIR << 30) | (GPIO61_DIR << 29) |
+ (GPIO60_DIR << 28) | (GPIO59_DIR << 27) | (GPIO58_DIR << 26) |
+ (GPIO57_DIR << 25) | (GPIO56_DIR << 24) | (GPIO55_DIR << 23) |
+ (GPIO54_DIR << 22) | (GPIO53_DIR << 21) | (GPIO52_DIR << 20) |
+ (GPIO51_DIR << 19) | (GPIO50_DIR << 18) | (GPIO49_DIR << 17) |
+ (GPIO48_DIR << 16) | (GPIO47_DIR << 15) | (GPIO46_DIR << 14) |
+ (GPIO45_DIR << 13) | (GPIO44_DIR << 12) | (GPIO43_DIR << 11) |
+ (GPIO42_DIR << 10) | (GPIO41_DIR << 9) | (GPIO40_DIR << 8) |
+ (GPIO39_DIR << 7) | (GPIO38_DIR << 6) | (GPIO37_DIR << 5) |
+ (GPIO36_DIR << 4) | (GPIO35_DIR << 3) | (GPIO34_DIR << 2) |
+ (GPIO33_DIR << 1) | (GPIO32_DIR << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0020,
+ (GPIO95_DIR << 31) | (GPIO94_DIR << 30) | (GPIO93_DIR << 29) |
+ (GPIO92_DIR << 28) | (GPIO91_DIR << 27) | (GPIO90_DIR << 26) |
+ (GPIO89_DIR << 25) | (GPIO88_DIR << 24) | (GPIO87_DIR << 23) |
+ (GPIO86_DIR << 22) | (GPIO85_DIR << 21) | (GPIO84_DIR << 20) |
+ (GPIO83_DIR << 19) | (GPIO82_DIR << 18) | (GPIO81_DIR << 17) |
+ (GPIO80_DIR << 16) | (GPIO79_DIR << 15) | (GPIO78_DIR << 14) |
+ (GPIO77_DIR << 13) | (GPIO76_DIR << 12) | (GPIO75_DIR << 11) |
+ (GPIO74_DIR << 10) | (GPIO73_DIR << 9) | (GPIO72_DIR << 8) | (GPIO71_DIR << 7) |
+ (GPIO70_DIR << 6) | (GPIO69_DIR << 5) | (GPIO68_DIR << 4) | (GPIO67_DIR << 3) |
+ (GPIO66_DIR << 2) | (GPIO65_DIR << 1) | (GPIO64_DIR << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0030,
+ (GPIO127_DIR << 31) | (GPIO126_DIR << 30) | (GPIO125_DIR << 29) |
+ (GPIO124_DIR << 28) | (GPIO123_DIR << 27) | (GPIO122_DIR << 26) |
+ (GPIO121_DIR << 25) | (GPIO120_DIR << 24) | (GPIO119_DIR << 23) |
+ (GPIO118_DIR << 22) | (GPIO117_DIR << 21) | (GPIO116_DIR << 20) |
+ (GPIO115_DIR << 19) | (GPIO114_DIR << 18) | (GPIO113_DIR << 17) |
+ (GPIO112_DIR << 16) | (GPIO111_DIR << 15) | (GPIO110_DIR << 14) |
+ (GPIO109_DIR << 13) | (GPIO108_DIR << 12) | (GPIO107_DIR << 11) |
+ (GPIO106_DIR << 10) | (GPIO105_DIR << 9) | (GPIO104_DIR << 8) |
+ (GPIO103_DIR << 7) | (GPIO102_DIR << 6) | (GPIO101_DIR << 5) |
+ (GPIO100_DIR << 4) | (GPIO99_DIR << 3) | (GPIO98_DIR << 2) |
+ (GPIO97_DIR << 1) | (GPIO96_DIR << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0040,
+ (GPIO159_DIR << 31) | (GPIO158_DIR << 30) | (GPIO157_DIR << 29) |
+ (GPIO156_DIR << 28) | (GPIO155_DIR << 27) | (GPIO154_DIR << 26) |
+ (GPIO153_DIR << 25) | (GPIO152_DIR << 24) | (GPIO151_DIR << 23) |
+ (GPIO150_DIR << 22) | (GPIO149_DIR << 21) | (GPIO148_DIR << 20) |
+ (GPIO147_DIR << 19) | (GPIO146_DIR << 18) | (GPIO145_DIR << 17) |
+ (GPIO144_DIR << 16) | (GPIO143_DIR << 15) | (GPIO142_DIR << 14) |
+ (GPIO141_DIR << 13) | (GPIO140_DIR << 12) | (GPIO139_DIR << 11) |
+ (GPIO138_DIR << 10) | (GPIO137_DIR << 9) | (GPIO136_DIR << 8) |
+ (GPIO135_DIR << 7) | (GPIO134_DIR << 6) | (GPIO133_DIR << 5) |
+ (GPIO132_DIR << 4) | (GPIO131_DIR << 3) | (GPIO130_DIR << 2) |
+ (GPIO129_DIR << 1) | (GPIO128_DIR << 0),
+ (0x1 << 31) | (0x1 << 30) | (0x1 << 29) |
+ (0x1 << 28) | (0x1 << 27) | (0x1 << 26) |
+ (0x1 << 25) | (0x1 << 24) | (0x1 << 23) |
+ (0x1 << 22) | (0x1 << 21) | (0x1 << 20) |
+ (0x1 << 19) | (0x1 << 18) | (0x1 << 17) |
+ (0x1 << 16) | (0x1 << 15) | (0x1 << 14) |
+ (0x1 << 13) | (0x1 << 12) | (0x1 << 11) |
+ (0x1 << 10) | (0x1 << 9) | (0x1 << 8) |
+ (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
+ (0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
+ (0x1 << 1) | (0x1 << 0)
+ },
+ {
+ GPIO_BASE + 0x0050,
+ (GPIO160_DIR << 0),
+ (0x1 << 0)
+ },
+ {
+ IO_CFG_LM_BASE + 0x0050,
+ (GPIO36_PUPD << 2) | (GPIO35_PUPD << 3) |
+ (GPIO34_PUPD << 4) | (GPIO33_PUPD << 5) |
+ (GPIO32_PUPD << 1) | (GPIO31_PUPD << 0) |
+ (GPIO30_PUPD << 6),
+ (0x1 << 2) | (0x1 << 3) | (0x1 << 4) |
+ (0x1 << 5) | (0x1 << 1) | (0x1 << 0) |
+ (0x1 << 6)
+ },
+ {
+ IO_CFG_BL_BASE + 0x0050,
+ (GPIO64_PUPD << 0) | (GPIO63_PUPD << 2) |
+ (GPIO62_PUPD << 3) | (GPIO61_PUPD << 4) |
+ (GPIO60_PUPD << 5) | (GPIO59_PUPD << 1),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 3) |
+ (0x1 << 4) | (0x1 << 5) | (0x1 << 1)
+ },
+ {
+ IO_CFG_RM_BASE + 0x0060,
+ (GPIO115_PUPD << 0) | (GPIO114_PUPD << 2) | (GPIO113_PUPD << 1) |
+ (GPIO112_PUPD << 3) | (GPIO111_PUPD << 5) | (GPIO110_PUPD << 4),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 1) |
+ (0x1 << 3) | (0x1 << 5) | (0x1 << 4)
+ },
+ {
+ IO_CFG_TR_BASE + 0x0030,
+ (GPIO145_PUPD << 3) | (GPIO144_PUPD << 6) | (GPIO143_PUPD << 4) |
+ (GPIO142_PUPD << 1) | (GPIO141_PUPD << 2) | (GPIO140_PUPD << 11) |
+ (GPIO139_PUPD << 5) | (GPIO138_PUPD << 0) | (GPIO137_PUPD << 10) |
+ (GPIO136_PUPD << 9) | (GPIO135_PUPD << 7) | (GPIO134_PUPD << 8),
+ (0x1 << 3) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 2) | (0x1 << 11) |
+ (0x1 << 5) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 9) | (0x1 << 7) | (0x1 << 8)
+ },
+ {
+ IO_CFG_LM_BASE + 0x0070,
+ (GPIO36_R0 << 2) | (GPIO35_R0 << 3) | (GPIO34_R0 << 4) |
+ (GPIO33_R0 << 5) | (GPIO32_R0 << 1) | (GPIO31_R0 << 0) |
+ (GPIO30_R0 << 6),
+ (0x1 << 2) | (0x1 << 3) | (0x1 << 4) |
+ (0x1 << 5) | (0x1 << 1) | (0x1 << 0) |
+ (0x1 << 6)
+ },
+ {
+ IO_CFG_BL_BASE + 0x0070,
+ (GPIO64_R0 << 0) | (GPIO63_R0 << 2) | (GPIO62_R0 << 3) |
+ (GPIO61_R0 << 4) | (GPIO60_R0 << 5) | (GPIO59_R0 << 1),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 3) |
+ (0x1 << 4) | (0x1 << 5) | (0x1 << 1)
+ },
+ {
+ IO_CFG_RM_BASE + 0x0080,
+ (GPIO115_R0 << 0) | (GPIO114_R0 << 2) | (GPIO113_R0 << 1) |
+ (GPIO112_R0 << 3) | (GPIO111_R0 << 5) | (GPIO110_R0 << 4),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 1) |
+ (0x1 << 3) | (0x1 << 5) | (0x1 << 4)
+ },
+ {
+ IO_CFG_TR_BASE + 0x0040,
+ (GPIO145_R0 << 3) | (GPIO144_R0 << 6) | (GPIO143_R0 << 4) |
+ (GPIO142_R0 << 1) | (GPIO141_R0 << 2) | (GPIO140_R0 << 11) |
+ (GPIO139_R0 << 5) | (GPIO138_R0 << 0) | (GPIO137_R0 << 10) |
+ (GPIO136_R0 << 9) | (GPIO135_R0 << 7) | (GPIO134_R0 << 8),
+ (0x1 << 3) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 2) | (0x1 << 11) |
+ (0x1 << 5) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 9) | (0x1 << 7) | (0x1 << 8)
+ },
+ {
+ IO_CFG_LM_BASE + 0x0080,
+ (GPIO36_R1 << 2) | (GPIO35_R1 << 3) | (GPIO34_R1 << 4) |
+ (GPIO33_R1 << 5) | (GPIO32_R1 << 1) | (GPIO31_R1 << 0) |
+ (GPIO30_R1 << 6),
+ (0x1 << 2) | (0x1 << 3) | (0x1 << 4) |
+ (0x1 << 5) | (0x1 << 1) | (0x1 << 0) |
+ (0x1 << 6)
+ },
+ {
+ IO_CFG_BL_BASE + 0x0080,
+ (GPIO64_R1 << 0) | (GPIO63_R1 << 2) | (GPIO62_R1 << 3) |
+ (GPIO61_R1 << 4) | (GPIO60_R1 << 5) | (GPIO59_R1 << 1),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 3) |
+ (0x1 << 4) | (0x1 << 5) | (0x1 << 1)
+ },
+ {
+ IO_CFG_RM_BASE + 0x0090,
+ (GPIO115_R1 << 0) | (GPIO114_R1 << 2) | (GPIO113_R1 << 1) |
+ (GPIO112_R1 << 3) | (GPIO111_R1 << 5) | (GPIO110_R1 << 4),
+ (0x1 << 0) | (0x1 << 2) | (0x1 << 1) |
+ (0x1 << 3) | (0x1 << 5) | (0x1 << 4)
+ },
+ {
+ IO_CFG_TR_BASE + 0x0050,
+ (GPIO145_R1 << 3) | (GPIO144_R1 << 6) | (GPIO143_R1 << 4) |
+ (GPIO142_R1 << 1) | (GPIO141_R1 << 2) | (GPIO140_R1 << 11) |
+ (GPIO139_R1 << 5) | (GPIO138_R1 << 0) | (GPIO137_R1 << 10) |
+ (GPIO136_R1 << 9) | (GPIO135_R1 << 7) | (GPIO134_R1 << 8),
+ (0x1 << 3) | (0x1 << 6) | (0x1 << 4) |
+ (0x1 << 1) | (0x1 << 2) | (0x1 << 11) |
+ (0x1 << 5) | (0x1 << 0) | (0x1 << 10) |
+ (0x1 << 9) | (0x1 << 7) | (0x1 << 8)
+ }
+};
+
+void mt_i2c_gpio_init(void)
+{
+ u32 reg_val;
+
+ /* set the i2c gpio pull up R select*/
+ /* SDA2 [11:10] SCL2 [5:4] */
+ /* SDA1 [9:8] SCL1 [3:2] */
+ /* SDA0 [7:6] SCL0 [1:0] */
+ /* 00:75k 01:5k 10:15k 11:1k */
+ reg_val = readl(IO_CFG_LB_BASE + RSEL_CFG);
+ reg_val |= 0xfff;
+ writel(reg_val, IO_CFG_LB_BASE + RSEL_CFG);
+
+ /* i2c GPIO EH setting */
+ /* i2c GPIO EH setting use dafault value */
+
+ /* i2c pull up setting*/
+ /* i2c pull up default enable */
+
+}
+
+void mt_gpio_init(void)
+{
+ u32 i;
+ u32 reg_val;
+
+ /* set the gpio settings from cust_gpio_boot.h */
+ for (i = 0; i < ARRAY_SIZE(gpio_init_value); i++) {
+ reg_val = readl(gpio_init_value[i].reg_addr);
+ reg_val &= ~gpio_init_value[i].mask;
+ reg_val |= gpio_init_value[i].val;
+ writel(reg_val, gpio_init_value[i].reg_addr);
+ }
+
+ mt_i2c_gpio_init();
+
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/hsm/hsm.h b/src/bsp/lk/platform/mt2731/drivers/hsm/hsm.h
new file mode 100644
index 0000000..0db0868
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/hsm/hsm.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2019. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#ifndef _MTK_DRV_HSM_H
+#define _MTK_DRV_HSM_H
+
+/* header file */
+#include <reg.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_typedefs.h>
+
+/* register */
+#define SECURITY_AO_BASE (IO_PHYS + 0x0001A000)
+#define HSM_CPU_RST_B (SECURITY_AO_BASE + 0x640)
+#define HSM_EX_IRQ_SEL2 (SECURITY_AO_BASE + 0x64C)
+#define HSM_EX_IRQ_TRANS_LEVEL2 (SECURITY_AO_BASE + 0x664)
+
+/* definition */
+#define HSM_SET_BITS(REG, BIT) ((*(volatile unsigned int *)(REG)) |= (unsigned int)(BIT))
+#define HSM_CLR_BITS(REG, BIT) ((*(volatile unsigned int *)(REG)) &= ~((unsigned int)(BIT)))
+
+#define HSM_OS_SIZE (256*1024)
+
+#define HSM_OS_RAM_ADDR (0x44170000)
+#define HSM_OS_RAM_SIZE (0x100000)
+
+#define MPU_REGION_OF_HSM (25)
+
+#endif
\ No newline at end of file
diff --git a/src/bsp/lk/platform/mt2731/drivers/hsm/load_hsm.c b/src/bsp/lk/platform/mt2731/drivers/hsm/load_hsm.c
new file mode 100644
index 0000000..4f77ec5
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/hsm/load_hsm.c
@@ -0,0 +1,211 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2020. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_gpt_v4.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+
+#include <arch/ops.h>
+#include <assert.h>
+#include <lib/bio.h>
+#include <errno.h>
+#include <platform.h>
+#include <trace.h>
+
+#include "hsm.h"
+
+#define MODULE_NAME "LK_LD_HSM"
+
+/* MPU setting */
+#include "platform/emi_mpu_mt.h"
+
+static const unsigned long long mpu_att_hsm[16] = {
+ SEC_RW, [1 ... 10] = FORBIDDEN, NO_PROTECTION, [12 ... 15] = FORBIDDEN };
+
+static void hsm_set_mpu_setting(void)
+{
+ struct emi_region_info_t region_info;
+
+ region_info.start = HSM_OS_RAM_ADDR;
+ region_info.end = HSM_OS_RAM_ADDR + HSM_OS_RAM_SIZE - 1;
+ region_info.region = MPU_REGION_OF_HSM;
+
+ /* MPU region lock */
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ mpu_att_hsm[15], mpu_att_hsm[14],
+ mpu_att_hsm[13], mpu_att_hsm[12],
+ mpu_att_hsm[11], mpu_att_hsm[10],
+ mpu_att_hsm[9], mpu_att_hsm[8],
+ mpu_att_hsm[7], mpu_att_hsm[6],
+ mpu_att_hsm[5], mpu_att_hsm[4],
+ mpu_att_hsm[3], mpu_att_hsm[2],
+ mpu_att_hsm[1], mpu_att_hsm[0]);
+
+ emi_mpu_set_protection(®ion_info);
+}
+
+
+/* Device tree related */
+#define HSM_OS_RAM_RESERVE_NODENAME "reserve-memory-hsm-os-ram"
+#define HSM_OS_RAM_RESERVE_COMPATIBLE "mediatek,reserve-memory-hsm-os-ram"
+
+#define HSM_OS_IMG_RESERVE_NODENAME "reserve-memory-hsm-os-img"
+#define HSM_OS_IMG_RESERVE_COMPATIBLE "mediatek,reserve-memory-hsm-os-img"
+
+#define HSM_NODE_COMPATIBLE_PROP "compatible"
+#define HSM_NODE_ARRTIBUTE_PROP "no-map"
+#define HSM_NODE_RANGE_PROP "reg"
+
+static int hsm_write_reserve_memory_to_dt(void *fdt_dtb, unsigned int addr, unsigned int size, const char *node_name, const char *compatible_name)
+{
+ int parsent_node, img_node;
+ int ret;
+ fdt32_t range[4];
+
+ /* debug */
+ dprintf(CRITICAL, "[HSM] DT reserve addr 0x%x, size 0x%x\n", (unsigned int)addr, size);
+
+ /* early skip */
+ if (size == 0)
+ return 0;
+
+ /* Find out reserved-memory */
+ parsent_node = fdt_path_offset(fdt_dtb, "/reserved-memory");
+ if (parsent_node < 0) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "fdt_path_offset");
+ ASSERT(0);
+ return parsent_node;
+ }
+
+ /* To add a new subnode */
+ img_node = fdt_add_subnode(fdt_dtb, parsent_node, node_name);
+ if (img_node < 0) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "fdt_add_subnode");
+ return img_node;
+ }
+
+ range[0] = range[2] = 0;
+ range[1] = cpu_to_fdt32(addr);
+ range[3] = cpu_to_fdt32(size);
+ ret = fdt_setprop(fdt_dtb, img_node, HSM_NODE_RANGE_PROP, range, sizeof(range));
+ if (ret)
+ return ret;
+
+ ret = fdt_setprop(fdt_dtb, img_node, HSM_NODE_ARRTIBUTE_PROP, NULL, 0);
+ if (ret)
+ return ret;
+
+ ret = fdt_setprop_string(fdt_dtb, img_node, HSM_NODE_COMPATIBLE_PROP, compatible_name);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+extern __WEAK paddr_t kvaddr_to_paddr(void *ptr);
+
+int hsm_update_info_to_dt(void *boot_dtb)
+{
+ /* Set MPU setting to protect HSM memory */
+ hsm_set_mpu_setting();
+
+ /* HSM OS RAM part */
+ hsm_write_reserve_memory_to_dt(boot_dtb, HSM_OS_RAM_ADDR, HSM_OS_RAM_SIZE, HSM_OS_RAM_RESERVE_NODENAME, HSM_OS_RAM_RESERVE_COMPATIBLE);
+
+ /* HSM OS IMG part */
+ hsm_write_reserve_memory_to_dt(boot_dtb, HSM_OS_ADDR, HSM_OS_SIZE, HSM_OS_IMG_RESERVE_NODENAME, HSM_OS_IMG_RESERVE_COMPATIBLE);
+
+ return 0;
+}
+
+
+/* HSM operation */
+static void hsm_reset(void)
+{
+ /* release HSM from reset */
+ writel(0x0, HSM_CPU_RST_B);
+ writel(0x1, HSM_CPU_RST_B);
+
+ /* set boot address to ROM */
+ HSM_CLR_BITS(HSM_EX_IRQ_TRANS_LEVEL2, 0x1FFFE);
+ HSM_CLR_BITS(HSM_EX_IRQ_SEL2, 0x3FFFE);
+
+ /* HSM software reset */
+ HSM_SET_BITS(0x10001140, 0x200);
+ gpt_busy_wait_ms(1);
+ HSM_SET_BITS(0x10001144, 0x200);
+}
+
+static int load_raw_data(const char *part_name, unsigned char *mem_addr, int size)
+{
+ bdev_t *bdev;
+ int len;
+
+ arch_clean_invalidate_cache_range((addr_t)mem_addr, size);
+ bdev = bio_open_by_label(part_name);
+ if (!bdev) {
+ dprintf(CRITICAL,"partition %s not exists\n", part_name);
+ return -ENODEV;
+ }
+
+ len = bio_read(bdev, mem_addr, 0, size);
+ if (len < 0) {
+ dprintf(CRITICAL, "[%s] %s boot image header read error. LINE: %d\n", MODULE_NAME, part_name, __LINE__);
+ return -EIO;;
+ }
+
+ bio_close(bdev);
+ arch_clean_invalidate_cache_range((addr_t)mem_addr, size);
+
+ return len;
+}
+
+int load_hsm_os(const char *part_name)
+{
+ int err;
+
+ /* load HSM OS */
+ err = load_raw_data(part_name, (unsigned char *)HSM_OS_ADDR, HSM_OS_SIZE);
+
+ if (err > 0) {
+ /* release reset pin to trigger HSM */
+ hsm_reset();
+ }
+
+ return 0;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/hsm/rules.mk b/src/bsp/lk/platform/mt2731/drivers/hsm/rules.mk
new file mode 100644
index 0000000..42c3e38
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/hsm/rules.mk
@@ -0,0 +1,4 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/load_hsm.c \
diff --git a/src/bsp/lk/platform/mt2731/drivers/i2c/mtk_i2c.c b/src/bsp/lk/platform/mt2731/drivers/i2c/mtk_i2c.c
new file mode 100644
index 0000000..43c40b0
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/i2c/mtk_i2c.c
@@ -0,0 +1,920 @@
+#include <stdint.h>
+#include <platform/mtk_i2c.h>
+//#include <platform/mt_pmic_wrap_init.h>
+//#include <platform/mt_gpio.h>
+
+/******************************internal API********************************************************/
+#define I2C_PMIC_WR(addr, data) pwrap_write((U32)addr, data)
+#define I2C_PMIC_RD(addr) ({ \
+ U32 ext_data; \
+ (pwrap_read((U32)addr,&ext_data) != 0)?-1:ext_data;})
+
+static inline void i2c_writel(mt_i2c * i2c, U8 offset, U16 value)
+{
+ //__raw_writew(value, (i2c->base) + (offset));
+ writel(value, (i2c->base) + (offset));
+}
+
+static inline U32 i2c_readl(mt_i2c * i2c, U16 offset)
+{
+ return readl((i2c->base) + (offset));
+}
+/***********************************declare API**************************/
+static void mt_i2c_clock_enable(mt_i2c *i2c);
+static void mt_i2c_clock_disable(mt_i2c *i2c);
+
+/***********************************I2C DEBUG********************************************************/
+#define I2C_DEBUG_FS
+#ifdef I2C_DEBUG_FS
+#define PORT_COUNT 8
+#define MESSAGE_COUNT 16
+#define I2C_T_DMA 1
+#define I2C_T_TRANSFERFLOW 2
+#define I2C_T_SPEED 3
+/*7 ports,16 types of message*/
+U8 i2c_port[ PORT_COUNT ][ MESSAGE_COUNT ];
+
+#define I2CINFO( type, format, arg...) do { \
+ if ( type < MESSAGE_COUNT && type >= 0 ) { \
+ if ( i2c_port[i2c->id][0] != 0 && ( i2c_port[i2c->id][type] != 0 || i2c_port[i2c->id][MESSAGE_COUNT - 1] != 0) ) { \
+ I2CLOG( format, ## arg); \
+ } \
+ } \
+ } while (0)
+#else
+#define I2CINFO(type, format, arg...)
+#endif
+/***********************************common API********************************************************/
+/*Set i2c port speed*/
+
+/* calculate i2c port speed */
+static S32 mtk_i2c_calculate_speed(mt_i2c *i2c,
+ U32 clk_src_in_khz,
+ U32 speed_hkz,
+ U32 *timing_step_cnt,
+ U32 *timing_sample_cnt)
+{
+ U32 khz;
+ U32 step_cnt;
+ U32 sample_cnt;
+ U32 sclk;
+ U32 hclk;
+ U32 max_step_cnt;
+ U32 sample_div = MAX_SAMPLE_CNT_DIV;
+ U32 step_div;
+ U32 min_div;
+ U32 best_mul;
+ U32 cnt_mul;
+
+ if (speed_hkz > MAX_HS_MODE_SPEED) {
+ return -EINVAL_I2C;
+ } else if (speed_hkz > MAX_FS_MODE_SPEED) {
+ max_step_cnt = MAX_HS_STEP_CNT_DIV;
+ } else {
+ max_step_cnt = MAX_STEP_CNT_DIV;
+ }
+ step_div = max_step_cnt;
+
+ /* Find the best combination */
+ khz = speed_hkz;
+ hclk = clk_src_in_khz;
+ min_div = ((hclk >> 1) + khz - 1) / khz;
+ best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
+ for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
+ step_cnt = (min_div + sample_cnt - 1) / sample_cnt;
+ cnt_mul = step_cnt * sample_cnt;
+ if (step_cnt > max_step_cnt)
+ continue;
+ if (cnt_mul < best_mul) {
+ best_mul = cnt_mul;
+ sample_div = sample_cnt;
+ step_div = step_cnt;
+ if (best_mul == min_div)
+ break;
+ }
+ }
+ sample_cnt = sample_div;
+ step_cnt = step_div;
+ sclk = hclk / (2 * sample_cnt * step_cnt);
+ if (sclk > khz) {
+ I2CERR("i2c%d %s mode: unsupported speed (%dkhz)\n",
+ i2c->id, (speed_hkz > MAX_FS_MODE_SPEED) ? "HS" : "ST/FT", khz);
+ return -EINVAL_I2C;
+ }
+
+ /* Just for MT6765/MT6762/MT6779 */
+ /* which the step_cnt needn't minus 1 when sample_cnt==1 */
+ if (--sample_cnt)
+ step_cnt--;
+
+ *timing_step_cnt = step_cnt;
+ *timing_sample_cnt = sample_cnt;
+
+ return 0;
+}
+
+/*Set i2c port speed*/
+S32 i2c_set_speed(mt_i2c *i2c)
+{
+ int ret = 0;
+ U32 step_cnt = 0;
+ U32 sample_cnt = 0;
+ U32 l_step_cnt = 0;
+ U32 l_sample_cnt = 0;
+ static U32 speedInHz;
+ U32 clk_src_in_khz = i2c->clk;
+ U32 duty = 50;
+ U32 high_speed_reg;
+ static S32 mode = 0;
+ U32 timing_reg;
+ U32 ltiming_reg;
+
+ if (clk_src_in_khz == 0) {
+ I2CERR(" zero i2c source clock.\n");
+ ret = -EINVAL_I2C;
+ goto end;
+ }
+
+ mode = i2c->mode;
+ speedInHz = i2c->speed;
+
+ if ((mode == FS_MODE && speedInHz > MAX_FS_MODE_SPEED) ||
+ (mode == HS_MODE && speedInHz > MAX_HS_MODE_SPEED)) {
+ I2CERR(" the speed is too fast for this mode.\n");
+ I2C_BUG_ON((mode == FS_MODE && khz > MAX_FS_MODE_SPEED) ||
+ (mode == HS_MODE && khz > MAX_HS_MODE_SPEED));
+ ret = -EINVAL_I2C;
+ goto end;
+ }
+
+ if (speedInHz > MAX_FS_MODE_SPEED && !i2c->pushpull) {
+ /* Set the high speed mode register */
+ ret = mtk_i2c_calculate_speed(i2c, clk_src_in_khz,
+ MAX_FS_MODE_SPEED, &l_step_cnt, &l_sample_cnt);
+ if (ret < 0)
+ return ret;
+
+ ret = mtk_i2c_calculate_speed(i2c, clk_src_in_khz,
+ speedInHz, &step_cnt, &sample_cnt);
+ if (ret < 0)
+ return ret;
+
+ high_speed_reg = 0x3 |
+ (sample_cnt & 0x7) << 12 |
+ (step_cnt & 0x7) << 8;
+
+ timing_reg =
+ (l_sample_cnt & 0x7) << 8 |
+ (l_step_cnt & 0x3f) << 0;
+
+
+ ltiming_reg = (l_sample_cnt << 6) | (l_step_cnt << 0) |
+ (sample_cnt & 0x7) << 12 |
+ (step_cnt & 0x7) << 9;
+ } else {
+ if (speedInHz > MAX_ST_MODE_SPEED && speedInHz <= MAX_FS_MODE_SPEED)
+ duty = DUTY_CYCLE;
+ ret = mtk_i2c_calculate_speed(i2c, clk_src_in_khz,
+ (speedInHz * 50 / duty), &step_cnt, &sample_cnt);
+ if (ret < 0)
+ return ret;
+
+ ret = mtk_i2c_calculate_speed(i2c, clk_src_in_khz,
+ (speedInHz * 50 / (100 - duty)), &l_step_cnt, &l_sample_cnt);
+ if (ret < 0)
+ return ret;
+
+ timing_reg =
+ (sample_cnt & 0x7) << 8 |
+ (step_cnt & 0x3f) << 0;
+
+ ltiming_reg = (l_sample_cnt & 0x7) << 6 |
+ (l_step_cnt & 0x3f) << 0;
+ /* Disable the high speed transaction */
+ high_speed_reg = 0x0;
+ }
+
+ i2c->htiming_reg = timing_reg;
+ i2c->ltiming_reg = ltiming_reg;
+ i2c->high_speed_reg = high_speed_reg;
+end:
+ return ret;
+}
+
+void _i2c_dump_info(mt_i2c *i2c)
+{
+ //I2CFUC();
+ I2CERR("I2C structure:\n"
+ I2CTAG"Clk=%d,Id=%d,Mode=%x,St_rs=%x,Dma_en=%x,Op=%x,Poll_en=%x,Irq_stat=%x\n"
+ I2CTAG"Trans_len=%x,Trans_num=%x,Trans_auxlen=%x,Data_size=%x,speed=%d\n",
+ //,Trans_stop=%u,Trans_comp=%u,Trans_error=%u\n"
+ i2c->clk,i2c->id,i2c->mode,i2c->st_rs,i2c->dma_en,i2c->op,i2c->poll_en,i2c->irq_stat,
+ i2c->trans_data.trans_len,i2c->trans_data.trans_num,i2c->trans_data.trans_auxlen,i2c->trans_data.data_size,i2c->speed);
+ // atomic_read(&i2c->trans_stop),atomic_read(&i2c->trans_comp),atomic_read(&i2c->trans_err),
+
+ I2CERR("base address 0x%lx\n",i2c->base);
+ I2CERR("I2C register:\n"
+ I2CTAG"SLAVE_ADDR=%x,INTR_MASK=%x,INTR_STAT=%x,CONTROL=%x,TRANSFER_LEN=%x\n"
+ I2CTAG"TRANSAC_LEN=%x,DELAY_LEN=%x,HTIMING=%x,LTIMING=%x,START=%x,FIFO_STAT=%x\n"
+ I2CTAG"IO_CONFIG=%x,HS=%x,DCM_EN=%x,DEBUGSTAT=%x,EXT_CONF=%x,TRANSFER_LEN_AUX=%x\n",
+ (i2c_readl(i2c, OFFSET_SLAVE_ADDR)),
+ (i2c_readl(i2c, OFFSET_INTR_MASK)),
+ (i2c_readl(i2c, OFFSET_INTR_STAT)),
+ (i2c_readl(i2c, OFFSET_CONTROL)),
+ (i2c_readl(i2c, OFFSET_TRANSFER_LEN)),
+ (i2c_readl(i2c, OFFSET_TRANSAC_LEN)),
+ (i2c_readl(i2c, OFFSET_DELAY_LEN)),
+ (i2c_readl(i2c, OFFSET_HTIMING)),
+ (i2c_readl(i2c, OFFSET_LTIMING)),
+ (i2c_readl(i2c, OFFSET_START)),
+ (i2c_readl(i2c, OFFSET_FIFO_STAT)),
+ (i2c_readl(i2c, OFFSET_IO_CONFIG)),
+ (i2c_readl(i2c, OFFSET_HS)),
+ (i2c_readl(i2c, OFFSET_DCM_EN)),
+ (i2c_readl(i2c, OFFSET_DEBUGSTAT)),
+ (i2c_readl(i2c, OFFSET_EXT_CONF)),
+ (i2c_readl(i2c, OFFSET_TRANSFER_LEN_AUX)));
+ /*
+ I2CERR("DMA register:\nINT_FLAG %x\nCON %x\nTX_MEM_ADDR %x\nRX_MEM_ADDR %x\nTX_LEN %x\nRX_LEN %x\nINT_EN %x\nEN %x\n",
+ (__raw_readl(i2c->pdmabase+OFFSET_INT_FLAG)),
+ (__raw_readl(i2c->pdmabase+OFFSET_CON)),
+ (__raw_readl(i2c->pdmabase+OFFSET_TX_MEM_ADDR)),
+ (__raw_readl(i2c->pdmabase+OFFSET_RX_MEM_ADDR)),
+ (__raw_readl(i2c->pdmabase+OFFSET_TX_LEN)),
+ (__raw_readl(i2c->pdmabase+OFFSET_RX_LEN)),
+ (__raw_readl(i2c->pdmabase+OFFSET_S32_EN)),
+ (__raw_readl(i2c->pdmabase+OFFSET_EN)));
+ */
+ /*6589 side and PMIC side clock*/
+ //I2CERR("Clock %s\n",(((readl(0xF0003018)>>26) | (readl(0xF000301c)&0x1 << 6)) & (1 << i2c->id))?"disable":"enable");
+ //if(i2c->id >=4)
+ // I2CERR("Clock PMIC %s\n",((I2C_PMIC_RD(0x011A) & 0x7) & (1 << (i2c->id - 4)))?"disable":"enable");
+ //1<<(i2c->id-4): 0x011A bit[0~2]:i2c0~2,i2c->id:i2c 4~6
+ return;
+}
+static S32 _i2c_deal_result(mt_i2c *i2c)
+{
+ long tmo = 1;
+ U16 data_size = 0;
+ U8 *ptr = i2c->msg_buf;
+ BOOL TRANSFER_ERROR=FALSE;
+ S32 ret = i2c->msg_len;
+ long tmo_poll = 0xffff;
+ //I2CFUC();
+ //addr_reg = i2c->read_flag ? ((i2c->addr << 1) | 0x1) : ((i2c->addr << 1) & ~0x1);
+
+ if (i2c->poll_en) {
+ /*master read && poll mode*/
+ for (;;) {
+ /*check the interrupt status register*/
+ i2c->irq_stat = i2c_readl(i2c, OFFSET_INTR_STAT);
+ //I2CLOG("irq_stat = 0x%x\n", i2c->irq_stat);
+ if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR )) {
+ //transfer error
+ //atomic_set(&i2c->trans_stop, 1);
+ //spin_lock(&i2c->lock);
+ /*Clear interrupt status,write 1 clear*/
+ //i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR | I2C_ACKERR ));
+ TRANSFER_ERROR=TRUE;
+ tmo = 1;
+ //spin_unlock(&i2c->lock);
+ break;
+ } else if (i2c->irq_stat & I2C_TRANSAC_COMP) {
+ //transfer complete
+ tmo = 1;
+ break;
+ }
+ tmo_poll --;
+ if (tmo_poll == 0) {
+ tmo = 0;
+ break;
+ }
+ }
+ } else { /*Interrupt mode,wait for interrupt wake up*/
+ //tmo = wait_event_timeout(i2c->wait,atomic_read(&i2c->trans_stop), tmo);
+ }
+
+ //I2CLOG("tmo = 0x%x\n", tmo);
+ /*Check the transfer status*/
+ if (!(tmo == 0 )&& TRANSFER_ERROR==FALSE ) {
+ /*Transfer success ,we need to get data from fifo*/
+ if ((!i2c->dma_en) && (i2c->op == I2C_MASTER_RD || i2c->op == I2C_MASTER_WRRD) ) {
+ /*only read mode or write_read mode and fifo mode need to get data*/
+ if (I2C_MASTER_WRRD != i2c->op)
+ data_size = (i2c->msg_len) & 0xFFFF;
+ else
+ data_size = (i2c->msg_len >> 16) & 0xFFFF;
+
+ //I2CLOG("data_size=%d\n",data_size);
+ while (data_size--) {
+ *ptr = i2c_readl(i2c, OFFSET_DATA_PORT);
+#ifdef I2C_EARLY_PORTING
+ I2CLOG("addr %x read byte = 0x%x\n", i2c->addr, *ptr);
+#endif
+ ptr++;
+ }
+ }
+ } else {
+ /*Timeout or ACKERR*/
+ if ( tmo == 0 ) {
+ I2CERR("id=%d,addr: %x, transfer timeout\n",i2c->id, i2c->addr);
+ ret = -ETIMEDOUT_I2C;
+ } else {
+ I2CERR("id=%d,addr: %x, transfer error\n",i2c->id,i2c->addr);
+ ret = -EREMOTEIO_I2C;
+ }
+ if (i2c->irq_stat & I2C_HS_NACKERR)
+ I2CERR("I2C_HS_NACKERR\n");
+ if (i2c->irq_stat & I2C_ACKERR)
+ I2CERR("I2C_ACKERR\n");
+ if (i2c->filter_msg==FALSE) { //TEST
+ _i2c_dump_info(i2c);
+ }
+
+ //spin_lock(&i2c->lock);
+ /*Reset i2c port*/
+ i2c_writel(i2c, OFFSET_SOFTRESET, 0x0001);
+ /*Set slave address*/
+ i2c_writel( i2c, OFFSET_SLAVE_ADDR, 0x0000 );
+ /*Clear interrupt status*/
+ i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR|I2C_ACKERR|I2C_TRANSAC_COMP));
+ /*Clear fifo address*/
+ i2c_writel(i2c, OFFSET_FIFO_ADDR_CLR, 0x0005);
+
+ //spin_unlock(&i2c->lock);
+ }
+ return ret;
+}
+
+
+void _i2c_write_reg(mt_i2c *i2c)
+{
+ U8 *ptr = i2c->msg_buf;
+ U32 data_size=i2c->trans_data.data_size;
+ U32 addr_reg=0;
+ //I2CFUC();
+
+ //i2c_writel(i2c, OFFSET_CONTROL, i2c->control_reg);
+ i2c_writel(i2c, OFFSET_CLOCK_DIV, ((I2C_CLK_DIV - 1) << 8) +
+ (I2C_CLK_DIV - 1));
+ /*set start condition */
+ if (i2c->speed <= 100) {
+ i2c_writel(i2c,OFFSET_EXT_CONF, 0x8001);
+ } else {
+ i2c_writel(i2c, OFFSET_EXT_CONF, 0x1801);
+ }
+ //set timing reg
+ i2c_writel(i2c, OFFSET_HTIMING, i2c->htiming_reg);
+ i2c_writel(i2c, OFFSET_LTIMING, i2c->ltiming_reg);
+ i2c_writel(i2c, OFFSET_HS, i2c->high_speed_reg);
+ if (0 == i2c->delay_len)
+ i2c->delay_len = 2;
+ if (~i2c->control_reg & I2C_CONTROL_RS) { // bit is set to 1, i.e.,use repeated stop
+ i2c_writel(i2c, OFFSET_DELAY_LEN, i2c->delay_len);
+ }
+ /*Set ioconfig*/
+ if (i2c->pushpull) {
+ i2c->control_reg &= (~I2C_CONTROL_CLK_EXT_EN);
+ i2c_writel(i2c, OFFSET_CONTROL, i2c->control_reg);
+ i2c_writel(i2c, OFFSET_IO_CONFIG, 0x0000);
+ } else {
+ i2c_writel(i2c, OFFSET_IO_CONFIG, 0x0003);
+ i2c_writel(i2c, OFFSET_CONTROL, i2c->control_reg);
+ }
+
+ /*Set slave address*/
+ addr_reg = i2c->read_flag ? ((i2c->addr << 1) | 0x1) : ((i2c->addr << 1) & ~0x1);
+ i2c_writel(i2c, OFFSET_SLAVE_ADDR, addr_reg);
+ /*Clear interrupt status*/
+ i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP));
+ /*Clear fifo address*/
+ i2c_writel(i2c, OFFSET_FIFO_ADDR_CLR, 0x0005);
+ /*Setup the interrupt mask flag*/
+ if (i2c->poll_en)
+ i2c_writel(i2c, OFFSET_INTR_MASK, i2c_readl(i2c, OFFSET_INTR_MASK) & ~(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP)); /*Disable interrupt*/
+ else
+ i2c_writel(i2c, OFFSET_INTR_MASK, i2c_readl(i2c, OFFSET_INTR_MASK) | (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP)); /*Enable interrupt*/
+ /*Set transfer len */
+ i2c_writel(i2c, OFFSET_TRANSFER_LEN, i2c->trans_data.trans_len & 0xFFFF);
+ i2c_writel(i2c, OFFSET_TRANSFER_LEN_AUX, i2c->trans_data.trans_auxlen & 0xFFFF);
+ /*Set transaction len*/
+ i2c_writel(i2c, OFFSET_TRANSAC_LEN, i2c->trans_data.trans_num & 0xFF);
+ /*Prepare buffer data to start transfer*/
+
+#if 0
+ if (i2c->dma_en) {
+ /* Reset I2C DMA status */
+ mt_reg_sync_writel(0x0001, i2c->pdmabase + OFFSET_RST);
+ if (I2C_MASTER_RD == i2c->op) {
+ mt_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
+ mt_reg_sync_writel(0x0001, i2c->pdmabase + OFFSET_CON);
+ mt_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
+ mt_reg_sync_writel(i2c->trans_data.data_size, i2c->pdmabase + OFFSET_RX_LEN);
+ } else if (I2C_MASTER_WR == i2c->op) {
+ mt_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
+ mt_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_CON);
+ mt_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
+ mt_reg_sync_writel(i2c->trans_data.data_size, i2c->pdmabase + OFFSET_TX_LEN);
+ } else {
+ mt_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
+ mt_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_CON);
+ mt_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
+ mt_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
+ mt_reg_sync_writel(i2c->trans_data.trans_len, i2c->pdmabase + OFFSET_TX_LEN);
+ mt_reg_sync_writel(i2c->trans_data.trans_auxlen, i2c->pdmabase + OFFSET_RX_LEN);
+ }
+ I2C_MB();
+ mt_reg_sync_writel(0x0001, i2c->pdmabase + OFFSET_EN);
+
+ I2CINFO( I2C_T_DMA, "addr %.2x dma %.2X byte\n", i2c->addr, i2c->trans_data.data_size);
+ I2CINFO( I2C_T_DMA, "DMA Register:INT_FLAG:0x%x,CON:0x%x,TX_MEM_ADDR:0x%x, \
+ RX_MEM_ADDR:0x%x,TX_LEN:0x%x,RX_LEN:0x%x,EN:0x%x\n",\
+ readl(i2c->pdmabase + OFFSET_INT_FLAG),\
+ readl(i2c->pdmabase + OFFSET_CON),\
+ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),\
+ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR),\
+ readl(i2c->pdmabase + OFFSET_TX_LEN),\
+ readl(i2c->pdmabase + OFFSET_RX_LEN),\
+ readl(i2c->pdmabase + OFFSET_EN));
+
+ } else {
+#endif
+
+/*Set fifo mode data*/
+ if (I2C_MASTER_RD == i2c->op) {
+ /*do not need set fifo data*/
+ } else {
+ /*both write && write_read mode*/
+ while (data_size--) {
+ i2c_writel(i2c, OFFSET_DATA_PORT, *ptr);
+ //dev_info(i2c->dev, "addr %.2x write byte = 0x%.2X\n", addr, *ptr);
+ ptr++;
+ }
+ }
+#if 0
+ }
+#endif
+ /*Set trans_data*/
+ i2c->trans_data.data_size = data_size;
+
+}
+S32 _i2c_get_transfer_len(mt_i2c *i2c)
+{
+ S32 ret = I2C_OK;
+ u16 trans_num = 0;
+ u16 data_size = 0;
+ u16 trans_len = 0;
+ u16 trans_auxlen = 0;
+ //I2CFUC();
+ /*Get Transfer len and transaux len*/
+ if (FALSE == i2c->dma_en) {
+ /*non-DMA mode*/
+ if (I2C_MASTER_WRRD != i2c->op) {
+ trans_len = (i2c->msg_len) & 0xFFFF;
+ trans_num = (i2c->msg_len >> 16) & 0xFF;
+ if (0 == trans_num)
+ trans_num = 1;
+ trans_auxlen = 0;
+ data_size = trans_len*trans_num;
+
+ if (!trans_len || !trans_num || trans_len*trans_num > I2C_FIFO_SIZE) {
+ I2CERR(" non-WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
+ I2C_BUG_ON(!trans_len || !trans_num || trans_len*trans_num > I2C_FIFO_SIZE);
+ ret = -EINVAL_I2C;
+ }
+ } else {
+ trans_len = (i2c->msg_len) & 0xFFFF;
+ trans_auxlen = (i2c->msg_len >> 16) & 0xFFFF;
+ trans_num = 2;
+ data_size = trans_len;
+ if (!trans_len || !trans_auxlen || trans_len > I2C_FIFO_SIZE || trans_auxlen > I2C_FIFO_SIZE) {
+ I2CERR(" WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
+ I2C_BUG_ON(!trans_len || !trans_auxlen || trans_len > I2C_FIFO_SIZE || trans_auxlen > I2C_FIFO_SIZE);
+ ret = -EINVAL_I2C;
+ }
+ }
+ } else {
+ /*DMA mode*/
+ if (I2C_MASTER_WRRD != i2c->op) {
+ trans_len = (i2c->msg_len) & 0xFFFF;
+ trans_num = (i2c->msg_len >> 16) & 0xFF;
+ if (0 == trans_num)
+ trans_num = 1;
+ trans_auxlen = 0;
+ data_size = trans_len*trans_num;
+
+ if (!trans_len || !trans_num || trans_len > MAX_DMA_TRANS_SIZE || trans_num > MAX_DMA_TRANS_NUM) {
+ I2CERR(" DMA non-WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
+ I2C_BUG_ON(!trans_len || !trans_num || trans_len > MAX_DMA_TRANS_SIZE || trans_num > MAX_DMA_TRANS_NUM);
+ ret = -EINVAL_I2C;
+ }
+ I2CINFO(I2C_T_DMA, "DMA non-WRRD mode!trans_len=%x, tans_num=%x, trans_auxlen=%x\n",trans_len, trans_num, trans_auxlen);
+ } else {
+ trans_len = (i2c->msg_len) & 0xFFFF;
+ trans_auxlen = (i2c->msg_len >> 16) & 0xFFFF;
+ trans_num = 2;
+ data_size = trans_len;
+ if (!trans_len || !trans_auxlen || trans_len > MAX_DMA_TRANS_SIZE || trans_auxlen > MAX_DMA_TRANS_NUM) {
+ I2CERR(" DMA WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
+ I2C_BUG_ON(!trans_len || !trans_auxlen || trans_len > MAX_DMA_TRANS_SIZE || trans_auxlen > MAX_DMA_TRANS_NUM);
+ ret = -EINVAL_I2C;
+ }
+ I2CINFO(I2C_T_DMA, "DMA WRRD mode!trans_len=%x, tans_num=%x, trans_auxlen=%x\n",trans_len, trans_num, trans_auxlen);
+ }
+ }
+
+ i2c->trans_data.trans_num = trans_num;
+ i2c->trans_data.trans_len = trans_len;
+ i2c->trans_data.data_size = data_size;
+ i2c->trans_data.trans_auxlen = trans_auxlen;
+
+ return ret;
+}
+S32 _i2c_transfer_interface(mt_i2c *i2c)
+{
+ S32 return_value=0;
+ S32 ret=0;
+ U8 *ptr = i2c->msg_buf;
+ //I2CFUC();
+ if (i2c->dma_en) {
+ I2CINFO( I2C_T_DMA, "DMA Transfer mode!\n");
+ if (i2c->pdmabase == 0) {
+ I2CERR(" I2C%d doesnot support DMA mode!\n",i2c->id);
+ I2C_BUG_ON(i2c->pdmabase == NULL);
+ ret = -EINVAL_I2C;
+ goto err;
+ }
+ if ((uintptr_t)ptr > DMA_ADDRESS_HIGH) {
+ I2CERR(" DMA mode should use physical buffer address!\n");
+ I2C_BUG_ON((U32)ptr > DMA_ADDRESS_HIGH);
+ ret = -EINVAL_I2C;
+ goto err;
+ }
+ }
+
+ i2c->irq_stat = 0;
+ return_value=_i2c_get_transfer_len(i2c);
+ if ( return_value < 0 ) {
+ I2CERR("_i2c_get_transfer_len fail,return_value=%d\n",return_value);
+ ret =-EINVAL_I2C;
+ goto err;
+ }
+ //get clock
+ i2c->clk = I2C_CLK_RATE;
+
+ return_value=i2c_set_speed(i2c);
+ if ( return_value < 0 ) {
+ I2CERR("i2c_set_speed fail,return_value=%d\n",return_value);
+ ret =-EINVAL_I2C;
+ goto err;
+ }
+ /*Set Control Register*/
+#ifdef CONFIG_MT_I2C_FPGA_ENABLE
+ i2c->control_reg = I2C_CONTROL_ACKERR_DET_EN;
+#else
+ i2c->control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN;
+#endif
+ if (i2c->dma_en) {
+ i2c->control_reg |= I2C_CONTROL_DMA_EN;
+ }
+ if (I2C_MASTER_WRRD == i2c->op)
+ i2c->control_reg |= I2C_CONTROL_DIR_CHANGE;
+
+ if (HS_MODE == i2c->mode || (i2c->trans_data.trans_num > 1 && I2C_TRANS_REPEATED_START == i2c->st_rs)) {
+ i2c->control_reg |= I2C_CONTROL_RS;
+ }
+
+ //spin_lock(&i2c->lock);
+ _i2c_write_reg(i2c);
+ /*All register must be prepared before setting the start bit [SMP]*/
+ I2C_MB();
+ I2CINFO( I2C_T_TRANSFERFLOW, "Before start .....\n");
+ /*Start the transfer*/
+ i2c_writel(i2c, OFFSET_START, 0x0001);
+ //spin_unlock(&i2c->lock);
+ ret = _i2c_deal_result(i2c);
+ I2CINFO(I2C_T_TRANSFERFLOW, "After i2c transfer .....\n");
+err:
+
+ return ret;
+}
+S32 _i2c_check_para(mt_i2c *i2c)
+{
+ S32 ret=0;
+ //I2CFUC();
+ if (i2c->addr == 0) {
+ I2CERR(" addr is invalid.\n");
+ I2C_BUG_ON(i2c->addr == NULL);
+ ret = -EINVAL_I2C;
+ goto err;
+ }
+
+ if (i2c->msg_buf == NULL) {
+ I2CERR(" data buffer is NULL.\n");
+ I2C_BUG_ON(i2c->msg_buf == NULL);
+ ret = -EINVAL_I2C;
+ goto err;
+ }
+err:
+ return ret;
+
+}
+
+void _config_mt_i2c(mt_i2c *i2c)
+{
+ //I2CFUC();
+ switch (i2c->id) {
+ case I2C0:
+ i2c->base = I2C0_BASE;
+ i2c->pdmabase = I2C0_APDMA_BASE;
+ break;
+ case I2C1:
+ i2c->base = I2C1_BASE;
+ i2c->pdmabase = I2C1_APDMA_BASE;
+ break;
+ case I2C2:
+ i2c->base = I2C2_BASE;
+ i2c->pdmabase = I2C2_APDMA_BASE;
+ break;
+ case I2C3:
+ i2c->base = I2C3_BASE;
+ i2c->pdmabase = I2C3_APDMA_BASE;
+ break;
+ case I2C4:
+ i2c->base = I2C4_BASE;
+ i2c->pdmabase = I2C4_APDMA_BASE;
+ break;
+ default:
+ I2CERR("invalid para: i2c->id=%d\n", i2c->id);
+ break;
+ }
+ if (i2c->st_rs == I2C_TRANS_REPEATED_START)
+ i2c->st_rs = I2C_TRANS_REPEATED_START;
+ else
+ i2c->st_rs = I2C_TRANS_STOP;
+
+ i2c->dma_en = FALSE;
+ i2c->poll_en = TRUE;
+
+ if (i2c->filter_msg == TRUE)
+ i2c->filter_msg = TRUE;
+ else
+ i2c->filter_msg = FALSE;
+
+ ///*Set device speed,set it before set_control register
+ if (0 == i2c->speed) {
+ i2c->mode = ST_MODE;
+ i2c->speed = MAX_ST_MODE_SPEED;
+ } else {
+ if (i2c->mode == HS_MODE)
+ i2c->mode = HS_MODE;
+ else
+ i2c->mode = FS_MODE;
+ }
+
+ /*Set ioconfig*/
+ if (i2c->pushpull==TRUE)
+ i2c->pushpull=TRUE;
+ else
+ i2c->pushpull=FALSE;
+
+}
+
+/*-----------------------------------------------------------------------
+ * new read interface: Read bytes
+ * mt_i2c: I2C chip config, see mt_i2c_t.
+ * buffer: Where to read/write the data.
+ * len: How many bytes to read/write
+ * Returns: ERROR_CODE
+ */
+S32 i2c_read(mt_i2c *i2c,U8 *buffer, U32 len)
+{
+ S32 ret = I2C_OK;
+#ifdef I2C_EARLY_PORTING
+ I2CFUC();
+#endif
+ //read
+ i2c->read_flag|= I2C_M_RD;
+ i2c->op = I2C_MASTER_RD;
+ i2c->msg_buf = buffer;
+ i2c->msg_len = len;
+ ret=_i2c_check_para(i2c);
+ if (ret< 0) {
+ I2CERR(" _i2c_check_para fail\n");
+ goto err;
+ }
+
+ _config_mt_i2c(i2c);
+ //get the addr
+ ret=_i2c_transfer_interface(i2c);
+
+ if ((int)i2c->msg_len != ret) {
+ I2CERR("read %d bytes fails,ret=%d.\n",i2c->msg_len,ret);
+ ret = -1;
+ return ret;
+ } else {
+ ret = I2C_OK;
+ //I2CLOG("read %d bytes pass,ret=%d.\n",i2c->msg_len,ret);
+ }
+err:
+ return ret;
+}
+
+/*-----------------------------------------------------------------------
+ * New write interface: Write bytes
+ * i2c: I2C chip config, see mt_i2c_t.
+ * buffer: Where to read/write the data.
+ * len: How many bytes to read/write
+ * Returns: ERROR_CODE
+ */
+S32 i2c_write(mt_i2c *i2c,U8 *buffer, U32 len)
+{
+ S32 ret = I2C_OK;
+#ifdef I2C_EARLY_PORTING
+ I2CFUC();
+#endif
+ //write
+ i2c->read_flag = !I2C_M_RD;
+ i2c->op = I2C_MASTER_WR;
+ i2c->msg_buf = buffer;
+ i2c->msg_len = len;
+ ret=_i2c_check_para(i2c);
+ if (ret< 0) {
+ I2CERR(" _i2c_check_para fail\n");
+ goto err;
+ }
+
+ _config_mt_i2c(i2c);
+ //get the addr
+ ret=_i2c_transfer_interface(i2c);
+
+ if ((int)i2c->msg_len != ret) {
+ I2CERR("Write %d bytes fails,ret=%d.\n",i2c->msg_len,ret);
+ ret = -1;
+ return ret;
+ } else {
+ ret = I2C_OK;
+ //I2CLOG("Write %d bytes pass,ret=%d.\n",i2c->msg_len,ret);
+ }
+err:
+ return ret;
+}
+
+/*-----------------------------------------------------------------------
+ * New write then read back interface: Write bytes then read bytes
+ * i2c: I2C chip config, see mt_i2c_t.
+ * buffer: Where to read/write the data.
+ * write_len: How many bytes to write
+ * read_len: How many bytes to read
+ * Returns: ERROR_CODE
+ */
+S32 i2c_write_read(mt_i2c *i2c,U8 *buffer, U32 write_len, U32 read_len)
+{
+ S32 ret = I2C_OK;
+ //I2CFUC();
+ //write and read
+ i2c->op = I2C_MASTER_WRRD;
+ i2c->read_flag=!I2C_M_RD;
+ i2c->msg_buf = buffer;
+ i2c->msg_len = ((read_len & 0xFFFF) << 16) | (write_len & 0xFFFF);
+ ret=_i2c_check_para(i2c);
+ if (ret< 0) {
+ I2CERR(" _i2c_check_para fail\n");
+ goto err;
+ }
+
+ _config_mt_i2c(i2c);
+ //get the addr
+ ret=_i2c_transfer_interface(i2c);
+
+ if ((int)i2c->msg_len != ret) {
+ I2CERR("write_read 0x%x bytes fails,ret=%d.\n",i2c->msg_len,ret);
+ ret = -1;
+ return ret;
+ } else {
+ ret = I2C_OK;
+ //I2CLOG("write_read 0x%x bytes pass,ret=%d.\n",i2c->msg_len,ret);
+ }
+err:
+ return ret;
+}
+
+int i2c_hw_init(void)
+{
+#ifdef I2C_EARLY_PORTING_TEST
+ mt_i2c_test();
+#endif
+ return 0;
+}
+
+/* Test LK_I2C */
+#ifdef I2C_EARLY_PORTING_TEST
+U32 mt_i2c_test_device(int id, int addr, int offset, int value)
+{
+ U32 ret = 0;
+ U32 len = 0;
+ U8 write_byte[2], read_byte[2];
+ U32 delay_count = 0xff;
+ struct mt_i2c_t i2c;
+ //int i = 0;
+
+ I2CLOG("i2c %d test start++++++++++++++++++++\n", id);
+
+
+ i2c.id = id;
+ i2c.addr = addr;
+ i2c.mode = FS_MODE;
+ i2c.speed = 200;
+ /* i2c.mode = FS_MODE;
+ i2c.speed = 200;*/
+ /* ================================================== */
+
+ I2CLOG("\ntest i2c write\n\n");
+ write_byte[0] = offset;
+ write_byte[1] = value;
+ len = 2;
+ ret = i2c_write(&i2c, write_byte, len);
+ if (I2C_OK != ret) {
+ I2CERR("Write 2 bytes fails(%lx).\n", ret);
+ ret = -1;
+ return ret;
+ } else {
+ I2CLOG("Write 2 bytes pass,these bytes are %x, %x.\n", write_byte[0],
+ write_byte[1]);
+ }
+
+ /* mdelay(1000); */
+
+ for (delay_count = 0xff; delay_count > 0; delay_count--) ;
+ /* ================================================== */
+ I2CLOG("\ntest i2c read\n\n");
+ //1st:write addree 00,1byte(0x0A)
+ //write_byte[0] = 0x0e;
+ write_byte[0] = offset;
+
+ len = 1;
+ ret = i2c_write(&i2c, write_byte, len);
+ if (I2C_OK != ret) {
+ I2CERR("Write 1 bytes fails(%lx).\n", ret);
+ ret = -1;
+ return ret;
+ //continue;
+ } else {
+ I2CLOG("Write 1 bytes pass,these bytes are %x.\n", write_byte[0]);
+ }
+ /* mdelay(1000); */
+ for (delay_count = 0xff; delay_count > 0; delay_count--) ;
+ /* 2rd:read back 1byte(0x0A) */
+ read_byte[0] = 0x55;
+ len = 1;
+ ret = i2c_read(&i2c, read_byte, len);
+ if ((I2C_OK != ret) || read_byte[0] != value) {
+ I2CERR("read 1 bytes fails(%lx).\n", ret);
+ I2CLOG("read 1 bytes ,read_byte=%x\n", read_byte[0]);
+ ret = -1;
+ return ret;
+ //continue;
+ } else {
+ I2CLOG("read 1 bytes pass,read_byte=%x\n", read_byte[0]);
+ }
+
+ /* mdelay(1000); */
+
+ for (delay_count = 0xff; delay_count > 0; delay_count--) ;
+ /* ================================================== */
+ I2CLOG("\ntest i2c write_read\n\n");
+ read_byte[0] = offset;
+ /* write_byte[1] = 0x34; */
+ len = (1 & 0xFF) << 8 | (1 & 0xFF);
+ ret = i2c_write_read(&i2c, read_byte, 1, 1);
+ if (I2C_OK != ret || read_byte[0] != value) {
+ I2CERR("write_read 1 byte fails(ret=%lx).\n", ret);
+ I2CLOG("write_read 1 byte fails, read_byte=%x\n", read_byte[0]);
+ ret = -1;
+ return ret;
+ } else {
+ I2CLOG("Write_Read 1 byte pass ,this byte is %x.\n", read_byte[0]);
+ ret = 0;
+ }
+
+ I2CLOG("i2c %d test done-------------------\n", id);
+ return ret;
+}
+
+int mt_i2c_test(void)
+{
+ int ret;
+ int i = 0;
+
+ for (i = 0; i < 1; i++) {
+ //ret = mt_i2c_test_eeprom(i);
+ ret = mt_i2c_test_device(i, 0x0c, 0x31, 0x03);
+ if (0 == ret) {
+ I2CLOG("I2C%d,EEPROM test PASS!!\n", i);
+ } else {
+ I2CLOG("I2C%d,EEPROM test FAIL!!(%d)\n", i, ret);
+ }
+ }
+ return 0;
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/key/mtk_key.c b/src/bsp/lk/platform/mt2731/drivers/key/mtk_key.c
new file mode 100644
index 0000000..f5b5524
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/key/mtk_key.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <debug.h>
+#include <platform/mt_reg_base.h>
+#include <reg.h>
+
+#define GPIO_DIN1 (GPIO_BASE + 0x210)
+
+bool check_download_key(void)
+{
+#if !(CFG_FPGA_PLATFORM)
+ return (readl(GPIO_DIN1) & (1U << 26)) == 0;
+#else
+ return false;
+#endif
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.c
new file mode 100644
index 0000000..0adfb35
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.c
@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <arch/ops.h>
+#include <errno.h>
+#include <lib/bio.h>
+#include <libfdt.h>
+#include <lib/decompress.h>
+#include <kernel/thread.h>
+#include <kernel/vm.h>
+#include <trace.h>
+
+#include "ccci_fit.h"
+#include "image.h"
+
+#define LOCAL_TRACE 0
+
+#define uswap_32(x) \
+ ((((x) & 0xff000000) >> 24) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x000000ff) << 24))
+
+int ccci_fit_image_get_node(const void *fit, const char *image_uname)
+{
+ int noffset, images_noffset;
+
+ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ if (images_noffset < 0) {
+ dprintf(CRITICAL,"Can't find images parent node '%s' (%s)\n",
+ FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+ return images_noffset;
+ }
+
+ noffset = fdt_subnode_offset(fit, images_noffset, image_uname);
+ if (noffset < 0) {
+ dprintf(CRITICAL,"Can't get node offset for image name: '%s' (%s)\n",
+ image_uname, fdt_strerror(noffset));
+ }
+
+ return noffset;
+}
+
+int ccci_fit_image_get_data(const void *fit, int noffset,
+ const void **data, uint32_t *size)
+{
+ int len;
+ *data = fdt_getprop(fit, noffset, FDT_DATA_NODE, &len);
+ if (*data == NULL)
+ return -1;
+
+ *size = len;
+
+ return 0;
+}
+
+int ccci_fit_conf_get_prop_node(const void *fit, int noffset,
+ const char *prop_name)
+{
+ char *uname;
+ int len;
+
+ /* get kernel image unit name from configuration kernel property */
+ uname = (char *)fdt_getprop(fit, noffset, prop_name, &len);
+ if (uname == NULL)
+ return len;
+
+ return ccci_fit_image_get_node(fit, uname);
+}
+
+/**
+ * fit_get_img_subnode_offset() - get a subnode offset for a given image name
+ *
+ * This finds subnode offset using given image name within node "/images"
+ *
+ * @fit: fit image start address
+ * @image_name: image name. "kernel", "fdt" or "ramdisk"...
+ *
+ * returns:
+ * great than or equal 0, on success
+ * otherwise, on failure
+ *
+ */
+static int ccci_fit_get_img_subnode_offset(void *fit, const char *image_name)
+{
+ int noffset;
+
+ /* get image node offset */
+ noffset = fdt_path_offset(fit, "/images");
+ if (noffset < 0) {
+ dprintf(CRITICAL, "Can't find image node(%s)\n", fdt_strerror(noffset));
+ return noffset;
+ }
+
+ /* get subnode offset */
+ noffset = fdt_subnode_offset(fit, noffset, image_name);
+ if (noffset < 0)
+ dprintf(CRITICAL, "Can't get node offset for image name: '%s' (%s)\n",
+ image_name, fdt_strerror(noffset));
+
+ return noffset;
+}
+
+/**
+ * fit_get_def_cfg_offset() - get a subnode offset from node "/configurations"
+ *
+ * This finds configuration subnode offset in node "configruations".
+ * If "conf" is not given, it will find property "default" for the case.
+ *
+ * @fit: fit image start address
+ * @conf: configuration name
+ *
+ * returns:
+ * great than or equal 0, on success
+ * otherwise, on failure
+ *
+ */
+static int ccci_fit_get_def_cfg_offset(void *fit, const char *conf)
+{
+ int noffset, cfg_noffset, len;
+
+ noffset = fdt_path_offset(fit, "/configurations");
+ if (noffset < 0) {
+ dprintf(CRITICAL, "can't find configuration node\n");
+ return noffset;
+ }
+
+ if (conf == NULL) {
+ conf = (char *)fdt_getprop(fit, noffset,
+ "default", &len);
+ if (conf == NULL) {
+ dprintf(CRITICAL, "Can't get default conf name\n");
+ return len;
+ }
+ dprintf(SPEW, "got default conf: %s\n", conf);
+ }
+
+ cfg_noffset = fdt_subnode_offset(fit, noffset, conf);
+ if (cfg_noffset < 0)
+ dprintf(CRITICAL, "Can't get conf subnode\n");
+ else
+ dprintf(SPEW, "got conf: %s subnode\n", conf);
+
+ return cfg_noffset;
+}
+
+int ccci_fit_get_image(const char *label, void *md_mem_base)
+{
+ bdev_t *bdev;
+ struct fdt_header fdt;
+ size_t totalsize;
+ int fdt_len, ret = 0;
+
+ fdt_len = sizeof(struct fdt_header);
+ bdev = bio_open_by_label(label) ? : bio_open(label);
+ if (!bdev) {
+ dprintf(CRITICAL, "Partition [%s] is not exist.\n", label);
+ return -ENODEV;
+ }
+
+ if (bio_read(bdev, &fdt, 0, fdt_len) < fdt_len) {
+ ret = -EIO;
+ goto closebdev;
+ }
+
+ ret = fdt_check_header(&fdt);
+ if (ret) {
+ dprintf(CRITICAL, "[%s] check header failed\n", label);
+ goto closebdev;
+ }
+
+ totalsize = fdt_totalsize(&fdt);
+
+ if (bio_read(bdev, md_mem_base, 0, totalsize) < totalsize) {
+ ret = -EIO;
+ goto closebdev;
+ }
+
+closebdev:
+ bio_close(bdev);
+
+ return ret;
+}
+
+int ccci_fit_processing_data(void *fit, const char *image_name, int noffset,
+ addr_t *load, size_t *load_size, paddr_t *entry)
+{
+ int len, ret, ac;
+ size_t size;
+ const char *type;
+ const void *data, *compression;
+ const uint32_t *load_prop, *entry_prop;
+ addr_t load_addr;
+ paddr_t entry_addr;
+
+ data = fdt_getprop(fit, noffset, "data", &len);
+ if (!data) {
+ dprintf(CRITICAL, "%s can't get prop data\n", image_name);
+ return len;
+ }
+ size = len;
+
+ compression = fdt_getprop(fit, noffset, "compression", &len);
+ if (!compression) {
+ dprintf(CRITICAL, "%s compression is not specified\n", image_name);
+ return -EINVAL;
+ }
+
+ type = fdt_getprop(fit, noffset, "type", &len);
+ if (!type) {
+ dprintf(CRITICAL, "%s image type is not specified\n", image_name);
+ return -EINVAL;
+ }
+
+ /* read address-cells from root */
+ ac = fdt_address_cells(fit, 0);
+ if (ac <= 0 || (ac > sizeof(ulong) / sizeof(uint))) {
+ LTRACEF("%s #address-cells with a bad format or value\n", image_name);
+ return -EINVAL;
+ }
+
+ load_prop = fdt_getprop(fit, noffset, "load", &len);
+ if (!load_prop &&
+ (!strcmp(type, "kernel") || (!strcmp(type, "loadable")))) {
+ dprintf(CRITICAL, "%s need load addr\n", image_name);
+ return -EINVAL;
+ }
+
+ /* load address determination:
+ * 1. "load" property exist: use address in "load" property
+ * 2. "load" property not exist: use runtime address of "data" property
+ */
+ load_addr = (addr_t)data;
+ if (load_prop) {
+ load_addr = (addr_t)uswap_32(load_prop[0]);
+ if (ac == 2)
+ load_addr = (load_addr << 32) | (addr_t)uswap_32(load_prop[1]);
+#if WITH_KERNEL_VM
+ load_addr = (addr_t)paddr_to_kvaddr(load_addr);
+#endif
+ }
+
+ if (!strcmp((char *)compression, "lz4")) {
+ ret = unlz4(data, size - 4, (void *)(load_addr));
+ if (ret != LZ4_OK) {
+ dprintf(ALWAYS, "lz4 decompress failure\n");
+ return -LZ4_FAIL;
+ }
+ /* In lz4 kernel image, the last four bytes are the uncompressed
+ * kernel image size */
+ size = *(u32 *)(data + size - 4);
+ } else if (!strcmp((char *)compression, "none")) {
+ memmove((void *)(load_addr), data, size);
+ } else {
+ dprintf(CRITICAL, "%s compression does not support\n", image_name);
+ return -EINVAL;
+ }
+
+#if WITH_KERNEL_VM
+ /* always flush cache to PoC */
+ arch_clean_cache_range(load_addr, size);
+#endif
+
+ LTRACEF("[%s] load_addr 0x%lx\n", image_name, load_addr);
+ LTRACEF("[%s] fit = %p\n", image_name, fit);
+ LTRACEF("[%s] data = %p\n", image_name, data);
+ LTRACEF("[%s] size = %zu\n", image_name, size);
+
+ /* return load, load_size and entry address if caller spcified */
+ if (load)
+ *load = load_addr;
+
+ if (load_size)
+ *load_size = size;
+
+ if (entry) {
+ /*
+ * entry address determination:
+ * 1. "entry" property not exist: entry address = load address
+ * 2. "entry" & "load" properties both exist: "entry" property
+ * contains the absolute address of entry, thus
+ * entry address = "entry"
+ * 3. only "entry" property exist: "entry" property contains the
+ * entry offset to load address, thus
+ * entry address = "entry" + load address
+ */
+
+#if WITH_KERNEL_VM
+ load_addr = kvaddr_to_paddr((void *)load_addr);
+#endif
+ entry_addr = load_addr;
+ entry_prop = fdt_getprop(fit, noffset, "entry", &len);
+ if (entry_prop) {
+ entry_addr = (paddr_t)uswap_32(entry_prop[0]);
+ if (ac == 2) {
+ entry_addr = (entry_addr << 32) |
+ (paddr_t)uswap_32(entry_prop[1]);
+ }
+ entry_addr += load_prop ? 0 : load_addr;
+ }
+ *entry = entry_addr;
+
+ LTRACEF("[%s] entry_addr 0x%lx\n", image_name, *entry);
+ }
+
+ return 0;
+}
+
+int ccci_fit_load_loadable_image(void *fit, const char *sub_node_name, addr_t *load)
+{
+ int noffset;
+ int ret;
+
+ noffset = ccci_fit_get_img_subnode_offset(fit, sub_node_name);
+ if (noffset < 0) {
+ LTRACEF("%s: fit_get_img_subnode_offset fail\n", sub_node_name);
+ return noffset;
+ }
+
+ if (hash_check_enabled()) {
+ ret = fit_image_integrity_verify(fit, noffset);
+ LTRACEF("%s: integrity check %s\n",
+ sub_node_name, ret ? "fail" : "pass");
+ if (ret)
+ return -EACCES;
+ }
+
+ return ccci_fit_processing_data(fit, sub_node_name, noffset, load, NULL, NULL);
+}
+
+int ccci_fit_conf_verify_sig(const char *conf, void *fit)
+{
+ int ret;
+ int noffset;
+
+ /* get defualt configuration offset (conf@1, conf@2,...or confg@n) */
+ noffset = ccci_fit_get_def_cfg_offset(fit, conf);
+ if (noffset < 0)
+ return noffset;
+
+ /* verify config signature */
+ if (rsa_check_enabled()) {
+ ret = fit_verify_sign(fit, noffset);
+ dprintf(ALWAYS, "Verify sign: %s\n", ret ? "fail" : "pass");
+ if (ret)
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+static int ccci_fit_image_integrity_check_process(void *arg)
+{
+ int ret;
+ struct verify_data *verify_info;
+
+ verify_info = (struct verify_data *)arg;
+ ret = fit_image_integrity_verify(verify_info->fit_image,
+ verify_info->noffset);
+
+ return ret;
+}
+
+int ccci_fit_load_image(const char *conf, const char *img_pro, void *fit,
+ addr_t *load, size_t *load_size, paddr_t *entry,
+ bool need_verified)
+{
+ int noffset, len, cfg_noffset;
+ int ret, rc;
+ const char *image_name;
+ thread_t *integrity_verify_t;
+
+ /* get defualt configuration offset (conf@1, conf@2,...or confg@n) */
+ cfg_noffset = ccci_fit_get_def_cfg_offset(fit, conf);
+ if (cfg_noffset < 0)
+ return cfg_noffset;
+
+ /* unit name: fdt@1, kernel@2, ramdisk@3 and so on */
+ image_name = (char *)fdt_getprop(fit, cfg_noffset, img_pro, &len);
+ if (image_name == NULL) {
+ LTRACEF("%s get image name failed\n", img_pro);
+ return -ENOENT;
+ }
+
+ /* get this sub image node offset */
+ noffset = ccci_fit_get_img_subnode_offset(fit, image_name);
+ if (noffset < 0) {
+ dprintf(CRITICAL, "get sub image node (%s) failed\n", image_name);
+ return noffset;
+ }
+
+ /* verify integrity of this image */
+ if (hash_check_enabled() && need_verified) {
+#if WITH_SMP
+ struct verify_data verify_info;
+ verify_info.fit_image = fit;
+ verify_info.noffset = noffset;
+
+ integrity_verify_t = thread_create("integrity_verify_t",
+ &ccci_fit_image_integrity_check_process, &verify_info,
+ DEFAULT_PRIORITY, DEFAULT_STACK_SIZE);
+
+ /* Assigned the thread to active cpu */
+ extern __WEAK void plat_mp_assign_workcpu(thread_t *t);
+ plat_mp_assign_workcpu(integrity_verify_t);
+ thread_resume(integrity_verify_t);
+#else
+ ret = fit_image_integrity_verify(fit, noffset);
+ LTRACEF_LEVEL(CRITICAL, "check %s integrity: %s\n",
+ image_name, ret ? "fail" : "pass");
+ if (ret < 0)
+ return -EACCES;
+#endif
+ } /* verify end */
+
+ //rc = fit_processing_data(fit, image_name, noffset, load, load_size, entry);
+
+#if WITH_SMP
+ if (hash_check_enabled() && need_verified) {
+ thread_join(integrity_verify_t, &ret, INFINITE_TIME);
+ LTRACEF_LEVEL(CRITICAL, "check %s integrity: %s\n",
+ image_name, ret ? "fail" : "pass");
+ if (ret < 0)
+ return -EACCES;
+ }
+#endif
+
+ return rc;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.h b/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.h
new file mode 100644
index 0000000..a684558
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_fit.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <sys/types.h>
+
+/**
+ * fit_get_image() - load fit image from a partition
+ *
+ * the function will use bio to access a partition from a storage and
+ * check fdt header. If pass, allocate memory buffer to read the fit image
+ * to load_buf
+ *
+ * @label: partition name
+ * @load_buf: pointer to buffer pointer, the address of allocated memory
+ * buffer with fit image loaded was passing back to the caller
+ * via this argument.
+ *
+ * returns:
+ * 0, on success
+ * otherwise, on failure
+ *
+ */
+int ccci_fit_get_image(const char *label, void *md_mem_base);
+
+/**
+ * fit_image_get_data() - get data property of a subimage node
+ * @fit: fit image start address
+ * @noffset: the offset to the subimage node
+ * @data: return data pointer
+ * @size: return data size
+ *
+ * returns:
+ * 0, on success
+ * otherwise, on failure
+ */
+int ccci_fit_image_get_data(const void *fit, int noffset,
+ const void **data, uint32_t *size);
+/**
+ * fit_conf_verify_sig() - verify fit configuration signature
+ *
+ * @conf: configuration name
+ * @fit: fit image start address
+ *
+ * returns:
+ * 0, on success
+ * otherwise, on failure
+ */
+int ccci_fit_conf_verify_sig(const char *conf, void *fit);
+
+/**
+ * fit_load_image() - load fit image to proper address
+ *
+ * This checks FIT configuration to find sub-image nodes image
+ * and load the image to right address
+ *
+ * @conf: configuration name
+ * @img_pro: image property name
+ * @fit: fit image start address
+ * @load: returned load address
+ * @load_size: returned loaded raw image size
+ * @entry: returned entry address
+ * @need_verified: whether to check image integrity
+ *
+ * returns:
+ * 0, on success
+ * otherwise, on failure
+ *
+ */
+int ccci_fit_load_image(const char *conf, const char *img_pro, void *fit,
+ addr_t *load, size_t *load_size, paddr_t *entry,
+ bool need_verified);
+
+/**
+ * fit_load_loadable_image() - load "loadable" images to "load" address
+ *
+ * This function finds "sub_node_name" loadable image nodes, do integrity check
+ * per hash_check_enabled(), and load images to "load" address.
+ *
+ * @fit: fit image start address
+ * @sub_node_name: loadable image subnode name
+ * @load: returned loadable image load address
+ *
+ * return:
+ * 0: success
+ * otherwise: failure error code
+ *
+ */
+int ccci_fit_load_loadable_image(void *fit, const char *sub_node_name, addr_t *load);
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_api_wrapper.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_api_wrapper.c
new file mode 100644
index 0000000..3082053
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_api_wrapper.c
@@ -0,0 +1,381 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#ifdef MBLOCK_LIB_SUPPORT
+#include <mblock.h>
+#endif
+#ifdef MTK_AB_OTA_UPDATER
+#include "bootctrl.h"
+#endif
+#include <assert.h>
+#ifdef TELE_CCCI_SUPPORT
+#include <lib/bio.h>
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#include <platform/sec_export.h>
+#include <block_generic_interface.h>
+#include <part_interface.h>
+#include <part_status.h>
+#endif
+
+#define MODULE_NAME "LK_LD_MD"
+
+#ifndef TELE_CCCI_SUPPORT
+/***************************************************************************************************
+** Sub section:
+** Memory operation: Reserve, Resize, Return
+***************************************************************************************************/
+extern BOOT_ARGUMENT *g_boot_arg;
+#endif
+static int free_in_kernel;
+extern void arch_clean_invalidate_cache_range(addr_t start, size_t len);
+
+int ccci_resize_reserve_mem(unsigned char *addr, int old_size, int new_size)
+{
+#ifdef TELE_CCCI_SUPPORT
+ keep_md_image_retrieve_memory( ((unsigned long)addr) + new_size, old_size - new_size);
+ return 0;
+#else
+ return mblock_resize(&g_boot_arg->mblock_info, &g_boot_arg->orig_dram_info, (u64)(unsigned long)addr,
+ (u64)old_size, (u64)new_size);
+#endif
+}
+
+/* This function will export to platform code to use */
+static void *ccci_request_mem_v0(unsigned int mem_size, unsigned long long limit, unsigned long align)
+{
+#ifdef TELE_CCCI_SUPPORT
+ return NULL;
+#else
+ void *resv_addr;
+#if defined(MBLOCK_EXPAND) && defined(MBLOCK_LIB_SUPPORT) && (MBLOCK_EXPAND(MBLOCK_LIB_SUPPORT) == MBLOCK_EXPAND(2))
+ resv_addr = (void *)((unsigned long)mblock_reserve_ext(&g_boot_arg->mblock_info, mem_size, align, limit, 0, "ccci"));
+#else
+ resv_addr = (void *)((unsigned long)mblock_reserve(&g_boot_arg->mblock_info, mem_size, align, limit, RANKMAX));
+#endif
+ ALWAYS_LOG("request size: 0x%08x, get start address: %p\n", mem_size, resv_addr);
+ return resv_addr;
+#endif
+}
+
+#if defined(MBLOCK_EXPAND)
+#if defined(MBLOCK_LIB_SUPPORT) && (MBLOCK_EXPAND(MBLOCK_LIB_SUPPORT) == MBLOCK_EXPAND(2))
+static void *ccci_request_memext(unsigned int mem_size, unsigned long long limit, unsigned long align)
+{
+ void *resv_addr;
+ resv_addr = (void *)((unsigned long)mblock_reserve_ext(&g_boot_arg->mblock_info, mem_size, align, limit, 1, "ccci"));
+ ALWAYS_LOG("request size: 0x%08x, get start address: %p\n", mem_size, resv_addr);
+ return resv_addr;
+}
+#endif
+#endif
+
+void *ccci_request_mem(unsigned int mem_size, unsigned long long limit, unsigned long align)
+{
+ return ccci_request_mem_v0(mem_size, limit, align);
+}
+
+void *ccci_request_resv_memory(unsigned int mem_size, unsigned long long limit, unsigned long align)
+{
+#ifdef TELE_CCCI_SUPPORT
+ return NULL;
+#else
+ if (free_in_kernel)
+ return ccci_request_memext(mem_size, limit, align);
+ return ccci_request_mem_v0(mem_size, limit, align);
+#endif
+}
+
+void *ccci_request_named_mem(const char *name, unsigned int mem_size, unsigned long long limit, unsigned long align)
+{
+#ifdef TELE_CCCI_SUPPORT
+ if (strcmp(name, "ccci_tag_mem") == 0) {
+ ALWAYS_LOG("req_mem of ccci_tag_mem: %p\n", (void *)AP_MD_SHARE_NC);
+ return (void *)AP_MD_SHARE_NC;
+ } else if (strcmp(name, "md_smem_ncache") == 0) {
+ ALWAYS_LOG("req_mem of md_smem_ncache: %p\n", (void *)AP_MD_SHARE_NC);
+ return (void *)AP_MD_SHARE_NC;
+ } else if (strcmp(name, "md_smem_cache") == 0) {
+ ALWAYS_LOG("req_mem of md_smem_cache: %p\n", (void *)AP_MD_SHARE_C);
+ return (void *)AP_MD_SHARE_C;
+ } else if (strcmp(name, "md1rom") == 0) {
+ ALWAYS_LOG("req_mem of md1rom: %p\n", (void *)MD_ADDR);
+ return (void *)MD_ADDR;
+ } else {
+ ALWAYS_LOG("req_mem of mem: NULL\n");
+ return NULL;
+ }
+#else
+ void *resv_addr;
+
+ if (free_in_kernel) {
+ resv_addr = (void *)((unsigned long)mblock_reserve_ext(&g_boot_arg->mblock_info, mem_size, align, limit, 1, name));
+ ALWAYS_LOG("name[%s] request size: 0x%08x, get start address: %p\n", name, mem_size, resv_addr);
+ return resv_addr;
+ }
+ return ccci_request_mem_v0(mem_size, limit, align);
+#endif
+}
+
+//#define TAG_MAX_LK_INFO_SIZE (0x10000)
+#define TAG_MEM_ALIGNMENT (0x1000L)
+#define TAG_MEM_LIMIT (0xC0000000LL)
+
+__WEAK int get_mem_limit_and_align(const char name[], unsigned long long *limit,
+ unsigned long *align)
+{
+
+ long long plat_query_ret;
+
+ ALWAYS_LOG("get limit and align weak func\r\n");
+
+ if (strcmp(name, "ccci_tag_mem") == 0) {
+ *limit = TAG_MEM_LIMIT;
+ *align = TAG_MEM_ALIGNMENT;
+ return 0;
+ } else if ((strcmp(name, "md1rom") == 0) || (strcmp(name, "md3rom") == 0)) {
+
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("ro_rw_mem_limit");
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("ro rw mem limit abnormal:%d\n", (int)plat_query_ret);
+ //err_code = -LD_ERR_PT_ALLOC_RORW_MEM_FAIL;
+ return -1;
+ }
+ *limit = (unsigned long long)plat_query_ret;
+
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("ro_rw_mem_align");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("align abnormal for ro rw:%d\n", (int)plat_query_ret);
+ //err_code = -LD_ERR_PT_ALIGN_SETTING_ABNORMAL;
+ //update_md_err_to_lk_info(MD_SYS1, err_code);
+ return -1;
+ }
+ *align = (unsigned long)plat_query_ret;
+
+ } else if ((strcmp(name, "md_smem_cache") == 0) || (strcmp(name, "md_smem_ncache") == 0)) {
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("share_mem_limit");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("limit abnormal:%d\n", (int)plat_query_ret);
+ //err_code = -LD_ERR_PT_LIMIT_SETTING_ABNORMAL;
+ return -1;
+ }
+ *limit = (unsigned long long)plat_query_ret;
+
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("share_mem_align");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("align abnormal:%d\n", (int)plat_query_ret);
+ //err_code = -LD_ERR_PT_ALIGN_SETTING_ABNORMAL;
+ return -1;
+ }
+ *align = (unsigned long)plat_query_ret;
+ }
+ return 0;
+}
+
+void *resv_named_memory(const char name[], unsigned int size)
+{
+#ifdef TELE_CCCI_SUPPORT
+ unsigned long long limit = 0;
+ unsigned long align = 0;
+#else
+ unsigned long long limit;
+ unsigned long align;
+
+ if(get_mem_limit_and_align(name, &limit, &align) < 0) {
+ ALWAYS_LOG("get limit and align fail for %s\r\n", name);
+ return NULL;
+ }
+#endif
+ return ccci_request_named_mem(name, size, limit, align);
+}
+
+
+int ccci_retrieve_mem(unsigned char *addr, int size)
+{
+ ALWAYS_LOG(" 0x%xB retrieved by AP\n", (int)size);
+ log_retrieve_info(addr, size);
+#ifndef TELE_CCCI_SUPPORT
+#if defined(MBLOCK_EXPAND)
+#if defined(MBLOCK_LIB_SUPPORT) && (MBLOCK_EXPAND(MBLOCK_LIB_SUPPORT) == MBLOCK_EXPAND(2))
+ /*don't retrieve in lk, leave it to kernel.*/
+#else
+ return mblock_create(&g_boot_arg->mblock_info, &g_boot_arg->orig_dram_info, (u64)(unsigned long)addr,(u64)size);
+#endif
+#else
+ return mblock_create(&g_boot_arg->mblock_info, &g_boot_arg->orig_dram_info, (u64)(unsigned long)addr,(u64)size);
+#endif
+#endif
+ return 0;
+}
+
+
+int ccci_free_not_used_reserved_memory(unsigned char *md_start_addr, int reserved, int required)
+{
+ ALWAYS_LOG("md memory require:0x%x, reserved:0x%x\n", required, reserved);
+
+ /* Resize if acutal memory less then reserved*/
+ if (required == 0) {
+ ALWAYS_LOG("using default reserved\n");
+ return reserved;
+ } else if (required < reserved) {
+ /* Resize reserved memory */
+ if (free_in_kernel)
+ ccci_retrieve_mem((unsigned char*)(md_start_addr + required), reserved - required);
+ else
+ ccci_resize_reserve_mem(md_start_addr, reserved, required);
+ }
+ return required;
+}
+
+
+
+/***************************************************************************************************
+** Sub section:
+** Load raw data from partition, support function
+***************************************************************************************************/
+#ifdef MTK_AB_OTA_UPDATER
+static char *ab_suffix;
+#endif
+#ifdef TELE_CCCI_SUPPORT
+int ccci_load_raw_data(const char *part_name, unsigned char *mem_addr, unsigned int offset, int size)
+{
+ bdev_t *bdev;
+ struct fdt_header fdt;
+ int fdt_len;
+ int len;
+
+ LD_DBG_LOG("ccci_load_raw_data, name[%s], mem_addr[%p], offset[%x], size[%x]\n",
+ part_name, mem_addr, offset, size);
+ arch_clean_invalidate_cache_range((addr_t)mem_addr, size);
+ bdev = bio_open_by_label(part_name);
+ if (!bdev) {
+ ALWAYS_LOG("partition %s not exists\n", part_name);
+ return -LD_ERR_PT_NOT_FOUND;//return -ENODEV;
+ }
+
+#ifdef MTK_SECURITY_SW_SUPPORT //remove fdt header
+ fdt_len = sizeof(struct fdt_header);
+ offset = offset + fdt_len;
+#endif
+
+ LD_DBG_LOG(" > to 0x%llx (at dram), size:0x%x\n",(u64)((unsigned long)mem_addr), size);
+ len = bio_read(bdev, mem_addr, offset, size);
+ if (len < 0) {
+ ALWAYS_LOG("[%s] %s boot image header read error. LINE: %d\n", MODULE_NAME, part_name, __LINE__);
+ return -LD_ERR_PT_READ_RAW_FAIL;
+ }
+
+ bio_close(bdev);
+ arch_clean_invalidate_cache_range((addr_t)mem_addr, size);
+ LD_DBG_LOG("ccci_load_raw_data clen cache done\n");
+
+ return len;
+}
+#else
+int ccci_load_raw_data(char *part_name, unsigned char *mem_addr, unsigned int offset, int size)
+{
+ int len;
+#if defined(MTK_EMMC_SUPPORT) || defined(MTK_UFS_SUPPORT)
+ u64 __attribute__((unused))storage_start_addr;
+#else
+ unsigned long __attribute__((unused))storage_start_addr;
+#endif
+#ifdef MTK_AB_OTA_UPDATER
+ char partition_name[32];
+#endif
+
+ LD_DBG_LOG("ccci_load_raw_data, name[%s], mem_addr[%p], offset[%x], size[%x]\n",
+ part_name, mem_addr, offset, size);
+
+ if (partition_exists(part_name) != PART_OK) {
+ ALWAYS_LOG("partition %s not exists\n", part_name);
+ return -LD_ERR_PT_NOT_FOUND;
+ }
+
+ storage_start_addr = partition_get_offset_by_name(part_name);
+ LD_DBG_LOG("image[%s](%d) addr is 0x%llx in partition\n", part_name, offset, (u64)storage_start_addr);
+ LD_DBG_LOG(" > to 0x%llx (at dram), size:0x%x\n",(u64)((unsigned long)mem_addr), size);
+
+ len = partition_read(part_name, offset, mem_addr, size);
+ if (len < 0) {
+ ALWAYS_LOG("[%s] %s boot image header read error. LINE: %d\n", MODULE_NAME, part_name, __LINE__);
+ return -LD_ERR_PT_READ_RAW_FAIL;
+ }
+
+ return len;
+}
+#endif
+
+void ccci_ld_md_wrapper_api_init(void)
+{
+ free_in_kernel = 0;
+#if defined(MBLOCK_EXPAND)
+#if defined(MBLOCK_LIB_SUPPORT) && (MBLOCK_EXPAND(MBLOCK_LIB_SUPPORT) == MBLOCK_EXPAND(2))
+ free_in_kernel = 1;
+ ALWAYS_LOG("free_in_kernel = %d\n", free_in_kernel);
+#endif
+#endif
+
+#ifdef MTK_AB_OTA_UPDATER
+ /* get partition "_a"/"_b" suffix */
+ ab_suffix = get_suffix();
+#endif
+}
+
+
+/* This function should be called after ccci_tag_info function ready */
+void ccci_ld_md_add_wrapper_api_info(void)
+{
+#if defined(MBLOCK_EXPAND)
+#if defined(MBLOCK_LIB_SUPPORT) && (MBLOCK_EXPAND(MBLOCK_LIB_SUPPORT) == MBLOCK_EXPAND(2))
+ if (insert_ccci_tag_inf("free_in_kernel", (char*)&free_in_kernel, sizeof(unsigned int)) < 0)
+ ALWAYS_LOG("insert free_in_kernel fail\n");
+#endif
+#endif
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_ass.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_ass.c
new file mode 100644
index 0000000..6255afb
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_ass.c
@@ -0,0 +1,852 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#endif
+#define MODULE_NAME "LK_LD_MD"
+
+/*==============================================================================*/
+/* region |idx | bits | AP | MD1 | MDHW */
+/* md1_rom(dsp_rom)| 0 | 3:0 | f | f | f */
+/* md1_mcurw_hwro | 1 | 7:4 | f | f | f */
+/* md1_mcuro_hwrw | 2 |11:8 | f | f | f */
+/* md1_mcurw_hwrw | 3 |15:12 | f | f | f */
+/* md1_rw | 4 |19:16 | f | f | f */
+static void parse_mem_layout_attr_v5_hdr(struct md_check_header_v5 *hdr, struct image_section_desc tbl[])
+{
+ unsigned int i, j;
+ unsigned int region_attr_merged, shift_num, tmp;
+
+ for (i = 0; i < 8; i++) {
+ region_attr_merged = 0;
+ for (j = 0; j < 4; j++) {
+ shift_num = i<<2;/* equal *4 */
+ tmp = (hdr->domain_attr[j]&(0x0000000F<<shift_num))>>shift_num;
+ region_attr_merged |= (tmp<<(j*4));
+ }
+
+ tbl[i].mpu_attr = region_attr_merged;
+ tbl[i].offset = hdr->region_info[i].region_offset;
+ tbl[i].size = hdr->region_info[i].region_size;
+ tbl[i].relate_idx = 0;
+ tbl[i].ext_flag = 0;
+ }
+
+ /* Mark for end */
+ tbl[i].offset = 0;
+ tbl[i].size = 0;
+}
+
+static void parse_mem_layout_attr_v6_hdr(struct md_check_header_v6 *hdr, struct image_section_desc tbl[])
+{
+ unsigned int i, j;
+ unsigned int region_attr_merged, shift_num, tmp;
+
+ for (i = 0; i < 8; i++) {
+ region_attr_merged = 0;
+ for (j = 0; j < 4; j++) {
+ shift_num = i<<2;/* equal *4 */
+ tmp = (hdr->domain_attr[j]&(0x0000000F<<shift_num))>>shift_num;
+ region_attr_merged |= (tmp<<(j*4));
+ }
+
+ tbl[i].mpu_attr = region_attr_merged;
+ tbl[i].offset = hdr->region_info[i].region_offset;
+ tbl[i].size = hdr->region_info[i].region_size;
+ tbl[i].relate_idx = 0;
+ tbl[i].ext_flag = 0;
+ }
+
+ /* Mark for end */
+ tbl[i].offset = 0;
+ tbl[i].size = 0;
+}
+
+static void *ccci_get_md_header(void *tail_addr, int *header_ver)
+{
+ int size;
+ void *header_addr = NULL;
+ LD_DBG_LOG("ccci_get_md_header tail_addr[%p]\n", tail_addr);
+ if (!tail_addr)
+ return NULL;
+
+ size = *((unsigned int *)(tail_addr - 4));
+ LD_DBG_LOG("ccci_get_md_header check headr v1(%d), v3(%d), v5(%d), v6(%d) curr(%d)\n",
+ (int)sizeof(struct md_check_header_v1), (int)sizeof(struct md_check_header_v3),
+ (int)sizeof(struct md_check_header_v5), (int)sizeof(struct md_check_header_v6), size);
+
+ if (size == sizeof(struct md_check_header_v1)) {
+ header_addr = tail_addr - sizeof(struct md_check_header_v1);
+ if (header_ver)
+ *header_ver = 1;
+ } else if (size == sizeof(struct md_check_header_v3)) {
+ header_addr = tail_addr - sizeof(struct md_check_header_v3);
+ if (header_ver)
+ *header_ver = 3;
+ } else if (size == sizeof(struct md_check_header_v5)) {
+ header_addr = tail_addr - sizeof(struct md_check_header_v5);
+ if (header_ver)
+ *header_ver = 5;
+ } else if (size == sizeof(struct md_check_header_v6)) {
+ header_addr = tail_addr - sizeof(struct md_check_header_v6);
+ if (header_ver)
+ *header_ver = 6;
+ }
+
+ return header_addr;
+}
+
+static int ccci_get_max_chk_hdr_size(void)
+{
+ int max = (int)sizeof(struct md_check_header_v5);
+ int size = (int)sizeof(struct md_check_header_v4);
+
+ if (max < size)
+ max = size;
+ size = (int)sizeof(struct md_check_header_v3);
+ if (max < size)
+ max = size;
+ size = (int)sizeof(struct md_check_header_v1);
+ if (max < size)
+ max = size;
+ size = (int)sizeof(struct md_check_header_v6);
+ if (max < size)
+ max = size;
+
+ return max;
+}
+
+static int get_chk_hdr_size_by_ver(int ver)
+{
+ switch (ver) {
+ case 5:
+ return (int)sizeof(struct md_check_header_v5);
+ case 6:
+ return (int)sizeof(struct md_check_header_v6);
+ case 1:
+ return (int)sizeof(struct md_check_header_v1);
+ case 4:
+ return (int)sizeof(struct md_check_header_v4);
+ case 3:
+ return (int)sizeof(struct md_check_header_v3);
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int ccci_md_header_dump(void *header_addr, int ver)
+{
+#ifdef LD_IMG_DUMP_LOG_EN
+ //int size;
+ struct md_check_header_v1 *v1_hdr;
+ struct md_check_header_v3 *v3_hdr;
+ struct md_check_header_v5 *v5_hdr;
+ struct md_check_header_v6 *v6_hdr;
+ int i;
+ if (!header_addr)
+ return -LD_ERR_NULL_PTR;
+
+ switch (ver) {
+ case 1:
+ /* parsing md check header */
+ v1_hdr = (struct md_check_header_v1 *)header_addr;
+ LD_DBG_LOG("===== Dump v1 md header =====\n");
+ LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v1_hdr->common.check_header);
+ LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v1_hdr->common.header_verno);
+ LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v1_hdr->common.product_ver);
+ LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v1_hdr->common.image_type);
+ LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v1_hdr->common.mem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v1_hdr->common.md_img_size);
+ LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v1_hdr->ap_md_smem_size);
+ LD_DBG_LOG("=============================\n");
+ break;
+ case 3: /* V3 */
+ case 4:
+ /* parsing md check header */
+ v3_hdr = (struct md_check_header_v3 *)header_addr;
+ LD_DBG_LOG("===== Dump v3 md header =====\n");
+ LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v3_hdr->common.check_header);
+ LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v3_hdr->common.header_verno);
+ LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v3_hdr->common.product_ver);
+ LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v3_hdr->common.image_type);
+ LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v3_hdr->common.mem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v3_hdr->common.md_img_size);
+ LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v3_hdr->dsp_img_offset);
+ LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v3_hdr->dsp_img_size);
+ LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v3_hdr->rpc_sec_mem_addr);
+ LD_DBG_LOG("=============================\n");
+ break;
+ case 5:
+ /* parsing md check header */
+ v5_hdr = (struct md_check_header_v5 *)header_addr;
+ LD_DBG_LOG("===== Dump v5 md header =====\n");
+ LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v5_hdr->common.check_header);
+ LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v5_hdr->common.header_verno);
+ LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v5_hdr->common.product_ver);
+ LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v5_hdr->common.image_type);
+ LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v5_hdr->common.mem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v5_hdr->common.md_img_size);
+ LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v5_hdr->dsp_img_offset);
+ LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v5_hdr->dsp_img_size);
+ LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v5_hdr->rpc_sec_mem_addr);
+ LD_DBG_LOG("[%s] MD IMG - armv7 offset : 0x%08X\n", MODULE_NAME, v5_hdr->arm7_img_offset);
+ LD_DBG_LOG("[%s] MD IMG - armv7 size : 0x%08X\n", MODULE_NAME, v5_hdr->arm7_img_size);
+ LD_DBG_LOG("[%s] MD IMG - region num : 0x%08X\n", MODULE_NAME, v5_hdr->region_num);
+ LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v5_hdr->ap_md_smem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_md_smem_size: 0x%08X\n", MODULE_NAME, v5_hdr->md_to_md_smem_size);
+ for (i = 0; i < 8; i++) {
+ LD_DBG_LOG("[%s] MD IMG - region[%d] off : 0x%08X\n", MODULE_NAME, i,
+ v5_hdr->region_info[i].region_offset);
+ LD_DBG_LOG("[%s] MD IMG - region[%d] size: 0x%08X\n", MODULE_NAME, i,
+ v5_hdr->region_info[i].region_size);
+ }
+ for (i = 0; i < 4; i++) {
+ LD_DBG_LOG("[%s] MD IMG - domain_attr[%d] : 0x%08X\n", MODULE_NAME, i,
+ v5_hdr->domain_attr[i]);
+ }
+ for (i = 0; i < MAX_PADDING_NUM_V5_HDR; i++) {
+ LD_DBG_LOG("[%s] MD IMG - padding info[%d] offset: 0x%08X\n", MODULE_NAME, i,
+ v5_hdr->padding_blk[i].start_offset);
+ LD_DBG_LOG("[%s] MD IMG - padding info[%d] size: 0x%08X\n", MODULE_NAME, i,
+ v5_hdr->padding_blk[i].length);
+ }
+ LD_DBG_LOG("=============================\n");
+ break;
+ case 6:
+ /* parsing md check header */
+ v6_hdr = (struct md_check_header_v6 *)header_addr;
+ LD_DBG_LOG("===== Dump v6 md header =====\n");
+ LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v6_hdr->common.check_header);
+ LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v6_hdr->common.header_verno);
+ LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v6_hdr->common.product_ver);
+ LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v6_hdr->common.image_type);
+ LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v6_hdr->common.mem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v6_hdr->common.md_img_size);
+ LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v6_hdr->dsp_img_offset);
+ LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v6_hdr->dsp_img_size);
+ LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v6_hdr->rpc_sec_mem_addr);
+ LD_DBG_LOG("[%s] MD IMG - armv7 offset : 0x%08X\n", MODULE_NAME, v6_hdr->arm7_img_offset);
+ LD_DBG_LOG("[%s] MD IMG - armv7 size : 0x%08X\n", MODULE_NAME, v6_hdr->arm7_img_size);
+ LD_DBG_LOG("[%s] MD IMG - region num : 0x%08X\n", MODULE_NAME, v6_hdr->region_num);
+ LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v6_hdr->ap_md_smem_size);
+ LD_DBG_LOG("[%s] MD IMG - md_md_smem_size: 0x%08X\n", MODULE_NAME, v6_hdr->md_to_md_smem_size);
+ for (i = 0; i < 8; i++) {
+ LD_DBG_LOG("[%s] MD IMG - region[%d] off : 0x%08X\n", MODULE_NAME, i,
+ v6_hdr->region_info[i].region_offset);
+ LD_DBG_LOG("[%s] MD IMG - region[%d] size: 0x%08X\n", MODULE_NAME, i,
+ v6_hdr->region_info[i].region_size);
+ }
+ for (i = 0; i < 4; i++) {
+ LD_DBG_LOG("[%s] MD IMG - domain_attr[%d] : 0x%08X\n", MODULE_NAME, i,
+ v6_hdr->domain_attr[i]);
+ }
+ for (i = 0; i < MAX_PADDING_NUM_V6_HDR; i++) {
+ LD_DBG_LOG("[%s] MD IMG - padding info[%d] offset: 0x%08X\n", MODULE_NAME, i,
+ v6_hdr->padding_blk[i].start_offset);
+ LD_DBG_LOG("[%s] MD IMG - padding info[%d] size: 0x%08X\n", MODULE_NAME, i,
+ v6_hdr->padding_blk[i].length);
+ }
+ LD_DBG_LOG("[%s] MD IMG - drdi offset : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_offset);
+ LD_DBG_LOG("[%s] MD IMG - drdi size : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_size);
+ LD_DBG_LOG("[%s] Runtime - drdi rt offset : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_rt_offset);
+ LD_DBG_LOG("[%s] Runtime - drdi rt size : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_rt_size);
+ LD_DBG_LOG("=============================\n");
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+}
+
+int verify_main_img_check_header(modem_info_t *info)
+{
+ struct md_check_header_comm *common_hdr;
+ int md_hdr_ver;
+ char md_str[16];
+ int ret;
+
+ /* Parse check header */
+ common_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, &md_hdr_ver);
+
+ if (common_hdr == NULL) {
+ ALWAYS_LOG("parse check header fail\n");
+ ret = -LD_ERR_GET_COM_CHK_HDR_FAIL;
+ goto _Hdr_Verity_Exit;
+ }
+
+ if (strncmp((char const *)common_hdr->check_header, "CHECK_HEADER", 12)) {
+ ALWAYS_LOG("invald md check header str[%s]\n", common_hdr->check_header);
+ ret = -LD_ERR_CHK_HDR_PATTERN;
+ goto _Hdr_Verity_Exit;
+ }
+
+ /* Dump header info */
+ ccci_md_header_dump(common_hdr, md_hdr_ver);
+
+ /* Post to platform */
+ ccci_hal_post_hdr_info((void*)common_hdr, md_hdr_ver, (int)info->md_id);
+
+ if (info->resv_mem_size < common_hdr->mem_size) {
+ ALWAYS_LOG("Reserved memory not enough, resv:%d, require:%d\n",
+ (int)info->resv_mem_size, (int)common_hdr->mem_size);
+ ret = -LD_ERR_RESERVE_MEM_NOT_ENOUGH;
+ goto _Hdr_Verity_Exit;
+ }
+
+ info->resv_mem_size = common_hdr->mem_size;
+ info->ro_rw_size = common_hdr->md_img_size;
+ info->md_type = common_hdr->image_type;
+
+ if (info->md_id < MD1_DSP) {
+ /* Inssert image size and check header info to arguments array for kernel */
+ snprintf(md_str, 16, "md%dimg", info->md_id + 1);
+ if (insert_ccci_tag_inf(md_str, (char*)&info->ro_rw_size, sizeof(unsigned int)) < 0)
+ ALWAYS_LOG("insert %s fail\n", md_str);
+
+ /* Inssert image size and check header info to arguments array for kernel */
+ snprintf(md_str, 16, "md%d_chk", info->md_id + 1);
+ if (insert_ccci_tag_inf(md_str, (char*)common_hdr, get_chk_hdr_size_by_ver(md_hdr_ver)) < 0)
+ ALWAYS_LOG("insert %s fail\n", md_str);
+ }
+ ccci_update_md_version(info->md_id, common_hdr->build_ver);
+
+ return 0;
+
+_Hdr_Verity_Exit:
+ return ret;
+}
+
+/***************************************************************************************************
+****************************************************************************************************
+** Sub section:
+** Download image list part: normal load and dummy AP
+** MD1 default using v5 header; MD3 default using v1 header
+****************************************************************************************************
+***************************************************************************************************/
+static download_info_t *find_ptr_at_img_list(download_info_t img_list[], int img_type)
+{
+ download_info_t *curr = img_list;
+ while (curr->img_type != 0) {
+ if (curr->img_type == img_type)
+ return curr;
+ curr++;
+ }
+ return NULL;
+}
+/* --- Assistant function for MD check header v5 --- */
+int ass_func_for_v5_normal_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ download_info_t *ld_list = (download_info_t *)data;
+ struct md_check_header_v5 *chk_hdr;
+ download_info_t *curr;
+ unsigned char *md_resv_mem_addr = NULL;
+ struct image_section_desc *tbl;
+ int mpu_num_for_padding;
+ int ret;
+
+ /* region: 8; padding:3; mark for end:1 total: 12(=8+3+1) */
+ tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*12);
+ if (tbl == NULL)
+ return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _free_alloc_mem;
+ }
+
+ /* Get md main image addr at memory */
+ curr = find_ptr_at_img_list(ld_list, main_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
+ goto _free_alloc_mem;
+ } else
+ md_resv_mem_addr = curr->mem_addr;
+
+ /* Get dsp image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, dsp_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
+ goto _free_alloc_mem;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
+ curr->img_size = chk_hdr->dsp_img_size;
+ }
+
+ /* Get armv7 image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, armv7_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
+ goto _free_alloc_mem;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset;
+ curr->img_size = chk_hdr->arm7_img_size;
+ }
+
+ parse_mem_layout_attr_v5_hdr(chk_hdr, tbl);
+ mpu_num_for_padding = ccci_hal_get_mpu_num_for_padding_mem();
+ if (mpu_num_for_padding >= 1)
+ retrieve_free_padding_mem_v5_hdr((modem_info_t *)load_info, tbl, chk_hdr, mpu_num_for_padding);
+
+ ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
+ if (ret < 0)
+ goto _free_alloc_mem;
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_free_alloc_mem:
+ if (tbl)
+ free(tbl);
+
+ return ret;
+}
+
+int ass_func_for_v6_normal_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ download_info_t *ld_list = (download_info_t *)data;
+ struct md_check_header_v6 *chk_hdr;
+ download_info_t *curr;
+ unsigned char *md_resv_mem_addr = NULL;
+ struct image_section_desc *tbl;
+ int mpu_num_for_padding;
+ int i, ret;
+
+ /* region: 8; padding:8; mark for end:1 total: 17(=8+8+1) */
+ tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*17);
+ if (tbl == NULL)
+ return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
+
+ for (i = 0; i < 17; i++)
+ tbl[i].ext_flag = 0;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _free_alloc_mem;
+ }
+
+ /* Get md main image addr at memory */
+ curr = find_ptr_at_img_list(ld_list, main_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
+ goto _free_alloc_mem;
+ } else
+ md_resv_mem_addr = curr->mem_addr;
+
+ /* Get dsp image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, dsp_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
+ goto _free_alloc_mem;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
+ if (curr->ass_func)
+ curr->img_size = DSP_IMG_MAX_SIZE; /* it will be overwriten after loading */
+ else
+ curr->img_size = chk_hdr->dsp_img_size;
+ }
+
+ /* Get armv7 image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, armv7_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
+ goto _free_alloc_mem;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset;
+ curr->img_size = chk_hdr->arm7_img_size;
+ }
+
+ /* Get drdi image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, drdi_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_DRDI_INF_FAIL;
+ goto _free_alloc_mem;
+ } else {
+ /* Note here, just for MD R3 BM script compatible workaround,
+ for final solution, rt_xxx check should be removed */
+ if ((chk_hdr->drdi_rt_offset != 0) && (chk_hdr->drdi_rt_size != 0)) {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->drdi_offset;
+ curr->img_size = chk_hdr->drdi_size;
+ }
+ }
+
+ parse_mem_layout_attr_v6_hdr(chk_hdr, tbl);
+ mpu_num_for_padding = ccci_hal_get_mpu_num_for_padding_mem();
+ if (mpu_num_for_padding >= 1)
+ retrieve_free_padding_mem_v6_hdr((modem_info_t *)load_info, tbl, chk_hdr, mpu_num_for_padding);
+
+ ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
+ if (ret < 0)
+ goto _free_alloc_mem;
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_free_alloc_mem:
+ if (tbl)
+ free(tbl);
+
+ return ret;
+}
+
+int ass_func_for_v1_normal_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ struct md_check_header_v1 *chk_hdr;
+ struct image_section_desc *tbl;
+ int ret;
+
+ /* region: 2; mark for end:1 total: 3(=2+1) */
+ tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*3);
+ if (tbl == NULL)
+ return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _free_alloc_mem;
+ }
+
+ /* Configure mpu info */
+ /* RO part */
+ tbl[0].mpu_attr = 0xFFFFFFFF;
+ tbl[0].offset = 0;
+ tbl[0].size = chk_hdr->common.md_img_size;
+ tbl[0].relate_idx = 0;
+ tbl[0].ext_flag = 0;
+ /* RW part */
+ tbl[1].mpu_attr = 0xFFFFFFFF;
+ tbl[1].offset = tbl[0].offset + tbl[0].size;
+ tbl[1].size = chk_hdr->common.mem_size - chk_hdr->common.md_img_size;
+ tbl[1].relate_idx = 0;
+ tbl[1].ext_flag = 0;
+ /* Mark for end */
+ tbl[2].mpu_attr = 0xFFFFFFFF;
+ tbl[2].offset = 0;
+ tbl[2].size = 0;
+ tbl[2].relate_idx = 0;
+ tbl[2].ext_flag = 0;
+
+ ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
+ if (ret < 0)
+ goto _free_alloc_mem;
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_free_alloc_mem:
+ if (tbl)
+ free(tbl);
+
+ return ret;
+}
+
+int ass_func_for_v1_r8_normal_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ struct md_check_header_v1 *chk_hdr;
+ struct image_section_desc *tbl;
+ int ret;
+
+ /* region: 2; mark for end:1 total: 3(=2+1) */
+ tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*3);
+ if (tbl == NULL)
+ return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _free_alloc_mem;
+ }
+
+ /* Configure mpu info */
+ /* RO part */
+ tbl[0].mpu_attr = 0xFFFFFFFF;
+ tbl[0].offset = 0;
+ tbl[0].size = chk_hdr->common.md_img_size;
+ tbl[0].size = (tbl[0].size + 0xFFFF)&(~0xFFFF);
+ tbl[0].relate_idx = 0;
+ tbl[0].ext_flag = 0;
+ /* RW part */
+ tbl[1].mpu_attr = 0xFFFFFFFF;
+ tbl[1].offset = tbl[0].offset + tbl[0].size;
+ tbl[1].size = chk_hdr->common.mem_size - tbl[0].size;
+ tbl[1].relate_idx = 0;
+ tbl[1].ext_flag = 0;
+ /* Mark for end */
+ tbl[2].mpu_attr = 0xFFFFFFFF;
+ tbl[2].offset = 0;
+ tbl[2].size = 0;
+ tbl[2].relate_idx = 0;
+ tbl[2].ext_flag = 0;
+
+ ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
+ if (ret < 0)
+ goto _free_alloc_mem;
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_free_alloc_mem:
+ if (tbl)
+ free(tbl);
+
+ return ret;
+}
+
+/* --- Assistant function for DSP check header v3 --- */
+int ass_func_for_dsp_normal_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ struct md_check_header_v3 *chk_hdr;
+ struct image_section_desc *tbl;
+ int ret;
+
+ /* region: 8; padding:3; mark for end:1 total: 12(=8+3+1) */
+ tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*12);
+ if (tbl == NULL)
+ return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _free_alloc_mem;
+ }
+
+ /* Configure mpu info */
+ /* RO part */
+ tbl[0].mpu_attr = 0xFFFFFFFF;
+ /*dsp base addr = md base addr + DSP offset, so RO offset should be 0*/
+ tbl[0].offset = 0;
+ tbl[0].size = chk_hdr->common.md_img_size; /*DSP RO size = dsp img + padding*/
+ /*64K align*/
+ tbl[0].size = ((tbl[0].size + 0xFFFF)&(~0xFFFF));
+ tbl[0].relate_idx = 0;
+ tbl[0].ext_flag = 0;
+
+ /* RW part */
+ tbl[1].mpu_attr = 0xFFFFFFFF;
+ tbl[1].offset = tbl[0].offset + tbl[0].size;
+ tbl[1].size = chk_hdr->common.mem_size - tbl[0].size;
+ tbl[1].relate_idx = 0;
+ tbl[1].ext_flag = 0;
+
+ /* Mark for end */
+ tbl[3].mpu_attr = 0xFFFFFFFF;
+ tbl[3].offset = 0;
+ tbl[3].size = 0;
+ tbl[3].relate_idx = 0;
+ tbl[3].ext_flag = 0;
+
+ ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
+ if (ret < 0)
+ goto _free_alloc_mem;
+
+_free_alloc_mem:
+ if (tbl)
+ free(tbl);
+
+ return ret;
+}
+
+int ass_func_for_v5_md_only_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ download_info_t *ld_list = (download_info_t *)data;
+ struct md_check_header_v5 *chk_hdr;
+ download_info_t *curr;
+ unsigned char *md_resv_mem_addr = NULL;
+ int ret;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _exit;
+ }
+
+ /* Get md main image(MD only/HVT) addr at memory */
+ curr = find_ptr_at_img_list(ld_list, main_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
+ goto _exit;
+ } else
+ md_resv_mem_addr = curr->mem_addr;
+
+ /* Get dsp image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, dsp_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
+ curr->img_size = chk_hdr->dsp_img_size;
+ }
+
+ /* Get armv7 image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, armv7_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset; /* using arm7 section as ramdisk */
+ curr->img_size = chk_hdr->arm7_img_size;
+ }
+
+ /* Get ramdisk image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, ramdisk_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_RAMDISK_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->ramdisk_offset;
+ curr->img_size = chk_hdr->ramdisk_size;
+ }
+
+ /* Get l1_core image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, l1_core_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_L1CORE_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->region_info[7].region_offset; /* using padding[1] section as l1core */
+ curr->img_size = chk_hdr->region_info[7].region_size;
+ }
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_exit:
+ return ret;
+}
+
+int ass_func_for_v6_md_only_img(void *load_info, void *data)
+{
+ modem_info_t *info = (modem_info_t *)load_info;
+ download_info_t *ld_list = (download_info_t *)data;
+ struct md_check_header_v6 *chk_hdr;
+ download_info_t *curr;
+ unsigned char *md_resv_mem_addr = NULL;
+ int ret;
+
+ /* find start addr for check header */
+ chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
+ if (chk_hdr == NULL) {
+ ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
+ goto _exit;
+ }
+
+ /* Get md main image(MD only/HVT) addr at memory */
+ curr = find_ptr_at_img_list(ld_list, main_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
+ goto _exit;
+ } else
+ md_resv_mem_addr = curr->mem_addr;
+
+ /* Get dsp image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, dsp_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
+ curr->img_size = chk_hdr->dsp_img_size;
+ }
+
+ /* Get armv7 image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, armv7_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset; /* using arm7 section as ramdisk */
+ curr->img_size = chk_hdr->arm7_img_size;
+ }
+
+ /* Get ramdisk image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, ramdisk_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_RAMDISK_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->ramdisk_offset;
+ curr->img_size = chk_hdr->ramdisk_size;
+ }
+
+ /* Get l1_core image addr at memory and size */
+ curr = find_ptr_at_img_list(ld_list, l1_core_img);
+ if (curr == NULL) {
+ ret = -LD_ERR_ASS_FIND_L1CORE_INF_FAIL;
+ goto _exit;
+ } else {
+ curr->mem_addr = md_resv_mem_addr + chk_hdr->region_info[7].region_offset; /* using padding[1] section as l1core */
+ curr->img_size = chk_hdr->region_info[7].region_size;
+ }
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+_exit:
+ return ret;
+}
+
+int ass_func_for_v1_md_only_img(void *load_info, void *data)
+{
+ int ret;
+
+ ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
+
+ return ret;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.c
new file mode 100644
index 0000000..5519868
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.c
@@ -0,0 +1,931 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#include "ccci_ld_md_tel.h"
+#include "ccci_fit.h"
+
+#ifdef MBLOCK_LIB_SUPPORT
+#include <mblock.h>
+#endif
+#ifdef MTK_AB_OTA_UPDATER
+#include "bootctrl.h"
+#endif
+#include <assert.h>
+
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#include <platform.h>
+#include <platform/mkimg.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#include <platform/sec_export.h>
+#include <block_generic_interface.h>
+#include <img_info.h>
+#endif
+
+#define MODULE_NAME "LK_LD_MD"
+
+/***************************************************************************************************
+* Quick search pattern:
+* 1. Download list
+***************************************************************************************************/
+
+
+/***************************************************************************************************
+** Sub sectoin:
+** modem info
+***************************************************************************************************/
+static modem_info_t s_g_md_ld_status[MAX_MD_NUM];
+static int s_g_md_ld_record_num;
+
+static void add_hdr_info(modem_info_t tbl[], modem_info_t *hdr)
+{
+#if WITH_KERNEL_VM
+ tbl[s_g_md_ld_record_num].base_addr = kvaddr_to_paddr((void *)hdr->base_addr);
+#else
+ tbl[s_g_md_ld_record_num].base_addr = hdr->base_addr;
+#endif
+ tbl[s_g_md_ld_record_num].resv_mem_size = hdr->resv_mem_size;
+ tbl[s_g_md_ld_record_num].err_no = hdr->err_no;
+ tbl[s_g_md_ld_record_num].md_id = hdr->md_id;
+ tbl[s_g_md_ld_record_num].ver = 0;
+ tbl[s_g_md_ld_record_num].md_type = hdr->md_type;
+ tbl[s_g_md_ld_record_num].load_size = hdr->load_size;
+ tbl[s_g_md_ld_record_num].ro_rw_size = hdr->ro_rw_size;
+ s_g_md_ld_record_num++;
+}
+
+/***************************************************************************************************
+** Sub section:
+** String to unsigned int lib function, pure software code
+***************************************************************************************************/
+unsigned int str2uint(char *str)
+{
+ /* max 32bit integer is 4294967296, buf[16] is enough */
+ char buf[16];
+ int i;
+ int num;
+ int base = 10;
+ int ret_val;
+ if (NULL == str)
+ return 0;
+
+ i = 0;
+ while (i<16) {
+ /* Format it */
+ if ((str[i] == 'X') || (str[i] == 'x')) {
+ buf[i] = 'x';
+ if (i != 1)
+ return 0; /* not 0[x]XXXXXXXX */
+ else if (buf[0] != '0')
+ return 0; /* not [0]xXXXXXXXX */
+ else
+ base = 16;
+ } else if ((str[i] >= '0') && (str[i] <= '9'))
+ buf[i] = str[i];
+ else if ((str[i] >= 'a') && (str[i] <= 'f')) {
+ if (base != 16)
+ return 0;
+ buf[i] = str[i];
+ } else if ((str[i] >= 'A') && (str[i] <= 'F')) {
+ if (base != 16)
+ return 0;
+ buf[i] = str[i] - 'A' + 'a';
+ } else if (str[i] == 0) {
+ buf[i] = 0;
+ i++;
+ break;
+ } else
+ return 0;
+
+ i++;
+ }
+
+ num = i-1;
+ ret_val = 0;
+ if (base == 10) {
+ for (i=0; i<num; i++)
+ ret_val = ret_val*10 + buf[i] - '0';
+ } else if (base == 16) {
+ for (i=2; i<num; i++) {
+ if (buf[i] >= 'a')
+ ret_val = ret_val*16 + buf[i] - 'a' + 10;
+ else
+ ret_val = ret_val*16 + buf[i] - '0';
+ }
+ }
+ return ret_val;
+}
+
+static int find_offset_mdfit(void *fit)
+{
+ int load_size, hdr_offset = 0;
+ int buf_size = 512;
+ char *buf = malloc(buf_size);
+ unsigned int *tmp = NULL;
+
+ while(1)
+ {
+ load_size = (int)ccci_load_raw_data(fit, (unsigned char*)buf, hdr_offset, buf_size);
+ if ((unsigned int)load_size != buf_size) {
+ ALWAYS_LOG("load hdr fail(%d)\n", load_size);
+ return -1;
+ }
+
+ for(tmp = (unsigned int *)buf ; tmp< buf + buf_size; tmp++)
+ {
+ if (*tmp == MKIMG_MAGIC) {
+ ALWAYS_LOG("find magic\n");
+ free(buf);
+ return hdr_offset;
+ }
+ if (hdr_offset > 50000) {
+ ALWAYS_LOG("can't find magic\n");
+ free(buf);
+ return -LD_ERR_PT_P_HDR_MAGIC_MIS_MATCH;
+ }
+ hdr_offset = hdr_offset + 4;
+ }
+ }
+}
+
+static int find_hdr_in_partiton(const char *partition_name, const char *hdr_name, union mkimg_hdr *p_hdr, unsigned int p_hdr_size)
+{
+ int load_size;
+ int hdr_offset = find_offset_mdfit(partition_name);
+ ALWAYS_LOG("hdr_offset(0x%x)\n", hdr_offset);
+
+ while(1) {
+ load_size = (int)ccci_load_raw_data(partition_name, (unsigned char*)p_hdr, hdr_offset, p_hdr_size);
+ if ((unsigned int)load_size != p_hdr_size) {
+ ALWAYS_LOG("load hdr fail(%d)\n", load_size);
+ return -1;
+ }
+ if (p_hdr->info.magic != MKIMG_MAGIC) {
+ ALWAYS_LOG("invalid magic(%x):(%x)ref\n", p_hdr->info.magic, MKIMG_MAGIC);
+ return -LD_ERR_PT_P_HDR_MAGIC_MIS_MATCH;
+ }
+ if (strcmp(p_hdr->info.name, hdr_name) == 0)
+ return hdr_offset;
+
+ hdr_offset += p_hdr->info.hdr_sz;
+ hdr_offset += ((p_hdr->info.dsz + p_hdr->info.align_sz - 1) & (~(p_hdr->info.align_sz - 1)));
+ }
+}
+
+static int load_image_by_name(const char *partition_list[], const char *name,
+ unsigned char *mem_addr, unsigned int max_size, unsigned int flags)
+{
+ int i = 0;
+ int hdr_offset;
+ union mkimg_hdr *p_hdr;
+ int load_size;
+ int ret = -1;
+ int img_size_with_padding;
+ int partiton_idx = 0;
+
+ /* allocate partition header memory first */
+ p_hdr = (union mkimg_hdr *)malloc(sizeof(union mkimg_hdr));
+ if (p_hdr==NULL) {
+ ALWAYS_LOG("alloc mem for hdr fail\n");
+ return -LD_ERR_PT_ALLOC_HDR_MEM_FAIL;
+ }
+
+ while (partition_list[i] != NULL) {
+ hdr_offset = find_hdr_in_partiton(partition_list[i], name, p_hdr, sizeof(union mkimg_hdr));
+ if (hdr_offset < 0) {
+ i++;
+ continue;
+ }
+ partiton_idx = i;
+ break;
+ }
+
+ if (hdr_offset < 0) {
+ ALWAYS_LOG("load sub image %s fail\n", name);
+ ret = -LD_ERR_GET_COM_CHK_HDR_FAIL;
+ goto _Exit;
+ }
+
+ LD_DBG_LOG("dump p_hdr info\n");
+ LD_DBG_LOG(" p_hdr->info.magic:%x\n", p_hdr->info.magic);
+ LD_DBG_LOG(" p_hdr->info.dsz:%x\n", p_hdr->info.dsz);
+ LD_DBG_LOG(" p_hdr->info.name:%s\n", p_hdr->info.name);
+ LD_DBG_LOG(" p_hdr->info.mode:%x\n", p_hdr->info.mode);
+ LD_DBG_LOG(" p_hdr->info.hdr_sz:%x\n", p_hdr->info.hdr_sz);
+
+ if (p_hdr->info.dsz > max_size) {
+ ALWAYS_LOG("load sub image %s fail\n", name);
+ ret = -LD_ERR_PT_IMG_TOO_LARGE;
+ goto _Exit;
+ }
+
+ /* load image raw data */
+ load_size = (int)ccci_load_raw_data(partition_list[i], mem_addr, hdr_offset + p_hdr->info.hdr_sz,
+ p_hdr->info.dsz);
+ if ((unsigned int)load_size != p_hdr->info.dsz) {
+ ALWAYS_LOG("load sub-image data fail(%d:%d)\n", load_size, p_hdr->info.dsz);
+ ret = -LD_ERR_PT_LD_IMG_DATA_FAIL;
+ goto _Exit;
+ }
+
+ /* Calcualte size that add padding */
+ img_size_with_padding = (load_size + p_hdr->info.align_sz - 1) & (~(p_hdr->info.align_sz -1));
+ /* Clear padding data to 0 */
+ for (i = 0; i < img_size_with_padding - (int)p_hdr->info.dsz; i++)
+ mem_addr[p_hdr->info.dsz + i] = 0;
+
+ ret = load_size;
+
+_Exit:
+ free(p_hdr);
+ return ret;
+}
+
+static int load_main_image(download_info_t *main_img, unsigned long long limit, unsigned long align,
+ unsigned char **base_addr, int *resv_mem_size)
+{
+ unsigned char *md_mem_base;
+ const char *partition_list[2];
+ int ret, load_size;
+
+ /* reserve memory for modem with max requirement */
+#ifdef TELE_CCCI_SUPPORT
+ //md_mem_base = (void *)MD_ADDR;
+ md_mem_base = resv_named_memory("md1rom", main_img->max_size);
+#else
+ md_mem_base = ccci_request_resv_memory(main_img->max_size, limit, align);
+#endif
+ if (md_mem_base == NULL) {
+ ALWAYS_LOG("allocate MD memory fail\n");
+ ret = -LD_ERR_PT_ALLOC_MD_MEM_FAIL;
+ goto _Exit;
+ }
+
+ partition_list[0] = main_img->partition_name;
+ partition_list[1] = NULL;
+ load_size = load_image_by_name(partition_list, main_img->image_name, md_mem_base, main_img->max_size,
+ main_img->ext_flag);// by image name
+ if (load_size < 0) {
+ ret = load_size;
+ /* If enter this function, it means we hope modem feature should be support, we should check error */
+ /* So, release reserved memory is not neccessary */
+ goto _Exit;
+ }
+
+ if (load_size < MAIN_IMG_MIN_SIZE) { /* 32kB */
+ ALWAYS_LOG("img size abnormal,size(0x%x)\n", load_size);
+ ret = -LD_ERR_PT_MAIN_IMG_SIZE_ABNORMAL;
+ goto _Exit;
+ }
+
+ main_img->img_size = load_size;
+ *base_addr = md_mem_base;
+ *resv_mem_size = main_img->max_size;
+ main_img->mem_addr = md_mem_base;
+ main_img->img_size = load_size;
+ ret = load_size;
+
+_Exit:
+ return ret;
+}
+
+static int dsp_img_post_process(download_info_t *dsp_img, int md_id)
+{
+ modem_info_t dsp_info;
+ int ret;
+
+ /*dsp base addr = md base addr + DSP offset*/
+ dsp_info.base_addr = (unsigned long long)((unsigned long)dsp_img->mem_addr);
+ dsp_info.resv_mem_size = dsp_img->max_size;
+ dsp_info.load_size = dsp_img->img_size;
+ if (md_id == MD_SYS1)
+ dsp_info.md_id = MD1_DSP;
+ else {
+ ALWAYS_LOG("Not MD1, DSP doesn't need to check\n");
+ return 0;
+ }
+
+ if (dsp_img->ass_func) {
+ ret = verify_main_img_check_header(&dsp_info);
+ if (ret < 0)
+ ALWAYS_LOG("by pass dsp check header verify(%d)\n", ret);
+ else {
+ ret = dsp_img->ass_func((void*)&dsp_info, (void*)dsp_img);
+ if (ret < 0) {
+ ALWAYS_LOG("dsp assistan func process fail:%d\n", ret);
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+
+/* --- load raw data to DRAM that listed at table --- */
+static int ld_img_at_list(download_info_t img_list[], modem_info_t *info, unsigned long long limit, unsigned long align)
+{
+ int load_size;
+ int md_mem_resv_size = 0;
+ int md_mem_required_size = 0;
+ unsigned char *md_resv_mem_addr = NULL;
+ int ret = 0;
+ download_info_t *curr;
+ download_info_t *md_main_img;
+ const char *partition_list[3];
+
+#ifdef SINGLE_BIN_MODEM
+ ALWAYS_LOG("single bin!\n");
+#else
+ ALWAYS_LOG("not single bin!\n");
+#endif
+
+ if (img_list == NULL) {
+ ALWAYS_LOG("image list is NULL!\n");
+ return -LD_ERR_PT_IMG_LIST_NULL;
+ }
+ /* find main image at list */
+ curr = img_list;
+ while (curr->img_type != 0) {
+ if (curr->img_type == main_img)
+ break;
+ curr++;
+ }
+ if (curr->img_type != main_img)
+ return -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
+
+ md_main_img = curr;
+
+ /* alloc memory and load main image */
+ ret = load_main_image(md_main_img, limit, align, &md_resv_mem_addr, &md_mem_resv_size);
+ if (ret < 0)
+ return ret;
+ /* check header verify and sub image offset and size update */
+ info->base_addr = (unsigned long long)((unsigned long)md_resv_mem_addr);
+ info->resv_mem_size = md_mem_resv_size;
+ info->load_size = ret;
+ ret = verify_main_img_check_header(info);
+
+ if (ret < 0) {
+ ALWAYS_LOG("md check header verify fail:%d\n", ret);
+ goto _MD_Exit;
+ }
+
+ if (md_main_img->ass_func) {
+ ret = md_main_img->ass_func((void*)info, (void*)img_list);
+ if (ret < 0) {
+ ALWAYS_LOG("assistan func process fail:%d\n", ret);
+ goto _MD_Exit;
+ }
+ }
+ md_mem_required_size = info->resv_mem_size;
+
+ /* load sub image one by one */
+ curr = img_list;
+#ifdef SINGLE_BIN_MODEM
+ partition_list[0] = md_main_img->partition_name;
+#else
+ partition_list[0] = curr->partition_name;
+ /* partition_list[0] will update later */
+#endif
+ partition_list[1] = NULL;
+ partition_list[2] = NULL;
+
+ while (curr->img_type != 0) {
+ /* By pass main image */
+ if (curr->img_type == main_img) {
+ curr++;
+ continue;
+ }
+ /* By pass ext image that no need to load after query main image setting */
+ if ((curr->mem_addr == NULL) || (curr->img_size == 0)) {
+ curr++;
+ continue;
+ }
+#ifndef SINGLE_BIN_MODEM
+ partition_list[0] = curr->partition_name;
+#endif
+ load_size = load_image_by_name(partition_list, curr->image_name, curr->mem_addr,
+ curr->max_size, curr->ext_flag);
+
+ if ((load_size >= 0) && (load_size > curr->img_size)) {
+ ALWAYS_LOG("image size not sync to chk_hdr hdr:[0x%x]<>a:[0x%x]\n",
+ curr->img_size, load_size);
+ ret = -LD_ERR_PT_IMG_SIZE_NOT_SYNC_CHK_HDR;
+ goto _MD_Exit;
+ } else if (load_size < 0) {
+ ALWAYS_LOG("load sub image: %s fail with ret info: %s\n",
+ curr->image_name, ld_md_errno_to_str(load_size));
+ ret = load_size;
+ goto _MD_Exit;
+ }
+
+ if (curr->img_type == dsp_img) {
+ curr->img_size = load_size;
+ ret = dsp_img_post_process(curr, info->md_id);
+ if (ret < 0)
+ goto _MD_Exit;
+ }
+ curr++;
+ }
+
+ /* Sync cache to make sure all data flash to DRAM to avoid MPU violation */
+ arch_sync_cache_range((addr_t)md_resv_mem_addr, (size_t)md_mem_resv_size);
+
+ info->err_no = 0;
+
+ /* Retrieve not used memory if needed*/
+ if (md_mem_resv_size != md_mem_required_size)
+ ccci_free_not_used_reserved_memory(md_resv_mem_addr, md_mem_resv_size, md_mem_required_size);
+
+ return 0;
+
+_MD_Exit:
+ if (md_resv_mem_addr) {
+ ALWAYS_LOG("Free reserved memory\n");
+ ccci_free_not_used_reserved_memory(md_resv_mem_addr, md_mem_resv_size, 0);
+ }
+
+ return ret;
+}
+
+/* --- Download list --------------------------------------- */
+/* --- This part is used for normal load ------------------- */
+#ifdef TELE_REDUCE_CODE//MAX_MD_SIZE
+static download_info_t md1_download_list_v20000[] = {/* for 92, 93 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr | ass func p */
+ {main_img, MD_PART_NAME, "md1rom", MAX_MD_SIZE, 0, 0, NULL, ass_func_for_v6_normal_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x2000000, 0, 0, NULL, ass_func_for_dsp_normal_img},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, 0, NULL, NULL},
+ {drdi_img, MD_PART_NAME, "md1drdi", 0x4000000, 0, 0, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+static download_info_t md1_download_list_v20001[] = {/* for 92 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr */
+ {main_img, MD_PART_NAME, "md1rom", MAX_MD_SIZE, 0, DUMMY_AP_FLAG, NULL, ass_func_for_v6_md_only_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x2000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {ramdisk_img,"userdata", "md1ramdisk",0x2000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {l1_core_img,"boot" , "l1core", 0x1000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+#else
+
+static download_info_t md1_download_list[] = {/* for 90, 91 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr | ass func p */
+ {main_img, "md1img", "md1rom", 0xA000000, 0, 0, NULL, ass_func_for_v5_normal_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x200000, 0, 0, NULL, NULL},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, 0, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+
+static download_info_t md1_download_list_v20000[] = {/* for 92, 93 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr | ass func p */
+ {main_img, "md1img", "md1rom", 0x10000000, 0, 0, NULL, ass_func_for_v6_normal_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x2000000, 0, 0, NULL, ass_func_for_dsp_normal_img},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, 0, NULL, NULL},
+ {drdi_img, "md1img", "md1drdi", 0x400000, 0, 0, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+static download_info_t md1_download_list_v40000[] = {/* for r8 modem with v1 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr | ass func p */
+ {main_img, "md1img", "md1rom", 0x1800000, 0, 0, NULL, ass_func_for_v1_r8_normal_img},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+
+
+static download_info_t md3_download_list[] = {
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr */
+ {main_img, "md3img", "md3rom", 0xC00000, 0, 0, NULL, ass_func_for_v1_normal_img},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+
+/* --- This part is used for dummy ap load ------------------- */
+static download_info_t md1_download_list_v10001[] = {/* for 90,91 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr */
+ {main_img, "md1img", "md1rom", 0x20000000, 0, DUMMY_AP_FLAG, NULL, ass_func_for_v5_md_only_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x200000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {ramdisk_img,"userdata", "md1ramdisk",0x2000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {l1_core_img,"boot" , "l1core", 0x1000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+static download_info_t md1_download_list_v20001[] = {/* for 92 */
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr */
+ {main_img, "md1img", "md1rom", 0x20000000, 0, DUMMY_AP_FLAG, NULL, ass_func_for_v6_md_only_img},
+ {dsp_img, "md1dsp", "md1dsp", 0x2000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {armv7_img, "md1arm7", "md1arm7", 0x200000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {ramdisk_img,"userdata", "md1ramdisk",0x2000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {l1_core_img,"boot" , "l1core", 0x1000000, 0, DUMMY_AP_FLAG, NULL, NULL},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+
+static download_info_t md3_download_list_v10001[] = {
+ /* img type | partition | image name | max size | img size | ext_flag | mem addr */
+ {main_img, "md3img", "md3rom", 0x10000000, 0, DUMMY_AP_FLAG, NULL, ass_func_for_v1_md_only_img},
+ {0, NULL, NULL, 0, 0, 0, NULL, NULL},
+};
+#endif
+static char md1_version[65];
+static char md3_version[65];
+static int md1_version_rdy, md3_version_rdy;
+
+int load_modem_image(const char *part_name)
+{
+ modem_info_t info;
+ unsigned long long ro_rw_limit;
+ unsigned long long ld_img_ver;
+ unsigned long align;
+ long long plat_query_ret;
+ int err_code = 0;
+ int ret;
+ unsigned char *smem_addr = NULL;
+ int smem_size = 0;
+ unsigned int md_load_status_flag = 0;
+ unsigned char *md_mem_base = NULL;
+#ifdef TELE_CCCI_SUPPORT
+ lk_time_t time_lk_md_init = current_time();
+#else
+ int time_lk_md_init = get_timer(0);
+#endif
+ char buf[128];
+
+ memset(md1_version, 0, sizeof(md1_version));
+ memset(md3_version, 0, sizeof(md3_version));
+ md1_version_rdy = 0;
+ md3_version_rdy = 0;
+
+ ccci_ld_md_wrapper_api_init();
+
+ /* --- 1. Get platform configure setting ---*/
+ if (ccci_hal_get_ld_md_plat_setting("support_detect") > 0) {
+ ALWAYS_LOG("Enter load_modem_image v2.0\n");
+ } else {
+ ALWAYS_LOG("Using load_modem_image v1.0\n");
+ err_code = -LD_ERR_PT_V2_PLAT_NOT_RDY;
+ goto _err_exit;
+ }
+ /* 2. tag info init */
+ ret = ccci_lk_tag_info_init((unsigned long long)((unsigned long)smem_addr));
+ if (ret < 0) {
+ ALWAYS_LOG("allocate tag memory fail\n");
+ err_code = -LD_ERR_PT_ALLOC_CMD_BUF_FAIL;
+ goto _err_exit;
+ }
+ /* 3. tel info init */
+#ifdef LK_MD_TEL_SUPPORT
+ ret = ccci_ld_md_tel_init();
+ if (ret < 0) {
+ err_code = -LD_ERR_PT_ALLOC_CMD_BUF_FAIL;
+ goto _err_exit;
+ }
+#endif
+ /* 4. security info init */
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("ro_rw_mem_limit");
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("ro rw mem limit abnormal:%d\n", (int)plat_query_ret);
+ err_code = -LD_ERR_PT_ALLOC_RORW_MEM_FAIL;
+ goto _err_exit;
+ }
+ ro_rw_limit = (unsigned long long)plat_query_ret;
+
+#ifdef MTK_SECURITY_SW_SUPPORT
+ md_mem_base = resv_named_memory("md1rom", 0x20000000);
+ ret = ccci_fit_get_image(part_name, md_mem_base);
+ if (ret < 0) {
+ ALWAYS_LOG("fit_get_image failed: %s %d!\n", part_name, ret);
+ goto _err_exit;
+ }
+ ret = ccci_fit_conf_verify_sig(NULL, md_mem_base);
+ if (ret < 0) {
+ ALWAYS_LOG("fit_conf_verify_sig failed: %s %d!\n", part_name, ret);
+ goto _err_exit;
+ }
+
+ ret = ccci_fit_load_image(NULL, "kernel", md_mem_base, NULL ,NULL, NULL, true);
+ if (ret < 0) {
+ ALWAYS_LOG("MD-fit image verify failed!\n");
+ goto _err_exit;
+ }
+#endif
+
+ /* 5. Prepare done, begin to load MD one by one */
+ if (ccci_get_opt_val("opt_md1_support") > 0) {
+ ALWAYS_LOG("-- MD1 --\n");
+
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("ro_rw_mem_align");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("align abnormal for ro rw:%d\n", (int)plat_query_ret);
+ err_code = -LD_ERR_PT_ALIGN_SETTING_ABNORMAL;
+ update_md_err_to_lk_info(MD_SYS1, err_code);
+ goto _load_md2;
+ }
+ align = (unsigned long)plat_query_ret;
+
+ /* Load image */
+ memset(&info, 0, sizeof(modem_info_t));
+ info.md_id = MD_SYS1;
+ ld_img_ver = ccci_hal_get_ld_md_plat_setting("ld_version");
+ switch (ld_img_ver) {
+#ifndef TELE_REDUCE_CODE
+ case 0x10001:
+ ret = ld_img_at_list(md1_download_list_v10001, &info, ro_rw_limit, align);
+ break;
+ case 0x10000:
+ ret = ld_img_at_list(md1_download_list, &info, ro_rw_limit, align);
+ break;
+#endif
+ case 0x20000:
+ md1_download_list_v20000[0].partition_name = part_name;
+ md1_download_list_v20000[3].partition_name = part_name;
+ ret = ld_img_at_list(md1_download_list_v20000, &info, ro_rw_limit, align);
+ break;
+ case 0x20001:
+ ret = ld_img_at_list(md1_download_list_v20001, &info, ro_rw_limit, align);
+ break;
+#ifndef TELE_REDUCE_CODE
+ case 0x40000:
+ ret = ld_img_at_list(md1_download_list_v40000, &info, ro_rw_limit, align);
+ break;
+#endif
+ default:
+#ifdef TELE_REDUCE_CODE
+ md1_download_list_v20000[0].partition_name = part_name;
+ md1_download_list_v20000[3].partition_name = part_name;
+ ret = ld_img_at_list(md1_download_list_v20000, &info, ro_rw_limit, align);
+#else
+ ret = ld_img_at_list(md1_download_list, &info, ro_rw_limit, align);
+#endif
+ break;
+ }
+ if (ret < 0) {
+ err_code = -LD_ERR_PT_MD1_LOAD_FAIL;
+ update_md_err_to_lk_info(MD_SYS1, ret);
+ ALWAYS_LOG("md1 load fail:%d\n", ret);
+#ifdef MTK_SECURITY_SW_SUPPORT
+ return -1;
+#endif
+ goto _load_md2;
+ }
+
+ /* Load success */
+ update_md_load_flag_to_lk_info(MD_SYS1);
+ add_hdr_info(s_g_md_ld_status, &info);
+ md_load_status_flag |= (1<<MD_SYS1);
+ }
+_load_md2:
+ /* Do nothong currently */
+ goto _load_md3;
+_load_md3:
+#ifndef TELE_REDUCE_CODE
+ if (ccci_get_opt_val("opt_md3_support") > 0) {
+ ALWAYS_LOG("-- MD3 --\n");
+
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("ro_rw_mem_align");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("align abnormal for ro rw:%d\n", (int)plat_query_ret);
+ err_code = -LD_ERR_PT_ALIGN_SETTING_ABNORMAL;
+ update_md_err_to_lk_info(MD_SYS3, err_code);
+ goto _load_end;
+ }
+ align = (unsigned long)plat_query_ret;
+
+ /* Load image */
+ memset(&info, 0, sizeof(modem_info_t));
+ info.md_id = MD_SYS3;
+ if (ccci_hal_get_ld_md_plat_setting("ld_version") == 0x10001 ||
+ ccci_hal_get_ld_md_plat_setting("ld_version") == 0x20001)
+ ret = ld_img_at_list(md3_download_list_v10001, &info, ro_rw_limit, align);
+ else
+ ret = ld_img_at_list(md3_download_list, &info, ro_rw_limit, align);
+ if (ret < 0) {
+ err_code = -LD_ERR_PT_MD3_LOAD_FAIL;
+ update_md_err_to_lk_info(MD_SYS3, ret);
+ ALWAYS_LOG("md3 load fail:%d\n", ret);
+#ifdef MTK_SECURITY_SW_SUPPORT
+ return -1
+#endif
+ goto _load_end;
+ }
+
+ /* Load success */
+ update_md_load_flag_to_lk_info(MD_SYS3);
+ add_hdr_info(s_g_md_ld_status, &info);
+ md_load_status_flag |= (1<<MD_SYS3);
+ }
+#endif
+_load_end:
+ /* 6. smem init: start */
+ plat_query_ret = ccci_hal_get_ld_md_plat_setting("share_memory_size");
+
+ if (plat_query_ret <= 0) {
+ ALWAYS_LOG("Share memory size abnormal:%d\n", (int)plat_query_ret);
+ err_code = -LD_ERR_PT_SMEM_SIZE_ABNORMAL;
+ goto _err_exit;
+ }
+ smem_size = (int)plat_query_ret;
+#ifdef REQUEST_SMEM_IN_LK
+ smem_addr = resv_named_memory("md_smem_ncache", smem_size);
+ if (smem_addr == NULL) {
+ ALWAYS_LOG("allocate MD share memory fail\n");
+ err_code = -LD_ERR_PT_ALLOC_SMEM_FAIL;
+ goto _err_exit;
+ }
+ keep_md_ncache_memory((unsigned long long)smem_addr, smem_size);
+ ccci_hal_apply_hw_remap_for_md_smem(smem_addr, smem_size);
+ /* smem init: end */
+#endif
+ /* 7. information settings. */
+ /* update hdr_count info */
+ if (insert_ccci_tag_inf("hdr_count", (char*)&s_g_md_ld_record_num, sizeof(unsigned int)) < 0)
+ ALWAYS_LOG("insert hdr_count fail\n");
+
+ /* update hdr tbl info */
+ if (insert_ccci_tag_inf("hdr_tbl_inf", (char*)s_g_md_ld_status,
+ sizeof(modem_info_t)*s_g_md_ld_record_num) < 0)
+ ALWAYS_LOG("insert hdr_tbl_inf fail\n");
+
+ if (insert_ccci_tag_inf("retrieve_num", (char*)&retrieve_info_num, sizeof(int)) < 0)
+ ALWAYS_LOG("insert retrieve_num fail\n");
+
+ ret = ccci_hal_apply_platform_setting(md_load_status_flag);
+ if (ret < 0) {
+ /* free all reserved share memory */
+ ALWAYS_LOG("ccci_hal_apply_platform_setting ret %d \n", ret);
+ err_code = -LD_ERR_PT_APPLY_PLAT_SETTING_FAIL;
+ update_common_err_to_lk_info(err_code);
+ goto _err_exit;
+ } else if (ret == 0) {
+ /* free all reserved share memory */
+ ALWAYS_LOG("No MD Image enabled %d \n", ret);
+ /* err_code = 0; */
+ goto _err_exit;
+ } else if (ret < smem_size) {
+ /* smem size returned from platform setting API, */
+ /* resize share memory to final size */
+ ALWAYS_LOG("re-size share memory form %x to %x\n", smem_size, ret);
+#ifdef REQUEST_SMEM_IN_LK
+ ccci_resize_reserve_mem(smem_addr, smem_size, ret);
+#endif
+ }
+ extern void load_success_notify(int error_no)__attribute__((weak));
+ if (load_success_notify) {
+ load_success_notify(err_code);
+ }
+
+ goto _OK_and_exit;
+
+_err_exit:
+#ifdef LK_MD_TEL_SUPPORT
+ ccci_free_local_cmd_line_buf();
+#endif
+ update_common_err_to_lk_info(err_code);
+
+_OK_and_exit:
+
+ ccci_ld_md_add_wrapper_api_info();
+ ccci_lk_info_ctl_dump();
+#ifdef TELE_CCCI_SUPPORT
+ CRITICAL_LOG("[PROFILE] ------- load_modem_image init cost %d ms ----\n", (int)(current_time() - time_lk_md_init));
+#else
+ CRITICAL_LOG("[PROFILE] ------- load_modem_image init cost %d ms ----\n", (int)get_timer(time_lk_md_init));
+#endif
+ ret = ccci_get_md_version(MD_SYS1, buf, 128);
+ CRITICAL_LOG("[MD1 Baseband version] %s(%d)\r\n", buf, ret);
+ ret = ccci_get_md_version(MD_SYS3, buf, 128);
+ CRITICAL_LOG("[MD3 Baseband version] %s(%d)\r\n", buf, ret);
+ return 0;
+}
+
+void ccci_update_md_version(int md_id, unsigned char ver[])
+{
+ if (md_id == MD_SYS1) {
+ md1_version_rdy = 1;
+ snprintf(md1_version, 65, "%s", ver);
+ } else if (md_id == MD_SYS3) {
+ md3_version_rdy = 1;
+ snprintf(md3_version, 65, "%s", ver);
+ }
+}
+
+int ccci_get_md_version(int md_id, char buf[], int size)
+{
+ if ((md_id == MD_SYS1) && md1_version_rdy)
+ return snprintf(buf, size, "%s", md1_version);
+ else if ((md_id == MD_SYS3) && md3_version_rdy)
+ return snprintf(buf, size, "%s", md3_version);
+
+ return -1;
+}
+
+static const char *errno_str[] = {
+ "LD_ERR_NULL_PTR",
+ "LD_ERR_GET_COM_CHK_HDR_FAIL",
+ "LD_ERR_CHK_HDR_PATTERN",
+ "LD_ERR_RESERVE_MEM_NOT_ENOUGH",
+ "LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL",
+ "LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL",
+ "LD_ERR_ASS_FIND_MAIN_INF_FAIL",
+ "LD_ERR_ASS_FIND_DSP_INF_FAIL",
+ "LD_ERR_ASS_FIND_ARMV7_INF_FAIL",
+ "LD_ERR_ASS_FIND_RAMDISK_INF_FAIL",
+ "LD_ERR_ASS_FIND_L1CORE_INF_FAIL",
+ "LD_ERR_TAG_BUF_FULL",
+ "LD_ERR_PAD_SIZE_LESS_THAN_64K",
+ "LD_ERR_PAD_INVALID_INF",
+ "LD_ERR_PAD_FREE_INF_ABNORMAL",
+ "LD_ERR_PAD_OVER_TWO_REGION",
+ "LD_ERR_PAD_MISC",
+ "LD_ERR_PAD_REGION_NOT_ENOUGH",
+ "LD_ERR_PAD_NO_REGION_RETRIEVE",
+ "LD_ERR_OPT_SETTING_INVALID",
+ "LD_ERR_OPT_NOT_FOUND",
+ "LD_ERR_OPT_CMD_BUF_ALLOC_FAIL",
+ "LD_ERR_PT_DEV_NULL",
+ "LD_ERR_PT_NOT_FOUND",
+ "LD_ERR_PT_READ_RAW_FAIL",
+ "LD_ERR_PT_IMG_LIST_NULL",
+ "LD_ERR_PT_ALLOC_HDR_MEM_FAIL",
+ "LD_ERR_PT_READ_HDR_SIZE_ABNORMAL",
+ "LD_ERR_PT_P_HDR_MAGIC_MIS_MATCH",
+ "LD_ERR_PT_MAIN_IMG_SIZE_ABNORMAL",
+ "LD_ERR_PT_CERT_CHAIN_FAIL",
+ "LD_ERR_PT_IMG_TOO_LARGE",
+ "LD_ERR_PT_IMG_SIZE_NOT_SYNC_CHK_HDR",
+ "LD_ERR_PT_ALLOC_MD_MEM_FAIL",
+ "LD_ERR_PT_LD_IMG_DATA_FAIL",
+ "LD_ERR_PT_HASH_CHK_FAIL",
+ "LD_ERR_PT_V2_PLAT_NOT_RDY",
+ "LD_ERR_PT_SMEM_SIZE_ABNORMAL",
+ "LD_ERR_PT_LIMIT_SETTING_ABNORMAL",
+ "LD_ERR_PT_ALIGN_SETTING_ABNORMAL",
+ "LD_ERR_PT_ALLOC_RORW_MEM_FAIL",
+ "LD_ERR_PT_ALLOC_SMEM_FAIL",
+ "LD_ERR_PT_ALLOC_CMD_BUF_FAIL",
+ "LD_ERR_PT_MD1_LOAD_FAIL",
+ "LD_ERR_PT_MD3_LOAD_FAIL",
+ "LD_ERR_PT_APPLY_PLAT_SETTING_FAIL",
+ "LD_ERR_PT_CHK_IMG_NAME_FAIL",
+ "LD_ERR_PLAT_INVALID_MD_ID",
+ "LD_ERR_PLAT_MPU_REGION_EMPTY",
+ "LD_ERR_PLAT_MPU_REGION_TOO_MORE",
+ "LD_ERR_PLAT_MPU_REGION_NUM_NOT_SYNC",
+ "LD_ERR_PLAT_ABNORMAL_FREE_REGION",
+ "LD_ERR_PLAT_ABNORMAL_PAD_ARRAY",
+ "LD_ERR_PLAT_NO_MORE_FREE_REGION",
+ "LD_ERR_PLAT_MD1_NOT_RDY",
+ "LD_ERR_ASS_FIND_DRDI_INF_FAIL"
+};
+const char *ld_md_errno_to_str(int err_no)
+{
+ if (err_no < 1)
+ return "invalid errno";
+
+ if ((err_no-1) < (int)(sizeof(errno_str)/sizeof(char*)))
+ return errno_str[err_no-1];
+
+ return "errno not found";
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.h b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.h
new file mode 100644
index 0000000..56793d9
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_core.h
@@ -0,0 +1,443 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#ifndef __CCCI_LD_MD_CORE_H__
+#define __CCCI_LD_MD_CORE_H__
+
+#include "ccci_ld_md_log_cfg.h"
+#ifndef TELE_CCCI_SUPPORT
+#include <verified_boot_common.h>
+#endif
+
+/* Log part */
+#if defined(MTK_BUILD_USER_LOAD)
+#define CRITICAL_LOG(fmt, args...) do {dprintf(CRITICAL, fmt, ##args);} while (0)
+#define ALWAYS_LOG(fmt, args...)
+#define DBG_LOG(fmt, args...)
+#else
+#define CRITICAL_LOG(fmt, args...) do {dprintf(CRITICAL, fmt, ##args);} while (0)
+#define ALWAYS_LOG(fmt, args...) do {dprintf(ALWAYS, fmt, ##args);} while (0)
+#define DBG_LOG(fmt, args...) do {dprintf(INFO, fmt, ##args);} while (0)
+#endif
+
+/* Switch log */
+#ifdef TAG_DEBUG_LOG_EN
+#define TAG_DBG_LOG(fmt, args...) do {dprintf(ALWAYS, fmt, ##args);} while (0)
+#else
+#define TAG_DBG_LOG(fmt, args...)
+#endif
+#ifdef PADDING_MEM_DEBUG_LOG_EN
+#define PADDING_LOG(fmt, args...) do {dprintf(ALWAYS, fmt, ##args);} while (0)
+#else
+#define PADDING_LOG(fmt, args...)
+#endif
+#ifdef LD_IMG_DUMP_LOG_EN
+#define LD_DBG_LOG(fmt, args...) do {dprintf(ALWAYS, fmt, ##args);} while (0)
+#else
+#define LD_DBG_LOG(fmt, args...)
+#endif
+#ifdef MPU_DBG_LOG_EN
+#define MPU_DBG_LOG(fmt, args...) do {dprintf(INFO, fmt, ##args);} while (0)
+#else
+#define MPU_DBG_LOG(fmt, args...)
+#endif
+#ifdef ENABLE_DT_DBG_LOG
+#define DT_DBG_LOG(fmt, args...) do {dprintf(INFO, fmt, ##args);} while (0)
+#else
+#define DT_DBG_LOG(fmt, args...)
+#endif
+
+
+/***************************************************************************************************
+** Core Global variable and macro defination part
+***************************************************************************************************/
+
+#define MAX_MD_NUM 4
+#define MAX_PADDING_NUM_V5_HDR 3
+#define MAX_PADDING_NUM_V6_HDR 8
+
+#define MAIN_IMG_MIN_SIZE 0x8000
+#define DSP_IMG_MAX_SIZE 0x1800000
+#define MPU_64K_ALIGN_MASK (~(0x10000-1))
+#define MPU_64K_VALUE (0x10000)
+#define MEM_4K_ALIGN_MASK (~(0x1000-1))
+#define MEM_4K_VALUE (0x1000)
+
+enum {
+ MD_SYS1 = 0,
+ MD_SYS2,
+ MD_SYS3,
+ MD_SYS4,
+ MD1_DSP,
+};
+
+/***************************************************************************************************
+** Sub sectoin:
+** modem info
+***************************************************************************************************/
+typedef struct _modem_info {
+ unsigned long long base_addr;
+ unsigned int resv_mem_size;
+ char md_id;
+ char err_no;
+ char md_type;
+ char ver;
+ int load_size;/*ROM + Check header*/
+ int ro_rw_size;
+} modem_info_t;
+
+extern int retrieve_info_num;
+
+/***************************************************************************************************
+** Sub section:
+** modem/dsp check header
+***************************************************************************************************/
+struct md_check_header_comm {
+ unsigned char check_header[12]; /* magic number is "CHECK_HEADER"*/
+ unsigned int header_verno; /* header structure version number */
+ unsigned int product_ver; /* 0x0:invalid; 0x1:debug version; 0x2:release version */
+ unsigned int image_type; /* 0x0:invalid; 0x1:2G modem; 0x2: 3G modem */
+ unsigned char platform[16]; /* MT6573_S01 or MT6573_S02 */
+ unsigned char build_time[64]; /* build time string */
+ unsigned char build_ver[64]; /* project version, ex:11A_MD.W11.28 */
+
+ unsigned char bind_sys_id; /* bind to md sys id, MD SYS1: 1, MD SYS2: 2 */
+ unsigned char ext_attr; /* no shrink: 0, shrink: 1*/
+ unsigned char reserved[2]; /* for reserved */
+
+ unsigned int mem_size; /* md ROM/RAM image size requested by md */
+ unsigned int md_img_size; /* md image size, exclude head size*/
+} __attribute__((packed));
+
+struct md_check_header_v1 {
+ struct md_check_header_comm common; /* common part */
+ unsigned int ap_md_smem_size; /* share memory size */
+ unsigned int size; /* the size of this structure */
+} __attribute__((packed));
+
+struct md_check_header_v3 {
+ struct md_check_header_comm common; /* common part */
+ unsigned int rpc_sec_mem_addr; /* RPC secure memory address */
+
+ unsigned int dsp_img_offset;
+ unsigned int dsp_img_size;
+ unsigned char reserved2[88];
+
+ unsigned int size; /* the size of this structure */
+} __attribute__((packed));
+
+typedef struct _md_regin_info {
+ unsigned int region_offset;
+ unsigned int region_size;
+} md_regin_info;
+
+struct md_check_header_v4 {
+ struct md_check_header_comm common; /* common part */
+ unsigned int rpc_sec_mem_addr; /* RPC secure memory address */
+
+ unsigned int dsp_img_offset;
+ unsigned int dsp_img_size;
+
+ unsigned int region_num; /* total region number */
+ md_regin_info region_info[8]; /* max support 8 regions */
+ unsigned int domain_attr[4]; /* max support 4 domain settings, each region has 4 control bits*/
+
+ unsigned char reserved2[4];
+
+ unsigned int size; /* the size of this structure */
+} __attribute__((packed));
+
+typedef struct _free_padding_block {
+ unsigned int start_offset;
+ unsigned int length;
+} free_padding_block_t;
+
+struct md_check_header_v5 {
+ struct md_check_header_comm common; /* common part */
+ unsigned int rpc_sec_mem_addr; /* RPC secure memory address */
+
+ unsigned int dsp_img_offset;
+ unsigned int dsp_img_size;
+
+ unsigned int region_num; /* total region number */
+ md_regin_info region_info[8]; /* max support 8 regions */
+ unsigned int domain_attr[4]; /* max support 4 domain settings, each region has 4 control bits*/
+
+ unsigned int arm7_img_offset;
+ unsigned int arm7_img_size;
+
+ free_padding_block_t padding_blk[MAX_PADDING_NUM_V5_HDR]; /* should be 3 */
+ unsigned int ap_md_smem_size;
+ unsigned int md_to_md_smem_size;
+
+ unsigned int ramdisk_offset;
+ unsigned int ramdisk_size;
+
+ unsigned char reserved_1[16];
+
+ unsigned int size; /* the size of this structure */
+};
+
+struct md_check_header_v6 {
+ struct md_check_header_comm common; /* common part */
+ unsigned int rpc_sec_mem_addr; /* RPC secure memory address */
+
+ unsigned int dsp_img_offset;
+ unsigned int dsp_img_size;
+
+ unsigned int region_num; /* total region number */
+ md_regin_info region_info[8]; /* max support 8 regions */
+ unsigned int domain_attr[4]; /* max support 4 domain settings, each region has 4 control bits*/
+
+ unsigned int arm7_img_offset;
+ unsigned int arm7_img_size;
+
+ free_padding_block_t padding_blk[MAX_PADDING_NUM_V6_HDR]; /* should be 8 */
+
+ unsigned int ap_md_smem_size;
+ unsigned int md_to_md_smem_size;
+
+ unsigned int ramdisk_offset;
+ unsigned int ramdisk_size;
+
+ unsigned int drdi_offset; /* For load sub image */
+ unsigned int drdi_size; /* For load sub image */
+ unsigned int drdi_rt_offset; /* For runtime position */
+ unsigned int drdi_rt_size; /* For runtime position */
+
+ unsigned int amms_pos_size;
+ unsigned int consys_size;
+ unsigned char reserved_1[120];
+
+ unsigned int size; /* the size of this structure */
+};
+
+struct image_section_desc {
+ unsigned int offset;
+ unsigned int size;
+ unsigned int mpu_attr;
+ unsigned int ext_flag;
+ unsigned int relate_idx;
+};
+
+/* dsp check header */
+struct dsp_check_header {
+ unsigned char check_header[8];
+ unsigned char file_info_H[12];
+ unsigned char unknown[52];
+ unsigned char chip_id[16];
+ unsigned char dsp_info[48];
+};
+
+/***************************************************************************************************
+** Sub section:
+** padding memory for v5 check hdr
+***************************************************************************************************/
+/* This function only support 3 cases
+** case 0: |======|======| ==> |++====|======|
+** case 1: |======|======| ==> |==++==|======|
+** case 2: |======|======| ==> |====++|======|
+** case 4: |======|======| ==> |=====+|+=====| NOT suppose this case !!!!
+*/
+#define VALID_PADDING (1<<0)
+#define NEED_MPU_MORE (1<<1)
+#define NEED_REMOVE (1<<2)
+#define MD_ALL_RANGE (1<<3)
+#define MD_DRDI_REGION (1<<4)
+
+#define LOGIC_BINDING_IDX_START 0x1000
+
+struct padding_tag {
+ free_padding_block_t padding_mem;
+ int status;
+};
+
+/***************************************************************************************************
+** Sub section:
+** Telephony operation parsing and prepare part
+***************************************************************************************************/
+struct opt_cfg {
+ char *name;
+ int val;
+};
+
+/* 0 | 0 | Lf | Lt | W | C | T | G */
+#define MD_CAP_KEY (0x5A<<24)
+#define MD_CAP_GSM (1<<0)
+#define MD_CAP_TDS_CDMA (1<<1)
+#define MD_CAP_CDMA2000 (1<<2)
+#define MD_CAP_WCDMA (1<<3)
+#define MD_CAP_TDD_LTE (1<<4)
+#define MD_CAP_FDD_LTE (1<<5)
+#define MD_CAP_NR (1<<6)
+#define MD_CAP_MASK (MD_CAP_GSM|MD_CAP_TDS_CDMA|MD_CAP_WCDMA|MD_CAP_TDD_LTE|MD_CAP_FDD_LTE|MD_CAP_CDMA2000|MD_CAP_NR)
+
+
+typedef enum {
+ RAT_VER_DEFAULT = 0,
+ RAT_VER_R8,
+ RAT_VER_90,
+ RAT_VER_91_92,
+ RAT_VER_93,
+} lk_md_generation_t;
+
+/***************************************************************************************************
+** Sub section
+** image loading part for each image list
+** NOTE: this structure has a duplicate one at platform code
+***************************************************************************************************/
+#define LD_IMG_NO_VERIFY (1<<0)
+#define DUMMY_AP_FLAG LD_IMG_NO_VERIFY
+
+typedef int (*ld_md_assistant_t)(void *load_info, void *data);
+
+typedef struct _download_info {
+ int img_type; /* Main image, or plug-in image */
+ const char *partition_name;
+ const char *image_name;
+ int max_size;
+ int img_size;
+ int ext_flag;
+ unsigned char *mem_addr;
+ ld_md_assistant_t ass_func;
+} download_info_t;
+
+enum {
+ main_img = 1,
+ dsp_img,
+ armv7_img,
+ ramdisk_img,
+ l1_core_img,
+ drdi_img,
+ max_img_num
+};
+
+
+/* This function is used by common and platform code to use */
+unsigned int str2uint(char *str);
+
+
+/*************************************************************************/
+/* Sub module exported API */
+/*************************************************************************/
+/* --- Tag info --- */
+int insert_ccci_tag_inf(const char *name, char *data, unsigned int size);
+int ccci_lk_tag_info_init(unsigned long long base_addr);
+void ccci_lk_info_ctl_dump(void);
+void update_md_err_to_lk_info(int md_id, int error);
+int get_md_err_from_lk_info(int md_id);
+void update_md_load_flag_to_lk_info(int md_id);
+void update_common_err_to_lk_info(int error);
+void ccci_lk_info_re_cfg(unsigned long long base_addr, unsigned int size);
+void keep_md_image_retrieve_memory(unsigned long long address, unsigned int size);
+void keep_md_ncache_memory(unsigned long long address, unsigned int size);
+void keep_md_cache_memory(unsigned long long address, unsigned int size);
+/* --- assistance --- */
+int verify_main_img_check_header(modem_info_t *info);
+int ass_func_for_v5_normal_img(void *load_info, void *data);
+int ass_func_for_v6_normal_img(void *load_info, void *data);
+int ass_func_for_v1_normal_img(void *load_info, void *data);
+int ass_func_for_v1_r8_normal_img(void *load_info, void *data);
+int ass_func_for_dsp_normal_img(void *load_info, void *data);
+int ass_func_for_v5_md_only_img(void *load_info, void *data);
+int ass_func_for_v6_md_only_img(void *load_info, void *data);
+int ass_func_for_v1_md_only_img(void *load_info, void *data);
+/* --- padding memory --- */
+int retrieve_free_padding_mem_v5_hdr(modem_info_t *info,
+ struct image_section_desc mem_tbl[], void *hdr, int mpu_num);
+int retrieve_free_padding_mem_v6_hdr(modem_info_t *info,
+ struct image_section_desc mem_tbl[], void *hdr, int mpu_num);
+void log_retrieve_info(unsigned char *addr, int size);
+/* --- errno string --- */
+const char *ld_md_errno_to_str(int err_no);
+
+/* --- md version api --- */
+void ccci_update_md_version(int md_id, unsigned char ver[]);
+int ccci_get_md_version(int md_id, char buf[], int size);
+
+/* --- wrapper api --- */
+void *ccci_request_resv_memory(unsigned int mem_size, unsigned long long limit, unsigned long align);
+void *ccci_request_mem(unsigned int mem_size, unsigned long long limit, unsigned long align);
+void *ccci_request_named_mem(const char *name, unsigned int mem_size, unsigned long long limit, unsigned long align);
+void *resv_named_memory(const char name[], unsigned int size);
+int ccci_retrieve_mem(unsigned char *addr, int size);
+int ccci_load_raw_data(const char *part_name, unsigned char *mem_addr, unsigned int offset, int size);
+int ccci_resize_reserve_mem(unsigned char *addr, int old_size, int new_size);
+int ccci_free_not_used_reserved_memory(unsigned char *md_start_addr, int reserved, int required);
+void ccci_ld_md_wrapper_api_init(void);
+void ccci_ld_md_add_wrapper_api_info(void);
+
+/* --- sec api --- */
+void ccci_ld_md_sec_init(void);
+int ccci_ld_md_sec_ptr_hdr_verify(const char *partition_name, const char *image_name);
+int ccci_ld_md_sec_image_verify(const char *partition_name, const char *image_name, unsigned char *mem_addr, int size);
+
+
+/* API that implemented by other module */
+#ifdef TELE_CCCI_SUPPORT
+#if WITH_KERNEL_VM
+extern __WEAK paddr_t kvaddr_to_paddr(void *ptr);
+#endif
+#else
+extern int mblock_create(mblock_info_t *mblock_info, dram_info_t *orig_dram_info, u64 addr, u64 size);
+#endif
+extern void arch_sync_cache_range(addr_t start, size_t len);
+extern char *get_env(char *name);
+extern char *get_ro_env(char *name)__attribute__((weak));
+extern int set_env(char *name, char *value);
+
+/***************************************************************************************************
+****************************************************************************************************
+** Sub section:
+** Export API from platform, for reasons the following, weak key word added.
+** 1. in order to make code compatible;
+** 2. avoid build error that some old platform does not support
+****************************************************************************************************
+***************************************************************************************************/
+extern int plat_dt_reserve_mem_size_fixup(void *fdt)__attribute__((weak));
+extern long long plat_ccci_get_ld_md_plat_setting(const char cfg_name[])__attribute__((weak));
+extern int plat_get_padding_mpu_num(void)__attribute__((weak));
+extern int plat_apply_hw_remap_for_md_ro_rw(void*)__attribute__((weak));
+extern int plat_apply_hw_remap_for_md_smem(void* addr, int size)__attribute__((weak));
+extern int plat_send_mpu_info_to_platorm(void*, void*)__attribute__((weak));
+extern int plat_apply_platform_setting(int)__attribute__((weak));
+extern void plat_post_hdr_info(void* hdr, int ver, int id)__attribute__((weak));
+extern int get_mem_limit_and_align(const char key[], unsigned long long *limit, unsigned long *align);
+
+/* HAL API */
+long long ccci_hal_get_ld_md_plat_setting(const char cfg_name[]);
+int ccci_hal_get_mpu_num_for_padding_mem(void);
+int ccci_hal_apply_hw_remap_for_md_ro_rw(void *md_info);
+int ccci_hal_apply_hw_remap_for_md_smem(void *addr, int size);
+int ccci_hal_send_mpu_info_to_platorm(void *md_info, void *mem_info);
+int ccci_hal_apply_platform_setting(int load_flag);
+void ccci_hal_post_hdr_info(void *hdr, int ver, int id);
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_errno.h b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_errno.h
new file mode 100644
index 0000000..ae7c594
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_errno.h
@@ -0,0 +1,95 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#ifndef __CCCI_LD_MD_ERRNO_H__
+#define __CCCI_LD_MD_ERRNO_H__
+
+enum {
+ LD_ERR_NULL_PTR = 1,
+ LD_ERR_GET_COM_CHK_HDR_FAIL,
+ LD_ERR_CHK_HDR_PATTERN,
+ LD_ERR_RESERVE_MEM_NOT_ENOUGH,
+ LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL,
+ LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL,
+ LD_ERR_ASS_FIND_MAIN_INF_FAIL,
+ LD_ERR_ASS_FIND_DSP_INF_FAIL,
+ LD_ERR_ASS_FIND_ARMV7_INF_FAIL,
+ LD_ERR_ASS_FIND_RAMDISK_INF_FAIL,
+ LD_ERR_ASS_FIND_L1CORE_INF_FAIL,
+ LD_ERR_TAG_BUF_FULL,
+ LD_ERR_PAD_SIZE_LESS_THAN_64K,
+ LD_ERR_PAD_INVALID_INF,
+ LD_ERR_PAD_FREE_INF_ABNORMAL,
+ LD_ERR_PAD_OVER_TWO_REGION,
+ LD_ERR_PAD_MISC,
+ LD_ERR_PAD_REGION_NOT_ENOUGH,
+ LD_ERR_PAD_NO_REGION_RETRIEVE,
+ LD_ERR_OPT_SETTING_INVALID,
+ LD_ERR_OPT_NOT_FOUND,
+ LD_ERR_OPT_CMD_BUF_ALLOC_FAIL,
+ LD_ERR_PT_DEV_NULL,
+ LD_ERR_PT_NOT_FOUND,
+ LD_ERR_PT_READ_RAW_FAIL,
+ LD_ERR_PT_IMG_LIST_NULL,
+ LD_ERR_PT_ALLOC_HDR_MEM_FAIL,
+ LD_ERR_PT_READ_HDR_SIZE_ABNORMAL,
+ LD_ERR_PT_P_HDR_MAGIC_MIS_MATCH,
+ LD_ERR_PT_MAIN_IMG_SIZE_ABNORMAL,
+ LD_ERR_PT_CERT_CHAIN_FAIL,
+ LD_ERR_PT_IMG_TOO_LARGE,
+ LD_ERR_PT_IMG_SIZE_NOT_SYNC_CHK_HDR,
+ LD_ERR_PT_ALLOC_MD_MEM_FAIL,
+ LD_ERR_PT_LD_IMG_DATA_FAIL,
+ LD_ERR_PT_HASH_CHK_FAIL,
+ LD_ERR_PT_V2_PLAT_NOT_RDY,
+ LD_ERR_PT_SMEM_SIZE_ABNORMAL,
+ LD_ERR_PT_LIMIT_SETTING_ABNORMAL,
+ LD_ERR_PT_ALIGN_SETTING_ABNORMAL,
+ LD_ERR_PT_ALLOC_RORW_MEM_FAIL,
+ LD_ERR_PT_ALLOC_SMEM_FAIL,
+ LD_ERR_PT_ALLOC_CMD_BUF_FAIL,
+ LD_ERR_PT_MD1_LOAD_FAIL,
+ LD_ERR_PT_MD3_LOAD_FAIL,
+ LD_ERR_PT_APPLY_PLAT_SETTING_FAIL,
+ LD_ERR_PT_CHK_IMG_NAME_FAIL,
+ LD_ERR_PLAT_INVALID_MD_ID,
+ LD_ERR_PLAT_MPU_REGION_EMPTY,
+ LD_ERR_PLAT_MPU_REGION_TOO_MORE,
+ LD_ERR_PLAT_MPU_REGION_NUM_NOT_SYNC,
+ LD_ERR_PLAT_ABNORMAL_FREE_REGION,
+ LD_ERR_PLAT_ABNORMAL_PAD_ARRAY,
+ LD_ERR_PLAT_NO_MORE_FREE_REGION,
+ LD_ERR_PLAT_MD1_NOT_RDY,
+ LD_ERR_ASS_FIND_DRDI_INF_FAIL,
+};
+
+
+
+#endif
\ No newline at end of file
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_hal.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_hal.c
new file mode 100644
index 0000000..fa9f2e1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_hal.c
@@ -0,0 +1,123 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#endif
+#define MODULE_NAME "LK_LD_MD"
+
+/******************************************************************************/
+/* Platform code wrapper */
+long long ccci_hal_get_ld_md_plat_setting(const char cfg_name[])
+{
+ long long (*NULL_FP)(const char str[]) = 0;
+ if (strcmp(cfg_name, "support_detect") == 0) {
+ if (NULL_FP == plat_ccci_get_ld_md_plat_setting)
+ return 0LL;
+ return 1LL;
+ }
+
+ if (NULL_FP == plat_ccci_get_ld_md_plat_setting)
+ return 0LL;
+
+ return plat_ccci_get_ld_md_plat_setting(cfg_name);
+}
+
+int ccci_hal_get_mpu_num_for_padding_mem(void)
+{
+ int (*NULL_FP)(void) = 0;
+ if (NULL_FP == plat_get_padding_mpu_num)
+ return 0;
+
+ return plat_get_padding_mpu_num();
+}
+
+int ccci_hal_apply_hw_remap_for_md_ro_rw(void *md_info)
+{
+ int (*NULL_FP)(void *) = 0;
+ if (NULL_FP == plat_apply_hw_remap_for_md_ro_rw)
+ return -1;
+
+ return plat_apply_hw_remap_for_md_ro_rw(md_info);
+}
+
+int ccci_hal_apply_hw_remap_for_md_smem(void *addr, int size)
+{
+ int (*NULL_FP)(void *, int) = 0;
+ if (NULL_FP == plat_apply_hw_remap_for_md_smem)
+ return -1;
+
+ return plat_apply_hw_remap_for_md_smem(addr, size);
+}
+
+int ccci_hal_send_mpu_info_to_platorm(void *md_info, void *mem_info)
+{
+ int (*NULL_FP)(void *, void *) = 0;
+ if (NULL_FP == plat_send_mpu_info_to_platorm)
+ return -1;
+
+ return plat_send_mpu_info_to_platorm(md_info, mem_info);
+}
+
+int ccci_hal_apply_platform_setting(int load_flag)
+{
+ int (*NULL_FP)(int) = 0;
+ if (NULL_FP == plat_apply_platform_setting)
+ return -1;
+
+ return plat_apply_platform_setting(load_flag);
+}
+
+void ccci_hal_post_hdr_info(void *hdr, int ver, int id)
+{
+ void (*NULL_FP)(void *, int, int) = 0;
+ if (NULL_FP == plat_post_hdr_info)
+ return;
+
+ plat_post_hdr_info(hdr, ver, id);
+}
+
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_log_cfg.h b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_log_cfg.h
new file mode 100644
index 0000000..c2614c4
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_log_cfg.h
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#ifndef __CCCI_LD_MD_LOG_CFG_H__
+#define __CCCI_LD_MD_LOG_CFG_H__
+
+#if !defined(MTK_BUILD_USER_LOAD)
+//#define PADDING_MEM_DEBUG_LOG_EN
+//#define TAG_DEBUG_LOG_EN
+#define LD_IMG_DUMP_LOG_EN
+//#define ENABLE_DT_DBG_LOG
+//#define MPU_DBG_LOG_EN
+#endif
+
+#define TELE_CCCI_SUPPORT
+
+#ifdef TELE_CCCI_SUPPORT
+#define TELE_REDUCE_CODE
+#define REQUEST_SMEM_IN_LK
+#define CCCI_MD_TAG_INFO
+#else
+#define LK_MD_TEL_SUPPORT
+#define REQUEST_SMEM_IN_LK
+#define CCCI_MD_TAG_INFO
+#endif
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_padding.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_padding.c
new file mode 100644
index 0000000..94b5f8c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_padding.c
@@ -0,0 +1,563 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#endif
+
+#define MODULE_NAME "LK_LD_MD"
+
+
+/***************************************************************************************************
+** Sub section:
+** padding memory for v5 check hdr
+***************************************************************************************************/
+/* This function only support 3 cases
+** case 0: |======|======| ==> |++====|======|
+** case 1: |======|======| ==> |==++==|======|
+** case 2: |======|======| ==> |====++|======|
+** case 4: |======|======| ==> |=====+|+=====| NOT suppose this case !!!!
+**
+** return value:
+** 1 : retrieve success and used one mpu region
+** 0 : retrieve success but not used one mpu region
+** -1 : error
+*/
+static int free_padding_mem_blk_match(modem_info_t *info, struct image_section_desc mem_tbl[],
+ int mem_tbl_item_num, free_padding_block_t *free_mem)
+{
+ int i;
+ int mem_blk_num = mem_tbl_item_num;
+ unsigned int tmp_start_addr, tmp_end_addr;
+ unsigned int old_start, old_end;
+ unsigned char *mem_addr = (unsigned char *)((unsigned long)info->base_addr);
+
+#ifdef TELE_CCCI_SUPPORT
+
+#else
+ ALWAYS_LOG("== Get retrieve %p~%p =======\n",
+ (unsigned char *)free_mem->start_offset,
+ (unsigned char *)free_mem->start_offset
+ + free_mem->length - 1);
+#endif
+ if (free_mem->length < MPU_64K_VALUE) {
+ ALWAYS_LOG("free memory too small\n");
+ return -LD_ERR_PAD_SIZE_LESS_THAN_64K;
+ }
+
+ /* Find free memory position */
+ for (i = 0; i < mem_blk_num; i++) {
+ PADDING_LOG("i=%d, offset 0x%x, size 0x%x\n", i, mem_tbl[i].offset, mem_tbl[i].size);
+ if ((free_mem->start_offset >= mem_tbl[i].offset) &&
+ (free_mem->start_offset <= (mem_tbl[i].offset + mem_tbl[i].size -1)))
+ break;
+ }
+
+ if (i == mem_blk_num) {
+ ALWAYS_LOG("invalid free memory slot info, not at any block\n");
+ return -LD_ERR_PAD_INVALID_INF;
+ }
+
+ old_start = mem_tbl[i].offset;
+ old_end = mem_tbl[i].offset + mem_tbl[i].size -1;
+ DBG_LOG("[%p~%p] ==>\n", mem_addr + old_start, mem_addr + old_end);
+ if (free_mem->start_offset == mem_tbl[i].offset) {
+ /* case 0, no need use one mpu region */
+ if (free_mem->length > mem_tbl[i].size) {
+ ALWAYS_LOG("free memory size too large\n");
+ return -LD_ERR_PAD_FREE_INF_ABNORMAL;
+ }
+ /* Adjust mpu start address */
+ tmp_start_addr = mem_tbl[i].offset;
+ mem_tbl[i].offset += free_mem->length;
+ mem_tbl[i].offset &= MPU_64K_ALIGN_MASK;
+ mem_tbl[i].size = mem_tbl[i].size - (mem_tbl[i].offset - tmp_start_addr);
+ mem_tbl[i].ext_flag |= VALID_PADDING;
+ ALWAYS_LOG("[%p-Retrieve-%p|%p-Reserved-%p]\n",
+ mem_addr + free_mem->start_offset, mem_addr + mem_tbl[i].offset + mem_tbl[i].size -1,
+ mem_addr + mem_tbl[i].offset, mem_addr + mem_tbl[i].offset + mem_tbl[i].size - 1);
+ ccci_retrieve_mem((unsigned char*)(free_mem->start_offset + mem_addr), mem_tbl[i].offset - tmp_start_addr);
+ return 0;
+ }
+
+ if ((free_mem->start_offset + free_mem->length) < (mem_tbl[i].offset + mem_tbl[i].size)) {
+ /* case 1, need use one mpu region, seperate it to three part */
+ tmp_end_addr = mem_tbl[i].offset + mem_tbl[i].size -1;
+ mem_tbl[i].size = ((free_mem->start_offset + MPU_64K_VALUE - 1) & MPU_64K_ALIGN_MASK) - mem_tbl[i].offset;
+ tmp_start_addr = (free_mem->start_offset + free_mem->length) & MPU_64K_ALIGN_MASK;
+ if (((mem_tbl[i].size - mem_tbl[i].offset + 1) >= MPU_64K_VALUE) &&
+ ((tmp_end_addr - tmp_start_addr +1) >= MPU_64K_VALUE)) {
+ ALWAYS_LOG("[%p-Reserved-%p|%p-Retrieve-0%p|%p-Reserved-%p]\n",
+ mem_addr + mem_tbl[i].offset, mem_addr + mem_tbl[i].offset + mem_tbl[i].size -1,
+ mem_addr + mem_tbl[i].offset + mem_tbl[i].size, mem_addr + tmp_start_addr - 1,
+ mem_addr + tmp_start_addr, mem_addr + tmp_end_addr);
+ ccci_retrieve_mem((unsigned char*)(mem_tbl[i].offset + mem_tbl[i].size + mem_addr),
+ tmp_start_addr - (mem_tbl[i].offset + mem_tbl[i].size));
+ mem_tbl[mem_blk_num].offset = tmp_start_addr;
+ mem_tbl[mem_blk_num].size = tmp_end_addr - tmp_start_addr + 1;
+ mem_tbl[mem_blk_num].ext_flag = NEED_MPU_MORE|VALID_PADDING;
+ if (mem_tbl[i].relate_idx != 0)
+ mem_tbl[mem_blk_num].relate_idx = mem_tbl[i].relate_idx; /* Multiple - cut */
+ else {
+ mem_tbl[mem_blk_num].relate_idx = LOGIC_BINDING_IDX_START + i;
+ mem_tbl[i].relate_idx = LOGIC_BINDING_IDX_START + i;
+ }
+ mem_blk_num++;
+ }
+ return 1;
+ }
+
+ if ((free_mem->start_offset + free_mem->length) == (mem_tbl[i].offset + mem_tbl[i].size)) {
+ /* case 2, no need use one mpu region */
+ tmp_end_addr = mem_tbl[i].offset + mem_tbl[i].size - 1;
+ mem_tbl[i].size = ((free_mem->start_offset + MPU_64K_VALUE - 1) & MPU_64K_ALIGN_MASK) - mem_tbl[i].offset;
+ mem_tbl[i].ext_flag |= VALID_PADDING;
+ ALWAYS_LOG("[%p-Reserved-%p|%p-Retrieve-%p]\n",
+ mem_addr + mem_tbl[i].offset, mem_addr + mem_tbl[i].offset + mem_tbl[i].size -1,
+ mem_addr + mem_tbl[i].offset + mem_tbl[i].size, mem_addr + tmp_end_addr);
+ ccci_retrieve_mem((unsigned char*)(mem_addr + mem_tbl[i].offset + mem_tbl[i].size),
+ tmp_end_addr - (mem_tbl[i].offset + mem_tbl[i].size) + 1);
+ return 0;
+ }
+
+ if ((free_mem->start_offset + free_mem->length) > (mem_tbl[i].offset + mem_tbl[i].size)) {
+ ALWAYS_LOG("over two region\n");
+ return -LD_ERR_PAD_OVER_TWO_REGION;
+ }
+
+ return -LD_ERR_PAD_MISC;
+}
+
+static int padding_mem_pre_process_v5_hdr(struct image_section_desc mem_tbl[],
+ free_padding_block_t free_slot[], int mpu_num)
+{
+ int i, j;
+ int mem_blk_num = 0;
+ int padding_mem_num = 0;
+ free_padding_block_t *padding_mem;
+ struct padding_tag padding_tag_tbl[MAX_PADDING_NUM_V5_HDR+1], *small_ptr = NULL;
+ int padding_with_additional_num = 0;
+ unsigned int small_length = 0;
+
+ while (mem_tbl[mem_blk_num].offset || mem_tbl[mem_blk_num].size) {
+ PADDING_LOG("mem_tbl[mem_blk_num].offset:%x\n", mem_tbl[mem_blk_num].offset);
+ PADDING_LOG("mem_tbl[mem_blk_num].size:%x\n", mem_tbl[mem_blk_num].size);
+ mem_blk_num++;
+ }
+
+ PADDING_LOG("mem_blk_num:%d\n", mem_blk_num);
+
+ while (free_slot[padding_mem_num].start_offset || free_slot[padding_mem_num].length) {
+ padding_tag_tbl[padding_mem_num].padding_mem.start_offset = free_slot[padding_mem_num].start_offset;
+ padding_tag_tbl[padding_mem_num].padding_mem.length = free_slot[padding_mem_num].length;
+ padding_tag_tbl[padding_mem_num].status = VALID_PADDING;
+
+ PADDING_LOG("padding_tag_tbl[%d].offset:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].padding_mem.start_offset);
+ PADDING_LOG("padding_tag_tbl[%d].length:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].padding_mem.length);
+ PADDING_LOG("padding_tag_tbl[%d].status:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].status);
+
+ padding_mem_num++;
+ if (padding_mem_num >= MAX_PADDING_NUM_V5_HDR)
+ /* For current design, only have MAX_PADDING_NUM_V5_HDR number padding */
+ break;
+ }
+ for (i = padding_mem_num; i < (MAX_PADDING_NUM_V5_HDR+1); i++)
+ padding_tag_tbl[i].status = 0;
+
+ for (j = 0; j < padding_mem_num; j++) {
+ padding_mem = &padding_tag_tbl[j].padding_mem;
+ /* Find free memory position */
+ for (i = 0; i < mem_blk_num; i++) {
+ if ((padding_mem->start_offset >= mem_tbl[i].offset) &&
+ (padding_mem->start_offset < (mem_tbl[i].offset + mem_tbl[i].size)))
+ break;
+ }
+ if (i == mem_blk_num)
+ continue;
+
+ PADDING_LOG("padding_pre, get: offset:0x%x, size:0x%x\n",
+ padding_mem->start_offset, padding_mem->length);
+
+ if (padding_mem->start_offset == mem_tbl[i].offset) {
+ PADDING_LOG("case I\n");
+ continue;/* case 0, no need use one mpu region */
+ } else if ((padding_mem->start_offset + padding_mem->length) < (mem_tbl[i].offset + mem_tbl[i].size)) {
+ /* case 1, need use one mpu region, seperate it to three part */
+ padding_tag_tbl[j].status |= NEED_MPU_MORE;
+ padding_with_additional_num++;
+ PADDING_LOG("case II\n");
+ } else if ((padding_mem->start_offset + padding_mem->length) == (mem_tbl[i].offset + mem_tbl[i].size)) {
+ PADDING_LOG("case III\n");
+ continue;/* case 2, no need use one mpu region */
+ } else if ((padding_mem->start_offset + padding_mem->length) > (mem_tbl[i].offset + mem_tbl[i].size)) {
+ PADDING_LOG("case IV\n");
+ continue;/* over two region */
+ }
+ }
+ ALWAYS_LOG("padding_with_additional_num:%d with mpu_num:%d\n", padding_with_additional_num, mpu_num);
+
+ /* If mpu region not enough, remove the small padding memory part */
+ while (padding_with_additional_num > mpu_num) {
+ /* Find first tag that with additional region */
+ for (i = 0; i < (MAX_PADDING_NUM_V5_HDR + 1); i++) {
+ if (padding_tag_tbl[i].status & NEED_MPU_MORE) {
+ small_ptr = &padding_tag_tbl[i];
+ small_length = small_ptr->padding_mem.length;
+ break;
+ }
+ }
+
+ for (j = i; j < (MAX_PADDING_NUM_V5_HDR + 1); j++) {
+ /* Find the smallest padding with mpu */
+ if ((padding_tag_tbl[j].status & NEED_MPU_MORE) &&
+ (padding_tag_tbl[j].padding_mem.length < small_length)) {
+ small_ptr = &padding_tag_tbl[j];
+ small_length = small_ptr->padding_mem.length;
+ }
+ }
+ small_ptr->status |= NEED_REMOVE;
+ small_ptr->status &= (~NEED_MPU_MORE);
+ padding_mem_num--;
+ padding_with_additional_num--;
+ ALWAYS_LOG("MPU region not enough, cancel to retrieve padding(offset):0x%08x ~ 0x%08x\n",
+ small_ptr->padding_mem.start_offset,
+ small_ptr->padding_mem.start_offset+small_ptr->padding_mem.length);
+ }
+
+ /* Update final padding list
+ ** Remove smallest item, j always <= i */
+ j = 0;
+ for (i = 0; i < MAX_PADDING_NUM_V5_HDR ; i++) {
+ if (padding_tag_tbl[i].status & NEED_REMOVE)
+ continue;
+
+ free_slot[j].start_offset = padding_tag_tbl[i].padding_mem.start_offset;
+ free_slot[j].length = padding_tag_tbl[i].padding_mem.length;
+ j++;
+ }
+
+ free_slot[j].start_offset = 0;/* mark for new end */
+ free_slot[j].length = 0;/* mark for new end */
+
+ return padding_mem_num;
+}
+
+int retrieve_free_padding_mem_v5_hdr(modem_info_t *info,
+ struct image_section_desc mem_tbl[], void *hdr, int mpu_num)
+{
+ int i, j;
+ int retrieve_blk_num = 0;
+ struct md_check_header_v5 *chk_hdr = (struct md_check_header_v5 *)hdr;
+ int mem_blk_num = 0;
+ free_padding_block_t free_slot[MAX_PADDING_NUM_V5_HDR+1]; /* Maximux is 3, that confirned with MD */
+
+ if (mpu_num < 1) {
+ ALWAYS_LOG("free mpu region not enough for padding memory feature\n");
+ return -LD_ERR_PAD_REGION_NOT_ENOUGH;
+ }
+
+ j = 0;
+ for (i = 0; i < MAX_PADDING_NUM_V5_HDR; i++) {
+ if ((chk_hdr->padding_blk[i].start_offset == 0) &&
+ (chk_hdr->padding_blk[i].length == 0))
+ continue;
+ else {
+ free_slot[j].start_offset = chk_hdr->padding_blk[i].start_offset;
+ free_slot[j].length = chk_hdr->padding_blk[i].length;
+ j++;
+ }
+ }
+ free_slot[j].start_offset = 0; /* Mark for last */
+ free_slot[j].length = 0;
+
+ if (0 == j) {
+ ALWAYS_LOG("no free padding memmory to retrieve\n");
+ return -LD_ERR_PAD_NO_REGION_RETRIEVE;
+ }
+
+ /* Reserve 1 region for all range protect usage */
+ retrieve_blk_num = padding_mem_pre_process_v5_hdr(mem_tbl, free_slot, mpu_num - 1);
+
+ /* Calculate mem_tbl number again */
+ mem_blk_num = 0;
+ while (mem_tbl[mem_blk_num].offset || mem_tbl[mem_blk_num].size)
+ mem_blk_num++;
+
+ ALWAYS_LOG("retrieve_blk_num: %d\n", retrieve_blk_num);
+
+ for (i = 0; i < retrieve_blk_num; i++) {
+ if (free_padding_mem_blk_match(info, mem_tbl, mem_blk_num, &free_slot[i]) > 0)
+ mem_blk_num++;
+ }
+
+ /* Add lowest padding mpu setting to avoid prefetch violation */
+ mem_tbl[mem_blk_num].offset = 0;
+ mem_tbl[mem_blk_num].size = chk_hdr->common.mem_size;
+ mem_tbl[mem_blk_num].mpu_attr = 0xFFFFFFFF;
+ mem_tbl[mem_blk_num].ext_flag = MD_ALL_RANGE;
+ mem_tbl[mem_blk_num].relate_idx = 0;
+
+ /* Mark for end */
+ mem_blk_num++;
+ mem_tbl[mem_blk_num].offset = 0;
+ mem_tbl[mem_blk_num].size = 0;
+
+ return 0;
+}
+
+static int padding_mem_pre_process_v6_hdr(struct image_section_desc mem_tbl[],
+ free_padding_block_t free_slot[], int mpu_num)
+{
+ int i, j;
+ int mem_blk_num = 0;
+ int padding_mem_num = 0;
+ free_padding_block_t *padding_mem;
+ struct padding_tag padding_tag_tbl[MAX_PADDING_NUM_V6_HDR+1], *small_ptr = NULL;
+ int padding_with_additional_num = 0;
+ unsigned int small_length = 0;
+
+ while (mem_tbl[mem_blk_num].offset || mem_tbl[mem_blk_num].size) {
+ PADDING_LOG("mem_tbl[%d].offset:%x\n", mem_blk_num, mem_tbl[mem_blk_num].offset);
+ PADDING_LOG("mem_tbl[%d].size:%x\n", mem_blk_num, mem_tbl[mem_blk_num].size);
+ mem_blk_num++;
+ }
+
+ PADDING_LOG("mem_blk_num:%d\n", mem_blk_num);
+
+ while (free_slot[padding_mem_num].start_offset || free_slot[padding_mem_num].length) {
+ padding_tag_tbl[padding_mem_num].padding_mem.start_offset = free_slot[padding_mem_num].start_offset;
+ padding_tag_tbl[padding_mem_num].padding_mem.length = free_slot[padding_mem_num].length;
+ padding_tag_tbl[padding_mem_num].status = VALID_PADDING;
+
+ PADDING_LOG("padding_tag_tbl[%d].offset:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].padding_mem.start_offset);
+ PADDING_LOG("padding_tag_tbl[%d].length:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].padding_mem.length);
+ PADDING_LOG("padding_tag_tbl[%d].status:0x%x\n", padding_mem_num,
+ padding_tag_tbl[padding_mem_num].status);
+
+ padding_mem_num++;
+ if (padding_mem_num >= MAX_PADDING_NUM_V6_HDR)
+ /* For current design, only have MAX_PADDING_NUM_V6_HDR number padding */
+ break;
+ }
+ for (i = padding_mem_num; i < (MAX_PADDING_NUM_V6_HDR+1); i++)
+ padding_tag_tbl[i].status = 0;
+
+ for (j = 0; j < padding_mem_num; j++) {
+ padding_mem = &padding_tag_tbl[j].padding_mem;
+ /* Find free memory position */
+ for (i = 0; i < mem_blk_num; i++) {
+ if ((padding_mem->start_offset >= mem_tbl[i].offset) &&
+ (padding_mem->start_offset < (mem_tbl[i].offset + mem_tbl[i].size)))
+ break;
+ }
+ if (i == mem_blk_num)
+ continue;
+
+ PADDING_LOG("padding_pre, get: offset:0x%x, size:0x%x\n",
+ padding_mem->start_offset, padding_mem->length);
+
+ if (padding_mem->start_offset == mem_tbl[i].offset) {
+ PADDING_LOG("case I\n");
+ continue;/* case 0, no need use one mpu region */
+ } else if ((padding_mem->start_offset + padding_mem->length) < (mem_tbl[i].offset + mem_tbl[i].size)) {
+ /* case 1, need use one mpu region, seperate it to three part */
+ padding_tag_tbl[j].status |= NEED_MPU_MORE;
+ padding_with_additional_num++;
+ PADDING_LOG("case II\n");
+ } else if ((padding_mem->start_offset + padding_mem->length) == (mem_tbl[i].offset + mem_tbl[i].size)) {
+ PADDING_LOG("case III\n");
+ continue;/* case 2, no need use one mpu region */
+ } else if ((padding_mem->start_offset + padding_mem->length) > (mem_tbl[i].offset + mem_tbl[i].size)) {
+ PADDING_LOG("case IV\n");
+ continue;/* over two region */
+ }
+ }
+ ALWAYS_LOG("padding_with_additional_num:%d with mpu_num:%d\n", padding_with_additional_num, mpu_num);
+
+ /* If mpu region not enough, remove the small padding memory part */
+ while (padding_with_additional_num > mpu_num) {
+ /* Find first tag that with additional region */
+ for (i = 0; i < (MAX_PADDING_NUM_V6_HDR + 1); i++) {
+ if (padding_tag_tbl[i].status & NEED_MPU_MORE) {
+ small_ptr = &padding_tag_tbl[i];
+ small_length = small_ptr->padding_mem.length;
+ break;
+ }
+ }
+
+ for (j = i; j < (MAX_PADDING_NUM_V6_HDR + 1); j++) {
+ /* Find the smallest padding with mpu */
+ if ((padding_tag_tbl[j].status & NEED_MPU_MORE) &&
+ (padding_tag_tbl[j].padding_mem.length < small_length)) {
+ small_ptr = &padding_tag_tbl[j];
+ small_length = small_ptr->padding_mem.length;
+ }
+ }
+ small_ptr->status |= NEED_REMOVE;
+ small_ptr->status &= (~NEED_MPU_MORE);
+ padding_mem_num--;
+ padding_with_additional_num--;
+ ALWAYS_LOG("MPU region not enough, cancel to retrieve padding(offset):0x%08x ~ 0x%08x\n",
+ small_ptr->padding_mem.start_offset,
+ small_ptr->padding_mem.start_offset+small_ptr->padding_mem.length);
+ }
+
+ /* Update final padding list
+ ** Remove smallest item, j always <= i */
+ j = 0;
+ for (i = 0; i < MAX_PADDING_NUM_V6_HDR ; i++) {
+ if (padding_tag_tbl[i].status & NEED_REMOVE)
+ continue;
+
+ free_slot[j].start_offset = padding_tag_tbl[i].padding_mem.start_offset;
+ free_slot[j].length = padding_tag_tbl[i].padding_mem.length;
+ j++;
+ }
+
+ free_slot[j].start_offset = 0;/* mark for new end */
+ free_slot[j].length = 0;/* mark for new end */
+
+ return padding_mem_num;
+}
+
+int retrieve_free_padding_mem_v6_hdr(modem_info_t *info,
+ struct image_section_desc mem_tbl[], void *hdr, int mpu_num)
+{
+ int i, j;
+ int retrieve_blk_num = 0;
+ struct md_check_header_v6 *chk_hdr = (struct md_check_header_v6 *)hdr;
+ int mem_blk_num = 0;
+ free_padding_block_t free_slot[MAX_PADDING_NUM_V6_HDR+1]; /* Maximux is 8, that confirned with MD */
+
+ if (mpu_num < 1) {
+ ALWAYS_LOG("free mpu region not enough for padding memory feature\n");
+ return -LD_ERR_PAD_REGION_NOT_ENOUGH;
+ }
+
+ j = 0;
+ for (i = 0; i < MAX_PADDING_NUM_V6_HDR; i++) {
+ if ((chk_hdr->padding_blk[i].start_offset == 0) &&
+ (chk_hdr->padding_blk[i].length == 0))
+ continue;
+ else {
+ free_slot[j].start_offset = chk_hdr->padding_blk[i].start_offset;
+ free_slot[j].length = chk_hdr->padding_blk[i].length;
+ j++;
+ }
+ }
+ free_slot[j].start_offset = 0; /* Mark for last */
+ free_slot[j].length = 0;
+
+ if (0 == j) {
+ ALWAYS_LOG("no free padding memmory to retrieve\n");
+ return -LD_ERR_PAD_NO_REGION_RETRIEVE;
+ }
+
+ /* Reserve 1 region for all range protect usage */
+ retrieve_blk_num = padding_mem_pre_process_v6_hdr(mem_tbl, free_slot, mpu_num - 1);
+
+ /* Calculate mem_tbl number again */
+ mem_blk_num = 0;
+ while (mem_tbl[mem_blk_num].offset || mem_tbl[mem_blk_num].size)
+ mem_blk_num++;
+
+ ALWAYS_LOG("retrieve_blk_num: %d\n", retrieve_blk_num);
+
+ for (i = 0; i < retrieve_blk_num; i++) {
+ if (free_padding_mem_blk_match(info, mem_tbl, mem_blk_num, &free_slot[i]) > 0)
+ mem_blk_num++;
+ }
+
+ /* Add DRDI mpu setting if need */
+ if ((chk_hdr->drdi_rt_offset != 0) && (chk_hdr->drdi_rt_size != 0)) {
+ mem_tbl[mem_blk_num].offset = chk_hdr->drdi_rt_offset;
+ mem_tbl[mem_blk_num].size = chk_hdr->drdi_rt_size;
+ mem_tbl[mem_blk_num].mpu_attr = 0xFFFFFFFF;
+ mem_tbl[mem_blk_num].ext_flag = MD_DRDI_REGION;
+ mem_tbl[mem_blk_num].relate_idx = 0;
+ mem_blk_num++;
+ }
+
+ /* Add lowest padding mpu setting to avoid prefetch violation */
+ mem_tbl[mem_blk_num].offset = 0;
+ mem_tbl[mem_blk_num].size = chk_hdr->common.mem_size;
+ mem_tbl[mem_blk_num].mpu_attr = 0xFFFFFFFF;
+ mem_tbl[mem_blk_num].ext_flag = MD_ALL_RANGE;
+ mem_tbl[mem_blk_num].relate_idx = 0;
+
+ /* Mark for end */
+ mem_blk_num++;
+ mem_tbl[mem_blk_num].offset = 0;
+ mem_tbl[mem_blk_num].size = 0;
+
+ return 0;
+}
+
+int retrieve_info_num;
+void log_retrieve_info(unsigned char *addr, int size)
+{
+ char buf[32];
+ u64 array[2];
+ array[0] = (u64)((unsigned long)addr);
+ array[1] = (u64)size;
+ snprintf(buf, 32, "retrieve%d", retrieve_info_num);
+
+#ifdef TELE_CCCI_SUPPORT
+ keep_md_image_retrieve_memory((unsigned long)addr, size);
+#endif
+
+ if (insert_ccci_tag_inf(buf, (char*)&array, sizeof(array)) < 0)
+ ALWAYS_LOG("insert %s fail\n", buf);
+
+ retrieve_info_num++;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_sec.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_sec.c
new file mode 100644
index 0000000..c8775b8
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_sec.c
@@ -0,0 +1,189 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#include <assert.h>
+#include <platform/mtk_wdt.h>
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#include <platform.h>
+#include "sec_boot.h"
+#else
+#include <platform/errno.h>
+#include <video.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#include <platform/sec_export.h>
+#include <block_generic_interface.h>
+#include <verified_boot_common.h>
+#include <platform/verified_boot.h>
+#endif
+#define MODULE_NAME "LK_LD_MD"
+
+/* Security policy */
+#ifdef MTK_SECURITY_SW_SUPPORT
+static unsigned int verify_hash;
+static unsigned int lte_sbc_en;
+static unsigned int c2k_sbc_en;
+static int time_md_auth;
+static int time_md_auth_init;
+static unsigned int sec_feature_mask;
+static int g_fill_default_pubk_hash = 0;
+#endif
+
+extern uint32_t sec_get_ltemd_sbcen(void);
+extern uint32_t sec_get_c2kmd_sbcen(void);
+extern uint32_t sec_md_sbcen_init(void);
+
+void ccci_ld_md_sec_init(void)
+{
+#ifdef MTK_SECURITY_SW_SUPPORT
+ sec_md_sbcen_init();
+ verify_hash = 0;
+ lte_sbc_en = sec_get_ltemd_sbcen();
+ c2k_sbc_en = sec_get_c2kmd_sbcen();
+ sec_feature_mask = 0;
+#endif
+}
+
+int ccci_ld_md_sec_ptr_hdr_verify(const char *partition_name, const char *image_name)
+{
+ int ret = 0;
+
+ if (!strncmp((char const *)image_name, "md1drdi",8)) {
+ return ret;
+ }
+
+ ALWAYS_LOG("ptr hdr verify:partition[%s], image_name[%s]\n", partition_name, image_name);
+
+ /* Check sec policy to see if verification is required */
+#ifdef MTK_SECURITY_SW_SUPPORT
+ /* do verify md cert-chain if need */
+#ifdef TELE_CCCI_SUPPORT
+ time_md_auth_init = current_time();
+#else
+ time_md_auth_init = get_timer(0);
+#endif
+#ifdef MTK_SECURITY_ANTI_ROLLBACK
+ sec_feature_mask |= SEC_FEATURE_MASK_ANTIROLLBACK;
+#endif
+ ret = sec_img_auth_init((char *)partition_name, (char *)image_name, sec_feature_mask);
+
+ if (0 != ret) {
+ ALWAYS_LOG("img cert-chain verification fail: 0x%x\n", ret);
+ return ret;
+ }
+#ifdef MTK_SECURITY_ANTI_ROLLBACK
+ ret = sec_rollback_check(1);
+ if (0 != ret) {
+ ALWAYS_LOG("Verify %s image version fail!!!!\n", image_name);
+ return ret;
+ }
+#endif
+#ifdef TELE_CCCI_SUPPORT
+ ALWAYS_LOG("Verify %s cert chain cost %d ms\n", image_name, (int)(current_time() - (time_md_auth_init)));
+#else
+ ALWAYS_LOG("Verify %s cert chain cost %d ms\n", image_name, (int)get_timer(time_md_auth_init));
+#endif
+
+#endif
+
+ if (ret == 0)
+ return 0;
+ else
+ return -1;
+}
+
+
+int ccci_ld_md_sec_image_verify(const char *partition_name, const char *image_name, unsigned char *mem_addr, int size)
+{
+ int ret = 0;
+
+ if (!strncmp((char const *)image_name, "md1drdi",8)) {
+ return ret;
+ }
+
+ ALWAYS_LOG("image verify:partition[%s], image_name[%s], addr[%p], size[0x%x]\n",
+ partition_name, image_name, mem_addr, size);
+
+#ifdef MTK_SECURITY_SW_SUPPORT
+ /* Verify md image hash value */
+ /* When SBC_EN is fused, bypass sec_img_auth */
+ verify_hash = 1;
+
+ if (!strncmp((char const *)image_name, "md1rom",7)) {
+ if (0x01 == lte_sbc_en) {
+ ALWAYS_LOG("LTE now, and lte sbc en = 0x1 \n");
+ /* Bypass image hash verification at AP side*/
+ verify_hash = 0;
+ } else
+ ALWAYS_LOG("LTE now, and lte sbc en != 0x1 \n");
+ }
+ if (!strncmp((char const *)image_name, "md3rom",7)) {
+ if (0x01 == c2k_sbc_en) {
+ ALWAYS_LOG("C2K now, and c2k sbc en = 0x1 \n");
+ /* Bypass image hash verification at AP side*/
+ verify_hash = 0;
+ } else
+ ALWAYS_LOG("C2K now, and c2k sbc en != 0x1 \n");
+ }
+ if (1 == verify_hash) {
+#ifdef TELE_CCCI_SUPPORT
+ time_md_auth = current_time();
+#else
+ time_md_auth = get_timer(0);
+#endif
+ ret = sec_img_auth(mem_addr, size);
+ if (0 != ret) {
+ ALWAYS_LOG("image hash verification fail: %d\n", ret);
+ return ret;
+ }
+ ALWAYS_LOG("Image hash verification success: ret = %d\n", ret);
+#ifdef TELE_CCCI_SUPPORT
+ ALWAYS_LOG("Verify %s image hash cost %d ms\n", image_name, (int)(current_time() - (time_md_auth)));
+#else
+ ALWAYS_LOG("Verify %s image hash cost %d ms\n", image_name, (int)get_timer(time_md_auth));
+#endif
+ }
+#endif
+ return ret;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tag_dt.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tag_dt.c
new file mode 100644
index 0000000..3a2f900
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tag_dt.c
@@ -0,0 +1,482 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#ifdef CCCI_MD_TAG_INFO
+#include "ccci_ld_md_errno.h"
+#ifdef TELE_CCCI_SUPPORT
+#include <assert.h>
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/mt_gpt.h>
+#include <platform/boot_mode.h>
+#endif
+#define MODULE_NAME "LK_LD_MD"
+
+/***************************************************************************************************
+** Sub module: ccci_lk_info (LK to Kernel arguments and information)
+** Using share memory and device tree
+** ccci_lk_info structure is stored at device tree
+** other more detail parameters are stored at share memory
+***************************************************************************************************/
+typedef struct _ccci_lk_info {
+ unsigned long long lk_info_base_addr;
+ unsigned int lk_info_size;
+ int lk_info_err_no;
+ int lk_info_version;
+ int lk_info_tag_num;
+ unsigned int lk_info_ld_flag;
+ int lk_info_ld_md_errno[MAX_MD_NUM];
+} ccci_lk_info_t;
+
+#define TAG_MAX_LK_INFO_SIZE (0x10000)
+#define CCCI_TAG_NAME_LEN (64)
+#ifdef TELE_CCCI_SUPPORT
+#define CCCI_LK_INFO_VER (2)
+#else
+#define CCCI_LK_INFO_VER (3) /* 1/2- ap-md share memory re-use, _ccci_lk_info+_v2 */
+#endif
+typedef struct _ccci_tag {
+ char tag_name[CCCI_TAG_NAME_LEN];
+ unsigned int data_offset;
+ unsigned int data_size;
+ unsigned int next_tag_offset;
+} ccci_tag_t;
+
+static ccci_lk_info_t s_g_ccci_lk_inf;
+
+int ccci_lk_tag_info_init(unsigned long long base_addr)
+{
+ int i;
+ unsigned char *mem_addr;
+
+ mem_addr = resv_named_memory("ccci_tag_mem", TAG_MAX_LK_INFO_SIZE);
+ if (mem_addr == NULL) {
+ ALWAYS_LOG("allocate tag memory fail\n");
+ return -1;
+ }
+
+ s_g_ccci_lk_inf.lk_info_base_addr = (unsigned long long)(unsigned long)mem_addr;
+ s_g_ccci_lk_inf.lk_info_size = 0;
+ s_g_ccci_lk_inf.lk_info_tag_num = 0;
+ s_g_ccci_lk_inf.lk_info_version = CCCI_LK_INFO_VER;
+ s_g_ccci_lk_inf.lk_info_ld_flag = 0;
+ s_g_ccci_lk_inf.lk_info_err_no = 0;
+ for (i=0; i < MAX_MD_NUM; i++)
+ s_g_ccci_lk_inf.lk_info_ld_md_errno[i] = 0;
+ return 0;
+}
+
+void ccci_lk_info_re_cfg(unsigned long long base_addr, unsigned int size)
+{
+ s_g_ccci_lk_inf.lk_info_base_addr = base_addr;
+ s_g_ccci_lk_inf.lk_info_size = size;
+}
+
+void update_common_err_to_lk_info(int error)
+{
+ s_g_ccci_lk_inf.lk_info_err_no = error;
+}
+
+void update_md_err_to_lk_info(int md_id, int error)
+{
+ s_g_ccci_lk_inf.lk_info_ld_md_errno[md_id] = error;
+}
+
+int get_md_err_from_lk_info(int md_id)
+{
+ return s_g_ccci_lk_inf.lk_info_ld_md_errno[md_id];
+}
+
+void update_md_load_flag_to_lk_info(int md_id)
+{
+ s_g_ccci_lk_inf.lk_info_ld_flag |= (1<<md_id);
+}
+
+int insert_ccci_tag_inf(const char *name, char *data, unsigned int size)
+{
+ int i;
+ unsigned int curr_offset = s_g_ccci_lk_inf.lk_info_size;
+ ccci_tag_t *tag = (ccci_tag_t *)((unsigned long)(s_g_ccci_lk_inf.lk_info_base_addr + curr_offset));
+ char* buf = (char *)((unsigned long)(s_g_ccci_lk_inf.lk_info_base_addr + curr_offset + sizeof(ccci_tag_t)));
+ int total_size = (curr_offset + size + sizeof(ccci_tag_t) + 7)&(~7); /* make sure 8 bytes align */
+
+ if (size == 0){
+ ALWAYS_LOG("tag info size is 0\n");
+ return 0;
+ }
+
+ if (total_size >= TAG_MAX_LK_INFO_SIZE) {
+ ALWAYS_LOG("not enought memory to insert(%d)\n", TAG_MAX_LK_INFO_SIZE - total_size);
+ return -LD_ERR_TAG_BUF_FULL;
+ }
+
+ /* Copy name */
+ for (i=0; i<CCCI_TAG_NAME_LEN-1; i++) {
+ if (name[i] == 0)
+ break;
+
+ tag->tag_name[i] = name[i];
+ }
+ tag->tag_name[i] = 0;
+
+ /* Set offset */
+ tag->data_offset = curr_offset + sizeof(ccci_tag_t);
+ /* Set data size */
+ tag->data_size = size;
+ /* Set next offset */
+ tag->next_tag_offset = total_size;
+ /* Copy data */
+ memcpy(buf, data, size);
+
+ /* update control structure */
+ s_g_ccci_lk_inf.lk_info_size = total_size;
+ s_g_ccci_lk_inf.lk_info_tag_num++;
+
+ TAG_DBG_LOG("tag insert(%d), [name]:%s [4 bytes]:[%x][%x][%x][%x] [size]:%d\n",
+ s_g_ccci_lk_inf.lk_info_tag_num, name, data[0], data[1], data[2], data[3], size);
+
+ return 0;
+}
+
+void ccci_lk_info_ctl_dump(void)
+{
+ ALWAYS_LOG("lk info.lk_info_base_addr: 0x%llx\n", s_g_ccci_lk_inf.lk_info_base_addr);
+ ALWAYS_LOG("lk info.lk_info_size: 0x%x\n", s_g_ccci_lk_inf.lk_info_size);
+ ALWAYS_LOG("lk info.lk_info_tag_num: 0x%x\n", s_g_ccci_lk_inf.lk_info_tag_num);
+}
+
+static int dt_reserve_mem_size_fixup(void *fdt)
+{
+ if (plat_dt_reserve_mem_size_fixup)
+ plat_dt_reserve_mem_size_fixup(fdt);
+
+ return 0;
+}
+/*
+** This function will using globle variable: s_g_ccci_lk_inf;
+** and a weak function will be called: md_reserve_mem_size_fixup
+**/
+unsigned int *update_lk_arg_info_to_dt(unsigned int *ptr, void *fdt)
+{
+ unsigned int i;
+ unsigned int *local_ptr;
+ unsigned int size = sizeof(ccci_lk_info_t)/sizeof(unsigned int);
+
+ local_ptr = (unsigned int *)&s_g_ccci_lk_inf;
+ for (i = 0; i < size; i++) {
+ *ptr = local_ptr[i];
+ ptr++;
+ }
+
+ /* update kernel dt if needed, most platform code do nothing */
+ dt_reserve_mem_size_fixup(fdt);
+
+ return ptr;
+}
+#ifdef TELE_CCCI_SUPPORT
+
+/* Device tree related */
+#define MD_CACHE_RESERVE_NODENAME "reserve-memory-mdcache"
+#define MD_CACHE_RESERVE_COMPATIBLE "mediatek,reserve-memory-mdcache"
+
+#define MD_NCACHE_RESERVE_NODENAME "reserve-memory-mdncache"
+#define MD_NCACHE_RESERVE_COMPATIBLE "mediatek,reserve-memory-mdncache"
+
+#define MD_IMAGE_RESERVE_NODENAME_PREFIX "reserve-memory-mdimage"
+#define MD_IMAGE_RESERVE_COMPATIBLE_PREFIX "mediatek,reserve-memory-mdimage"
+
+#define MD_NODE_COMPATIBLE_PROP "compatible"
+#define MD_NODE_ARRTIBUTE_PROP "no-map"
+#define MD_NODE_RANGE_PROP "reg"
+
+#define MD_IMAGE_MAX_RETRIEVE_COUNT 7
+
+typedef struct {
+ unsigned int start_address;
+ unsigned int end_address;
+} md_img_region_t;
+
+static md_img_region_t retrieve_memory_region[MD_IMAGE_MAX_RETRIEVE_COUNT];
+
+static int md_image_retrieve_count = 0;
+
+static unsigned int share_mem_cache_addr = 0;
+static unsigned int share_mem_cache_size = 0;
+static unsigned int share_mem_ncache_addr = 0;
+static unsigned int share_mem_ncache_size = 0;
+
+/*
+** This function will keep the address and size of retrieve memory.
+** Note: the address should be incremental, and size shouldn't overlay.
+ */
+void keep_md_image_retrieve_memory(unsigned long long address, unsigned int size)
+{
+ int i, j;
+ unsigned int entry_pa;
+ unsigned int valid_start, valid_end;
+
+ /* debug */
+ DBG_LOG("[ccci] retrieve addr 0x%x, size 0x%x, index %d\n", (unsigned int)address, size, md_image_retrieve_count);
+
+ ASSERT(md_image_retrieve_count < MD_IMAGE_MAX_RETRIEVE_COUNT);
+
+ /* entry_pa is 32-bit */
+ entry_pa = kvaddr_to_paddr((void *)address);
+
+ /* sorting by address */
+ /* use linear search due to data amount is few. */
+ for (i=0; i<md_image_retrieve_count; i++) {
+ if (entry_pa < retrieve_memory_region[i].start_address)
+ break;
+ }
+ /* move the data */
+ if (i != md_image_retrieve_count) {
+ for (j=md_image_retrieve_count; j>i; j--) {
+ memcpy( &retrieve_memory_region[j], &retrieve_memory_region[j-1], sizeof(md_img_region_t));
+ }
+ }
+
+ /* get valid range */
+ if (i == 0) {
+ valid_start = MD_ADDR;
+ } else {
+ valid_start = retrieve_memory_region[i-1].end_address;
+ }
+ if (i == md_image_retrieve_count) {
+ valid_end = MD_ADDR + MAX_MD_SIZE;
+ } else {
+ valid_end = retrieve_memory_region[i+1].start_address;
+ }
+
+ /* check range */
+ ASSERT(entry_pa >= valid_start);
+ ASSERT(entry_pa+size <= valid_end);
+
+ /* recode the entry */
+ retrieve_memory_region[i].start_address = entry_pa;
+ retrieve_memory_region[i].end_address = entry_pa+size;
+
+ md_image_retrieve_count++;
+}
+
+/*
+** This function will write a reserve-memory to device tree.
+ */
+static int write_reserve_memory_to_dt(void *fdt_dtb, unsigned int addr, unsigned int size, const char *node_name, const char *compatible_name)
+{
+ int parsent_node, img_node;
+ int ret;
+ fdt32_t range[4];
+
+ /* debug */
+ DBG_LOG("[ccci] DT reserve addr 0x%x, size 0x%x\n", (unsigned int)addr, size);
+
+ /* early skip */
+ if (size == 0)
+ return 0;
+
+ /* Find out reserved-memory */
+ parsent_node = fdt_path_offset(fdt_dtb, "/reserved-memory");
+ if (parsent_node < 0) {
+ CRITICAL_LOG("%s failed: %s\n", __func__, "fdt_path_offset");
+ ASSERT(0);
+ return parsent_node;
+ }
+
+ /* To add a new subnode */
+ img_node = fdt_add_subnode(fdt_dtb, parsent_node, node_name);
+ if (img_node < 0) {
+ CRITICAL_LOG("%s failed: %s\n", __func__, "fdt_add_subnode");
+ return img_node;
+ }
+
+ range[0] = range[2] = 0;
+ range[1] = cpu_to_fdt32(addr);
+ range[3] = cpu_to_fdt32(size);
+ ret = fdt_setprop(fdt_dtb, img_node, MD_NODE_RANGE_PROP, range, sizeof(range));
+ if (ret)
+ return ret;
+
+ /*for mdimage itself, we should mapped for AMMS-DRDI*/
+ if (strncmp("reserve-memory-mdimage", node_name, strlen("reserve-memory-mdimage")) != 0) {
+ DBG_LOG("%s %s no-map\n", __func__, node_name);
+ ret = fdt_setprop(fdt_dtb, img_node, MD_NODE_ARRTIBUTE_PROP, NULL, 0);
+ if (ret)
+ return ret;
+ }
+
+ ret = fdt_setprop_string(fdt_dtb, img_node, MD_NODE_COMPATIBLE_PROP, compatible_name);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+** This function will transfrom the retrieve memory into reserved memory.
+** Then write to device tree.
+ */
+static void reserve_md_image_handler(void *fdt_dtb)
+{
+ int i;
+ unsigned int size, reserve_start, reserve_end;
+ char node_name[30];
+ char compatible_name[40];
+
+ reserve_start = MD_ADDR;
+ for (i=0; i<md_image_retrieve_count; i++) {
+ /* set node name */
+ snprintf(node_name, sizeof(node_name), "%s%d", MD_IMAGE_RESERVE_NODENAME_PREFIX, i);
+ snprintf(compatible_name, sizeof(compatible_name), "%s%d", MD_IMAGE_RESERVE_COMPATIBLE_PREFIX, i);
+
+ reserve_end = retrieve_memory_region[i].start_address;
+
+ /* write to device tree */
+ size = reserve_end - reserve_start;
+ write_reserve_memory_to_dt(fdt_dtb, reserve_start, size, node_name, compatible_name);
+
+ reserve_start = retrieve_memory_region[i].end_address;
+ }
+ reserve_end = MD_ADDR + MAX_MD_SIZE;
+
+ /* set node name */
+ snprintf(node_name, sizeof(node_name), "%s%d", MD_IMAGE_RESERVE_NODENAME_PREFIX, i);
+ snprintf(compatible_name, sizeof(compatible_name), "%s%d", MD_IMAGE_RESERVE_COMPATIBLE_PREFIX, i);
+
+ /* write to device tree */
+ size = reserve_end - reserve_start;
+ write_reserve_memory_to_dt(fdt_dtb, reserve_start, size, node_name, compatible_name);
+}
+
+/*
+** This function will keep the address and size of cacheable and noncacheable.
+ */
+void keep_md_cache_memory(unsigned long long address, unsigned int size)
+{
+ share_mem_cache_addr = (unsigned int)address; // has been physical address
+ share_mem_cache_size = size;
+}
+
+void keep_md_ncache_memory(unsigned long long address, unsigned int size)
+{
+ share_mem_ncache_addr = kvaddr_to_paddr((void *)address);
+ share_mem_ncache_size = size;
+}
+
+/*
+** This function will write the reserved memory into device tree.
+ */
+static void reserve_md_ncache_handler(void *fdt_dtb)
+{
+ write_reserve_memory_to_dt(fdt_dtb, share_mem_ncache_addr, share_mem_ncache_size, MD_NCACHE_RESERVE_NODENAME, MD_NCACHE_RESERVE_COMPATIBLE);
+}
+
+static void reserve_md_cache_handler(void *fdt_dtb)
+{
+ write_reserve_memory_to_dt(fdt_dtb, share_mem_cache_addr, share_mem_cache_size, MD_CACHE_RESERVE_NODENAME, MD_CACHE_RESERVE_COMPATIBLE);
+}
+
+/*
+** This function will using globle variable: s_g_ccci_lk_inf;
+** and a weak function will be called: md_reserve_mem_size_fixup
+**/
+int ccci_update_md_arg_info_to_dt(void *boot_dtb)
+{
+ int chosen_node_offset = 0;
+ char *ptr = (char *)&s_g_ccci_lk_inf;
+ int ret = 0;
+
+ chosen_node_offset = fdt_path_offset(boot_dtb, "/chosen");
+#if WITH_KERNEL_VM
+ s_g_ccci_lk_inf.lk_info_base_addr =
+ kvaddr_to_paddr((void *)s_g_ccci_lk_inf.lk_info_base_addr);
+#endif
+
+ ret = fdt_setprop(boot_dtb, chosen_node_offset,
+ "ccci,modem_info_v2", ptr, sizeof(ccci_lk_info_t) + 1);
+ if (ret != 0) {
+ CRITICAL_LOG("[ccci] create modem arguments info DT Fail\n");
+ return -1;
+ }
+ CRITICAL_LOG("[ccci] create modem arguments info FDT OK\n");
+
+ /* write reserve-memory into device tree */
+ reserve_md_image_handler(boot_dtb);
+ reserve_md_ncache_handler(boot_dtb);
+ reserve_md_cache_handler(boot_dtb);
+ ALWAYS_LOG("[ccci] write reserve-memory into DT OK\n");
+
+ return ret;
+}
+
+#endif
+#else
+int insert_ccci_tag_inf(const char *name, char *data, unsigned int size)
+{
+ return 0;
+}
+int ccci_lk_tag_info_init(unsigned long long base_addr)
+{
+ return 0;
+}
+void ccci_lk_info_ctl_dump(void)
+{
+}
+void update_md_err_to_lk_info(int md_id, int error)
+{
+}
+
+int get_md_err_from_lk_info(int md_id)
+{
+ return 0;
+}
+void update_md_load_flag_to_lk_info(int md_id)
+{
+}
+void update_common_err_to_lk_info(int error)
+{
+}
+void ccci_lk_info_re_cfg(unsigned long long base_addr, unsigned int size)
+{
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.c
new file mode 100644
index 0000000..d7174d0
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.c
@@ -0,0 +1,850 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <debug.h>
+#include "ccci_ld_md_core.h"
+#ifdef LK_MD_TEL_SUPPORT
+#include "ccci_ld_md_errno.h"
+#include <lk_load_md_wrapper.h>
+#ifdef TELE_CCCI_SUPPORT
+#include <errno.h>
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#endif
+
+#define MODULE_NAME "LK_LD_MD"
+
+/***************************************************************************************************
+** Sub section:
+** Telephony operation parsing and prepare part
+***************************************************************************************************/
+/* For the following option setting, please check config.h after build, or $project.mk */
+#ifdef MTK_C2K_LTE_MODE
+#define C2K_LTE_MODE (MTK_C2K_LTE_MODE)
+#else
+#define C2K_LTE_MODE (0)
+#endif
+
+#ifdef MTK_PROTOCOL1_RAT_CONFIG
+#define PS1_RAT_DEFAULT MTK_PROTOCOL1_RAT_CONFIG
+#else
+#define PS1_RAT_DEFAULT ""
+#endif
+
+static char *get_lk_ro_env_str(char *name)
+{
+ char *(*NULL_FP)(char *) = 0;
+
+ if (NULL_FP == get_ro_env) {
+ ALWAYS_LOG("dummy get_ro_env\n");
+ return NULL;
+ }
+
+ return get_ro_env(name);
+}
+
+/* Legacy capability table */
+#define LEGACY_UBIN_START_ID (8)
+static const unsigned int legacy_ubin_rat_map[] = {
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ultg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_GSM), /* ulwg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ulwtg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_CDMA2000|MD_CAP_GSM), /* ulwcg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_CDMA2000|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ulwctg */
+ (MD_CAP_TDD_LTE|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ulttg */
+ (MD_CAP_FDD_LTE|MD_CAP_WCDMA|MD_CAP_GSM), /* ulfwg */
+ (MD_CAP_FDD_LTE|MD_CAP_WCDMA|MD_CAP_CDMA2000|MD_CAP_GSM), /* ulfwcg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDD_LTE|MD_CAP_CDMA2000|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ulctg */
+ (MD_CAP_TDD_LTE|MD_CAP_CDMA2000|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ultctg */
+ (MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_GSM), /*ultwg */
+ (MD_CAP_TDD_LTE|MD_CAP_WCDMA|MD_CAP_CDMA2000|MD_CAP_GSM), /* ultwcg */
+ (MD_CAP_FDD_LTE|MD_CAP_TDS_CDMA|MD_CAP_GSM), /* ulftg */
+ (MD_CAP_FDD_LTE|MD_CAP_CDMA2000|MD_CAP_TDS_CDMA|MD_CAP_GSM)/* ulfctg */
+};
+
+/* Specail case convert map table source */
+static const unsigned int ubin_convert_table_src[] = {
+ (MD_CAP_GSM|MD_CAP_TDD_LTE|MD_CAP_FDD_LTE|MD_CAP_CDMA2000),
+ (MD_CAP_GSM|MD_CAP_WCDMA|MD_CAP_CDMA2000)
+};
+
+/* Specail case convert map table destination */
+static const unsigned int ubin_convert_table_des[] = {
+ (MD_CAP_GSM|MD_CAP_WCDMA|MD_CAP_TDD_LTE|MD_CAP_FDD_LTE|MD_CAP_CDMA2000),
+ (MD_CAP_GSM|MD_CAP_WCDMA|MD_CAP_TDD_LTE|MD_CAP_FDD_LTE|MD_CAP_CDMA2000)
+};
+
+enum md_type {
+ md_type_2g = 1,
+ md_type_3g,
+ md_type_wg,
+ md_type_tg,
+ md_type_lwg,
+ md_type_ltg,
+};
+
+/**************************************************************************************************************/
+/* Global variable or table at this file */
+/**************************************************************************************************************/
+static struct opt_cfg default_option_list[] = { /* string lenght should less then 32 */
+ {"opt_md1_support", 0},/* if MD1_SUPPORT > 0, MD1_EN true */
+ {"opt_md3_support", 0},/* if MD3_SUPPORT > 0, MD3_EN true, ECCCI_C2K true, C2K_SUPPORT true */
+ {"opt_c2k_lte_mode", C2K_LTE_MODE},/* mode 0:none; 1: SVLTE; 2: SRLTE */
+ {"opt_lte_support", 0},
+ {"opt_c2k_support", 0},
+};
+
+
+static char *s_g_local_cmd_line_buf;
+static int s_g_local_cmd_line_buf_size;
+static int s_g_curr_opt_buf_offset;
+
+static int radio_cfg_by_name(void *fdt, int offset, char name[])
+{
+ int len;
+ const void *fdt_tmp;
+
+ fdt_tmp = fdt_getprop(fdt, offset, name, &len);
+ if (!fdt_tmp || !len)
+ return -1;
+
+ return (int)fdt32_to_cpu(*(unsigned int *)fdt_tmp);
+}
+
+static int radio_cap_dts_confirm(void *fdt, int offset, char name[])
+{
+ int len;
+ const void *fdt_tmp;
+
+ fdt_tmp = fdt_getprop(fdt, offset, "compatible", &len);
+ if (!fdt_tmp || !len)
+ return -1;
+
+ if (strcmp((char*)fdt_tmp, name))
+ return -1;
+
+ return 0;
+}
+
+struct radio_md_cap_bit {
+ char *key;
+ unsigned int bit;
+};
+
+static struct radio_md_cap_bit radio_cap_bitmap_table[] =
+{
+ {"radio_md_g_en", MD_CAP_GSM},
+ {"radio_md_w_en", MD_CAP_WCDMA},
+ {"radio_md_t_en", MD_CAP_TDS_CDMA},
+ {"radio_md_c_en", MD_CAP_CDMA2000},
+ {"radio_md_lf_en", MD_CAP_FDD_LTE},
+ {"radio_md_lt_en", MD_CAP_TDD_LTE},
+ {"radio_md_nr_en", MD_CAP_NR},
+};
+
+static int get_radio_cfg_from_dt(void *fdt, unsigned int *radio_cap_bitmap)
+{
+ int nodeoffset;
+ int ret;
+ unsigned int i;
+
+ if (!radio_cap_bitmap) {
+ ALWAYS_LOG("cap bitmap is NULL\n");
+ return -1;
+ }
+
+ nodeoffset = fdt_path_offset(fdt, "/radio_md_cfg");
+ if (nodeoffset < 0) {
+ ALWAYS_LOG("/radio_md_cfg disable at dts\n");
+ return -1;
+ }
+
+ if (radio_cap_dts_confirm(fdt, nodeoffset, "mediatek,radio_md_cfg")) {
+ ALWAYS_LOG("/radio_md_cfg compatible disable at dts\n");
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(radio_cap_bitmap_table)/sizeof(struct radio_md_cap_bit); i++) {
+ ret = radio_cfg_by_name(fdt, nodeoffset, radio_cap_bitmap_table[i].key);
+ if (ret < 0) {
+ ALWAYS_LOG("radio cap:%s using default\n", radio_cap_bitmap_table[i].key);
+ return -1;
+ }
+ if (ret > 0)
+ *radio_cap_bitmap |= radio_cap_bitmap_table[i].bit;
+ }
+
+ ret = radio_cfg_by_name(fdt, nodeoffset, "radio_md_c2k_lte_mode");
+ if (ret >= 0) {
+ for (i = 0; i < sizeof(default_option_list)/sizeof(struct opt_cfg); i++) {
+ if (!strcmp(default_option_list[i].name, "opt_c2k_lte_mode")) {
+ ALWAYS_LOG("c2k_lte_mode at dts val:%d\n", ret);
+ default_option_list[i].val = ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/**************************************************************************************************/
+/* Local function for telephony */
+/**************************************************************************************************/
+static unsigned int get_capability_bit(char cap_str[])
+{
+ if (cap_str == NULL)
+ return 0;
+ if ((strcmp(cap_str, "LF") == 0) || (strcmp(cap_str, "Lf") == 0) || (strcmp(cap_str, "lf") == 0))
+ return MD_CAP_FDD_LTE;
+ if ((strcmp(cap_str, "LT") == 0) || (strcmp(cap_str, "Lt") == 0) || (strcmp(cap_str, "lt") == 0))
+ return MD_CAP_TDD_LTE;
+ if ((strcmp(cap_str, "W") == 0) || (strcmp(cap_str, "w") == 0))
+ return MD_CAP_WCDMA;
+ if ((strcmp(cap_str, "C") == 0) || (strcmp(cap_str, "c") == 0))
+ return MD_CAP_CDMA2000;
+ if ((strcmp(cap_str, "T") == 0) || (strcmp(cap_str, "t") == 0))
+ return MD_CAP_TDS_CDMA;
+ if ((strcmp(cap_str, "G") == 0) || (strcmp(cap_str, "g") == 0))
+ return MD_CAP_GSM;
+
+ return 0;
+}
+
+#define MAX_CAP_STR_LENGTH 16
+static unsigned int get_capablity_bit_map(char str[])
+{
+ char tmp_str[MAX_CAP_STR_LENGTH];
+ int tmp_str_curr_pos = 0;
+ unsigned int capability_bit_map = 0;
+ int str_len;
+ int i;
+
+ if (str == NULL)
+ return 0;
+
+ str_len = strlen(str);
+ for (i = 0; i < str_len; i++) {
+ if (str[i] == ' ')
+ continue;
+ if (str[i] == '\t')
+ continue;
+ if ((str[i] == '/') || (str[i] == '_')) {
+ if (tmp_str_curr_pos) {
+ tmp_str[tmp_str_curr_pos] = 0;
+ capability_bit_map |= get_capability_bit(tmp_str);
+ }
+ tmp_str_curr_pos = 0;
+ continue;
+ }
+ if (tmp_str_curr_pos < (MAX_CAP_STR_LENGTH-1)) {
+ tmp_str[tmp_str_curr_pos] = str[i];
+ tmp_str_curr_pos++;
+ } else
+ break;
+ }
+ if (tmp_str_curr_pos) {
+ tmp_str[tmp_str_curr_pos] = 0;
+ capability_bit_map |= get_capability_bit(tmp_str);
+ }
+
+ return capability_bit_map;
+}
+
+static unsigned int compatible_convert(unsigned int src_rat)
+{
+ unsigned int i;
+
+ for (i = 0; i < (sizeof(ubin_convert_table_src)/sizeof(unsigned int)); i++) {
+ if (ubin_convert_table_src[i] == src_rat)
+ return ubin_convert_table_des[i];
+ }
+ return src_rat;
+}
+
+static unsigned int get_ubin_val_by_bitmap(unsigned int rat_bitmap)
+{
+ unsigned int val;
+ unsigned int i;
+
+ val = rat_bitmap & MD_CAP_MASK;
+ val = compatible_convert(val);
+ for (i = 0; i < (sizeof(legacy_ubin_rat_map)/sizeof(unsigned int)); i++) {
+ if (val == legacy_ubin_rat_map[i])
+ return LEGACY_UBIN_START_ID + i;
+ }
+ return rat_bitmap|MD_CAP_KEY;
+}
+
+static int cal_md3_type_by_rat_bitmap(unsigned int rat_bitmap)
+{
+ int rat_ver;
+ long long plat_ret;
+
+ plat_ret = ccci_hal_get_ld_md_plat_setting("rat_plat_ver");
+ if (plat_ret > 0)
+ rat_ver = (int)plat_ret;
+ else
+ rat_ver = RAT_VER_DEFAULT;
+
+ switch (rat_ver) {
+ case RAT_VER_93:
+ return 0;
+
+ case RAT_VER_DEFAULT:
+ /* go through */
+ default: /* Include case 0, using univeral bin rat version */
+ if (rat_bitmap & MD_CAP_CDMA2000)
+ return md_type_3g;
+ return 0;
+ }
+}
+
+static int cal_md1_type_by_rat_bitmap(unsigned int rat_bitmap)
+{
+ int rat_ver;
+ long long plat_ret;
+
+ plat_ret = ccci_hal_get_ld_md_plat_setting("rat_plat_ver");
+ if (plat_ret > 0)
+ rat_ver = (int)plat_ret;
+ else
+ rat_ver = RAT_VER_DEFAULT;
+
+ switch (rat_ver) {
+ case RAT_VER_R8:
+ if (rat_bitmap & MD_CAP_WCDMA)
+ return md_type_wg;
+ if (rat_bitmap & MD_CAP_TDS_CDMA)
+ return md_type_tg;
+ if (rat_bitmap & MD_CAP_GSM)
+ return md_type_2g;
+ return 0;
+
+ case RAT_VER_90:
+ /* 5, 6, 3, 4, 1 */
+ if (rat_bitmap & (MD_CAP_FDD_LTE | MD_CAP_TDD_LTE)) {
+ if ((rat_bitmap & (MD_CAP_TDS_CDMA | MD_CAP_WCDMA)) == (MD_CAP_TDS_CDMA | MD_CAP_WCDMA))
+ return md_type_ltg;
+ if (rat_bitmap & MD_CAP_TDS_CDMA)
+ return md_type_ltg;
+ if (rat_bitmap & MD_CAP_WCDMA)
+ return md_type_lwg;
+ return md_type_lwg; /* Using lwg as default */
+ }
+ if ((rat_bitmap & MD_CAP_MASK) == (MD_CAP_WCDMA | MD_CAP_GSM | MD_CAP_CDMA2000))
+ return md_type_lwg; /* Special setting for wcg with non-lk load modem */
+ if (rat_bitmap & MD_CAP_WCDMA)
+ return md_type_wg;
+ if (rat_bitmap & MD_CAP_TDS_CDMA)
+ return md_type_tg;
+ if (rat_bitmap & MD_CAP_GSM)
+ return md_type_2g;
+ return 0;
+
+ case RAT_VER_DEFAULT:
+ /* go through */
+ default: /* Include case 0, using univeral bin rat version */
+ return (int)get_ubin_val_by_bitmap(rat_bitmap);
+ }
+}
+
+static int append_rat_str(char buf[], int size, char append_str[])
+{
+ int buf_used;
+ int append_size;
+ int left_size;
+
+ buf_used = strlen(buf);
+ append_size = strlen(append_str) + 1;
+
+ left_size = size - buf_used;
+ if (left_size > append_size) {
+ if (buf_used > 0)
+ return snprintf(&buf[buf_used], left_size, "/%s", append_str);
+ return snprintf(&buf[buf_used], left_size, "%s", append_str);
+ }
+
+ return -1;
+}
+
+static void rat_bitmap_to_str(unsigned int rat_bitmap, char rat_str_des[], int des_size)
+{
+ if (des_size > 0) {
+ rat_str_des[des_size - 1] = 0;
+ if (rat_bitmap == 0) {
+ rat_str_des[0] = 0;
+ return;
+ }
+ } else
+ return;
+
+ /* Gen string */
+ if (rat_bitmap & MD_CAP_CDMA2000)
+ append_rat_str(rat_str_des, des_size, "C");
+ if (rat_bitmap & MD_CAP_FDD_LTE)
+ append_rat_str(rat_str_des, des_size, "Lf");
+ if (rat_bitmap & MD_CAP_TDD_LTE)
+ append_rat_str(rat_str_des, des_size, "Lt");
+ if (rat_bitmap & MD_CAP_WCDMA)
+ append_rat_str(rat_str_des, des_size, "W");
+ if (rat_bitmap & MD_CAP_TDS_CDMA)
+ append_rat_str(rat_str_des, des_size, "T");
+ if (rat_bitmap & MD_CAP_GSM)
+ append_rat_str(rat_str_des, des_size, "G");
+}
+
+static int get_md_support_value_by_rat_bitmap(int md_id, unsigned int rat_bitmap)
+{
+ if (md_id == MD_SYS1)
+ return cal_md1_type_by_rat_bitmap(rat_bitmap);
+
+ if (md_id == MD_SYS3)
+ return cal_md3_type_by_rat_bitmap(rat_bitmap);
+
+ return 0;
+}
+
+static void adjust_setting_by_rat_bitmap(unsigned int bit_map, struct opt_cfg option_list[], int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++) {
+ if (strcmp(option_list[i].name, "opt_md1_support") == 0) {
+ #ifdef DUMMY_AP_MODE
+ option_list[i].val = 12;
+ #else
+ option_list[i].val = get_md_support_value_by_rat_bitmap(MD_SYS1, bit_map);
+ #endif
+ continue;
+ }
+ if (strcmp(option_list[i].name, "opt_md3_support") == 0) {
+ #ifdef DUMMY_AP_MODE
+ option_list[i].val = 2;
+ #else
+ option_list[i].val = get_md_support_value_by_rat_bitmap(MD_SYS3, bit_map);
+ #endif
+ continue;
+ }
+ if (strcmp(option_list[i].name, "opt_c2k_support") == 0) {
+ if (bit_map & MD_CAP_CDMA2000)
+ option_list[i].val = 1;
+ else
+ option_list[i].val = 0;
+ continue;
+ }
+ if (strcmp(option_list[i].name, "opt_lte_support") == 0) {
+ if (bit_map & (MD_CAP_FDD_LTE | MD_CAP_TDD_LTE))
+ option_list[i].val = 1;
+ else
+ option_list[i].val = 0;
+ continue;
+ }
+ }
+}
+
+static int option_validation_check(unsigned int bit_map, struct opt_cfg option_list[], int num)
+{
+ int i;
+ int md1_support = 0, md3_support = 0, lte_support = 0;
+ int val;
+
+ for (i = 0; i < num; i++) {
+ if (strcmp(option_list[i].name, "opt_md1_support") == 0) {
+ md1_support = option_list[i].val;
+ continue;
+ }
+ if (strcmp(option_list[i].name, "opt_md3_support") == 0) {
+ md3_support = option_list[i].val;
+ continue;
+ }
+ if (strcmp(option_list[i].name, "opt_lte_support") == 0) {
+ lte_support = option_list[i].val;
+ continue;
+ }
+ }
+
+ /* Check lte_support */
+ if ((!!(bit_map & (MD_CAP_FDD_LTE | MD_CAP_TDD_LTE))) != (!!lte_support))
+ return -1;
+
+ /* Check opt_md1_support */
+ val = get_md_support_value_by_rat_bitmap(MD_SYS1, bit_map);
+ if ((val > 0) && (md1_support == 0))
+ return -1;
+
+ if ((val == 0) && (md1_support > 0))
+ return -1;
+
+ /* Check opt_md3_support */
+ val = get_md_support_value_by_rat_bitmap(MD_SYS3, bit_map);
+ if ((val > 0) && (md3_support == 0))
+ return -1;
+
+ if ((val == 0) && (md3_support > 0))
+ return -1;
+
+ /* All check OK */
+ return 0;
+}
+
+/* Using command line buffer to store opt value */
+static int add_opt_setting_to_buf(char name[], char val[])
+{
+ int name_len;
+ int value_len;
+
+ if ((name == NULL) || (val == NULL)) {
+ ALWAYS_LOG("dt args invalid\n");
+ return -1;
+ }
+
+ name_len = strlen(name) + 1;
+ value_len = strlen(val) + 1;
+
+ if ((s_g_local_cmd_line_buf_size - s_g_curr_opt_buf_offset) < (value_len + name_len)) {
+ ALWAYS_LOG("dt buf free size not enough\n");
+ return -1;
+ }
+
+ /* copy name */
+ memcpy(&s_g_local_cmd_line_buf[s_g_curr_opt_buf_offset], name, name_len);
+ s_g_curr_opt_buf_offset += name_len;
+ /* copy value */
+ memcpy(&s_g_local_cmd_line_buf[s_g_curr_opt_buf_offset], val, value_len);
+ s_g_curr_opt_buf_offset += value_len;
+
+ return 0;
+}
+
+struct tel_mode_case {
+ char *ps1_rat;
+ int md1_support;
+ int md3_support;
+ int c2k_lte_mode;
+};
+
+struct tel_mode_case tel_mode_list[] = {
+ {.ps1_rat = "C/W/G", .md1_support = 11, .md3_support = 0, .c2k_lte_mode = 2,}, /* C2K 3M (C/W/G) */
+ {.ps1_rat = "Lf/W/G", .md1_support = 14, .md3_support = 0, .c2k_lte_mode = 0,}, /* FDD 3M (Lf/W/G) */
+ {.ps1_rat = "Lt/T/G", .md1_support = 13, .md3_support = 0, .c2k_lte_mode = 0,}, /* TDD 3M (Lt/T/G) */
+ {.ps1_rat = "C/Lf/Lt/G", .md1_support = 11, .md3_support = 0, .c2k_lte_mode = 2,}, /* C2K 4M (C/Lf/Lt/G) */
+ {.ps1_rat = "Lf/Lt/W/G", .md1_support = 9, .md3_support = 0, .c2k_lte_mode = 0,}, /* FDD 4M (Lf/Lt/W/G) */
+ {.ps1_rat = "C/Lf/Lt/W/G", .md1_support = 11, .md3_support = 0, .c2k_lte_mode = 2,}, /* C2K 5M (C/Lf/Lt/W/G) */
+ {.ps1_rat = "Lf/Lt/W/T/G", .md1_support = 10, .md3_support = 0, .c2k_lte_mode = 0,}, /* FDD 5M (Lf/Lt/W/T/G) */
+ {.ps1_rat = "C/Lf/Lt/W/T/G", .md1_support = 12, .md3_support = 0, .c2k_lte_mode = 2,} /* 6M (C/Lf/Lt/W/T/G) */
+};
+
+static int cust_tel_mode_calc_by_idx(int idx, struct opt_cfg *d_opt_list, int num, unsigned int *cap_bit_map)
+{
+ int i;
+
+ if (idx >= (int)(sizeof(tel_mode_list)/sizeof(struct tel_mode_case)))
+ return -1;
+ *cap_bit_map = get_capablity_bit_map(tel_mode_list[idx].ps1_rat);
+ for (i = 0; i < num; i++) {
+ if (strcmp(d_opt_list[i].name, "opt_md1_support") == 0) {
+ d_opt_list[i].val = tel_mode_list[idx].md1_support;
+ continue;
+ }
+ if (strcmp(d_opt_list[i].name, "opt_md3_support") == 0) {
+ d_opt_list[i].val = tel_mode_list[idx].md3_support;
+ continue;
+ }
+ if (strcmp(d_opt_list[i].name, "opt_c2k_lte_mode") == 0) {
+ d_opt_list[i].val = tel_mode_list[idx].c2k_lte_mode;
+ continue;
+ }
+ }
+ return 0;
+}
+
+static void update_to_default(struct opt_cfg *d_opt_list, struct opt_cfg *default_list, int num)
+{
+ int i, j;
+
+ for (i = 0; i < num; i++) {
+ if (strcmp(d_opt_list[i].name, default_list[i].name) == 0) {
+ default_list[i].val = d_opt_list[i].val;
+ continue;
+ }
+ for (j = 0; j < num; j++) {
+ if (strcmp(d_opt_list[j].name, default_list[i].name) == 0) {
+ default_list[i].val = d_opt_list[j].val;
+ break;
+ }
+ }
+ }
+}
+
+static int mtk_tel_mode_calc(struct opt_cfg *d_opt_list, int num, unsigned int *cap_bit_map)
+{
+ int i;
+ char *ret_val_ptr;
+ int val;
+ int has_update = 0;
+
+ ret_val_ptr = get_lk_ro_env_str("opt_ps1_rat");
+ *cap_bit_map = get_capablity_bit_map(ret_val_ptr);
+ if (ret_val_ptr)
+ has_update = 1;
+ for (i = 0; i < num; i++) {
+ ret_val_ptr = get_lk_ro_env_str(d_opt_list[i].name);
+ if (ret_val_ptr) {
+ has_update = 1;
+ val = str2uint(ret_val_ptr);
+ d_opt_list[i].val = val;
+ }
+ }
+
+ if (has_update)
+ return 0;
+
+ return -1;
+}
+
+int dynamic_setting_calc(struct opt_cfg *d_opt_list, unsigned int *cap_bit_map)
+{
+ int idx, ret;
+ unsigned int cfg_item_num = sizeof(default_option_list)/sizeof(struct opt_cfg);
+
+ /* Copy default setting */
+ memcpy(d_opt_list, default_option_list, sizeof(default_option_list));
+
+ /* Check custom telephony switch setting */
+ idx = get_cust_tel_mode_idx();
+ ALWAYS_LOG("cust_tel_mode_idx val:%d\n", idx);
+ if (idx >= 0) /* Using custom setting */
+ ret = cust_tel_mode_calc_by_idx(idx, d_opt_list, (int)cfg_item_num, cap_bit_map);
+ else /* Using mtk solution */
+ ret = mtk_tel_mode_calc(d_opt_list, (int)cfg_item_num, cap_bit_map);
+
+ if (ret < 0)
+ return 1;/* No change */
+
+ adjust_setting_by_rat_bitmap(*cap_bit_map, d_opt_list, cfg_item_num);
+ ret = option_validation_check(*cap_bit_map, d_opt_list, cfg_item_num);
+ if (ret == 0)
+ return 0; /* Changed */
+ else
+ return -1;/* Roll back to default */
+}
+
+/***********************************************************************************************/
+/* Functions that will be called by exteranl */
+/***********************************************************************************************/
+int update_md_opt_to_fdt_firmware(void *fdt)
+{
+#ifdef LK_OPT_TO_KERNEL_CCCI
+ int nodeoffset;
+ char *name, *value;
+ int name_len, val_len;
+ int i = 0;
+
+ if (s_g_curr_opt_buf_offset == 0) {
+ ALWAYS_LOG("no need update md_opt_cfg\n");
+ return 0;
+ }
+
+ nodeoffset = fdt_path_offset(fdt, "/firmware/android");
+ if (nodeoffset < 0) {
+ ALWAYS_LOG("/firmware/android not found\n");
+ return -1;
+ }
+
+ while (i < s_g_curr_opt_buf_offset) {
+ name_len = strlen(&s_g_local_cmd_line_buf[i]) + 1;
+ name = &s_g_local_cmd_line_buf[i];
+ i += name_len;
+ val_len = strlen(&s_g_local_cmd_line_buf[i]) + 1;
+ value = &s_g_local_cmd_line_buf[i];
+ i += val_len;
+ fdt_setprop_string(fdt, nodeoffset, name, value);
+ }
+#endif
+
+ return 0;
+}
+
+extern void *g_fdt;
+
+int prepare_tel_fo_setting(void)
+{
+ unsigned int i;
+ char val_str[8];
+ char *new_value = NULL;
+ char def_rat_str[32];
+ int value;
+ struct opt_cfg *new_opt_list;
+ int using_default = 1; /* 1: Using default, 0: Using new setting, -1: New setting abnormal */
+ unsigned int default_cap_bit_map, cap_bit_map = 0, dts_cap_bitmap;
+ unsigned int cfg_item_num = sizeof(default_option_list)/sizeof(struct opt_cfg);
+
+ /* Prepare default option setting */
+ dts_cap_bitmap = 0;
+ if (get_radio_cfg_from_dt(g_fdt, &dts_cap_bitmap) < 0)
+ default_cap_bit_map = get_capablity_bit_map(PS1_RAT_DEFAULT);
+ else
+ default_cap_bit_map = dts_cap_bitmap;
+ if (default_cap_bit_map)
+ adjust_setting_by_rat_bitmap(default_cap_bit_map, default_option_list, cfg_item_num);
+
+ /* Prepare dynamic env setting table */
+ new_opt_list = (struct opt_cfg *)malloc(sizeof(default_option_list));
+ if (new_opt_list)
+ using_default = dynamic_setting_calc(new_opt_list, &cap_bit_map);
+ if (using_default == 0) {
+ update_to_default(new_opt_list, default_option_list, (int)cfg_item_num);
+ default_cap_bit_map = cap_bit_map;
+ }
+
+ /* Update to tag buffer for kernel */
+ for (i = 0; i < cfg_item_num; i++) {
+ snprintf(val_str, sizeof(val_str), "%d", default_option_list[i].val);
+ add_opt_setting_to_buf(default_option_list[i].name, val_str);
+ insert_ccci_tag_inf(default_option_list[i].name, (char*)&default_option_list[i].val, sizeof(int));
+ }
+ def_rat_str[0] = '\0';
+ if (default_cap_bit_map) {
+ rat_bitmap_to_str(default_cap_bit_map, def_rat_str, sizeof(def_rat_str));
+ add_opt_setting_to_buf("opt_ps1_rat", def_rat_str);
+ insert_ccci_tag_inf("opt_ps1_rat", (char*)&default_cap_bit_map, sizeof(int));
+ }
+ ALWAYS_LOG("Radio cap final:%s[0x%x]\n", def_rat_str, default_cap_bit_map);
+ def_rat_str[0] = '\0';
+ rat_bitmap_to_str(dts_cap_bitmap, def_rat_str, sizeof(def_rat_str));
+ ALWAYS_LOG(" ----- dts:%s[0x%x]\n", def_rat_str, dts_cap_bitmap);
+ def_rat_str[0] = '\0';
+ rat_bitmap_to_str(get_capablity_bit_map(PS1_RAT_DEFAULT), def_rat_str, sizeof(def_rat_str));
+ ALWAYS_LOG(" ----- prj:%s[0x%x]\n", def_rat_str, get_capablity_bit_map(PS1_RAT_DEFAULT));
+ def_rat_str[0] = '\0';
+ rat_bitmap_to_str(cap_bit_map, def_rat_str, sizeof(def_rat_str));
+ ALWAYS_LOG(" --dynamic:%s[0x%x]\n", def_rat_str, cap_bit_map);
+
+ /* update using default or not */
+ insert_ccci_tag_inf("opt_using_default", (char*)&using_default, sizeof(int));
+ snprintf(val_str, sizeof(val_str), "%d", using_default);
+ add_opt_setting_to_buf("opt_using_default", val_str);
+
+ /* update platform option */
+ value = (int)ccci_hal_get_ld_md_plat_setting("rat_plat_ver");
+ if ((value == RAT_VER_R8) || (value == RAT_VER_90))
+ value = 0;
+ else if (value == RAT_VER_91_92)
+ value = 1;
+ else if (value == RAT_VER_93)
+ value = 1;
+ else
+ value = 1;
+
+ snprintf(val_str, sizeof(val_str), "%d", value);
+ add_opt_setting_to_buf("opt_eccci_c2k", val_str);
+ insert_ccci_tag_inf("opt_eccci_c2k", (char*)&value, sizeof(int));
+
+ new_value = get_env("msim_config");
+ if (new_value != NULL)
+ add_opt_setting_to_buf("product.hardware.sku", new_value);
+
+ /* Notify Kernel using LK setting */
+#ifdef LK_OPT_TO_KERNEL_CCCI
+ value = 1;
+ insert_ccci_tag_inf("opt_using_lk_val", (char*)&value, sizeof(int)); /* Notify Kernel using kernel setting */
+#endif
+
+ if (new_opt_list)
+ free(new_opt_list);
+
+ return 0;
+}
+
+int ccci_get_opt_val(const char opt[])
+{
+ int i;
+
+ for (i = 0; i < (int)(sizeof(default_option_list)/sizeof(struct opt_cfg)); i++) {
+ if (strcmp(default_option_list[i].name, opt) == 0) {
+ return default_option_list[i].val;
+ }
+ }
+
+ return -LD_ERR_OPT_NOT_FOUND;
+}
+
+int ccci_alloc_local_cmd_line_buf(int size)
+{
+ s_g_local_cmd_line_buf = malloc(size);
+ if (s_g_local_cmd_line_buf == NULL)
+ return -LD_ERR_OPT_CMD_BUF_ALLOC_FAIL;
+ s_g_local_cmd_line_buf_size = size;
+ return 0;
+}
+
+void ccci_free_local_cmd_line_buf(void)
+{
+ if (s_g_local_cmd_line_buf)
+ free(s_g_local_cmd_line_buf);
+
+ s_g_local_cmd_line_buf_size = 0;
+}
+
+int ccci_ld_md_tel_init(void)
+{
+ if (ccci_alloc_local_cmd_line_buf(1024) < 0) {
+ ALWAYS_LOG("allocate local cmd line memory fail\n");
+ return -1;
+ }
+
+ prepare_tel_fo_setting();
+ return 0;
+}
+#else
+int ccci_ld_md_tel_init(void)
+{
+ return 0;
+}
+int ccci_get_opt_val(const char opt[])
+{
+ return 1;
+}
+void ccci_free_local_cmd_line_buf(void)
+{
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.h b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.h
new file mode 100644
index 0000000..205c186
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_ld_md_tel.h
@@ -0,0 +1,39 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#ifndef __CCCI_LD_MD_TEL_H__
+#define __CCCI_LD_MD_TEL_H__
+
+int ccci_ld_md_tel_init(void);
+int ccci_get_opt_val(const char opt[]);
+void ccci_free_local_cmd_line_buf(void);
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/ccci_lk_load_img_plat.c b/src/bsp/lk/platform/mt2731/drivers/md/ccci_lk_load_img_plat.c
new file mode 100644
index 0000000..33812b8
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/ccci_lk_load_img_plat.c
@@ -0,0 +1,1157 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+#include <sys/types.h>
+#include <stdint.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <printf.h>
+#include <string.h>
+#include <malloc.h>
+#include <libfdt.h>
+#include <assert.h>
+#include <debug.h>
+#define MODULE_NAME "LK_LD_MD"
+#include "ccci_ld_md_core.h"
+#include "ccci_ld_md_errno.h"
+#ifdef TELE_CCCI_SUPPORT
+#include <reg.h>
+#include <errno.h>
+#include "platform/emi_mpu_mt.h"
+#else
+#include <platform/errno.h>
+#include <platform/partition.h>
+#include <platform/boot_mode.h>
+#include <platform/mt_gpt.h>
+#include <platform/mt_emi_mpu.h>
+#include <mt_boot.h>
+#endif
+#include <platform/sip.h>
+
+#define CCCI_SMEM_SIZE_DFD (448*1024)
+#define CCCI_SMEM_SIZE_CCB_DHL (2*1024*1024)
+#define CCCI_SMEM_SIZE_RAW_DHL (6.5*1024*1024)
+#define CCCI_SMEM_SIZE_LWA (0) // (8*1024*1024)
+#define CCCI_SMEM_SIZE_PHY_C_L0 (0*1024*1024)
+#define CCCI_SMEM_SIZE_PHY_C_L1 (32*1024*1024)
+#define CCCI_SMEM_SIZE_PHY_C_L2 (64*1024*1024)
+#define CCCI_SMEM_SIZE_PHY_C_L3 (128*1024*1024)
+#define CCCI_SMEM_SIZE_PHY_C_L4 (222*1024*1024)
+#define CCB_DATA_BUF_DEFAULT_GEAR 1 /* NOTE: This value may be different at different platform */
+#define CCB_DATA_BUF_SIZE (CCCI_SMEM_SIZE_CCB_DHL + CCCI_SMEM_SIZE_RAW_DHL)
+
+/***************************************************************************************************
+** Feature Option setting part
+***************************************************************************************************/
+#define ENABLE_EMI_PROTECTION
+//#ifndef EMI_MPU_DGROUP_NUM
+//#define EMI_MPU_DGROUP_NUM 2
+//#endif
+
+/***************************************************************************************************
+** HW remap section
+***************************************************************************************************/
+extern unsigned int ddr_enable_4gb(void)__attribute__((weak));
+static int is_4gb_ddr_support_en(void)
+{
+ int ret;
+ if (ddr_enable_4gb) {
+ ret = ddr_enable_4gb();
+ ALWAYS_LOG("ddr_enable_4GB sta:%d\n", ret);
+ return ret;
+ } else {
+ ALWAYS_LOG("ddr 4GB disable\n");
+ return 0;
+ }
+}
+
+/*-------- Register base part -------------------------------*/
+/* HW remap for MD1 */
+#ifdef TELE_CCCI_SUPPORT
+#define INFRA_AO_BASE (INFRACFG_BASE)
+#define ccci_get_reg32(addr) readl(addr)
+#define ccci_set_reg32(addr, val) writel(val, addr)
+#else
+#define INFRA_AO_BASE (0x10001000)
+#define ccci_get_reg32(addr) DRV_Reg32(addr)
+#define ccci_set_reg32(addr, val) DRV_WriteReg32(addr, val)
+#endif
+#define REMAP_REG_BASE bcrm_INFRA_AO_wrapper_u_bcrm_INFRA_AO_bcrm
+/* -- MD1 Bank 0 */
+#define MD1_BANK0_MAP0 (REMAP_REG_BASE + 0x1C)
+#define MD1_BANK0_MAP1 (REMAP_REG_BASE + 0x20)
+#define MD1_BANK0_MAP2 (REMAP_REG_BASE + 0x24)
+#define MD1_BANK0_MAP3 (REMAP_REG_BASE + 0x28)
+
+#ifndef _MTK_SECURE_API_H_
+#define _MTK_SECURE_API_H_
+
+#if ARCH_ARM64
+#define MTK_SIP_SMC_AARCH_BIT 0x40000000
+#else
+#define MTK_SIP_SMC_AARCH_BIT 0x00000000
+#endif
+
+/* 0x82000200 - 0x820003FF & 0xC2000300 - 0xC20003FF */
+#define MTK_SIP_KERNEL_MDHW_REMAP_SET \
+ (0x82000266 | MTK_SIP_SMC_AARCH_BIT)
+#define MTK_SIP_KERNEL_MDHW_REMAP_GET \
+ (0x82000267 | MTK_SIP_SMC_AARCH_BIT)
+
+extern size_t mt_secure_call_all(size_t function_id,
+ size_t arg0, size_t arg1, size_t arg2,
+ size_t arg3, size_t *r1, size_t *r2, size_t *r3);
+
+
+#if ARCH_ARM64
+#define LOCAL_REG_SET_DECLARE \
+ register size_t reg0 __asm__("x0") = function_id; \
+ register size_t reg1 __asm__("x1") = arg0; \
+ register size_t reg2 __asm__("x2") = arg1; \
+ register size_t reg3 __asm__("x3") = arg2; \
+ register size_t reg4 __asm__("x4") = arg3; \
+ size_t ret
+#else
+#define LOCAL_REG_SET_DECLARE \
+ register size_t reg0 __asm__("r0") = function_id; \
+ register size_t reg1 __asm__("r1") = arg0; \
+ register size_t reg2 __asm__("r2") = arg1; \
+ register size_t reg3 __asm__("r3") = arg2; \
+ register size_t reg4 __asm__("r4") = arg3; \
+ size_t ret
+#endif
+
+size_t mt_secure_call_all(size_t function_id,
+ size_t arg0, size_t arg1, size_t arg2,
+ size_t arg3, size_t *r1, size_t *r2, size_t *r3)
+{
+ LOCAL_REG_SET_DECLARE;
+
+#if ARCH_ARM64//def CONFIG_ARM64
+ __asm__ volatile ("smc #0x0\n" : "+r"(reg0),
+ "+r"(reg1), "+r"(reg2), "+r"(reg3), "+r"(reg4));
+#else
+ __asm__ volatile (__SMC(0) : "+r"(reg0),
+ "+r"(reg1), "+r"(reg2), "+r"(reg3), "+r"(reg4));
+#endif
+ ret = reg0;
+ if (r1 != NULL)
+ *r1 = reg1;
+ if (r2 != NULL)
+ *r2 = reg2;
+ if (r3 != NULL)
+ *r3 = reg3;
+ return ret;
+}
+#endif /* _MTK_SECURE_API_H_ */
+
+enum {
+ MD_BANK0_HW_REMAP,
+ MD_BANK4_HW_REMAP,
+};
+
+static int md_mem_ro_rw_remapping(unsigned int md_id, unsigned long long addr)
+{
+ unsigned long long md_img_start_addr;
+ size_t r1, r2, r3;
+#if WITH_KERNEL_VM
+ md_img_start_addr = kvaddr_to_paddr((void *)addr);
+#else
+ md_img_start_addr = addr;
+#endif
+ ALWAYS_LOG("---> Map 0x00000000 to 0x%llx for MD%d\n", md_img_start_addr, md_id+1);
+
+ mt_secure_call_all(MTK_SIP_KERNEL_MDHW_REMAP_SET,
+ MD_BANK0_HW_REMAP,
+ (u32)md_img_start_addr, (u32)(md_img_start_addr >> 32), 0,
+ &r1, &r2, &r3);
+#if ARCH_ARM64
+ ALWAYS_LOG("---> HW re-Map register: 0x%lx, 0x%lx, 0x%lx\n", r1, r2, r3);
+#else
+ ALWAYS_LOG("---> HW re-Map register: 0x%x, 0x%x, 0x%x\n", r1, r2, r3);
+#endif
+
+ /* just for normal world can't access verification.
+ ALWAYS_LOG("BANK0_MAPX value:0x%X, 0x%X, 0x%x\n",
+ ccci_get_reg32(MD1_BANK0_MAP0),
+ ccci_get_reg32(MD1_BANK0_MAP1),
+ ccci_get_reg32(MD1_BANK0_MAP2)); */
+ return 0;
+}
+
+
+static int md_bank4_remapping_by_slot(unsigned int md_id, unsigned long long m_addr, int slot)
+{
+ size_t r1, r2, r3;
+ unsigned long long addr = m_addr;
+
+ ALWAYS_LOG("---> HW-remap slot(%d): 0x%llx\n", slot, addr);
+
+ mt_secure_call_all(MTK_SIP_KERNEL_MDHW_REMAP_SET,
+ MD_BANK4_HW_REMAP,
+ (u32)addr, (u32)(addr >> 32), (size_t)slot,
+ &r1, &r2, &r3);
+#if ARCH_ARM64
+ CRITICAL_LOG("---> HW-remap slot(%d): 0x%lx\n", slot, r1);
+#else
+ CRITICAL_LOG("---> HW-remap slot(%d): 0x%x\n", slot, r1);
+#endif
+ return 0;
+}
+
+static int md_smem_rw_remapping(unsigned int md_id, unsigned long long addr)
+{
+ unsigned int i;
+ ALWAYS_LOG("---> Map 0x40000000 to 0x%llx for MD%d\n", addr, md_id+1);
+
+ for (i = 0; i < 8; i++)
+ md_bank4_remapping_by_slot(md_id, (addr + 0x2000000*i), i);
+
+ return 0;
+}
+
+/* =================================================== */
+/* MPU Region defination */
+/* =================================================== */
+/* Note: This structure should sync with Kernel!!!! */
+typedef unsigned long long mpu_att_t;
+
+typedef struct _mpu_cfg {
+ unsigned int start;
+ unsigned int end;
+ int region;
+ unsigned int permission[EMI_MPU_DGROUP_NUM];
+ int relate_region;
+} mpu_cfg_t;
+#ifdef ENABLE_EMI_PROTECTION
+
+#define MPU_REGION_ID_MD1_ROM 9
+#define MPU_REGION_ID_MD_DSP1 10 /*DSP RO*/
+#define MPU_REGION_ID_MD_DSP2 11 /*DSP RW*/
+#define MPU_REGION_ID_MD_DRDI 12
+#define MPU_REGION_ID_MD1_MCURW_HWRW 13
+#define MPU_REGION_ID_MD1_MCURW_HWRO 14
+#define MPU_REGION_ID_MD1_MCURO_HWRW 15
+/* #define MPU_REGION_ID_PADDING1 15 */
+#define MPU_REGION_ID_PADDING2 16
+#define MPU_REGION_ID_PADDING3 17
+#define MPU_REGION_ID_PADDING4 18
+#define MPU_REGION_ID_PADDING5 19
+#ifndef TELE_CCCI_SUPPORT
+#define MPU_REGION_ID_MD_PROTECT -1
+#else
+#define MPU_REGION_ID_MD_PROTECT 30
+#endif
+#define MPU_REGION_ID_MD1_CCB 22
+#define MPU_REGION_ID_MD1_SMEM 23
+
+#define MPU_REGION_ID_AP 31
+#define MPU_REGION_ID_TOTAL_NUM (MPU_REGION_ID_AP + 1)
+
+#define MPU_MDOMAIN_ID_AP 0
+#define MPU_MDOMAIN_ID_MD1 1
+#define MPU_MDOMAIN_ID_MDHW 7
+#define MPU_MDOMAIN_ID_TOTAL_NUM 16
+
+static const mpu_att_t mpu_att_default[MPU_REGION_ID_TOTAL_NUM][MPU_MDOMAIN_ID_TOTAL_NUM] = {
+ /*===================================================================================================================*/
+ /* No | | D0(AP) | D1(Rsv) | D2(CONN) | D3(SCP) | D4(MM) | D5(Rsv ) | D6(MFG) | D7(Rsv)
+ |D8(Rsv) | D9(MD1) | D10-D14(Rsv) | D15(MDHW) |*/
+ /*--------------+----------------------------------------------------------------------------------------------------*/
+ /* 0*/{}, /*Secure OS*/
+ /* 1*/{}, /*ATF*/
+ /* 2*/{}, /*Secure Memory*/
+ /* 3*/{}, /*Tinysys-SSPM ROM*/
+ /* 4*/{}, /*Tinysys-SSPM share buffer*/
+ /* 5*/{}, /*Trusted UI*/
+ /* 6*/{}, /*AMMS*/
+ /* 7*/{}, /*AMMS*/
+ /* 8*/{}, /*Security CCCI share memory*/
+ /* 9*/{ SEC_R_NSEC_R, SEC_R_NSEC_R, [2 ... 6] = FORBIDDEN, SEC_R_NSEC_R, [8 ... 15] = FORBIDDEN},
+ /*10*/{ SEC_R_NSEC_R, SEC_R_NSEC_R, [2 ... 6] = FORBIDDEN, SEC_R_NSEC_R, [8 ... 15] = FORBIDDEN},
+ /*11*/{ SEC_R_NSEC_R, NO_PROTECTION, [2 ... 6] = FORBIDDEN, NO_PROTECTION, [8 ... 15] = FORBIDDEN},
+ /*12*/{ SEC_R_NSEC_R, SEC_R_NSEC_R, [2 ... 6] = FORBIDDEN, SEC_R_NSEC_R, [8 ... 15] = FORBIDDEN}, /*DRDI*/
+ /*13*/{ SEC_R_NSEC_R, NO_PROTECTION, [2 ... 6] = FORBIDDEN, NO_PROTECTION, [8 ... 15] = FORBIDDEN},
+ /*14*/{ SEC_R_NSEC_R, NO_PROTECTION, [2 ... 6] = FORBIDDEN, SEC_R_NSEC_R, [8 ... 15] = FORBIDDEN},
+ /*15*/{ SEC_R_NSEC_R, SEC_R_NSEC_R, [2 ... 6] = FORBIDDEN, NO_PROTECTION, [8 ... 15] = FORBIDDEN},
+ /*16*/{ SEC_R_NSEC_R, FORBIDDEN, [2 ... 6] = FORBIDDEN, FORBIDDEN, [8 ... 15] = FORBIDDEN},
+ /*17*/{ SEC_R_NSEC_R, FORBIDDEN, [2 ... 6] = FORBIDDEN, FORBIDDEN, [8 ... 15] = FORBIDDEN},
+ /*18*/{ SEC_R_NSEC_R, FORBIDDEN, [2 ... 6] = FORBIDDEN, FORBIDDEN, [8 ... 15] = FORBIDDEN},
+ /*19*/{ SEC_R_NSEC_R, FORBIDDEN, [2 ... 6] = FORBIDDEN, FORBIDDEN, [8 ... 15] = FORBIDDEN},
+ /*20*/{},
+ /*21*/{},/*MD-Consys Direct Path*/
+ /*22*/{ NO_PROTECTION, NO_PROTECTION, [2 ... 6] = FORBIDDEN, NO_PROTECTION, [8 ... 15] = FORBIDDEN},
+ /*23*/{ NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION,[4 ... 6] = FORBIDDEN, NO_PROTECTION, [8 ... 15] = FORBIDDEN},
+ /*24*/{}, /*Set in LK MD Padding1*/
+ /*25*/{}, /*Set in LK MD Padding2*/
+ /*26*/{}, /*Set in LK MD Padding3*/
+ /*27*/{}, /*Set in LK MD Padding4*/
+ /*28*/{}, /*Set in LK MD Padding5*/
+ /*29*/{}, /*Set in LK MD Protect*/
+ /*30*/{/* NO_PROTECTION, FORBIDDEN, [2 ... 3] = FORBIDDEN, NO_PROTECTION, FORBIDDEN, SEC_R_NSEC_RW,
+ [7 ... 15] = FORBIDDEN*/
+ },
+ /*31*/{
+ NO_PROTECTION, FORBIDDEN, [2 ... 3] = FORBIDDEN, NO_PROTECTION, FORBIDDEN, SEC_R_NSEC_RW,
+ [7 ... 15] = FORBIDDEN
+ },
+};
+
+#define MPU_STR_BUF_SIZE 64
+
+static void get_mpu_attr_str(int lock, unsigned int apc[EMI_MPU_DGROUP_NUM], char buf[], int size)
+{
+ unsigned long long curr_attr;
+ char ch = lock?'L':'U';
+
+ if (EMI_MPU_DGROUP_NUM != 2) {
+ CRITICAL_LOG("[error]abnormal mpu domain group number %d\n", EMI_MPU_DGROUP_NUM);
+ return;
+ }
+ curr_attr = ((unsigned long long)apc[1] << 32) | apc[0];
+ snprintf(buf, size, "%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld-%lld(%c)",
+ curr_attr&7, (curr_attr>>3)&7, (curr_attr>>6)&7, (curr_attr>>9)&7,
+ (curr_attr>>12)&7, (curr_attr>>15)&7, (curr_attr>>18)&7, (curr_attr>>21)&7,
+ (curr_attr>>32)&7, (curr_attr>>35)&7, (curr_attr>>38)&7, (curr_attr>>41)&7,
+ (curr_attr>>44)&7, (curr_attr>>47)&7, (curr_attr>>50)&7, (curr_attr>>53)&7, ch);
+}
+
+static const unsigned char region_mapping_at_hdr_md1[] = {
+ MPU_REGION_ID_MD1_ROM, MPU_REGION_ID_MD1_MCURO_HWRW, MPU_REGION_ID_MD1_MCURW_HWRO,
+ MPU_REGION_ID_MD1_MCURW_HWRW
+};
+
+static const int free_mpu_region[] = {MPU_REGION_ID_PADDING2,
+ MPU_REGION_ID_PADDING3, MPU_REGION_ID_PADDING4, MPU_REGION_ID_PADDING5, MPU_REGION_ID_MD_PROTECT, -1
+ };
+static int curr_free_mpu_idx;
+static int get_free_mpu_region(void)
+{
+ int ret;
+ if (curr_free_mpu_idx < (int)(sizeof(free_mpu_region)/sizeof(int))) {
+ ret = free_mpu_region[curr_free_mpu_idx];
+ curr_free_mpu_idx++;
+ } else
+ ret = -LD_ERR_PLAT_MPU_REGION_EMPTY;
+ return ret;
+}
+
+#ifndef TELE_CCCI_SUPPORT
+/*make sure protect region is the last valid region*/
+static int get_md_protect_mpu_region(void)
+{
+ int last_index;
+
+ last_index = (int)(sizeof(free_mpu_region)/sizeof(int)) -1;
+ if (free_mpu_region[last_index] < 0) /*free region end by -1*/
+ last_index--; /*make sure it is index of last valid region*/
+
+ if (curr_free_mpu_idx > last_index)
+ return -LD_ERR_PLAT_MPU_REGION_EMPTY;
+
+ return free_mpu_region[last_index];
+}
+#endif
+
+static void get_mpu_region_default_access_att(
+ unsigned int apc[EMI_MPU_DGROUP_NUM], int region, int lock)
+{
+#ifdef ENABLE_EMI_PROTECTION
+ SET_ACCESS_PERMISSION(apc, lock,
+ mpu_att_default[region][15], mpu_att_default[region][14],
+ mpu_att_default[region][13], mpu_att_default[region][12],
+ mpu_att_default[region][11], mpu_att_default[region][10],
+ mpu_att_default[region][9], mpu_att_default[region][8],
+ mpu_att_default[region][7], mpu_att_default[region][6],
+ mpu_att_default[region][5], mpu_att_default[region][4],
+ mpu_att_default[region][3], mpu_att_default[region][2],
+ mpu_att_default[region][1], mpu_att_default[region][0]);
+#endif
+}
+
+static void mpu_attr_calculate(
+ unsigned int apc[EMI_MPU_DGROUP_NUM], int region_id, unsigned int request_attr)
+{
+ mpu_att_t tmp_mpu_att[MPU_MDOMAIN_ID_TOTAL_NUM], i;
+ for (i = 0; i < MPU_MDOMAIN_ID_TOTAL_NUM; i++)
+ tmp_mpu_att[i] = mpu_att_default[region_id][i];
+
+ /* AP MD1 MDHW: AP */
+ if ((request_attr & 0xF) <= FORBIDDEN)
+ tmp_mpu_att[MPU_MDOMAIN_ID_AP] = (request_attr & 0xF);
+ /* AP MD1 MDHW: MD1 */
+ request_attr = (request_attr >> 4);
+ if ((request_attr & 0xF) <= FORBIDDEN)
+ tmp_mpu_att[MPU_MDOMAIN_ID_MD1] = (request_attr & 0xF);
+ /* AP MD1 MDHW: MDHW */
+ request_attr = (request_attr >> 4);
+ if ((request_attr & 0xF) <= FORBIDDEN)
+ tmp_mpu_att[MPU_MDOMAIN_ID_MDHW] = (request_attr & 0xF);
+#ifdef ENABLE_EMI_PROTECTION
+ /* MPU region lock */
+ SET_ACCESS_PERMISSION(apc, 1,
+ tmp_mpu_att[15], tmp_mpu_att[14],
+ tmp_mpu_att[13], tmp_mpu_att[12],
+ tmp_mpu_att[11], tmp_mpu_att[10],
+ tmp_mpu_att[9], tmp_mpu_att[8],
+ tmp_mpu_att[7], tmp_mpu_att[6],
+ tmp_mpu_att[5], tmp_mpu_att[4],
+ tmp_mpu_att[3], tmp_mpu_att[2],
+ tmp_mpu_att[1], tmp_mpu_att[0]);
+#endif
+}
+#endif
+static void ccci_mem_access_cfg(mpu_cfg_t *mpu_cfg_list, int clear)
+{
+#ifdef ENABLE_EMI_PROTECTION
+ mpu_cfg_t *curr;
+ struct emi_region_info_t region_info;
+ unsigned int curr_attr[EMI_MPU_DGROUP_NUM];
+ char buf[MPU_STR_BUF_SIZE];
+ int i;
+
+ if (NULL == mpu_cfg_list)
+ return;
+
+ SET_ACCESS_PERMISSION(curr_attr, 0,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION);
+ for (curr = mpu_cfg_list; curr->region != -1; curr++) {
+ if (clear) {
+ region_info.region = (unsigned int)curr->region;
+ region_info.start = 0;
+ region_info.end = 0;
+ for (i = 0; i < EMI_MPU_DGROUP_NUM; i++)
+ region_info.apc[i] = curr_attr[i];
+ emi_mpu_set_protection(®ion_info);
+ //emi_mpu_clear_protection(®ion_info);
+ get_mpu_attr_str(0, curr_attr, buf, MPU_STR_BUF_SIZE);
+ ALWAYS_LOG("Clr MPU:S:0x%x E:0x%x A:<%d>[0~15]%s\n",
+ 0, 0, curr->region, buf);
+ } else {
+ region_info.start = curr->start;
+ region_info.end = curr->end;
+ region_info.region = (unsigned int)curr->region;
+ for (i = 0; i < EMI_MPU_DGROUP_NUM; i++)
+ region_info.apc[i] = curr->permission[i];
+ emi_mpu_set_protection(®ion_info);
+ get_mpu_attr_str(0, curr->permission, buf, MPU_STR_BUF_SIZE);
+ ALWAYS_LOG("Set MPU:S:0x%x E:0x%x A:<%d>[0~15]%s\n",
+ curr->start, curr->end, curr->region, buf);
+ }
+ }
+#endif
+}
+
+/*--------- Implement one by one -------------------------------------------------------------------------------*/
+#ifdef ENABLE_EMI_PROTECTION
+int plat_get_padding_mpu_num(void)
+{
+ return (int)(sizeof(free_mpu_region)/sizeof(unsigned int)) - 1;
+}
+#endif
+/*---------------------------------------------------------------------------------------------------*/
+/* Global variable for share memory */
+/*---------------------------------------------------------------------------------------------------*/
+#ifndef TELE_CCCI_SUPPORT
+static unsigned int ap_md1_smem_size_at_lk_env;
+#endif
+static unsigned int ap_md1_smem_size_at_img;
+#if defined(TELE_CCCI_SUPPORT) && defined(DUMMY_AP_MODE)
+#define AP_MD1_SMEM_SIZE 0x200000
+#else
+#define AP_MD1_SMEM_SIZE 0x100000
+#endif
+#define MAX_SMEM_SIZE 0x4000000 //history: 6M-->256M-->64M
+typedef struct _smem_layout {
+ unsigned long long base_addr;
+ unsigned int ap_md1_smem_offset;
+ unsigned int ap_md1_smem_size;
+ unsigned int ap_md3_smem_offset;
+ unsigned int ap_md3_smem_size;
+ unsigned int md1_md3_smem_offset;
+ unsigned int md1_md3_smem_size;
+ unsigned int total_smem_size;
+} smem_layout_t;
+static smem_layout_t smem_info;
+
+typedef struct _ccb_layout {
+ unsigned long long ccb_data_buffer_addr;
+ unsigned int ccb_data_buffer_size;
+} ccb_layout_t;
+static ccb_layout_t ccb_info;
+#ifndef TELE_REDUCE_CODE
+unsigned int md1_phy_cap_size;
+#endif
+
+void plat_notify_secure(unsigned long long base_addr)
+{
+
+#if LK_AS_BL33 == 1
+ unsigned long addr_get;
+
+ mt_secure_call_all(MTK_SIP_LK_AMMS_MD_BASE_ADDR_AARCH32, base_addr, 0, 0, 0, 0, 0, 0);
+ addr_get = mt_secure_call_all(MTK_SIP_LK_AMMS_GET_MD_BASE_ADDR_AARCH32, 0, 0, 0, 0, 0, 0, 0);
+ ALWAYS_LOG("mt_secure_call: set_addr = 0x%x, get_addr = 0x%x\n", base_addr, addr_get);
+#endif
+}
+
+/*---------------------------------------------------------------------------------------------------*/
+/* HW remap function implement */
+/*---------------------------------------------------------------------------------------------------*/
+int plat_apply_hw_remap_for_md_ro_rw(void* info)
+{
+ modem_info_t *md_ld_info = (modem_info_t *)info;
+ plat_notify_secure(md_ld_info->base_addr);
+ return md_mem_ro_rw_remapping((unsigned int)md_ld_info->md_id, md_ld_info->base_addr);
+}
+
+int plat_apply_hw_remap_for_md_smem(void *addr, int size)
+{
+ /* For share memory final size depends on MD number, just store start address and size
+ ** actual setting will do later
+ */
+#if WITH_KERNEL_VM
+ smem_info.base_addr = kvaddr_to_paddr((void *)addr);
+#else
+ smem_info.base_addr = (unsigned long long)((unsigned long)addr);
+#endif
+ ALWAYS_LOG("smem_info.base_addr: %p ->0x%llx\n", addr, smem_info.base_addr);
+
+ return 0;
+}
+
+enum SMEM_USER_ID {
+ SMEM_USER_RAW_DFD = 0,
+ SMEM_USER_MAX,
+};
+
+int get_ccci_md_view_smem_addr_size(unsigned int user_id,
+ unsigned long long *ap_addr, unsigned int *md_addr, unsigned int *size)
+{
+ int ret = 0;
+ switch(user_id){
+ case SMEM_USER_RAW_DFD:
+ *size = CCCI_SMEM_SIZE_DFD;
+ if (ap_addr)
+ *ap_addr = smem_info.base_addr + smem_info.ap_md1_smem_offset + 0x100000;
+ else
+ ret = -2;
+ if (md_addr)
+ *md_addr = 0x40000000 + smem_info.ap_md1_smem_offset + 0x100000;
+ else
+ ret = -3;
+ break;
+ default:
+ ret = -1;
+ }
+ if (ret >= 0)
+ ALWAYS_LOG("[ccci]get_md_view_smem: user_id = 0x%x, ap_addr = 0x%llx, md_addr = 0x%x, size = 0x%x\n",
+ user_id, *ap_addr, *md_addr, *size);
+ else
+ ALWAYS_LOG("[ccci]get_md_view_smem: param error, ret = %d\n", ret);
+ return ret;
+}
+
+/*---------------------------------------------------------------------------------------------------*/
+/* check header info collection by plat_post_hdr_info */
+/*---------------------------------------------------------------------------------------------------*/
+void plat_post_hdr_info(void* hdr, int ver, int id)
+{
+ if (id == MD_SYS1) {
+ ap_md1_smem_size_at_img = ((struct md_check_header_v6*)hdr)->ap_md_smem_size;
+ }
+}
+
+/*---------------------------------------------------------------------------------------------------*/
+/* MPU static global variable and mpu relate function implement */
+/*---------------------------------------------------------------------------------------------------*/
+#define MPU_REGION_TOTAL_NUM (16) /* = MD1+MD3 */
+static mpu_cfg_t mpu_tbl[MPU_REGION_TOTAL_NUM];
+#ifdef ENABLE_EMI_PROTECTION
+static int s_g_curr_mpu_num;
+/*
+** if set start=0x0, end=0x10000, the actural protected area will be 0x0-0x1FFFF,
+** here we use 64KB align, MPU actually request 32KB align since MT6582, but this works...
+** we assume emi_mpu_set_region_protection will round end address down to 64KB align.
+*/
+static void dump_received_pure_mpu_setting(struct image_section_desc *mem_info, int item_num)
+{
+ int i;
+ for (i =0; i < item_num; i++)
+ MPU_DBG_LOG("mpu sec dec %d: offset:%x, size:%x, mpu_attr:%x, ext_flag:%x, relate_idx:%x\n", i,
+ mem_info[i].offset, mem_info[i].size, mem_info[i].mpu_attr,
+ mem_info[i].ext_flag, mem_info[i].relate_idx);
+}
+static int find_bind_mpu_region(mpu_cfg_t *mpu_tbl_hdr, int item_num, unsigned int bind_key)
+{
+ int i;
+ for (i = 0; i < item_num; i++) {
+ if (mpu_tbl_hdr[i].relate_region == (int)bind_key)
+ return i;
+ }
+
+ return -1;
+}
+
+static int md1_mpu_setting_process(void *p_md_ld_info, void *p_mem_info, mpu_cfg_t *mpu_tbl_hdr)
+{
+ modem_info_t *md_ld_info = (modem_info_t *)p_md_ld_info;
+ struct image_section_desc *mem_info = (struct image_section_desc *)p_mem_info;
+ int normal_region_num = 0;
+ int total_region_num = 0;
+ int curr_idx = 0;
+ int i, j;
+ int all_range_region_idx = -1;
+ int bind_idx;
+ int free_region_id;
+ int didi_region_idx = -1;
+
+ /* Calculate mpu num and padding num */
+ for (i = 0; i < MPU_REGION_TOTAL_NUM; i++) {
+ if ((mem_info[i].offset == 0) && (mem_info[i].size == 0))
+ break;
+
+ if (mem_info[i].ext_flag & MD_ALL_RANGE)
+ all_range_region_idx = i;
+ if (mem_info[i].ext_flag & MD_DRDI_REGION)
+ didi_region_idx = i;
+ }
+ total_region_num = i;
+
+ dump_received_pure_mpu_setting(mem_info, total_region_num);
+
+ for (i = 0; i < total_region_num; i++) {
+ if (mem_info[i].ext_flag & (MD_DRDI_REGION|MD_ALL_RANGE|NEED_REMOVE|NEED_MPU_MORE))
+ continue;
+ /* Process normal case first */
+ if (curr_idx >= (int)(sizeof(region_mapping_at_hdr_md1)/sizeof(unsigned char))) {
+ CRITICAL_LOG("[error]md%d: mpu region too more %d\n", md_ld_info->md_id+1,
+ (int)(sizeof(region_mapping_at_hdr_md1)/sizeof(unsigned char)));
+ return -LD_ERR_PLAT_MPU_REGION_TOO_MORE;
+ }
+#if WITH_KERNEL_VM
+ mpu_tbl_hdr[curr_idx].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[i].offset;
+#else
+ mpu_tbl_hdr[curr_idx].start = (unsigned int)md_ld_info->base_addr + mem_info[i].offset;
+#endif
+ mpu_tbl_hdr[curr_idx].end = mpu_tbl_hdr[curr_idx].start + mem_info[i].size;
+ mpu_tbl_hdr[curr_idx].end = ((mpu_tbl_hdr[curr_idx].end + 0xFFFF)&(~0xFFFF)) - 1;/* 64K align */
+ mpu_attr_calculate(
+ mpu_tbl_hdr[curr_idx].permission, region_mapping_at_hdr_md1[curr_idx], mem_info[i].mpu_attr);
+ mpu_tbl_hdr[curr_idx].region = (int)region_mapping_at_hdr_md1[curr_idx];
+ mpu_tbl_hdr[curr_idx].relate_region = mem_info[i].relate_idx;
+ curr_idx++;
+ normal_region_num++;
+ }
+ if (normal_region_num != (int)(sizeof(region_mapping_at_hdr_md1)/sizeof(unsigned char))) {
+ CRITICAL_LOG("[error]md%d: mpu region not sync %d:%d\n", md_ld_info->md_id+1, normal_region_num,
+ (int)(sizeof(region_mapping_at_hdr_md1)/sizeof(unsigned char)));
+ return -LD_ERR_PLAT_MPU_REGION_NUM_NOT_SYNC;
+ }
+ for (i = 0; i < total_region_num; i++) {
+ if (mem_info[i].ext_flag & NEED_MPU_MORE) {
+ bind_idx = find_bind_mpu_region(mpu_tbl_hdr, curr_idx, mem_info[i].relate_idx);
+ if (bind_idx >= 0) {
+#if WITH_KERNEL_VM
+ mpu_tbl_hdr[curr_idx].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[i].offset;
+#else
+ mpu_tbl_hdr[curr_idx].start = (unsigned int)md_ld_info->base_addr + mem_info[i].offset;
+#endif
+ mpu_tbl_hdr[curr_idx].end = mpu_tbl_hdr[curr_idx].start + mem_info[i].size;
+ /* 64K align */
+ mpu_tbl_hdr[curr_idx].end = ((mpu_tbl_hdr[curr_idx].end + 0xFFFF)&(~0xFFFF)) - 1;
+ for (j = 0; j < EMI_MPU_DGROUP_NUM; j++)
+ mpu_tbl_hdr[curr_idx].permission[j] = mpu_tbl_hdr[bind_idx].permission[j];
+ /* setting relate region */
+ free_region_id = get_free_mpu_region();
+ if (free_region_id < 0) {
+ CRITICAL_LOG("[error]abnormal free region id %d +\n", free_region_id);
+ return -LD_ERR_PLAT_ABNORMAL_FREE_REGION;
+ }
+ mpu_tbl_hdr[curr_idx].region = free_region_id;
+ mpu_tbl_hdr[curr_idx].relate_region = mem_info[i].relate_idx;
+ mpu_tbl_hdr[bind_idx].relate_region = free_region_id;
+ curr_idx++;
+ } else {
+ CRITICAL_LOG("md%d: padding array abnormal\n", md_ld_info->md_id+1);
+ return -LD_ERR_PLAT_ABNORMAL_PAD_ARRAY;
+ }
+ }
+ }
+
+ /* Apply DRDI if needed */
+ if (didi_region_idx >= 0) {
+ get_mpu_region_default_access_att(mpu_tbl_hdr[curr_idx].permission, MPU_REGION_ID_MD_DRDI, 1);
+#if WITH_KERNEL_VM
+ mpu_tbl_hdr[curr_idx].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[didi_region_idx].offset;
+#else
+ mpu_tbl_hdr[curr_idx].start = (unsigned int)md_ld_info->base_addr + mem_info[didi_region_idx].offset;
+#endif
+ mpu_tbl_hdr[curr_idx].end = mpu_tbl_hdr[curr_idx].start + mem_info[didi_region_idx].size;
+ /* 64K align */
+ mpu_tbl_hdr[curr_idx].end = ((mpu_tbl_hdr[curr_idx].end + 0xFFFF)&(~0xFFFF)) - 1;
+ mpu_tbl_hdr[curr_idx].region = MPU_REGION_ID_MD_DRDI;
+ mpu_tbl_hdr[curr_idx].relate_region = 0;
+ curr_idx++;
+ }
+#ifndef TELE_CCCI_SUPPORT
+ /* Apply MD all range mpu protect setting */
+ free_region_id = get_md_protect_mpu_region(); //get_free_mpu_region();
+ if (free_region_id < 0) {
+ CRITICAL_LOG("[error]no more free region\n");
+ return -LD_ERR_PLAT_NO_MORE_FREE_REGION;
+ }
+ get_mpu_region_default_access_att(mpu_tbl_hdr[curr_idx].permission, free_region_id, 1);
+#if WITH_KERNEL_VM
+ mpu_tbl_hdr[curr_idx].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[all_range_region_idx].offset;
+#else
+ mpu_tbl_hdr[curr_idx].start = (unsigned int)md_ld_info->base_addr + mem_info[all_range_region_idx].offset;
+#endif
+ /*mpu_tbl_hdr[curr_idx].end = mpu_tbl_hdr[curr_idx].start + mem_info[all_range_region_idx].size;*/
+ mpu_tbl_hdr[curr_idx].end = mpu_tbl_hdr[curr_idx].start + MAX_MD_SIZE;//256 * 1024 * 1024;
+ /* 64K align */
+ mpu_tbl_hdr[curr_idx].end = ((mpu_tbl_hdr[curr_idx].end + 0xFFFF)&(~0xFFFF)) - 1;
+ mpu_tbl_hdr[curr_idx].region = free_region_id;
+ mpu_tbl_hdr[curr_idx].relate_region = 0;
+ curr_idx++;
+#endif
+ /* Clear logic relate index to 0 to mark as end */
+ for (i = 0; i < curr_idx; i++) {
+ if (mpu_tbl_hdr[i].relate_region >= LOGIC_BINDING_IDX_START)
+ mpu_tbl_hdr[i].relate_region = 0;
+ }
+ return curr_idx;
+}
+#endif
+int plat_send_mpu_info_to_platorm(void *p_md_ld_info, void *p_mem_info)
+{
+#ifdef ENABLE_EMI_PROTECTION
+ modem_info_t *md_ld_info = (modem_info_t *)p_md_ld_info;
+ struct image_section_desc *mem_info = (struct image_section_desc *)p_mem_info;
+ int md_id = md_ld_info->md_id;
+ int ret;
+ int i;
+ char buf[MPU_STR_BUF_SIZE];
+
+ if (md_id == MD_SYS1) {
+ ret = md1_mpu_setting_process(p_md_ld_info, p_mem_info, &mpu_tbl[s_g_curr_mpu_num]);
+ if (ret > 0)
+ s_g_curr_mpu_num += ret;
+ } else if (md_id == MD1_DSP) {
+ /* RO part */
+ get_mpu_region_default_access_att(mpu_tbl[s_g_curr_mpu_num].permission, MPU_REGION_ID_MD_DSP1, 1);
+#if WITH_KERNEL_VM
+ mpu_tbl[s_g_curr_mpu_num].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[0].offset;
+#else
+ mpu_tbl[s_g_curr_mpu_num].start = (unsigned int)md_ld_info->base_addr + mem_info[0].offset;
+#endif
+ mpu_tbl[s_g_curr_mpu_num].end = mpu_tbl[s_g_curr_mpu_num].start + mem_info[0].size;
+ mpu_tbl[s_g_curr_mpu_num].region = MPU_REGION_ID_MD_DSP1;
+ /* 64K align */
+ mpu_tbl[s_g_curr_mpu_num].end = ((mpu_tbl[s_g_curr_mpu_num].end + 0xFFFF)&(~0xFFFF)) - 1;
+ s_g_curr_mpu_num++;
+
+ /* RW part */
+ get_mpu_region_default_access_att(mpu_tbl[s_g_curr_mpu_num].permission, MPU_REGION_ID_MD_DSP2, 1);
+#if WITH_KERNEL_VM
+ mpu_tbl[s_g_curr_mpu_num].start = kvaddr_to_paddr((void *)md_ld_info->base_addr) + mem_info[1].offset;
+#else
+ mpu_tbl[s_g_curr_mpu_num].start = (unsigned int)md_ld_info->base_addr + mem_info[1].offset;
+#endif
+ mpu_tbl[s_g_curr_mpu_num].end = mpu_tbl[s_g_curr_mpu_num].start + mem_info[1].size;
+ mpu_tbl[s_g_curr_mpu_num].region = MPU_REGION_ID_MD_DSP2;
+ /* 64K align */
+ mpu_tbl[s_g_curr_mpu_num].end = ((mpu_tbl[s_g_curr_mpu_num].end + 0xFFFF)&(~0xFFFF)) - 1;
+ s_g_curr_mpu_num++;
+ }
+
+ for (i =0; i < s_g_curr_mpu_num; i++) {
+ get_mpu_attr_str(0, mpu_tbl[i].permission, buf, MPU_STR_BUF_SIZE);
+ MPU_DBG_LOG("plat mpu dec %d: region:%d[%d], start:0x%x, end:0x%x, attr:%s\n", i,
+ mpu_tbl[i].region, mpu_tbl[i].relate_region, mpu_tbl[i].start, mpu_tbl[i].end, buf);
+ }
+#endif
+ return 0;
+}
+
+#ifndef TELE_CCCI_SUPPORT
+static void set_ccb_gear_val(unsigned int gear_id)
+{
+ int ret;
+ char env_buf[12];
+
+ memset(env_buf, 0, sizeof(env_buf));
+ snprintf(env_buf, sizeof(env_buf), "%u", gear_id);
+ ret = set_env("md1_ccb_cap_gear", env_buf);
+ if (ret < 0) {
+ ALWAYS_LOG("set env[md1_ccb_cap_gear]fail, ret=%d\n", ret);
+ assert(0);
+ } else
+ ALWAYS_LOG("set env[md1_ccb_cap_gear]%d\n", gear_id);
+}
+
+static unsigned int get_ccb_gear_val(void)
+{
+ unsigned int md1_ccb_cap_gear;
+
+ if (g_boot_mode == META_BOOT || true == get_atm_enable_status()) {
+ ALWAYS_LOG("meta mode[md1_ccb_cap_gear]%d\n", CCB_DATA_BUF_DEFAULT_GEAR);
+ set_ccb_gear_val(CCB_DATA_BUF_DEFAULT_GEAR);
+ return CCB_DATA_BUF_DEFAULT_GEAR;
+ }
+ md1_ccb_cap_gear = str2uint(get_env("md1_ccb_cap_gear"));
+ if (md1_ccb_cap_gear != 0) {
+ ALWAYS_LOG("get env[md1_ccb_cap_gear]%d\n", md1_ccb_cap_gear);
+ return md1_ccb_cap_gear;
+ } else {
+#ifdef MTK_DYNAMIC_CCB_BUFFER_GEAR_ID
+ md1_ccb_cap_gear = MTK_DYNAMIC_CCB_BUFFER_GEAR_ID;
+#else
+ md1_ccb_cap_gear = CCB_DATA_BUF_DEFAULT_GEAR;
+#endif
+ set_ccb_gear_val(md1_ccb_cap_gear);
+ return md1_ccb_cap_gear;
+ }
+}
+#endif
+
+/*------------------------------------------------------------------------------------------------*/
+/* Suppor function for share memory calculate */
+/*------------------------------------------------------------------------------------------------*/
+static int cal_ncacheable_smem_layout(void)
+{
+#ifndef TELE_REDUCE_CODE
+ unsigned int md1_phy_cap_gear;
+
+#ifdef TELE_CCCI_SUPPORT
+ md1_phy_cap_gear = 0;
+#else
+ ap_md1_smem_size_at_lk_env = str2uint(get_env("apmd1_smem"));
+ md1_phy_cap_gear = str2uint(get_env("md1_phy_cap_gear"));
+ ALWAYS_LOG("env[apmd1_smem]%x.\n", ap_md1_smem_size_at_lk_env);
+ ALWAYS_LOG("env[md1_phy_cap_gear]%x.\n", md1_phy_cap_gear);
+#endif
+#endif
+ smem_info.ap_md1_smem_offset = 0;
+#ifndef TELE_CCCI_SUPPORT
+ if (ap_md1_smem_size_at_lk_env)
+ smem_info.ap_md1_smem_size = ap_md1_smem_size_at_lk_env;
+ else
+#endif
+ if (ap_md1_smem_size_at_img)
+ smem_info.ap_md1_smem_size = ap_md1_smem_size_at_img;
+ else
+ smem_info.ap_md1_smem_size = AP_MD1_SMEM_SIZE;
+
+ smem_info.md1_md3_smem_offset = 0;
+ smem_info.md1_md3_smem_size = 0;
+ smem_info.ap_md3_smem_offset = 0;
+ smem_info.ap_md3_smem_size = 0;
+ /*
+ add dfd size to ap_md1_smem_size
+ kernel only ioremap ap_md1_smem_size
+ Otherwise,KE happen in clear_smem_region
+ */
+#ifndef DUMMY_AP_MODE
+ smem_info.ap_md1_smem_size += CCCI_SMEM_SIZE_DFD;
+#endif
+ smem_info.total_smem_size = smem_info.ap_md1_smem_size;
+#ifndef TELE_REDUCE_CODE
+ switch (md1_phy_cap_gear) {
+ case 0:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L0;
+ break;
+ case 1:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L1;
+ break;
+ case 2:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L2;
+ break;
+ case 3:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L3;
+ break;
+ case 4:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L4;
+ break;
+ default:
+ md1_phy_cap_size = CCCI_SMEM_SIZE_PHY_C_L0;
+ break;
+ }
+ ALWAYS_LOG("md1 phy capture size: %x\n", md1_phy_cap_size);
+ /* add 2M for SIB header to avoid MD MPU violation if SIB exist */
+ if(md1_phy_cap_size != CCCI_SMEM_SIZE_PHY_C_L0)
+ smem_info.ap_md1_smem_size += 2 * 1024 * 1024;
+ smem_info.total_smem_size += md1_phy_cap_size;
+#endif
+ ALWAYS_LOG("smem_info.base_addr: %llx\n", smem_info.base_addr);
+ ALWAYS_LOG("smem_info.ap_md1_smem_offset: %x\n", smem_info.ap_md1_smem_offset);
+ ALWAYS_LOG("smem_info.ap_md1_smem_size: %x\n", smem_info.ap_md1_smem_size);
+#ifndef TELE_CCCI_SUPPORT
+ ALWAYS_LOG("smem_info.ap_md3_smem_offset: %x\n", smem_info.ap_md3_smem_offset);
+ ALWAYS_LOG("smem_info.ap_md3_smem_size: %x\n", smem_info.ap_md3_smem_size);
+ ALWAYS_LOG("smem_info.md1_md3_smem_offset: %x\n", smem_info.md1_md3_smem_offset);
+ ALWAYS_LOG("smem_info.md1_md3_smem_size: %x\n", smem_info.md1_md3_smem_size);
+#endif
+ ALWAYS_LOG("smem_info.total_smem_size: %x\n", smem_info.total_smem_size);
+
+ return (int)smem_info.total_smem_size;
+
+}
+
+static int cal_share_mem_layout(int load_flag)
+{
+#ifndef TELE_CCCI_SUPPORT
+ unsigned int md1_ccb_cap_gear;
+#endif
+ unsigned int md1_bank4_cache_offset;
+ unsigned int md1_ccb_size = CCB_DATA_BUF_SIZE;
+ unsigned char * ccb_data_buf = NULL;
+#ifndef TELE_CCCI_SUPPORT
+ md1_ccb_cap_gear = get_ccb_gear_val();
+ switch(md1_ccb_cap_gear)
+ {
+ case 0: /* none, using default*/
+ md1_ccb_size = CCB_DATA_BUF_SIZE;
+ break;
+ case 1:
+ md1_ccb_size = 22 * 1024 * 1024;
+ break;
+ case 2:
+ md1_ccb_size = 12 * 1024 * 1024;
+ break;
+ case 3:
+ md1_ccb_size = 0 * 1024 * 1024;
+ break;
+ case 11:
+ md1_ccb_size = 4 * 1024 * 1024;
+ break;
+ default:
+ md1_ccb_size = CCB_DATA_BUF_SIZE;
+ break;
+ }
+#endif
+ ALWAYS_LOG("allocate ccb data buffer0x%x\n", md1_ccb_size);
+#ifdef TELE_CCCI_SUPPORT
+ if (md1_ccb_size != 0)
+ ccb_data_buf = resv_named_memory("md_smem_cache", md1_ccb_size);
+#else
+ if (md1_ccb_size != 0)
+ ccb_data_buf = ccci_request_mem(md1_ccb_size, 0x80000000LL, 0x2000000L);
+#endif
+ if (ccb_data_buf == NULL) {
+ ccb_info.ccb_data_buffer_addr = 0;
+ ccb_info.ccb_data_buffer_size = 0;
+ CRITICAL_LOG("allocate ccb data buffer share memory fail\n");
+ } else {
+#if WITH_KERNEL_VM
+ ccb_info.ccb_data_buffer_addr = kvaddr_to_paddr((void *)ccb_data_buf);
+#else
+ ccb_info.ccb_data_buffer_addr = (unsigned long long)((unsigned long)ccb_data_buf);
+#endif
+ ccb_info.ccb_data_buffer_size = md1_ccb_size;
+
+ if (insert_ccci_tag_inf("ccb_info", (char*)&ccb_info, sizeof(ccb_layout_t)) < 0)
+ CRITICAL_LOG("insert ccb_info fail\n");
+
+ ALWAYS_LOG("ccb_info.ccb_data_buffer_addr: 0x%llx\n", ccb_info.ccb_data_buffer_addr);
+ ALWAYS_LOG("ccb_info.ccb_data_buffer_size: %x\n", ccb_info.ccb_data_buffer_size);
+ /* CCB must in last 32M */
+
+ md1_bank4_cache_offset = 224 * 1024 * 1024;
+ if (insert_ccci_tag_inf("md1_smem_cahce_offset", (char*)&md1_bank4_cache_offset,
+ sizeof(md1_bank4_cache_offset)) < 0)
+ CRITICAL_LOG("insert md1_smem_cahce_offset fail\n");
+ }
+ keep_md_cache_memory(ccb_info.ccb_data_buffer_addr, ccb_info.ccb_data_buffer_size);
+
+ /* insert share memory layout to lk info */
+ ALWAYS_LOG("smem_info.total_smem_size: %x\n", smem_info.total_smem_size);
+ if (insert_ccci_tag_inf("smem_layout", (char*)&smem_info, sizeof(smem_layout_t)) < 0)
+ ALWAYS_LOG("insert smem_layout fail\n");
+#ifndef TELE_REDUCE_CODE
+ ALWAYS_LOG("md1 phy capture size: %x\n", md1_phy_cap_size);
+ if (insert_ccci_tag_inf("md1_phy_cap", (char*)&md1_phy_cap_size, sizeof(md1_phy_cap_size)) < 0)
+ CRITICAL_LOG("insert md1_phy_cap fail\n");
+#endif
+ return (int)smem_info.total_smem_size;
+}
+#ifdef DUMMY_AP_MODE
+static void boot_to_dummy_ap_mode(int load_md_flag);
+#endif
+/*------------------------------------------------------------------------------------------------*/
+/* Note: This function using global variable
+** if set start=0x0, end=0x10000, the actural protected area will be 0x0-0x1FFFF,
+** here we use 64KB align, MPU actually request 32KB align since MT6582, but this works...
+** we assume emi_mpu_set_region_protection will round end address down to 64KB align.
+*/
+int plat_apply_platform_setting(int load_md_flag)
+{
+ int smem_final_size = 0;
+
+#ifdef DUMMY_AP_MODE
+ /* This function will never return */
+ ALWAYS_LOG("boot to dummy ap mode!!!\n");
+ boot_to_dummy_ap_mode(load_md_flag);
+ return 0;
+#endif
+
+ /* Check loading validation */
+ if (((load_md_flag & (1<<MD_SYS1)) == 0) && (load_md_flag & (1<<MD_SYS3))) {
+ CRITICAL_LOG("md3 depends on md1,but md1 not loaded\n");
+ return -LD_ERR_PLAT_MD1_NOT_RDY;
+ }
+ if ((load_md_flag & ((1<<MD_SYS1)|(1<<MD_SYS3))) == 0) {
+ CRITICAL_LOG("both md1 and md3 not enable\n");
+ return 0;
+ }
+#ifdef REQUEST_SMEM_IN_LK
+ smem_final_size = cal_share_mem_layout(load_md_flag);
+#endif
+#ifdef ENABLE_EMI_PROTECTION
+ ALWAYS_LOG("ap md1 share mem MPU need configure\n");
+ mpu_tbl[s_g_curr_mpu_num].region = MPU_REGION_ID_MD1_SMEM;
+ get_mpu_region_default_access_att(mpu_tbl[s_g_curr_mpu_num].permission, MPU_REGION_ID_MD1_SMEM, 0);
+ mpu_tbl[s_g_curr_mpu_num].start = (unsigned int)smem_info.base_addr + smem_info.ap_md1_smem_offset;
+ mpu_tbl[s_g_curr_mpu_num].end = (unsigned int)smem_info.base_addr + smem_info.ap_md1_smem_offset
+ + smem_final_size;
+ mpu_tbl[s_g_curr_mpu_num].end = ((mpu_tbl[s_g_curr_mpu_num].end + 0xFFFF)&(~0xFFFF)) - 1;
+ s_g_curr_mpu_num++;
+
+ /* add for ccb data buffer mpu */
+ mpu_tbl[s_g_curr_mpu_num].region = MPU_REGION_ID_MD1_CCB;
+ get_mpu_region_default_access_att(mpu_tbl[s_g_curr_mpu_num].permission, MPU_REGION_ID_MD1_CCB, 0);
+ mpu_tbl[s_g_curr_mpu_num].start = (unsigned int)ccb_info.ccb_data_buffer_addr;
+ mpu_tbl[s_g_curr_mpu_num].end = (unsigned int)ccb_info.ccb_data_buffer_addr + ccb_info.ccb_data_buffer_size;
+ mpu_tbl[s_g_curr_mpu_num].end = ((mpu_tbl[s_g_curr_mpu_num].end + 0xFFFF)&(~0xFFFF)) - 1;
+ s_g_curr_mpu_num++;
+
+
+ mpu_tbl[s_g_curr_mpu_num].region = -1; /* mark for end */
+ /* Insert mpu tag info */
+ if (insert_ccci_tag_inf("md_mpu_inf", (char*)mpu_tbl, sizeof(mpu_cfg_t)*s_g_curr_mpu_num) < 0)
+ CRITICAL_LOG("insert md_mpu_inf fail\n");
+ if (insert_ccci_tag_inf("md_mpu_num", (char*)&s_g_curr_mpu_num, sizeof(int)) < 0)
+ CRITICAL_LOG("insert md_mpu_num fail\n");
+#endif
+ /* Apply all MPU setting */
+ ccci_mem_access_cfg(mpu_tbl, 0);
+#ifdef REQUEST_SMEM_IN_LK
+ /* Apply share memory HW remap setting and lock it */
+ if (load_md_flag & (1<<MD_SYS1)) {
+ md_smem_rw_remapping(MD_SYS1, (smem_info.base_addr + smem_info.ap_md1_smem_offset));
+ /* remapping CCB to last 32M in bank4 */
+ md_bank4_remapping_by_slot(MD_SYS1, ccb_info.ccb_data_buffer_addr, 7);
+ }
+#endif
+ return smem_final_size;
+}
+
+/*------------------------------------------------------------------------------------------------*/
+/* platform configure setting info. */
+/*------------------------------------------------------------------------------------------------*/
+long long plat_ccci_get_ld_md_plat_setting(const char cfg_name[])
+{
+ if (strcmp(cfg_name, "share_memory_size") == 0) {
+
+#ifdef DUMMY_AP_MODE
+ return 0x200000;
+#endif
+#ifdef TELE_CCCI_SUPPORT
+ return (long long)(cal_ncacheable_smem_layout());
+#else
+ return (long long)(MAX_SMEM_SIZE);
+#endif
+ }
+
+ if (strcmp(cfg_name, "share_mem_limit") == 0)
+ return 0x80000000LL;
+
+ if (strcmp(cfg_name, "ro_rw_mem_limit") == 0) {
+#ifdef DUMMY_AP_MODE
+ return 0xA0000000LL;
+#endif
+ return 0xC0000000LL;
+ }
+
+ if (strcmp(cfg_name, "ro_rw_mem_align") == 0)
+ return 0x2000000LL;
+
+ if (strcmp(cfg_name, "share_mem_align") == 0)
+ return 0x2000000LL;
+
+ if (strcmp(cfg_name, "ld_version") == 0) {
+
+#ifdef DUMMY_AP_MODE
+ return 0x20001;
+#endif
+ return 0x20000;/* xxxx_yyyy, xxxx: main id, yyyy sub id */
+ }
+
+ if (strcmp(cfg_name, "rat_plat_ver") == 0)
+ return RAT_VER_93;
+
+ return -1LL;
+}
+
+#ifdef DUMMY_AP_MODE
+#include <platform/mt_irq.h>
+extern void dummy_ap_boot_up_md(int md_en_flag);
+extern int load_modem_image(void);
+extern int dummy_ap_irq_helper(unsigned int);
+#ifndef TELE_CCCI_SUPPORT
+/* Remember add this function to file platform.c(platform code) */
+void dummy_ap_entry(void)
+{
+ load_modem_image();
+}
+
+/* Remember add this function to file interrupts.c(platform code) */
+void dummy_ap_irq_handler(unsigned int irq)
+{
+ if (dummy_ap_irq_helper(irq)) {
+ mt_irq_ack(irq);
+ unmask_interrupt(irq);
+ }
+}
+#endif
+void boot_to_dummy_ap_mode(int load_md_flag)
+{
+ md_smem_rw_remapping(MD_SYS1, smem_info.base_addr);
+ /* Before boot dummy AP, clear share memory */
+ memset((void*)((unsigned long)smem_info.base_addr), 0, 0x100000);
+
+ dummy_ap_boot_up_md(load_md_flag);
+}
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/cert.h b/src/bsp/lk/platform/mt2731/drivers/md/cert.h
new file mode 100644
index 0000000..c75af8b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/cert.h
@@ -0,0 +1,190 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#ifndef _CERT_H_
+#define _CERT_H_
+
+//#include <pal_typedefs.h>
+
+#define ASN_ID_SIZE 1
+#define MAX_OID_LEN (64)
+#define MAX_OID_SINGLE_NODE_LEN (4)
+#define MAX_RSA_BYTE_LEN (256)
+
+#define PUBK_DER_OBJ_SIZE (0x10f)
+#define BITSTRING_PADDING_SIZE (1)
+
+/* object identifier index array start */
+#define ASN_OID_SIG_IDX 0x00
+#define ASN_OID_PUBK_IDX 0x01
+#define ASN_OID_ROOTPUBK_IDX 0x02
+#define ASN_OID_IMGPUBK_IDX 0x03
+#define ASN_OID_PUBKHASH_IDX 0x04
+#define ASN_OID_IMGHASH_IDX 0x05
+#define ASN_OID_IMGVER_IDX 0x06
+#define ASN_OID_SWID_IDX 0x07
+#define ASN_OID_CERT_VER_IDX 0x08
+#define ASN_OID_CERT_APPLYSIG_IDX 0x09
+#define ASN_OID_IMGHDRHASH_IDX 0x0a
+#define ASN_OID_IMGGROUP_IDX 0x0b
+#define ASN_OID_SHA256_WITH_RSA_IDX 0x0c
+#define ASN_OID_SHA256_IDX 0x0d
+#define ASN_OID_SOCID_IDX 0x0e
+#define ASN_OID_MAX_IDX 0x0e
+/* object identifier index array end */
+
+/* definition of object identifiers */
+#define RSASSA_PSS_OID "1.2.840.113549.1.1.10"
+#define SHA256_WITH_RSA_OID "1.2.840.113549.1.1.11"
+#define PUBK_RSA_ENC_OID "1.2.840.113549.1.1.1"
+#define SHA256_OID "2.16.840.1.101.3.4.2.1"
+#define MTK_PUBK_OID_GROUP "2.16.886.2454.1"
+#define MTK_IMG_INFO_OID_GROUP "2.16.886.2454.2"
+#define MTK_CERT_OID_GROUP "2.16.886.2454.3"
+
+#define MTK_OID_ROOTPUBK "2.16.886.2454.1.1"
+#define MTK_OID_IMGPUBK "2.16.886.2454.1.2"
+#define MTK_OID_PUBKHASH "2.16.886.2454.1.3"
+
+#define MTK_OID_IMGHASH "2.16.886.2454.2.1"
+#define MTK_OID_IMGVER "2.16.886.2454.2.2"
+#define MTK_OID_SWID "2.16.886.2454.2.3"
+#define MTK_OID_IMGHDRHASH "2.16.886.2454.2.4"
+#define MTK_OID_IMGGROUP "2.16.886.2454.2.5"
+/* 2.16.886.2454.2.6 is used for image hash list item*/
+#define MTK_OID_SOCID "2.16.886.2454.2.7"
+
+#define MTK_OID_CERT_VER "2.16.886.2454.3.1"
+#define MTK_OID_CERT_APPLYSIG "2.16.886.2454.3.2"
+
+#define ASN_ID_PC_FIELD 0x20
+#define ASN_ID_P 0x00
+#define ASN_ID_C 0x20
+#define ASN_ID_CLASS_PC_FIELD 0xe0
+
+#define ASN1_TABLE_MAX_SIZE (16)
+
+#define ASN_ID_INTEGER 0x02
+#define ASN_ID_BITSTRING 0x03
+#define ASN_ID_OCTSTRING 0x04
+#define ASN_ID_NULL 0x05
+#define ASN_ID_OID 0x06
+#define ASN_ID_PRINTABLESTRING 0x13
+#define ASN_ID_SEQUENCE 0x30
+#define ASN_ID_SET 0x31
+
+/* explicit object is a special case */
+/* id & 0xe0 == 0xa0 and the tag number field is the index */
+#define ASN_ID_EXPLICIT 0xa0
+
+#define SHA256_HASH_SZ (32)
+#define RSA2048_KEY_SZ (256)
+#define RSA2048_SIG_SZ (256)
+#define ANDROID_VERIFIED_BOOT_SIG_SZ (256)
+#define ANDROID_AUTH_ATTR_TARGET_SZ (32)
+#define SOCID_LEN (32)
+
+#define GET_IMG_PUBK 0x00000001
+#define GET_IMG_VER 0x00000002
+#define GET_IMG_GROUP 0x00000004
+#define GET_SW_ID 0x00000008
+#define GET_MD_PUBK_HASH 0x00000010
+#define GET_IMG_HDR_HASH 0x00000020
+#define GET_IMG_HASH 0x00000040
+#define GET_APPLY_SIG 0x00000080
+
+
+typedef struct {
+ uint8_t n[RSA2048_KEY_SZ];
+ uint32_t n_size;
+ uint8_t e[RSA2048_KEY_SZ];
+ uint32_t e_size;
+} PUBK_T;
+
+typedef struct {
+ PUBK_T img_pubk;
+ uint8_t img_pubk_hash[SHA256_HASH_SZ];
+ uint32_t img_pubk_hash_sz;
+ uint32_t sw_id;
+ uint32_t sw_id_sz;
+ uint32_t img_ver;
+ uint32_t img_ver_sz;
+ uint32_t img_group;
+ uint32_t img_group_sz;
+} CERT1_INFO;
+
+typedef struct {
+ uint8_t img_hash[SHA256_HASH_SZ];
+ uint32_t img_hash_sz;
+ uint8_t img_hdr_hash[SHA256_HASH_SZ];
+ uint32_t img_hdr_hash_sz;
+ uint32_t img_ver;
+ uint32_t img_ver_sz;
+ uint32_t apply_sig;
+ uint32_t apply_sig_sz;
+ uint8_t socid[SOCID_LEN * 2];
+ uint32_t socid_sz;
+} CERT2_INFO;
+
+typedef struct {
+ PUBK_T img_pubk;
+ uint8_t img_sig[ANDROID_VERIFIED_BOOT_SIG_SZ];
+ uint32_t img_sig_sz;
+ uint8_t *auth_attr;
+ uint32_t auth_attr_sz;
+ uint8_t auth_attr_target[ANDROID_AUTH_ATTR_TARGET_SZ];
+ uint32_t auth_attr_target_sz;
+ uint32_t auth_attr_img_len;
+ uint32_t auth_attr_img_len_sz;
+} VERIFIED_BOOT_SIG_INFO;
+
+int key_hash_vfy(uint8_t *buf,
+ uint32_t buf_sz,
+ PUBK_T *pubk);
+
+
+int cert1_verify(uint8_t *cert,
+ uint32_t cert_img_siz,
+ CERT1_INFO *cert1_info);
+
+
+int cert2_verify(uint8_t *cert,
+ uint32_t cert_img_siz,
+ CERT1_INFO *cert1_info,
+ CERT2_INFO *cert2_info,
+ uint32_t oem_opt);
+
+int getkeyfromblob(void);
+
+#endif /* _CERT_H_ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/cert_engine.c b/src/bsp/lk/platform/mt2731/drivers/md/cert_engine.c
new file mode 100644
index 0000000..a00eac0
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/cert_engine.c
@@ -0,0 +1,1780 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#include "sec_dbg.h"
+#include "sec_fuse.h"
+#include "cert.h"
+#include "m1.h"
+#include "img_hdr.h"
+#include "cutils.h"
+#include "sha256.h"
+#include <string.h>
+#include "rsa.h"
+#include "sec_fuse.h"
+#include <libfdt.h>
+#include <image.h>
+#include <trace.h>
+#include <rsa.h>
+#include <debug.h>
+
+#define BUF_SIZE (512)
+#define SHA256_HASH_SIZE (32)
+
+#define MOD "CERT"
+
+#define list_each_subnod(fdt, node, parent) \
+ for (node = fdt_first_subnode(fdt, parent); \
+ node >= 0; \
+ node = fdt_next_subnode(fdt, node))
+
+uint8_t *g_cert_img = NULL;
+size_t g_cert_img_size = 0;
+
+/* used by loader to set oem key prebuilt in loader for public key
+authentication */
+extern struct key_prop g_sec_oemkey;
+extern const unsigned char blob[];
+
+/* public key for cert authentication */
+uint8_t g_pubk[0x200/*OEM_PUBK_SZ*/];
+
+/* hw root of trust, public key is fused */
+/* make two pubk_hash global since preloader stack size is small */
+uint8_t g_pubk_hash[SHA256_HASH_SIZE] = {0};
+uint8_t g_pubk_hash_fuse[SHA256_HASH_SIZE] = {0};
+
+/* internal global variable to cert library */
+uint8_t *g_cert_cur_pos = NULL;
+int g_cert_remaining_size = 0;
+PUBK_T g_cur_pubk;
+CT_M1_Key g_ct_key;
+
+extern CERT1_INFO g_cert1_info;
+extern CERT2_INFO g_cert2_info;
+
+const char const oid_tbl[][MAX_OID_LEN] = {
+ RSASSA_PSS_OID, PUBK_RSA_ENC_OID, MTK_OID_ROOTPUBK, MTK_OID_IMGPUBK,
+ MTK_OID_PUBKHASH, MTK_OID_IMGHASH, MTK_OID_IMGVER, MTK_OID_SWID,
+ MTK_OID_CERT_VER, MTK_OID_CERT_APPLYSIG, MTK_OID_IMGHDRHASH,
+ MTK_OID_IMGGROUP, SHA256_WITH_RSA_OID, SHA256_OID, MTK_OID_SOCID
+};
+
+uint32_t g_cert_img_type = IMG_TYPE_CERT1;
+
+#ifdef CERT_ENGINE_DEBUG
+static void dump_buffer(uint8_t *buf, uint32_t size)
+{
+ uint32_t i;
+
+ for (i = 0; i < size; i++) {
+ SMSG_ERROR("%x ", buf[i]);
+ if (0 == ((i + 1) % 16))
+ SMSG_ERROR("\n");
+ }
+ SMSG_ERROR("\n");
+
+ return;
+}
+#endif
+
+/* ================================== */
+/* security utility function: rev_buf */
+/* ================================== */
+static void rev_buf(uint8_t *buf, uint32_t buf_size)
+{
+ uint32_t i;
+ uint32_t halfsz;
+ uint8_t tmp;
+
+ if ((NULL == buf) || (buf_size <= 1))
+ return;
+
+ halfsz = buf_size >> 1;
+ for (i = 0; i < halfsz; i++) {
+ tmp = buf[i];
+ buf[i] = buf[buf_size - 1 - i];
+ buf[buf_size - 1 - i] = tmp;
+ }
+
+ return;
+}
+
+uint32_t sec_set_pubk(uint8_t *pubk, uint32_t pubk_size)
+{
+ int ret = 0;
+
+ if (pubk_size != MAX_RSA_BYTE_LEN)
+ return -1;
+
+ sec_memcpy(g_pubk, pubk, pubk_size);
+ rev_buf(g_pubk, MAX_RSA_BYTE_LEN);
+
+ return ret;
+}
+
+uint32_t sec_get_pubk(uint8_t *pubk, uint32_t pubk_size)
+{
+ int ret = 0;
+
+ if (pubk_size != MAX_RSA_BYTE_LEN)
+ return -1;
+
+ sec_memcpy(pubk, g_pubk, pubk_size);
+ rev_buf(pubk, MAX_RSA_BYTE_LEN);
+
+ return ret;
+}
+
+uint32_t sec_clear_pubk(void)
+{
+ int ret = 0;
+
+ memset(g_pubk, 0x0, MAX_RSA_BYTE_LEN);
+
+ return ret;
+}
+
+static int int_string_to_int(uint8_t *buf, uint32_t buf_sz,
+ uint32_t *val)
+{
+ int ret = 0;
+ uint32_t i = 0;
+ /* use tmp in case of buf == val */
+ uint32_t tmp = 0;
+
+ if (buf_sz > sizeof(uint32_t))
+ return 1;
+
+ for (i = 0; i < buf_sz; i++)
+ tmp = tmp << 8 | *(buf + i);
+
+ *val = tmp;
+
+ return ret;
+}
+
+uint8_t char_to_int(uint8_t c)
+{
+ if (c >= 0x30 && c <= 0x39)
+ return c - 0x30;
+ else if (c >= 0x41 && c <= 0x46)
+ return c - 0x41 + 10;
+ else if (c >= 0x61 && c <= 0x66)
+ return c - 0x61 + 10;
+ else
+ return c;
+}
+
+uint32_t string_to_hex(uint8_t *in, uint32_t in_len, \
+ uint8_t *out, uint32_t out_len)
+{
+ uint32_t ret = 0;
+ uint32_t i, j;
+
+ if (in == NULL || out == NULL) {
+ ret = 1;
+ goto end;
+ }
+
+ for (i = 0, j = 0; i < out_len, j < in_len; i++, j+=2)
+ out[i] = (char_to_int(in[j]) << 4) + char_to_int(in[j + 1]);
+
+end:
+ return ret;
+}
+
+/* ================================== */
+/* x509cert utility functions */
+/* ================================== */
+
+static int encode_OID(const char *oid, uint32_t oid_size,
+ uint8_t *oid_der, uint32_t *oid_der_size)
+{
+ int ret = 0;
+ char input_oid[MAX_OID_LEN] = {0};
+ char *ptr;
+ uint32_t val;
+ uint8_t val1;
+ uint8_t val2;
+ /* support value up which can be encoded into 16 bytes DER */
+ uint8_t final_val[MAX_OID_SINGLE_NODE_LEN];
+ uint32_t oid_der_buf_size;
+ uint32_t oid_der_cur_offset;
+
+ if (MAX_OID_LEN < oid_size) {
+ SMSG_ERROR("[%s] exceed max oid length\n", MOD);
+ ret = 1;
+ goto _error;
+ }
+
+ if (0 == *oid_der_size) {
+ SMSG_ERROR("[%s] oid der buf is empty\n", MOD);
+ ret = 1;
+ goto _error;
+ }
+
+ oid_der_buf_size = *oid_der_size;
+ *oid_der_size = 0;
+ oid_der_cur_offset = 0;
+
+ sec_memcpy(input_oid, oid, oid_size);
+
+ /* encode the first 2 nodes */
+ /* oid cannot have less than 2 nodes, exception is not handled here */
+ ptr = sec_strtok(input_oid, ".");
+ val1 = sec_atoi(ptr);
+ ptr = sec_strtok(NULL, ".");
+ val2 = sec_atoi(ptr);
+ oid_der[oid_der_cur_offset] = val1 * 40 + val2;
+
+ /* the first 2 nodes are always encoded into 1 byte */
+ oid_der_cur_offset++;
+ (*oid_der_size)++;
+
+ ptr = sec_strtok(NULL, ".");
+ while (NULL != ptr) {
+ val = sec_atoi(ptr);
+ if (val < 0x80) {
+ /* can be extracted to become another function */
+ /* encoded into single byte */
+ oid_der[oid_der_cur_offset] = (uint8_t)val;
+ oid_der_cur_offset++;
+ (*oid_der_size)++;
+ if (oid_der_cur_offset >= oid_der_buf_size)
+ goto _end;
+ } else {
+ /* can be extracted to become another function */
+ /* encoded into multiple bytes */
+ int num_of_bytes = 0;
+ int i;
+ while (val >> (num_of_bytes * 8))
+ num_of_bytes++;
+ /* add exception handling to handle buffer overflow issue */
+ for (i = 0; i < num_of_bytes; i++) {
+ final_val[i] = ((val >> (7 * (num_of_bytes - i - 1))) & 0x7f);
+ final_val[i] |= 0x80;
+ if (i == (num_of_bytes - 1))
+ final_val[i] &= 0x7f;
+ }
+ for (i = 0; i < num_of_bytes; i++)
+ oid_der[oid_der_cur_offset + i] = final_val[i];
+ oid_der_cur_offset += num_of_bytes;
+ *oid_der_size += num_of_bytes;
+ }
+ ptr = sec_strtok(NULL, ".");
+ }
+
+_end:
+_error:
+ return ret;
+}
+
+static int asn1_get_len(uint8_t *entry, uint32_t *entry_len_size,
+ uint32_t *entry_len)
+{
+ int ret = 0;
+ uint8_t *ptr = entry;
+ uint32_t i;
+
+ *entry_len = 0;
+ *entry_len_size = 1;
+
+ /* length field starts from the second byte of entry */
+ if ((*(entry + 1)) & 0x80) /* more than one byte is used for length */
+ *entry_len_size += ((*(entry + 1)) & 0x7f);
+
+ ptr++;
+ if (1 == *entry_len_size) /* short form */
+ *entry_len = *ptr;
+ else { /* long form */
+ for (i = 0; i < *entry_len_size - 1; i++) {
+ ptr++;
+ *entry_len = (*entry_len << 8) | (*ptr);
+ }
+ }
+
+ return ret;
+}
+
+static int asn1_get_next_obj(uint8_t id, uint8_t **obj,
+ uint32_t *len_size, uint32_t *len, uint32_t bypass_mode)
+{
+ int ret = 0;
+ size_t cur_obj_size = 0;
+ uint32_t expected_len = 0;
+
+ if (g_cert_remaining_size <= 0) {
+ SMSG_ERROR("[%s] end of cert, not found:\n", MOD);
+ ret = 1;
+ return ret;
+ }
+
+ SMSG_DEBUG("[%s] asn1_get_next_obj(16 bytes)(0x%lx):\n", MOD,
+ g_cert_cur_pos - g_cert_img);
+
+#ifdef CERT_ENGINE_DEBUG
+ dump_buffer(g_cert_cur_pos, 16);
+#endif
+
+ if (*len)
+ expected_len = *len;
+
+ *len_size = 0;
+ *len = 0;
+
+ ret = asn1_get_len(g_cert_cur_pos, len_size, len);
+ if (ret)
+ return ret;
+
+ /* id does not match, this is not the entry we want */
+ if (id != *g_cert_cur_pos)
+ ret = 1;
+
+ /* length does not match, this is not the entry we want */
+ if (expected_len && (expected_len != *len))
+ ret = 1;
+
+ switch (bypass_mode) {
+ case 0:
+ SMSG_TRACE("[%s] asn1_get_next_obj, traverse mode\n", MOD);
+ if (ASN_ID_C == ((*g_cert_cur_pos) & ASN_ID_PC_FIELD))
+ cur_obj_size = ASN_ID_SIZE + *len_size;
+ else
+ cur_obj_size = ASN_ID_SIZE + *len_size + *len;
+ break;
+ case 1:
+ SMSG_TRACE("[%s] asn1_get_next_obj, enforce in\n", MOD);
+ /* go into the structure directly */
+ cur_obj_size = ASN_ID_SIZE + *len_size;
+ if (*g_cert_cur_pos == ASN_ID_BITSTRING)
+ cur_obj_size += BITSTRING_PADDING_SIZE;
+ break;
+ case 2:
+ SMSG_TRACE("[%s] asn1_get_next_obj, enforce next\n", MOD);
+ cur_obj_size = ASN_ID_SIZE + *len_size + *len;
+ break;
+ default:
+ SMSG_TRACE("[%s] asn1_get_next_obj, unknown mode\n", MOD);
+ ret = 1;
+ }
+
+ SMSG_TRACE("[%s] cur_obj_size = 0x%lx\n", MOD, cur_obj_size);
+
+ *obj = g_cert_cur_pos;
+ g_cert_cur_pos += cur_obj_size;
+ g_cert_remaining_size -= cur_obj_size;
+
+ return ret;
+}
+
+/* find next oid object in buffer */
+static int asn1_get_oid(uint32_t oid_idx)
+{
+ int ret = 0;
+ uint8_t oid_der[MAX_OID_LEN] = {0};
+ uint32_t oid_der_size = MAX_OID_LEN;
+ uint32_t found = 0;
+ uint8_t *cur_obj = NULL;
+
+ if ((oid_idx > ASN_OID_MAX_IDX)) {
+ ret = 1;
+ return ret;
+ }
+
+ /* convert OID from string format to DER binary format */
+ ret = encode_OID(oid_tbl[oid_idx], sizeof(oid_tbl[oid_idx]), oid_der,
+ &oid_der_size);
+ if (ret)
+ goto _error;
+
+ SMSG_DEBUG("[%s] oid = %s\n", MOD, oid_tbl[oid_idx]);
+ SMSG_DEBUG("[%s] oid der =\n", MOD);
+
+#ifdef CERT_ENGINE_DEBUG
+ dump_buffer(oid_der, oid_der_size);
+#endif
+
+ while (g_cert_remaining_size > 0) {
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_OID, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ continue;
+
+ /* compare oid */
+ ret = sec_memcmp(cur_obj + ASN_ID_SIZE + len_size, oid_der, oid_der_size);
+ if (0 == ret) {
+ found = 1;
+ break;
+ }
+ }
+
+ SMSG_DEBUG("[%s] asn1_get_oid, found = %x\n", MOD, found);
+
+ if (!found)
+ ret = 1;
+
+_error:
+ return ret;
+}
+
+/* ========================================== */
+/* asn1 engine initialization and termination */
+/* ========================================== */
+
+static void asn1_engine_init(uint8_t *cert_buf, uint32_t cert_size)
+{
+ g_cert_cur_pos = cert_buf;
+ g_cert_remaining_size = cert_size;
+
+ return;
+}
+
+static void asn1_engine_terminate(void)
+{
+ g_cert_cur_pos = NULL;
+ g_cert_remaining_size = 0;
+
+ return;
+}
+
+/* ===================================== */
+/* extract raw data from asn1_der binary */
+/* ===================================== */
+static int asn1_get_int_string(uint8_t *cur_obj, uint8_t *out_buf,
+ uint32_t *out_buf_size)
+{
+ int ret = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ ret = asn1_get_len(cur_obj, &len_size, &len);
+ if (ret)
+ goto _end;
+
+ /* if bit 7 of the MSB is 1, then 0x00 is padded to the beginning of data */
+ if ((*(cur_obj + ASN_ID_SIZE + len_size) == 0x00) &&
+ (*(cur_obj + ASN_ID_SIZE + len_size + 1) & 0x80)) {
+ *out_buf_size = len - 1;
+ sec_memcpy(out_buf, cur_obj + ASN_ID_SIZE + len_size + 1, *out_buf_size);
+ } else {
+ *out_buf_size = len;
+ sec_memcpy(out_buf, cur_obj + ASN_ID_SIZE + len_size, *out_buf_size);
+ }
+
+_end:
+ return ret;
+}
+
+static int asn1_get_bitstring(uint8_t *cur_obj, uint8_t *out_buf,
+ uint32_t *out_buf_size)
+{
+ int ret = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ ret = asn1_get_len(cur_obj, &len_size, &len);
+ if (ret)
+ goto _end;
+
+ /* the first byte in bitstring object is the bits used in the last byte */
+ /* will always be 0 in our case, so ignore it */
+ *out_buf_size = len - 1;
+ sec_memcpy(out_buf, cur_obj + ASN_ID_SIZE + len_size + 1, *out_buf_size);
+
+_end:
+ return ret;
+}
+
+static int asn1_get_printable_string(uint8_t *cur_obj,
+ uint8_t *out_buf, uint32_t *out_buf_size)
+{
+ int ret = 0;
+
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ ret = asn1_get_len(cur_obj, &len_size, &len);
+ if (ret)
+ goto _end;
+
+ *out_buf_size = len;
+ sec_memcpy(out_buf, cur_obj + ASN_ID_SIZE + len_size, *out_buf_size);
+
+_end:
+ return ret;
+}
+
+static int asn1_get_octet_string(uint8_t *cur_obj, uint8_t *out_buf,
+ uint32_t *out_buf_size)
+{
+ int ret = 0;
+
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ ret = asn1_get_len(cur_obj, &len_size, &len);
+ if (ret)
+ goto _end;
+
+ *out_buf_size = len;
+ sec_memcpy(out_buf, cur_obj + ASN_ID_SIZE + len_size, *out_buf_size);
+
+_end:
+ return ret;
+}
+
+static int asn1_get_sequence(uint8_t *cur_obj, uint8_t **out_buf,
+ uint32_t *out_buf_size)
+{
+ int ret = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+
+ ret = asn1_get_len(cur_obj, &len_size, &len);
+ if (ret)
+ goto _end;
+
+ /* only pass address, do not copy to save space */
+ *out_buf = cur_obj;
+ *out_buf_size = ASN_ID_SIZE + len_size + len;
+
+_end:
+ return ret;
+}
+
+/* ========================================= */
+/* common function for cert1/cert2/cert_sv5 */
+/* ========================================= */
+static int cert_get_pubk_common(PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ ret = asn1_get_oid(ASN_OID_PUBK_IDX);
+ if (ret)
+ return ret;
+
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_NULL, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+
+ len = PUBK_DER_OBJ_SIZE; /* expected length of public key */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 1);
+ if (ret)
+ return ret;
+
+ /* a SEQUENCE */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_SEQUENCE, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+
+ /* INTEGER: n */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_int_string(cur_obj, pubk->n, &(pubk->n_size));
+ if (ret)
+ return ret;
+
+#ifdef CERT_ENGINE_DEBUG
+ SMSG_DEBUG("[%s] n =\n", MOD);
+ dump_buffer(pubk->n, pubk->n_size);
+#endif
+
+ /* INTEGER: e */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_int_string(cur_obj, pubk->e, &(pubk->e_size));
+ if (ret)
+ return ret;
+
+#ifdef CERT_ENGINE_DEBUG
+ SMSG_DEBUG("[%s] e =\n", MOD);
+ dump_buffer(pubk->e, pubk->e_size);
+#endif
+
+ return ret;
+}
+
+/* ========================================= */
+/* common function for cert1/cert2/cert_sv5 */
+/* ========================================= */
+static int cert_get_pubk(PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t found = 0;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = cert_get_pubk_common(pubk);
+ if (0 == ret)
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+/* ========================================= */
+/* common function for cert1/cert2/cert_sv5 */
+/* ========================================= */
+static int cert_get_sig(uint8_t *sig, uint32_t *sig_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_SIG_IDX);
+ if (ret)
+ break;
+
+ /* a SEQUENCE for pss param */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_SEQUENCE, &cur_obj, &len_size, &len, 2);
+ if (ret)
+ continue;
+
+ /* BITSTRING: signature */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ continue;
+ ret = asn1_get_bitstring(cur_obj, sig, sig_size);
+ if (ret)
+ continue;
+
+#ifdef CERT_ENGINE_DEBUG
+ SMSG_DEBUG("[%s] sig =\n", MOD);
+ dump_buffer((uint8_t *)sig, *sig_size);
+#endif
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+/* ========================================= */
+/* common function for cert1/cert2/cert_sv5 */
+/* ========================================= */
+static int cert_get_tbs_certificate(uint8_t **buf, uint32_t *buf_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_SEQUENCE, &cur_obj, &len_size, &len, 1);
+ if (ret)
+ continue;
+
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_SEQUENCE, &cur_obj, &len_size, &len, 2);
+ if (ret)
+ continue;
+
+ ret = asn1_get_sequence(cur_obj, buf, buf_size);
+ if (ret)
+ continue;
+
+#ifdef CERT_ENGINE_DEBUG
+ dump_buffer(*buf, *buf_size);
+#endif
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+/* ============================================================ */
+/* extract pubk2 from cert1 extensions: cert1 specific function */
+/* ============================================================ */
+static int cert_get_pubk2(PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t found = 0;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_IMGPUBK_IDX);
+ if (ret)
+ break;
+
+ ret = cert_get_pubk_common(pubk);
+ if (0 == ret)
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+static int cert_get_img_hdr_hash(uint8_t *img_hdr_hash,
+ uint32_t *img_hdr_hash_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ /* global variable for image loading, should not be used by library directly */
+ /* user to this library should prepare cert buffer */
+ /* please take these variables as input to cert library */
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_IMGHDRHASH_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: imgHash */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_bitstring(cur_obj, img_hdr_hash, img_hdr_hash_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+
+static int cert_get_img_hash(uint8_t *img_hash,
+ uint32_t *img_hash_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ /* global variable for image loading, should not be used by library directly */
+ /* user to this library should prepare cert buffer */
+ /* please take these variables as input to cert library */
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_IMGHASH_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: imgHash */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_bitstring(cur_obj, img_hash, img_hash_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+int cert_get_socid(uint8_t *socid,
+ uint32_t *socid_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ /* global variable for image loading, should not be used by library directly */
+ /* user to this library should prepare cert buffer */
+ /* please take these variables as input to cert library */
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_SOCID_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: imgHash */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_PRINTABLESTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_printable_string(cur_obj, socid, socid_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+static int cert_get_img_ver(uint8_t *img_ver, uint32_t *img_ver_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_IMGVER_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: imgVer */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_int_string(cur_obj, img_ver, img_ver_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+static int cert_get_sw_id(uint8_t *sw_id, uint32_t *sw_id_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_SWID_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: swID */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_int_string(cur_obj, sw_id, sw_id_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+static int cert_get_img_group(uint8_t *img_group,
+ uint32_t *img_group_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should
+ check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_IMGGROUP_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: swID */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_int_string(cur_obj, img_group, img_group_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+static int cert_get_apply_sig(uint8_t *apply_sig,
+ uint32_t *apply_sig_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_CERT_APPLYSIG_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: applySig */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_INTEGER, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+
+ ret = asn1_get_int_string(cur_obj, apply_sig, apply_sig_size);
+ if (ret)
+ continue;
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+int cert_get_pubk_hash(uint8_t *pubk_hash, uint32_t *pubk_hash_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_PUBKHASH_IDX);
+ if (ret)
+ break;
+
+ /* INTEGER: pubkHash */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ return ret;
+ ret = asn1_get_bitstring(cur_obj, pubk_hash, pubk_hash_size);
+ if (ret)
+ continue;
+
+#ifdef CERT_ENGINE_DEBUG
+ SMSG_DEBUG("[%s] pubk_hash =\n", MOD);
+ dump_buffer(pubk_hash, *pubk_hash_size);
+#endif
+
+ found = 1;
+ }//end of while (0 == found)
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+/* ========================= */
+/* public key authentication */
+/* ========================= */
+static int cert_get_ct_key(CT_M1_Key *m1_key, uint32_t *m1_key_size)
+{
+ int ret = 0;
+ uint32_t found = 0;
+ uint32_t len_size = 0;
+ uint32_t len = 0;
+ uint8_t *cur_obj = NULL;
+
+ asn1_engine_init(g_cert_img, g_cert_img_size);
+
+ /* there will be multiple objects with the same OID in cert, so we should check its format */
+ while (0 == found) {
+ if (0 == g_cert_remaining_size)
+ break;
+
+ ret = asn1_get_oid(ASN_OID_ROOTPUBK_IDX);
+ if (ret)
+ break;
+
+ /* BITSTRING: CT_M1_Key */
+ len = 0; /* does not specify length */
+ ret = asn1_get_next_obj(ASN_ID_BITSTRING, &cur_obj, &len_size, &len, 0);
+ if (ret)
+ continue;
+ ret = asn1_get_bitstring(cur_obj, (uint8_t *)m1_key, m1_key_size);
+ if (ret)
+ continue;
+
+#ifdef CERT_ENGINE_DEBUG
+ dump_buffer((uint8_t *)m1_key, sizeof(CT_M1_Key));
+#endif
+
+ found = 1;
+ }
+
+ if (0 == found)
+ ret = 1;
+
+ asn1_engine_terminate();
+
+ return ret;
+}
+
+int key_hash_vfy(uint8_t *buf, uint32_t buf_sz,
+ PUBK_T *pubk)
+{
+ int ret = 0;
+ struct sha256_context s_ctx = {0};
+
+ /* compute hash of key and compare it to fuse */
+ SMSG_ERROR("[SBC] sbc_en = %d\n", efuse_sbc_enabled());
+ if (efuse_sbc_enabled()) {
+ SMSG_ERROR("[SBC] sbc_en = 1\n");
+
+ sha256_start(&s_ctx);
+ sha256_process(&s_ctx, buf, buf_sz);
+ sha256_end(&s_ctx, g_pubk_hash);
+
+ ret = efuse_get_pubk_hash(g_pubk_hash_fuse, SHA256_HASH_SIZE);
+ if (ret)
+ goto _end;
+
+ if (sec_memcmp(g_pubk_hash, g_pubk_hash_fuse, SHA256_HASH_SIZE)) {
+ ret = 1;
+ SMSG_ERROR("pubk auth fail\n");
+ uint32_t i = 0;
+ SMSG_ERROR("pubk_hash =\n");
+ for (i = 0; i < SHA256_HASH_SIZE; i++) {
+ SMSG_ERROR("0x%x ", g_pubk_hash[i]);
+ if (((i + 1) % 16) == 0)
+ SMSG_ERROR("\n");
+ }
+ SMSG_ERROR("pubk_hash_fuse =\n");
+ for (i = 0; i < SHA256_HASH_SIZE; i++) {
+ SMSG_ERROR("0x%x ", g_pubk_hash_fuse[i]);
+ if (((i + 1) % 16) == 0)
+ SMSG_ERROR("\n");
+ }
+ goto _end;
+ }
+ } else {
+ /* sw root of trust, public key is embedded in loader/DA */
+ if (sec_memcmp(g_sec_oemkey.modulus, pubk->n, pubk->n_size)) {
+ uint32_t i = 0;
+ dprintf(CRITICAL, "g_sec_oemkey =\n");
+ for (i = 0; i < pubk->n_size; i++) {
+ uint8_t value = *((uint8_t*)g_sec_oemkey.modulus + i);
+ dprintf(CRITICAL, "0x%x ", value);
+ if (((i + 1) % 16) == 0)
+ SMSG_ERROR("\n");
+ }
+ dprintf(CRITICAL, "pubk->n =\n");
+ for (i = 0; i < pubk->n_size; i++) {
+ dprintf(CRITICAL, "0x%x ", pubk->n[i]);
+ if (((i + 1) % 16) == 0)
+ dprintf(CRITICAL, "\n");
+ }
+ ret = 1;
+ dprintf(CRITICAL, "pubk auth fail\n");
+ goto _end;
+ }
+ }
+
+_end:
+ return ret;
+}
+
+int cert_ce_key_auth(CT_CE_Key *ce_key, uint32_t ce_key_size,
+ PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t i = 0;
+
+ if (pubk->e_size != ce_key->e_len) {
+ ret = 1;
+ goto _end;
+ }
+
+ for (i = 0; i < ce_key->e_len; i++) {
+ if (pubk->e[i] != ce_key->e[i]) {
+ ret = 1;
+ goto _end;
+ }
+ }
+
+ if (pubk->n_size != ce_key->n_len) {
+ ret = 1;
+ goto _end;
+ }
+
+ for (i = 0; i < ce_key->n_len; i++) {
+ if (pubk->n[i] != ce_key->n[i]) {
+ ret = 1;
+ goto _end;
+ }
+ }
+
+ ret = key_hash_vfy((uint8_t *)ce_key, ce_key_size, pubk);
+ if (ret)
+ goto _end;
+
+_end:
+ return ret;
+}
+
+static int cert_m1_key_auth(CT_M1_Key *m1_key, uint32_t m1_key_size,
+ PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t i = 0;
+
+ /* n and e in m1_key is stored in unit of 2 bytes,
+ so reversed in 2 byte unit */
+ /* if n_size or e_size is not multiple of 2, must padd 0 at
+ the beginning before comparision with m1_key */
+
+ if ((((pubk->e_size + 1) / 2)) != m1_key->e_len) {
+ ret = 1;
+ goto end;
+ }
+
+ for (i = 0; i < m1_key->e_len; i++) {
+ unsigned short e_short = 0;
+ if (pubk->e_size % 2) {
+ if (0 == i)
+ e_short = pubk->e[2 * i];
+ else
+ e_short = pubk->e[2 * i - 1] << 8 | pubk->e[2 * i];
+ } else
+ e_short = (pubk->e[2 * i] << 8) | pubk->e[2 * i + 1];
+
+ if (e_short != m1_key->e[i]) {
+ ret = 1;
+ goto end;
+ }
+ }
+
+ if ((((pubk->n_size + 1) / 2)) != m1_key->n_len) {
+ ret = 1;
+ goto end;
+ }
+
+ for (i = 0; i < m1_key->n_len; i++) {
+ unsigned short n_short = 0;
+ if (pubk->n_size % 2) {
+ if (0 == i)
+ n_short = pubk->n[2 * i];
+ else
+ n_short = pubk->n[2 * i - 1] << 8 | pubk->n[2 * i];
+ } else
+ n_short = (pubk->n[2 * i] << 8) | pubk->n[2 * i + 1];
+
+ if (n_short != m1_key->n[i]) {
+ ret = 1;
+ goto end;
+ }
+ }
+
+ ret = key_hash_vfy((uint8_t *)m1_key, m1_key_size, pubk);
+end:
+ return ret;
+}
+
+static int cert_rootpubk_auth(PUBK_T *pubk)
+{
+ int ret = 0;
+ /* size of m1 and ce key are the same */
+ uint32_t ct_key_size = sizeof(CT_M1_Key);
+
+ /* we are not sure whether it's m1 or ce, */
+ /* so we assume it's m1 and determine later with m_coeff field */
+ ret = cert_get_ct_key(&g_ct_key, &ct_key_size);
+ if (ret)
+ goto error;
+
+ if (g_ct_key.m_coeff == 0) {
+ dprintf(CRITICAL, "cert_ce_key_auth start!!\n");
+ ret = cert_ce_key_auth((CT_CE_Key *)&g_ct_key, ct_key_size, pubk);
+ if (ret)
+ goto error;
+ } else {
+ dprintf(CRITICAL, "cert_m1_key_auth start!!\n");
+ ret = cert_m1_key_auth(&g_ct_key, ct_key_size, pubk);
+ if (ret)
+ goto error;
+ }
+
+error:
+ return ret;
+}
+
+static int cert_img_pubk_auth(PUBK_T *authenticated_pubk, PUBK_T *pubk)
+{
+ int ret = 0;
+ uint32_t i = 0;
+
+ if (authenticated_pubk->n_size != pubk->n_size) {
+ ret = 1;
+ goto _error;
+ }
+
+ if (authenticated_pubk->e_size != pubk->e_size) {
+ ret = 1;
+ goto _error;
+ }
+
+ for (i = 0; i < authenticated_pubk->n_size; i++) {
+ if (authenticated_pubk->n[i] != pubk->n[i]) {
+ ret = 1;
+ goto _error;
+ }
+ }
+
+ for (i = 0; i < authenticated_pubk->e_size; i++) {
+ if (authenticated_pubk->e[i] != pubk->e[i]) {
+ ret = 1;
+ goto _error;
+ }
+ }
+
+ ret = sec_set_pubk(pubk->n, pubk->n_size);
+ if (ret)
+ goto _error;
+
+_error:
+ return ret;
+}
+
+struct algo_info {
+ int hash_len;
+ int salt_len;
+ int embits;
+};
+
+static void mgf1(uint8_t *mgfSeed, int maskdb_len, uint8_t *db)
+{
+ struct sha256_context s_ctx = {0};
+ uint8_t *p;
+ uint8_t buf[4];
+ int i;
+
+ uint8_t out[SHA256_HASH_SIZE];
+
+ p = db;
+ memset(buf, 0, 4);
+ for (i = 0;
+ i <= ((maskdb_len + (SHA256_HASH_SIZE - 1)) / SHA256_HASH_SIZE) - 1;
+ i++) {
+ buf[0] = (uint8_t)((i >> 24) & 0xff);
+ buf[1] = (uint8_t)((i >> 16) & 0xff);
+ buf[2] = (uint8_t)((i >> 8) & 0xff);
+ buf[3] = (uint8_t)((i >> 0) & 0xff);
+
+ sha256_start(&s_ctx);
+ sha256_process(&s_ctx, mgfSeed, SHA256_HASH_SIZE);
+ sha256_process(&s_ctx, buf, 4);
+ sha256_end(&s_ctx, out);
+ memcpy(p, out, SHA256_HASH_SIZE);
+ p += SHA256_HASH_SIZE;
+ }
+}
+
+static int rsa_verify_pss(const struct algo_info *algo, uint8_t *hash, uint8_t *plain)
+{
+ int em_len = algo->embits / 8;
+ int maskedDB_len = em_len - algo->hash_len - 1;
+
+ struct sha256_context s_ctx = {0};
+ uint8_t db[em_len];
+ uint8_t h_prime[algo->hash_len];
+ uint8_t *em, *maskedDB, *salt, *h;
+ uint64_t padding1;
+ int i;
+
+ em = maskedDB = plain;
+ if (*(em + em_len - 1) != 0xbc)
+ return -1; /* rightmost octet of em doesn't not equal to 0xbc */
+
+ h = em + maskedDB_len; /* H start pointer in em */
+ if ((*maskedDB & (0xff << (8 - (8 * em_len - (algo->embits - 1))))) != 0)
+ return -1;
+
+ mgf1(h, maskedDB_len, db);
+
+ /* TODO: xor 4 bytes a time */
+ for (i = 0; i < maskedDB_len; i++)
+ *(db + i) ^= *(maskedDB + i);
+
+ *db &= (0xff >> (8 * em_len - (algo->embits - 1)));
+ //dump_mem(db, maskedDB_len, "dump dbMask");
+
+
+ i = maskedDB_len - algo->salt_len - 1;
+ if (*(db + i) != 0x01)
+ return -1; /* padding2 last byte not equal to 0x01 */
+
+ i--;
+ for (; i >= 0; i--) {
+ if (*(db + i) != 0)
+ return -1; /* padding2 leading bytes not equal to 0x00 */
+ }
+
+ salt = db + (maskedDB_len - algo->salt_len);
+ //dump_mem(salt, algo->salt_len, "dump salt");
+
+ sha256_start(&s_ctx);
+ padding1 = 0;
+ sha256_process(&s_ctx, (uint8_t *)&padding1, 8);
+ sha256_process(&s_ctx, hash, algo->hash_len);
+ sha256_process(&s_ctx, salt, algo->salt_len);
+ sha256_end(&s_ctx, h_prime);
+
+ //dump_mem(h, algo->hash_len, "dump H");
+ //dump_mem(h_prime, algo->hash_len, "dump H'");
+
+ if (memcmp(h, h_prime, algo->hash_len))
+ return -1;
+
+ return 0;
+}
+
+void mod_exp_65537_mont(uintptr_t *r, const uintptr_t *a,
+ const struct key_prop *pkey);
+
+/* =================== */
+/* data authentication */
+/* =================== */
+static int data_auth_core(uint8_t *buf, uint32_t buf_size,
+ uint8_t *sig_buf, uint32_t sig_size)
+{
+ int ret = 0;
+ uint8_t hash[SHA256_HASH_SIZE] = {0};
+ uint8_t __attribute__((aligned(8))) sign[MAX_RSA_BYTE_LEN],
+ dec_sig[MAX_RSA_BYTE_LEN] ,rr[MAX_RSA_BYTE_LEN] = {0};
+ uint64_t n0inv;
+ struct algo_info algo = {0};
+ struct key_prop key = {0};
+
+ struct sha256_context s_ctx = {0};
+ sha256_start(&s_ctx);
+ sha256_process(&s_ctx, buf, buf_size);
+ sha256_end(&s_ctx, hash);
+
+ if (MAX_RSA_BYTE_LEN != sig_size) {
+ ret = 1;
+ goto _error;
+ }
+
+ sec_memcpy(sign, sig_buf, MAX_RSA_BYTE_LEN);
+ rev_buf(sign, MAX_RSA_BYTE_LEN);
+
+ sec_memcpy(rr, g_sec_oemkey.rr, MAX_RSA_BYTE_LEN);
+ rev_buf(rr, MAX_RSA_BYTE_LEN);
+
+ n0inv =__builtin_bswap64(g_sec_oemkey.n0inv);
+
+ key.modulus = g_pubk;
+ key.exp_len = g_sec_oemkey.exp_len;
+ key.n0inv = n0inv;
+ key.num_bits = g_sec_oemkey.num_bits;
+ key.public_exponent = g_sec_oemkey.public_exponent;
+ key.rr = rr;
+
+ mod_exp_65537_mont((uintptr_t *)dec_sig, (uintptr_t *)sign, &key);
+
+ rev_buf(dec_sig, MAX_RSA_BYTE_LEN);
+
+ algo.hash_len = SHA256_HASH_SIZE;
+ algo.salt_len = SHA256_HASH_SIZE;
+ algo.embits = MAX_RSA_BYTE_LEN * 8;
+ if (rsa_verify_pss(&algo, hash, dec_sig)) {
+ ret = 1;
+ goto _error;
+ }
+
+_error:
+ return ret;
+}
+
+static int cert_auth_core(void)
+{
+ int ret = 0;
+ uint8_t *tbs_certificate = NULL;
+ uint32_t tbs_certificate_size = 0;
+
+ uint32_t sig_size = BUF_SIZE;
+ uint8_t sig[BUF_SIZE] = {0};
+
+ ret = cert_get_tbs_certificate(&tbs_certificate, &tbs_certificate_size);
+ if (ret)
+ goto _error;
+
+ ret = cert_get_sig(sig, &sig_size);
+ if (ret)
+ goto _error;
+
+ ret = data_auth_core(tbs_certificate, tbs_certificate_size, sig, sig_size);
+ if (ret)
+ goto _error;
+
+_error:
+ return ret;
+}
+
+int get_cert1_info(uint8_t *cert, uint32_t cert_img_size,
+ uint32_t info_id)
+{
+ int ret = 0;
+ IMG_HDR_T *img_hdr = NULL;
+
+ img_hdr = (IMG_HDR_T *)cert;
+ g_cert_img = cert + img_hdr->info.hdr_size;
+ g_cert_img_size = cert_img_size - img_hdr->info.hdr_size;
+
+ if (info_id & GET_IMG_PUBK) {
+ ret = cert_get_pubk2(&(g_cert1_info.img_pubk));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_IMG_VER) {
+ ret = cert_get_img_ver((uint8_t *)&(g_cert1_info.img_ver), &(g_cert1_info.img_ver_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_IMG_GROUP) {
+ ret = cert_get_img_group((uint8_t *)&(g_cert1_info.img_group),
+ &(g_cert1_info.img_group_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_SW_ID) {
+ ret = cert_get_sw_id((uint8_t *)&(g_cert1_info.sw_id), &(g_cert1_info.sw_id_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_MD_PUBK_HASH)
+ ret = cert_get_pubk_hash(g_cert1_info.img_pubk_hash,
+ &(g_cert1_info.img_pubk_hash_sz));
+
+ return ret;
+}
+
+int get_cert2_info(uint8_t *cert, uint32_t cert_img_size,
+ uint32_t info_id)
+{
+ int ret = 0;
+ IMG_HDR_T *img_hdr = NULL;
+
+ img_hdr = (IMG_HDR_T *)cert;
+ g_cert_img = cert + img_hdr->info.hdr_size;
+ g_cert_img_size = cert_img_size - img_hdr->info.hdr_size;
+
+ if (info_id & GET_IMG_HDR_HASH) {
+ ret = cert_get_img_hdr_hash(g_cert2_info.img_hdr_hash,
+ &(g_cert2_info.img_hdr_hash_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_IMG_HASH) {
+ ret = cert_get_img_hash(g_cert2_info.img_hash, &(g_cert2_info.img_hash_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_IMG_VER) {
+ ret = cert_get_img_ver((uint8_t *)&(g_cert2_info.img_ver), &(g_cert2_info.img_ver_sz));
+ if (ret)
+ return ret;
+ }
+ if (info_id & GET_APPLY_SIG) {
+ ret = cert_get_apply_sig((uint8_t *)&(g_cert2_info.apply_sig),
+ &(g_cert2_info.apply_sig_sz));
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+
+int cert1_verify(uint8_t *cert, uint32_t cert_img_size,
+ CERT1_INFO *cert1_info)
+{
+ int ret = 0;
+ uint32_t cert_info_id = 0;
+ IMG_HDR_T *img_hdr = NULL;
+
+ memset(&g_cur_pubk, 0x0, sizeof(g_cur_pubk));
+ g_cur_pubk.n_size = sizeof(g_cur_pubk.n);
+ g_cur_pubk.e_size = sizeof(g_cur_pubk.e);
+
+ img_hdr = (IMG_HDR_T *)cert;
+ g_cert_img_type = img_hdr->info.img_type;
+ g_cert_img = cert + img_hdr->info.hdr_size;
+ g_cert_img_size = cert_img_size - img_hdr->info.hdr_size;
+
+#ifdef CERT_ENGINE_DEBUG
+ /* dump cert1/cert_md image */
+ dump_buffer(g_cert_img, g_cert_img_size);
+#endif
+
+ /* extract public key from cert, but public key will not be used until it's authenticated */
+ ret = cert_get_pubk(&g_cur_pubk);
+ if (ret)
+ goto _error;
+
+ /*Comment out by HY Lin for local test*/
+ ret = cert_rootpubk_auth(&g_cur_pubk);
+ if (ret)
+ goto _error;
+
+ ret = sec_set_pubk(g_cur_pubk.n, g_cur_pubk.n_size);
+ if (ret)
+ goto _error;
+
+ /* verify signature of cert1 */
+ ret = cert_auth_core();
+ if (ret)
+ goto _error;
+
+ cert_info_id = GET_IMG_PUBK | GET_IMG_VER | GET_IMG_GROUP | GET_SW_ID;
+ ret = get_cert1_info(cert, cert_img_size, cert_info_id);
+ if (ret)
+ goto _error;
+
+ /* only CERT_MD has public key hash */
+ if (g_cert_img_type == IMG_TYPE_CERT1_MD) {
+ ret = get_cert1_info(cert, cert_img_size, GET_MD_PUBK_HASH);
+ if (ret)
+ goto _error;
+ }
+_error:
+ return ret;
+}
+
+int cert2_verify(uint8_t *cert, uint32_t cert_img_size,
+ CERT1_INFO *cert1_info, CERT2_INFO *cert2_info, uint32_t oem_opt)
+{
+ int ret = 0;
+ uint32_t cert_info_id = 0;
+ IMG_HDR_T *img_hdr = NULL;
+
+ memset(&g_cur_pubk, 0x0, sizeof(g_cur_pubk));
+ g_cur_pubk.n_size = sizeof(g_cur_pubk.n);
+ g_cur_pubk.e_size = sizeof(g_cur_pubk.e);
+
+ img_hdr = (IMG_HDR_T *)cert;
+ g_cert_img = cert + img_hdr->info.hdr_size;
+ g_cert_img_size = cert_img_size - img_hdr->info.hdr_size;
+
+#ifdef CERT_ENGINE_DEBUG
+ /* dump cert2 image */
+ dump_buffer(g_cert_img, g_cert_img_size);
+#endif
+
+ /* extract public key from cert, but public key will not be used until it's authenticated */
+ ret = cert_get_pubk(&g_cur_pubk);
+ if (ret)
+ goto _error;
+
+ ret = cert_img_pubk_auth(&(cert1_info->img_pubk), &g_cur_pubk);
+ if (ret)
+ goto _error;
+
+ /* verify signature of cert2 */
+ ret = cert_auth_core();
+ if (ret)
+ goto _error;
+
+ /* get image hash/image version and apply_sig from cert2 extension */
+ cert_info_id = GET_IMG_HDR_HASH | GET_IMG_HASH | GET_IMG_VER | GET_APPLY_SIG;
+
+ ret = get_cert2_info(cert, cert_img_size, cert_info_id);
+ if (ret)
+ goto _error;
+
+_error:
+ return ret;
+}
+
+int getkeyfromblob(void)
+{
+ int rsa_length = RSA2048_BYTES;
+ const uint8_t *pubk ,*sign_tmp;
+ uint64_t n0inv;
+
+ int noffset, sig_node, i, tmp, len;
+ const void *sig_blob = &blob[0];
+
+ sig_node = fdt_subnode_offset(sig_blob, 0, FDT_SIG_NODE);
+ if (sig_node < 0) {
+ dprintf(CRITICAL, "No sign node (signature): %s\n",fdt_strerror(sig_node));
+ return -1;
+ }
+ list_each_subnod(sig_blob, tmp, sig_node) {
+ if (tmp >= 0) {
+ noffset = tmp;
+ } else {
+ break;
+ }
+ }
+
+ get_pubkey_info(&g_sec_oemkey, sig_blob, noffset, &len);
+
+ return 0;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/cutils.c b/src/bsp/lk/platform/mt2731/drivers/md/cutils.c
new file mode 100644
index 0000000..d5f081b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/cutils.c
@@ -0,0 +1,165 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#include "cutils.h"
+#include <stdlib.h>
+#include <string.h>
+
+/* ========================== */
+/* c utility function: memcpy */
+/* ========================== */
+void *sec_memcpy(void *dest, const void *src, size_t num)
+{
+ uint8_t *dest_ptr;
+ uint8_t *src_ptr;
+ uint32_t i;
+
+ dest_ptr = (uint8_t *)dest;
+ src_ptr = (uint8_t *)src;
+
+ for (i = 0; i < num; i++) {
+ *dest_ptr = *src_ptr;
+ dest_ptr++;
+ src_ptr++;
+ }
+
+ return dest;
+}
+
+/* ========================== */
+/* c utility function: strlen */
+/* ========================== */
+size_t sec_strlen(const char *str)
+{
+ size_t str_size = 0;
+ const char *ptr;
+
+ if (NULL == str)
+ return str_size;
+
+ ptr = str;
+ while ('\0' != *ptr) {
+ ptr++;
+ str_size++;
+ }
+
+ return str_size;
+}
+
+/* ========================== */
+/* c utility function: memcmp */
+/* ========================== */
+int sec_memcmp(const void *ptr1, const void *ptr2, size_t num)
+{
+ int ret = 0;
+ uint32_t i = 0;
+ const uint8_t *local_ptr1;
+ const uint8_t *local_ptr2;
+
+ local_ptr1 = (const uint8_t *)ptr1;
+ local_ptr2 = (const uint8_t *)ptr2;
+
+ for (i = 0; i < num; i++) {
+ if (*(local_ptr1 + i) != *(local_ptr2 + i)) {
+ ret = (*(local_ptr1 + i) > *(local_ptr2 + i)) ? 1 : -1;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/* ========================== */
+/* c utility function: atoi */
+/* ========================== */
+int sec_atoi(const char *str)
+{
+ int integer = 0;
+ const char *ptr;
+
+ if (NULL == str)
+ return 0;
+
+ ptr = str;
+ while ('\0' != *ptr) {
+ if ((*ptr >= '0') || (*ptr <= '9'))
+ integer = integer * 10 + (*ptr - '0');
+ ptr++;
+ }
+
+ return integer;
+}
+
+/* ========================== */
+/* c utility function: strtok */
+/* ========================== */
+char *sec_strtok(char *str, const char *delimiters)
+{
+ static size_t remaining_str_size = 0;
+ static char *cur_pos = NULL;
+
+ if (str) {
+ char *ptr = NULL;
+ const char *delimiter = NULL;
+ uint32_t i;
+ remaining_str_size = sec_strlen(str);
+ ptr = str;
+ for (i = 0; i < remaining_str_size; i++) {
+ delimiter = delimiters;
+ while ('\0' != *delimiter) {
+ if (*ptr == *delimiter)
+ *ptr = '\0';
+ delimiter++;
+ }
+ ptr++;
+ }
+ cur_pos = str;
+ } else {
+ if (NULL == cur_pos)
+ return cur_pos;
+
+ while ('\0' != *cur_pos) {
+ cur_pos++;
+ remaining_str_size--;
+ }
+
+ if (remaining_str_size != 0) {
+ cur_pos++;
+ remaining_str_size--;
+ } else
+ cur_pos = NULL;
+ }
+
+ return cur_pos;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/cutils.h b/src/bsp/lk/platform/mt2731/drivers/md/cutils.h
new file mode 100644
index 0000000..57091aa
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/cutils.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#ifndef _CUTILS_H_
+#define _CUTILS_H_
+
+#define TARGET (1)
+
+#if TARGET
+//typedef unsigned int size_t;
+#ifndef NULL
+#define NULL (0)
+#endif
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+#include <sys/types.h>
+
+void *sec_memcpy(void *dest, const void *src, size_t num);
+size_t sec_strlen(const char *str);
+int sec_memcmp(const void *ptr1, const void *ptr2, size_t num);
+int sec_atoi(const char *str);
+char *sec_strtok(char *str, const char *delimiters);
+
+#endif /* _CUTILS_H_ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/dummy_ap.c b/src/bsp/lk/platform/mt2731/drivers/md/dummy_ap.c
new file mode 100644
index 0000000..21d9bc5
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/dummy_ap.c
@@ -0,0 +1,675 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2016. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+//#define CTP_ENV
+#ifndef CTP_ENV
+/* Note: Pleae enable DUMMY_AP option at rule.mk if hope to use this function */
+#define TELE_CCCI_SUPPORT
+#ifdef TELE_CCCI_SUPPORT
+#include <platform/interrupts.h>
+#include <platform/mtk_wdt.h>
+#else
+#include <boot_args.h>
+#include <target/cust_key.h>
+#include <platform/upmu_common.h>
+#include <platform/upmu_hw.h>
+#endif
+#include <debug.h>
+#include <dev/uart.h>
+#include <platform/mtk_key.h>
+#include <platform/mt_gpio.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <err.h>
+#include <reg.h>
+#include <string.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_irq.h>
+#include <platform/timer.h>
+#include <sys/types.h>
+#include <arch/ops.h>
+#include <platform/spm.h>
+#include <platform/spm_mtcmos.h>
+#else
+/*CTP environment*/
+#include <gpio.h>
+#include <barriers.h>
+#include <sync_write.h>
+#include <upmu_hw.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_mtcmos.h>
+#include <efuse.h>
+
+#define dprintf(CRITICAL, fmt, args...) dbg_print("[MD]: "fmt, ##args)
+static void let_md_go(int md_id);
+static void config_md_boot_env(int md_id, int boot_mode);
+#endif /*CTP_ENV*/
+
+//------- feature option part ---------------------------------------
+//#define DEFAULT_META
+#define ENABLE_MD_RESET_SPM
+//#define ENABLE_MD_RESET_RGU
+//#define IGNORE_MD_WDT
+//#define IGNORE_MD1_WDT
+//#define IGNORE_MD2_WDT
+//#define NO_UNGATE_MD
+
+//------- enum and macro part ---------------------------------------
+enum {
+ MD_SYS1 = 0,
+ MD_SYS2,
+ MD_SYS3,
+ MD_SYS4,
+};
+
+enum {
+ AP_ONLY = -1,
+ MD1_ONLY = 0,
+ MD2_ONLY,
+ MD1_MD2,
+};
+
+#ifdef TELE_CCCI_SUPPORT
+#define INFRA_AO_BASE (INFRACFG_BASE)
+
+#define INFRA_AP2MD_DUMMY_REG 0x370
+#define INFRA_AP2MD_DUMMY_BIT 0
+
+#define INFRA_MD2PERI_PROT_EN 0x220
+#define INFRA_MD2PERI_PROT_RDY 0x228
+#define INFRA_MD2PERI_PROT_SET (0x2A0)
+#define INFRA_MD2PERI_PROT_CLR (0x2A4)
+#define INFRA_MD2PERI_PROT_BIT 6
+
+#define INFRA_PERI2MD_PROT_EN 0x220
+#define INFRA_PERI2MD_PROT_RDY 0x228
+#define INFRA_PERI2MD_PROT_SET (0x2A0)
+#define INFRA_PERI2MD_PROT_CLR (0x2A4)
+#define INFRA_PERI2MD_PROT_BIT 7
+
+#define INFRA_MISC2 (0xF0C)
+
+#define ccci_get_reg32(addr) readl(addr)
+#define ccci_set_reg32(addr, val) writel(val, addr)
+#define ccci_write32(b, a, v) writel(v, (b)+(a))//DRV_WriteReg32((b)+(a), (v))
+#define ccci_read32(b, a) readl((b)+(a))
+#define udelay(x) spin(x)
+#define mdelay(x) (udelay((x)*1000))
+#else
+#define MD1_BASE (0x20000000)
+#define ccci_write32(b, a, v) DRV_WriteReg32((b)+(a), (v))
+#define ccci_read32(b, a) DRV_Reg32((b)+(a))
+#define ccci_write16(b, a, v) DRV_WriteReg16((b)+(a), (v))
+#define ccci_read16(b, a) DRV_Reg16((b)+(a))
+#define ccci_write8(b, a, v) DRV_WriteReg8((b)+(a), (v))
+#define ccci_read8(b, a) DRV_Reg8((b)+(a))
+#endif
+
+struct sram_cfg {
+ unsigned int offset;
+ unsigned int start_bit;
+ unsigned int end_bit;
+};
+
+
+//------- IRQ ID part: mt_irq.h none, so add by ourselves----------------------
+#define GIC_PRIVATE_SIGNALS (32)
+#define MT_MD_WDT1_IRQ_ID (210+GIC_PRIVATE_SIGNALS)
+
+
+//------- register part ---------------------------------------
+#define MD1_BUS_PROTECT_VDNR_CON (INFRA_AO_BASE + 0x71C)
+#define MD1_BUS_PROTECT_SET (INFRA_AO_BASE + 0x2A0)
+#define MD1_BUS_PROTECT_CLR (INFRA_AO_BASE + 0x2A4)
+#define MD1_BUS_PROTECT_STA (INFRA_AO_BASE + 0x228)
+#define MD1_BUS_PROTECT1_SET (INFRA_AO_BASE + 0x2A8)
+#define MD1_BUS_PROTECT1_CLR (INFRA_AO_BASE + 0x2AC)
+#define MD1_BUS_PROTECT1_STA (INFRA_AO_BASE + 0x258)
+#define PROTECTION_BITMASK ((0x1 << 3)|(0x1 << 4)) // bit 3,4
+#define PROTECTION1_BITMASK (0x1 << 6)|(0x1 << 7) // bit 6,7
+
+#define MD1_SRAM_POWE1 (MD1_BASE + 0x01D8010)//(0x201D_8010 )
+#define MD1_SRAM_POWE2 (MD1_BASE + 0x6110000)//(0x2611_0000 )
+
+#define MD1_BOOT_VECTOR_EN (MD1_BASE + 0x24)//(0x20000024)
+#define MD1_META_FLAG (MD1_BASE + 0x10)//(0x20000010)
+
+#define TOPRGU_BASE (TOP_RGU_BASE)//(0x10007000)
+#define TOP_RGU_WDT_MODE (0x0)
+#define TOP_RGU_WDT_SWRST (0x14)
+#define TOP_RGU_WDT_SWSYSRST (0x18)
+#define TOP_RGU_WDT_NONRST_REG (0x20)
+#define TOP_RGU_LATCH_CONTROL (0x44)
+#define MD1_SYS (1 << 7)
+
+#define UNLOCK_KEY (0x88000000)
+
+// MD RGU PCore
+#define BASE_ADDR_MDRSTCTL (MD1_BASE + 0xF0000)//0x200F0000
+#define MD_RGU_BASE (BASE_ADDR_MDRSTCTL + 0x100)
+#define WDT_MD_MODE (0x0)
+#define WDT_MD_MODE_KEY (0x55000030)
+
+// AP view
+#define BASE_MADDR_MDTOP_PLLMIXED (MD1_BASE + 0x140000)//(0x20140000)
+#define BASE_MADDR_MDTOP_CLKSW (MD1_BASE + 0x150000)//(0x20150000)
+
+#define REG_APMIXEDSYS_AP_PLL_CON0 (APMIXED_BASE+0x0)
+
+#define REG_MDTOP_PLLMIXED_PLL_VERSION (BASE_MADDR_MDTOP_PLLMIXED)
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (BASE_MADDR_MDTOP_PLLMIXED+0x4)
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (BASE_MADDR_MDTOP_PLLMIXED+0x10)
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x40)
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x48)
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x50)
+#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x58)
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x60)
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (BASE_MADDR_MDTOP_PLLMIXED+0x64)
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (BASE_MADDR_MDTOP_PLLMIXED+0x100)
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (BASE_MADDR_MDTOP_PLLMIXED+0x104)
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (BASE_MADDR_MDTOP_PLLMIXED+0x314)
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (BASE_MADDR_MDTOP_PLLMIXED+0x318)
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY (BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+#define REG_MDTOP_CLKSW_CLKON_CTL (BASE_MADDR_MDTOP_CLKSW+0x20)
+#define REG_MDTOP_CLKSW_CLKSEL_CTL (BASE_MADDR_MDTOP_CLKSW+0x24)
+#define REG_MDTOP_CLKSW_SDF_CK_CTL (BASE_MADDR_MDTOP_CLKSW+0x28)
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (BASE_MADDR_MDTOP_CLKSW+0x84)
+
+#define MD_PLL_MAGIC_NUM 0x62930000
+
+//#define APMIXED_BASE (BASE_MADDR_APMIXEDSYS)
+#define AP_PLL_CON0 (0x0)
+#define AP_PLL_CON1 (0x4)
+#define MDPLL_CON0 (0x3A0)
+#define MDPLL_CON3 (0x3AC)
+
+#define UINT32P (volatile unsigned int *)
+
+//in mt_spm_reg.h
+#ifndef TELE_CCCI_SUPPORT
+#define SLEEP_BASE (0x10006000)
+#define POWERON_CONFIG_EN (UINT32P (SLEEP_BASE+0x0))
+#define SPM_POWER_ON_VAL1 (UINT32P (SLEEP_BASE+0x8))
+#endif
+
+//------- GPIO part ---------------------------------------
+#define GPIO_MAGIC (0x80000000)
+// -- UART
+#define NO_NEED_UART_CONFIG
+#ifndef NO_NEED_UART_CONFIG
+#define UART1_TX_GPIO_ID (GPIO96 | GPIO_MAGIC)
+#define UART1_RX_GPIO_ID (GPIO95 | GPIO_MAGIC)
+#define UART2_TX_GPIO_ID (GPIO21 | GPIO_MAGIC)
+#define UART2_RX_GPIO_ID (GPIO20 | GPIO_MAGIC)
+#define UART3_TX_GPIO_ID (GPIO151 | GPIO_MAGIC)
+#define UART3_RX_GPIO_ID (GPIO150 | GPIO_MAGIC)
+#define UART4_TX_GPIO_ID (GPIO28 | GPIO_MAGIC)
+#define UART4_RX_GPIO_ID (GPIO27 | GPIO_MAGIC)
+#endif
+
+//------- code part ---------------------------------------
+static unsigned int img_load_flag = 0;
+
+
+void md_uart_config(int type_id, int boot_mode)
+{
+#ifndef NO_NEED_UART_CONFIG
+ switch (type_id) {
+ case AP_ONLY: // for AP only
+ dprintf(CRITICAL, "md_uart_config:%d, UART1->AP_0, UART2->N/A, UART3->MD1_0, UART4->N/A\n", type_id);
+ // same as dws initial setting
+ mt_set_gpio_mode(UART1_TX_GPIO_ID, GPIO_MODE_01);
+ mt_set_gpio_mode(UART1_RX_GPIO_ID, GPIO_MODE_01);
+ mt_set_gpio_mode(UART3_TX_GPIO_ID, GPIO_MODE_06);
+ mt_set_gpio_mode(UART3_RX_GPIO_ID, GPIO_MODE_06);
+ break;
+ case MD1_ONLY: // for AP & MD1
+ case MD2_ONLY: // for AP & C2K
+ case MD1_MD2: // for both MD1 and C2K
+ if (boot_mode) {
+ dprintf(CRITICAL, "md_uart_config:%d, UART3->MD1_0, UART1->AP_0, UART2->NA/A, UART4->N/A\n", type_id);
+ mt_set_gpio_mode(UART1_TX_GPIO_ID, GPIO_MODE_01);
+ mt_set_gpio_mode(UART1_RX_GPIO_ID, GPIO_MODE_01);
+ mt_set_gpio_mode(UART3_TX_GPIO_ID, GPIO_MODE_05);
+ mt_set_gpio_mode(UART3_RX_GPIO_ID, GPIO_MODE_05);
+
+ }
+ break;
+ default:
+ break;
+ }
+#endif
+}
+
+void bus_protection_en(int md_id)
+{
+ if (md_id == MD_SYS1) {
+ /* enable protection for MD1 */
+ dprintf(CRITICAL, "enable protection for md\n");
+ DRV_WriteReg32(MD1_BUS_PROTECT_VDNR_CON, 0x7F);
+ DRV_WriteReg32(MD1_BUS_PROTECT_SET, PROTECTION1_BITMASK);
+ /* poll protection ready */
+ dprintf(CRITICAL, "wait protection ....\n");
+ while ((DRV_Reg32(MD1_BUS_PROTECT_STA)&PROTECTION1_BITMASK) != PROTECTION1_BITMASK) {
+ dprintf(CRITICAL, "0x%x\n", DRV_Reg32(MD1_BUS_PROTECT_STA));
+ }
+ DRV_WriteReg32(MD1_BUS_PROTECT_SET, PROTECTION_BITMASK);
+ dprintf(CRITICAL, "wait protection1 ....\n");
+ while ((DRV_Reg32(MD1_BUS_PROTECT_STA)&PROTECTION_BITMASK) != PROTECTION_BITMASK) {
+ dprintf(CRITICAL, "0x%x\n", DRV_Reg32(MD1_BUS_PROTECT_STA));
+ }
+ dprintf(CRITICAL, "protection enable done\n");
+
+ return;
+ }
+}
+
+void bus_protection_diable(int md_id)
+{
+ if (md_id == MD_SYS1) {
+ /* enable protection for MD1 */
+ dprintf(CRITICAL, "disable protection for md\n");
+ DRV_WriteReg32(MD1_BUS_PROTECT_CLR,
+ (PROTECTION_BITMASK|PROTECTION1_BITMASK));
+ dprintf(CRITICAL, "protection disable done\n");
+ return;
+ }
+}
+
+
+static void md1_pre_access_md_reg(void)
+{
+ unsigned int reg_val;
+ uintptr_t infra_ao_base = INFRA_AO_BASE;
+
+ /*clear dummy reg flag to access modem reg*/
+ reg_val = ccci_read32(infra_ao_base, INFRA_AP2MD_DUMMY_REG);
+ reg_val &= (~(0x1 << INFRA_AP2MD_DUMMY_BIT));
+ ccci_write32(infra_ao_base, INFRA_AP2MD_DUMMY_REG, reg_val);
+
+ dprintf(CRITICAL, "pre: ap2md dummy reg 0x%lx: 0x%X\n", INFRA_AO_BASE + INFRA_AP2MD_DUMMY_REG,
+ ccci_read32(infra_ao_base, INFRA_AP2MD_DUMMY_REG));
+
+ /*disable MD to AP*/
+ ccci_write32(infra_ao_base, INFRA_MD2PERI_PROT_SET, (0x1 << INFRA_MD2PERI_PROT_BIT));
+ while ((ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_RDY) & (0x1 << INFRA_MD2PERI_PROT_BIT))
+ != (0x1 << INFRA_MD2PERI_PROT_BIT))
+ ;
+ dprintf(CRITICAL, "md2peri: en[0x%X], rdy[0x%X]\n",
+ ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_EN),
+ ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_RDY));
+}
+
+static void md1_post_access_md_reg(void)
+{
+ unsigned int reg_val;
+ uintptr_t infra_ao_base = INFRA_AO_BASE;
+
+ /*disable AP to MD*/
+ ccci_write32(infra_ao_base, INFRA_PERI2MD_PROT_SET, (0x1 << INFRA_PERI2MD_PROT_BIT));
+ while ((ccci_read32(infra_ao_base, INFRA_PERI2MD_PROT_RDY) & (0x1 << INFRA_PERI2MD_PROT_BIT))
+ != (0x1 << INFRA_PERI2MD_PROT_BIT))
+ ;
+ dprintf(CRITICAL, "peri2md: en[0x%X], rdy[0x%X]\n",
+ ccci_read32(infra_ao_base, INFRA_PERI2MD_PROT_EN),
+ ccci_read32(infra_ao_base, INFRA_PERI2MD_PROT_RDY));
+
+ /*enable MD to AP*/
+ ccci_write32(infra_ao_base, INFRA_MD2PERI_PROT_CLR, (0x1 << INFRA_MD2PERI_PROT_BIT));
+ while ((ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_RDY) & (0x1 << INFRA_MD2PERI_PROT_BIT)))
+ ;
+ dprintf(CRITICAL, "md2peri: en[0x%X], rdy[0x%X]\n",
+ ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_EN),
+ ccci_read32(infra_ao_base, INFRA_MD2PERI_PROT_RDY));
+
+ /*set dummy reg flag and let md access AP*/
+ reg_val = ccci_read32(infra_ao_base, INFRA_AP2MD_DUMMY_REG);
+ reg_val |= (0x1 << INFRA_AP2MD_DUMMY_BIT);
+ ccci_write32(infra_ao_base, INFRA_AP2MD_DUMMY_REG, reg_val);
+ dprintf(CRITICAL, "post: ap2md dummy reg 0x%lX: 0x%X\n", INFRA_AO_BASE + INFRA_AP2MD_DUMMY_REG,
+ ccci_read32(infra_ao_base, INFRA_AP2MD_DUMMY_REG));
+}
+
+void pmic_init_sequence(void)
+{
+ dprintf(CRITICAL, "pmic_init_sequence skipped!\n");
+}
+
+static void md1_pmic_setting(void)
+{
+ // assume set in preloader
+ dprintf(CRITICAL, "md1_pmic_setting skipped!\n");
+}
+
+int md_common_setting(void)
+{
+ unsigned int reg_value;
+
+ // MD srcclkena setting: [7:4]=4'h0010, [3:0]=4'h0001
+ reg_value = ccci_read32(INFRA_AO_BASE, INFRA_MISC2);
+ reg_value &= ~(0xFF);
+ reg_value |= 0x21;
+ ccci_write32(INFRA_AO_BASE, INFRA_MISC2, reg_value);
+ dprintf(CRITICAL, "MD srcclkena setting:0x%x\n", ccci_read32(INFRA_AO_BASE, INFRA_MISC2));
+
+ pmic_init_sequence();
+
+ return 0;
+}
+
+void md_common_pll_init(void)
+{
+ // initial CLKSQ_LPF
+ ccci_write32(APMIXED_BASE, AP_PLL_CON0,
+ ccci_read32(APMIXED_BASE, AP_PLL_CON0) | (0x1 << 1));
+ udelay(100);
+}
+
+void md1_pll_init(void)
+{
+ md_common_pll_init();
+
+ dprintf(CRITICAL, "Read MD PLL version:0x%x(@0x%lx)\n",
+ ccci_read32(REG_MDTOP_PLLMIXED_PLL_VERSION, 0),
+ REG_MDTOP_PLLMIXED_PLL_VERSION);
+
+ // Default md_srclkena_ack settle time = 136T 32K
+ ccci_write32(REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL, 0, 0x02020E88);
+
+ ccci_write32(REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0, 0, 0x801713B1); // fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+ ccci_write32(REG_MDTOP_PLLMIXED_MDTXPLL_CTL0, 0, 0x80171400); // 300MHz /* Fvco = 2400M */
+ ccci_write32(REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0, 0, 0x80229E00); // 400MHz /* Fvco = 3600M */
+ ccci_write32(REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0, 0, 0x80204E00); // 672MHz /* Fvco = 3360M */
+ ccci_write32(REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0, 0, 0x80213C00); // 864MHz /* Fvco = 3456M */
+
+ /*
+ * Polling until MDMCUPLL complete frequency adjustment
+ * Once MDMCUPLL complete, other PLL should complete too
+ */
+ while ((ccci_read32(REG_MDTOP_PLLMIXED_MDMCUPLL_STS, 0) >> 14) & 0x1) {};
+
+ /* Default disable BPI /7 clock */
+ ccci_write32(REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1, 0,
+ (ccci_read32(REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1, 0)&(~(0x80))));
+
+ /*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+ ccci_write32(REG_MDTOP_PLLMIXED_MDPLL_CTL1, 0, 0x4C43100);
+
+ /* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+ other PLL ON controlled by HW" */
+ ccci_write32(REG_MDTOP_PLLMIXED_PLL_ON_CTL, 0, 0x100010);
+
+ /*
+ * Wait MD bus clock ready
+ * Once MD bus ready, other clock should be ready too
+ * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ */
+ while ((ccci_read32(REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS, 0)&0x8000) != 0x8000) {};
+
+ // Switch MDMCU & MD BUS clock to PLL frequency
+ ccci_write32(REG_MDTOP_CLKSW_CLKSEL_CTL, 0, ccci_read32(REG_MDTOP_CLKSW_CLKSEL_CTL, 0)|0x3);
+
+ // Switch all clock to PLL frequency
+ ccci_write32(REG_MDTOP_CLKSW_CLKSEL_CTL, 0, ccci_read32(REG_MDTOP_CLKSW_CLKSEL_CTL, 0)|0x58103FC);
+
+ // Switch SDF clock to PLL frequency
+ ccci_write32(REG_MDTOP_CLKSW_SDF_CK_CTL, 0, ccci_read32(REG_MDTOP_CLKSW_CLKSEL_CTL, 0)|0x10);
+
+ // Turn off all SW clock request, except ATB
+ ccci_write32(REG_MDTOP_CLKSW_CLKON_CTL, 0, 0x1);
+
+ // Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ ccci_write32(REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ, 0, 0xFFFF);
+
+ // Mask all PLL ADJ RDY IRQ
+ ccci_write32(REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK, 0, 0xFFFF);
+
+ /* Make a record that means MD pll has been initialized. */
+ /* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+ If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+ ccci_write32(REG_MDTOP_PLLMIXED_PLL_DUMMY, 0, MD_PLL_MAGIC_NUM);
+
+ dprintf(CRITICAL, "md1_pll_init done!\n");
+}
+
+void md1_boot(int boot_mode)
+{
+ // step 1: configure modem related buck
+ md1_pmic_setting();
+
+ // step 2: Power on MTCMOS
+ spm_mtcmos_ctrl_md1(STA_POWER_ON);
+ dprintf(CRITICAL, "MD1 MTCMOS power on done!\n");
+ md1_pre_access_md_reg();
+
+ // step 5: configure md_srclkena setting
+ // INFRA_MISC2 already finished in md_common_setting()
+ // SRCLKEN_O1 force on
+ spm_write(POWERON_CONFIG_EN, 0x0B160001);
+ spm_write(SPM_POWER_ON_VAL1, 0x80215830);
+ dprintf(CRITICAL, "md_srclkena done!\n");
+
+ // step 6: configure PLL setting
+ md1_pll_init();
+
+ // step 7: disable MD WDT
+#if !defined(ENABLE_MD_RESET_SPM) && !defined(ENABLE_MD_RESET_RGU)
+ ccci_write32(MD_RGU_BASE, WDT_MD_MODE, WDT_MD_MODE_KEY); // disable MD WDT & MD AUX_WDT
+#endif
+
+}
+
+static void config_md_boot_env(int md_id, int boot_mode)
+{
+ switch (md_id) {
+ case MD_SYS1:
+ md1_boot(boot_mode);
+ break;
+ default:
+ break;
+ }
+}
+
+static void let_md_go(int md_id)
+{
+ switch (md_id) {
+ case MD_SYS1:
+ ccci_write32(MD1_SRAM_POWE1, 0, 0);
+ ccci_write32(MD1_SRAM_POWE2, 0, 0);
+ udelay(10);
+ /* step 8: trigger modem SW to run */
+#ifndef NO_UNGATE_MD
+ ccci_write32(MD1_BOOT_VECTOR_EN, 0, 1);
+ md1_post_access_md_reg();
+#else
+ md1_post_access_md_reg();
+ dprintf(CRITICAL, "do not let MD1 go\n");
+#endif
+ break;
+ default:
+ break;
+ }
+}
+
+void md_wdt_irq_handler(unsigned int irq)
+{
+#if defined(ENABLE_MD_RESET_SPM) || defined(ENABLE_MD_RESET_RGU)
+ unsigned int cnt = ccci_read32(TOPRGU_BASE, TOP_RGU_WDT_NONRST_REG);
+
+ // update counter
+ ccci_write32(TOPRGU_BASE, TOP_RGU_WDT_NONRST_REG, cnt + 1);
+ // reset UART config
+ md_uart_config(AP_ONLY, 0);
+ dprintf(CRITICAL, "\n\n\n\nCurrent wdt cnt:%d\n", cnt + 1);
+
+ if (irq == MT_MD_WDT1_IRQ_ID) {
+#ifdef ENABLE_MD_RESET_SPM
+ dprintf(CRITICAL, "MD1 power off\n");
+ spm_mtcmos_ctrl_md1(STA_POWER_DOWN);
+ mdelay(5);
+ config_md_boot_env(MD_SYS1, 0);
+#endif
+#ifdef ENABLE_MD_RESET_RGU
+ dprintf(CRITICAL, "MD1 reset\n");
+
+ bus_protection_en(0);
+ ccci_write32(TOPRGU_BASE, TOP_RGU_WDT_SWSYSRST,
+ (ccci_read32(TOPRGU_BASE, TOP_RGU_WDT_SWSYSRST) | UNLOCK_KEY) | MD1_SYS);
+ mdelay(5);
+ ccci_write32(TOPRGU_BASE, TOP_RGU_WDT_SWSYSRST,
+ (ccci_read32(TOPRGU_BASE, TOP_RGU_WDT_SWSYSRST) | UNLOCK_KEY) & (~MD1_SYS));
+ bus_protection_diable(0);
+#endif
+ let_md_go(MD_SYS1);
+ }
+
+ dprintf(CRITICAL, "Config UART after MD WDT! %d\n", cnt+1);
+ if ((img_load_flag&((1 << MD_SYS1) | (1 << MD_SYS3))) == ((1 << MD_SYS1) | (1 << MD_SYS3))) {
+ md_uart_config(MD1_MD2, 0);
+ } else if (img_load_flag & (1 << MD_SYS1)) {
+ md_uart_config(MD1_ONLY, 0);
+ } else if (img_load_flag & (1 << MD_SYS3)) {
+ md_uart_config(MD2_ONLY, 0);
+ }
+#else
+ md_uart_config(AP_ONLY, 0);
+ dprintf(CRITICAL, "Get MD WDT irq, STA:%x!!\n", ccci_read32(MD_RGU_BASE, 0xC));
+#ifdef IGNORE_MD_WDT
+ dprintf(CRITICAL, "ignore MD WDT\n");
+#else
+ dprintf(CRITICAL, "whole system reboot\n");
+ ccci_write32(TOPRGU_BASE, TOP_RGU_LATCH_CONTROL, 0x95000000);
+ ccci_write32(TOPRGU_BASE, TOP_RGU_WDT_MODE, 0x22000004);
+ ccci_write32(TOPRGU_BASE, TOP_RGU_WDT_SWRST, 0x1209);
+ while (1);
+#endif
+#endif
+}
+
+static enum handler_return dummy_ap_irq_helper(void *arg)
+{
+#ifndef IGNORE_MD1_WDT
+ md_wdt_irq_handler(MT_MD_WDT1_IRQ_ID);
+#else
+ dprintf(CRITICAL, "ignore MD1 WDT\n");
+#endif
+ return INT_RESCHEDULE;
+}
+
+extern int get_md_err_from_lk_info(int md_id);
+
+#ifndef CTP_ENV
+extern const char *ld_md_errno_to_str(int err_no);
+void md_wdt_init(void)
+{
+ if (img_load_flag & (1 << MD_SYS1)) {
+ mt_irq_set_sens(MT_MD_WDT1_IRQ_ID, EDGE_SENSITIVE);
+ mt_irq_set_polarity(MT_MD_WDT1_IRQ_ID, MT65xx_POLARITY_LOW);
+ register_int_handler(MT_MD_WDT1_IRQ_ID, dummy_ap_irq_helper, NULL);
+ unmask_interrupt(MT_MD_WDT1_IRQ_ID);
+ }
+}
+#endif //#ifndef CTP_ENV
+
+void dummy_ap_boot_up_md(int md_ld_flag)
+{
+ int boot_mode = 0;
+ int i;
+ int ret;
+ img_load_flag = (unsigned int)md_ld_flag;
+
+ // reinit UART, overwrite DWS setting
+ md_uart_config(AP_ONLY, 0);
+
+ // Disable AP WDT
+#ifndef CTP_ENV
+ mtk_wdt_disable();
+#else
+ ccci_write32(TOPRGU_BASE, 0, 0x22000000);
+#endif
+ dprintf(CRITICAL, "Welcome to use dummy AP!\n");
+
+ dprintf(CRITICAL, "load flag for dummy AP: %x\n", img_load_flag);
+#ifndef CTP_ENV
+ if (img_load_flag == 0) {
+ dprintf(CRITICAL, "no MD loaded for dummy AP\n");
+ ret = get_md_err_from_lk_info(MD_SYS1);
+ dprintf(CRITICAL, "hint for MD1 errno: %x, %s\n", ret, ld_md_errno_to_str(-ret));
+ ret = get_md_err_from_lk_info(MD_SYS3);
+ dprintf(CRITICAL, "hint for MD3 errno: %x, %s\n", ret, ld_md_errno_to_str(-ret));
+ dprintf(CRITICAL, "stop.....\n");
+ while (1);
+ }
+
+ if (img_load_flag & (1 << MD_SYS1)) {
+ dprintf(CRITICAL, "MD1 loaded");
+ ret = get_md_err_from_lk_info(MD_SYS1);
+ if (ret < 0) {
+ dprintf(CRITICAL, "MD1 load image has error, errno:%s", ld_md_errno_to_str(-ret));
+ while (1);
+ }
+ }
+ dprintf(CRITICAL, "Get boot mode is %d\n", boot_mode);
+
+ // 3, MD WDT ISR init
+ dprintf(CRITICAL, "Init MD WDT\n");
+ md_wdt_init();
+#endif
+
+ // 4. Common setting for all MD
+ md_common_setting();
+
+ // 5. Setup per-MD env before boot up MD
+ for (i=0; i<3; i++) {
+ if (img_load_flag & (1 << i)) {
+ dprintf(CRITICAL, "MD%d Enabled\n", i+1);
+ config_md_boot_env(i, boot_mode);
+ }
+ }
+
+ // 6. Switch UART
+ dprintf(CRITICAL, "Switch UART!\n");
+ md_uart_config(MD1_ONLY, boot_mode);
+
+ for (i=0; i<3; i++) {
+ if (img_load_flag & (1 << i)) {
+ dprintf(CRITICAL, "Trigger MD%d run\n", i+1);
+ let_md_go(i);
+ }
+ }
+
+#ifndef CTP_ENV
+ dprintf(CRITICAL, "enter while(1), ^O^!!!!!!!!!\n");
+ while (1);
+#endif
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/img_hdr.h b/src/bsp/lk/platform/mt2731/drivers/md/img_hdr.h
new file mode 100644
index 0000000..31aefe5
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/img_hdr.h
@@ -0,0 +1,113 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#ifndef _IMG_HDR_H_
+#define _IMG_HDR_H_
+
+#define IMG_MAGIC (0x58881688)
+#define IMG_EXT_MAGIC (0x58891689)
+
+#define IMG_NAME_SIZE (32)
+
+#define IMG_HDR_SZ (0x200)
+#define BOOT_IMG_HDR_SZ (0x800)
+#define MAX_HDR_SZ (BOOT_IMG_HDR_SZ)
+
+/* image header types */
+#define IMG_HDR_TYPE_UNKNOWN 0
+#define IMG_HDR_TYPE_RAW 1
+#define IMG_HDR_TYPE_BOOT 2
+#define IMG_HDR_TYPE_DTBO 3
+
+/* image types */
+#define IMG_TYPE_ID_OFFSET (0)
+#define IMG_TYPE_RESERVED0_OFFSET (8)
+#define IMG_TYPE_RESERVED1_OFFSET (16)
+#define IMG_TYPE_GROUP_OFFSET (24)
+
+#define IMG_TYPE_ID_MASK (0xffU << IMG_TYPE_ID_OFFSET)
+#define IMG_TYPE_RESERVED0_MASK (0xffU << IMG_TYPE_RESERVED0_OFFSET)
+#define IMG_TYPE_RESERVED1_MASK (0xffU << IMG_TYPE_RESERVED1_OFFSET)
+#define IMG_TYPE_GROUP_MASK (0xffU << IMG_TYPE_GROUP_OFFSET)
+
+#define IMG_TYPE_GROUP_AP (0x00U << IMG_TYPE_GROUP_OFFSET)
+#define IMG_TYPE_GROUP_MD (0x01U << IMG_TYPE_GROUP_OFFSET)
+#define IMG_TYPE_GROUP_CERT (0x02U << IMG_TYPE_GROUP_OFFSET)
+
+/* AP group */
+#define IMG_TYPE_IMG_AP_BIN (0x00 | IMG_TYPE_GROUP_AP)
+#define IMG_TYPE_AND_VFY_BOOT_SIG (0x01 | IMG_TYPE_GROUP_AP)
+
+/* MD group */
+#define IMG_TYPE_IMG_MD_LTE (0x00 | IMG_TYPE_GROUP_MD)
+#define IMG_TYPE_IMG_MD_C2K (0x01 | IMG_TYPE_GROUP_MD)
+
+/* CERT group */
+#define IMG_TYPE_CERT1 (0x00 | IMG_TYPE_GROUP_CERT)
+#define IMG_TYPE_CERT1_MD (0x01 | IMG_TYPE_GROUP_CERT)
+#define IMG_TYPE_CERT2 (0x02 | IMG_TYPE_GROUP_CERT)
+
+#define IMG_ALIGN_SZ 16
+
+typedef union {
+ struct {
+ unsigned int magic;
+ unsigned int dsize;
+ char name[IMG_NAME_SIZE];
+ unsigned int maddr;
+ unsigned int mode;
+ /* extension */
+ unsigned int ext_magic;
+ unsigned int hdr_size;
+ unsigned int hdr_version;
+ unsigned int img_type;
+ unsigned int img_list_end;
+ unsigned int align_size;
+ unsigned int dsize_extend;
+ unsigned int maddr_extend;
+ } info;
+ unsigned char data[IMG_HDR_SZ];
+} IMG_HDR_T;
+
+/* the source of data may be boot image header or image header */
+typedef struct {
+ unsigned int img_hdr_type;
+ unsigned int img_hdr_sz;
+ unsigned int img_type;
+ unsigned int img_sz;
+ unsigned int img_list_end;
+ char img_name[IMG_NAME_SIZE];
+} IMG_INFO;
+
+#endif /* _IMG_HDR_H_ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/img_util.h b/src/bsp/lk/platform/mt2731/drivers/md/img_util.h
new file mode 100644
index 0000000..36fc1ad
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/img_util.h
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2018. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef IMG_UTIL_H
+#define IMG_UTIL_H
+//#include <pal_typedefs.h>
+
+#define EXTRACT_BYTE(x, n) ((uint64_t)((uint8_t *)&x)[n])
+#define CPU_TO_U32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \
+ (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))
+
+static inline uint32_t u32_to_cpu(uint32_t x)
+{
+ return (uint32_t)CPU_TO_U32(x);
+}
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/img_utils.c b/src/bsp/lk/platform/mt2731/drivers/md/img_utils.c
new file mode 100644
index 0000000..d4c3c55
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/img_utils.c
@@ -0,0 +1,93 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include "sec_boot.h"
+#include "sec_dbg.h"
+#include "sec_part_name.h"
+#include "stdlib.h"
+#include "string.h"
+#include <lib/mempool.h>
+
+#define MOD "SECLIB_IMG_VERIFY"
+
+uint8_t *img_buf = NULL;
+uint32_t img_buf_current_allocated = 0;
+
+void seclib_image_buf_init(void)
+{
+ if (NULL == img_buf) {
+ img_buf = mempool_alloc(SEC_IMG_BUFFER_LENGTH, MEMPOOL_ANY);
+ if (NULL == img_buf) {
+ SMSG_ERROR("[%s] malloc memory for heap failed!!\n", MOD);
+ ASSERT(0);
+ } else
+ img_buf_current_allocated = 0;
+ }
+}
+
+void seclib_image_buf_reset(void)
+{
+ if (NULL != img_buf) {
+ memset(img_buf, 0, SEC_IMG_BUFFER_LENGTH);
+ img_buf_current_allocated = 0;
+ }
+}
+
+void seclib_image_buf_free(void)
+{
+ if (NULL != img_buf)
+ mempool_free(img_buf);
+ img_buf = NULL;
+ img_buf_current_allocated = 0;
+}
+
+uint8_t *seclib_image_allocate_mem(uint32_t buf_len)
+{
+ uint8_t *current_free;
+
+ if (img_buf_current_allocated + buf_len > SEC_IMG_BUFFER_LENGTH) {
+ SMSG_ERROR("[%s] Memory is not enough\n", MOD);
+ ASSERT(0);
+ }
+ current_free = img_buf + img_buf_current_allocated;
+ img_buf_current_allocated = img_buf_current_allocated + buf_len;
+
+ memset(current_free, 0, buf_len);
+
+ SMSG_ERROR("[%s] Allocate memory size %d\n", MOD, buf_len);
+
+ return current_free;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/logtab.h b/src/bsp/lk/platform/mt2731/drivers/md/logtab.h
new file mode 100644
index 0000000..8037ec6
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/logtab.h
@@ -0,0 +1,58 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+const float s_logv_2[] = {
+ 0.000000000, 0.000000000, 1.000000000, 0.630929754, /* 0 1 2 3 */
+ 0.500000000, 0.430676558, 0.386852807, 0.356207187, /* 4 5 6 7 */
+ 0.333333333, 0.315464877, 0.301029996, 0.289064826, /* 8 9 10 11 */
+ 0.278942946, 0.270238154, 0.262649535, 0.255958025, /* 12 13 14 15 */
+ 0.250000000, 0.244650542, 0.239812467, 0.235408913, /* 16 17 18 19 */
+ 0.231378213, 0.227670249, 0.224243824, 0.221064729, /* 20 21 22 23 */
+ 0.218104292, 0.215338279, 0.212746054, 0.210309918, /* 24 25 26 27 */
+ 0.208014598, 0.205846832, 0.203795047, 0.201849087, /* 28 29 30 31 */
+ 0.200000000, 0.198239863, 0.196561632, 0.194959022, /* 32 33 34 35 */
+ 0.193426404, 0.191958720, 0.190551412, 0.189200360, /* 36 37 38 39 */
+ 0.187901825, 0.186652411, 0.185449023, 0.184288833, /* 40 41 42 43 */
+ 0.183169251, 0.182087900, 0.181042597, 0.180031327, /* 44 45 46 47 */
+ 0.179052232, 0.178103594, 0.177183820, 0.176291434, /* 48 49 50 51 */
+ 0.175425064, 0.174583430, 0.173765343, 0.172969690, /* 52 53 54 55 */
+ 0.172195434, 0.171441601, 0.170707280, 0.169991616, /* 56 57 58 59 */
+ 0.169293808, 0.168613099, 0.167948779, 0.167300179, /* 60 61 62 63 */
+ 0.166666667
+};
+
+
+/* $Source$ */
+/* $Revision: 0.36 $ */
+/* $Date: 2005-08-01 16:37:28 +0000 $ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/m1.h b/src/bsp/lk/platform/mt2731/drivers/md/m1.h
new file mode 100644
index 0000000..3b6cc1c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/m1.h
@@ -0,0 +1,64 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#ifndef _M1_H_
+#define _M1_H_
+
+#define M1_1024_KEY_LEN 128 /* 1024 bits */
+#define M1_2048_KEY_LEN 256 /* 2048 bits */
+#define M1_MAX_KEY_LEN M1_2048_KEY_LEN
+#define M1_CUT_LEN (M1_MAX_KEY_LEN-2) // cut length must be <= (N_LEN - 1)
+
+/* =========================== */
+/* m1 key structure definition */
+/* =========================== */
+
+typedef struct {
+ unsigned int e_len;
+ unsigned int n_len;
+ unsigned short m_coeff;
+ unsigned short cut_len;
+ unsigned short e[M1_2048_KEY_LEN >> 1];
+ unsigned short n[M1_2048_KEY_LEN >> 1];
+} CT_M1_Key;
+
+typedef struct {
+ unsigned int e_len;
+ unsigned int n_len;
+ unsigned int reserved;
+ unsigned char e[M1_2048_KEY_LEN];
+ unsigned char n[M1_2048_KEY_LEN];
+} CT_CE_Key;
+
+#endif /* _M1_H_ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/mpi-config.h b/src/bsp/lk/platform/mt2731/drivers/md/mpi-config.h
new file mode 100644
index 0000000..2fde7c7
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/mpi-config.h
@@ -0,0 +1,122 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef MPI_CONFIG_H_
+#define MPI_CONFIG_H_
+
+/*
+ For boolean options,
+ 0 = no
+ 1 = yes
+
+ Other options are documented individually.
+
+ */
+
+#ifndef MP_IOFUNC
+#define MP_IOFUNC 0 /* include mp_print() ? */
+#endif
+
+#ifndef MP_MODARITH
+#define MP_MODARITH 1 /* include modular arithmetic ? */
+#endif
+
+#ifndef MP_NUMTH
+#define MP_NUMTH 1 /* include number theoretic functions? */
+#endif
+
+#ifndef MP_LOGTAB
+#define MP_LOGTAB 1 /* use table of logs instead of log()? */
+#endif
+
+#ifndef MP_MEMSET
+#define MP_MEMSET 1 /* use memset() to zero buffers? */
+#endif
+
+#ifndef MP_MEMCPY
+#define MP_MEMCPY 1 /* use memcpy() to copy buffers? */
+#endif
+
+#ifndef MP_CRYPTO
+#define MP_CRYPTO 1 /* erase memory on free? */
+#endif
+
+#ifndef MP_ARGCHK
+/*
+ 0 = no parameter checks
+ 1 = runtime checks, continue execution and return an error to caller
+ 2 = assertions; dump core on parameter errors
+ */
+#define MP_ARGCHK 1 /* how to check input arguments */
+#endif
+
+#ifndef MP_DEBUG
+#define MP_DEBUG 0 /* print diagnostic output? */
+#endif
+
+#ifndef MP_DEFPREC
+#define MP_DEFPREC 64 /* default precision, in digits */
+#endif
+
+#ifndef MP_MACRO
+#define MP_MACRO 1 /* use macros for frequent calls? */
+#endif
+
+#ifndef MP_SQUARE
+#define MP_SQUARE 1 /* use separate squaring code? */
+#endif
+
+#ifndef MP_PTAB_SIZE
+/*
+ When building mpprime.c, we build in a table of small prime
+ values to use for primality testing. The more you include,
+ the more space they take up. See primes.c for the possible
+ values (currently 16, 32, 64, 128, 256, and 6542)
+ */
+#define MP_PTAB_SIZE 128 /* how many built-in primes? */
+#endif
+
+#ifndef MP_COMPAT_MACROS
+#define MP_COMPAT_MACROS 1 /* define compatibility macros? */
+#endif
+
+#endif /* ifndef MPI_CONFIG_H_ */
+
+
+/* crc==3287762869, version==2, Sat Feb 02 06:43:53 2002 */
+
+/* $Source$ */
+/* $Revision: 0.36 $ */
+/* $Date: 2005-08-01 16:37:28 +0000 $ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/mpi-types.h b/src/bsp/lk/platform/mt2731/drivers/md/mpi-types.h
new file mode 100644
index 0000000..e35fd9d
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/mpi-types.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+#ifndef _MPI_TYPES_H_
+#define _MPI_TYPES_H_
+
+/* Type definitions generated by 'types.pl' */
+typedef char mp_sign;
+typedef unsigned short mp_digit; /* 2 byte type */
+typedef unsigned int mp_word; /* 4 byte type */
+typedef unsigned int mp_size;
+typedef int mp_err;
+
+#define MP_DIGIT_BIT (CHAR_BIT*sizeof(mp_digit))
+#define MP_DIGIT_MAX USHRT_MAX
+#define MP_WORD_BIT (CHAR_BIT*sizeof(mp_word))
+#define MP_WORD_MAX UINT_MAX
+
+#define MP_DIGIT_SIZE 2
+#define DIGIT_FMT "%04X"
+#define RADIX (MP_DIGIT_MAX+1)
+
+
+/* $Source$ */
+/* $Revision: 0.36 $ */
+/* $Date: 2005-08-01 16:37:28 +0000 $ */
+
+#endif /* _MPI_TYPES_H_ */
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/mpi.c b/src/bsp/lk/platform/mt2731/drivers/md/mpi.c
new file mode 100644
index 0000000..8d09e08
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/mpi.c
@@ -0,0 +1,4020 @@
+/*
+ mpi.h
+
+ by Michael J. Fromberger <sting@linguist.dartmouth.edu>
+ Copyright (C) 1998 Michael J. Fromberger, All Rights Reserved
+
+ Arbitrary precision integer arithmetic library
+
+ $Id: mpi.h,v 1.2 2005/05/05 14:38:47 tom Exp $
+ */
+
+#include "mpi.h"
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#if MP_DEBUG
+#include <stdio.h>
+
+#define DIAG(T,V) {fprintf(stderr,T);mp_print(V,stderr);fputc('\n',stderr);}
+#else
+#define DIAG(T,V)
+#endif
+
+/*
+ If MP_LOGTAB is not defined, use the math library to compute the
+ logarithms on the fly. Otherwise, use the static table below.
+ Pick which works best for your system.
+ */
+#if MP_LOGTAB
+
+/* {{{ s_logv_2[] - log table for 2 in various bases */
+
+/*
+ A table of the logs of 2 for various bases (the 0 and 1 entries of
+ this table are meaningless and should not be referenced).
+
+ This table is used to compute output lengths for the mp_toradix()
+ function. Since a number n in radix r takes up about log_r(n)
+ digits, we estimate the output size by taking the least integer
+ greater than log_r(n), where:
+
+ log_r(n) = log_2(n) * log_r(2)
+
+ This table, therefore, is a table of log_r(2) for 2 <= r <= 36,
+ which are the output bases supported.
+ */
+
+#include "logtab.h"
+
+/* }}} */
+#define LOG_V_2(R) s_logv_2[(R)]
+
+#else
+
+#include <math.h>
+#define LOG_V_2(R) (log(2.0)/log(R))
+
+#endif
+
+/* Default precision for newly created mp_int's */
+static unsigned int s_mp_defprec = MP_DEFPREC;
+
+/* {{{ Digit arithmetic macros */
+
+/*
+ When adding and multiplying digits, the results can be larger than
+ can be contained in an mp_digit. Thus, an mp_word is used. These
+ macros mask off the upper and lower digits of the mp_word (the
+ mp_word may be more than 2 mp_digits wide, but we only concern
+ ourselves with the low-order 2 mp_digits)
+
+ If your mp_word DOES have more than 2 mp_digits, you need to
+ uncomment the first line, and comment out the second.
+ */
+
+/* #define CARRYOUT(W) (((W)>>DIGIT_BIT)&MP_DIGIT_MAX) */
+#define CARRYOUT(W) ((W)>>DIGIT_BIT)
+#define ACCUM(W) ((W)&MP_DIGIT_MAX)
+
+/* }}} */
+
+/* {{{ Comparison constants */
+
+#define MP_LT -1
+#define MP_EQ 0
+#define MP_GT 1
+
+/* }}} */
+
+/* {{{ Constant strings */
+
+/* Constant strings returned by mp_strerror() */
+static const char *mp_err_string[] = {
+ "unknown result code", /* say what? */
+ "boolean true", /* MP_OKAY, MP_YES */
+ "boolean false", /* MP_NO */
+ "out of memory", /* MP_MEM */
+ "argument out of range", /* MP_RANGE */
+ "invalid input parameter", /* MP_BADARG */
+ "result is undefined" /* MP_UNDEF */
+};
+
+/* Value to digit maps for radix conversion */
+
+/* s_dmap_1 - standard digits and letters */
+static const char *s_dmap_1 =
+ "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz+/";
+
+#if 0
+/* s_dmap_2 - base64 ordering for digits */
+static const char *s_dmap_2 =
+ "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
+#endif
+
+/* }}} */
+
+/* {{{ Static function declarations */
+
+/*
+ If MP_MACRO is false, these will be defined as actual functions;
+ otherwise, suitable macro definitions will be used. This works
+ around the fact that ANSI C89 doesn't support an 'inline' keyword
+ (although I hear C9x will ... about bloody time). At present, the
+ macro definitions are identical to the function bodies, but they'll
+ expand in place, instead of generating a function call.
+
+ I chose these particular functions to be made into macros because
+ some profiling showed they are called a lot on a typical workload,
+ and yet they are primarily housekeeping.
+ */
+#if MP_MACRO == 0
+void s_mp_setz(mp_digit *dp, mp_size count); /* zero digits */
+void s_mp_copy(mp_digit *sp, mp_digit *dp, mp_size count); /* copy */
+void *s_mp_alloc(size_t nb, size_t ni); /* general allocator */
+void s_mp_free(void *ptr); /* general free function */
+#else
+
+/* Even if these are defined as macros, we need to respect the settings
+ of the MP_MEMSET and MP_MEMCPY configuration options...
+ */
+#if MP_MEMSET == 0
+#define s_mp_setz(dp, count) \
+ {int ix;for(ix=0;ix<(count);ix++)(dp)[ix]=0;}
+#else
+#define s_mp_setz(dp, count) memset(dp, 0, (count) * sizeof(mp_digit))
+#endif /* MP_MEMSET */
+
+#if MP_MEMCPY == 0
+#define s_mp_copy(sp, dp, count) \
+ {int ix;for(ix=0;ix<(count);ix++)(dp)[ix]=(sp)[ix];}
+#else
+#define s_mp_copy(sp, dp, count) memcpy(dp, sp, (count) * sizeof(mp_digit))
+#endif /* MP_MEMCPY */
+
+#define s_mp_alloc(nb, ni) calloc(nb, ni)
+#define s_mp_free(ptr) {if(ptr) free(ptr);}
+#endif /* MP_MACRO */
+
+mp_err s_mp_grow(mp_int *mp, mp_size min); /* increase allocated size */
+mp_err s_mp_pad(mp_int *mp, mp_size min); /* left pad with zeroes */
+
+void s_mp_clamp(mp_int *mp); /* clip leading zeroes */
+
+void s_mp_exch(mp_int *a, mp_int *b); /* swap a and b in place */
+
+mp_err s_mp_lshd(mp_int *mp, mp_size p); /* left-shift by p digits */
+void s_mp_rshd(mp_int *mp, mp_size p); /* right-shift by p digits */
+void s_mp_div_2d(mp_int *mp, mp_digit d); /* divide by 2^d in place */
+void s_mp_mod_2d(mp_int *mp, mp_digit d); /* modulo 2^d in place */
+mp_err s_mp_mul_2d(mp_int *mp, mp_digit d); /* multiply by 2^d in place*/
+void s_mp_div_2(mp_int *mp); /* divide by 2 in place */
+mp_err s_mp_mul_2(mp_int *mp); /* multiply by 2 in place */
+mp_digit s_mp_norm(mp_int *a, mp_int *b); /* normalize for division */
+mp_err s_mp_add_d(mp_int *mp, mp_digit d); /* unsigned digit addition */
+mp_err s_mp_sub_d(mp_int *mp, mp_digit d); /* unsigned digit subtract */
+mp_err s_mp_mul_d(mp_int *mp, mp_digit d); /* unsigned digit multiply */
+mp_err s_mp_div_d(mp_int *mp, mp_digit d, mp_digit *r);
+/* unsigned digit divide */
+mp_err s_mp_reduce(mp_int *x, mp_int *m, mp_int *mu);
+/* Barrett reduction */
+mp_err s_mp_add(mp_int *a, mp_int *b); /* magnitude addition */
+mp_err s_mp_sub(mp_int *a, mp_int *b); /* magnitude subtract */
+mp_err s_mp_mul(mp_int *a, mp_int *b); /* magnitude multiply */
+#if 0
+void s_mp_kmul(mp_digit *a, mp_digit *b, mp_digit *out, mp_size len);
+/* multiply buffers in place */
+#endif
+#if MP_SQUARE
+mp_err s_mp_sqr(mp_int *a); /* magnitude square */
+#else
+#define s_mp_sqr(a) s_mp_mul(a, a)
+#endif
+mp_err s_mp_div(mp_int *a, mp_int *b); /* magnitude divide */
+mp_err s_mp_2expt(mp_int *a, mp_digit k); /* a = 2^k */
+int s_mp_cmp(mp_int *a, mp_int *b); /* magnitude comparison */
+int s_mp_cmp_d(mp_int *a, mp_digit d); /* magnitude digit compare */
+int s_mp_ispow2(mp_int *v); /* is v a power of 2? */
+int s_mp_ispow2d(mp_digit d); /* is d a power of 2? */
+
+int s_mp_tovalue(char ch, int r); /* convert ch to value */
+char s_mp_todigit(int val, int r, int low); /* convert val to digit */
+int s_mp_outlen(int bits, int r); /* output length in bytes */
+
+/* }}} */
+
+/* {{{ Default precision manipulation */
+
+unsigned int mp_get_prec(void)
+{
+ return s_mp_defprec;
+
+} /* end mp_get_prec() */
+
+void mp_set_prec(unsigned int prec)
+{
+ if (prec == 0)
+ s_mp_defprec = MP_DEFPREC;
+ else
+ s_mp_defprec = prec;
+
+} /* end mp_set_prec() */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ mp_init(mp) */
+
+/*
+ mp_init(mp)
+
+ Initialize a new zero-valued mp_int. Returns MP_OKAY if successful,
+ MP_MEM if memory could not be allocated for the structure.
+ */
+
+mp_err mp_init(mp_int *mp)
+{
+ return mp_init_size(mp, s_mp_defprec);
+
+} /* end mp_init() */
+
+/* }}} */
+
+/* {{{ mp_init_array(mp[], count) */
+
+mp_err mp_init_array(mp_int mp[], int count)
+{
+ mp_err res;
+ int pos;
+
+ ARGCHK(mp != NULL && count > 0, MP_BADARG);
+
+ for (pos = 0; pos < count; ++pos) {
+ if ((res = mp_init(&mp[pos])) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ return MP_OKAY;
+
+CLEANUP:
+ while (--pos >= 0)
+ mp_clear(&mp[pos]);
+
+ return res;
+
+} /* end mp_init_array() */
+
+/* }}} */
+
+/* {{{ mp_init_size(mp, prec) */
+
+/*
+ mp_init_size(mp, prec)
+
+ Initialize a new zero-valued mp_int with at least the given
+ precision; returns MP_OKAY if successful, or MP_MEM if memory could
+ not be allocated for the structure.
+ */
+
+mp_err mp_init_size(mp_int *mp, mp_size prec)
+{
+ ARGCHK(mp != NULL && prec > 0, MP_BADARG);
+
+ if ((DIGITS(mp) = s_mp_alloc(prec, sizeof(mp_digit))) == NULL)
+ return MP_MEM;
+
+ SIGN(mp) = MP_ZPOS;
+ USED(mp) = 1;
+ ALLOC(mp) = prec;
+
+ return MP_OKAY;
+
+} /* end mp_init_size() */
+
+/* }}} */
+
+/* {{{ mp_init_copy(mp, from) */
+
+/*
+ mp_init_copy(mp, from)
+
+ Initialize mp as an exact copy of from. Returns MP_OKAY if
+ successful, MP_MEM if memory could not be allocated for the new
+ structure.
+ */
+
+mp_err mp_init_copy(mp_int *mp, mp_int *from)
+{
+ ARGCHK(mp != NULL && from != NULL, MP_BADARG);
+
+ if (mp == from)
+ return MP_OKAY;
+
+ if ((DIGITS(mp) = s_mp_alloc(USED(from), sizeof(mp_digit))) == NULL)
+ return MP_MEM;
+
+ s_mp_copy(DIGITS(from), DIGITS(mp), USED(from));
+ USED(mp) = USED(from);
+ ALLOC(mp) = USED(from);
+ SIGN(mp) = SIGN(from);
+
+ return MP_OKAY;
+
+} /* end mp_init_copy() */
+
+/* }}} */
+
+/* {{{ mp_copy(from, to) */
+
+/*
+ mp_copy(from, to)
+
+ Copies the mp_int 'from' to the mp_int 'to'. It is presumed that
+ 'to' has already been initialized (if not, use mp_init_copy()
+ instead). If 'from' and 'to' are identical, nothing happens.
+ */
+
+mp_err mp_copy(mp_int *from, mp_int *to)
+{
+ ARGCHK(from != NULL && to != NULL, MP_BADARG);
+
+ if (from == to)
+ return MP_OKAY;
+
+ { /* copy */
+ mp_digit *tmp;
+
+ /*
+ If the allocated buffer in 'to' already has enough space to hold
+ all the used digits of 'from', we'll re-use it to avoid hitting
+ the memory allocater more than necessary; otherwise, we'd have
+ to grow anyway, so we just allocate a hunk and make the copy as
+ usual
+ */
+ if (ALLOC(to) >= USED(from)) {
+ s_mp_setz(DIGITS(to) + USED(from), ALLOC(to) - USED(from));
+ s_mp_copy(DIGITS(from), DIGITS(to), USED(from));
+
+ } else {
+ if ((tmp = s_mp_alloc(USED(from), sizeof(mp_digit))) == NULL)
+ return MP_MEM;
+
+ s_mp_copy(DIGITS(from), tmp, USED(from));
+
+ if (DIGITS(to) != NULL) {
+#if MP_CRYPTO
+ s_mp_setz(DIGITS(to), ALLOC(to));
+#endif
+ s_mp_free(DIGITS(to));
+ }
+
+ DIGITS(to) = tmp;
+ ALLOC(to) = USED(from);
+ }
+
+ /* Copy the precision and sign from the original */
+ USED(to) = USED(from);
+ SIGN(to) = SIGN(from);
+ } /* end copy */
+
+ return MP_OKAY;
+
+} /* end mp_copy() */
+
+/* }}} */
+
+/* {{{ mp_exch(mp1, mp2) */
+
+/*
+ mp_exch(mp1, mp2)
+
+ Exchange mp1 and mp2 without allocating any intermediate memory
+ (well, unless you count the stack space needed for this call and the
+ locals it creates...). This cannot fail.
+ */
+
+void mp_exch(mp_int *mp1, mp_int *mp2)
+{
+#if MP_ARGCHK == 2
+ assert(mp1 != NULL && mp2 != NULL);
+#else
+ if (mp1 == NULL || mp2 == NULL)
+ return;
+#endif
+
+ s_mp_exch(mp1, mp2);
+
+} /* end mp_exch() */
+
+/* }}} */
+
+/* {{{ mp_clear(mp) */
+
+/*
+ mp_clear(mp)
+
+ Release the storage used by an mp_int, and void its fields so that
+ if someone calls mp_clear() again for the same int later, we won't
+ get tollchocked.
+ */
+
+void mp_clear(mp_int *mp)
+{
+ if (mp == NULL)
+ return;
+
+ if (DIGITS(mp) != NULL) {
+#if MP_CRYPTO
+ s_mp_setz(DIGITS(mp), ALLOC(mp));
+#endif
+ s_mp_free(DIGITS(mp));
+ DIGITS(mp) = NULL;
+ }
+
+ USED(mp) = 0;
+ ALLOC(mp) = 0;
+
+} /* end mp_clear() */
+
+/* }}} */
+
+/* {{{ mp_clear_array(mp[], count) */
+
+void mp_clear_array(mp_int mp[], int count)
+{
+ ARGCHK(mp != NULL && count > 0, MP_BADARG);
+
+ while (--count >= 0)
+ mp_clear(&mp[count]);
+
+} /* end mp_clear_array() */
+
+/* }}} */
+
+/* {{{ mp_zero(mp) */
+
+/*
+ mp_zero(mp)
+
+ Set mp to zero. Does not change the allocated size of the structure,
+ and therefore cannot fail (except on a bad argument, which we ignore)
+ */
+void mp_zero(mp_int *mp)
+{
+ if (mp == NULL)
+ return;
+
+ s_mp_setz(DIGITS(mp), ALLOC(mp));
+ USED(mp) = 1;
+ SIGN(mp) = MP_ZPOS;
+
+} /* end mp_zero() */
+
+/* }}} */
+
+/* {{{ mp_set(mp, d) */
+
+void mp_set(mp_int *mp, mp_digit d)
+{
+ if (mp == NULL)
+ return;
+
+ mp_zero(mp);
+ DIGIT(mp, 0) = d;
+
+} /* end mp_set() */
+
+/* }}} */
+
+/* {{{ mp_set_int(mp, z) */
+
+/*p_err mp_set_int(mp_int *mp, long z)
+{
+ int ix;
+ unsigned long v = abs(z);
+ mp_err res;
+
+ ARGCHK(mp != NULL, MP_BADARG);
+
+ mp_zero(mp);
+ if (z == 0)
+ return MP_OKAY; *//*hortcut for zero */
+
+ /*for (ix = sizeof(long) - 1; ix >= 0; ix--) {
+
+ if ((res = s_mp_mul_2d(mp, CHAR_BIT)) != MP_OKAY)
+ return res;
+
+ res = s_mp_add_d(mp,
+ (mp_digit)((v >> (ix * CHAR_BIT)) & UCHAR_MAX));
+ if (res != MP_OKAY)
+ return res;
+
+ }
+
+ if (z < 0)
+ SIGN(mp) = MP_NEG;
+
+ return MP_OKAY;
+
+} *//* end mp_set_int() */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ Digit arithmetic */
+
+/* {{{ mp_add_d(a, d, b) */
+
+/*
+ mp_add_d(a, d, b)
+
+ Compute the sum b = a + d, for a single digit d. Respects the sign of
+ its primary addend (single digits are unsigned anyway).
+ */
+
+mp_err mp_add_d(mp_int *a, mp_digit d, mp_int *b)
+{
+ mp_err res = MP_OKAY;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ if (SIGN(b) == MP_ZPOS)
+ res = s_mp_add_d(b, d);
+
+ else if (s_mp_cmp_d(b, d) >= 0)
+ res = s_mp_sub_d(b, d);
+
+ else {
+ SIGN(b) = MP_ZPOS;
+
+ DIGIT(b, 0) = d - DIGIT(b, 0);
+ }
+
+ return res;
+
+} /* end mp_add_d() */
+
+/* }}} */
+
+/* {{{ mp_sub_d(a, d, b) */
+
+/*
+ mp_sub_d(a, d, b)
+
+ Compute the difference b = a - d, for a single digit d. Respects the
+ sign of its subtrahend (single digits are unsigned anyway).
+ */
+
+mp_err mp_sub_d(mp_int *a, mp_digit d, mp_int *b)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ if (SIGN(b) == MP_NEG) {
+ if ((res = s_mp_add_d(b, d)) != MP_OKAY)
+ return res;
+
+ } else if (s_mp_cmp_d(b, d) >= 0) {
+ if ((res = s_mp_sub_d(b, d)) != MP_OKAY)
+ return res;
+
+ } else {
+ mp_neg(b, b);
+
+ DIGIT(b, 0) = d - DIGIT(b, 0);
+ SIGN(b) = MP_NEG;
+ }
+
+ if (s_mp_cmp_d(b, 0) == 0)
+ SIGN(b) = MP_ZPOS;
+
+ return MP_OKAY;
+
+} /* end mp_sub_d() */
+
+/* }}} */
+
+/* {{{ mp_mul_d(a, d, b) */
+
+/*
+ mp_mul_d(a, d, b)
+
+ Compute the product b = a * d, for a single digit d. Respects the sign
+ of its multiplicand (single digits are unsigned anyway)
+ */
+
+mp_err mp_mul_d(mp_int *a, mp_digit d, mp_int *b)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if (d == 0) {
+ mp_zero(b);
+ return MP_OKAY;
+ }
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ res = s_mp_mul_d(b, d);
+
+ return res;
+
+} /* end mp_mul_d() */
+
+/* }}} */
+
+/* {{{ mp_mul_2(a, c) */
+
+mp_err mp_mul_2(mp_int *a, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ return s_mp_mul_2(c);
+
+} /* end mp_mul_2() */
+
+/* }}} */
+
+/* {{{ mp_div_d(a, d, q, r) */
+
+/*
+ mp_div_d(a, d, q, r)
+
+ Compute the quotient q = a / d and remainder r = a mod d, for a
+ single digit d. Respects the sign of its divisor (single digits are
+ unsigned anyway).
+ */
+
+mp_err mp_div_d(mp_int *a, mp_digit d, mp_int *q, mp_digit *r)
+{
+ mp_err res;
+ mp_digit rem;
+ int pow;
+
+ ARGCHK(a != NULL, MP_BADARG);
+
+ if (d == 0)
+ return MP_RANGE;
+
+ /* Shortcut for powers of two ... */
+ if ((pow = s_mp_ispow2d(d)) >= 0) {
+ mp_digit mask;
+
+ mask = (1 << pow) - 1;
+ rem = DIGIT(a, 0) & mask;
+
+ if (q) {
+ mp_copy(a, q);
+ s_mp_div_2d(q, pow);
+ }
+
+ if (r)
+ *r = rem;
+
+ return MP_OKAY;
+ }
+
+ /*
+ If the quotient is actually going to be returned, we'll try to
+ avoid hitting the memory allocator by copying the dividend into it
+ and doing the division there. This can't be any _worse_ than
+ always copying, and will sometimes be better (since it won't make
+ another copy)
+
+ If it's not going to be returned, we need to allocate a temporary
+ to hold the quotient, which will just be discarded.
+ */
+ if (q) {
+ if ((res = mp_copy(a, q)) != MP_OKAY)
+ return res;
+
+ res = s_mp_div_d(q, d, &rem);
+ if (s_mp_cmp_d(q, 0) == MP_EQ)
+ SIGN(q) = MP_ZPOS;
+
+ } else {
+ mp_int qp;
+
+ if ((res = mp_init_copy(&qp, a)) != MP_OKAY)
+ return res;
+
+ res = s_mp_div_d(&qp, d, &rem);
+ if (s_mp_cmp_d(&qp, 0) == 0)
+ SIGN(&qp) = MP_ZPOS;
+
+ mp_clear(&qp);
+ }
+
+ if (r)
+ *r = rem;
+
+ return res;
+
+} /* end mp_div_d() */
+
+/* }}} */
+
+/* {{{ mp_div_2(a, c) */
+
+/*
+ mp_div_2(a, c)
+
+ Compute c = a / 2, disregarding the remainder.
+ */
+
+mp_err mp_div_2(mp_int *a, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ s_mp_div_2(c);
+
+ return MP_OKAY;
+
+} /* end mp_div_2() */
+
+/* }}} */
+
+/* {{{ mp_expt_d(a, d, b) */
+
+mp_err mp_expt_d(mp_int *a, mp_digit d, mp_int *c)
+{
+ mp_int s, x;
+ mp_err res;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_init(&s)) != MP_OKAY)
+ return res;
+ if ((res = mp_init_copy(&x, a)) != MP_OKAY)
+ goto X;
+
+ DIGIT(&s, 0) = 1;
+
+ while (d != 0) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d >>= 1;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ s_mp_exch(&s, c);
+
+CLEANUP:
+ mp_clear(&x);
+X:
+ mp_clear(&s);
+
+ return res;
+
+} /* end mp_expt_d() */
+
+/* }}} */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ Full arithmetic */
+
+/* {{{ mp_abs(a, b) */
+
+/*
+ mp_abs(a, b)
+
+ Compute b = |a|. 'a' and 'b' may be identical.
+ */
+
+mp_err mp_abs(mp_int *a, mp_int *b)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ SIGN(b) = MP_ZPOS;
+
+ return MP_OKAY;
+
+} /* end mp_abs() */
+
+/* }}} */
+
+/* {{{ mp_neg(a, b) */
+
+/*
+ mp_neg(a, b)
+
+ Compute b = -a. 'a' and 'b' may be identical.
+ */
+
+mp_err mp_neg(mp_int *a, mp_int *b)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ if (s_mp_cmp_d(b, 0) == MP_EQ)
+ SIGN(b) = MP_ZPOS;
+ else
+ SIGN(b) = (SIGN(b) == MP_NEG) ? MP_ZPOS : MP_NEG;
+
+ return MP_OKAY;
+
+} /* end mp_neg() */
+
+/* }}} */
+
+/* {{{ mp_add(a, b, c) */
+
+/*
+ mp_add(a, b, c)
+
+ Compute c = a + b. All parameters may be identical.
+ */
+
+mp_err mp_add(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_err res;
+ int cmp;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ if (SIGN(a) == SIGN(b)) { /* same sign: add values, keep sign */
+
+ /* Commutativity of addition lets us do this in either order,
+ so we avoid having to use a temporary even if the result
+ is supposed to replace the output
+ */
+ if (c == b) {
+ if ((res = s_mp_add(c, a)) != MP_OKAY)
+ return res;
+ } else {
+ if (c != a && (res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ if ((res = s_mp_add(c, b)) != MP_OKAY)
+ return res;
+ }
+
+ } else if ((cmp = s_mp_cmp(a, b)) > 0) { /* different sign: a > b */
+
+ /* If the output is going to be clobbered, we will use a temporary
+ variable; otherwise, we'll do it without touching the memory
+ allocator at all, if possible
+ */
+ if (c == b) {
+ mp_int tmp;
+
+ if ((res = mp_init_copy(&tmp, a)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_sub(&tmp, b)) != MP_OKAY) {
+ mp_clear(&tmp);
+ return res;
+ }
+
+ s_mp_exch(&tmp, c);
+ mp_clear(&tmp);
+
+ } else {
+
+ if (c != a && (res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_sub(c, b)) != MP_OKAY)
+ return res;
+
+ }
+
+ } else if (cmp == 0) { /* different sign, a == b */
+
+ mp_zero(c);
+ return MP_OKAY;
+
+ } else { /* different sign: a < b */
+
+ /* See above... */
+ if (c == a) {
+ mp_int tmp;
+
+ if ((res = mp_init_copy(&tmp, b)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_sub(&tmp, a)) != MP_OKAY) {
+ mp_clear(&tmp);
+ return res;
+ }
+
+ s_mp_exch(&tmp, c);
+ mp_clear(&tmp);
+
+ } else {
+
+ if (c != b && (res = mp_copy(b, c)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_sub(c, a)) != MP_OKAY)
+ return res;
+
+ }
+ }
+
+ if (USED(c) == 1 && DIGIT(c, 0) == 0)
+ SIGN(c) = MP_ZPOS;
+
+ return MP_OKAY;
+
+} /* end mp_add() */
+
+/* }}} */
+
+/* {{{ mp_sub(a, b, c) */
+
+/*
+ mp_sub(a, b, c)
+
+ Compute c = a - b. All parameters may be identical.
+ */
+
+mp_err mp_sub(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_err res;
+ int cmp;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ if (SIGN(a) != SIGN(b)) {
+ if (c == a) {
+ if ((res = s_mp_add(c, b)) != MP_OKAY)
+ return res;
+ } else {
+ if (c != b && ((res = mp_copy(b, c)) != MP_OKAY))
+ return res;
+ if ((res = s_mp_add(c, a)) != MP_OKAY)
+ return res;
+ SIGN(c) = SIGN(a);
+ }
+
+ } else if ((cmp = s_mp_cmp(a, b)) > 0) { /* Same sign, a > b */
+ if (c == b) {
+ mp_int tmp;
+
+ if ((res = mp_init_copy(&tmp, a)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_sub(&tmp, b)) != MP_OKAY) {
+ mp_clear(&tmp);
+ return res;
+ }
+ s_mp_exch(&tmp, c);
+ mp_clear(&tmp);
+
+ } else {
+ if (c != a && ((res = mp_copy(a, c)) != MP_OKAY))
+ return res;
+
+ if ((res = s_mp_sub(c, b)) != MP_OKAY)
+ return res;
+ }
+
+ } else if (cmp == 0) { /* Same sign, equal magnitude */
+ mp_zero(c);
+ return MP_OKAY;
+
+ } else { /* Same sign, b > a */
+ if (c == a) {
+ mp_int tmp;
+
+ if ((res = mp_init_copy(&tmp, b)) != MP_OKAY)
+ return res;
+
+ if ((res = s_mp_sub(&tmp, a)) != MP_OKAY) {
+ mp_clear(&tmp);
+ return res;
+ }
+ s_mp_exch(&tmp, c);
+ mp_clear(&tmp);
+
+ } else {
+ if (c != b && ((res = mp_copy(b, c)) != MP_OKAY))
+ return res;
+
+ if ((res = s_mp_sub(c, a)) != MP_OKAY)
+ return res;
+ }
+
+ SIGN(c) = !SIGN(b);
+ }
+
+ if (USED(c) == 1 && DIGIT(c, 0) == 0)
+ SIGN(c) = MP_ZPOS;
+
+ return MP_OKAY;
+
+} /* end mp_sub() */
+
+/* }}} */
+
+/* {{{ mp_mul(a, b, c) */
+
+/*
+ mp_mul(a, b, c)
+
+ Compute c = a * b. All parameters may be identical.
+ */
+
+mp_err mp_mul(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_err res;
+ mp_sign sgn;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ sgn = (SIGN(a) == SIGN(b)) ? MP_ZPOS : MP_NEG;
+
+ if (c == b) {
+ if ((res = s_mp_mul(c, a)) != MP_OKAY)
+ return res;
+
+ } else {
+ if ((res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ if ((res = s_mp_mul(c, b)) != MP_OKAY)
+ return res;
+ }
+
+ if (sgn == MP_ZPOS || s_mp_cmp_d(c, 0) == MP_EQ)
+ SIGN(c) = MP_ZPOS;
+ else
+ SIGN(c) = sgn;
+
+ return MP_OKAY;
+
+} /* end mp_mul() */
+
+/* }}} */
+
+/* {{{ mp_mul_2d(a, d, c) */
+
+/*
+ mp_mul_2d(a, d, c)
+
+ Compute c = a * 2^d. a may be the same as c.
+ */
+
+mp_err mp_mul_2d(mp_int *a, mp_digit d, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ if (d == 0)
+ return MP_OKAY;
+
+ return s_mp_mul_2d(c, d);
+
+} /* end mp_mul() */
+
+/* }}} */
+
+/* {{{ mp_sqr(a, b) */
+
+#if MP_SQUARE
+mp_err mp_sqr(mp_int *a, mp_int *b)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if ((res = mp_copy(a, b)) != MP_OKAY)
+ return res;
+
+ if ((res = s_mp_sqr(b)) != MP_OKAY)
+ return res;
+
+ SIGN(b) = MP_ZPOS;
+
+ return MP_OKAY;
+
+} /* end mp_sqr() */
+#endif
+
+/* }}} */
+
+/* {{{ mp_div(a, b, q, r) */
+
+/*
+ mp_div(a, b, q, r)
+
+ Compute q = a / b and r = a mod b. Input parameters may be re-used
+ as output parameters. If q or r is NULL, that portion of the
+ computation will be discarded (although it will still be computed)
+
+ Pay no attention to the hacker behind the curtain.
+ */
+
+mp_err mp_div(mp_int *a, mp_int *b, mp_int *q, mp_int *r)
+{
+ mp_err res;
+ mp_int qtmp, rtmp;
+ int cmp;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ if (mp_cmp_z(b) == MP_EQ)
+ return MP_RANGE;
+
+ /* If a <= b, we can compute the solution without division, and
+ avoid any memory allocation
+ */
+ if ((cmp = s_mp_cmp(a, b)) < 0) {
+ if (r) {
+ if ((res = mp_copy(a, r)) != MP_OKAY)
+ return res;
+ }
+
+ if (q)
+ mp_zero(q);
+
+ return MP_OKAY;
+
+ } else if (cmp == 0) {
+
+ /* Set quotient to 1, with appropriate sign */
+ if (q) {
+ int qneg = (SIGN(a) != SIGN(b));
+
+ mp_set(q, 1);
+ if (qneg)
+ SIGN(q) = MP_NEG;
+ }
+
+ if (r)
+ mp_zero(r);
+
+ return MP_OKAY;
+ }
+
+ /* If we get here, it means we actually have to do some division */
+
+ /* Set up some temporaries... */
+ if ((res = mp_init_copy(&qtmp, a)) != MP_OKAY)
+ return res;
+ if ((res = mp_init_copy(&rtmp, b)) != MP_OKAY)
+ goto CLEANUP;
+
+ if ((res = s_mp_div(&qtmp, &rtmp)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* Compute the signs for the output */
+ SIGN(&rtmp) = SIGN(a); /* Sr = Sa */
+ if (SIGN(a) == SIGN(b))
+ SIGN(&qtmp) = MP_ZPOS; /* Sq = MP_ZPOS if Sa = Sb */
+ else
+ SIGN(&qtmp) = MP_NEG; /* Sq = MP_NEG if Sa != Sb */
+
+ if (s_mp_cmp_d(&qtmp, 0) == MP_EQ)
+ SIGN(&qtmp) = MP_ZPOS;
+ if (s_mp_cmp_d(&rtmp, 0) == MP_EQ)
+ SIGN(&rtmp) = MP_ZPOS;
+
+ /* Copy output, if it is needed */
+ if (q)
+ s_mp_exch(&qtmp, q);
+
+ if (r)
+ s_mp_exch(&rtmp, r);
+
+CLEANUP:
+ mp_clear(&rtmp);
+ mp_clear(&qtmp);
+
+ return res;
+
+} /* end mp_div() */
+
+/* }}} */
+
+/* {{{ mp_div_2d(a, d, q, r) */
+
+mp_err mp_div_2d(mp_int *a, mp_digit d, mp_int *q, mp_int *r)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL, MP_BADARG);
+
+ if (q) {
+ if ((res = mp_copy(a, q)) != MP_OKAY)
+ return res;
+
+ s_mp_div_2d(q, d);
+ }
+
+ if (r) {
+ if ((res = mp_copy(a, r)) != MP_OKAY)
+ return res;
+
+ s_mp_mod_2d(r, d);
+ }
+
+ return MP_OKAY;
+
+} /* end mp_div_2d() */
+
+/* }}} */
+
+/* {{{ mp_expt(a, b, c) */
+
+/*
+ mp_expt(a, b, c)
+
+ Compute c = a ** b, that is, raise a to the b power. Uses a
+ standard iterative square-and-multiply technique.
+ */
+
+mp_err mp_expt(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_int s, x;
+ mp_err res;
+ mp_digit d;
+ int dig, bit;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ if (mp_cmp_z(b) < 0)
+ return MP_RANGE;
+
+ if ((res = mp_init(&s)) != MP_OKAY)
+ return res;
+
+ mp_set(&s, 1);
+
+ if ((res = mp_init_copy(&x, a)) != MP_OKAY)
+ goto X;
+
+ /* Loop over low-order digits in ascending order */
+ for (dig = 0; dig < (USED(b) - 1); dig++) {
+ d = DIGIT(b, dig);
+
+ /* Loop over bits of each non-maximal digit */
+ for (bit = 0; bit < DIGIT_BIT; bit++) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d >>= 1;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+ }
+
+ /* Consider now the last digit... */
+ d = DIGIT(b, dig);
+
+ while (d) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d >>= 1;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ if (mp_iseven(b))
+ SIGN(&s) = SIGN(a);
+
+ res = mp_copy(&s, c);
+
+CLEANUP:
+ mp_clear(&x);
+X:
+ mp_clear(&s);
+
+ return res;
+
+} /* end mp_expt() */
+
+/* }}} */
+
+/* {{{ mp_2expt(a, k) */
+
+/* Compute a = 2^k */
+
+mp_err mp_2expt(mp_int *a, mp_digit k)
+{
+ ARGCHK(a != NULL, MP_BADARG);
+
+ return s_mp_2expt(a, k);
+
+} /* end mp_2expt() */
+
+/* }}} */
+
+/* {{{ mp_mod(a, m, c) */
+
+/*
+ mp_mod(a, m, c)
+
+ Compute c = a (mod m). Result will always be 0 <= c < m.
+ */
+
+mp_err mp_mod(mp_int *a, mp_int *m, mp_int *c)
+{
+ mp_err res;
+ int mag;
+
+ ARGCHK(a != NULL && m != NULL && c != NULL, MP_BADARG);
+
+ if (SIGN(m) == MP_NEG)
+ return MP_RANGE;
+
+ /*
+ If |a| > m, we need to divide to get the remainder and take the
+ absolute value.
+
+ If |a| < m, we don't need to do any division, just copy and adjust
+ the sign (if a is negative).
+
+ If |a| == m, we can simply set the result to zero.
+
+ This order is intended to minimize the average path length of the
+ comparison chain on common workloads -- the most frequent cases are
+ that |a| != m, so we do those first.
+ */
+ if ((mag = s_mp_cmp(a, m)) > 0) {
+ if ((res = mp_div(a, m, NULL, c)) != MP_OKAY)
+ return res;
+
+ if (SIGN(c) == MP_NEG) {
+ if ((res = mp_add(c, m, c)) != MP_OKAY)
+ return res;
+ }
+
+ } else if (mag < 0) {
+ if ((res = mp_copy(a, c)) != MP_OKAY)
+ return res;
+
+ if (mp_cmp_z(a) < 0) {
+ if ((res = mp_add(c, m, c)) != MP_OKAY)
+ return res;
+
+ }
+
+ } else
+ mp_zero(c);
+
+
+ return MP_OKAY;
+
+} /* end mp_mod() */
+
+/* }}} */
+
+/* {{{ mp_mod_d(a, d, c) */
+
+/*
+ mp_mod_d(a, d, c)
+
+ Compute c = a (mod d). Result will always be 0 <= c < d
+ */
+mp_err mp_mod_d(mp_int *a, mp_digit d, mp_digit *c)
+{
+ mp_err res;
+ mp_digit rem;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if (s_mp_cmp_d(a, d) > 0) {
+ if ((res = mp_div_d(a, d, NULL, &rem)) != MP_OKAY)
+ return res;
+
+ } else {
+ if (SIGN(a) == MP_NEG)
+ rem = d - DIGIT(a, 0);
+ else
+ rem = DIGIT(a, 0);
+ }
+
+ if (c)
+ *c = rem;
+
+ return MP_OKAY;
+
+} /* end mp_mod_d() */
+
+/* }}} */
+
+/* {{{ mp_sqrt(a, b) */
+
+/*
+ mp_sqrt(a, b)
+
+ Compute the integer square root of a, and store the result in b.
+ Uses an integer-arithmetic version of Newton's iterative linear
+ approximation technique to determine this value; the result has the
+ following two properties:
+
+ b^2 <= a
+ (b+1)^2 >= a
+
+ It is a range error to pass a negative value.
+ */
+mp_err mp_sqrt(mp_int *a, mp_int *b)
+{
+ mp_int x, t;
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL, MP_BADARG);
+
+ /* Cannot take square root of a negative value */
+ if (SIGN(a) == MP_NEG)
+ return MP_RANGE;
+
+ /* Special cases for zero and one, trivial */
+ if (mp_cmp_d(a, 0) == MP_EQ || mp_cmp_d(a, 1) == MP_EQ)
+ return mp_copy(a, b);
+
+ /* Initialize the temporaries we'll use below */
+ if ((res = mp_init_size(&t, USED(a))) != MP_OKAY)
+ return res;
+
+ /* Compute an initial guess for the iteration as a itself */
+ if ((res = mp_init_copy(&x, a)) != MP_OKAY)
+ goto X;
+
+ s_mp_rshd(&x, (USED(&x) / 2) + 1);
+ mp_add_d(&x, 1, &x);
+
+ for (;;) {
+ /* t = (x * x) - a */
+ mp_copy(&x, &t); /* can't fail, t is big enough for original x */
+ if ((res = mp_sqr(&t, &t)) != MP_OKAY ||
+ (res = mp_sub(&t, a, &t)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* t = t / 2x */
+ s_mp_mul_2(&x);
+ if ((res = mp_div(&t, &x, &t, NULL)) != MP_OKAY)
+ goto CLEANUP;
+ s_mp_div_2(&x);
+
+ /* Terminate the loop, if the quotient is zero */
+ if (mp_cmp_z(&t) == MP_EQ)
+ break;
+
+ /* x = x - t */
+ if ((res = mp_sub(&x, &t, &x)) != MP_OKAY)
+ goto CLEANUP;
+
+ }
+
+ /* Copy result to output parameter */
+ mp_sub_d(&x, 1, &x);
+ s_mp_exch(&x, b);
+
+CLEANUP:
+ mp_clear(&x);
+X:
+ mp_clear(&t);
+
+ return res;
+
+} /* end mp_sqrt() */
+
+/* }}} */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ Modular arithmetic */
+
+#if MP_MODARITH
+/* {{{ mp_addmod(a, b, m, c) */
+
+/*
+ mp_addmod(a, b, m, c)
+
+ Compute c = (a + b) mod m
+ */
+
+mp_err mp_addmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL && m != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_add(a, b, c)) != MP_OKAY)
+ return res;
+ if ((res = mp_mod(c, m, c)) != MP_OKAY)
+ return res;
+
+ return MP_OKAY;
+
+}
+
+/* }}} */
+
+/* {{{ mp_submod(a, b, m, c) */
+
+/*
+ mp_submod(a, b, m, c)
+
+ Compute c = (a - b) mod m
+ */
+
+mp_err mp_submod(mp_int *a, mp_int *b, mp_int *m, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL && m != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_sub(a, b, c)) != MP_OKAY)
+ return res;
+ if ((res = mp_mod(c, m, c)) != MP_OKAY)
+ return res;
+
+ return MP_OKAY;
+
+}
+
+/* }}} */
+
+/* {{{ mp_mulmod(a, b, m, c) */
+
+/*
+ mp_mulmod(a, b, m, c)
+
+ Compute c = (a * b) mod m
+ */
+
+mp_err mp_mulmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL && m != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_mul(a, b, c)) != MP_OKAY)
+ return res;
+ if ((res = mp_mod(c, m, c)) != MP_OKAY)
+ return res;
+
+ return MP_OKAY;
+
+}
+
+/* }}} */
+
+/* {{{ mp_sqrmod(a, m, c) */
+
+#if MP_SQUARE
+mp_err mp_sqrmod(mp_int *a, mp_int *m, mp_int *c)
+{
+ mp_err res;
+
+ ARGCHK(a != NULL && m != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_sqr(a, c)) != MP_OKAY)
+ return res;
+ if ((res = mp_mod(c, m, c)) != MP_OKAY)
+ return res;
+
+ return MP_OKAY;
+
+} /* end mp_sqrmod() */
+#endif
+
+/* }}} */
+
+/* {{{ mp_exptmod(a, b, m, c) */
+
+/*
+ mp_exptmod(a, b, m, c)
+
+ Compute c = (a ** b) mod m. Uses a standard square-and-multiply
+ method with modular reductions at each step. (This is basically the
+ same code as mp_expt(), except for the addition of the reductions)
+
+ The modular reductions are done using Barrett's algorithm (see
+ s_mp_reduce() below for details)
+ */
+
+mp_err mp_exptmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c)
+{
+ mp_int s, x, mu;
+ mp_err res;
+ mp_digit d, *db = DIGITS(b);
+ mp_size ub = USED(b);
+ int dig, bit;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ if (mp_cmp_z(b) < 0 || mp_cmp_z(m) <= 0)
+ return MP_RANGE;
+
+ if ((res = mp_init(&s)) != MP_OKAY)
+ return res;
+
+ if ((res = mp_init_copy(&x, a)) != MP_OKAY)
+ goto X;
+
+ if ((res = mp_mod(&x, m, &x)) != MP_OKAY ||
+ (res = mp_init(&mu)) != MP_OKAY)
+ goto MU;
+
+ mp_set(&s, 1);
+
+ /* mu = b^2k / m */
+ res = s_mp_add_d(&mu, 1);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+
+ res = s_mp_lshd(&mu, 2 * USED(m));
+ if (res != MP_OKAY)
+ goto CLEANUP;
+
+ if ((res = mp_div(&mu, m, &mu, NULL)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* Loop over digits of b in ascending order, except highest order */
+ for (dig = 0; dig < (ub - 1); dig++) {
+ d = *db++;
+
+ /* Loop over the bits of the lower-order digits */
+ for (bit = 0; bit < DIGIT_BIT; bit++) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = s_mp_reduce(&s, m, &mu)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d >>= 1;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = s_mp_reduce(&x, m, &mu)) != MP_OKAY)
+ goto CLEANUP;
+ }
+ }
+
+ /* Now do the last digit... */
+ d = *db;
+
+ while (d) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = s_mp_reduce(&s, m, &mu)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d >>= 1;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = s_mp_reduce(&x, m, &mu)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ s_mp_exch(&s, c);
+
+CLEANUP:
+ mp_clear(&mu);
+MU:
+ mp_clear(&x);
+X:
+ mp_clear(&s);
+
+ return res;
+
+} /* end mp_exptmod() */
+
+/* }}} */
+
+/* {{{ mp_exptmod_d(a, d, m, c) */
+
+mp_err mp_exptmod_d(mp_int *a, mp_digit d, mp_int *m, mp_int *c)
+{
+ mp_int s, x;
+ mp_err res;
+
+ ARGCHK(a != NULL && c != NULL, MP_BADARG);
+
+ if ((res = mp_init(&s)) != MP_OKAY)
+ return res;
+ if ((res = mp_init_copy(&x, a)) != MP_OKAY)
+ goto X;
+
+ mp_set(&s, 1);
+
+ while (d != 0) {
+ if (d & 1) {
+ if ((res = s_mp_mul(&s, &x)) != MP_OKAY ||
+ (res = mp_mod(&s, m, &s)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ d /= 2;
+
+ if ((res = s_mp_sqr(&x)) != MP_OKAY ||
+ (res = mp_mod(&x, m, &x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ s_mp_exch(&s, c);
+
+CLEANUP:
+ mp_clear(&x);
+X:
+ mp_clear(&s);
+
+ return res;
+
+} /* end mp_exptmod_d() */
+
+/* }}} */
+#endif /* if MP_MODARITH */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ Comparison functions */
+
+/* {{{ mp_cmp_z(a) */
+
+/*
+ mp_cmp_z(a)
+
+ Compare a <=> 0. Returns <0 if a<0, 0 if a=0, >0 if a>0.
+ */
+
+int mp_cmp_z(mp_int *a)
+{
+ if (SIGN(a) == MP_NEG)
+ return MP_LT;
+ else if (USED(a) == 1 && DIGIT(a, 0) == 0)
+ return MP_EQ;
+ else
+ return MP_GT;
+
+} /* end mp_cmp_z() */
+
+/* }}} */
+
+/* {{{ mp_cmp_d(a, d) */
+
+/*
+ mp_cmp_d(a, d)
+
+ Compare a <=> d. Returns <0 if a<d, 0 if a=d, >0 if a>d
+ */
+
+int mp_cmp_d(mp_int *a, mp_digit d)
+{
+ ARGCHK(a != NULL, MP_EQ);
+
+ if (SIGN(a) == MP_NEG)
+ return MP_LT;
+
+ return s_mp_cmp_d(a, d);
+
+} /* end mp_cmp_d() */
+
+/* }}} */
+
+/* {{{ mp_cmp(a, b) */
+
+int mp_cmp(mp_int *a, mp_int *b)
+{
+ ARGCHK(a != NULL && b != NULL, MP_EQ);
+
+ if (SIGN(a) == SIGN(b)) {
+ int mag;
+
+ if ((mag = s_mp_cmp(a, b)) == MP_EQ)
+ return MP_EQ;
+
+ if (SIGN(a) == MP_ZPOS)
+ return mag;
+ else
+ return -mag;
+
+ } else if (SIGN(a) == MP_ZPOS)
+ return MP_GT;
+
+ else
+ return MP_LT;
+
+} /* end mp_cmp() */
+
+/* }}} */
+
+/* {{{ mp_cmp_mag(a, b) */
+
+/*
+ mp_cmp_mag(a, b)
+
+ Compares |a| <=> |b|, and returns an appropriate comparison result
+ */
+
+int mp_cmp_mag(mp_int *a, mp_int *b)
+{
+ ARGCHK(a != NULL && b != NULL, MP_EQ);
+
+ return s_mp_cmp(a, b);
+
+} /* end mp_cmp_mag() */
+
+/* }}} */
+
+/* {{{ mp_cmp_int(a, z) */
+
+/*
+ This just converts z to an mp_int, and uses the existing comparison
+ routines. This is sort of inefficient, but it's not clear to me how
+ frequently this wil get used anyway. For small positive constants,
+ you can always use mp_cmp_d(), and for zero, there is mp_cmp_z().
+ */
+/*int mp_cmp_int(mp_int *a, long z)
+{
+ mp_int tmp;
+ int out;
+ mp_err res;
+
+ ARGCHK(a != NULL, MP_EQ);
+
+ res = mp_init(&tmp);
+ if (res != MP_OKAY)
+ return MP_EQ;
+ mp_set_int(&tmp, z);
+ out = mp_cmp(a, &tmp);
+ mp_clear(&tmp);
+
+ return out;
+
+}*/ /* end mp_cmp_int() */
+
+/* }}} */
+
+/* {{{ mp_isodd(a) */
+
+/*
+ mp_isodd(a)
+
+ Returns a true (non-zero) value if a is odd, false (zero) otherwise.
+ */
+int mp_isodd(mp_int *a)
+{
+ ARGCHK(a != NULL, 0);
+
+ return (DIGIT(a, 0) & 1);
+
+} /* end mp_isodd() */
+
+/* }}} */
+
+/* {{{ mp_iseven(a) */
+
+int mp_iseven(mp_int *a)
+{
+ return !mp_isodd(a);
+
+} /* end mp_iseven() */
+
+/* }}} */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ Number theoretic functions */
+
+#if MP_NUMTH
+/* {{{ mp_gcd(a, b, c) */
+
+/*
+ Like the old mp_gcd() function, except computes the GCD using the
+ binary algorithm due to Josef Stein in 1961 (via Knuth).
+ */
+mp_err mp_gcd(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_err res;
+ mp_int u, v, t;
+ mp_size k = 0;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ if (mp_cmp_z(a) == MP_EQ && mp_cmp_z(b) == MP_EQ)
+ return MP_RANGE;
+ if (mp_cmp_z(a) == MP_EQ)
+ return mp_copy(b, c);
+
+ else if (mp_cmp_z(b) == MP_EQ)
+ return mp_copy(a, c);
+
+ if ((res = mp_init(&t)) != MP_OKAY)
+ return res;
+ if ((res = mp_init_copy(&u, a)) != MP_OKAY)
+ goto U;
+ if ((res = mp_init_copy(&v, b)) != MP_OKAY)
+ goto V;
+
+ SIGN(&u) = MP_ZPOS;
+ SIGN(&v) = MP_ZPOS;
+
+ /* Divide out common factors of 2 until at least 1 of a, b is even */
+ while (mp_iseven(&u) && mp_iseven(&v)) {
+ s_mp_div_2(&u);
+ s_mp_div_2(&v);
+ ++k;
+ }
+
+ /* Initialize t */
+ if (mp_isodd(&u)) {
+ if ((res = mp_copy(&v, &t)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* t = -v */
+ if (SIGN(&v) == MP_ZPOS)
+ SIGN(&t) = MP_NEG;
+ else
+ SIGN(&t) = MP_ZPOS;
+
+ } else {
+ if ((res = mp_copy(&u, &t)) != MP_OKAY)
+ goto CLEANUP;
+
+ }
+
+ for (;;) {
+ while (mp_iseven(&t))
+ s_mp_div_2(&t);
+
+ if (mp_cmp_z(&t) == MP_GT) {
+ if ((res = mp_copy(&t, &u)) != MP_OKAY)
+ goto CLEANUP;
+
+ } else {
+ if ((res = mp_copy(&t, &v)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* v = -t */
+ if (SIGN(&t) == MP_ZPOS)
+ SIGN(&v) = MP_NEG;
+ else
+ SIGN(&v) = MP_ZPOS;
+ }
+
+ if ((res = mp_sub(&u, &v, &t)) != MP_OKAY)
+ goto CLEANUP;
+
+ if (s_mp_cmp_d(&t, 0) == MP_EQ)
+ break;
+ }
+
+ s_mp_2expt(&v, k); /* v = 2^k */
+ res = mp_mul(&u, &v, c); /* c = u * v */
+
+CLEANUP:
+ mp_clear(&v);
+V:
+ mp_clear(&u);
+U:
+ mp_clear(&t);
+
+ return res;
+
+} /* end mp_bgcd() */
+
+/* }}} */
+
+/* {{{ mp_lcm(a, b, c) */
+
+/* We compute the least common multiple using the rule:
+
+ ab = [a, b](a, b)
+
+ ... by computing the product, and dividing out the gcd.
+ */
+
+mp_err mp_lcm(mp_int *a, mp_int *b, mp_int *c)
+{
+ mp_int gcd, prod;
+ mp_err res;
+
+ ARGCHK(a != NULL && b != NULL && c != NULL, MP_BADARG);
+
+ /* Set up temporaries */
+ if ((res = mp_init(&gcd)) != MP_OKAY)
+ return res;
+ if ((res = mp_init(&prod)) != MP_OKAY)
+ goto GCD;
+
+ if ((res = mp_mul(a, b, &prod)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = mp_gcd(a, b, &gcd)) != MP_OKAY)
+ goto CLEANUP;
+
+ res = mp_div(&prod, &gcd, c, NULL);
+
+CLEANUP:
+ mp_clear(&prod);
+GCD:
+ mp_clear(&gcd);
+
+ return res;
+
+} /* end mp_lcm() */
+
+/* }}} */
+
+/* {{{ mp_xgcd(a, b, g, x, y) */
+
+/*
+ mp_xgcd(a, b, g, x, y)
+
+ Compute g = (a, b) and values x and y satisfying Bezout's identity
+ (that is, ax + by = g). This uses the extended binary GCD algorithm
+ based on the Stein algorithm used for mp_gcd()
+ */
+
+mp_err mp_xgcd(mp_int *a, mp_int *b, mp_int *g, mp_int *x, mp_int *y)
+{
+ mp_int gx, xc, yc, u, v, A, B, C, D;
+ mp_int *clean[9];
+ mp_err res;
+ int last = -1;
+
+ if (mp_cmp_z(b) == 0)
+ return MP_RANGE;
+
+ /* Initialize all these variables we need */
+ if ((res = mp_init(&u)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &u;
+ if ((res = mp_init(&v)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &v;
+ if ((res = mp_init(&gx)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &gx;
+ if ((res = mp_init(&A)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &A;
+ if ((res = mp_init(&B)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &B;
+ if ((res = mp_init(&C)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &C;
+ if ((res = mp_init(&D)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &D;
+ if ((res = mp_init_copy(&xc, a)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &xc;
+ mp_abs(&xc, &xc);
+ if ((res = mp_init_copy(&yc, b)) != MP_OKAY) goto CLEANUP;
+ clean[++last] = &yc;
+ mp_abs(&yc, &yc);
+
+ mp_set(&gx, 1);
+
+ /* Divide by two until at least one of them is even */
+ while (mp_iseven(&xc) && mp_iseven(&yc)) {
+ s_mp_div_2(&xc);
+ s_mp_div_2(&yc);
+ if ((res = s_mp_mul_2(&gx)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ res = mp_copy(&xc, &u);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+
+ res = mp_copy(&yc, &v);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+
+ mp_set(&A, 1);
+ mp_set(&D, 1);
+
+ /* Loop through binary GCD algorithm */
+ for (;;) {
+ while (mp_iseven(&u)) {
+ s_mp_div_2(&u);
+
+ if (mp_iseven(&A) && mp_iseven(&B)) {
+ s_mp_div_2(&A);
+ s_mp_div_2(&B);
+ } else {
+ if ((res = mp_add(&A, &yc, &A)) != MP_OKAY) goto CLEANUP;
+ s_mp_div_2(&A);
+ if ((res = mp_sub(&B, &xc, &B)) != MP_OKAY) goto CLEANUP;
+ s_mp_div_2(&B);
+ }
+ }
+
+ while (mp_iseven(&v)) {
+ s_mp_div_2(&v);
+
+ if (mp_iseven(&C) && mp_iseven(&D)) {
+ s_mp_div_2(&C);
+ s_mp_div_2(&D);
+ } else {
+ if ((res = mp_add(&C, &yc, &C)) != MP_OKAY) goto CLEANUP;
+ s_mp_div_2(&C);
+ if ((res = mp_sub(&D, &xc, &D)) != MP_OKAY) goto CLEANUP;
+ s_mp_div_2(&D);
+ }
+ }
+
+ if (mp_cmp(&u, &v) >= 0) {
+ if ((res = mp_sub(&u, &v, &u)) != MP_OKAY) goto CLEANUP;
+ if ((res = mp_sub(&A, &C, &A)) != MP_OKAY) goto CLEANUP;
+ if ((res = mp_sub(&B, &D, &B)) != MP_OKAY) goto CLEANUP;
+
+ } else {
+ if ((res = mp_sub(&v, &u, &v)) != MP_OKAY) goto CLEANUP;
+ if ((res = mp_sub(&C, &A, &C)) != MP_OKAY) goto CLEANUP;
+ if ((res = mp_sub(&D, &B, &D)) != MP_OKAY) goto CLEANUP;
+
+ }
+
+ /* If we're done, copy results to output */
+ if (mp_cmp_z(&u) == 0) {
+ if (x)
+ if ((res = mp_copy(&C, x)) != MP_OKAY) goto CLEANUP;
+
+ if (y)
+ if ((res = mp_copy(&D, y)) != MP_OKAY) goto CLEANUP;
+
+ if (g)
+ if ((res = mp_mul(&gx, &v, g)) != MP_OKAY) goto CLEANUP;
+
+ break;
+ }
+ }
+
+CLEANUP:
+ while (last >= 0)
+ mp_clear(clean[last--]);
+
+ return res;
+
+} /* end mp_xgcd() */
+
+/* }}} */
+
+/* {{{ mp_invmod(a, m, c) */
+
+/*
+ mp_invmod(a, m, c)
+
+ Compute c = a^-1 (mod m), if there is an inverse for a (mod m).
+ This is equivalent to the question of whether (a, m) = 1. If not,
+ MP_UNDEF is returned, and there is no inverse.
+ */
+
+mp_err mp_invmod(mp_int *a, mp_int *m, mp_int *c)
+{
+ mp_int g, x;
+ mp_err res;
+
+ ARGCHK(a && m && c, MP_BADARG);
+
+ if (mp_cmp_z(a) == 0 || mp_cmp_z(m) == 0)
+ return MP_RANGE;
+
+ if ((res = mp_init(&g)) != MP_OKAY)
+ return res;
+ if ((res = mp_init(&x)) != MP_OKAY)
+ goto X;
+
+ if ((res = mp_xgcd(a, m, &g, &x, NULL)) != MP_OKAY)
+ goto CLEANUP;
+
+ if (mp_cmp_d(&g, 1) != MP_EQ) {
+ res = MP_UNDEF;
+ goto CLEANUP;
+ }
+
+ res = mp_mod(&x, m, c);
+ SIGN(c) = SIGN(a);
+
+CLEANUP:
+ mp_clear(&x);
+X:
+ mp_clear(&g);
+
+ return res;
+
+} /* end mp_invmod() */
+
+/* }}} */
+#endif /* if MP_NUMTH */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ mp_print(mp, ofp) */
+
+#if MP_IOFUNC
+/*
+ mp_print(mp, ofp)
+
+ Print a textual representation of the given mp_int on the output
+ stream 'ofp'. Output is generated using the internal radix.
+ */
+
+void mp_print(mp_int *mp, FILE *ofp)
+{
+ int ix;
+
+ if (mp == NULL || ofp == NULL)
+ return;
+
+ fputc((SIGN(mp) == MP_NEG) ? '-' : '+', ofp);
+
+ for (ix = USED(mp) - 1; ix >= 0; ix--)
+ fprintf(ofp, DIGIT_FMT, DIGIT(mp, ix));
+
+} /* end mp_print() */
+
+#endif /* if MP_IOFUNC */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* {{{ More I/O Functions */
+
+/* {{{ mp_read_signed_bin(mp, str, len) */
+
+/*
+ mp_read_signed_bin(mp, str, len)
+
+ Read in a raw value (base 256) into the given mp_int
+ */
+
+mp_err mp_read_signed_bin(mp_int *mp, unsigned char *str, int len)
+{
+ mp_err res;
+
+ ARGCHK(mp != NULL && str != NULL && len > 0, MP_BADARG);
+
+ if ((res = mp_read_unsigned_bin(mp, str + 1, len - 1)) == MP_OKAY) {
+ /* Get sign from first byte */
+ if (str[0])
+ SIGN(mp) = MP_NEG;
+ else
+ SIGN(mp) = MP_ZPOS;
+ }
+
+ return res;
+
+} /* end mp_read_signed_bin() */
+
+/* }}} */
+
+/* {{{ mp_signed_bin_size(mp) */
+
+int mp_signed_bin_size(mp_int *mp)
+{
+ ARGCHK(mp != NULL, 0);
+
+ return mp_unsigned_bin_size(mp) + 1;
+
+} /* end mp_signed_bin_size() */
+
+/* }}} */
+
+/* {{{ mp_to_signed_bin(mp, str) */
+
+mp_err mp_to_signed_bin(mp_int *mp, unsigned char *str)
+{
+ ARGCHK(mp != NULL && str != NULL, MP_BADARG);
+
+ /* Caller responsible for allocating enough memory (use mp_raw_size(mp)) */
+ str[0] = (char)SIGN(mp);
+
+ return mp_to_unsigned_bin(mp, str + 1);
+
+} /* end mp_to_signed_bin() */
+
+/* }}} */
+
+/* {{{ mp_read_unsigned_bin(mp, str, len) */
+
+/*
+ mp_read_unsigned_bin(mp, str, len)
+
+ Read in an unsigned value (base 256) into the given mp_int
+ */
+
+mp_err mp_read_unsigned_bin(mp_int *mp, unsigned char *str, int len)
+{
+ int ix;
+ mp_err res;
+
+ ARGCHK(mp != NULL && str != NULL && len > 0, MP_BADARG);
+
+ mp_zero(mp);
+
+ for (ix = 0; ix < len; ix++) {
+ if ((res = s_mp_mul_2d(mp, CHAR_BIT)) != MP_OKAY)
+ return res;
+
+ if ((res = mp_add_d(mp, str[ix], mp)) != MP_OKAY)
+ return res;
+ }
+
+ return MP_OKAY;
+
+} /* end mp_read_unsigned_bin() */
+
+/* }}} */
+
+/* {{{ mp_unsigned_bin_size(mp) */
+
+int mp_unsigned_bin_size(mp_int *mp)
+{
+ mp_digit topdig;
+ int count;
+
+ ARGCHK(mp != NULL, 0);
+
+ /* Special case for the value zero */
+ if (USED(mp) == 1 && DIGIT(mp, 0) == 0)
+ return 1;
+
+ count = (USED(mp) - 1) * sizeof(mp_digit);
+ topdig = DIGIT(mp, USED(mp) - 1);
+
+ while (topdig != 0) {
+ ++count;
+ topdig >>= CHAR_BIT;
+ }
+
+ return count;
+
+} /* end mp_unsigned_bin_size() */
+
+/* }}} */
+
+/* {{{ mp_to_unsigned_bin(mp, str) */
+
+mp_err mp_to_unsigned_bin(mp_int *mp, unsigned char *str)
+{
+ mp_digit *dp, *end, d;
+ unsigned char *spos;
+
+ ARGCHK(mp != NULL && str != NULL, MP_BADARG);
+
+ dp = DIGITS(mp);
+ end = dp + USED(mp) - 1;
+ spos = str;
+
+ /* Special case for zero, quick test */
+ if (dp == end && *dp == 0) {
+ *str = '\0';
+ return MP_OKAY;
+ }
+
+ /* Generate digits in reverse order */
+ while (dp < end) {
+ int ix;
+
+ d = *dp;
+ for (ix = 0; ix < sizeof(mp_digit); ++ix) {
+ *spos = d & UCHAR_MAX;
+ d >>= CHAR_BIT;
+ ++spos;
+ }
+
+ ++dp;
+ }
+
+ /* Now handle last digit specially, high order zeroes are not written */
+ d = *end;
+ while (d != 0) {
+ *spos = d & UCHAR_MAX;
+ d >>= CHAR_BIT;
+ ++spos;
+ }
+
+ /* Reverse everything to get digits in the correct order */
+ while (--spos > str) {
+ unsigned char t = *str;
+ *str = *spos;
+ *spos = t;
+
+ ++str;
+ }
+
+ return MP_OKAY;
+
+} /* end mp_to_unsigned_bin() */
+
+/* }}} */
+
+/* {{{ mp_count_bits(mp) */
+
+int mp_count_bits(mp_int *mp)
+{
+ int len;
+ mp_digit d;
+
+ ARGCHK(mp != NULL, MP_BADARG);
+
+ len = DIGIT_BIT * (USED(mp) - 1);
+ d = DIGIT(mp, USED(mp) - 1);
+
+ while (d != 0) {
+ ++len;
+ d >>= 1;
+ }
+
+ return len;
+
+} /* end mp_count_bits() */
+
+/* }}} */
+
+/* {{{ mp_read_radix(mp, str, radix) */
+
+/*
+ mp_read_radix(mp, str, radix)
+
+ Read an integer from the given string, and set mp to the resulting
+ value. The input is presumed to be in base 10. Leading non-digit
+ characters are ignored, and the function reads until a non-digit
+ character or the end of the string.
+ */
+
+mp_err mp_read_radix(mp_int *mp, unsigned char *str, int radix)
+{
+ int ix = 0, val = 0;
+ mp_err res;
+ mp_sign sig = MP_ZPOS;
+
+ ARGCHK(mp != NULL && str != NULL && radix >= 2 && radix <= MAX_RADIX,
+ MP_BADARG);
+
+ mp_zero(mp);
+
+ /* Skip leading non-digit characters until a digit or '-' or '+' */
+ while (str[ix] &&
+ (s_mp_tovalue(str[ix], radix) < 0) &&
+ str[ix] != '-' &&
+ str[ix] != '+')
+ ++ix;
+
+ if (str[ix] == '-') {
+ sig = MP_NEG;
+ ++ix;
+ } else if (str[ix] == '+') {
+ sig = MP_ZPOS; /* this is the default anyway... */
+ ++ix;
+ }
+
+ while ((val = s_mp_tovalue(str[ix], radix)) >= 0) {
+ if ((res = s_mp_mul_d(mp, radix)) != MP_OKAY)
+ return res;
+ if ((res = s_mp_add_d(mp, val)) != MP_OKAY)
+ return res;
+ ++ix;
+ }
+
+ if (s_mp_cmp_d(mp, 0) == MP_EQ)
+ SIGN(mp) = MP_ZPOS;
+ else
+ SIGN(mp) = sig;
+
+ return MP_OKAY;
+
+} /* end mp_read_radix() */
+
+/* }}} */
+
+/* {{{ mp_radix_size(mp, radix) */
+
+int mp_radix_size(mp_int *mp, int radix)
+{
+ int len;
+ ARGCHK(mp != NULL, 0);
+
+ len = s_mp_outlen(mp_count_bits(mp), radix) + 1; /* for NUL terminator */
+
+ if (mp_cmp_z(mp) < 0)
+ ++len; /* for sign */
+
+ return len;
+
+} /* end mp_radix_size() */
+
+/* }}} */
+
+/* {{{ mp_value_radix_size(num, qty, radix) */
+
+/* num = number of digits
+ qty = number of bits per digit
+ radix = target base
+
+ Return the number of digits in the specified radix that would be
+ needed to express 'num' digits of 'qty' bits each.
+ */
+int mp_value_radix_size(int num, int qty, int radix)
+{
+ ARGCHK(num >= 0 && qty > 0 && radix >= 2 && radix <= MAX_RADIX, 0);
+
+ return s_mp_outlen(num * qty, radix);
+
+} /* end mp_value_radix_size() */
+
+/* }}} */
+
+/* {{{ mp_toradix(mp, str, radix) */
+
+mp_err mp_toradix(mp_int *mp, unsigned char *str, int radix)
+{
+ int ix, pos = 0;
+
+ ARGCHK(mp != NULL && str != NULL, MP_BADARG);
+ ARGCHK(radix > 1 && radix <= MAX_RADIX, MP_RANGE);
+
+ if (mp_cmp_z(mp) == MP_EQ) {
+ str[0] = '0';
+ str[1] = '\0';
+ } else {
+ mp_err res;
+ mp_int tmp;
+ mp_sign sgn;
+ mp_digit rem, rdx = (mp_digit)radix;
+ char ch;
+
+ if ((res = mp_init_copy(&tmp, mp)) != MP_OKAY)
+ return res;
+
+ /* Save sign for later, and take absolute value */
+ sgn = SIGN(&tmp);
+ SIGN(&tmp) = MP_ZPOS;
+
+ /* Generate output digits in reverse order */
+ while (mp_cmp_z(&tmp) != 0) {
+ if ((res = s_mp_div_d(&tmp, rdx, &rem)) != MP_OKAY) {
+ mp_clear(&tmp);
+ return res;
+ }
+
+ /* Generate digits, use capital letters */
+ ch = s_mp_todigit(rem, radix, 0);
+
+ str[pos++] = ch;
+ }
+
+ /* Add - sign if original value was negative */
+ if (sgn == MP_NEG)
+ str[pos++] = '-';
+
+ /* Add trailing NUL to end the string */
+ str[pos--] = '\0';
+
+ /* Reverse the digits and sign indicator */
+ ix = 0;
+ while (ix < pos) {
+ char tmp = str[ix];
+
+ str[ix] = str[pos];
+ str[pos] = tmp;
+ ++ix;
+ --pos;
+ }
+
+ mp_clear(&tmp);
+ }
+
+ return MP_OKAY;
+
+} /* end mp_toradix() */
+
+/* }}} */
+
+/* {{{ mp_char2value(ch, r) */
+
+int mp_char2value(char ch, int r)
+{
+ return s_mp_tovalue(ch, r);
+
+} /* end mp_tovalue() */
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ mp_strerror(ec) */
+
+/*
+ mp_strerror(ec)
+
+ Return a string describing the meaning of error code 'ec'. The
+ string returned is allocated in static memory, so the caller should
+ not attempt to modify or free the memory associated with this
+ string.
+ */
+const char *mp_strerror(mp_err ec)
+{
+ int aec = (ec < 0) ? -ec : ec;
+
+ /* Code values are negative, so the senses of these comparisons
+ are accurate */
+ if (ec < MP_LAST_CODE || ec > MP_OKAY) {
+ return mp_err_string[0]; /* unknown error code */
+ } else
+ return mp_err_string[aec + 1];
+
+} /* end mp_strerror() */
+
+/* }}} */
+
+/*========================================================================*/
+/*------------------------------------------------------------------------*/
+/* Static function definitions (internal use only) */
+
+/* {{{ Memory management */
+
+/* {{{ s_mp_grow(mp, min) */
+
+/* Make sure there are at least 'min' digits allocated to mp */
+mp_err s_mp_grow(mp_int *mp, mp_size min)
+{
+ if (min > ALLOC(mp)) {
+ mp_digit *tmp;
+
+ /* Set min to next nearest default precision block size */
+ min = ((min + (s_mp_defprec - 1)) / s_mp_defprec) * s_mp_defprec;
+
+ if ((tmp = s_mp_alloc(min, sizeof(mp_digit))) == NULL)
+ return MP_MEM;
+
+ s_mp_copy(DIGITS(mp), tmp, USED(mp));
+
+#if MP_CRYPTO
+ s_mp_setz(DIGITS(mp), ALLOC(mp));
+#endif
+ s_mp_free(DIGITS(mp));
+ DIGITS(mp) = tmp;
+ ALLOC(mp) = min;
+ }
+
+ return MP_OKAY;
+
+} /* end s_mp_grow() */
+
+/* }}} */
+
+/* {{{ s_mp_pad(mp, min) */
+
+/* Make sure the used size of mp is at least 'min', growing if needed */
+mp_err s_mp_pad(mp_int *mp, mp_size min)
+{
+ if (min > USED(mp)) {
+ mp_err res;
+
+ /* Make sure there is room to increase precision */
+ if (min > ALLOC(mp) && (res = s_mp_grow(mp, min)) != MP_OKAY)
+ return res;
+
+ /* Increase precision; should already be 0-filled */
+ USED(mp) = min;
+ }
+
+ return MP_OKAY;
+
+} /* end s_mp_pad() */
+
+/* }}} */
+
+/* {{{ s_mp_setz(dp, count) */
+
+#if MP_MACRO == 0
+/* Set 'count' digits pointed to by dp to be zeroes */
+void s_mp_setz(mp_digit *dp, mp_size count)
+{
+#if MP_MEMSET == 0
+ int ix;
+
+ for (ix = 0; ix < count; ix++)
+ dp[ix] = 0;
+#else
+ memset(dp, 0, count * sizeof(mp_digit));
+#endif
+
+} /* end s_mp_setz() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_copy(sp, dp, count) */
+
+#if MP_MACRO == 0
+/* Copy 'count' digits from sp to dp */
+void s_mp_copy(mp_digit *sp, mp_digit *dp, mp_size count)
+{
+#if MP_MEMCPY == 0
+ int ix;
+
+ for (ix = 0; ix < count; ix++)
+ dp[ix] = sp[ix];
+#else
+ memcpy(dp, sp, count * sizeof(mp_digit));
+#endif
+
+} /* end s_mp_copy() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_alloc(nb, ni) */
+
+#if MP_MACRO == 0
+/* Allocate ni records of nb bytes each, and return a pointer to that */
+void *s_mp_alloc(size_t nb, size_t ni)
+{
+ return calloc(nb, ni);
+
+} /* end s_mp_alloc() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_free(ptr) */
+
+#if MP_MACRO == 0
+/* Free the memory pointed to by ptr */
+void s_mp_free(void *ptr)
+{
+ if (ptr)
+ free(ptr);
+
+} /* end s_mp_free() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_clamp(mp) */
+
+/* Remove leading zeroes from the given value */
+void s_mp_clamp(mp_int *mp)
+{
+ mp_size du = USED(mp);
+ mp_digit *zp = DIGITS(mp) + du - 1;
+
+ while (du > 1 && !*zp--)
+ --du;
+
+ USED(mp) = du;
+
+} /* end s_mp_clamp() */
+
+
+/* }}} */
+
+/* {{{ s_mp_exch(a, b) */
+
+/* Exchange the data for a and b; (b, a) = (a, b) */
+void s_mp_exch(mp_int *a, mp_int *b)
+{
+ mp_int tmp;
+
+ tmp = *a;
+ *a = *b;
+ *b = tmp;
+
+} /* end s_mp_exch() */
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ Arithmetic helpers */
+
+/* {{{ s_mp_lshd(mp, p) */
+
+/*
+ Shift mp leftward by p digits, growing if needed, and zero-filling
+ the in-shifted digits at the right end. This is a convenient
+ alternative to multiplication by powers of the radix
+ */
+
+mp_err s_mp_lshd(mp_int *mp, mp_size p)
+{
+ mp_err res;
+ mp_size pos;
+ mp_digit *dp;
+ int ix;
+
+ if (p == 0)
+ return MP_OKAY;
+
+ if ((res = s_mp_pad(mp, USED(mp) + p)) != MP_OKAY)
+ return res;
+
+ pos = USED(mp) - 1;
+ dp = DIGITS(mp);
+
+ /* Shift all the significant figures over as needed */
+ for (ix = pos - p; ix >= 0; ix--)
+ dp[ix + p] = dp[ix];
+
+ /* Fill the bottom digits with zeroes */
+ for (ix = 0; ix < p; ix++)
+ dp[ix] = 0;
+
+ return MP_OKAY;
+
+} /* end s_mp_lshd() */
+
+/* }}} */
+
+/* {{{ s_mp_rshd(mp, p) */
+
+/*
+ Shift mp rightward by p digits. Maintains the invariant that
+ digits above the precision are all zero. Digits shifted off the
+ end are lost. Cannot fail.
+ */
+
+void s_mp_rshd(mp_int *mp, mp_size p)
+{
+ mp_size ix;
+ mp_digit *dp;
+
+ if (p == 0)
+ return;
+
+ /* Shortcut when all digits are to be shifted off */
+ if (p >= USED(mp)) {
+ s_mp_setz(DIGITS(mp), ALLOC(mp));
+ USED(mp) = 1;
+ SIGN(mp) = MP_ZPOS;
+ return;
+ }
+
+ /* Shift all the significant figures over as needed */
+ dp = DIGITS(mp);
+ for (ix = p; ix < USED(mp); ix++)
+ dp[ix - p] = dp[ix];
+
+ /* Fill the top digits with zeroes */
+ ix -= p;
+ while (ix < USED(mp))
+ dp[ix++] = 0;
+
+ /* Strip off any leading zeroes */
+ s_mp_clamp(mp);
+
+} /* end s_mp_rshd() */
+
+/* }}} */
+
+/* {{{ s_mp_div_2(mp) */
+
+/* Divide by two -- take advantage of radix properties to do it fast */
+void s_mp_div_2(mp_int *mp)
+{
+ s_mp_div_2d(mp, 1);
+
+} /* end s_mp_div_2() */
+
+/* }}} */
+
+/* {{{ s_mp_mul_2(mp) */
+
+mp_err s_mp_mul_2(mp_int *mp)
+{
+ int ix;
+ mp_digit kin = 0, kout, *dp = DIGITS(mp);
+ mp_err res;
+
+ /* Shift digits leftward by 1 bit */
+ for (ix = 0; ix < USED(mp); ix++) {
+ kout = (dp[ix] >> (DIGIT_BIT - 1)) & 1;
+ dp[ix] = (dp[ix] << 1) | kin;
+
+ kin = kout;
+ }
+
+ /* Deal with rollover from last digit */
+ if (kin) {
+ if (ix >= ALLOC(mp)) {
+ if ((res = s_mp_grow(mp, ALLOC(mp) + 1)) != MP_OKAY)
+ return res;
+ dp = DIGITS(mp);
+ }
+
+ dp[ix] = kin;
+ USED(mp) += 1;
+ }
+
+ return MP_OKAY;
+
+} /* end s_mp_mul_2() */
+
+/* }}} */
+
+/* {{{ s_mp_mod_2d(mp, d) */
+
+/*
+ Remainder the integer by 2^d, where d is a number of bits. This
+ amounts to a bitwise AND of the value, and does not require the full
+ division code
+ */
+void s_mp_mod_2d(mp_int *mp, mp_digit d)
+{
+ unsigned int ndig = (d / DIGIT_BIT), nbit = (d % DIGIT_BIT);
+ unsigned int ix;
+ mp_digit dmask, *dp = DIGITS(mp);
+
+ if (ndig >= USED(mp))
+ return;
+
+ /* Flush all the bits above 2^d in its digit */
+ dmask = (1 << nbit) - 1;
+ dp[ndig] &= dmask;
+
+ /* Flush all digits above the one with 2^d in it */
+ for (ix = ndig + 1; ix < USED(mp); ix++)
+ dp[ix] = 0;
+
+ s_mp_clamp(mp);
+
+} /* end s_mp_mod_2d() */
+
+/* }}} */
+
+/* {{{ s_mp_mul_2d(mp, d) */
+
+/*
+ Multiply by the integer 2^d, where d is a number of bits. This
+ amounts to a bitwise shift of the value, and does not require the
+ full multiplication code.
+ */
+mp_err s_mp_mul_2d(mp_int *mp, mp_digit d)
+{
+ mp_err res;
+ mp_digit save, next, mask, *dp;
+ mp_size used;
+ int ix;
+
+ if ((res = s_mp_lshd(mp, d / DIGIT_BIT)) != MP_OKAY)
+ return res;
+
+ dp = DIGITS(mp);
+ used = USED(mp);
+ d %= DIGIT_BIT;
+
+ mask = (1 << d) - 1;
+
+ /* If the shift requires another digit, make sure we've got one to
+ work with */
+ if ((dp[used - 1] >> (DIGIT_BIT - d)) & mask) {
+ if ((res = s_mp_grow(mp, used + 1)) != MP_OKAY)
+ return res;
+ dp = DIGITS(mp);
+ }
+
+ /* Do the shifting... */
+ save = 0;
+ for (ix = 0; ix < used; ix++) {
+ next = (dp[ix] >> (DIGIT_BIT - d)) & mask;
+ dp[ix] = (dp[ix] << d) | save;
+ save = next;
+ }
+
+ /* If, at this point, we have a nonzero carryout into the next
+ digit, we'll increase the size by one digit, and store it...
+ */
+ if (save) {
+ dp[used] = save;
+ USED(mp) += 1;
+ }
+
+ s_mp_clamp(mp);
+ return MP_OKAY;
+
+} /* end s_mp_mul_2d() */
+
+/* }}} */
+
+/* {{{ s_mp_div_2d(mp, d) */
+
+/*
+ Divide the integer by 2^d, where d is a number of bits. This
+ amounts to a bitwise shift of the value, and does not require the
+ full division code (used in Barrett reduction, see below)
+ */
+void s_mp_div_2d(mp_int *mp, mp_digit d)
+{
+ int ix;
+ mp_digit save, next, mask, *dp = DIGITS(mp);
+
+ s_mp_rshd(mp, d / DIGIT_BIT);
+ d %= DIGIT_BIT;
+
+ mask = (1 << d) - 1;
+
+ save = 0;
+ for (ix = USED(mp) - 1; ix >= 0; ix--) {
+ next = dp[ix] & mask;
+ dp[ix] = (dp[ix] >> d) | (save << (DIGIT_BIT - d));
+ save = next;
+ }
+
+ s_mp_clamp(mp);
+
+} /* end s_mp_div_2d() */
+
+/* }}} */
+
+/* {{{ s_mp_norm(a, b) */
+
+/*
+ s_mp_norm(a, b)
+
+ Normalize a and b for division, where b is the divisor. In order
+ that we might make good guesses for quotient digits, we want the
+ leading digit of b to be at least half the radix, which we
+ accomplish by multiplying a and b by a constant. This constant is
+ returned (so that it can be divided back out of the remainder at the
+ end of the division process).
+
+ We multiply by the smallest power of 2 that gives us a leading digit
+ at least half the radix. By choosing a power of 2, we simplify the
+ multiplication and division steps to simple shifts.
+ */
+mp_digit s_mp_norm(mp_int *a, mp_int *b)
+{
+ mp_digit t, d = 0;
+
+ t = DIGIT(b, USED(b) - 1);
+ while (t < (RADIX / 2)) {
+ t <<= 1;
+ ++d;
+ }
+
+ if (d != 0) {
+ s_mp_mul_2d(a, d);
+ s_mp_mul_2d(b, d);
+ }
+
+ return d;
+
+} /* end s_mp_norm() */
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ Primitive digit arithmetic */
+
+/* {{{ s_mp_add_d(mp, d) */
+
+/* Add d to |mp| in place */
+mp_err s_mp_add_d(mp_int *mp, mp_digit d) /* unsigned digit addition */
+{
+ mp_word w, k = 0;
+ mp_size ix = 1, used = USED(mp);
+ mp_digit *dp = DIGITS(mp);
+
+ w = dp[0] + d;
+ dp[0] = ACCUM(w);
+ k = CARRYOUT(w);
+
+ while (ix < used && k) {
+ w = dp[ix] + k;
+ dp[ix] = ACCUM(w);
+ k = CARRYOUT(w);
+ ++ix;
+ }
+
+ if (k != 0) {
+ mp_err res;
+
+ if ((res = s_mp_pad(mp, USED(mp) + 1)) != MP_OKAY)
+ return res;
+
+ DIGIT(mp, ix) = k;
+ }
+
+ return MP_OKAY;
+
+} /* end s_mp_add_d() */
+
+/* }}} */
+
+/* {{{ s_mp_sub_d(mp, d) */
+
+/* Subtract d from |mp| in place, assumes |mp| > d */
+mp_err s_mp_sub_d(mp_int *mp, mp_digit d) /* unsigned digit subtract */
+{
+ mp_word w, b = 0;
+ mp_size ix = 1, used = USED(mp);
+ mp_digit *dp = DIGITS(mp);
+
+ /* Compute initial subtraction */
+ w = (RADIX + dp[0]) - d;
+ b = CARRYOUT(w) ? 0 : 1;
+ dp[0] = ACCUM(w);
+
+ /* Propagate borrows leftward */
+ while (b && ix < used) {
+ w = (RADIX + dp[ix]) - b;
+ b = CARRYOUT(w) ? 0 : 1;
+ dp[ix] = ACCUM(w);
+ ++ix;
+ }
+
+ /* Remove leading zeroes */
+ s_mp_clamp(mp);
+
+ /* If we have a borrow out, it's a violation of the input invariant */
+ if (b)
+ return MP_RANGE;
+ else
+ return MP_OKAY;
+
+} /* end s_mp_sub_d() */
+
+/* }}} */
+
+/* {{{ s_mp_mul_d(a, d) */
+
+/* Compute a = a * d, single digit multiplication */
+mp_err s_mp_mul_d(mp_int *a, mp_digit d)
+{
+ mp_word w, k = 0;
+ mp_size ix, max;
+ mp_err res;
+ mp_digit *dp = DIGITS(a);
+
+ /*
+ Single-digit multiplication will increase the precision of the
+ output by at most one digit. However, we can detect when this
+ will happen -- if the high-order digit of a, times d, gives a
+ two-digit result, then the precision of the result will increase;
+ otherwise it won't. We use this fact to avoid calling s_mp_pad()
+ unless absolutely necessary.
+ */
+ max = USED(a);
+ w = dp[max - 1] * d;
+ if (CARRYOUT(w) != 0) {
+ if ((res = s_mp_pad(a, max + 1)) != MP_OKAY)
+ return res;
+ dp = DIGITS(a);
+ }
+
+ for (ix = 0; ix < max; ix++) {
+ w = (dp[ix] * d) + k;
+ dp[ix] = ACCUM(w);
+ k = CARRYOUT(w);
+ }
+
+ /* If there is a precision increase, take care of it here; the above
+ test guarantees we have enough storage to do this safely.
+ */
+ if (k) {
+ dp[max] = k;
+ USED(a) = max + 1;
+ }
+
+ s_mp_clamp(a);
+
+ return MP_OKAY;
+
+} /* end s_mp_mul_d() */
+
+/* }}} */
+
+/* {{{ s_mp_div_d(mp, d, r) */
+
+/*
+ s_mp_div_d(mp, d, r)
+
+ Compute the quotient mp = mp / d and remainder r = mp mod d, for a
+ single digit d. If r is null, the remainder will be discarded.
+ */
+
+mp_err s_mp_div_d(mp_int *mp, mp_digit d, mp_digit *r)
+{
+ mp_word w = 0, t;
+ mp_int quot;
+ mp_err res;
+ mp_digit *dp = DIGITS(mp), *qp;
+ int ix;
+
+ if (d == 0)
+ return MP_RANGE;
+
+ /* Make room for the quotient */
+ if ((res = mp_init_size(", USED(mp))) != MP_OKAY)
+ return res;
+
+ USED(") = USED(mp); /* so clamping will work below */
+ qp = DIGITS(");
+
+ /* Divide without subtraction */
+ for (ix = USED(mp) - 1; ix >= 0; ix--) {
+ w = (w << DIGIT_BIT) | dp[ix];
+
+ if (w >= d) {
+ t = w / d;
+ w = w % d;
+ } else
+ t = 0;
+
+ qp[ix] = t;
+ }
+
+ /* Deliver the remainder, if desired */
+ if (r)
+ *r = w;
+
+ s_mp_clamp(");
+ mp_exch(", mp);
+ mp_clear(");
+
+ return MP_OKAY;
+
+} /* end s_mp_div_d() */
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ Primitive full arithmetic */
+
+/* {{{ s_mp_add(a, b) */
+
+/* Compute a = |a| + |b| */
+mp_err s_mp_add(mp_int *a, mp_int *b) /* magnitude addition */
+{
+ mp_word w = 0;
+ mp_digit *pa, *pb;
+ mp_size ix, used = USED(b);
+ mp_err res;
+
+ /* Make sure a has enough precision for the output value */
+ if ((used > USED(a)) && (res = s_mp_pad(a, used)) != MP_OKAY)
+ return res;
+
+ /*
+ Add up all digits up to the precision of b. If b had initially
+ the same precision as a, or greater, we took care of it by the
+ padding step above, so there is no problem. If b had initially
+ less precision, we'll have to make sure the carry out is duly
+ propagated upward among the higher-order digits of the sum.
+ */
+ pa = DIGITS(a);
+ pb = DIGITS(b);
+ for (ix = 0; ix < used; ++ix) {
+ w += *pa + *pb++;
+ *pa++ = ACCUM(w);
+ w = CARRYOUT(w);
+ }
+
+ /* If we run out of 'b' digits before we're actually done, make
+ sure the carries get propagated upward...
+ */
+ used = USED(a);
+ while (w && ix < used) {
+ w += *pa;
+ *pa++ = ACCUM(w);
+ w = CARRYOUT(w);
+ ++ix;
+ }
+
+ /* If there's an overall carry out, increase precision and include
+ it. We could have done this initially, but why touch the memory
+ allocator unless we're sure we have to?
+ */
+ if (w) {
+ if ((res = s_mp_pad(a, used + 1)) != MP_OKAY)
+ return res;
+
+ DIGIT(a, ix) = w; /* pa may not be valid after s_mp_pad() call */
+ }
+
+ return MP_OKAY;
+
+} /* end s_mp_add() */
+
+/* }}} */
+
+/* {{{ s_mp_sub(a, b) */
+
+/* Compute a = |a| - |b|, assumes |a| >= |b| */
+mp_err s_mp_sub(mp_int *a, mp_int *b) /* magnitude subtract */
+{
+ mp_word w = 0;
+ mp_digit *pa, *pb;
+ mp_size ix, used = USED(b);
+
+ /*
+ Subtract and propagate borrow. Up to the precision of b, this
+ accounts for the digits of b; after that, we just make sure the
+ carries get to the right place. This saves having to pad b out to
+ the precision of a just to make the loops work right...
+ */
+ pa = DIGITS(a);
+ pb = DIGITS(b);
+
+ for (ix = 0; ix < used; ++ix) {
+ w = (RADIX + *pa) - w - *pb++;
+ *pa++ = ACCUM(w);
+ w = CARRYOUT(w) ? 0 : 1;
+ }
+
+ used = USED(a);
+ while (ix < used) {
+ w = RADIX + *pa - w;
+ *pa++ = ACCUM(w);
+ w = CARRYOUT(w) ? 0 : 1;
+ ++ix;
+ }
+
+ /* Clobber any leading zeroes we created */
+ s_mp_clamp(a);
+
+ /*
+ If there was a borrow out, then |b| > |a| in violation
+ of our input invariant. We've already done the work,
+ but we'll at least complain about it...
+ */
+ if (w)
+ return MP_RANGE;
+ else
+ return MP_OKAY;
+
+} /* end s_mp_sub() */
+
+/* }}} */
+
+mp_err s_mp_reduce(mp_int *x, mp_int *m, mp_int *mu)
+{
+ mp_int q;
+ mp_err res;
+ mp_size um = USED(m);
+
+ if ((res = mp_init_copy(&q, x)) != MP_OKAY)
+ return res;
+
+ s_mp_rshd(&q, um - 1); /* q1 = x / b^(k-1) */
+ res = s_mp_mul(&q, mu); /* q2 = q1 * mu */
+ if (res != MP_OKAY)
+ goto CLEANUP;
+ s_mp_rshd(&q, um + 1); /* q3 = q2 / b^(k+1) */
+
+ /* x = x mod b^(k+1), quick (no division) */
+ s_mp_mod_2d(x, (mp_digit)(DIGIT_BIT * (um + 1)));
+
+ /* q = q * m mod b^(k+1), quick (no division), uses the short multiplier */
+#ifndef SHRT_MUL
+ res = s_mp_mul(&q, m);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+ s_mp_mod_2d(&q, (mp_digit)(DIGIT_BIT * (um + 1)));
+#else
+ s_mp_mul_dig(&q, m, um + 1);
+#endif
+
+ /* x = x - q */
+ if ((res = mp_sub(x, &q, x)) != MP_OKAY)
+ goto CLEANUP;
+
+ /* If x < 0, add b^(k+1) to it */
+ if (mp_cmp_z(x) < 0) {
+ mp_set(&q, 1);
+ if ((res = s_mp_lshd(&q, um + 1)) != MP_OKAY)
+ goto CLEANUP;
+ if ((res = mp_add(x, &q, x)) != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ /* Back off if it's too big */
+ while (mp_cmp(x, m) >= 0) {
+ if ((res = s_mp_sub(x, m)) != MP_OKAY)
+ break;
+ }
+
+CLEANUP:
+ mp_clear(&q);
+
+ return res;
+
+} /* end s_mp_reduce() */
+
+
+
+/* {{{ s_mp_mul(a, b) */
+
+/* Compute a = |a| * |b| */
+mp_err s_mp_mul(mp_int *a, mp_int *b)
+{
+ mp_word w, k = 0;
+ mp_int tmp;
+ mp_err res;
+ mp_size ix, jx, ua = USED(a), ub = USED(b);
+ mp_digit *pa, *pb, *pt, *pbt;
+
+ if ((res = mp_init_size(&tmp, ua + ub)) != MP_OKAY)
+ return res;
+
+ /* This has the effect of left-padding with zeroes... */
+ USED(&tmp) = ua + ub;
+
+ /* We're going to need the base value each iteration */
+ pbt = DIGITS(&tmp);
+
+ /* Outer loop: Digits of b */
+
+ pb = DIGITS(b);
+ for (ix = 0; ix < ub; ++ix, ++pb) {
+ if (*pb == 0)
+ continue;
+
+ /* Inner product: Digits of a */
+ pa = DIGITS(a);
+ for (jx = 0; jx < ua; ++jx, ++pa) {
+ pt = pbt + ix + jx;
+ w = *pb **pa + k + *pt;
+ *pt = ACCUM(w);
+ k = CARRYOUT(w);
+ }
+
+ pbt[ix + jx] = k;
+ k = 0;
+ }
+
+ s_mp_clamp(&tmp);
+ s_mp_exch(&tmp, a);
+
+ mp_clear(&tmp);
+
+ return MP_OKAY;
+
+} /* end s_mp_mul() */
+
+/* }}} */
+
+/* {{{ s_mp_kmul(a, b, out, len) */
+
+#if 0
+void s_mp_kmul(mp_digit *a, mp_digit *b, mp_digit *out, mp_size len)
+{
+ mp_word w, k = 0;
+ mp_size ix, jx;
+ mp_digit *pa, *pt;
+
+ for (ix = 0; ix < len; ++ix, ++b) {
+ if (*b == 0)
+ continue;
+
+ pa = a;
+ for (jx = 0; jx < len; ++jx, ++pa) {
+ pt = out + ix + jx;
+ w = *b **pa + k + *pt;
+ *pt = ACCUM(w);
+ k = CARRYOUT(w);
+ }
+
+ out[ix + jx] = k;
+ k = 0;
+ }
+
+} /* end s_mp_kmul() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_sqr(a) */
+
+/*
+ Computes the square of a, in place. This can be done more
+ efficiently than a general multiplication, because many of the
+ computation steps are redundant when squaring. The inner product
+ step is a bit more complicated, but we save a fair number of
+ iterations of the multiplication loop.
+ */
+#if MP_SQUARE
+mp_err s_mp_sqr(mp_int *a)
+{
+ volatile mp_word w = 0;
+ mp_word k = 0;
+ mp_int tmp;
+ mp_err res;
+ mp_size ix, jx, kx, used = USED(a);
+ mp_digit *pa1, *pa2, *pt, *pbt;
+
+ if ((res = mp_init_size(&tmp, 2 * used)) != MP_OKAY)
+ return res;
+
+ /* Left-pad with zeroes */
+ USED(&tmp) = 2 * used;
+
+ /* We need the base value each time through the loop */
+ pbt = DIGITS(&tmp);
+
+ pa1 = DIGITS(a);
+ for (ix = 0; ix < used; ++ix, ++pa1) {
+ if (*pa1 == 0)
+ continue;
+
+ w = DIGIT(&tmp, ix + ix) + (*pa1 **pa1);
+
+ pbt[ix + ix] = ACCUM(w);
+ k = CARRYOUT(w);
+
+ /*
+ The inner product is computed as:
+
+ (C, S) = t[i,j] + 2 a[i] a[j] + C
+
+ This can overflow what can be represented in an mp_word, and
+ since C arithmetic does not provide any way to check for
+ overflow, we have to check explicitly for overflow conditions
+ before they happen.
+ */
+ for (jx = ix + 1, pa2 = DIGITS(a) + jx; jx < used; ++jx, ++pa2) {
+ mp_word u = 0, v;
+
+ /* Store this in a temporary to avoid indirections later */
+ pt = pbt + ix + jx;
+
+ /* Compute the multiplicative step */
+ w = *pa1 **pa2;
+
+ /* If w is more than half MP_WORD_MAX, the doubling will
+ overflow, and we need to record a carry out into the next
+ word */
+ u = (w >> (MP_WORD_BIT - 1)) & 1;
+
+ /* Double what we've got, overflow will be ignored as defined
+ for C arithmetic (we've already noted if it is to occur)
+ */
+ w *= 2;
+
+ /* Compute the additive step */
+ v = *pt + k;
+
+ /* If we do not already have an overflow carry, check to see
+ if the addition will cause one, and set the carry out if so
+ */
+ u |= ((MP_WORD_MAX - v) < w);
+
+ /* Add in the rest, again ignoring overflow */
+ w += v;
+
+ /* Set the i,j digit of the output */
+ *pt = ACCUM(w);
+
+ /* Save carry information for the next iteration of the loop.
+ This is why k must be an mp_word, instead of an mp_digit */
+ k = CARRYOUT(w) | (u << DIGIT_BIT);
+
+ } /* for(jx ...) */
+
+ /* Set the last digit in the cycle and reset the carry */
+ k = DIGIT(&tmp, ix + jx) + k;
+ pbt[ix + jx] = ACCUM(k);
+ k = CARRYOUT(k);
+
+ /* If we are carrying out, propagate the carry to the next digit
+ in the output. This may cascade, so we have to be somewhat
+ circumspect -- but we will have enough precision in the output
+ that we won't overflow
+ */
+ kx = 1;
+ while (k) {
+ k = pbt[ix + jx + kx] + 1;
+ pbt[ix + jx + kx] = ACCUM(k);
+ k = CARRYOUT(k);
+ ++kx;
+ }
+ } /* for(ix ...) */
+
+ s_mp_clamp(&tmp);
+ s_mp_exch(&tmp, a);
+
+ mp_clear(&tmp);
+
+ return MP_OKAY;
+
+} /* end s_mp_sqr() */
+#endif
+
+/* }}} */
+
+/* {{{ s_mp_div(a, b) */
+
+/*
+ s_mp_div(a, b)
+
+ Compute a = a / b and b = a mod b. Assumes b > a.
+ */
+
+mp_err s_mp_div(mp_int *a, mp_int *b)
+{
+ mp_int quot, rem, t;
+ mp_word q;
+ mp_err res;
+ mp_digit d;
+ int ix;
+
+ if (mp_cmp_z(b) == 0)
+ return MP_RANGE;
+
+ /* Shortcut if b is power of two */
+ if ((ix = s_mp_ispow2(b)) >= 0) {
+ res = mp_copy(a, b); /* need this for remainder */
+ if (res != MP_OKAY)
+ return res;
+ s_mp_div_2d(a, (mp_digit)ix);
+ s_mp_mod_2d(b, (mp_digit)ix);
+
+ return MP_OKAY;
+ }
+
+ /* Allocate space to store the quotient */
+ if ((res = mp_init_size(", USED(a))) != MP_OKAY)
+ return res;
+
+ /* A working temporary for division */
+ if ((res = mp_init_size(&t, USED(a))) != MP_OKAY)
+ goto T;
+
+ /* Allocate space for the remainder */
+ if ((res = mp_init_size(&rem, USED(a))) != MP_OKAY)
+ goto REM;
+
+ /* Normalize to optimize guessing */
+ d = s_mp_norm(a, b);
+
+ /* Perform the division itself...woo! */
+ ix = USED(a) - 1;
+
+ while (ix >= 0) {
+ /* Find a partial substring of a which is at least b */
+ while (s_mp_cmp(&rem, b) < 0 && ix >= 0) {
+ if ((res = s_mp_lshd(&rem, 1)) != MP_OKAY)
+ goto CLEANUP;
+
+ if ((res = s_mp_lshd(", 1)) != MP_OKAY)
+ goto CLEANUP;
+
+ DIGIT(&rem, 0) = DIGIT(a, ix);
+ s_mp_clamp(&rem);
+ --ix;
+ }
+
+ /* If we didn't find one, we're finished dividing */
+ if (s_mp_cmp(&rem, b) < 0)
+ break;
+
+ /* Compute a guess for the next quotient digit */
+ q = DIGIT(&rem, USED(&rem) - 1);
+ if (q <= DIGIT(b, USED(b) - 1) && USED(&rem) > 1)
+ q = (q << DIGIT_BIT) | DIGIT(&rem, USED(&rem) - 2);
+
+ q /= DIGIT(b, USED(b) - 1);
+
+ /* The guess can be as much as RADIX + 1 */
+ if (q >= RADIX)
+ q = RADIX - 1;
+
+ /* See what that multiplies out to */
+ res = mp_copy(b, &t);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+
+ if ((res = s_mp_mul_d(&t, q)) != MP_OKAY)
+ goto CLEANUP;
+
+ /*
+ If it's too big, back it off. We should not have to do this
+ more than once, or, in rare cases, twice. Knuth describes a
+ method by which this could be reduced to a maximum of once, but
+ I didn't implement that here.
+ */
+ while (s_mp_cmp(&t, &rem) > 0) {
+ --q;
+ res = s_mp_sub(&t, b);
+ if (res != MP_OKAY)
+ goto CLEANUP;
+ }
+
+ /* At this point, q should be the right next digit */
+ if ((res = s_mp_sub(&rem, &t)) != MP_OKAY)
+ goto CLEANUP;
+
+ /*
+ Include the digit in the quotient. We allocated enough memory
+ for any quotient we could ever possibly get, so we should not
+ have to check for failures here
+ */
+ DIGIT(", 0) = q;
+ }
+
+ /* Denormalize remainder */
+ if (d != 0)
+ s_mp_div_2d(&rem, d);
+
+ s_mp_clamp(");
+ s_mp_clamp(&rem);
+
+ /* Copy quotient back to output */
+ s_mp_exch(", a);
+
+ /* Copy remainder back to output */
+ s_mp_exch(&rem, b);
+
+CLEANUP:
+ mp_clear(&rem);
+REM:
+ mp_clear(&t);
+T:
+ mp_clear(");
+
+ return res;
+
+} /* end s_mp_div() */
+
+/* }}} */
+
+/* {{{ s_mp_2expt(a, k) */
+
+mp_err s_mp_2expt(mp_int *a, mp_digit k)
+{
+ mp_err res;
+ mp_size dig, bit;
+
+ dig = k / DIGIT_BIT;
+ bit = k % DIGIT_BIT;
+
+ mp_zero(a);
+ if ((res = s_mp_pad(a, dig + 1)) != MP_OKAY)
+ return res;
+
+ DIGIT(a, dig) |= (1 << bit);
+
+ return MP_OKAY;
+
+} /* end s_mp_2expt() */
+
+/* }}} */
+
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ Primitive comparisons */
+
+/* {{{ s_mp_cmp(a, b) */
+
+/* Compare |a| <=> |b|, return 0 if equal, <0 if a<b, >0 if a>b */
+int s_mp_cmp(mp_int *a, mp_int *b)
+{
+ mp_size ua = USED(a), ub = USED(b);
+
+ if (ua > ub)
+ return MP_GT;
+ else if (ua < ub)
+ return MP_LT;
+ else {
+ int ix = ua - 1;
+ mp_digit *ap = DIGITS(a) + ix, *bp = DIGITS(b) + ix;
+
+ while (ix >= 0) {
+ if (*ap > *bp)
+ return MP_GT;
+ else if (*ap < *bp)
+ return MP_LT;
+
+ --ap;
+ --bp;
+ --ix;
+ }
+
+ return MP_EQ;
+ }
+
+} /* end s_mp_cmp() */
+
+/* }}} */
+
+/* {{{ s_mp_cmp_d(a, d) */
+
+/* Compare |a| <=> d, return 0 if equal, <0 if a<d, >0 if a>d */
+int s_mp_cmp_d(mp_int *a, mp_digit d)
+{
+ mp_size ua = USED(a);
+ mp_digit *ap = DIGITS(a);
+
+ if (ua > 1)
+ return MP_GT;
+
+ if (*ap < d)
+ return MP_LT;
+ else if (*ap > d)
+ return MP_GT;
+ else
+ return MP_EQ;
+
+} /* end s_mp_cmp_d() */
+
+/* }}} */
+
+/* {{{ s_mp_ispow2(v) */
+
+/*
+ Returns -1 if the value is not a power of two; otherwise, it returns
+ k such that v = 2^k, i.e. lg(v).
+ */
+int s_mp_ispow2(mp_int *v)
+{
+ mp_digit d, *dp;
+ mp_size uv = USED(v);
+ int extra = 0, ix;
+
+ d = DIGIT(v, uv - 1); /* most significant digit of v */
+
+ while (d && ((d & 1) == 0)) {
+ d >>= 1;
+ ++extra;
+ }
+
+ if (d == 1) {
+ ix = uv - 2;
+ dp = DIGITS(v) + ix;
+
+ while (ix >= 0) {
+ if (*dp)
+ return -1; /* not a power of two */
+
+ --dp;
+ --ix;
+ }
+
+ return ((uv - 1) * DIGIT_BIT) + extra;
+ }
+
+ return -1;
+
+} /* end s_mp_ispow2() */
+
+/* }}} */
+
+/* {{{ s_mp_ispow2d(d) */
+
+int s_mp_ispow2d(mp_digit d)
+{
+ int pow = 0;
+
+ while ((d & 1) == 0) {
+ ++pow;
+ d >>= 1;
+ }
+
+ if (d == 1)
+ return pow;
+
+ return -1;
+
+} /* end s_mp_ispow2d() */
+
+/* }}} */
+
+/* }}} */
+
+/* {{{ Primitive I/O helpers */
+
+/* {{{ s_mp_tovalue(ch, r) */
+
+/*
+ Convert the given character to its digit value, in the given radix.
+ If the given character is not understood in the given radix, -1 is
+ returned. Otherwise the digit's numeric value is returned.
+
+ The results will be odd if you use a radix < 2 or > 62, you are
+ expected to know what you're up to.
+ */
+int s_mp_tovalue(char ch, int r)
+{
+ int val, xch;
+
+ if (r > 36)
+ xch = ch;
+ else
+ xch = toupper(ch);
+
+ if (isdigit(xch))
+ val = xch - '0';
+ else if (isupper(xch))
+ val = xch - 'A' + 10;
+ else if (islower(xch))
+ val = xch - 'a' + 36;
+ else if (xch == '+')
+ val = 62;
+ else if (xch == '/')
+ val = 63;
+ else
+ return -1;
+
+ if (val < 0 || val >= r)
+ return -1;
+
+ return val;
+
+} /* end s_mp_tovalue() */
+
+/* }}} */
+
+/* {{{ s_mp_todigit(val, r, low) */
+
+/*
+ Convert val to a radix-r digit, if possible. If val is out of range
+ for r, returns zero. Otherwise, returns an ASCII character denoting
+ the value in the given radix.
+
+ The results may be odd if you use a radix < 2 or > 64, you are
+ expected to know what you're doing.
+ */
+
+char s_mp_todigit(int val, int r, int low)
+{
+ char ch;
+
+ if (val < 0 || val >= r)
+ return 0;
+
+ ch = s_dmap_1[val];
+
+ if (r <= 36 && low)
+ ch = tolower(ch);
+
+ return ch;
+
+} /* end s_mp_todigit() */
+
+/* }}} */
+
+/* {{{ s_mp_outlen(bits, radix) */
+
+/*
+ Return an estimate for how long a string is needed to hold a radix
+ r representation of a number with 'bits' significant bits.
+
+ Does not include space for a sign or a NUL terminator.
+ */
+int s_mp_outlen(int bits, int r)
+{
+ return (int)((double)bits * LOG_V_2(r));
+
+} /* end s_mp_outlen() */
+
+/* }}} */
+
+/* }}} */
+
+/*------------------------------------------------------------------------*/
+/* HERE THERE BE DRAGONS */
+/* crc==4242132123, version==2, Sat Feb 02 06:43:52 2002 */
+
+/* $Source$ */
+/* $Revision: 0.36 $ */
+/* $Date: 2005-08-01 16:37:28 +0000 $ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/mpi.h b/src/bsp/lk/platform/mt2731/drivers/md/mpi.h
new file mode 100644
index 0000000..d9556c1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/mpi.h
@@ -0,0 +1,260 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef _H_MPI_
+#define _H_MPI_
+
+#include "mpi-config.h"
+
+#define MP_LT -1
+#define MP_EQ 0
+#define MP_GT 1
+
+#if MP_DEBUG
+#undef MP_IOFUNC
+#define MP_IOFUNC 1
+#endif
+
+#if MP_IOFUNC
+#include <stdio.h>
+#include <ctype.h>
+#endif
+
+#include <limits.h>
+
+#define MP_NEG 1
+#define MP_ZPOS 0
+
+/* Included for compatibility... */
+#define NEG MP_NEG
+#define ZPOS MP_ZPOS
+
+#define MP_OKAY 0 /* no error, all is well */
+#define MP_YES 0 /* yes (boolean result) */
+#define MP_NO -1 /* no (boolean result) */
+#define MP_MEM -2 /* out of memory */
+#define MP_RANGE -3 /* argument out of range */
+#define MP_BADARG -4 /* invalid parameter */
+#define MP_UNDEF -5 /* answer is undefined */
+#define MP_LAST_CODE MP_UNDEF
+
+#include "mpi-types.h"
+
+/* Included for compatibility... */
+#define DIGIT_BIT MP_DIGIT_BIT
+#define DIGIT_MAX MP_DIGIT_MAX
+
+/* Macros for accessing the mp_int internals */
+#define SIGN(MP) ((MP)->sign)
+#define USED(MP) ((MP)->used)
+#define ALLOC(MP) ((MP)->alloc)
+#define DIGITS(MP) ((MP)->dp)
+#define DIGIT(MP,N) (MP)->dp[(N)]
+
+#ifdef MP_ARGCHK
+# undef MP_ARGCHK
+# define MP_ARGCHK 2
+#endif
+
+#if MP_ARGCHK == 1
+#define ARGCHK(X,Y) {if(!(X)){return (Y);}}
+#elif MP_ARGCHK == 2
+#include <assert.h>
+#define ARGCHK(X,Y) assert(X)
+#else
+#define ARGCHK(X,Y) /* */
+#endif
+
+/* This defines the maximum I/O base (minimum is 2) */
+#define MAX_RADIX 64
+
+typedef struct {
+ mp_sign sign; /* sign of this quantity */
+ mp_size alloc; /* how many digits allocated */
+ mp_size used; /* how many digits used */
+ mp_digit *dp; /* the digits themselves */
+} mp_int;
+
+/*------------------------------------------------------------------------*/
+/* Default precision */
+
+unsigned int mp_get_prec(void);
+void mp_set_prec(unsigned int prec);
+
+/*------------------------------------------------------------------------*/
+/* Memory management */
+
+mp_err mp_init(mp_int *mp);
+mp_err mp_init_array(mp_int mp[], int count);
+mp_err mp_init_size(mp_int *mp, mp_size prec);
+mp_err mp_init_copy(mp_int *mp, mp_int *from);
+mp_err mp_copy(mp_int *from, mp_int *to);
+void mp_exch(mp_int *mp1, mp_int *mp2);
+void mp_clear(mp_int *mp);
+void mp_clear_array(mp_int mp[], int count);
+void mp_zero(mp_int *mp);
+void mp_set(mp_int *mp, mp_digit d);
+//_err mp_set_int(mp_int *mp, long z);
+mp_err mp_shrink(mp_int *a);
+
+
+/*------------------------------------------------------------------------*/
+/* Single digit arithmetic */
+
+mp_err mp_add_d(mp_int *a, mp_digit d, mp_int *b);
+mp_err mp_sub_d(mp_int *a, mp_digit d, mp_int *b);
+mp_err mp_mul_d(mp_int *a, mp_digit d, mp_int *b);
+mp_err mp_mul_2(mp_int *a, mp_int *c);
+mp_err mp_div_d(mp_int *a, mp_digit d, mp_int *q, mp_digit *r);
+mp_err mp_div_2(mp_int *a, mp_int *c);
+mp_err mp_expt_d(mp_int *a, mp_digit d, mp_int *c);
+
+/*------------------------------------------------------------------------*/
+/* Sign manipulations */
+
+mp_err mp_abs(mp_int *a, mp_int *b);
+mp_err mp_neg(mp_int *a, mp_int *b);
+
+/*------------------------------------------------------------------------*/
+/* Full arithmetic */
+
+mp_err mp_add(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_sub(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_mul(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_mul_2d(mp_int *a, mp_digit d, mp_int *c);
+#if MP_SQUARE
+mp_err mp_sqr(mp_int *a, mp_int *b);
+#else
+#define mp_sqr(a, b) mp_mul(a, a, b)
+#endif
+mp_err mp_div(mp_int *a, mp_int *b, mp_int *q, mp_int *r);
+mp_err mp_div_2d(mp_int *a, mp_digit d, mp_int *q, mp_int *r);
+mp_err mp_expt(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_2expt(mp_int *a, mp_digit k);
+mp_err mp_sqrt(mp_int *a, mp_int *b);
+
+/*------------------------------------------------------------------------*/
+/* Modular arithmetic */
+
+#if MP_MODARITH
+mp_err mp_mod(mp_int *a, mp_int *m, mp_int *c);
+mp_err mp_mod_d(mp_int *a, mp_digit d, mp_digit *c);
+mp_err mp_addmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c);
+mp_err mp_submod(mp_int *a, mp_int *b, mp_int *m, mp_int *c);
+mp_err mp_mulmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c);
+#if MP_SQUARE
+mp_err mp_sqrmod(mp_int *a, mp_int *m, mp_int *c);
+#else
+#define mp_sqrmod(a, m, c) mp_mulmod(a, a, m, c)
+#endif
+mp_err mp_exptmod(mp_int *a, mp_int *b, mp_int *m, mp_int *c);
+mp_err mp_exptmod_d(mp_int *a, mp_digit d, mp_int *m, mp_int *c);
+#endif /* MP_MODARITH */
+
+/*------------------------------------------------------------------------*/
+/* Comparisons */
+
+int mp_cmp_z(mp_int *a);
+int mp_cmp_d(mp_int *a, mp_digit d);
+int mp_cmp(mp_int *a, mp_int *b);
+int mp_cmp_mag(mp_int *a, mp_int *b);
+//int mp_cmp_int(mp_int *a, long z);
+int mp_isodd(mp_int *a);
+int mp_iseven(mp_int *a);
+
+/*------------------------------------------------------------------------*/
+/* Number theoretic */
+
+#if MP_NUMTH
+mp_err mp_gcd(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_lcm(mp_int *a, mp_int *b, mp_int *c);
+mp_err mp_xgcd(mp_int *a, mp_int *b, mp_int *g, mp_int *x, mp_int *y);
+mp_err mp_invmod(mp_int *a, mp_int *m, mp_int *c);
+#endif /* end MP_NUMTH */
+
+/*------------------------------------------------------------------------*/
+/* Input and output */
+
+#if MP_IOFUNC
+void mp_print(mp_int *mp, FILE *ofp);
+#endif /* end MP_IOFUNC */
+
+/*------------------------------------------------------------------------*/
+/* Base conversion */
+
+#define BITS 1
+#define BYTES CHAR_BIT
+
+mp_err mp_read_signed_bin(mp_int *mp, unsigned char *str, int len);
+int mp_signed_bin_size(mp_int *mp);
+mp_err mp_to_signed_bin(mp_int *mp, unsigned char *str);
+
+mp_err mp_read_unsigned_bin(mp_int *mp, unsigned char *str, int len);
+int mp_unsigned_bin_size(mp_int *mp);
+mp_err mp_to_unsigned_bin(mp_int *mp, unsigned char *str);
+
+int mp_count_bits(mp_int *mp);
+
+#if MP_COMPAT_MACROS
+#define mp_read_raw(mp, str, len) mp_read_signed_bin((mp), (str), (len))
+#define mp_raw_size(mp) mp_signed_bin_size(mp)
+#define mp_toraw(mp, str) mp_to_signed_bin((mp), (str))
+#define mp_read_mag(mp, str, len) mp_read_unsigned_bin((mp), (str), (len))
+#define mp_mag_size(mp) mp_unsigned_bin_size(mp)
+#define mp_tomag(mp, str) mp_to_unsigned_bin((mp), (str))
+#endif
+
+mp_err mp_read_radix(mp_int *mp, unsigned char *str, int radix);
+int mp_radix_size(mp_int *mp, int radix);
+int mp_value_radix_size(int num, int qty, int radix);
+mp_err mp_toradix(mp_int *mp, unsigned char *str, int radix);
+
+int mp_char2value(char ch, int r);
+
+#define mp_tobinary(M, S) mp_toradix((M), (S), 2)
+#define mp_tooctal(M, S) mp_toradix((M), (S), 8)
+#define mp_todecimal(M, S) mp_toradix((M), (S), 10)
+#define mp_tohex(M, S) mp_toradix((M), (S), 16)
+
+/*------------------------------------------------------------------------*/
+/* Error strings */
+
+const char *mp_strerror(mp_err ec);
+
+#endif /* end _H_MPI_ */
+
+/* $Source$ */
+/* $Revision: 0.36 $ */
+/* $Date: 2005-08-01 16:37:28 +0000 $ */
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/rules.mk b/src/bsp/lk/platform/mt2731/drivers/md/rules.mk
new file mode 100644
index 0000000..22f9457
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/rules.mk
@@ -0,0 +1,34 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/ccci_ld_md_api_wrapper.c \
+ $(LOCAL_DIR)/ccci_ld_md_ass.c \
+ $(LOCAL_DIR)/ccci_ld_md_core.c \
+ $(LOCAL_DIR)/ccci_ld_md_padding.c \
+ $(LOCAL_DIR)/ccci_ld_md_tel.c \
+ $(LOCAL_DIR)/ccci_ld_md_tag_dt.c \
+ $(LOCAL_DIR)/ccci_ld_md_hal.c \
+ $(LOCAL_DIR)/img_utils.c \
+ $(LOCAL_DIR)/cutils.c \
+ $(LOCAL_DIR)/ccci_fit.c \
+
+MODULE_DEPS += \
+ lib/sha256 \
+ lib/rsa \
+ lib/fit \
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/ccci_lk_load_img_plat.c
+
+# single bin modem
+ifeq ($(strip $(SINGLE_BIN_MODEM_SUPPORT)),yes)
+GLOBAL_DEFINES += SINGLE_BIN_MODEM
+endif
+
+DUMMY_AP := 0
+ifeq ($(strip $(DUMMY_AP)),1)
+GLOBAL_DEFINES += DUMMY_AP_MODE
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/dummy_ap.c
+endif
\ No newline at end of file
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.c b/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.c
new file mode 100644
index 0000000..076790b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.c
@@ -0,0 +1,498 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+
+#include "sec_boot.h"
+#include "ccci_ld_md_core.h"
+#include "cert.h"
+#include "m1.h"
+#include "cutils.h"
+#include <string.h>
+#include "img_hdr.h"
+#include "sec_part_name.h"
+#include "sec_dbg.h"
+#include "sec_img_info.h"
+#include "ccci_ld_md_core.h"
+#include "sha256.h"
+#include "rsa.h"
+
+/******************************************************************************
+ * Feature Mask
+
+******************************************************************************/
+#define MOD "SBC"
+#define DEV_TYPE_COMBO_EMMC_ENABLED 3
+
+//extern MTK_ROMInfo_ST g_rom_info;
+bool g_combo_emmc_enabled;
+//extern BOOL is_recovery_mode(void);
+
+#define OEM_KEY_SZ 256
+
+#define VERIFIED_BOOT_SIG_BUF_SZ (0x800)
+
+#define ASN_ID_SEQUENCE 0x30
+#define VERIFIED_BOOT_SIG_ALIGN_SZ 16
+
+extern uint32_t sec_set_md_pubk_hash(uint32_t img_type);
+extern uint32_t sec_clear_pubk(void);
+extern void seclib_image_buf_init(void);
+extern uint8_t *seclib_image_allocate_mem(uint32_t buf_len);
+extern void seclib_image_buf_reset(void);
+extern void seclib_image_buf_free(void);
+
+/*read from storage: data_src is partition name
+ read from ram: data_src is data address*/
+
+/* Global Secure Information */
+struct key_prop g_sec_oemkey;
+uint8_t g_verified_boot_sig_exist = 0;
+uint8_t g_verified_boot_sig[VERIFIED_BOOT_SIG_BUF_SZ] = {0};
+uint32_t g_verified_boot_sig_sz = 0;
+uint8_t g_boot_img_hdr[MAX_HDR_SZ] = {0};
+uint32_t g_boot_img_hdr_sz = 0;
+
+IMG_INFO g_img_info;
+IMG_INFO g_cert_img_info;
+CERT1_INFO g_cert1_info;
+CERT2_INFO g_cert2_info;
+VERIFIED_BOOT_SIG_INFO g_verified_boot_sig_info;
+uint32_t g_auth_count = 0;
+
+static uint32_t name_compare(char *name1, char *name2)
+{
+ uint32_t name1_sz = strlen(name1);
+ uint32_t name2_sz = strlen(name2);
+
+ if (name1_sz != name2_sz)
+ return 1;
+
+ return memcmp(name1, name2, sizeof(char) * name1_sz);
+}
+
+/* byte reverse for buffer */
+void rev_buf(uint8_t *puint8_t_buf, uint32_t uint32_t_sz)
+{
+ uint32_t i, uint32_t_halfsz;
+ uint8_t uint8_t_tmp;
+ if ((NULL == puint8_t_buf) || (uint32_t_sz <= 1))
+ return;
+
+ uint32_t_halfsz = uint32_t_sz >> 1;
+ for (i = 0; i < uint32_t_halfsz; i++) {
+ uint8_t_tmp = puint8_t_buf[i];
+ puint8_t_buf[i] = puint8_t_buf[uint32_t_sz - 1 - i];
+ puint8_t_buf[uint32_t_sz - 1 - i] = uint8_t_tmp;
+ }
+}
+
+/******************************************************************************
+ * IMAGE VERIFICATION
+ ******************************************************************************/
+int sec_boot_check(int try_lock)
+{
+ int ret = 0;
+
+ /* this function is dummy since image authentication is done with image loading to accelerate boot time */
+
+ return ret;
+}
+
+uint32_t cert1_img_info_sanity(IMG_INFO *img_info)
+{
+ uint32_t ret = 0;
+
+ /* basic test of image header */
+ if (img_info->img_hdr_type != IMG_HDR_TYPE_RAW) {
+ dprintf(CRITICAL, "[%s] cert img_hdr_type = 0x%x\n", MOD, img_info->img_hdr_type);
+ ret = 1;
+ goto end;
+ }
+
+ if (img_info->img_type != IMG_TYPE_CERT1 &&
+ img_info->img_type != IMG_TYPE_CERT1_MD) {
+ ret = 1;
+ goto end;
+ }
+
+ if (SEC_IMG_BUFFER_LENGTH < img_info->img_sz + img_info->img_hdr_sz) {
+ ret = 1;
+ goto end;
+ }
+
+end:
+ return ret;
+}
+
+uint32_t cert2_img_info_sanity(IMG_INFO *img_info)
+{
+ uint32_t ret = 0;
+
+ /* basic test of image header */
+ if (img_info->img_hdr_type != IMG_HDR_TYPE_RAW) {
+ dprintf(CRITICAL, "[%s] cert img_hdr_type = 0x%x\n", MOD, img_info->img_hdr_type);
+ ret = 1;
+ goto end;
+ }
+
+ if (img_info->img_type != IMG_TYPE_CERT2) {
+ ret = 1;
+ goto end;
+ }
+
+ if (SEC_IMG_BUFFER_LENGTH < img_info->img_sz + img_info->img_hdr_sz) {
+ ret = 1;
+ goto end;
+ }
+
+end:
+ return ret;
+}
+
+uint32_t seclib_calc_hash(uint8_t *buf, uint32_t buf_sz,
+ uint32_t padding_sz, uint8_t *hash, uint32_t hash_sz)
+{
+ uint32_t ret = 0; int i;
+ struct sha256_context s_ctx = {0};
+
+ if (hash_sz != SHA256_HASH_SZ)
+ return -1;
+
+ memset((void *)hash, 0, hash_sz);
+ ret = sha256_start(&s_ctx);
+ if (ret)
+ return ret;
+
+ if (0 == padding_sz) {
+ ret = sha256_process(&s_ctx, buf, buf_sz);
+ if (ret)
+ return ret;
+ } else {
+ /* special processing for padding */
+ uint32_t in_len = 0;
+ uint8_t last_data[16] = {0};
+ in_len = (buf_sz / 16) * 16;
+ ret = sha256_process(&s_ctx, buf, in_len);
+ if (ret)
+ return ret;
+ sec_memcpy(last_data, buf + in_len, buf_sz - in_len);
+ ret = sha256_process(&s_ctx, last_data, 16);
+ if (ret)
+ return ret;
+ }
+
+ ret = sha256_end(&s_ctx, hash);
+ if (ret)
+ return ret;
+
+ dprintf(CRITICAL, "[%s] dump hash...\n", MOD);
+
+ return ret;
+}
+
+
+uint32_t sec_read_ram_data(char *src, uint8_t *dest, uint64_t offset, uint32_t size)
+{
+ if (src == NULL)
+ return 1;
+
+ memcpy(dest, src + offset, size);
+
+ return 0;
+}
+
+static void sec_cert_info_init()
+{
+ memset(&g_img_info, 0x0, sizeof(g_img_info));
+ memset(&g_cert_img_info, 0x0, sizeof(g_cert_img_info));
+ memset(&g_boot_img_hdr, 0x0, MAX_HDR_SZ);
+ g_boot_img_hdr_sz = 0;
+ g_verified_boot_sig_exist = 0;
+ g_verified_boot_sig_sz = 0;
+ g_auth_count += 1;
+
+ memset(&g_cert1_info, 0x0, sizeof(g_cert1_info));
+ g_cert1_info.img_pubk.n_size = sizeof(g_cert1_info.img_pubk.n);
+ g_cert1_info.img_pubk.e_size = sizeof(g_cert1_info.img_pubk.e);
+ g_cert1_info.img_pubk_hash_sz = sizeof(g_cert1_info.img_pubk_hash);
+ g_cert1_info.sw_id_sz = sizeof(g_cert1_info.sw_id);
+
+ memset(&g_cert2_info, 0x0, sizeof(g_cert2_info));
+ g_cert2_info.img_hash_sz = sizeof(g_cert2_info.img_hash);
+ g_cert2_info.img_hdr_hash_sz = sizeof(g_cert2_info.img_hdr_hash);
+ g_cert2_info.img_ver_sz = sizeof(g_cert2_info.img_ver);
+ g_cert2_info.apply_sig_sz = sizeof(g_cert2_info.apply_sig);
+}
+
+static uint32_t sec_buf_init(uint8_t **buf)
+{
+ uint32_t ret = 0;
+ seclib_image_buf_init();
+ seclib_image_buf_reset();
+ *buf = seclib_image_allocate_mem(SEC_IMG_BUFFER_LENGTH); /* allocate max size */
+ if (NULL == *buf)
+ ret = 1;
+ return ret;
+}
+
+static void sec_buf_free()
+{
+ seclib_image_buf_free();
+}
+
+static uint32_t sec_img_parse(char *part_name, char *img_name, uint8_t *buf, uint64_t *part_offset,
+ uint32_t *found)
+{
+ uint32_t ret = 0;
+ int load_size = 0;
+ char image_name[IMG_NAME_SIZE] = {0};
+
+ if (part_name == NULL || img_name == NULL || buf == NULL ||
+ part_offset == NULL || found == NULL) {
+ ret = 1;
+ goto end;
+ }
+
+ while (0 == *found) {
+ /* get image info */
+ load_size = ccci_load_raw_data(part_name, buf, *part_offset, MAX_HDR_SZ);
+ if ((unsigned int)load_size != MAX_HDR_SZ)
+ if (ret)
+ goto end;
+ ret = seclib_get_img_info(buf, MAX_HDR_SZ, &g_img_info);
+ if (ret)
+ goto end;
+
+ /* this covers the case which no more images are found */
+ if (g_img_info.img_list_end)
+ break;
+
+ if ((g_img_info.img_hdr_type != IMG_HDR_TYPE_RAW) &&
+ (g_img_info.img_hdr_type != IMG_HDR_TYPE_BOOT) &&
+ (g_img_info.img_hdr_type != IMG_HDR_TYPE_DTBO))
+ continue;
+
+ /* copy boot image header if it's boot image for yellow state verification */
+ if (g_img_info.img_hdr_type == IMG_HDR_TYPE_BOOT) {
+ g_boot_img_hdr_sz = g_img_info.img_hdr_sz;
+ memcpy(g_boot_img_hdr, buf, g_boot_img_hdr_sz);
+ }
+
+ /*Check image name in the header and the image name from caller*/
+ if (g_img_info.img_hdr_type == IMG_HDR_TYPE_RAW) {
+ /* Image name conversion*/
+ int i = 0;
+ while ((0x0 != (*(img_name + i))) & (i < IMG_NAME_SIZE)) {
+ image_name[i] = (*(img_name + i));
+ i++;
+ }
+ if ((0x0 != (*(img_name + i))))
+ dprintf(CRITICAL, "Image name length is too long \n");
+ if (!name_compare(g_img_info.img_name, image_name)) {
+ dprintf(CRITICAL, "Image name matched \n");
+ *found = 1;
+ }
+ } else
+ *found = 1;
+
+ *part_offset += g_img_info.img_hdr_sz;
+ *part_offset += g_img_info.img_sz;
+ }
+
+end:
+ return ret;
+}
+
+/* Verify cert chain */
+uint32_t sec_img_auth_init(char *part_name, char *img_name, uint32_t oem_opt)
+{
+ uint32_t ret = 0;
+ uint32_t found = 0;
+ uint8_t *buf = NULL;
+ uint64_t part_offset = 0;
+ uint32_t img_type_group = IMG_TYPE_GROUP_AP;
+ int32_t load_size = 0;
+
+ /* hash */
+ uint8_t img_hdr_hash[SHA256_HASH_SZ];
+ uint32_t img_hdr_hash_size = SHA256_HASH_SZ;
+
+ dprintf(CRITICAL, "start sec_img_auth_init\n");
+
+ sec_cert_info_init();
+ ret = sec_buf_init(&buf);
+ if (ret)
+ goto fail;
+ ret = sec_img_parse(part_name, img_name, buf, &part_offset, &found);
+ if (ret) {
+ dprintf(CRITICAL, "sec_img_parse failed\n");
+ goto fail;
+ }
+ else if (found == 0) {
+ ret = 1;
+ goto fail;
+ }
+
+ if (found) {
+ /* calculate image header hash */
+ ret = seclib_calc_hash(buf, g_img_info.img_hdr_sz, 0, img_hdr_hash,
+ img_hdr_hash_size);
+ if (ret)
+ goto fail;
+
+ /* cert1 sanity */
+ load_size = ccci_load_raw_data(part_name, buf, part_offset, IMG_HDR_SZ);
+ if ((unsigned int)load_size != IMG_HDR_SZ)
+ goto fail;
+
+ ret = seclib_get_img_info(buf, IMG_HDR_SZ, &g_cert_img_info);
+ if (ret)
+ goto fail;
+
+ ret = cert1_img_info_sanity(&g_cert_img_info);
+ if (ret)
+ goto fail;
+
+ /* load and verify cert1 */
+ if (g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz > SEC_IMG_BUFFER_LENGTH) {
+ ret = 1;
+ goto fail;
+ }
+
+ load_size = ccci_load_raw_data(part_name, buf, part_offset,
+ g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz);
+ if ((unsigned int)load_size !=
+ g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz)
+ goto fail;
+ getkeyfromblob();
+ ret = cert1_verify(buf, g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz,
+ &g_cert1_info);
+ if (ret)
+ goto fail;
+ /* write and lock pubk hash for md public key authentication */
+ /* Write register anyway */
+ img_type_group = seclib_get_img_group_type(g_img_info.img_type);
+ if (img_type_group == IMG_TYPE_GROUP_MD) {
+ ret = sec_set_md_pubk_hash(g_img_info.img_type);
+ if (ret) {
+ dprintf(CRITICAL, "fail to set MD pubk hash\n");
+ ret = 0;
+ }
+ }
+ /* get cert2 partition offset */
+ part_offset += g_cert_img_info.img_hdr_sz;
+ part_offset += g_cert_img_info.img_sz;
+
+ /* cert2 sanity */
+ load_size = ccci_load_raw_data(part_name, buf, part_offset, IMG_HDR_SZ);
+ if ((unsigned int)load_size != IMG_HDR_SZ)
+ goto fail;
+ ret = seclib_get_img_info(buf, IMG_HDR_SZ, &g_cert_img_info);
+ if (ret)
+ goto fail;
+ ret = cert2_img_info_sanity(&g_cert_img_info);
+ if (ret)
+ goto fail;
+
+ /* load and verify cert2 */
+ load_size = ccci_load_raw_data(part_name, buf, part_offset,
+ g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz);
+ if ((unsigned int)load_size !=
+ g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz)
+ goto fail;
+ ret = cert2_verify(buf, g_cert_img_info.img_hdr_sz + g_cert_img_info.img_sz,
+ &g_cert1_info, &g_cert2_info, oem_opt);
+ if (ret)
+ goto fail;
+
+ /* compare image header hash and authenticated image header hash in cert2 */
+ /* image hash can only be verified later after image is loaded */
+ if (sec_memcmp(g_cert2_info.img_hdr_hash, img_hdr_hash, SHA256_HASH_SZ)) {
+ ret = 1;
+ goto fail;
+ }
+
+ }
+
+pass:
+ dprintf(CRITICAL, "[%s] image %s auth init pass\n", MOD, img_name);
+ sec_buf_free();
+ return ret;
+fail:
+ dprintf(CRITICAL, "[%s] image %s auth init fail (0x%x)\n", MOD, img_name, ret);
+ sec_buf_free();
+ sec_clear_pubk();
+
+ if (g_verified_boot_sig_exist == 1)
+ ret = 1;
+
+ return ret;
+}
+
+uint32_t sec_img_auth(uint8_t *buf, uint32_t buf_sz)
+{
+ uint32_t ret = 0;
+ /* hash */
+ uint8_t img_hash[SHA256_HASH_SZ] = {0};
+ uint32_t img_hash_size = SHA256_HASH_SZ;
+ uint32_t padding_sz = 0;
+
+ dprintf(CRITICAL, "start sec_img_auth_init\n");
+
+ padding_sz = g_img_info.img_sz - buf_sz;
+
+#if IMAGE_HASH_ACCELERATE == 1
+ ret = calc_hash_hw(buf, buf_sz, padding_sz, img_hash, img_hash_size);
+ if (ret)
+ goto fail;
+#else
+ ret = seclib_calc_hash(buf, buf_sz, padding_sz, img_hash, img_hash_size);
+ if (ret)
+ goto fail;
+#endif
+
+ if (sec_memcmp(g_cert2_info.img_hash, img_hash, img_hash_size)) {
+ ret = 1;
+ goto fail;
+ }
+
+ dprintf(CRITICAL, "[%s][oem] img auth pass\n", MOD);
+ return ret;
+fail:
+ dprintf(CRITICAL, "[%s][oem] img auth fail (0x%x)\n", MOD, ret);
+ sec_clear_pubk();
+ return ret;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.h b/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.h
new file mode 100644
index 0000000..c5c971a
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_boot.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_BOOT_H
+#define SEC_BOOT_H
+
+#include <assert.h>
+
+/**************************************************************************
+ * [SEC-BOOT]
+ **************************************************************************/
+/* SEC-BOOT Attribute */
+#define ATTR_SBOOT_DISABLE 0x00
+#define ATTR_SBOOT_ENABLE 0x11
+#define ATTR_SBOOT_ONLY_ENABLE_ON_SCHIP 0x22
+
+#define SEC_IMG_BUFFER_LENGTH (0x100000)
+
+//int sec_func_init(uint64_t pl_start_addr);
+void rev_buf(uint8_t *puint8_t_buf, uint32_t uint32_t_sz);
+uint32_t sec_img_auth_init(char *part_name, char *img_name, uint32_t oem_opt);
+uint32_t sec_img_auth(uint8_t *buf, uint32_t buf_sz);
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_dbg.h b/src/bsp/lk/platform/mt2731/drivers/md/sec_dbg.h
new file mode 100644
index 0000000..19f11d2
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_dbg.h
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_DEBUG_H
+#define SEC_DEBUG_H
+
+#include <stdio.h>
+
+/* Define LOG LEVEL*/
+#define SEC_LOG_TRACE 0 //For source code trace
+#define SEC_LOG_DEBUG 0 //For debug purpose
+#define SEC_LOG_ERROR 1 //For critical error dump
+#define SEC_LOG_INFO 1 //For information to know when processing in normal case
+#define SEC_LOG_SCREEN 1 //For information that need to print to screen
+
+/* DEBUG MACRO */
+#define SMSG_TRACE(...) \
+ do { if (SEC_LOG_TRACE) printf(__VA_ARGS__); } while (0)
+
+#define SMSG_DEBUG(...) \
+ do { if (SEC_LOG_DEBUG) printf(__VA_ARGS__); } while (0)
+
+#define SMSG_ERROR(...) \
+ do { if (SEC_LOG_ERROR) printf(__VA_ARGS__); } while (0)
+
+#define SMSG_INFO(...) \
+ do { if (SEC_LOG_INFO) printf(__VA_ARGS__); } while (0)
+
+#define SMSG_SCREEN(...) \
+ do { if (SEC_LOG_SCREEN) video_printf(__VA_ARGS__); } while (0)
+
+/* Define LOG MODULE */
+#define MOD_POLICY "SEC_POLICY"
+#define MOD_HACC "SEC_HACC"
+#define MOD_AUTH "SEC_AUTH"
+#define MOD_INIT "SEC_INIT"
+#define MOD_CFG "SEC_CFG"
+#define MOD_MAIN "SEC_MAIN"
+#define MOD_EXT "SEC_EXT_REGION"
+#define MOD_PARSER "SEC_PARSER"
+#define MOD_ROM "SEC_ROMINFO"
+#define MOD_USBDL "SEC_USBDL"
+#define MOD_SRO "SEC_SRO"
+#define MOD_PART "SEC_PART"
+#define MOD_UNLOCK "SEC_UNLOCK"
+//Please add one here if you create a new file for your module
+
+/* Export Function */
+//unsigned int sec_error();
+//unsigned int sec_log_error(unsigned int err);
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.c b/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.c
new file mode 100644
index 0000000..95d6748
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.c
@@ -0,0 +1,75 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include <reg.h>
+#include "sec_fuse.h"
+
+/******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************/
+int efuse_sbc_enabled(void)
+{
+#if 0
+ //not use now
+ return (REG32(EFUSE_SEC_CTRL)&EFUSE_SBC_EN) ? 1 : 0;
+#endif
+ return 0;
+}
+
+unsigned int efuse_get_pubk_hash(unsigned char *hash, unsigned int hash_sz)
+{
+ unsigned int ret = 0;
+#if 0
+ //not use now
+ unsigned int i;
+
+ if (hash_sz != 32) {
+ ret = -1;
+ return ret;
+ }
+
+ for (i = 0; i < 8; i++) {
+ unsigned int reg;
+ reg = REG32(EFUSE_SBC_PUBK_HASH + 4 * i);
+ /* change endian */
+ *(hash + (i * 4) + 0) = (u8)((reg & 0x000000ff) >> 0);
+ *(hash + (i * 4) + 1) = (u8)((reg & 0x0000ff00) >> 8);
+ *(hash + (i * 4) + 2) = (u8)((reg & 0x00ff0000) >> 16);
+ *(hash + (i * 4) + 3) = (u8)((reg & 0xff000000) >> 24);
+ }
+#endif
+ return ret;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.h b/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.h
new file mode 100644
index 0000000..9d88d76
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_fuse.h
@@ -0,0 +1,46 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef EFUSE_H
+#define EFUSE_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int efuse_sbc_enabled(void);
+unsigned int efuse_get_pubk_hash(unsigned char *hash, unsigned int hash_sz);
+
+#endif /* EFUSE_H */
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.c b/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.c
new file mode 100644
index 0000000..26b6d2f
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.c
@@ -0,0 +1,88 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include <printf.h>
+#include <string.h>
+#include "sec_dbg.h"
+#include "img_hdr.h"
+#include "img_util.h"
+
+#define MOD "IMG_INFO"
+
+unsigned int seclib_get_img_group_type(unsigned int img_type)
+{
+ return img_type & IMG_TYPE_GROUP_MASK;
+}
+
+unsigned int seclib_get_img_info(unsigned char *buf, unsigned int buf_sz,
+ IMG_INFO *img_info)
+{
+ unsigned int ret = 0;
+#if 1
+
+ IMG_HDR_T *img_hdr = (IMG_HDR_T *)buf;
+ unsigned int align_size = 0;
+ unsigned page_sz = 0;
+
+ if (buf == NULL || img_info == NULL)
+ return 1;
+
+ if ((IMG_MAGIC == img_hdr->info.magic) &&
+ (IMG_EXT_MAGIC == img_hdr->info.ext_magic)) {
+ img_info->img_hdr_type = IMG_HDR_TYPE_RAW;
+ img_info->img_hdr_sz = img_hdr->info.hdr_size;
+ align_size = img_hdr->info.align_size;
+ /* dsize does not include image header and padding currently */
+ img_info->img_sz = ((img_hdr->info.dsize + align_size - 1) / align_size) *
+ align_size;
+ img_info->img_type = img_hdr->info.img_type;
+ img_info->img_list_end = img_hdr->info.img_list_end;
+ memcpy(img_info->img_name, img_hdr->info.name, IMG_NAME_SIZE);
+ } else {
+ img_info->img_hdr_type = IMG_HDR_TYPE_UNKNOWN;
+ img_info->img_sz = 0;
+ img_info->img_type = IMG_TYPE_IMG_AP_BIN;
+ img_info->img_list_end = 1;
+ memcpy(img_info->img_name, "NULL", 4);
+ }
+
+ SMSG_DEBUG("[%s] image_hdr_type = 0x%x\n", MOD, img_info->img_hdr_type);
+ SMSG_DEBUG("[%s] image_hdr_size = 0x%x\n", MOD, img_info->img_hdr_sz);
+ SMSG_DEBUG("[%s] image_type = 0x%x\n", MOD, img_info->img_type);
+ SMSG_DEBUG("[%s] image_size = 0x%x\n", MOD, img_info->img_sz);
+ SMSG_DEBUG("[%s] image_list_end = 0x%x\n", MOD, img_info->img_list_end);
+#endif
+ return ret;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.h b/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.h
new file mode 100644
index 0000000..b3f95d1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_img_info.h
@@ -0,0 +1,45 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2018. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_IMG_INFO_H
+#define SEC_IMG_INFO_H
+
+#include "img_hdr.h"
+
+uint32_t seclib_get_img_info(uint8_t *buf, uint32_t buf_sz, IMG_INFO *img_info);
+uint32_t seclib_get_img_group_type(uint32_t img_type);
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_md.c b/src/bsp/lk/platform/mt2731/drivers/md/sec_md.c
new file mode 100644
index 0000000..1d789b3
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_md.c
@@ -0,0 +1,195 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include <ctype.h>
+#include "sec_part_name.h"
+#include "sec_dbg.h"
+#include "sec_boot.h"
+#include "cert.h"
+#include "img_hdr.h"
+#include "sec_img_info.h"
+#include <reg.h>
+
+extern CERT1_INFO g_cert1_info;
+
+u8 g_md_lte_sbc_en = 0x0;
+u8 g_md_c2k_sbc_en = 0x0;
+
+#define LTE_OP_ZERO_2_TWO 0x00000
+#define LTE_OP_THREE_2_FIVE 0x00001
+#define LTE_OP_SIX_SEVEN 0x00002
+
+#define C2K_OP_ZERO_2_TWO 0x10000
+#define C2K_OP_THREE_2_FIVE 0x10001
+#define C2K_OP_SIX_SEVEN 0x10002
+
+#define MD_SBC_KEY_HASH0 (0xFFFFFFF0201D7000)
+#define MD_SBC_KEY_HASH1 (0xFFFFFFF0201D7004)
+#define MD_SBC_KEY_HASH2 (0xFFFFFFF0201D7008)
+#define MD_SBC_KEY_HASH3 (0xFFFFFFF0201D700C)
+#define MD_SBC_KEY_HASH4 (0xFFFFFFF0201D7010)
+#define MD_SBC_KEY_HASH5 (0xFFFFFFF0201D7014)
+#define MD_SBC_KEY_HASH6 (0xFFFFFFF0201D7018)
+#define MD_SBC_KEY_HASH7 (0xFFFFFFF0201D701C)
+#define MD_SBC_KEY_LOCK (0xFFFFFFF0201D7020)
+#define MD_SBC_KEY_LOCK_VAL (0x0000659E)
+
+#define LTE_SBC_EN (1U << 1) /* SEC_MSC */
+#define EFUSE_BASE_ADDR (0x11C10000)
+#define EFUSE_SEC_MSC (EFUSE_BASE_ADDR+0x04A0+0xFFFFFFF000000000)
+
+uint32_t sec_pubk_hash_convert(uint8_t *buf)
+{
+ return (*buf << 24) + (*(buf + 1) << 16) + (*(buf + 2) << 8) + *(buf + 3);
+}
+
+/* write the global public key hash into md register*/
+/* pre-condition: pubk hash is from cert. cert must be verified first.*/
+static int32_t md_reg_write_and_check(uint64_t addr, uint32_t value)
+{
+ *REG32(addr) = (value);
+ if (*REG32(addr) != value)
+ return -1;
+ return 0;
+}
+
+uint32_t sec_write_ltemd_reg()
+{
+ int i = 0;
+ uint32_t ret = 0;
+ uint32_t test_val = 0x11223344;
+
+ /*Default data interface*/
+ uint32_t pubk_hash[8] = {0};
+ //Real interpreter interface
+ for (i = 0; i < 8; i++)
+ pubk_hash[i] = sec_pubk_hash_convert(g_cert1_info.img_pubk_hash + i * 4);
+ /* write LTE modem public key hash through ATF SMC */
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH0, pubk_hash[0]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH1, pubk_hash[1]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH2, pubk_hash[2]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH3, pubk_hash[3]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH4, pubk_hash[4]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH5, pubk_hash[5]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH6, pubk_hash[6]);
+ if (ret)
+ goto exit;
+ ret = md_reg_write_and_check(MD_SBC_KEY_HASH7, pubk_hash[7]);
+ if (ret)
+ goto exit;
+
+ /******* lock *******/
+ *REG32(MD_SBC_KEY_LOCK) = MD_SBC_KEY_LOCK_VAL;
+ if (*REG32(MD_SBC_KEY_LOCK) != 0x1) {
+ SMSG_INFO("md_key_hash lock failed! \n");
+ ret = -1;
+ goto exit;
+ }
+ *REG32(MD_SBC_KEY_HASH0) = test_val;
+ if (*REG32(MD_SBC_KEY_HASH0) != pubk_hash[0]) {
+ SMSG_INFO("md_key_hash lock failed! \n");
+ ret = -1;
+ goto exit;
+ }
+
+ SMSG_INFO("set LTE pubk hash done\n");
+ return ret;
+exit:
+ SMSG_INFO("[Sec] set LTE pubk hash failed!\n");
+ return ret;
+}
+
+
+uint32_t sec_md_sbcen_init()
+{
+ uint32_t ret = 0;
+ /* Default value */
+ g_md_lte_sbc_en = 0;
+ /* read and set MD LTE */
+ if (LTE_SBC_EN == (*REG32(EFUSE_SEC_MSC) & LTE_SBC_EN))
+ g_md_lte_sbc_en = 0x01;
+ return ret;
+}
+
+uint32_t sec_get_c2kmd_sbcen()
+{
+ uint32_t ret = 0;
+ if (0x01 == g_md_c2k_sbc_en)
+ ret = 1;
+ return ret;
+}
+
+uint32_t sec_get_ltemd_sbcen()
+{
+ uint32_t ret = 0;
+ if (0x01 == g_md_lte_sbc_en)
+ ret = 1;
+ return ret;
+}
+
+uint32_t sec_set_md_pubk_hash(unsigned int img_type)
+{
+ uint32_t ret = 0;
+
+ if (!(*REG32(EFUSE_SEC_MSC) & LTE_SBC_EN)) {
+ SMSG_INFO("[SEC] No need to fill MD1 pubk hash.\n");
+ return 0;
+ }
+
+ if (seclib_get_img_group_type(img_type) != IMG_TYPE_GROUP_MD)
+ return 1;
+
+ if (IMG_TYPE_IMG_MD_LTE == img_type) {
+ ret = sec_write_ltemd_reg();
+ if (ret)
+ goto error;
+ }
+
+error:
+ return ret;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/md/sec_part_name.h b/src/bsp/lk/platform/mt2731/drivers/md/sec_part_name.h
new file mode 100644
index 0000000..9b8ee05
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/md/sec_part_name.h
@@ -0,0 +1,72 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_PART_NAME_H
+#define SEC_PART_NAME_H
+
+#define PART_PRELOADER "PRELOADER"
+#define PART_DSP_BL "DSP_BL"
+#define PART_MBR "MBR"
+#define PART_EBR1 "EBR1"
+#define PART_PMT "PMT"
+#define PART_PRO_INFO "PRO_INFO"
+#define PART_NVRAM "NVRAM"
+#define PART_PROTECT_F "PROTECT_F"
+#define PART_PROTECT_S "PROTECT_S"
+#define PART_SECCFG "SECCFG"
+#define PART_UBOOT "UBOOT"
+#define PART_BOOTIMG "BOOTIMG"
+#define PART_RECOVERY "RECOVERY"
+#define PART_SEC_RO "SEC_RO"
+#define PART_MISC "MISC"
+#define PART_LOGO "LOGO"
+#define PART_EBR2 "EBR2"
+#define PART_EXPDB "EXPDB"
+#define PART_ANDROID "ANDROID"
+#define PART_CACHE "CACHE"
+#define PART_USRDATA "USRDATA"
+#define PART_FAT "FAT"
+#define PART_BMTPOOL "BMTPOOL"
+/*preloader re-name*/
+#define PART_SECURE "SECURE"
+#define PART_SECSTATIC "SECSTATIC"
+#define PART_ANDSYSIMG "ANDSYSIMG"
+#define PART_USER "USER"
+/*Uboot re-name*/
+#define PART_DSP_DL "DSP_DL"
+#define PART_APANIC "APANIC"
+
+#endif /* SEC_PART_NAME_H */
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_core.c b/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_core.c
new file mode 100644
index 0000000..e79303d
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_core.c
@@ -0,0 +1,1938 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES */
+/*=======================================================================*/
+#include <config.h>
+#include <platform/msdc.h>
+#include <platform/mmc_core.h>
+#include <platform/mmc_rpmb.h>
+#include <platform/mmc_ioctl.h>
+#include <platform/mtk_bio_ioctl.h>
+#include <lib/bio.h>
+#include <lib/heap.h>
+#include <lib/partition.h>
+#include <pow2.h>
+#include <stdlib.h>
+#include <string.h>
+#include <err.h>
+#include <errno.h>
+#include <kernel/mutex.h>
+
+#define CMD_RETRIES (5)
+#define CMD_TIMEOUT (100) /* 100ms */
+#define PAD_DELAY_MAX 32
+
+static int mmc_set_ext_csd(struct mmc_card *card, u8 addr, u8 value);
+/* before DRAM k, malloc() is not ready, so define it globally */
+struct mmc_host msdc_host0;
+struct mmc_card emmc_card;
+
+typedef struct {
+ bdev_t bdev;
+ u32 part_id;
+ struct mmc_host *host;
+ struct mmc_card *card;
+} mmc_dev_t;
+
+struct msdc_delay_phase {
+ u8 maxlen;
+ u8 start;
+ u8 final_phase;
+};
+
+static const unsigned int tran_exp[] = {
+ 10000, 100000, 1000000, 10000000,
+ 0, 0, 0, 0
+};
+
+static const unsigned char tran_mant[] = {
+ 0, 10, 12, 13, 15, 20, 25, 30,
+ 35, 40, 45, 50, 55, 60, 70, 80,
+};
+
+static const unsigned char mmc_tran_mant[] = {
+ 0, 10, 12, 13, 15, 20, 26, 30,
+ 35, 40, 45, 52, 55, 60, 70, 80,
+};
+
+static u32 unstuff_bits(u32 *resp, u32 start, u32 size)
+{
+ const u32 __mask = (1 << (size)) - 1;
+ const int __off = 3 - ((start) / 32);
+ const int __shft = (start) & 31;
+ u32 __res;
+
+ __res = resp[__off] >> __shft;
+ if ((size) + __shft >= 32)
+ __res |= resp[__off-1] << (32 - __shft);
+ return __res & __mask;
+}
+
+#define UNSTUFF_BITS(r,s,sz) unstuff_bits(r,s,sz)
+
+static int mmc_switch_part(mmc_dev_t *dev)
+{
+ int err = MMC_ERR_NONE;
+ struct mmc_card *card;
+ struct mmc_host *host;
+ u8 cfg;
+
+ host = dev->host;
+ if (host->curr_part == dev->part_id)
+ /* already set to specific partition */
+ return MMC_ERR_NONE;
+
+ if (dev->part_id > EXT_CSD_PART_CFG_GP_PART_4) {
+ dprintf(CRITICAL, "[MSDC] Unsupported partid: %u\n", dev->part_id);
+ return MMC_ERR_INVALID;
+ }
+
+ card = dev->card;
+ ASSERT(card);
+
+ cfg = card->ext_csd.part_cfg;
+ cfg = (cfg & ~0x7) | dev->part_id;
+ err = mmc_set_ext_csd(card, EXT_CSD_PART_CFG, cfg);
+ if (err)
+ dprintf(CRITICAL, "[MSDC] switch to part %u failed!\n", dev->part_id);
+ else
+ card->ext_csd.part_cfg = cfg;
+
+ return err;
+}
+
+static int mmc_cmd(struct mmc_host *host, struct mmc_command *cmd)
+{
+ int err;
+ int retry = cmd->retries;
+
+ do {
+ err = msdc_cmd(host, cmd);
+ if (err == MMC_ERR_NONE || cmd->opcode == MMC_CMD21) /* do not tuning CMD21 */
+ break;
+ } while (retry--);
+
+ return err;
+}
+
+static int mmc_app_cmd(struct mmc_host *host, struct mmc_command *cmd,
+ u32 rca, int retries)
+{
+ int err = MMC_ERR_FAILED;
+ struct mmc_command appcmd;
+
+ appcmd.opcode = MMC_CMD_APP_CMD;
+ appcmd.arg = rca << 16;
+ appcmd.rsptyp = RESP_R1;
+ appcmd.retries = CMD_RETRIES;
+ appcmd.timeout = CMD_TIMEOUT;
+
+ do {
+ err = mmc_cmd(host, &appcmd);
+
+ if (err == MMC_ERR_NONE)
+ err = mmc_cmd(host, cmd);
+ if (err == MMC_ERR_NONE)
+ break;
+ } while (retries--);
+
+ return err;
+}
+
+static u32 mmc_select_voltage(struct mmc_host *host, u32 ocr)
+{
+ int bit;
+
+ ocr &= host->ocr_avail;
+
+ bit = __builtin_ffs(ocr);
+ if (bit) {
+ bit -= 1;
+ ocr &= 3 << bit;
+ } else {
+ ocr = 0;
+ }
+ return ocr;
+}
+
+static inline int mmc_go_idle(struct mmc_host *host)
+{
+ struct mmc_command cmd = {
+ MMC_CMD_GO_IDLE_STATE, 0, RESP_NONE, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+ return mmc_cmd(host, &cmd);
+}
+
+static int mmc_send_if_cond(struct mmc_host *host, u32 ocr)
+{
+ struct mmc_command cmd;
+ int err;
+ static const u8 test_pattern = 0xAA;
+ u8 result_pattern;
+
+ /*
+ * To support SD 2.0 cards, we must always invoke SD_SEND_IF_COND
+ * before SD_APP_OP_COND. This command will harmlessly fail for
+ * SD 1.0 cards.
+ */
+
+ cmd.opcode = SD_CMD_SEND_IF_COND;
+ cmd.arg = ((ocr & 0xFF8000) != 0) << 8 | test_pattern;
+ cmd.rsptyp = RESP_R1;
+ cmd.retries = 0;
+ cmd.timeout = CMD_TIMEOUT;
+
+ err = mmc_cmd(host, &cmd);
+
+ if (err != MMC_ERR_NONE)
+ return err;
+
+ result_pattern = cmd.resp[0] & 0xFF;
+
+ if (result_pattern != test_pattern)
+ return MMC_ERR_INVALID;
+
+ return MMC_ERR_NONE;
+}
+
+/*
+ * return MMC_ERR_RETRY means that need re-send CMD1 in stage 2
+ */
+static int mmc_send_op_cond_once(struct mmc_host *host, u32 ocr, u32 *rocr)
+{
+ int i, err = 0;
+ struct mmc_command cmd = {
+ MMC_CMD_SEND_OP_COND, 0, RESP_R3, {0}, CMD_TIMEOUT, 0, 0
+ };
+
+ cmd.arg = ocr;
+
+ for (i = 1; i; i--) {
+ err = mmc_cmd(host, &cmd);
+ if (err)
+ break;
+
+ /* if we're just probing, do a single pass */
+ if (ocr == 0)
+ break;
+
+ if (cmd.resp[0] & MMC_CARD_BUSY)
+ break;
+
+ err = MMC_ERR_RETRY;
+ }
+
+ if (!err && rocr)
+ *rocr = cmd.resp[0];
+
+ return err;
+}
+
+static int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
+{
+ int i, err = 0;
+ struct mmc_command cmd = {
+ MMC_CMD_SEND_OP_COND, 0, RESP_R3, {0}, CMD_TIMEOUT, 0, 0
+ };
+
+ cmd.arg = ocr;
+
+ for (i = 100; i; i--) {
+ err = mmc_cmd(host, &cmd);
+ if (err)
+ break;
+
+ /* if we're just probing, do a single pass */
+ if (ocr == 0)
+ break;
+
+ if (cmd.resp[0] & MMC_CARD_BUSY)
+ break;
+
+ err = MMC_ERR_TIMEOUT;
+
+ spin(10000);
+
+ }
+
+ if (!err && rocr)
+ *rocr = cmd.resp[0];
+
+ return err;
+}
+
+static int mmc_send_app_op_cond_once(struct mmc_host *host, u32 ocr, u32 *rocr)
+{
+ struct mmc_command cmd;
+ int i, err = 0;
+
+ cmd.opcode = SD_ACMD_SEND_OP_COND;
+ cmd.arg = ocr;
+ cmd.rsptyp = RESP_R3;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+
+ for (i = 1; i; i--) {
+ err = mmc_app_cmd(host, &cmd, 0, CMD_RETRIES);
+ if (err != MMC_ERR_NONE)
+ break;
+
+ if (cmd.resp[0] & MMC_CARD_BUSY || ocr == 0)
+ break;
+
+ err = MMC_ERR_RETRY;
+ }
+
+ if (rocr)
+ *rocr = cmd.resp[0];
+
+ return err;
+}
+
+static int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
+{
+ struct mmc_command cmd;
+ int i, err = 0;
+
+ cmd.opcode = SD_ACMD_SEND_OP_COND;
+ cmd.arg = ocr;
+ cmd.rsptyp = RESP_R3;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+
+ for (i = 100; i; i--) {
+ err = mmc_app_cmd(host, &cmd, 0, CMD_RETRIES);
+ if (err != MMC_ERR_NONE)
+ break;
+
+ if (cmd.resp[0] & MMC_CARD_BUSY || ocr == 0)
+ break;
+
+ err = MMC_ERR_TIMEOUT;
+
+ spin(10000);
+ }
+
+ if (rocr)
+ *rocr = cmd.resp[0];
+
+ return err;
+}
+
+static int mmc_all_send_cid(struct mmc_host *host)
+{
+ struct mmc_command cmd = {
+ MMC_CMD_ALL_SEND_CID, 0, RESP_R2, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+ return mmc_cmd(host, &cmd);
+}
+
+static int mmc_send_relative_addr(struct mmc_host *host,
+ struct mmc_card *card, unsigned int *rca)
+{
+ int err;
+ struct mmc_command cmd;
+
+ memset(&cmd, 0, sizeof(struct mmc_command));
+
+ if (mmc_card_mmc(card)) { /* set rca */
+ cmd.opcode = MMC_CMD_SET_RELATIVE_ADDR;
+ cmd.arg = *rca << 16;
+ cmd.rsptyp = RESP_R1;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+ } else { /* send rca */
+ cmd.opcode = SD_CMD_SEND_RELATIVE_ADDR;
+ cmd.arg = 0;
+ cmd.rsptyp = RESP_R6;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+ }
+ err = mmc_cmd(host, &cmd);
+ if ((err == MMC_ERR_NONE) && !mmc_card_mmc(card))
+ *rca = cmd.resp[0] >> 16;
+
+ return err;
+}
+
+static int mmc_select_card(struct mmc_host *host, struct mmc_card *card)
+{
+ struct mmc_command cmd = {
+ MMC_CMD_SELECT_CARD, 0, RESP_R1B, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+ cmd.arg = card->rca << 16;
+ return mmc_cmd(host, &cmd);
+}
+
+static int mmc_send_status(struct mmc_host *host, struct mmc_card *card,
+ u32 *status)
+{
+ int err;
+ struct mmc_command cmd = {
+ MMC_CMD_SEND_STATUS, 0, RESP_R1, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+ cmd.arg = card->rca << 16;
+
+ err = mmc_cmd(host, &cmd);
+ if (err == MMC_ERR_NONE)
+ *status = cmd.resp[0];
+ return err;
+}
+
+static int mmc_switch(struct mmc_host *host, struct mmc_card *card,
+ u8 set, u8 index, u8 value)
+{
+ int err;
+ u32 status = 0, count = 0;
+ struct mmc_command cmd = {
+ MMC_CMD_SWITCH, 0, RESP_R1B, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+
+ cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | (index << 16) |
+ (value << 8) | set;
+
+ err = mmc_cmd(host, &cmd);
+ if (err != MMC_ERR_NONE)
+ return err;
+
+ do {
+ err = mmc_send_status(host, card, &status);
+ if (err) {
+ dprintf(CRITICAL, "[eMMC] Fail to send status %d\n", err);
+ break;
+ }
+ if (status & R1_SWITCH_ERROR) {
+ dprintf(CRITICAL, "[eMMC] switch error. arg(0x%x)\n", cmd.arg);
+ return MMC_ERR_FAILED;
+ }
+ if (count++ >= 600000) {
+ dprintf(CRITICAL, "[%s]: timeout happend, count=%d, status=0x%x\n",
+ __func__, count, status);
+ break;
+ }
+ } while (!(status & R1_READY_FOR_DATA) || (R1_CURRENT_STATE(status) == 7));
+
+ if (!err && (index == EXT_CSD_PART_CFG))
+ host->curr_part = value & 0x7;
+
+ return err;
+}
+
+static int mmc_read_csds(struct mmc_host *host, struct mmc_card *card)
+{
+ int err;
+ struct mmc_command cmd = {
+ MMC_CMD_SEND_CSD, 0, RESP_R2, {0}, CMD_TIMEOUT * 100, CMD_RETRIES, 0
+ };
+
+ cmd.arg = card->rca << 16;
+
+ err = mmc_cmd(host, &cmd);
+ if (err == MMC_ERR_NONE) {
+ unsigned int e, m;
+ card->csd.mmca_vsn = UNSTUFF_BITS(&cmd.resp[0], 122, 4);
+ m = UNSTUFF_BITS(&cmd.resp[0], 99, 4);
+ e = UNSTUFF_BITS(&cmd.resp[0], 96, 3);
+ card->csd.max_dtr = tran_exp[e] * mmc_tran_mant[m];
+ e = UNSTUFF_BITS(&cmd.resp[0], 47, 3);
+ m = UNSTUFF_BITS(&cmd.resp[0], 62, 12);
+ card->csd.capacity = (1 + m) << (e + 2);
+ card->csd.read_blkbits = UNSTUFF_BITS(&cmd.resp[0], 80, 4);
+ memcpy(&card->raw_csd, &cmd.resp[0], sizeof(u32) * 4);
+ }
+
+ return err;
+}
+
+static int mmc_decode_csd(struct mmc_card *card)
+{
+ struct mmc_csd *csd = &card->csd;
+ unsigned int e, m, csd_struct;
+ u32 *resp = card->raw_csd;
+
+ /* common part; some part are updated later according to spec. */
+ csd_struct = unstuff_bits(resp, 126, 2);
+ csd->csd_struct = csd_struct;
+
+ /* For MMC
+ * We only understand CSD structure v1.1 and v1.2.
+ * v1.2 has extra information in bits 15, 11 and 10.
+ */
+ if ( ( mmc_card_mmc(card) &&
+ ( csd_struct != CSD_STRUCT_VER_1_0 && csd_struct != CSD_STRUCT_VER_1_1
+ && csd_struct != CSD_STRUCT_VER_1_2 && csd_struct != CSD_STRUCT_EXT_CSD )
+ ) ||
+ ( mmc_card_sd(card) && ( csd_struct != 0 && csd_struct!=1 ) )
+ ) {
+ dprintf(ALWAYS, "Unknown CSD ver %d\n", csd_struct);
+ return MMC_ERR_INVALID;
+ }
+
+ m = unstuff_bits(resp, 99, 4);
+ e = unstuff_bits(resp, 96, 3);
+ csd->max_dtr = tran_exp[e] * tran_mant[m];
+
+ /* update later according to spec. */
+ csd->read_blkbits = unstuff_bits(resp, 80, 4);
+
+ e = unstuff_bits(resp, 47, 3);
+ m = unstuff_bits(resp, 62, 12);
+ csd->capacity = (1 + m) << (e + 2);
+
+ //Specific part
+ if (mmc_card_sd(card)) {
+ switch (csd_struct) {
+ case 0:
+ break;
+ case 1:
+ /*
+ * This is a block-addressed SDHC card. Most
+ * interesting fields are unused and have fixed
+ * values. To avoid getting tripped by buggy cards,
+ * we assume those fixed values ourselves.
+ */
+ mmc_card_set_blockaddr(card);
+
+ m = unstuff_bits(resp, 48, 22);
+ csd->capacity = (1 + m) << 10;
+
+ csd->read_blkbits = 9;
+ break;
+ }
+ } else {
+ csd->mmca_vsn = unstuff_bits(resp, 122, 4);
+ }
+
+ return 0;
+}
+
+static void mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
+{
+ u32 caps = card->host->caps;
+ u8 card_type = ext_csd[EXT_CSD_CARD_TYPE];
+
+ card->ext_csd.sectors =
+ ext_csd[EXT_CSD_SEC_CNT + 0] << 0 |
+ ext_csd[EXT_CSD_SEC_CNT + 1] << 8 |
+ ext_csd[EXT_CSD_SEC_CNT + 2] << 16 |
+ ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
+
+ card->ext_csd.rev = ext_csd[EXT_CSD_REV];
+ card->ext_csd.boot_info = ext_csd[EXT_CSD_BOOT_INFO];
+ card->ext_csd.boot_part_sz = ext_csd[EXT_CSD_BOOT_SIZE_MULT] * 128 * 1024;
+ card->ext_csd.rpmb_sz = ext_csd[EXT_CSD_RPMB_SIZE_MULT] * 128 * 1024;
+
+ if (card->ext_csd.sectors)
+ mmc_card_set_blockaddr(card);
+
+ if (caps & MMC_CAP_EMMC_HS400 &&
+ card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) {
+ card->ext_csd.hs400_support = 1;
+ card->ext_csd.hs_max_dtr = 200000000;
+ } else if (caps & MMC_CAP_EMMC_HS200 &&
+ card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) {
+ card->ext_csd.hs_max_dtr = 200000000;
+ } else if (caps & MMC_CAP_DDR &&
+ card_type & EXT_CSD_CARD_TYPE_DDR_52) {
+ card->ext_csd.ddr_support = 1;
+ card->ext_csd.hs_max_dtr = 52000000;
+ } else if (caps & MMC_CAP_MMC_HIGHSPEED &&
+ card_type & EXT_CSD_CARD_TYPE_52) {
+ card->ext_csd.hs_max_dtr = 52000000;
+ } else if (card_type & EXT_CSD_CARD_TYPE_26) {
+ card->ext_csd.hs_max_dtr = 26000000;
+ } else {
+ /* MMC v4 spec says this cannot happen */
+ dprintf(CRITICAL, "[eMMC] MMCv4 but HS unsupported\n");
+ }
+
+ card->ext_csd.part_cfg = ext_csd[EXT_CSD_PART_CFG];
+ card->ext_csd.sec_support = ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT];
+ card->ext_csd.reset_en = ext_csd[EXT_CSD_RST_N_FUNC];
+
+ return;
+}
+
+/* Read and decode extended CSD. */
+static int mmc_read_ext_csd(struct mmc_host *host, struct mmc_card *card)
+{
+ int err = MMC_ERR_NONE;
+ u8 *ext_csd;
+ int result = MMC_ERR_NONE;
+ struct mmc_data data;
+ addr_t base = host->base;
+ struct mmc_command cmd = {
+ MMC_CMD_SEND_EXT_CSD, 0, RESP_R1, {0}, CMD_TIMEOUT, CMD_RETRIES, 0
+ };
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+ dprintf(CRITICAL, "[eMMC] MMCA_VSN: %d. Skip EXT_CSD\n",
+ card->csd.mmca_vsn);
+ return MMC_ERR_NONE;
+ }
+
+ /*
+ * As the ext_csd is so large and mostly unused, we don't store the
+ * raw block in mmc_card.
+ */
+ ext_csd = malloc(512);
+ ASSERT(ext_csd);
+ memset(ext_csd, 0, 512);
+
+ msdc_reset_tune_counter(host);
+
+ do {
+ MSDC_DMA_ON;
+ MSDC_CLR_FIFO();
+ MSDC_WRITE32(SDC_BLK_NUM, 1);
+ host->blklen = 512;
+ msdc_set_timeout(host, 100000000, 0);
+ err = mmc_cmd(host, &cmd);
+ if (err != MMC_ERR_NONE)
+ goto out;
+
+ data.cmd = &cmd;
+ data.blks = 1;
+ data.buf = ext_csd;
+ data.timeout = 100;
+ err = msdc_dma_transfer(host, &data);
+ MSDC_DMA_OFF;
+ if (err != MMC_ERR_NONE) {
+ if (msdc_abort_handler(host, 1))
+ dprintf(CRITICAL, "[eMMC] data abort failed\n");
+ result = msdc_tune_read(host);
+ }
+ } while (err && result != MMC_ERR_READTUNEFAIL);
+ msdc_reset_tune_counter(host);
+ mmc_decode_ext_csd(card, ext_csd);
+
+out:
+ free(ext_csd);
+ return err;
+}
+
+static void mmc_set_clock(struct mmc_host *host, int state, unsigned int hz)
+{
+ if (hz >= host->f_max) {
+ hz = host->f_max;
+ } else if (hz < host->f_min) {
+ hz = host->f_min;
+ }
+ msdc_config_clock(host, state, hz);
+}
+
+static int mmc_set_bus_width(struct mmc_host *host, struct mmc_card *card, int width)
+{
+ int err = MMC_ERR_NONE;
+ u32 arg = 0;
+ struct mmc_command cmd;
+
+ if (mmc_card_sd(card)) {
+ if (width == HOST_BUS_WIDTH_8) {
+ arg = SD_BUS_WIDTH_4;
+ width = HOST_BUS_WIDTH_4;
+ }
+
+ if ((width == HOST_BUS_WIDTH_4) && (host->caps & MMC_CAP_4_BIT_DATA)) {
+ arg = SD_BUS_WIDTH_4;
+ } else {
+ arg = SD_BUS_WIDTH_1;
+ width = HOST_BUS_WIDTH_1;
+ }
+
+ cmd.opcode = SD_ACMD_SET_BUSWIDTH;
+ cmd.arg = arg;
+ cmd.rsptyp = RESP_R1;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+
+ err = mmc_app_cmd(host, &cmd, card->rca, 0);
+ if (err != MMC_ERR_NONE)
+ goto out;
+
+ msdc_config_bus(host, width);
+ } else if (mmc_card_mmc(card)) {
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
+ goto out;
+
+ if (width == HOST_BUS_WIDTH_8) {
+ if (host->caps & MMC_CAP_8_BIT_DATA) {
+ arg = EXT_CSD_BUS_WIDTH_8;
+ } else {
+ width = HOST_BUS_WIDTH_4;
+ }
+ }
+ if (width == HOST_BUS_WIDTH_4) {
+ if (host->caps & MMC_CAP_4_BIT_DATA) {
+ arg = EXT_CSD_BUS_WIDTH_4;
+ } else {
+ width = HOST_BUS_WIDTH_1;
+ }
+ }
+ if (width == HOST_BUS_WIDTH_1)
+ arg = EXT_CSD_BUS_WIDTH_1;
+
+ err = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, arg);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Switch to bus width(%d) failed\n", arg);
+ goto out;
+ }
+ mmc_card_clr_ddr(card);
+
+ msdc_config_bus(host, width);
+ }
+
+out:
+ return err;
+}
+
+static u32 test_delay_bit(u32 delay, u32 bit)
+{
+ bit %= PAD_DELAY_MAX;
+ return delay & (1 << bit);
+}
+
+static int get_delay_len(u32 delay, u32 start_bit)
+{
+ u32 i;
+
+ for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
+ if (test_delay_bit(delay, start_bit + i) == 0)
+ return i;
+ }
+ return PAD_DELAY_MAX - start_bit;
+}
+
+static struct msdc_delay_phase get_best_delay(u32 delay)
+{
+ int start = 0, len = 0;
+ int start_final = 0, len_final = 0;
+ u8 final_phase = 0xff;
+ struct msdc_delay_phase delay_phase = { 0, };
+
+ if (delay == 0) {
+ dprintf(CRITICAL, "phase error: [map:%x]\n", delay);
+ delay_phase.final_phase = final_phase;
+ return delay_phase;
+ }
+
+ while (start < PAD_DELAY_MAX) {
+ len = get_delay_len(delay, start);
+ if (len_final < len) {
+ start_final = start;
+ len_final = len;
+ }
+ start += len ? len : 1;
+ if (len >= 12 && start_final < 4)
+ break;
+ }
+
+ /* The rule is that to find the smallest delay cell */
+ if (start_final == 0)
+ final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
+ else
+ final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
+ dprintf(ALWAYS, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
+ delay, len_final, final_phase);
+
+ delay_phase.maxlen = len_final;
+ delay_phase.start = start_final;
+ delay_phase.final_phase = final_phase;
+ return delay_phase;
+}
+
+static int mmc_hs200_tune_cmd(struct mmc_host *host, int *cmd_error)
+{
+ int err = MMC_ERR_NONE;
+ u8 *tune_data;
+ u16 data_len = host->caps & MMC_CAP_8_BIT_DATA ? 128: 64;
+ struct mmc_data data;
+ addr_t base = host->base;
+ struct mmc_command cmd = {
+ MMC_CMD21, 0, RESP_R1, {0}, CMD_TIMEOUT, 0, 0
+ };
+
+ tune_data = malloc(data_len);
+ ASSERT(tune_data);
+ memset(tune_data, 0, data_len);
+ *cmd_error = MMC_ERR_NONE;
+
+ msdc_reset_tune_counter(host);
+
+ MSDC_DMA_ON;
+ MSDC_CLR_FIFO();
+ MSDC_WRITE32(SDC_BLK_NUM, 1);
+ host->blklen = data_len;
+ msdc_set_timeout(host, 100000000, 0);
+ err = mmc_cmd(host, &cmd);
+ if (err != MMC_ERR_NONE)
+ *cmd_error = err; /* still need receive data, or will impact the next cmd21 */
+
+ data.cmd = &cmd;
+ data.blks = 1;
+ data.buf = tune_data;
+ data.timeout = 100;
+ err = msdc_dma_transfer(host, &data);
+ MSDC_DMA_OFF;
+ msdc_reset_tune_counter(host);
+
+out:
+ free(tune_data);
+ return err;
+}
+
+static int msdc_tune_together(struct mmc_host *host)
+{
+ addr_t base = host->base;
+ u32 rise_delay = 0, fall_delay = 0;
+ struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
+ u8 final_delay, final_maxlen;
+ int cmd_err;
+ int i;
+ int ret;
+
+ /* Enable Top Data DLY1 and CMD DLY1 */
+ MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
+ MSDC_SET_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL);
+
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_RSPL);
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL | MSDC_IOCON_W_D_SMPL);
+ for (i = 0 ; i < PAD_DELAY_MAX; i++) {
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, i);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, i);
+ ret = mmc_hs200_tune_cmd(host, &cmd_err);
+ if (!ret && !cmd_err)
+ rise_delay |= (1 << i);
+ }
+ final_rise_delay = get_best_delay(rise_delay);
+ /* if rising edge has enough margin, then do not scan falling edge */
+ if (final_rise_delay.maxlen >= 12 ||
+ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
+ goto skip_fall;
+
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_RSPL);
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL | MSDC_IOCON_W_D_SMPL);
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, i);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, i);
+ ret = mmc_hs200_tune_cmd(host, &cmd_err);
+ if (!ret && !cmd_err)
+ fall_delay |= (1 << i);
+ }
+ final_fall_delay = get_best_delay(fall_delay);
+
+skip_fall:
+ final_maxlen = MAX(final_rise_delay.maxlen, final_fall_delay.maxlen);
+ if (final_maxlen == final_rise_delay.maxlen) {
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_RSPL);
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL | MSDC_IOCON_W_D_SMPL);
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY,
+ final_rise_delay.final_phase);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY,
+ final_rise_delay.final_phase);
+ final_delay = final_rise_delay.final_phase;
+ } else {
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_RSPL);
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL | MSDC_IOCON_W_D_SMPL);
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY,
+ final_fall_delay.final_phase);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY,
+ final_fall_delay.final_phase);
+ final_delay = final_fall_delay.final_phase;
+ }
+
+ dprintf(ALWAYS, "Final cmd/data pad delay: %x\n", final_delay);
+ return final_delay == 0xff ? -EIO : 0;
+}
+
+static int mmc_select_hs200(struct mmc_card *card)
+{
+ struct mmc_host *host = card->host;
+ int ret;
+
+ ret = mmc_set_bus_width(host, card, HOST_BUS_WIDTH_8);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "failed to set bus width!\n");
+ return ret;
+ }
+
+ ret = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
+ EXT_CSD_HS_TIMEING_HS200);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "failed to switch to hs200 mode!\n");
+ return ret;
+ }
+
+ mmc_card_set_hs200(card);
+ mmc_set_clock(host, card->state, card->ext_csd.hs_max_dtr);
+
+ return 0;
+}
+
+static int mmc_select_hs400(struct mmc_card *card)
+{
+ struct mmc_host *host = card->host;
+ addr_t base = host->base;
+ int ret;
+
+ mmc_set_clock(host, card->state, 50000000);
+ ret = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
+ EXT_CSD_HS_TIMEING_HS);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "switch to high-speed from hs200 failed, err:%d\n", ret);
+ return ret;
+ }
+
+ ret = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8_DDR);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "switch to bus width for hs400 failed, err:%d\n", ret);
+ return ret;
+ }
+
+ ret = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
+ EXT_CSD_HS_TIMEING_HS400);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "switch to hs400 failed, err:%d\n", ret);
+ return ret;
+ }
+ mmc_card_set_hs400(card);
+ mmc_set_clock(host, card->state, card->ext_csd.hs_max_dtr);
+
+ /*
+ * Apply hs400 settings:
+ * set data tune to default value and apply ds delay setting
+ */
+
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL | MSDC_IOCON_W_D_SMPL);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, 0);
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS); /* hs400 mode must set it to 0 */
+ MSDC_WRITE32(TOP_EMMC50_PAD_DS_TUNE, 0x14814); /* Apply 2731 DS delay setting */
+
+ return ret;
+}
+
+static int mmc_hs200_tuning(struct mmc_card *card)
+{
+ struct mmc_host *host = card->host;
+ int ret;
+
+ ret = msdc_tune_together(host);
+ if (ret == -EIO) {
+ dprintf(CRITICAL, "hs200 tuning cmd/data error!\n");
+ return ret;
+ }
+
+ return MMC_ERR_NONE;
+}
+
+static int mmc_erase_start(struct mmc_card *card, u32 blknr)
+{
+ struct mmc_command cmd = {
+ MMC_CMD_ERASE_GROUP_START, 0, RESP_R1, {0}, CMD_TIMEOUT, 3, 0
+ };
+ if (mmc_card_sd(card))
+ cmd.opcode = MMC_CMD_ERASE_WR_BLK_START;
+ cmd.arg = blknr;
+ return mmc_cmd(card->host, &cmd);
+}
+
+static int mmc_erase_end(struct mmc_card *card, u32 blknr)
+{
+ struct mmc_command cmd = {
+ MMC_CMD_ERASE_GROUP_END, 0, RESP_R1, {0}, CMD_TIMEOUT, 3, 0
+ };
+ if (mmc_card_sd(card))
+ cmd.opcode = MMC_CMD_ERASE_WR_BLK_END;
+ cmd.arg = blknr;
+ return mmc_cmd(card->host, &cmd);
+}
+
+static int mmc_erase(struct mmc_card *card, u32 arg)
+{
+ int err;
+ u32 status;
+ struct mmc_command cmd = {
+ MMC_CMD_ERASE, 0, RESP_R1B, {0}, CMD_TIMEOUT, 3, 0
+ };
+ if (mmc_card_sd(card))
+ arg = 0;
+ cmd.arg = arg;
+
+ if (arg & MMC_ERASE_SECURE_REQ) {
+ if (!(card->ext_csd.sec_support & EXT_CSD_SEC_FEATURE_ER_EN))
+ return MMC_ERR_INVALID;
+ }
+ if ((arg & MMC_ERASE_GC_REQ) || (arg & MMC_ERASE_TRIM)) {
+ if (!(card->ext_csd.sec_support & EXT_CSD_SEC_FEATURE_GB_CL_EN))
+ return MMC_ERR_INVALID;
+ }
+
+ err = mmc_cmd(card->host, &cmd);
+ if (err)
+ return err;
+
+ do {
+ err = mmc_send_status(card->host, card, &status);
+ if (err)
+ break;
+ if (R1_STATUS(status) != 0)
+ break;
+ } while (R1_CURRENT_STATE(status) == 7);
+
+ return err;
+}
+
+static int mmc_do_trim(struct mmc_card *card, off_t start_addr, size_t len)
+{
+ int err = MMC_ERR_NONE;
+ off_t end_addr;
+
+ if (len < card->blklen) {
+ dprintf(CRITICAL, "%s: invalid len: %zd\n", __func__, len);
+ return MMC_ERR_INVALID;
+ }
+
+ end_addr =((start_addr + len) / card->blklen - 1) * card->blklen;
+
+ if (mmc_card_highcaps(card)) {
+ start_addr >>= MMC_BLOCK_BITS_SHFT;
+ end_addr >>= MMC_BLOCK_BITS_SHFT;
+ }
+
+ err = mmc_erase_start(card, start_addr);
+ if (err)
+ goto error;
+
+ err = mmc_erase_end(card, end_addr);
+ if (err)
+ goto error;
+
+ err = mmc_erase(card, MMC_ERASE_TRIM);
+
+error:
+ if (err)
+ dprintf(CRITICAL, "%s: erase range (0x%llx~0x%llx) failed,Err<%d>\n",
+ __func__, start_addr, end_addr, err);
+
+ return err;
+}
+
+static int mmc_set_ext_csd(struct mmc_card *card, u8 addr, u8 value)
+{
+ int err;
+
+ /* can't write */
+ if (192 <= addr || !card)
+ return MMC_ERR_INVALID;
+
+ err = mmc_switch(card->host, card, EXT_CSD_CMD_SET_NORMAL, addr, value);
+
+ if (err == MMC_ERR_NONE)
+ err = mmc_read_ext_csd(card->host, card);
+
+ return err;
+}
+
+static int mmc_set_reset_func(struct mmc_card *card, u8 enable)
+{
+ int err = MMC_ERR_FAILED;
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
+ goto out;
+
+ if (card->ext_csd.reset_en == 0) {
+ err = mmc_set_ext_csd(card, EXT_CSD_RST_N_FUNC, enable);
+ if (err == MMC_ERR_NONE)
+ card->ext_csd.reset_en = enable;
+ } else {
+ /* no need set */
+ return MMC_ERR_NONE;
+ }
+out:
+ return err;
+}
+
+static int mmc_set_boot_bus(struct mmc_card *card, u8 rst_bwidth, u8 mode, u8 bwidth)
+{
+ int err = MMC_ERR_FAILED;
+ u8 arg;
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
+ goto out;
+
+ arg = mode | rst_bwidth | bwidth;
+
+ err = mmc_set_ext_csd(card, EXT_CSD_BOOT_BUS_WIDTH, arg);
+out:
+ return err;
+}
+
+static int mmc_set_part_config(struct mmc_card *card, u8 cfg)
+{
+ int err = MMC_ERR_FAILED;
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
+ goto out;
+
+ err = mmc_set_ext_csd(card, EXT_CSD_PART_CFG, cfg);
+out:
+ return err;
+}
+
+static int mmc_boot_config(struct mmc_card *card, u8 acken, u8 enpart, u8 buswidth, u8 busmode)
+{
+ int err = MMC_ERR_FAILED;
+ u8 val;
+ u8 rst_bwidth = 0;
+ u8 cfg;
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4 ||
+ !card->ext_csd.boot_info || card->ext_csd.rev < 3)
+ goto out;
+
+ cfg = card->ext_csd.part_cfg;
+ /* configure boot partition */
+ val = acken | enpart | (cfg & 0x7);
+ err = mmc_set_part_config(card, val);
+ if (err != MMC_ERR_NONE)
+ goto out;
+ else
+ card->ext_csd.part_cfg = val;
+
+ /* configure boot bus mode and width */
+ rst_bwidth = (buswidth != EXT_CSD_BOOT_BUS_WIDTH_1 ? 1 : 0) << 2;
+ dprintf(INFO, " =====Set boot Bus Width<%d>=======\n", buswidth);
+ dprintf(INFO, " =====Set boot Bus mode<%d>=======\n", busmode);
+ err = mmc_set_boot_bus(card, rst_bwidth, busmode, buswidth);
+out:
+
+ return err;
+}
+
+#define EFUSE_BOOTDEV_SPEEDUP_EN (0x1 << 5)
+
+#define EFUSE_IS_EMMC_BOOT_BUS_WIDTH_8BIT() \
+ (readl((EFUSE_BASE + 0x20)) & EFUSE_BOOTDEV_SPEEDUP_EN)
+
+static int emmc_boot_prepare(struct mmc_card *card)
+{
+ int err = MMC_ERR_NONE;
+ u8 buswidth = EXT_CSD_BOOT_BUS_WIDTH_1;
+
+ if (EFUSE_IS_EMMC_BOOT_BUS_WIDTH_8BIT())
+ buswidth = EXT_CSD_BOOT_BUS_WIDTH_8;
+
+ err = mmc_boot_config(card, EXT_CSD_PART_CFG_EN_ACK,
+ EXT_CSD_PART_CFG_EN_BOOT_PART_1,
+ buswidth, EXT_CSD_BOOT_BUS_MODE_DEFT);
+ if (err)
+ goto exit;
+
+ err = mmc_set_reset_func(card, 1);
+exit:
+ return err;
+}
+
+static int mmc_dev_bread(struct mmc_card *card, unsigned long blknr, u32 blkcnt, u8 *dst)
+{
+ struct mmc_host *host = card->host;
+ u32 blksz = host->blklen;
+ int tune = 0;
+ int retry = 3;
+ int err;
+ unsigned long src;
+
+ src = mmc_card_highcaps(card) ? blknr : blknr * blksz;
+
+ do {
+ if (!tune) {
+ err = host->blk_read(host, (uchar *)dst, src, blkcnt);
+ } else {
+#ifdef FEATURE_MMC_RD_TUNING
+ err = msdc_tune_bread(host, (uchar *)dst, src, blkcnt);
+#endif
+ if (err && (host->sclk > (host->f_max >> 4)))
+ mmc_set_clock(host, card->state, host->sclk >> 1);
+ }
+ if (err == MMC_ERR_NONE) {
+ break;
+ }
+
+ if (err == MMC_ERR_BADCRC || err == MMC_ERR_ACMD_RSPCRC || err == MMC_ERR_CMD_RSPCRC) {
+ tune = 1;
+ retry++;
+ } else if (err == MMC_ERR_READTUNEFAIL || err == MMC_ERR_CMDTUNEFAIL) {
+ dprintf(CRITICAL, "[eMMC] Fail to tuning,%s",
+ (err == MMC_ERR_CMDTUNEFAIL) ?
+ "cmd tune failed!\n" : "read tune failed!\n");
+ break;
+ }
+ } while (retry--);
+
+ return err;
+}
+
+static int mmc_dev_bwrite(struct mmc_card *card, unsigned long blknr,
+ u32 blkcnt, const u8 *src)
+{
+ struct mmc_host *host = card->host;
+ u32 blksz = host->blklen;
+ u32 status;
+ int tune = 0;
+ int retry = 3;
+ int err;
+ unsigned long dst;
+
+ dst = mmc_card_highcaps(card) ? blknr : blknr * blksz;
+
+ do {
+ if (!tune) {
+ err = host->blk_write(host, dst, (uchar *)src, blkcnt);
+ } else {
+#ifdef FEATURE_MMC_WR_TUNING
+ err = msdc_tune_bwrite(host, dst, (uchar *)src, blkcnt);
+#endif
+ if (err && (host->sclk > (host->f_max >> 4)))
+ mmc_set_clock(host, card->state, host->sclk >> 1);
+ }
+ if (err == MMC_ERR_NONE) {
+ do {
+ err = mmc_send_status(host, card, &status);
+ if (err) {
+ dprintf(CRITICAL, "[eMMC] Fail to send status %d\n", err);
+ break;
+ }
+ } while (!(status & R1_READY_FOR_DATA) ||
+ (R1_CURRENT_STATE(status) == 7));
+ dprintf(INFO, "[eMMC] Write %d bytes (DONE)\n", blkcnt * blksz);
+ break;
+ }
+
+ if (err == MMC_ERR_BADCRC || err == MMC_ERR_ACMD_RSPCRC || err == MMC_ERR_CMD_RSPCRC) {
+ tune = 1;
+ retry++;
+ } else if (err == MMC_ERR_WRITETUNEFAIL || err == MMC_ERR_CMDTUNEFAIL) {
+ dprintf(CRITICAL, "[eMMC] Fail to tuning,%s",
+ (err == MMC_ERR_CMDTUNEFAIL) ?
+ "cmd tune failed!\n" : "write tune failed!\n");
+ break;
+ }
+ } while (retry--);
+
+ return err;
+}
+
+static ssize_t mmc_block_read(struct bdev *dev, void *buf, bnum_t block,
+ uint count)
+{
+ mmc_dev_t *__dev = (mmc_dev_t *)dev;
+ struct mmc_host *host = __dev->host;
+ struct mmc_card *card = __dev->card;
+ u32 maxblks = host->max_phys_segs;
+ u32 leftblks, totalblks = count;
+ ssize_t ret = 0;
+
+ mutex_acquire(&host->lock);
+ if (mmc_switch_part(__dev)) {
+ ret = ERR_IO;
+ goto done;
+ }
+
+ do {
+ leftblks = ((count > maxblks) ? maxblks : count);
+ if (mmc_dev_bread(card, (unsigned long)block, leftblks, buf)) {
+ ret = ERR_IO;
+ goto done;
+ }
+ block += leftblks;
+ buf += maxblks * dev->block_size;
+ count -= leftblks;
+ } while (count);
+
+ if (dev->block_size * totalblks > 0x7fffffffU)
+ /* ssize_t is defined as signed, should take a look here */
+ dprintf(CRITICAL, "[MSDC] %s: WARN! The return size is overflow! 0x%zx\n",
+ __func__, dev->block_size * totalblks);
+
+done:
+ mutex_release(&host->lock);
+ if (ret != 0) {
+ return ret;
+ } else {
+ return (ssize_t)dev->block_size * totalblks;
+ }
+}
+
+static ssize_t mmc_block_write(struct bdev *dev, const void *buf, bnum_t block,
+ uint count)
+{
+ mmc_dev_t *__dev = (mmc_dev_t *)dev;
+ struct mmc_host *host = __dev->host;
+ struct mmc_card *card = __dev->card;
+ u32 maxblks = host->max_phys_segs;
+ u32 leftblks, totalblks = count;
+ ssize_t ret = 0;
+
+ mutex_acquire(&host->lock);
+ if (mmc_switch_part(__dev)) {
+ ret = ERR_IO;
+ goto done;
+ }
+
+ do {
+ leftblks = ((count > maxblks) ? maxblks : count);
+ if (mmc_dev_bwrite(card, (unsigned long)block, leftblks, buf)) {
+ ret = ERR_IO;
+ goto done;
+ }
+ block += leftblks;
+ buf = (u8 *)buf + maxblks * dev->block_size;
+ count -= leftblks;
+ } while (count);
+
+ if (dev->block_size * totalblks > 0x7fffffffU)
+ /* ssize_t is defined as signed, should take a look here */
+ dprintf(CRITICAL, "[MSDC] %s: WARN! The return size is overflow! 0x%zx\n",
+ __func__, dev->block_size * totalblks);
+
+done:
+ mutex_release(&host->lock);
+ if (ret != 0) {
+ return ret;
+ } else {
+ return (ssize_t)dev->block_size * totalblks;
+ }
+}
+
+static ssize_t mmc_wrap_erase(struct bdev *bdev, off_t offset, size_t len)
+{
+ mmc_dev_t *dev = (mmc_dev_t *)bdev;
+ struct mmc_host *host = dev->host;
+ ssize_t ret = 0;
+
+ mutex_acquire(&host->lock);
+ if (mmc_switch_part(dev)) {
+ ret = ERR_IO;
+ goto done;
+ }
+
+ /* ATTENTION:
+ * We use TRIM here, which is block-based(512B) wipping,
+ * If using ERASE here, please ensure the offset & size are
+ * erase-group aligned,
+ * OTHERWISE, some valid data may be wiped. refer to JEDEC spec:
+ * The Device will ignore all LSB's below the Erase Group size,
+ * effectively ROUNDING the address DOWN to the Erase Group boundary. */
+ ASSERT(dev && len);
+ if ((offset % MMC_BLOCK_SIZE) || (len % MMC_BLOCK_SIZE)) {
+ dprintf(CRITICAL, "%s: offset(0x%llx)/len(%zu) is not block-aligned!\n",
+ __func__, offset, len);
+ ret = ERR_IO;
+ goto done;
+ }
+
+ ASSERT(dev->card);
+ if (mmc_do_trim(dev->card, offset, len)) {
+ ret = ERR_IO;
+ goto done;
+ }
+
+done:
+ mutex_release(&host->lock);
+ return ret ? ret: (ssize_t)len;
+}
+
+static ssize_t mmc_rpmb_dummy_read(struct bdev *dev, void *buf, bnum_t block,
+ uint count)
+{
+ return 0;
+}
+
+static ssize_t mmc_rpmb_dummy_write(struct bdev *dev, const void *buf, bnum_t block,
+ uint count)
+{
+ return 0;
+}
+
+static ssize_t mmc_rpmb_dummy_erase(struct bdev *bdev, off_t offset, size_t len)
+{
+ return 0;
+}
+
+static int mmc_set_block_count(struct mmc_host *host, unsigned int blockcount,
+ bool is_rel_write)
+{
+ struct mmc_command cmd = {0};
+
+ cmd.opcode = MMC_CMD_SET_BLOCK_COUNT;
+ cmd.arg = blockcount & 0x0000FFFF;
+ if (is_rel_write)
+ cmd.arg |= 1 << 31;
+ cmd.rsptyp = RESP_R1;
+
+ return mmc_cmd(host, &cmd);
+}
+
+static int mmc_rpmb_ioctl_cmd(struct bdev *dev, struct mmc_ioc_cmd *arg)
+{
+ mmc_dev_t *__dev = (mmc_dev_t *)dev;
+ struct mmc_host *host = __dev->host;
+ //struct mmc_card *card = __dev->card;
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
+ addr_t base = host->base;
+ int ret = 0;
+ int old_autocmd = msdc_get_autocmd(host);
+
+ msdc_set_autocmd(host, 0);
+ cmd.opcode = arg->opcode;
+ cmd.arg = arg->arg;
+ cmd.rsptyp = arg->flags; /* arg->flags must be type of enum of RESP_NONE ~ RESP_R1B */
+
+ if (arg->blocks) {
+ ret = mmc_set_block_count(host, arg->blocks,
+ arg->write_flag & (1 << 31));
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "mmc cmd23 failed!\n");
+ goto out;
+ }
+ }
+
+ if (arg->blocks) {
+ MSDC_DMA_ON;
+ MSDC_CLR_FIFO();
+ MSDC_WRITE32(SDC_BLK_NUM, arg->blocks);
+ host->blklen = 512;
+ msdc_set_timeout(host, 100000000, 0);
+ ret = mmc_cmd(host, &cmd);
+ if (ret != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "mmc cmd failed\n");
+ goto out;
+ }
+
+ data.cmd = &cmd;
+ data.blks = arg->blocks;
+ data.buf = (uchar *)(uintptr_t)arg->data_ptr;
+ data.timeout = 100;
+ ret = msdc_dma_transfer(host, &data);
+ MSDC_DMA_OFF;
+
+ } else {
+ ret = mmc_cmd(host, &cmd);
+ }
+
+out:
+ msdc_set_autocmd(host, old_autocmd);
+ return ret;
+}
+
+static int mmc_rpmb_ioctl(struct bdev *dev, int request, void *argp)
+{
+ mmc_dev_t *__dev = (mmc_dev_t *)dev;
+ struct mmc_host *host = __dev->host;
+ int ret = 0;
+
+ mutex_acquire(&host->lock);
+ if (mmc_switch_part(__dev)) {
+ ret = ERR_IO;
+ goto done;
+ }
+
+ switch (request) {
+ case MMC_IOC_CMD:
+ ret = mmc_rpmb_ioctl_cmd(dev, (struct mmc_ioc_cmd *)argp);
+ break;
+ default:
+ ret = ERR_INVALID_ARGS;
+ break;
+ }
+
+done:
+ mutex_release(&host->lock);
+ return ret;
+}
+
+static int mmc_bio_ioctl(struct bdev *dev, int request, void *argp)
+{
+ int ret = 0;
+
+ switch (request) {
+ case BIO_IOCTL_QUERY_CAP_REWRITABLE:
+ ret = NO_ERROR;
+ *(void **)argp = (void *)true;
+ break;
+ default:
+ ret = ERR_INVALID_ARGS;
+ break;
+ }
+ return ret;
+}
+
+static int mmc_init_mem_card_stage1(struct mmc_host *host,
+ struct mmc_card *card, u32 ocr)
+{
+ int err;
+
+ /*
+ * Sanity check the voltages that the card claims to
+ * support.
+ */
+ if (ocr & 0x7F)
+ ocr &= ~0x7F;
+
+ ocr = host->ocr = mmc_select_voltage(host, ocr);
+
+ /*
+ * Can we support the voltage(s) of the card(s)?
+ */
+ if (!host->ocr) {
+ err = MMC_ERR_FAILED;
+ goto out;
+ }
+
+ err = mmc_go_idle(host);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in GO_IDLE_STATE cmd\n");
+ goto out;
+ }
+
+ /* send interface condition */
+ if (mmc_card_sd(card))
+ err = mmc_send_if_cond(host, ocr);
+
+ /* host support HCS[30] */
+ ocr |= (1 << 30);
+
+ /* send operation condition */
+ if (mmc_card_sd(card)) {
+ err = mmc_send_app_op_cond_once(host, ocr, &card->ocr);
+ } else {
+ /* The extra bit indicates that we support high capacity */
+ err = mmc_send_op_cond_once(host, ocr, &card->ocr);
+ }
+
+out:
+ /* MMC_ERR_RETRY is not error */
+ return err;
+}
+
+static int mmc_init_mem_card_stage2(struct mmc_host *host,
+ struct mmc_card *card, bool retry_opcond)
+{
+ int err = MMC_ERR_NONE;
+ u32 ocr = host->ocr;
+
+ /* host support HCS[30] */
+ ocr |= (1 << 30);
+
+ if (retry_opcond) {
+ /* send operation condition */
+ if (mmc_card_sd(card)) {
+ err = mmc_send_app_op_cond(host, ocr, &card->ocr);
+ } else {
+ /* The extra bit indicates that we support high capacity */
+ err = mmc_send_op_cond(host, ocr, &card->ocr);
+ }
+ }
+
+ if (err != MMC_ERR_NONE) {
+ dprintf(INFO, "Fail in SEND_OP_COND cmd\n");
+ goto out;
+ }
+
+ /* set hcs bit if a high-capacity card */
+ card->state |= ((card->ocr >> 30) & 0x1) ? MMC_STATE_HIGHCAPS : 0;
+ /* send cid */
+ err = mmc_all_send_cid(host);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in SEND_CID cmd\n");
+ goto out;
+ }
+
+ /* assign a rca */
+ card->rca = 0x1;
+
+ /* set/send rca */
+ err = mmc_send_relative_addr(host, card, &card->rca);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in SEND_RCA cmd\n");
+ goto out;
+ }
+
+ /* send csd */
+ err = mmc_read_csds(host, card);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in SEND_CSD cmd\n");
+ goto out;
+ }
+ mmc_decode_csd(card);
+
+ /* select this card */
+ err = mmc_select_card(host, card);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in select card cmd\n");
+ goto out;
+ }
+
+ if (mmc_card_sd(card)) {
+ /* set bus width */
+ mmc_set_bus_width(host, card, HOST_BUS_WIDTH_4);
+ /* compute bus speed. usd defalut speed */
+ card->maxhz = 26000000;
+ mmc_set_clock(host, card->state, card->maxhz);
+ } else {
+
+ /* send ext csd */
+ err = mmc_read_ext_csd(host, card);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in SEND_EXT_CSD cmd\n");
+ goto out;
+ }
+ if (host->caps & MMC_CAP_EMMC_HS200 && host->caps & MMC_CAP_EMMC_HS400) {
+ if (card->ext_csd.hs400_support) {
+ err = mmc_select_hs200(card);
+ if (err != MMC_ERR_NONE)
+ goto select_hs;
+ err = mmc_hs200_tuning(card);
+ if (err != MMC_ERR_NONE)
+ goto select_hs;
+ err = mmc_select_hs400(card);
+ if (err != MMC_ERR_NONE)
+ goto select_hs;
+ else
+ goto card_init_done;
+ }
+ }
+
+select_hs:
+ /* activate high speed (if supported) */
+ if ((card->ext_csd.hs_max_dtr != 0) && (host->caps & MMC_CAP_MMC_HIGHSPEED)) {
+ mmc_set_clock(host, 0, host->f_min);
+ err = mmc_switch(host, card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+ if (err == MMC_ERR_NONE) {
+ dprintf(INFO, "[eMMC] Switched to High-Speed mode!\n");
+ mmc_card_clear_hs200(card);
+ mmc_card_clear_hs400(card);
+ mmc_card_clear_ddr(card);
+ mmc_card_set_highspeed(card);
+ mmc_set_clock(host, card->state, 50000000);
+ /* set bus width */
+ mmc_set_bus_width(host, card, HOST_BUS_WIDTH_8);
+ }
+ }
+
+card_init_done:
+ /* compute bus speed. */
+ card->maxhz = (unsigned int)-1;
+
+ if (mmc_card_highspeed(card) || mmc_card_hs400(card)) {
+ if (card->maxhz > card->ext_csd.hs_max_dtr)
+ card->maxhz = card->ext_csd.hs_max_dtr;
+ } else if (card->maxhz > card->csd.max_dtr) {
+ card->maxhz = card->csd.max_dtr;
+ }
+ }
+
+ if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
+ /* The EXT_CSD sector count is in number or 512 byte sectors. */
+ card->blklen = MMC_BLOCK_SIZE;
+ card->nblks = card->ext_csd.sectors;
+ } else {
+ /* The CSD capacity field is in units of read_blkbits.
+ * set_capacity takes units of 512 bytes.
+ */
+ card->blklen = MMC_BLOCK_SIZE;
+ host->blklen = MMC_BLOCK_SIZE;
+ card->nblks = card->csd.capacity << (card->csd.read_blkbits - 9);
+ }
+
+ dprintf(CRITICAL,"[eMMC/SD] Size: %d MB, Max.Speed: %d kHz, blklen(%d), nblks(%d), ro(%d)\n",
+ ((card->nblks / 1024) * card->blklen) / 1024 , card->maxhz / 1000,
+ card->blklen, card->nblks, mmc_card_readonly(card));
+
+ card->ready = 1;
+
+ dprintf(INFO, "[eMMC/SD] Initialized\n");
+out:
+ return err;
+}
+
+static int mmc_init_card_stage1(struct mmc_host *host, struct mmc_card *card)
+{
+ int err;
+ u32 ocr;
+
+ dprintf(INFO, "[%s]: start\n", __func__);
+ memset(card, 0, sizeof(struct mmc_card));
+
+ mmc_card_set_present(card);
+ mmc_card_set_host(card, host);
+ mmc_card_set_unknown(card);
+
+ err = mmc_go_idle(host);
+ if (err != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[eMMC] Fail in GO_IDLE_STATE cmd\n");
+ goto out;
+ }
+
+ /* send interface condition */
+ if (host->host_id)
+ mmc_send_if_cond(host, host->ocr_avail);
+
+ /* query operation condition */
+
+ if (host->host_id) {
+ err = mmc_send_app_op_cond(host, 0, &ocr);
+ if (err != MMC_ERR_NONE) {
+ err = mmc_send_op_cond(host, 0, &ocr);
+ if (err != MMC_ERR_NONE) {
+ dprintf(INFO, "Fail in MMC_CMD_SEND_OP_COND/SD_ACMD_SEND_OP_COND cmd\n");
+ goto out;
+ }
+ mmc_card_set_mmc(card);
+ } else {
+ mmc_card_set_sd(card);
+ }
+ } else {
+ err = mmc_send_op_cond(host, 0, &ocr);
+ if (err != MMC_ERR_NONE) {
+ dprintf(INFO, "Fail in MMC_CMD_SEND_OP_COND/SD_ACMD_SEND_OP_COND cmd\n");
+ goto out;
+ }
+ mmc_card_set_mmc(card);
+ }
+
+ host->card = card;
+ err = mmc_init_mem_card_stage1(host, card, ocr);
+
+out:
+ return err;
+}
+
+static int mmc_init_card_stage2(struct mmc_host *host, struct mmc_card *card,
+ bool retry_opcond)
+{
+ int err;
+
+ err = mmc_init_mem_card_stage2(host, card, retry_opcond);
+ if (err) {
+ dprintf(CRITICAL, "[%s]: failed, err=%d\n", __func__, err);
+ return err;
+ }
+ host->card = card;
+ dprintf(INFO, "[%s]: finish successfully\n",__func__);
+ return 0;
+}
+
+static inline int mmc_init_host(struct mmc_host *host)
+{
+ mutex_init(&host->lock);
+ return msdc_init(host);
+}
+
+static int mmc_bio_ops(const void *name, const int part_id, const int nblks,
+ struct mmc_host *host, struct mmc_card *card)
+{
+ mmc_dev_t *dev;
+ bio_erase_geometry_info_t *geometry;
+
+ dev = malloc(sizeof(mmc_dev_t));
+ /* malloc fail */
+ ASSERT(dev);
+ /* construct the block device */
+ memset(dev, 0, sizeof(mmc_dev_t));
+
+ geometry = (bio_erase_geometry_info_t *)malloc(sizeof(bio_erase_geometry_info_t));
+ if (!geometry) {
+ dprintf(CRITICAL, "%s: no enough memory for geometry\n", __func__);
+ free(dev);
+ return -1;
+ }
+
+ /* setup partition id*/
+ dev->part_id = part_id;
+ /* setup host */
+ dev->host = host;
+ /* setup card */
+ dev->card = card;
+
+ geometry->start = 0;
+ geometry->size = card->nblks * card->blklen;
+ geometry->erase_size = 512;
+ geometry->erase_shift = log2_uint(geometry->erase_size);
+
+ /* bio block device register */
+ bio_initialize_bdev(&dev->bdev, name,
+ card->blklen, nblks,
+ 1, geometry, BIO_FLAGS_NONE);
+ /* override our block device hooks */
+ if (part_id == EXT_CSD_PART_CFG_RPMB_PART) {
+ dev->bdev.read_block = mmc_rpmb_dummy_read;
+ dev->bdev.write_block = mmc_rpmb_dummy_write;
+ dev->bdev.erase = mmc_rpmb_dummy_erase;
+ dev->bdev.ioctl = mmc_rpmb_ioctl;
+ } else {
+ dev->bdev.read_block = mmc_block_read;
+ dev->bdev.write_block = mmc_block_write;
+ dev->bdev.erase = mmc_wrap_erase;
+ dev->bdev.ioctl = mmc_bio_ioctl;
+ }
+ bio_register_device(&dev->bdev);
+ return (partition_publish(dev->bdev.name, 0x0) < 0) ? -1 : 0;
+}
+
+struct mmc_card *emmc_init_stage1(bool *retry_opcond)
+{
+ int err = MMC_ERR_NONE;
+ struct mmc_host *host;
+ struct mmc_card *card;
+
+ host = &msdc_host0;
+ /* construct the block device */
+ memset(host, 0, sizeof(struct mmc_host));
+ host->host_id = 0;
+
+ card = &emmc_card;
+ /* construct the block device */
+ memset(card, 0, sizeof(struct mmc_card));
+
+ err = mmc_init_host(host);
+
+ if (err == MMC_ERR_NONE)
+ err = mmc_init_card_stage1(host, card);
+
+ if (err && err != MMC_ERR_RETRY) {
+ dprintf(CRITICAL, "failed in %s \n", __func__);
+ return NULL;
+ } else if (err == MMC_ERR_RETRY) {
+ *retry_opcond = true;
+ } else {
+ *retry_opcond = false;
+ }
+
+ return card;
+}
+
+int emmc_init_stage2(struct mmc_card *card, bool retry_opcond)
+{
+ int err = MMC_ERR_NONE;
+
+ struct mmc_host *host;
+ int boot_part_nblks = 0;
+ int rpmb_part_nblks = 0;
+
+ host = card->host;
+ err = mmc_init_card_stage2(host, card, retry_opcond);
+ /* mmc init fail */
+ ASSERT(err == MMC_ERR_NONE);
+
+ err = emmc_boot_prepare(card);
+ ASSERT(err == MMC_ERR_NONE);
+
+ err = mmc_bio_ops("mmc0", EXT_CSD_PART_CFG_DEFT_PART, card->nblks, host, card);
+ if (err)
+ goto end;
+
+ boot_part_nblks = card->ext_csd.boot_part_sz/card->blklen;
+
+ err = mmc_bio_ops("mmc0boot0", EXT_CSD_PART_CFG_BOOT_PART_1, boot_part_nblks,
+ host, card);
+ if (err)
+ goto end;
+
+ err = mmc_bio_ops("mmc0boot1", EXT_CSD_PART_CFG_BOOT_PART_2, boot_part_nblks,
+ host, card);
+ if (err)
+ goto end;
+
+ rpmb_part_nblks = card->ext_csd.rpmb_sz/card->blklen;
+
+ err = mmc_bio_ops("mmc0rpmb", EXT_CSD_PART_CFG_RPMB_PART, rpmb_part_nblks,
+ host, card);
+
+end:
+ return err;
+}
+
+int sdmmc_init(u8 host_id)
+{
+ int err = MMC_ERR_NONE;
+ struct mmc_host *host;
+ struct mmc_card *card;
+ bool retry_opcond;
+
+ printf("%s enter\n", __func__);
+
+ host = malloc(sizeof(struct mmc_host));
+ /* malloc fail */
+ if (!host) {
+ dprintf(INFO, "Failed to malloc host!\n");
+ err = -ENOMEM;
+ goto end;
+ }
+ /* construct the block device */
+ memset(host, 0, sizeof(struct mmc_host));
+ host->host_id = host_id;
+
+ card = malloc(sizeof(struct mmc_card));
+ /* malloc fail */
+ if (!card) {
+ dprintf(INFO, "Failed to malloc card!\n");
+ free(host);
+ err = -ENOMEM;
+ goto end;
+ }
+ /* construct the block device */
+ memset(card, 0, sizeof(struct mmc_card));
+
+ err = mmc_init_host(host);
+
+ if (err == MMC_ERR_NONE)
+ err = mmc_init_card_stage1(host, card);
+ /* mmc init fail */
+ if (err && err != MMC_ERR_RETRY) {
+ dprintf(INFO, "mmc_init_card fail!\n");
+ free(host);
+ free(card);
+ goto end;
+ } else if (err == MMC_ERR_RETRY) {
+ retry_opcond = true;
+ } else {
+ retry_opcond = false;
+ }
+
+ err = mmc_init_card_stage2(host, card, retry_opcond);
+ if (err != MMC_ERR_NONE) {
+ dprintf(INFO, "mmc_init_card fail!\n");
+ free(host);
+ free(card);
+ goto end;
+ }
+ err = mmc_bio_ops("sdmmc1", EXT_CSD_PART_CFG_DEFT_PART, card->nblks, host, card);
+
+end:
+ return err;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_rpmb.c b/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_rpmb.c
new file mode 100644
index 0000000..ba9a401
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/mmc/mmc_rpmb.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <lib/bio.h>
+#include <platform/mmc_ioctl.h>
+#include <platform/mmc_rpmb.h>
+#include <platform/mtk_trng.h>
+#include <rpmb_mac.h>
+#include <debug.h>
+
+static void reverse_endian(void *data, size_t size)
+{
+ unsigned int i;
+ char tmp;
+ char *swp = (char *)data;
+
+ for (i = 0 ; i< (size/2); ++i) {
+ tmp = swp[i];
+ swp[i] = swp[size-1-i];
+ swp[size-1-i] = tmp;
+ }
+}
+
+int mmc_rpmb_set_key(u8 *key)
+{
+ int ret;
+ bdev_t *rpdev;
+ struct mmc_ioc_cmd *idata;
+ unsigned char *rpmb_pkt;
+
+ idata = malloc(sizeof(struct mmc_ioc_cmd));
+ if (idata == NULL) {
+ return -2;
+ }
+ rpmb_pkt = malloc(512);
+ if (rpmb_pkt == NULL) {
+ free(idata);
+ return -2;
+ }
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+
+ rpdev = bio_open("mmc0rpmb");
+ if (rpdev == NULL) {
+ free(rpmb_pkt);
+ free(idata);
+ return -3;
+ }
+
+ /* get wc for status */
+ rpmb_pkt[0] = 2;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1;
+ reverse_endian(rpmb_pkt, 512);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 0;
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ reverse_endian(rpmb_pkt, 512);
+ /* check result */
+ ret = *(unsigned short *)&rpmb_pkt[2];
+ if (ret != 7) /* 7 means not programmed yet */
+ goto rpmb_end;
+ dprintf(INFO, "ret=%d, key not programmed yet\n", ret);
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, sizeof(struct mmc_rpmb_cfg));
+
+ rpmb_pkt[0] = 1;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1 << 31;
+ reverse_endian(rpmb_pkt, 512);
+ memcpy(&rpmb_pkt[RPMB_MAC_BEG], key, 32);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, sizeof(struct mmc_rpmb_cfg));
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 0;
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ reverse_endian(rpmb_pkt, 512);
+
+ ret = ((unsigned short *)&rpmb_pkt)[2];
+
+rpmb_end:
+ free(rpmb_pkt);
+ free(idata);
+ bio_close(rpdev);
+ return ret;
+}
+
+int mmc_rpmb_block_read(int blknr, unsigned char blk[256])
+{
+ int ret;
+ bdev_t *rpdev;
+ struct mmc_ioc_cmd *idata;
+ unsigned char *rpmb_pkt;
+ unsigned char mac[RPMB_SZ_MAC];
+ unsigned char nonce[RPMB_SZ_NONCE];
+ unsigned int mac_sz = RPMB_SZ_MAC;
+ int i;
+
+ idata = malloc(sizeof(struct mmc_ioc_cmd));
+ if (idata == NULL)
+ return -2;
+ rpmb_pkt = malloc(512);
+ if (rpmb_pkt == NULL) {
+ free(idata);
+ return -2;
+ }
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+
+ rpdev = bio_open("mmc0rpmb");
+ if (rpdev == NULL) {
+ free(rpmb_pkt);
+ free(idata);
+ return -3;
+ }
+
+ /* read */
+ rpmb_pkt[0] = 4;
+ rpmb_pkt[4] = 1;
+ rpmb_pkt[6] = blknr;
+ if (trng_drv_get_random_data(nonce, RPMB_SZ_NONCE) != RPMB_SZ_NONCE)
+ return -4;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1;
+ reverse_endian(rpmb_pkt, 512);
+ memcpy(rpmb_pkt + RPMB_NONCE_BEG, nonce, RPMB_SZ_NONCE);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 0;
+ reverse_endian(rpmb_pkt, 512);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ ret = *(unsigned short *)&rpmb_pkt[RPMB_RES_BEG];
+ reverse_endian(&ret, sizeof(short));
+ if (ret != 0)
+ goto rpmb_end;
+
+ rpmb_hmac_init(rpmb_pkt + RPMB_DATA_BEG, 512 - RPMB_DATA_BEG);
+ rpmb_hmac_done(mac, &mac_sz);
+ ret = 0;
+ for (i = 0; i < RPMB_SZ_NONCE; i++)
+ ret |= nonce[i] ^ rpmb_pkt[RPMB_NONCE_BEG + i];
+
+ if (ret != 0) {
+ ret = -5;
+ goto rpmb_end;
+ }
+ for (i = 0; i < RPMB_SZ_MAC; i++)
+ ret |= mac[i] ^ rpmb_pkt[RPMB_MAC_BEG + i];
+
+ if (ret != 0) {
+ ret = -1;
+ goto rpmb_end;
+ }
+ memcpy(blk, rpmb_pkt + RPMB_DATA_BEG, RPMB_SZ_DATA);
+ reverse_endian(blk, RPMB_SZ_DATA);
+
+rpmb_end:
+ free(rpmb_pkt);
+ free(idata);
+ bio_close(rpdev);
+ return ret;
+}
+
+int mmc_rpmb_block_write(int blknr, unsigned char blk[256])
+{
+ int ret;
+ bdev_t *rpdev;
+ struct mmc_ioc_cmd *idata;
+ unsigned char *rpmb_pkt;
+ unsigned char nonce[RPMB_SZ_NONCE];
+ unsigned int wc, mac_sz = RPMB_SZ_MAC;
+
+ idata = malloc(sizeof(struct mmc_ioc_cmd));
+ if (idata == NULL) {
+ return -2;
+ }
+ rpmb_pkt = malloc(512);
+ if (rpmb_pkt == NULL) {
+ free(idata);
+ return -2;
+ }
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+
+ rpdev = bio_open("mmc0rpmb");
+ if (rpdev == NULL) {
+ free(rpmb_pkt);
+ free(idata);
+ return -3;
+ }
+
+ /* get wc */
+ rpmb_pkt[0] = 2;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1;
+ reverse_endian(rpmb_pkt, 512);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 0;
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ reverse_endian(rpmb_pkt, 512);
+ /* check result */
+ ret = *(unsigned short *)&rpmb_pkt[2];
+ if (ret != 0) /* get success */
+ goto rpmb_end;
+ wc = *(unsigned int *)&rpmb_pkt[8];
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+ /* do write */
+ rpmb_pkt[0] = 0x3;
+ rpmb_pkt[4] = 1;
+ rpmb_pkt[6] = blknr;
+ *(unsigned int *)&rpmb_pkt[8] = wc;
+ memcpy(rpmb_pkt + 28, blk, RPMB_SZ_DATA);
+ if (trng_drv_get_random_data(nonce, RPMB_SZ_NONCE) != RPMB_SZ_NONCE)
+ return -4;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1<<31;
+ reverse_endian(rpmb_pkt, 512);
+ memcpy(rpmb_pkt + RPMB_NONCE_BEG, nonce, RPMB_SZ_NONCE);
+ rpmb_hmac_init(rpmb_pkt + RPMB_DATA_BEG, 512 - RPMB_DATA_BEG);
+ rpmb_hmac_done(rpmb_pkt + RPMB_MAC_BEG, &mac_sz);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+ /* request to read result back */
+ rpmb_pkt[0] = 0x5;
+
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 1;
+ reverse_endian(rpmb_pkt, 512);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ memset(idata, 0, sizeof(struct mmc_ioc_cmd));
+ memset(rpmb_pkt, 0, 512);
+ /* read result back */
+ idata->flags = RESP_R1;
+ idata->opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
+ idata->blksz = 512;
+ idata->blocks = 1;
+ idata->write_flag = 0;
+ reverse_endian(rpmb_pkt, 512);
+ mmc_ioc_cmd_set_data((*idata), rpmb_pkt);
+
+ ret = bio_ioctl(rpdev, MMC_IOC_CMD, idata);
+ if (ret != 0)
+ goto rpmb_end;
+
+ reverse_endian(rpmb_pkt, 512);
+ /* get result */
+ ret = *(unsigned short *)&rpmb_pkt[2];
+
+rpmb_end:
+ free(rpmb_pkt);
+ free(idata);
+ bio_close(rpdev);
+ return ret;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/mmc/msdc.c b/src/bsp/lk/platform/mt2731/drivers/mmc/msdc.c
new file mode 100644
index 0000000..074da44
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/mmc/msdc.c
@@ -0,0 +1,2473 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#define MSDC_DEBUG_KICKOFF
+
+#include <platform/msdc.h>
+#include <platform/mmc_core.h>
+#include <kernel/event.h>
+#include <kernel/vm.h>
+#include <platform/interrupts.h>
+#include <platform/mt_irq.h>
+#include <string.h>
+#include <assert.h>
+
+#define CMD_RETRIES (5)
+#define CMD_TIMEOUT (100) /* 100ms */
+
+#define PERI_MSDC_SRCSEL (0xc100000c)
+
+/* Tuning Parameter */
+#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
+#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
+#define DEFAULT_WDOD (0) /* write data output delay. no delay. */
+#define DEFAULT_BSYDLY (8) /* card busy delay. 8 extend sclk */
+
+/* Declarations */
+static int msdc_send_cmd(struct mmc_host *host, struct mmc_command *cmd);
+static int msdc_wait_cmd_done(struct mmc_host *host, struct mmc_command *cmd);
+static int msdc_tune_cmdrsp(struct mmc_host *host, struct mmc_command *cmd);
+static void msdc_config_pin(struct mmc_host *host, int mode);
+
+typedef struct {
+ int autocmd;
+ int rdsmpl;
+ int wdsmpl;
+ int rsmpl;
+ int start_bit;
+} msdc_priv_t;
+
+static int msdc_rsp[] = {
+ 0, /* RESP_NONE */
+ 1, /* RESP_R1 */
+ 2, /* RESP_R2 */
+ 3, /* RESP_R3 */
+ 4, /* RESP_R4 */
+ 1, /* RESP_R5 */
+ 1, /* RESP_R6 */
+ 1, /* RESP_R7 */
+ 7, /* RESP_R1b */
+};
+
+struct msdc_cust {
+ unsigned char clk_src; /* host clock source */
+ unsigned char hclk_src; /* host clock source */
+ unsigned char cmd_edge; /* command latch edge */
+ unsigned char data_edge; /* data latch edge */
+#define MSDC_SMPL_RISING (0)
+#define MSDC_SMPL_FALLING (1)
+#define MSDC_SMPL_SEPERATE (2)
+ unsigned char clk_drv; /* clock pad driving */
+ unsigned char cmd_drv; /* command pad driving */
+ unsigned char dat_drv; /* data pad driving */
+ unsigned char rst_drv; /* reset pin pad driving */
+ unsigned char ds_drv; /* ds pad driving */
+ unsigned char data_pins; /* data pins */
+ unsigned int data_offset; /* data address offset */
+ unsigned int flags; /* hardware capability flags */
+#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
+#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
+#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
+#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
+#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
+#define MSDC_REMOVABLE (1 << 5) /* removable slot */
+#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
+#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
+#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
+#define MSDC_DDR (1 << 9) /* ddr mode support */
+#define MSDC_HS200 (1 << 10) /* hs200 mode support(eMMC4.5) */
+#define MSDC_HS400 (1 << 11) /* hs200 mode support(eMMC5.0) */
+} msdc_cap[2] = {
+ {
+ MSDC50_CLKSRC_DEFAULT, /* host clock source */
+ MSDC50_CLKSRC4HCLK_273MHZ, /* host clock source */
+ MSDC_SMPL_RISING, /* command latch edge */
+ MSDC_SMPL_RISING, /* data latch edge */
+ MSDC_DRVN_GEAR4, /* clock pad driving */
+ MSDC_DRVN_GEAR4, /* command pad driving */
+ MSDC_DRVN_GEAR4, /* data pad driving */
+ MSDC_DRVN_GEAR4, /* rst pad driving */
+ MSDC_DRVN_GEAR4, /* ds pad driving */
+ 8, /* data pins */
+ 0, /* data address offset */
+ MSDC_HIGHSPEED | MSDC_HS200 | MSDC_HS400
+ },
+
+ {
+ MSDC50_CLKSRC_DEFAULT, /* host clock source */
+ MSDC50_CLKSRC4HCLK_273MHZ, /* host clock source */
+ MSDC_SMPL_RISING, /* command latch edge */
+ MSDC_SMPL_RISING, /* data latch edge */
+ MSDC_DRVN_GEAR2, /* clock pad driving */
+ MSDC_DRVN_GEAR2, /* command pad driving */
+ MSDC_DRVN_GEAR2, /* data pad driving */
+ MSDC_DRVN_GEAR2, /* rst pad driving */
+ MSDC_DRVN_GEAR2, /* ds pad driving */
+ 4, /* data pins */
+ 0, /* data address offset */
+ MSDC_HIGHSPEED
+ },
+};
+
+static event_t msdc_int_event;
+static u32 g_int_status = 0;
+static msdc_priv_t msdc_priv;
+
+#ifndef FPGA_PLATFORM
+/* add function for MSDC_PAD_CTL handle */
+void msdc_dump_padctl_by_id(u32 id)
+{
+#if defined(MTK_MSDC_BRINGUP_DEBUG)
+ if (id == 0) {
+ dprintf(CRITICAL,
+ "MSDC0 GPIO16[0x%lx] =0x%x\tshould:32'b.001.001 ........ ........ ........\n",
+ MSDC0_GPIO_MODE16, MSDC_READ32(MSDC0_GPIO_MODE16));
+ dprintf(CRITICAL,
+ "MSDC0 GPIO17[0x%lx] =0x%x\tshould:32'b.001.001 .001.001 .001.001 .001.001\n",
+ MSDC0_GPIO_MODE17, MSDC_READ32(MSDC0_GPIO_MODE17));
+ dprintf(CRITICAL,
+ "MSDC0 GPIO18[0x%lx] =0x%x\tshould:32'b........ ........ ........ .001.001\n",
+ MSDC0_GPIO_MODE18, MSDC_READ32(MSDC0_GPIO_MODE18));
+
+ dprintf(CRITICAL,
+ "MSDC0 SMT [0x%lx] =0x%x\tshould:32'b........ ........ ....1111 11111111\n",
+ MSDC0_GPIO_SMT_ADDR, MSDC_READ32(MSDC0_GPIO_SMT_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 IES [0x%lx] =0x%x\tshould:32'b........ ........ ....1111 11111111\n",
+ MSDC0_GPIO_IES_ADDR, MSDC_READ32(MSDC0_GPIO_IES_ADDR));
+
+ dprintf(CRITICAL,
+ "MSDC0 PUPD [0x%lx] =0x%x\tshould:32'b........ ........ ....0100 00000001\n",
+ MSDC0_GPIO_PUPD0_ADDR, MSDC_READ32(MSDC0_GPIO_PUPD0_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 R0 [0x%lx] =0x%x\tshould:32'b........ ........ ....0011 11111110\n",
+ MSDC0_GPIO_R0_ADDR, MSDC_READ32(MSDC0_GPIO_R0_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 R1 [0x%lx] =0x%x\tshould:32'b........ ........ ....0100 00000001\n",
+ MSDC0_GPIO_R1_ADDR, MSDC_READ32(MSDC0_GPIO_R1_ADDR));
+
+ dprintf(CRITICAL,
+ "MSDC0 TDSEL0 [0x%lx] =0x%x\tshould:32'b00000000 00000000 00000000 00000000\n",
+ MSDC0_GPIO_TDSEL0_ADDR, MSDC_READ32(MSDC0_GPIO_TDSEL0_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 TDSEL1 [0x%lx] =0x%x\tshould:32'b........ ........ ........ 00000000\n",
+ MSDC0_GPIO_TDSEL1_ADDR, MSDC_READ32(MSDC0_GPIO_TDSEL1_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 RDSEL0 [0x%lx] =0x%x\tshould:32'b..000000 00000000 00000000 00000000\n",
+ MSDC0_GPIO_RDSEL0_ADDR, MSDC_READ32(MSDC0_GPIO_RDSEL0_ADDR));
+ dprintf(CRITICAL,
+ "MSDC0 RDSEL1 [0x%lx] =0x%x\tshould:32'b..000000 00000000 00000000 00000000\n",
+ MSDC0_GPIO_RDSEL1_ADDR, MSDC_READ32(MSDC0_GPIO_RDSEL1_ADDR));
+
+ dprintf(CRITICAL,
+ "MSDC0 DRV_CFG0 [0x%lx] =0x%x\tshould: 32'b..001001 00100100 10010010 01001001\n",
+ MSDC0_DRV_CFG0, MSDC_READ32(MSDC0_DRV_CFG0));
+ dprintf(CRITICAL,
+ "MSDC0 DRV_CFG1 [0x%lx] =0x%x\tshould: 32'b........ ........ ........ ..001001\n",
+ MSDC0_DRV_CFG1, MSDC_READ32(MSDC0_DRV_CFG1));
+ }
+ else if (id == 1) {
+ } else if (id == 3) {
+ }
+#endif
+}
+
+static void msdc_set_smt(struct mmc_host *host, int smt)
+{
+ MSDC_SET_FIELD(MSDC0_GPIO_SMT_ADDR, MSDC0_SMT_ALL_MASK,
+ (smt ? 0xFFF : 0));
+}
+
+static void msdc_set_ies(struct mmc_host *host, int set_ies)
+{
+ MSDC_SET_FIELD(MSDC0_GPIO_IES_ADDR, MSDC0_IES_ALL_MASK,
+ (set_ies ? 0xFFF : 0));
+}
+
+/* pull up means that host driver the line to HIGH
+ * pull down means that host driver the line to LOW */
+static void msdc_pin_set(struct mmc_host *host, int pull_up_down, MSDC_PIN_STATE mode)
+{
+ /* driver CLK/DAT pin */
+ ASSERT(host);
+ ASSERT(mode < MSDC_PST_MAX);
+ /* 1. don't pull CLK high;
+ * 2. Don't toggle RST to prevent from entering boot mode
+ */
+ if (pull_up_down == MSDC_PIN_PULL_NONE) {
+ /* Switch MSDC0_* to no ohm PU */
+ MSDC_SET_FIELD(MSDC0_GPIO_PUPD0_ADDR, MSDC0_PUPD_ALL_MASK, 0x0);
+ MSDC_SET_FIELD(MSDC0_GPIO_R0_ADDR, MSDC0_R0_ALL_MASK, 0x0);
+ MSDC_SET_FIELD(MSDC0_GPIO_R1_ADDR, MSDC0_R1_ALL_MASK, 0x0);
+ } else if (pull_up_down == MSDC_PIN_PULL_DOWN) {
+ /* Switch MSDC0_* to 50K ohm PD */
+ MSDC_SET_FIELD(MSDC0_GPIO_PUPD0_ADDR, MSDC0_PUPD_ALL_MASK, 0x7FF);
+ MSDC_SET_FIELD(MSDC0_GPIO_R0_ADDR, MSDC0_R0_ALL_MASK, 0x0);
+ MSDC_SET_FIELD(MSDC0_GPIO_R1_ADDR, MSDC0_R1_ALL_MASK, 0x7FF);
+ } else if (pull_up_down == MSDC_PIN_PULL_UP) {
+ /* Switch MSDC0_CLK to 50K ohm PD,
+ * MSDC0_CMD/MSDC0_DAT* to 10K ohm PU,
+ * MSDC0_DSL to 50K ohm PD
+ */
+ MSDC_SET_FIELD(MSDC0_GPIO_PUPD0_ADDR, MSDC0_PUPD_ALL_MASK, 0x401);
+ MSDC_SET_FIELD(MSDC0_GPIO_R0_ADDR, MSDC0_R0_ALL_MASK, 0x3FE);
+ MSDC_SET_FIELD(MSDC0_GPIO_R1_ADDR, MSDC0_R1_ALL_MASK, 0x401);
+ }
+}
+
+/* host can modify from 0-7 */
+static void msdc_set_driving(struct mmc_host *host, struct msdc_cust *msdc_cap)
+{
+ ASSERT(host);
+ ASSERT(msdc_cap);
+
+ if (host && msdc_cap) {
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_CLK_MASK, msdc_cap->clk_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_CMD_MASK, msdc_cap->cmd_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT0_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT1_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT2_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT3_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT4_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT5_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT6_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG0, MSDC0_DRV_DAT7_MASK, msdc_cap->dat_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG1, MSDC0_DRV_DS_MASK, msdc_cap->ds_drv);
+ MSDC_SET_FIELD(MSDC0_DRV_CFG1, MSDC0_DRV_RST_MASK, msdc_cap->rst_drv);
+ }
+}
+
+void msdc_set_pin_mode(struct mmc_host *host)
+{
+ MSDC_SET_FIELD(MSDC0_GPIO_MODE16, 0xFF000000, 0x11);
+ MSDC_SET_FIELD(MSDC0_GPIO_MODE17, 0xFFFFFFFF, 0x11111111);
+ MSDC_SET_FIELD(MSDC0_GPIO_MODE18, 0x000000FF, 0x11);
+}
+
+void msdc_set_rdsel_wrap(struct mmc_host *host)
+{
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL0_ADDR, MSDC0_RDSEL0_CLK_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL0_ADDR, MSDC0_RDSEL0_CMD_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL0_ADDR, MSDC0_RDSEL0_DAT0_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL0_ADDR, MSDC0_RDSEL0_DAT4_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL0_ADDR, MSDC0_RDSEL0_DAT5_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL1_ADDR, MSDC0_RDSEL1_DSL_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL1_ADDR, MSDC0_RDSEL1_RSTB_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL1_ADDR, MSDC0_RDSEL1_DAT123_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL1_ADDR, MSDC0_RDSEL1_DAT7_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_RDSEL1_ADDR, MSDC0_RDSEL1_DAT6_MASK,
+ 0);
+}
+
+void msdc_set_tdsel_wrap(struct mmc_host *host)
+{
+ MSDC_SET_FIELD(MSDC0_GPIO_TDSEL0_ADDR, MSDC0_TDSEL0_CMD_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_TDSEL0_ADDR, MSDC0_TDSEL0_DAT_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_TDSEL0_ADDR, MSDC0_TDSEL0_CLK_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_TDSEL1_ADDR, MSDC0_TDSEL1_DSL_MASK,
+ 0);
+ MSDC_SET_FIELD(MSDC0_GPIO_TDSEL1_ADDR, MSDC0_TDSEL1_RSTB_MASK,
+ 0);
+}
+
+void msdc_gpio_and_pad_init(struct mmc_host *host)
+{
+ /* set smt enable */
+ msdc_set_smt(host, 1);
+
+ /* set pull enable */
+ msdc_config_pin(host, MSDC_PIN_PULL_UP);
+
+ /* set gpio to msdc mode */
+ msdc_set_pin_mode(host);
+
+ /* set ies enable */
+ msdc_set_ies(host, 1);
+
+ /* set driving */
+ msdc_set_driving(host, &msdc_cap[host->host_id]);
+
+ /* set tdsel and rdsel */
+ msdc_set_tdsel_wrap(host);
+ msdc_set_rdsel_wrap(host);
+
+ msdc_dump_padctl_by_id(host->host_id);
+}
+#endif
+
+#ifndef FPGA_PLATFORM /* don't power on/off device and use power-on default volt */
+/* MT2712EVB, GPIO67 to control SD VCCQ, output H --> 3.3V, output L --> 1.8V */
+/* set to 3.3V */
+static void sd_card_vccq_on(void)
+{
+ /* Need porting if needed */
+}
+
+static int pmic_config_interface(int a, int b, int c, int d)
+{
+ return 0;
+}
+
+static void msdc_set_card_pwr(struct mmc_host *host, int on)
+{
+ unsigned int ret;
+
+ ret = pmic_config_interface(0xAB,0x7,0x7,4); /* VMCH=3.3V */
+
+ if (ret == 0) {
+ if (on) {
+ ret = pmic_config_interface(0xAB,0x1,0x1,0); /* VMCH_EN=1 */
+ } else {
+ ret = pmic_config_interface(0xAB,0x0,0x1,0); /* VMCH_EN=0 */
+ }
+ }
+
+ if (ret != 0) {
+ dprintf(CRITICAL, "PMIC: Set MSDC Host Power Fail\n");
+ } else {
+ spin(3000);
+ }
+}
+
+static void msdc_set_host_pwr(struct mmc_host *host, int on)
+{
+ unsigned int ret;
+
+ ret = pmic_config_interface(0xA7,0x7,0x7,4); /* VMC=3.3V */
+
+ if (ret == 0) {
+ if (on) {
+ ret = pmic_config_interface(0xA7,0x1,0x1,0); /* VMC_EN=1 */
+ } else {
+ ret = pmic_config_interface(0xA7,0x0,0x1,0); /* VMC_EN=0 */
+ }
+ }
+
+ if (ret != 0) {
+ dprintf(CRITICAL, "PMIC: Set MSDC Card Power Fail\n");
+ }
+}
+#else
+#define PWR_GPIO (0x10001E84)
+#define PWR_GPIO_EO (0x10001E88)
+
+#define PWR_MASK_EN (0x1 << 8)
+#define PWR_MASK_VOL_18 (0x1 << 9)
+#define PWR_MASK_VOL_33 (0x1 << 10)
+#define PWR_MASK_L4 (0x1 << 11)
+#define PWR_MSDC_DIR (PWR_MASK_EN | PWR_MASK_VOL_18 | PWR_MASK_VOL_33 | PWR_MASK_L4)
+
+#define MSDC0_PWR_MASK_EN (0x1 << 12)
+#define MSDC0_PWR_MASK_VOL_18 (0x1 << 13)
+#define MSDC0_PWR_MASK_VOL_33 (0x1 << 14)
+#define MSDC0_PWR_MASK_L4 (0x1 << 15)
+#define MSDC0_PWR_MSDC_DIR (MSDC0_PWR_MASK_EN | MSDC0_PWR_MASK_VOL_18 | MSDC0_PWR_MASK_VOL_33 | MSDC0_PWR_MASK_L4)
+
+static void sd_card_vccq_on(void)
+{
+}
+
+static void msdc_clr_gpio(u32 bits)
+{
+ switch (bits) {
+ case MSDC0_PWR_MASK_EN:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (MSDC0_PWR_MASK_EN),0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (MSDC0_PWR_MASK_EN),0);
+ break;
+ case MSDC0_PWR_MASK_VOL_18:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 0);
+ break;
+ case MSDC0_PWR_MASK_VOL_33:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 0);
+ break;
+ case MSDC0_PWR_MASK_L4:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, MSDC0_PWR_MASK_L4, 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, MSDC0_PWR_MASK_L4, 0);
+ break;
+ case PWR_MASK_EN:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, PWR_MASK_EN,0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, PWR_MASK_EN,0);
+ break;
+ case PWR_MASK_VOL_18:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 0);
+ break;
+ case PWR_MASK_VOL_33:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 0);
+ break;
+ case PWR_MASK_L4:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, PWR_MASK_L4, 0);
+ MSDC_SET_FIELD(PWR_GPIO_EO, PWR_MASK_L4, 0);
+ break;
+ default:
+ dprintf(CRITICAL, "[%s:%s]invalid value: 0x%x\n", __FILE__, __func__, bits);
+ break;
+ }
+}
+
+static void msdc_set_gpio(u32 bits)
+{
+
+ switch (bits) {
+ case MSDC0_PWR_MASK_EN:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, MSDC0_PWR_MASK_EN,1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, MSDC0_PWR_MASK_EN,1);
+ break;
+ case MSDC0_PWR_MASK_VOL_18:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 1);
+ break;
+ case MSDC0_PWR_MASK_VOL_33:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 2);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (MSDC0_PWR_MASK_VOL_18|MSDC0_PWR_MASK_VOL_33), 2);
+ break;
+ case MSDC0_PWR_MASK_L4:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, MSDC0_PWR_MASK_L4, 1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, MSDC0_PWR_MASK_L4, 1);
+ break;
+ case PWR_MASK_EN:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, PWR_MASK_EN,1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, PWR_MASK_EN,1);
+ break;
+ case PWR_MASK_VOL_18:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 1);
+ break;
+ case PWR_MASK_VOL_33:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 2);
+ MSDC_SET_FIELD(PWR_GPIO_EO, (PWR_MASK_VOL_18|PWR_MASK_VOL_33), 2);
+ break;
+ case PWR_MASK_L4:
+ /* check for set before */
+ MSDC_SET_FIELD(PWR_GPIO, PWR_MASK_L4, 1);
+ MSDC_SET_FIELD(PWR_GPIO_EO, PWR_MASK_L4, 1);
+ break;
+ default:
+ dprintf(CRITICAL, "[%s:%s]invalid value: 0x%x\n", __FILE__, __func__, bits);
+ break;
+ }
+}
+
+static void msdc_set_card_pwr(struct mmc_host *host, int on)
+{
+ if (on) {
+ msdc_set_gpio(MSDC0_PWR_MASK_VOL_18);
+ msdc_set_gpio(MSDC0_PWR_MASK_L4);
+ msdc_set_gpio(MSDC0_PWR_MASK_EN);
+ } else {
+ msdc_clr_gpio(MSDC0_PWR_MASK_EN);
+ msdc_clr_gpio(MSDC0_PWR_MASK_VOL_18);
+ msdc_clr_gpio(MSDC0_PWR_MASK_L4);
+ }
+ spin(10000);
+}
+
+static void msdc_set_host_level_pwr(struct mmc_host *host, u32 level)
+{
+ msdc_clr_gpio(PWR_MASK_VOL_18);
+ msdc_clr_gpio(PWR_MASK_VOL_33);
+
+ if (level) {
+ msdc_set_gpio(PWR_MASK_VOL_18);
+ } else {
+ msdc_set_gpio(PWR_MASK_VOL_33);
+ }
+ msdc_set_gpio(PWR_MASK_L4);
+}
+
+static void msdc_set_host_pwr(struct mmc_host *host, int on)
+{
+ msdc_set_host_level_pwr(host, 0);
+}
+#endif
+
+static void msdc_set_startbit(struct mmc_host *host, u8 start_bit)
+{
+ addr_t base = host->base;
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+
+ /* set start bit */
+ MSDC_SET_FIELD(MSDC_CFG, MSDC_CFG_START_BIT, start_bit);
+ priv->start_bit = start_bit;
+ dprintf(INFO, "start bit = %d, MSDC_CFG[0x%x]\n", start_bit, MSDC_READ32(MSDC_CFG));
+}
+
+#define TYPE_CMD_RESP_EDGE (0)
+#define TYPE_WRITE_CRC_EDGE (1)
+#define TYPE_READ_DATA_EDGE (2)
+#define TYPE_WRITE_DATA_EDGE (3)
+
+static void msdc_set_smpl(struct mmc_host *host, u8 HS400, u8 mode, u8 type)
+{
+ addr_t base = host->base;
+ int i=0;
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+ static u8 read_data_edge[8] = {MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING,
+ MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING
+ };
+ static u8 write_data_edge[4] = {MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING, MSDC_SMPL_RISING};
+
+ switch (type) {
+ case TYPE_CMD_RESP_EDGE:
+ if (HS400) {
+ // eMMC5.0 only output resp at CLK pin, so no need to select DS pin
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_PADCMD_LATCHCK, 0); //latch cmd resp at CLK pin
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CMD_RESP_SEL, 0);//latch cmd resp at CLK pin
+ }
+
+ if (mode == MSDC_SMPL_RISING || mode == MSDC_SMPL_FALLING) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, mode);
+ priv->rsmpl = mode;
+ } else {
+ dprintf(CRITICAL, "[%s]: invalid resp parameter: HS400=%d, type=%d, mode=%d\n", __func__, HS400, type, mode);
+ }
+ break;
+
+ case TYPE_WRITE_CRC_EDGE:
+ if (HS400) {
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_SEL, 1);//latch write crc status at DS pin
+ } else {
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_SEL, 0);//latch write crc status at CLK pin
+ }
+
+ if (mode == MSDC_SMPL_RISING || mode == MSDC_SMPL_FALLING) {
+ if (HS400) {
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_EDGE, mode);
+ } else {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL_SEL, 0);
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL, mode);
+ }
+ priv->wdsmpl = mode;
+ } else if (mode == MSDC_SMPL_SEPERATE && !HS400) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D0SPL, write_data_edge[0]); //only dat0 is for write crc status.
+ priv->wdsmpl = mode;
+ } else {
+ dprintf(CRITICAL, "[%s]: invalid crc parameter: HS400=%d, type=%d, mode=%d\n", __func__, HS400, type, mode);
+ }
+ break;
+
+ case TYPE_READ_DATA_EDGE:
+ if (HS400) {
+ msdc_set_startbit(host, START_AT_RISING_AND_FALLING); //for HS400, start bit is output both on rising and falling edge
+ priv->start_bit = START_AT_RISING_AND_FALLING;
+ } else {
+ msdc_set_startbit(host, START_AT_RISING); //for the other mode, start bit is only output on rising edge. but DDR50 can try falling edge if error casued by pad delay
+ priv->start_bit = START_AT_RISING;
+ }
+ if (mode == MSDC_SMPL_RISING || mode == MSDC_SMPL_FALLING) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL_SEL, 0);
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, mode);
+ priv->rdsmpl = mode;
+ } else if (mode == MSDC_SMPL_SEPERATE) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL_SEL, 1);
+ for (i=0; i<8; i++) {
+ MSDC_SET_FIELD(MSDC_IOCON, (MSDC_IOCON_R_D0SPL << i), read_data_edge[i]);
+ }
+ priv->rdsmpl = mode;
+ } else {
+ dprintf(CRITICAL, "[%s]: invalid read parameter: HS400=%d, type=%d, mode=%d\n", __func__, HS400, type, mode);
+ }
+ break;
+
+ case TYPE_WRITE_DATA_EDGE:
+ MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_SEL, 0);//latch write crc status at CLK pin
+
+ if (mode == MSDC_SMPL_RISING|| mode == MSDC_SMPL_FALLING) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL_SEL, 0);
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL, mode);
+ priv->wdsmpl = mode;
+ } else if (mode == MSDC_SMPL_SEPERATE) {
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL_SEL, 1);
+ for (i=0; i<4; i++) {
+ MSDC_SET_FIELD(MSDC_IOCON, (MSDC_IOCON_W_D0SPL << i), write_data_edge[i]);//dat0~4 is for SDIO card.
+ }
+ priv->wdsmpl = mode;
+ } else {
+ dprintf(CRITICAL, "[%s]: invalid write parameter: HS400=%d, type=%d, mode=%d\n", __func__, HS400, type, mode);
+ }
+ break;
+
+ default:
+ dprintf(CRITICAL, "[%s]: invalid parameter: HS400=%d, type=%d, mode=%d\n", __func__, HS400, type, mode);
+ break;
+ }
+}
+
+void msdc_set_timeout(struct mmc_host *host, u32 ns, u32 clks)
+{
+ addr_t base = host->base;
+ u32 timeout, clk_ns;
+ u32 mode = 0;
+
+ if (host->sclk == 0) {
+ timeout = 0;
+ } else {
+ clk_ns = 1000000000UL / host->sclk;
+ timeout = (ns + clk_ns - 1) / clk_ns + clks;
+ timeout = (timeout + (1 << 20) - 1) >> 20; /* in 1048576 sclk cycle unit */
+ MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, mode);
+ timeout = mode >= 2 ? timeout * 2 : timeout; //DDR mode will double the clk cycles for data timeout
+ timeout = timeout > 1 ? timeout - 1 : 0;
+ timeout = timeout > 255 ? 255 : timeout;
+ }
+ MSDC_SET_FIELD(SDC_CFG, SDC_CFG_DTOC, timeout);
+ dprintf(INFO, "[MSDC] Set read data timeout: %dns %dclks -> %d (65536 sclk cycles)\n",
+ ns, clks, timeout + 1);
+}
+
+void msdc_set_autocmd(struct mmc_host *host, int cmd)
+{
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+
+ priv->autocmd = cmd;
+}
+
+int msdc_get_autocmd(struct mmc_host *host)
+{
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+
+ return priv->autocmd;
+}
+
+static void msdc_abort(struct mmc_host *host)
+{
+ addr_t base = host->base;
+
+ dprintf(CRITICAL, "[MSDC] Abort: MSDC_FIFOCS=%xh MSDC_PS=%xh SDC_STS=%xh\n",
+ MSDC_READ32(MSDC_FIFOCS), MSDC_READ32(MSDC_PS), MSDC_READ32(SDC_STS));
+ /* reset controller */
+ MSDC_RESET();
+
+ /* clear fifo */
+ MSDC_CLR_FIFO();
+
+ /* make sure txfifo and rxfifo are empty */
+ if (MSDC_TXFIFOCNT() != 0 || MSDC_RXFIFOCNT() != 0) {
+ dprintf(INFO, "[MSDC] Abort: TXFIFO(%d), RXFIFO(%d) != 0\n",
+ MSDC_TXFIFOCNT(), MSDC_RXFIFOCNT());
+ }
+
+ /* clear all interrupts */
+ MSDC_CLR_INT();
+}
+
+static int msdc_get_card_status(struct mmc_host *host, u32 *status)
+{
+ int err;
+ struct mmc_command cmd;
+
+ cmd.opcode = MMC_CMD_SEND_STATUS;
+ cmd.arg = host->card->rca << 16;
+ cmd.rsptyp = RESP_R1;
+ cmd.retries = CMD_RETRIES;
+ cmd.timeout = CMD_TIMEOUT;
+
+ err = msdc_send_cmd(host, &cmd);
+ if (!err)
+ err = msdc_wait_cmd_done(host, &cmd);
+
+ if (err == MMC_ERR_NONE)
+ *status = cmd.resp[0];
+
+ return err;
+}
+
+int msdc_abort_handler(struct mmc_host *host, int abort_card)
+{
+ struct mmc_command stop;
+ u32 status = 0;
+ u32 state = 0;
+
+ while (state != 4) { // until status to "tran"
+ msdc_abort(host);
+ if (msdc_get_card_status(host, &status)) {
+ dprintf(CRITICAL, "Get card status failed\n");
+ return 1;
+ }
+ state = R1_CURRENT_STATE(status);
+ dprintf(INFO, "check card state<%d>\n", state);
+ if (state == 5 || state == 6) {
+ dprintf(INFO, "state<%d> need cmd12 to stop\n", state);
+ if (abort_card) {
+ stop.opcode = MMC_CMD_STOP_TRANSMISSION;
+ stop.rsptyp = RESP_R1B;
+ stop.arg = 0;
+ stop.retries = CMD_RETRIES;
+ stop.timeout = CMD_TIMEOUT;
+ msdc_send_cmd(host, &stop);
+ msdc_wait_cmd_done(host, &stop); // don't tuning
+ } else if (state == 7) { // busy in programing
+ dprintf(INFO, "state<%d> card is busy\n", state);
+ spin(100000);
+ } else if (state != 4) {
+ dprintf(INFO, "state<%d> ??? \n", state);
+ return 1;
+ }
+ }
+ }
+ msdc_abort(host);
+ return 0;
+}
+
+static u32 msdc_intr_wait(struct mmc_host *host, u32 intrs)
+{
+ u32 sts = 0;
+ u32 tmo = UINT_MAX;
+ int ret = 0;
+
+ /* warning that interrupts are not enabled */
+ ret = event_wait_timeout(&msdc_int_event, tmo);
+ if (ret != 0) {
+ addr_t base = host->base;
+ dprintf(CRITICAL, "[%s]: failed to get event INT=0x%x\n",
+ __func__, MSDC_READ32(MSDC_INT));
+ g_int_status = 0;
+ return 0;
+ }
+
+ sts = g_int_status;
+ g_int_status = 0;
+
+ if (~intrs & sts)
+ dprintf(CRITICAL, "[MSDC]<CHECKME> Unexpected INT(0x%x)\n", ~intrs & sts);
+
+ return sts;
+}
+
+static enum handler_return msdc_interrupt_handler(void *arg)
+{
+ struct mmc_host *host = arg;
+ addr_t base = host->base;
+
+ /* Save & Clear the interrupt */
+ g_int_status = MSDC_READ32(MSDC_INT);
+ MSDC_WRITE32(MSDC_INT, g_int_status & host->intr_mask);
+ MSDC_WRITE32(MSDC_INTEN, 0);
+ host->intr_mask = 0;
+
+ /* MUST BE *false*! otherwise, schedule in interrupt */
+ event_signal(&msdc_int_event, false);
+
+ return INT_RESCHEDULE;
+}
+
+static int msdc_send_cmd(struct mmc_host *host, struct mmc_command *cmd)
+{
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+ addr_t base = host->base;
+ u32 opcode = cmd->opcode;
+ u32 rsptyp = cmd->rsptyp;
+ u32 rawcmd;
+ u32 error = MMC_ERR_NONE;
+
+ /* rawcmd :
+ * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
+ * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
+ */
+ rawcmd = (opcode & ~(SD_CMD_BIT | SD_CMD_APP_BIT)) |
+ msdc_rsp[rsptyp] << 7 | host->blklen << 16;
+
+ if (opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+ rawcmd |= ((2 << 11) | (1 << 13));
+ if (priv->autocmd & MSDC_AUTOCMD12) {
+ rawcmd |= (1 << 28);
+ } else if (priv->autocmd & MSDC_AUTOCMD23) {
+ rawcmd |= (2 << 28);
+ }
+ } else if (opcode == MMC_CMD_WRITE_BLOCK || opcode == MMC_CMD50) {
+ rawcmd |= ((1 << 11) | (1 << 13));
+ } else if (opcode == MMC_CMD_READ_MULTIPLE_BLOCK) {
+ rawcmd |= (2 << 11);
+ if (priv->autocmd & MSDC_AUTOCMD12) {
+ rawcmd |= (1 << 28);
+ } else if (priv->autocmd & MSDC_AUTOCMD23) {
+ rawcmd |= (2 << 28);
+ }
+ } else if (opcode == MMC_CMD_READ_SINGLE_BLOCK ||
+ opcode == SD_ACMD_SEND_SCR ||
+ opcode == SD_CMD_SWITCH ||
+ opcode == MMC_CMD_SEND_EXT_CSD ||
+ opcode == MMC_CMD_SEND_WRITE_PROT ||
+ opcode == MMC_CMD_SEND_WRITE_PROT_TYPE ||
+ opcode == MMC_CMD21) {
+ rawcmd |= (1 << 11);
+ } else if (opcode == MMC_CMD_STOP_TRANSMISSION) {
+ rawcmd |= (1 << 14);
+ rawcmd &= ~(0x0FFF << 16);
+ } else if (opcode == SD_IO_RW_EXTENDED) {
+ if (cmd->arg & 0x80000000) /* R/W flag */
+ rawcmd |= (1 << 13);
+ if ((cmd->arg & 0x08000000) && ((cmd->arg & 0x1FF) > 1))
+ rawcmd |= (2 << 11); /* multiple block mode */
+ else
+ rawcmd |= (1 << 11);
+ } else if (opcode == SD_IO_RW_DIRECT) {
+ if ((cmd->arg & 0x80000000) && ((cmd->arg >> 9) & 0x1FFFF))/* I/O abt */
+ rawcmd |= (1 << 14);
+ } else if (opcode == SD_CMD_VOL_SWITCH) {
+ rawcmd |= (1 << 30);
+ } else if (opcode == SD_CMD_SEND_TUNING_BLOCK) {
+ rawcmd |= (1 << 11); /* CHECKME */
+ if (priv->autocmd & MSDC_AUTOCMD19)
+ rawcmd |= (3 << 28);
+ } else if (opcode == MMC_CMD_GO_IRQ_STATE) {
+ rawcmd |= (1 << 15);
+ } else if (opcode == MMC_CMD_WRITE_DAT_UNTIL_STOP) {
+ rawcmd |= ((1<< 13) | (3 << 11));
+ } else if (opcode == MMC_CMD_READ_DAT_UNTIL_STOP) {
+ rawcmd |= (3 << 11);
+ }
+
+ dprintf(INFO, "+[MSDC%d] CMD(%d): ARG(0x%x), RAW(0x%x), BLK_NUM(0x%x) RSP(%d)\n",host->host_id,
+ (opcode & ~(SD_CMD_BIT | SD_CMD_APP_BIT)), cmd->arg, rawcmd,
+ MSDC_READ32(SDC_BLK_NUM), rsptyp);
+
+ while (SDC_IS_CMD_BUSY());
+ if ((rsptyp == RESP_R1B) || (opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK) ||
+ opcode == MMC_CMD_WRITE_BLOCK || opcode == MMC_CMD_READ_MULTIPLE_BLOCK ||
+ opcode == MMC_CMD_READ_SINGLE_BLOCK)
+ while (SDC_IS_BUSY());
+
+ SDC_SEND_CMD(rawcmd, cmd->arg);
+
+end:
+ cmd->error = error;
+
+ return error;
+}
+
+static int msdc_wait_cmd_done(struct mmc_host *host, struct mmc_command *cmd)
+{
+ addr_t base = host->base;
+ u32 rsptyp = cmd->rsptyp;
+ u32 status;
+ u32 opcode = (cmd->opcode & ~(SD_CMD_BIT | SD_CMD_APP_BIT));
+ u32 error = MMC_ERR_NONE;
+ u32 wints = MSDC_INT_CMDTMO | MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR |
+ MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO;
+ u32 *resp = &cmd->resp[0];
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+
+ while (1) {
+ /* Wait for interrupt coming */
+ while (((status = MSDC_READ32(MSDC_INT)) & wints) == 0);
+ MSDC_WRITE32(MSDC_INT, (status & wints));
+ if (~wints & status)
+ dprintf(CRITICAL, "[MSDC]<CHECKME> Unexpected INT(0x%x)\n",
+ ~wints & status);
+
+ if (status & MSDC_INT_CMDRDY)
+ break;
+ else if (status & MSDC_INT_RSPCRCERR) {
+ if (opcode != MMC_CMD21)
+ dprintf(CRITICAL, "[MSDC] cmd%d CRCERR! (0x%x)\n", opcode, status);
+ error = MMC_ERR_BADCRC;
+ goto err;
+ } else if (status & MSDC_INT_CMDTMO) {
+ dprintf(CRITICAL, "[MSDC] cmd%d TMO! (0x%x)\n", opcode, status);
+ error = MMC_ERR_TIMEOUT;
+ goto err;
+ } else if (priv->autocmd & MSDC_AUTOCMD23) {
+ if (status & MSDC_INT_ACMDRDY)
+ /* Autocmd rdy is set prior to cmd rdy */
+ continue;
+ else if (status & MSDC_INT_ACMDCRCERR) {
+ dprintf(CRITICAL, "[MSDC] autocmd23 CRCERR! (0x%x)\n", status);
+ error = MMC_ERR_ACMD_RSPCRC;
+ goto err;
+ } else if (status & MSDC_INT_ACMDTMO) {
+ dprintf(CRITICAL, "[MSDC] autocmd23 TMO! (0x%x)\n", status);
+ error = MMC_ERR_ACMD_TIMEOUT;
+ goto err;
+ }
+ } else {
+ dprintf(CRITICAL, "[MSDC] cmd%d UNEXPECT status! (0x%x)\n",
+ opcode, status);
+ error = MMC_ERR_UNEXPECT;
+ goto err;
+ }
+ }
+
+ switch (rsptyp) {
+ case RESP_NONE:
+ dprintf(INFO, "-[MSDC] CMD(%d): RSP(%d)\n",
+ opcode, rsptyp);
+ break;
+ case RESP_R2:
+ *resp++ = MSDC_READ32(SDC_RESP3);
+ *resp++ = MSDC_READ32(SDC_RESP2);
+ *resp++ = MSDC_READ32(SDC_RESP1);
+ *resp++ = MSDC_READ32(SDC_RESP0);
+ dprintf(INFO, "-[MSDC] CMD(%d): RSP(%d) = 0x%x 0x%x 0x%x 0x%x\n",
+ opcode, cmd->rsptyp, cmd->resp[0], cmd->resp[1],
+ cmd->resp[2], cmd->resp[3]);
+ break;
+ default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
+ cmd->resp[0] = MSDC_READ32(SDC_RESP0);
+ dprintf(INFO, "-[MSDC] CMD(%d): RSP(%d) = 0x%x\n",
+ opcode, cmd->rsptyp, cmd->resp[0]);
+ break;
+ }
+
+err:
+ if (rsptyp == RESP_R1B)
+ while ((MSDC_READ32(MSDC_PS) & MSDC_PS_DAT0) != MSDC_PS_DAT0);
+
+ cmd->error = error;
+
+ return error;
+}
+
+int msdc_cmd(struct mmc_host *host, struct mmc_command *cmd)
+{
+ int err;
+
+ err = msdc_send_cmd(host, cmd);
+ if (err != MMC_ERR_NONE)
+ return err;
+
+ err = msdc_wait_cmd_done(host, cmd);
+
+ /*
+ * For CMD21 resp CRC error, sitll need receive data, so MUST not
+ * clear fifo or do host reset
+ */
+ if (err && cmd->opcode != MMC_CMD21) {
+ addr_t base = host->base;
+ u32 tmp = MSDC_READ32(SDC_CMD);
+
+ /* check if data is used by the command or not */
+ if (tmp & SDC_CMD_DTYP) {
+ if (msdc_abort_handler(host, 1)) {
+ dprintf(CRITICAL, "[MSDC] abort failed\n");
+ }
+ }
+
+ if (cmd->opcode == MMC_CMD_APP_CMD ||
+ cmd->opcode == SD_CMD_SEND_IF_COND) {
+ if (err == MMC_ERR_TIMEOUT)
+ return err;
+ }
+
+ err = msdc_tune_cmdrsp(host, cmd);
+ }
+
+ return err;
+}
+
+#ifdef MSDC_USE_DMA_MODE
+static void msdc_flush_membuf(void *buf, u32 len)
+{
+ arch_clean_invalidate_cache_range((addr_t)buf,len);
+}
+
+static int msdc_dma_wait_done(struct mmc_host *host, struct mmc_command *cmd)
+{
+ addr_t base = host->base;
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+ u32 status;
+ u32 error = MMC_ERR_NONE;
+ u32 wints = MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR |
+ MSDC_INT_DXFER_DONE | MSDC_INT_DMAQ_EMPTY |
+ MSDC_INT_ACMDRDY | MSDC_INT_ACMDTMO | MSDC_INT_ACMDCRCERR |
+ MSDC_INT_CMDRDY | MSDC_INT_CMDTMO | MSDC_INT_RSPCRCERR;
+
+ /* Deliver it to irq handler */
+ host->intr_mask = wints;
+
+ do {
+ status = msdc_intr_wait(host, wints);
+
+ if (status & MSDC_INT_XFER_COMPL) {
+ if (mmc_op_multi(cmd->opcode) && (priv->autocmd & MSDC_AUTOCMD12)) {
+ /* acmd rdy should be checked after xfer_done been held */
+ if (status & MSDC_INT_ACMDRDY) {
+ break;
+ } else if (status & MSDC_INT_ACMDTMO) {
+ dprintf(CRITICAL, "[MSDC] ACMD12 timeout(%xh)\n", status);
+ error = MMC_ERR_ACMD_TIMEOUT;
+ goto end;
+ } else if (status & MSDC_INT_ACMDCRCERR) {
+ dprintf(CRITICAL, "[MSDC] ACMD12 CRC error(%xh)\n", status);
+ error = MMC_ERR_ACMD_RSPCRC;
+ goto end;
+ }
+ } else
+ break;
+ }
+
+ if (status == 0 || status & MSDC_INT_DATTMO) {
+ dprintf(CRITICAL, "[MSDC] DMA DAT timeout(%xh)\n", status);
+ error = MMC_ERR_TIMEOUT;
+ goto end;
+ } else if (status & MSDC_INT_DATCRCERR) {
+ if (cmd->opcode != MMC_CMD21)
+ dprintf(CRITICAL, "[MSDC] DMA DAT CRC error(%xh)\n", status);
+ error = MMC_ERR_BADCRC;
+ goto end;
+ } else {
+ dprintf(CRITICAL, "[MSDC] Unexpect status(0x%x)\n", status);
+ error = MMC_ERR_UNEXPECT;
+ goto end;
+ }
+ } while (1);
+
+end:
+ if (error)
+ MSDC_RESET();
+
+ return error;
+}
+
+int msdc_dma_transfer(struct mmc_host *host, struct mmc_data *data)
+{
+ addr_t base = host->base;
+ int err;
+ paddr_t pa;
+
+ /* Set dma timeout */
+ msdc_set_timeout(host, data->timeout * 1000000, 0);
+ /* DRAM address */
+#if WITH_KERNEL_VM
+ pa = kvaddr_to_paddr(data->buf);
+#else
+ pa = (paddr_t)(data->buf);
+#endif
+ if (sizeof(pa) > 4)
+ dprintf(INFO, "[MSDC] WARN: 64bit physical address!\n");
+ MSDC_WRITE32(MSDC_DMA_SA, (u32)pa);
+ MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BURSTSZ, MSDC_DMA_BURST_64B);
+ /* BASIC_DMA mode */
+ MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
+ /* This is the last buffer */
+ MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
+ /* Total transfer size */
+ MSDC_WRITE32(MSDC_DMA_LEN, data->blks * host->blklen);
+ /* Set interrupts bit */
+ MSDC_SET_BIT32(MSDC_INTEN,
+ MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR);
+ /* Clean & Invalidate cache */
+ msdc_flush_membuf(data->buf, data->blks * host->blklen);
+ /* Trigger DMA start */
+ MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
+ /* wait DMA transferring done */
+ err = msdc_dma_wait_done(host, data->cmd);
+ msdc_flush_membuf(data->buf, data->blks * host->blklen);
+ if (err) {
+ /*
+ * We do not want print out error logs of CMD21, As it may
+ * let user confused.
+ */
+ if (data->cmd->opcode == MMC_CMD21) {
+ /* reset controller */
+ MSDC_RESET();
+
+ /* clear fifo */
+ MSDC_CLR_FIFO();
+
+ /* make sure txfifo and rxfifo are empty */
+ if (MSDC_TXFIFOCNT() != 0 || MSDC_RXFIFOCNT() != 0) {
+ dprintf(INFO, "[MSDC] Abort: TXFIFO(%d), RXFIFO(%d) != 0\n",
+ MSDC_TXFIFOCNT(), MSDC_RXFIFOCNT());
+ }
+
+ /* clear all interrupts */
+ MSDC_CLR_INT();
+
+ } else {
+ dprintf(CRITICAL, "[MSDC] DMA failed! err(%d)\n", err);
+ if (msdc_abort_handler(host, 1)) {
+ dprintf(CRITICAL, "[MSDC] eMMC cannot back to TRANS mode!\n");
+ return MMC_ERR_FAILED;
+ }
+ }
+ }
+
+ /* Check DMA status and stop DMA transfer */
+ MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
+ while (MSDC_READ32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
+
+ return err;
+}
+
+static int msdc_dma_rw(struct mmc_host *host, u8 *buf, u32 blkaddr, u32 nblks, bool rd)
+{
+ int multi, err;
+ struct mmc_command cmd;
+ struct mmc_data data;
+ addr_t base = host->base;
+
+ ASSERT(nblks <= host->max_phys_segs);
+
+ dprintf(INFO, "[MSDC] %s data %d blks %s 0x%x\n",
+ rd ? "Read" : "Write", nblks, rd ? "from" : "to", blkaddr);
+
+ multi = nblks > 1 ? 1 : 0;
+ /* DMA and block number _MUST_BE_ set prior to issuing command */
+ MSDC_DMA_ON;
+ MSDC_WRITE32(SDC_BLK_NUM, nblks);
+
+ /* send read command */
+ if (rd)
+ cmd.opcode =
+ multi ? MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK;
+ else
+ cmd.opcode = multi ? MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_BLOCK;
+ cmd.arg = blkaddr;
+ cmd.rsptyp = RESP_R1;
+ cmd.retries = 0;
+ cmd.timeout = CMD_TIMEOUT;
+
+ err = msdc_cmd(host, &cmd);
+ if (err != MMC_ERR_NONE)
+ return err;
+
+ data.cmd = &cmd;
+ data.blks = nblks;
+ data.buf = buf;
+ if (rd)
+ data.timeout = 100;
+ else
+ data.timeout = 250;
+
+ err = msdc_dma_transfer(host, &data);
+ MSDC_DMA_OFF;
+
+ return err;
+}
+
+static int msdc_dma_bread(struct mmc_host *host, u8 *dst, u32 src, u32 nblks)
+{
+ return msdc_dma_rw(host, dst, src, nblks, true);
+}
+
+static int msdc_dma_bwrite(struct mmc_host *host, u32 dst, u8 *src, u32 nblks)
+{
+ return msdc_dma_rw(host, src, dst, nblks, false);
+}
+#else
+static int msdc_pio_read_word(struct mmc_host *host, u32 *ptr, u32 size)
+{
+ int err = MMC_ERR_NONE;
+ addr_t base = host->base;
+ u32 ints = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO | MSDC_INT_XFER_COMPL;
+ //u32 timeout = 100000;
+ u32 status;
+ u32 totalsz = size;
+ u8 done = 0;
+ u8 *u8ptr;
+ u32 dcrc=0;
+
+ while (1) {
+ status = MSDC_READ32(MSDC_INT);
+ MSDC_WRITE32(MSDC_INT, status);
+ if (status & ~ints)
+ dprintf(CRITICAL, "[MSDC]<CHECKME> Unexpected INT(0x%x)\n", status);
+ if (status & MSDC_INT_DATCRCERR) {
+ MSDC_GET_FIELD(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc);
+ dprintf(CRITICAL, "[MSDC] DAT CRC error (0x%x), Left:%d/%d bytes, RXFIFO:%d,dcrc:0x%x\n",
+ status, size, totalsz, MSDC_RXFIFOCNT(),dcrc);
+ err = MMC_ERR_BADCRC;
+ break;
+ } else if (status & MSDC_INT_DATTMO) {
+ dprintf(CRITICAL, "[MSDC] DAT TMO error (0x%x), Left: %d/%d bytes, RXFIFO:%d\n",
+ status, size, totalsz, MSDC_RXFIFOCNT());
+ err = MMC_ERR_TIMEOUT;
+ break;
+ } else if (status & MSDC_INT_ACMDCRCERR) {
+ MSDC_GET_FIELD(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc);
+ dprintf(CRITICAL, "[MSDC] AUTOCMD CRC error (0x%x), Left:%d/%d bytes, RXFIFO:%d,dcrc:0x%x\n",
+ status, size, totalsz, MSDC_RXFIFOCNT(),dcrc);
+ err = MMC_ERR_ACMD_RSPCRC;
+ break;
+ } else if (status & MSDC_INT_XFER_COMPL) {
+ done = 1;
+ }
+
+ if (size == 0 && done)
+ break;
+
+ /* Note. RXFIFO count would be aligned to 4-bytes alignment size */
+ if ((size >= MSDC_FIFO_THD) && (MSDC_RXFIFOCNT() >= MSDC_FIFO_THD)) {
+ int left = MSDC_FIFO_THD >> 2;
+ do {
+ *ptr++ = MSDC_FIFO_READ32();
+ } while (--left);
+ size -= MSDC_FIFO_THD;
+ dprintf(INFO, "[MSDC] Read %d bytes, RXFIFOCNT: %d, Left: %d/%d\n",
+ MSDC_FIFO_THD, MSDC_RXFIFOCNT(), size, totalsz);
+ } else if ((size < MSDC_FIFO_THD) && MSDC_RXFIFOCNT() >= size) {
+ while (size) {
+ if (size > 3) {
+ *ptr++ = MSDC_FIFO_READ32();
+ } else {
+ u8ptr = (u8 *)ptr;
+ while (size --)
+ *u8ptr++ = MSDC_FIFO_READ8();
+ }
+ }
+ dprintf(INFO, "[MSDC] Read left bytes, RXFIFOCNT: %d, Left: %d/%d\n",
+ MSDC_RXFIFOCNT(), size, totalsz);
+ }
+ }
+
+ return err;
+}
+
+static int msdc_pio_read(struct mmc_host *host, u32 *ptr, u32 size)
+{
+ int err = msdc_pio_read_word(host, (u32 *)ptr, size);
+
+ if (err != MMC_ERR_NONE) {
+ msdc_abort(host); /* reset internal fifo and state machine */
+ dprintf(CRITICAL, "[MSDC] %d-bit PIO Read Error (%d)\n", 32, err);
+ }
+
+ return err;
+}
+
+static int msdc_pio_write_word(struct mmc_host *host, u32 *ptr, u32 size)
+{
+ int err = MMC_ERR_NONE;
+ addr_t base = host->base;
+ u32 ints = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO | MSDC_INT_XFER_COMPL;
+ //u32 timeout = 250000;
+ u32 status;
+ u8 *u8ptr;
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+
+ while (1) {
+ status = MSDC_READ32(MSDC_INT);
+ MSDC_WRITE32(MSDC_INT, status);
+ if (status & ~ints) {
+ dprintf(CRITICAL, "[MSDC]<CHECKME> Unexpected INT(0x%x)\n", status);
+ }
+ if (status & MSDC_INT_DATCRCERR) {
+ dprintf(CRITICAL, "[MSDC] DAT CRC error (0x%x), Left DAT: %d bytes\n",
+ status, size);
+ err = MMC_ERR_BADCRC;
+ break;
+ } else if (status & MSDC_INT_DATTMO) {
+ dprintf(CRITICAL, "[MSDC] DAT TMO error (0x%x), Left DAT: %d bytes, MSDC_FIFOCS=%xh\n",
+ status, size, MSDC_READ32(MSDC_FIFOCS));
+ err = MMC_ERR_TIMEOUT;
+ break;
+ } else if (status & MSDC_INT_ACMDCRCERR) {
+ dprintf(CRITICAL, "[MSDC] AUTO CMD CRC error (0x%x), Left DAT: %d bytes\n",
+ status, size);
+ err = MMC_ERR_ACMD_RSPCRC;
+ break;
+ } else if (status & MSDC_INT_XFER_COMPL) {
+ if (size == 0) {
+ dprintf(INFO, "[MSDC] all data flushed to card\n");
+ break;
+ } else
+ dprintf(INFO, "[MSDC]<CHECKME> XFER_COMPL before all data written\n");
+ }
+
+ if (size == 0)
+ continue;
+
+ if (size >= MSDC_FIFO_SZ) {
+ if (MSDC_TXFIFOCNT() == 0) {
+ int left = MSDC_FIFO_SZ >> 2;
+ do {
+ MSDC_FIFO_WRITE32(*ptr);
+ ptr++;
+ } while (--left);
+ size -= MSDC_FIFO_SZ;
+ }
+ } else if (size < MSDC_FIFO_SZ && MSDC_TXFIFOCNT() == 0) {
+ while (size ) {
+ if (size > 3) {
+ MSDC_FIFO_WRITE32(*ptr);
+ ptr++;
+ size -= 4;
+ } else {
+ u8ptr = (u8 *)ptr;
+ while (size --) {
+ MSDC_FIFO_WRITE8(*u8ptr);
+ u8ptr++;
+ }
+ }
+ }
+ }
+ }
+
+ return err;
+}
+
+static int msdc_pio_write(struct mmc_host *host, u32 *ptr, u32 size)
+{
+ int err = msdc_pio_write_word(host, (u32 *)ptr, size);
+
+ if (err != MMC_ERR_NONE) {
+ msdc_abort(host); /* reset internal fifo and state machine */
+ dprintf(CRITICAL, "[MSDC] PIO Write Error (%d)\n", err);
+ }
+
+ return err;
+}
+
+static int msdc_pio_bread(struct mmc_host *host, u8 *dst, u32 src, u32 nblks)
+{
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+ addr_t base = host->base;
+ u32 blksz = host->blklen;
+ int err = MMC_ERR_NONE, derr = MMC_ERR_NONE;
+ int multi;
+ struct mmc_command cmd;
+ struct mmc_command stop;
+ u32 *ptr = (u32 *)dst;
+
+ dprintf(INFO, "[MSDC] Read data %d bytes from 0x%x\n", nblks * blksz, src);
+
+ multi = nblks > 1 ? 1 : 0;
+
+ MSDC_CLR_FIFO();
+ MSDC_WRITE32(SDC_BLK_NUM, nblks);
+ msdc_set_timeout(host, 100000000, 0);
+
+ /* send read command */
+ cmd.opcode = multi ? MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK;
+ cmd.rsptyp = RESP_R1;
+ cmd.arg = src;
+ cmd.retries = 0;
+ cmd.timeout = CMD_TIMEOUT;
+ err = msdc_cmd(host, &cmd);
+
+ if (err != MMC_ERR_NONE)
+ goto done;
+
+ err = derr = msdc_pio_read(host, (u32 *)ptr, nblks * blksz);
+
+done:
+ if (err != MMC_ERR_NONE) {
+ if (derr != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[MSDC] Read data error (%d)\n", derr);
+ if (msdc_abort_handler(host, 1))
+ dprintf(CRITICAL, "[MSDC] abort failed\n");
+ } else {
+ dprintf(CRITICAL, "[MSDC] Read error (%d)\n", err);
+ }
+ }
+ return (derr == MMC_ERR_NONE) ? err : derr;
+}
+
+static int msdc_pio_bwrite(struct mmc_host *host, u32 dst, u8 *src, u32 nblks)
+{
+ msdc_priv_t *priv = (msdc_priv_t *)host->priv;
+ addr_t base = host->base;
+ int err = MMC_ERR_NONE, derr = MMC_ERR_NONE;
+ int multi;
+ u32 blksz = host->blklen;
+ struct mmc_command cmd;
+ struct mmc_command stop;
+ u32 *ptr = (u32 *)src;
+
+ dprintf(CRITICAL, "[MSDC] Write data %d bytes to 0x%x\n", nblks * blksz, dst);
+
+ multi = nblks > 1 ? 1 : 0;
+
+ MSDC_CLR_FIFO();
+ MSDC_WRITE32(SDC_BLK_NUM, nblks);
+
+ /* No need since MSDC always waits 8 cycles for write data timeout */
+
+ /* send write command */
+ cmd.opcode = multi ? MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_BLOCK;
+ cmd.rsptyp = RESP_R1;
+ cmd.arg = dst;
+ cmd.retries = 0;
+ cmd.timeout = CMD_TIMEOUT;
+ err = msdc_cmd(host, &cmd);
+
+ if (err != MMC_ERR_NONE)
+ goto done;
+
+ err = derr = msdc_pio_write(host, (u32 *)ptr, nblks * blksz);
+
+done:
+ if (err != MMC_ERR_NONE) {
+ if (derr != MMC_ERR_NONE) {
+ dprintf(CRITICAL, "[MSDC] Write data error (%d)\n", derr);
+ if (msdc_abort_handler(host, 1))
+ dprintf(CRITICAL, "[MSDC] abort failed\n");
+ } else {
+ dprintf(CRITICAL, "[MSDC] Write error (%d)\n", err);
+ }
+ }
+ return (derr == MMC_ERR_NONE) ? err : derr;
+}
+#endif
+
+
+static void msdc_config_clksrc(struct mmc_host *host, u32 clksrc, u32 hclksrc)
+{
+ // modify the clock
+ ASSERT(host);
+ /*
+ * For MT2712, MSDC0 use 400Mhz(MSDCPLL) source clock
+ */
+ host->clksrc = clksrc;
+ host->hclksrc = hclksrc;
+#ifndef FPGA_PLATFORM
+ if (host->host_id == 0)
+ host->clk = 400 * 1000 * 1000;
+ else
+ host->clk = 200 * 1000 * 1000;
+#else
+ host->clk = MSDC_OP_SCLK;
+#endif
+
+ /* Chaotian, may need update this part of code */
+ dprintf(INFO, "[info][%s] pll_clk %u (%uMHz), pll_hclk %u\n",
+ __func__, host->clksrc, host->clk/1000000, host->hclksrc);
+}
+
+void msdc_reset_timing_register(struct mmc_host *host)
+{
+ addr_t base = host->base;
+
+ MSDC_WRITE32(MSDC_IOCON, 0x00000000);
+ MSDC_WRITE32(MSDC_DAT_RDDLY0, 0x00000000);
+ MSDC_WRITE32(MSDC_DAT_RDDLY1, 0x00000000);
+ MSDC_WRITE32(MSDC_DAT_RDDLY2, 0x00000000);
+ MSDC_WRITE32(MSDC_DAT_RDDLY3, 0x00000000);
+ MSDC_WRITE32(MSDC_PATCH_BIT0, MSDC_PB0_DEFAULT);
+ MSDC_WRITE32(MSDC_PATCH_BIT1, MSDC_PB1_DEFAULT);
+ MSDC_WRITE32(MSDC_PATCH_BIT2, MSDC_PB2_DEFAULT);
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ /* DE comment: clear SDC_FIFO_CFG[24:25] can make
+ * tune(modify EMMC_TOP_CONTROL & EMMC_TOP_CMD) better
+ */
+ MSDC_SET_FIELD(SDC_FIFO_CFG, SDC_FIFO_CFG_WR_VALID_SEL, 0);
+ MSDC_SET_FIELD(SDC_FIFO_CFG, SDC_FIFO_CFG_RD_VALID_SEL, 0);
+#endif
+ MSDC_WRITE32(MSDC_PAD_TUNE0, 0);
+ MSDC_WRITE32(MSDC_PAD_TUNE1, 0);
+}
+
+void msdc_init_tune_path(struct mmc_host *host, int hs400)
+{
+ addr_t base = host->base;
+
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_RESPWAITCNT, 3);
+
+ MSDC_CLR_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_RXDLYSEL);
+
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_DDLSEL);
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL_SEL);
+
+ #if !defined(FPGA_PLATFORM)
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL);
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL_SEL);
+ #else
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL);
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL);
+ #endif
+
+ if (hs400) {
+ MSDC_CLR_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
+ MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL);
+ } else
+ {
+ MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
+ MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL);
+ }
+
+ if (hs400)
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
+ else
+ MSDC_SET_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
+
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_W_D_SMPL_SEL);
+
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGRESP);
+ MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL);
+ MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRRDLY2SEL);
+
+ if (host->host_id != 1)
+ MSDC_CLR_BIT32(EMMC50_CFG0, MSDC_EMMC50_CFG_CMD_RESP_SEL);
+
+ MSDC_SET_FIELD(MSDC_PATCH_BIT1, MSDC_PB0_CKGEN_MSDC_DLY_SEL, 0);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT1, MSDC_PB1_CMD_RSP_TA_CNTR,
+ CMD_RSP_TA_CNTR_DEFAULT);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT1, MSDC_PB1_WRDAT_CRCS_TA_CNTR,
+ WRDAT_CRCS_TA_CNTR_DEFAULT);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT1, MSDC_PB1_GET_BUSY_MA,
+ BUSY_MA_DEFAULT);
+
+ #if !defined(FPGA_PLATFORM)
+ if (hs400) {
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CRCSTSENSEL,
+ CRCSTSENSEL_HS400_DEFAULT);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_RESPSTENSEL,
+ RESPSTENSEL_HS400_DEFAULT);
+ } else
+ {
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CRCSTSENSEL,
+ CRCSTSENSEL_HS_DEFAULT);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_RESPSTENSEL,
+ RESPSTENSEL_HS_DEFAULT);
+ }
+ #else
+ if (!hs400) {
+ MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CRCSTSENSEL,
+ CRCSTSENSEL_FPGA_DEFAULT);
+ }
+ #endif
+
+ MSDC_SET_BIT32(MSDC_PATCH_BIT1, MSDC_PB1_DDR_CMD_FIX_SEL);
+
+ /* DDR50 mode */
+ MSDC_SET_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_DDR50_SEL);
+ /* set SDC_RX_ENHANCE_EN for async-fifo RX tune */
+ if (!host->base_top)
+ MSDC_SET_FIELD(SDC_ADV_CFG0, SDC_ADV_CFG0_SDC_RX_ENH_EN, 1);
+ else
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, SDC_RX_ENH_EN, 1);
+}
+
+void msdc_config_clock(struct mmc_host *host, int state, u32 hz)
+{
+ msdc_priv_t *priv = host->priv;
+ addr_t base = host->base;
+ u32 mode = 0;
+ u32 div;
+ u32 sclk;
+ u32 u4buswidth=0;
+
+ if (hz >= host->f_max) {
+ hz = host->f_max;
+ } else if (hz < host->f_min) {
+ hz = host->f_min;
+ }
+
+ msdc_config_clksrc(host, host->clksrc, host->hclksrc);
+ MSDC_CLR_BIT32(MSDC_CFG, MSDC_CFG_CKMOD_HS400);
+ MSDC_SET_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
+
+ if (state & MMC_STATE_HS400) {
+ mode = 0x3;
+ div = 0; /* we let hs400 mode fixed at 200Mhz */
+ sclk = host->clk >> 1;
+ MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_CKMOD_HS400);
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
+ } else if (state&MMC_STATE_DDR) {
+ mode = 0x2; /* ddr mode and use divisor */
+ if (hz >= (host->clk >> 2)) {
+ div = 0; /* mean div = 1/2 */
+ sclk = host->clk >> 2; /* sclk = clk/div/2. 2: internal divisor */
+ } else {
+ div = (host->clk + ((hz << 2) - 1)) / (hz << 2);
+ sclk = (host->clk >> 2) / div;
+ div = (div >> 1); /* since there is 1/2 internal divisor */
+ }
+ } else if (hz >= host->clk) {
+ mode = 0x1; /* no divisor and divisor is ignored */
+ div = 0;
+ sclk = host->clk;
+ } else {
+ mode = 0x0; /* use divisor */
+ if (hz >= (host->clk >> 1)) {
+ div = 0; /* mean div = 1/2 */
+ sclk = host->clk >> 1; /* sclk = clk / 2 */
+ } else {
+ div = (host->clk + ((hz << 2) - 1)) / (hz << 2);
+ sclk = (host->clk >> 2) / div;
+ }
+ }
+ host->sclk = sclk;
+
+ /* set clock mode and divisor */
+ MSDC_SET_FIELD(MSDC_CFG, (MSDC_CFG_CKMOD |MSDC_CFG_CKDIV),\
+ (mode << 12) | div);
+ /* wait clock stable */
+ while (!(MSDC_READ32(MSDC_CFG) & MSDC_CFG_CKSTB)) {}
+
+ if (state & MMC_STATE_HS400) {
+ msdc_set_smpl(host, 1, priv->rsmpl, TYPE_CMD_RESP_EDGE);
+ msdc_set_smpl(host, 1, priv->rdsmpl, TYPE_READ_DATA_EDGE);
+ msdc_set_smpl(host, 1, priv->wdsmpl, TYPE_WRITE_CRC_EDGE);
+ } else {
+ #if !defined(FPGA_PLATFORM)
+ msdc_set_smpl(host, 0, priv->rsmpl, TYPE_CMD_RESP_EDGE);
+ #else
+ if (hz < 1000000)
+ msdc_set_smpl(host, 0, MSDC_SMPL_RISING, TYPE_CMD_RESP_EDGE);
+ else
+ msdc_set_smpl(host, 0, priv->rsmpl, TYPE_CMD_RESP_EDGE);
+ #endif
+
+ #if !defined(FPGA_PLATFORM)
+ msdc_set_smpl(host, 0, priv->rdsmpl, TYPE_READ_DATA_EDGE);
+ #else
+ if (hz < 1000000)
+ msdc_set_smpl(host, 0, MSDC_SMPL_RISING, TYPE_READ_DATA_EDGE);
+ //msdc_set_smpl(host, 0, MSDC_SMPL_FALLING, TYPE_READ_DATA_EDGE);
+ else
+ msdc_set_smpl(host, 0, MSDC_SMPL_RISING, TYPE_READ_DATA_EDGE);
+ //msdc_set_smpl(host, 0, MSDC_SMPL_FALLING, TYPE_READ_DATA_EDGE);
+ #endif
+
+ msdc_set_smpl(host, 0, priv->wdsmpl, TYPE_WRITE_CRC_EDGE);
+ }
+
+ if (mode==2 || mode==3) {
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL);
+ } else {
+ MSDC_SET_BIT32(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL);
+ }
+ if (mode == 2) {
+ MSDC_SET_BIT32(MSDC_IOCON, MSDC_IOCON_DDR50CKD);
+ } else {
+ MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_DDR50CKD);
+ }
+
+ msdc_init_tune_path(host, (mode ==3) ? 1 : 0);
+
+ MSDC_GET_FIELD(SDC_CFG,SDC_CFG_BUSWIDTH,u4buswidth);
+
+ dprintf(INFO,
+ "[MSDC] SET_CLK(%dkHz): SCLK(%dkHz) MODE(%d) DIV(%d) DS(%d) RS(%d) buswidth(%s)\n",
+ hz/1000, sclk/1000, mode, div, msdc_cap[host->host_id].data_edge,
+ msdc_cap[host->host_id].cmd_edge,
+ (u4buswidth == 0) ?
+ "1-bit" : (u4buswidth == 1) ?
+ "4-bits" : (u4buswidth == 2) ?
+ "8-bits" : "undefined");
+}
+
+void msdc_config_bus(struct mmc_host *host, u32 width)
+{
+ u32 val,mode, div;
+ addr_t base = host->base;
+
+ val = (width == HOST_BUS_WIDTH_8) ? 2 :
+ (width == HOST_BUS_WIDTH_4) ? 1 : 0;
+
+ MSDC_SET_FIELD(SDC_CFG, SDC_CFG_BUSWIDTH, val);
+ MSDC_GET_FIELD(MSDC_CFG,MSDC_CFG_CKMOD,mode);
+ MSDC_GET_FIELD(MSDC_CFG,MSDC_CFG_CKDIV,div);
+
+ dprintf(INFO, "CLK (%dMHz), SCLK(%dkHz) MODE(%d) DIV(%d) buswidth(%u-bits)\n",
+ host->clk/1000000, host->sclk/1000, mode, div, width);
+}
+
+static void msdc_config_pin(struct mmc_host *host, int mode)
+{
+ dprintf(INFO, "[MSDC] Pins mode(%d), none(0), down(1), up(2), keep(3)\n", mode);
+
+ switch (mode) {
+ case MSDC_PIN_PULL_UP:
+ msdc_pin_set(host, MSDC_PIN_PULL_UP, MSDC_10KOHM);
+ break;
+ case MSDC_PIN_PULL_DOWN:
+ msdc_pin_set(host, MSDC_PIN_PULL_DOWN, MSDC_50KOHM);
+ break;
+ case MSDC_PIN_PULL_NONE:
+ default:
+ msdc_pin_set(host, MSDC_PIN_PULL_NONE, MSDC_50KOHM);
+ break;
+ }
+}
+
+void msdc_clock(struct mmc_host *host, int on)
+{
+ /* Chaotian, may need update this part of code */
+ dprintf(INFO, "[MSDC] Turn %s %s clock \n", on ? "on" : "off", "host");
+}
+
+static void msdc_host_power(struct mmc_host *host, int on)
+{
+ dprintf(INFO, "[MSDC] Turn %s %s power \n", on ? "on" : "off", "host");
+ return; /* power always on, return directly */
+
+ if (on) {
+ msdc_config_pin(host, MSDC_PIN_PULL_UP);
+ msdc_set_host_pwr(host, 1);
+ msdc_clock(host, 1);
+ } else {
+ msdc_clock(host, 0);
+ msdc_set_host_pwr(host, 0);
+ msdc_config_pin(host, MSDC_PIN_PULL_DOWN);
+ }
+}
+
+static void msdc_card_power(struct mmc_host *host, int on)
+{
+ dprintf(INFO, "[MSDC] Turn %s %s power \n", on ? "on" : "off", "card");
+ return; /* power always on, return directly */
+
+ if (on) {
+ msdc_set_card_pwr(host, 1);
+ } else {
+ msdc_set_card_pwr(host, 0);
+ }
+}
+
+void msdc_power(struct mmc_host *host, u8 mode)
+{
+ if (mode == MMC_POWER_ON || mode == MMC_POWER_UP) {
+ msdc_host_power(host, 1);
+ msdc_card_power(host, 1);
+ } else {
+ msdc_card_power(host, 0);
+ msdc_host_power(host, 0);
+ }
+}
+
+void msdc_reset_tune_counter(struct mmc_host *host)
+{
+ host->time_read = 0;
+}
+
+#ifdef FEATURE_MMC_CM_TUNING
+static int msdc_tune_cmdrsp(struct mmc_host *host, struct mmc_command *cmd)
+{
+ addr_t base = host->base;
+ int result = MMC_ERR_CMDTUNEFAIL;
+ unsigned int orig_rsmpl, cur_rsmpl, rsmpl, orig_clkmode;
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
+ unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly1_sel, cur_dly2_sel;
+ unsigned int orig_dly = 0, cur_dly;
+ unsigned int dly;
+#endif
+ u8 hs400 = 0;
+#if MSDC_TUNE_LOG
+ u32 times = 0;
+#endif
+
+ MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
+ hs400 = (orig_clkmode == 3) ? 1 : 0;
+ MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ if (!host->base_top) {
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRDLY, orig_dly1);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL, orig_dly1_sel);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE1_CMDRDLY2, orig_dly2);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE1_CMDRRDLY2SEL, orig_dly2_sel);
+ } else {
+ MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, orig_dly1);
+ MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL, orig_dly1_sel);
+ MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY2, orig_dly2);
+ MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL, orig_dly2_sel);
+ }
+ orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
+ cur_dly = orig_dly;
+ cur_dly1 = orig_dly1;
+ cur_dly2 = orig_dly2;
+ cur_dly1_sel = orig_dly1_sel;
+ cur_dly2_sel = orig_dly2_sel;
+
+ dly = 0;
+
+ do {
+#endif
+
+ for (rsmpl = 0; rsmpl < 2; rsmpl++) {
+ cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
+ msdc_set_smpl(host, hs400, cur_rsmpl, TYPE_CMD_RESP_EDGE);
+ if (host->sclk <= 400000) {
+ msdc_set_smpl(host, hs400, 0, TYPE_CMD_RESP_EDGE);
+ }
+ if (cmd->opcode != MMC_CMD_STOP_TRANSMISSION) {
+ #if 0 /* ToDo: no SD card for MT2731 now, may need in the future */
+ if (host->app_cmd){
+ host->app_cmd = false;
+ result = msdc_app_cmd(host);
+ host->app_cmd = true;
+ if (result != MMC_ERR_NONE)
+ return MMC_ERR_CMDTUNEFAIL;
+ }
+ #endif
+ result = msdc_send_cmd(host, cmd);
+ if (result == MMC_ERR_TIMEOUT)
+ rsmpl--;
+ if (result != MMC_ERR_NONE && cmd->opcode != MMC_CMD_STOP_TRANSMISSION) {
+ if (cmd->opcode == MMC_CMD_READ_MULTIPLE_BLOCK
+ || cmd->opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK
+ || cmd->opcode == MMC_CMD_READ_SINGLE_BLOCK
+ || cmd->opcode == MMC_CMD_WRITE_BLOCK
+ || cmd->opcode == MMC_CMD_SEND_WRITE_PROT_TYPE)
+ msdc_abort_handler(host,1);
+ continue;
+ }
+ result = msdc_wait_cmd_done(host, cmd);
+ } else if (cmd->opcode == MMC_CMD_STOP_TRANSMISSION) {
+ result = MMC_ERR_NONE;
+ goto Pass;
+ } else
+ result = MMC_ERR_BADCRC;
+
+#if MSDC_TUNE_LOG
+
+ times++;
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ dprintf(INFO, "[SD%d] <TUNE_CMD%d><%d><%s> CMDRRDLY=%d, RSPL=%dh\n",
+ host->host_id, (cmd->opcode & (~(SD_CMD_BIT | SD_CMD_APP_BIT))),
+ times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ orig_dly + dly, cur_rsmpl);
+ dprintf(INFO, "[SD%d] <TUNE_CMD><%d><%s> CMDRRDLY1=%xh, CMDRRDLY1SEL=%x,"
+ " CMDRRDLY2=%xh, CMDRRDLY2SEL=%xh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_dly1, cur_dly1_sel, cur_dly2, cur_dly2_sel);
+
+#else
+ dprintf(INFO, "[SD%d] <TUNE_CMD%d><%d><%s> RSPL=%dh\n",
+ host->host_id, (cmd->opcode & (~(SD_CMD_BIT | SD_CMD_APP_BIT))),
+ times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_rsmpl);
+#endif
+#endif
+
+ if (result == MMC_ERR_NONE) {
+ #if 0 /* ToDo: no SD card for MT2731 now, may need in the future */
+ host->app_cmd = false;
+ #endif
+ goto Pass;
+ }
+
+ if (cmd->opcode == MMC_CMD_READ_MULTIPLE_BLOCK
+ || cmd->opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK
+ || cmd->opcode == MMC_CMD_READ_SINGLE_BLOCK
+ || cmd->opcode == MMC_CMD_WRITE_BLOCK)
+ msdc_abort_handler(host,1);
+ }
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ cur_dly = (orig_dly + dly + 1) % 63;
+ cur_dly1_sel = 1;
+ if (cur_dly < 32) {
+ cur_dly1 = cur_dly;
+ cur_dly2 = 0;
+ cur_dly2_sel = 0;
+ } else {
+ cur_dly1 = 31;
+ cur_dly2 = cur_dly - 31;
+ cur_dly2_sel = 1;
+ }
+
+ if (!host->base_top) {
+ MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRDLY, cur_dly1);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRDLY2, cur_dly2);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRRDLY2SEL, cur_dly2_sel);
+ } else {
+ MSDC_SET_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL);
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, cur_dly1);
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY2, cur_dly2);
+ MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL, cur_dly2_sel);
+ }
+ } while (++dly <= 62);
+#endif
+
+ dprintf(ALWAYS,"msdc tune CMD failed\n");
+ return MMC_ERR_CMDTUNEFAIL;
+Pass:
+ dprintf(ALWAYS,"msdc tune CMD pass\n");
+ return result;
+}
+#endif
+
+#ifdef FEATURE_MMC_RD_TUNING
+int msdc_tune_bread(struct mmc_host *host, u8 *dst, u32 src, u32 nblks)
+{
+ addr_t base = host->base;
+ int result = MMC_ERR_CMDTUNEFAIL;
+ u32 orig_rdsmpl, cur_rdsmpl, rdsmpl, orig_clkmode;
+ unsigned int rdsmpl_end;
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ u32 orig_dly1 = 0, orig_dly1_sel, cur_dly1;
+ u32 orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly1_sel, cur_dly2_sel;
+ u32 orig_dly = 0, cur_dly;
+ u32 dly;
+#endif
+ u32 dcrc = 0;
+ u32 hs400;
+#if MSDC_TUNE_LOG
+ u32 times = 0;
+#endif
+
+ MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
+ hs400 = (orig_clkmode==3) ? 1 : 0;
+ if (orig_clkmode==2 || orig_clkmode==3)
+ rdsmpl_end = 0;
+ else
+ rdsmpl_end = 1;
+
+ MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL, orig_rdsmpl);
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ if (!host->base_top) {
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, orig_dly1);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, orig_dly1_sel);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, orig_dly2);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, orig_dly2_sel);
+ } else {
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, orig_dly1);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, orig_dly1_sel);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, orig_dly2);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, orig_dly2_sel);
+ }
+ orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
+ cur_dly = orig_dly;
+ cur_dly1 = orig_dly1;
+ cur_dly2 = orig_dly2;
+ cur_dly1_sel = orig_dly1_sel;
+ cur_dly2_sel = orig_dly2_sel;
+
+ dly = 0;
+
+ do {
+#endif
+ for (rdsmpl = 0; rdsmpl <= rdsmpl_end; rdsmpl++) {
+
+ cur_rdsmpl = (orig_rdsmpl + rdsmpl) % 2;
+ msdc_set_smpl(host, hs400, cur_rdsmpl, TYPE_READ_DATA_EDGE);
+
+ result = host->blk_read(host, dst, src, nblks);
+ if (result == MMC_ERR_CMDTUNEFAIL || result == MMC_ERR_CMD_RSPCRC || result == MMC_ERR_ACMD_RSPCRC)
+ goto Pass;
+
+ MSDC_GET_FIELD(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc);
+
+#if MSDC_TUNE_LOG
+
+ times++;
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ dprintf(INFO, "[SD%d] <TUNE_READ><%d><%s> DATRRDLY=%d, RSPL=%dh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ orig_dly + dly, cur_rdsmpl);
+ dprintf(INFO, "[SD%d] <TUNE_READ><%d><%s> DATRRDLY1=%xh, DATRRDLY1SEL=%x,"
+ " DATRRDLY2=%xh, DATRRDLY2SEL=%xh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_dly1, cur_dly1_sel, cur_dly2, cur_dly2_sel);
+#else
+ dprintf(INFO, "[SD%d] <TUNE_READ><%d><%s>RSPL=%dh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_rdsmpl);
+#endif
+#endif
+
+ if (result == MMC_ERR_NONE && dcrc == 0) {
+ goto Pass;
+ } else {
+ result = MMC_ERR_BADCRC;
+ }
+
+ }
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ cur_dly = (orig_dly + dly + 1) % 63;
+ cur_dly1_sel = 1;
+ if (cur_dly < 32) {
+ cur_dly1 = cur_dly;
+ cur_dly2 = 0;
+ cur_dly2_sel = 0;
+ } else {
+ cur_dly1 = 31;
+ cur_dly2 = cur_dly - 31;
+ cur_dly2_sel = 1;
+ }
+
+ if (!host->base_top) {
+ MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, cur_dly1);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, cur_dly2);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, cur_dly2_sel);
+ } else {
+ MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, cur_dly1);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, cur_dly2);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, cur_dly2_sel);
+ }
+ } while (dly++ <= 62);
+#endif
+
+ dprintf(ALWAYS, "msdc tune bread failed\n");
+ return MMC_ERR_CMDTUNEFAIL;
+Pass:
+ dprintf(ALWAYS, "msdc tune bread Pass\n");
+ return result;
+}
+#define READ_TUNING_MAX_HS (2 * 32)
+#define READ_TUNING_MAX_UHS (2 * 32 * 32)
+#define READ_TUNING_MAX_UHS_CLKMOD1 (2 * 32 * 32 *8)
+
+int msdc_tune_read(struct mmc_host *host)
+{
+ addr_t base = host->base;
+ u32 cur_dsmpl = 0, orig_dsmpl;
+ MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, orig_dsmpl);
+ cur_dsmpl = (orig_dsmpl + 1) ;
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, cur_dsmpl % 2);
+ return 0;
+#if 0
+ addr_t base = host->base;
+ u32 dcrc, ddr = 0, sel = 0;
+ u32 cur_rxdly0 = 0 , cur_rxdly1 = 0;
+ u32 cur_dsmpl = 0, orig_dsmpl;
+ u32 cur_dsel = 0,orig_dsel;
+ u32 cur_dl_cksel = 0,orig_dl_cksel;
+ u32 cur_dat0 = 0, cur_dat1 = 0, cur_dat2 = 0, cur_dat3 = 0, cur_dat4 = 0, cur_dat5 = 0,
+ cur_dat6 = 0, cur_dat7 = 0;
+ u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3, orig_dat4, orig_dat5,
+ orig_dat6, orig_dat7;
+ u32 orig_clkmode;
+ u32 times = 0;
+ int result = MMC_ERR_NONE;
+
+ if (host->sclk > 100000000)
+ sel = 1;
+ if (host->card)
+ ddr = mmc_card_ddr(host->card);
+ MSDC_GET_FIELD(MSDC_CFG,MSDC_CFG_CKMOD,orig_clkmode);
+ //if(orig_clkmode == 1)
+ //MSDC_SET_FIELD(MSDC_PATCH_BIT0, MSDC_CKGEN_RX_SDCLKO_SEL, 0);
+
+ MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_CKGEN_MSDC_DLY_SEL, orig_dsel);
+ MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_INT_DAT_LATCH_CK_SEL, orig_dl_cksel);
+ MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
+
+ /* Tune Method 2. delay each data line */
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
+
+
+ cur_dsmpl = (orig_dsmpl + 1) ;
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl % 2);
+ if (cur_dsmpl >= 2) {
+ MSDC_GET_FIELD(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc);
+ if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
+
+ cur_rxdly0 = MSDC_READ32(MSDC_DAT_RDDLY0);
+ cur_rxdly1 = MSDC_READ32(MSDC_DAT_RDDLY1);
+
+ orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
+ orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
+ orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
+ orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
+ orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
+ orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
+ orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
+ orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
+
+ if (ddr) {
+ cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? (orig_dat0 + 1) : orig_dat0;
+ cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? (orig_dat1 + 1) : orig_dat1;
+ cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? (orig_dat2 + 1) : orig_dat2;
+ cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? (orig_dat3 + 1) : orig_dat3;
+ cur_dat4 = (dcrc & (1 << 4) || dcrc & (1 << 12)) ? (orig_dat4 + 1) : orig_dat4;
+ cur_dat5 = (dcrc & (1 << 5) || dcrc & (1 << 13)) ? (orig_dat5 + 1) : orig_dat5;
+ cur_dat6 = (dcrc & (1 << 6) || dcrc & (1 << 14)) ? (orig_dat6 + 1) : orig_dat6;
+ cur_dat7 = (dcrc & (1 << 7) || dcrc & (1 << 15)) ? (orig_dat7 + 1) : orig_dat7;
+ } else {
+ cur_dat0 = (dcrc & (1 << 0)) ? (orig_dat0 + 1) : orig_dat0;
+ cur_dat1 = (dcrc & (1 << 1)) ? (orig_dat1 + 1) : orig_dat1;
+ cur_dat2 = (dcrc & (1 << 2)) ? (orig_dat2 + 1) : orig_dat2;
+ cur_dat3 = (dcrc & (1 << 3)) ? (orig_dat3 + 1) : orig_dat3;
+ cur_dat4 = (dcrc & (1 << 4)) ? (orig_dat4 + 1) : orig_dat4;
+ cur_dat5 = (dcrc & (1 << 5)) ? (orig_dat5 + 1) : orig_dat5;
+ cur_dat6 = (dcrc & (1 << 6)) ? (orig_dat6 + 1) : orig_dat6;
+ cur_dat7 = (dcrc & (1 << 7)) ? (orig_dat7 + 1) : orig_dat7;
+ }
+
+ cur_rxdly0 = ((cur_dat0 & 0x1F) << 24) | ((cur_dat1 & 0x1F) << 16) |
+ ((cur_dat2 & 0x1F) << 8) | ((cur_dat3 & 0x1F) << 0);
+ cur_rxdly1 = ((cur_dat4 & 0x1F) << 24) | ((cur_dat5 & 0x1F)<< 16) |
+ ((cur_dat6 & 0x1F) << 8) | ((cur_dat7 & 0x1F) << 0);
+
+ MSDC_WRITE32(MSDC_DAT_RDDLY0, cur_rxdly0);
+ MSDC_WRITE32(MSDC_DAT_RDDLY1, cur_rxdly1);
+ }
+ if (cur_dat0 >= 32 || cur_dat1 >= 32 || cur_dat2 >= 32 || cur_dat3 >= 32 ||
+ cur_dat4 >= 32 || cur_dat5 >= 32 || cur_dat6 >= 32 || cur_dat7 >= 32) {
+ if (sel) {
+
+ cur_dsel = (orig_dsel + 1);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT0, MSDC_CKGEN_MSDC_DLY_SEL, cur_dsel % 32);
+
+ }
+ }
+ if (cur_dsel >= 32) {
+ if (orig_clkmode == 1 && sel) {
+
+ cur_dl_cksel = (orig_dl_cksel + 1);
+ MSDC_SET_FIELD(MSDC_PATCH_BIT0, MSDC_INT_DAT_LATCH_CK_SEL, cur_dl_cksel % 8);
+ }
+ }
+ ++(host->time_read);
+ if ((sel == 1 && orig_clkmode == 1 && host->time_read == READ_TUNING_MAX_UHS_CLKMOD1)||
+ (sel == 1 && orig_clkmode != 1 && host->time_read == READ_TUNING_MAX_UHS)||
+ (sel == 0 && orig_clkmode != 1 && host->time_read == READ_TUNING_MAX_HS)) {
+
+ result = MMC_ERR_READTUNEFAIL;
+ }
+
+ return result;
+#endif
+}
+#endif
+
+#ifdef FEATURE_MMC_WR_TUNING
+int msdc_tune_bwrite(struct mmc_host *host, u32 dst, u8 *src, u32 nblks)
+{
+ addr_t base = host->base;
+ int result = MMC_ERR_CMDTUNEFAIL;
+ unsigned int orig_dsmpl, cur_dsmpl, dsmpl, dsmpl_end, orig_clkmode;
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
+ unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly1_sel, cur_dly2_sel;
+ unsigned int orig_dly = 0, cur_dly;
+ unsigned int dly;
+#endif
+ u8 hs400 = 0;
+#if MSDC_TUNE_LOG
+ u32 times = 0;
+#endif
+
+ MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
+ hs400 = (orig_clkmode == 3) ? 1 : 0;
+ if (orig_clkmode==2 || orig_clkmode==3)
+ dsmpl_end = 0;
+ else
+ dsmpl_end = 1;
+
+ if (host->host_id==0) {
+ if (hs400)
+ MSDC_GET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_EDGE, orig_dsmpl);
+ else
+ MSDC_GET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, orig_dsmpl);
+ } else {
+ MSDC_GET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, orig_dsmpl);
+ }
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ if (!host->base_top) {
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, orig_dly1);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, orig_dly1_sel);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, orig_dly2);
+ MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, orig_dly2_sel);
+ } else {
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, orig_dly1);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, orig_dly1_sel);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, orig_dly2);
+ MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, orig_dly2_sel);
+ }
+ orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
+ cur_dly = orig_dly;
+ cur_dly1 = orig_dly1;
+ cur_dly2 = orig_dly2;
+ cur_dly1_sel = orig_dly1_sel;
+ cur_dly2_sel = orig_dly2_sel;
+
+ dly = 0;
+
+ do {
+#endif
+
+ for (dsmpl = 0; dsmpl <= dsmpl_end; dsmpl++) {
+
+ cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
+ msdc_set_smpl(host, hs400, cur_dsmpl, TYPE_WRITE_CRC_EDGE);
+
+ result = host->blk_write(host, dst, src, nblks);
+ if (result == MMC_ERR_CMDTUNEFAIL || result == MMC_ERR_CMD_RSPCRC || result == MMC_ERR_ACMD_RSPCRC)
+ goto Pass;
+
+#if MSDC_TUNE_LOG
+
+ times++;
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ dprintf(INFO, "[SD%d] <TUNE_WRITE><%d><%s> DATRRDLY=%d, RDSPL=%dh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ orig_dly + dly, cur_dsmpl);
+ dprintf(INFO, "[SD%d] <TUNE_WRITE><%d><%s> DATRRDLY1=%xh, DATRRDLY1SEL=%x,"
+ " DATRRDLY2=%xh, DATRRDLY2SEL=%xh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_dly1, cur_dly1_sel, cur_dly2, cur_dly2_sel);
+#else
+ dprintf(INFO, "[SD%d] <TUNE_WRITE><%d><%s> RDSPL=%dh\n",
+ host->host_id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
+ cur_dsmpl);
+#endif
+#endif
+
+ if (result == MMC_ERR_NONE) {
+ goto Pass;
+ } else {
+ result = MMC_ERR_BADCRC;
+ }
+ }
+
+#ifndef FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+ cur_dly = (orig_dly + dly + 1) % 63;
+ cur_dly1_sel = 1;
+ if (cur_dly < 32) {
+ cur_dly1 = cur_dly;
+ cur_dly2 = 0;
+ cur_dly2_sel = 0;
+ } else {
+ cur_dly1 = 31;
+ cur_dly2 = cur_dly - 31;
+ cur_dly2_sel = 1;
+ }
+
+ if (!host->base_top) {
+ MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, cur_dly1);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, cur_dly2);
+ MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, cur_dly2_sel);
+ } else {
+ MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, cur_dly1);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, cur_dly2);
+ MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, cur_dly2_sel);
+ }
+ } while (dly++ <= 62);
+#endif
+
+ dprintf(ALWAYS, "msdc tune bwrite failed\n");
+ return MMC_ERR_CMDTUNEFAIL;
+Pass:
+ dprintf(ALWAYS, "msdc tune bwrite Pass\n");
+ return result;
+}
+#endif
+
+void msdc_emmc_boot_stop(struct mmc_host *host)
+{
+ addr_t base = host->base;
+ u32 count = 0;
+
+ /* Step5. stop the boot mode */
+ MSDC_WRITE32(SDC_ARG, 0x00000000);
+ MSDC_WRITE32(SDC_CMD, 0x00001000);
+
+ MSDC_SET_FIELD(EMMC_CFG0, EMMC_CFG0_BOOTWDLY, 2);
+ MSDC_SET_BIT32(EMMC_CFG0, EMMC_CFG0_BOOTSTOP);
+ while (MSDC_READ32(EMMC_STS) & EMMC_STS_BOOTUPSTATE) {
+ spin(1000);
+ count++;
+ if (count >= 1000) {
+ dprintf(ALWAYS, "Timeout to wait EMMC to leave boot state!\n");
+ break;
+ }
+ }
+
+ /* Step6. */
+ MSDC_CLR_BIT32(EMMC_CFG0, EMMC_CFG0_BOOTSUPP);
+
+ /* Step7. clear EMMC_STS bits */
+ MSDC_WRITE32(EMMC_STS, MSDC_READ32(EMMC_STS));
+}
+
+int msdc_init(struct mmc_host *host)
+{
+ addr_t base = host->host_id ? MSDC1_BASE: MSDC0_BASE; /* only support MSDC0, MSDC1 */
+ addr_t top_base = host->host_id ? MSDC1_TOP_BASE: MSDC0_TOP_BASE; /* only support MSDC0, MSDC1 */
+ msdc_priv_t *priv;
+
+ dprintf(INFO, "[%s]: Host controller intialization start \n", __func__);
+
+ priv = &msdc_priv;
+ memset(priv, 0, sizeof(msdc_priv_t));
+
+ host->base = base;
+ host->base_top = top_base;
+
+ host->clksrc = msdc_cap[host->host_id].clk_src;
+ host->hclksrc= msdc_cap[host->host_id].hclk_src;
+
+ host->f_max = MSDC_MAX_SCLK;
+ host->f_min = MSDC_MIN_SCLK;
+ host->blklen = 0;
+ host->priv = (void *)priv;
+ host->caps = MMC_CAP_MULTIWRITE;
+
+ if (msdc_cap[host->host_id].flags & MSDC_HIGHSPEED)
+ host->caps |= (MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED);
+ if (msdc_cap[host->host_id].flags & MSDC_DDR)
+ host->caps |= MMC_CAP_DDR;
+ if (msdc_cap[host->host_id].data_pins == 4)
+ host->caps |= MMC_CAP_4_BIT_DATA;
+ if (msdc_cap[host->host_id].data_pins == 8)
+ host->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
+ if (msdc_cap[host->host_id].flags & MSDC_HS200)
+ host->caps |= MMC_CAP_EMMC_HS200;
+ if (msdc_cap[host->host_id].flags & MSDC_HS400)
+ host->caps |= MMC_CAP_EMMC_HS400;
+
+ host->ocr_avail = MMC_VDD_32_33; /* TODO: To be customized */
+
+ /* Configure BASIC_DMA + AUTOCMD12 for better R/W performance
+ * NOTE: ACMD23 only support transferring size of up to 32M */
+ priv->autocmd = MSDC_AUTOCMD12;
+ if (priv->autocmd == MSDC_AUTOCMD23)
+ /* The maximal transferring size is size of *[15:0] number of blocks* */
+ host->max_phys_segs = 0xffff;
+ else
+ /* The maximal transferring size is size of DMA_LENGTH */
+ host->max_phys_segs = (UINT_MAX & ~511) >> MMC_BLOCK_BITS_SHFT;
+
+ priv->rdsmpl = msdc_cap[host->host_id].data_edge;
+ priv->wdsmpl = msdc_cap[host->host_id].data_edge;
+ priv->rsmpl = msdc_cap[host->host_id].cmd_edge;
+
+#ifdef MSDC_USE_DMA_MODE
+ host->blk_read = msdc_dma_bread;
+ host->blk_write = msdc_dma_bwrite;
+ dprintf(INFO, "Transfer method: DMA\n");
+#else
+ host->blk_read = msdc_pio_bread;
+ host->blk_write = msdc_pio_bwrite;
+ dprintf(INFO, "Transfer method: PIO\n");
+#endif
+
+ priv->rdsmpl = msdc_cap[host->host_id].data_edge;
+ priv->rsmpl = msdc_cap[host->host_id].cmd_edge;
+
+ /* disable EMMC boot mode */
+ msdc_emmc_boot_stop(host);
+
+ msdc_power(host, MMC_POWER_OFF);
+ msdc_power(host, MMC_POWER_ON);
+
+ if (host->host_id == 1)
+ sd_card_vccq_on();
+
+ /* set to SD/MMC mode */
+ MSDC_SET_FIELD(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
+ MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_PIO);
+ MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_CKPDN);
+
+ MSDC_RESET();
+ MSDC_CLR_FIFO();
+ MSDC_CLR_INT();
+
+ /* enable SDIO mode. it's must otherwise sdio command failed */
+ MSDC_SET_BIT32(SDC_CFG, SDC_CFG_SDIO);
+
+ /* disable detect SDIO device interupt function */
+ MSDC_CLR_BIT32(SDC_CFG, SDC_CFG_SDIOIDE);
+
+ /* enable wake up events */
+#if defined(MMC_MSDC_DRV_CTP)
+ MSDC_SET_BIT32(SDC_CFG, SDC_CFG_INSWKUP);
+#endif
+
+ /* reset tuning parameter */
+ msdc_reset_timing_register(host);
+
+ msdc_init_tune_path(host, 0);
+
+ /* Disable support 64G */
+ MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_SUPPORT64G);
+
+ /* clear boot mode setting */
+ MSDC_WRITE32(EMMC_CFG0, 0);
+ MSDC_WRITE32(EMMC_STS, 0);
+
+#if !defined(FPGA_PLATFORM)
+ msdc_gpio_and_pad_init(host);
+#endif
+
+ /* set sampling edge */
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, msdc_cap[host->host_id].cmd_edge);
+ MSDC_SET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, msdc_cap[host->host_id].data_edge);
+
+ /* write crc timeout detection */
+ MSDC_SET_FIELD(MSDC_PATCH_BIT0, 1 << 30, 1);
+
+#if defined(MMC_MSDC_DRV_CTP)
+#if (MSDC_USE_FORCE_FLUSH || MSDC_USE_RELIABLE_WRITE || MSDC_USE_DATA_TAG || MSDC_USE_PACKED_CMD)
+ MSDC_SET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_BLKNUM_SEL, 0);
+#else
+ MSDC_SET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_BLKNUM_SEL, 1);
+#endif
+#endif
+
+ msdc_set_startbit(host, START_AT_RISING);
+
+ msdc_config_bus(host, HOST_BUS_WIDTH_1);
+ msdc_config_clock(host, 0, MSDC_MIN_SCLK);
+
+ msdc_set_timeout(host, 100000000, 0);
+
+ /* disable SDIO func */
+ MSDC_SET_FIELD(SDC_CFG, SDC_CFG_SDIO, 0);
+ MSDC_SET_FIELD(SDC_CFG, SDC_CFG_SDIOIDE, 0);
+ MSDC_SET_FIELD(SDC_CFG, SDC_CFG_INSWKUP, 0);
+
+ /* Clear all interrupts first */
+ MSDC_CLR_INT();
+ MSDC_WRITE32(MSDC_INTEN, 0);
+
+#ifdef MSDC_USE_DMA_MODE
+ /* Register msdc irq */
+ mt_irq_set_sens(MSDC0_IRQ_BIT_ID + host->host_id, LEVEL_SENSITIVE);
+ mt_irq_set_polarity(MSDC0_IRQ_BIT_ID + host->host_id, MT65xx_POLARITY_LOW);
+ event_init(&msdc_int_event, false, EVENT_FLAG_AUTOUNSIGNAL);
+ register_int_handler(MSDC0_IRQ_BIT_ID + host->host_id, msdc_interrupt_handler, host);
+ unmask_interrupt(MSDC0_IRQ_BIT_ID + host->host_id);
+#endif
+
+ dprintf(INFO, "[%s]: Host controller intialization done\n", __func__);
+ return 0;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/mmc/rules.mk b/src/bsp/lk/platform/mt2731/drivers/mmc/rules.mk
new file mode 100644
index 0000000..44a804b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/mmc/rules.mk
@@ -0,0 +1,14 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+MODULE := $(LOCAL_DIR)
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/msdc.c \
+ $(LOCAL_DIR)/mmc_core.c \
+ $(LOCAL_DIR)/mmc_rpmb.c \
+
+MODULE_DEPS += \
+ lib/bio \
+ lib/partition \
+ lib/rpmb \
+
+include make/module.mk
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.c b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.c
new file mode 100644
index 0000000..fbf9dc6
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.c
@@ -0,0 +1,2724 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include <arch/ops.h>
+#include <debug.h>
+#include <dev/udc.h>
+#include <errno.h>
+#include <kernel/thread.h>
+#include <platform/interrupts.h>
+#include <platform/mt_irq.h>
+#include <platform/timer.h>
+#include <platform/udc-common.h>
+#include <reg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "mt_usb.h"
+
+#ifdef SUPPORT_QMU
+#include "mt_usb_qmu.h"
+#endif
+
+//TODO
+#define MACH_FPGA
+#ifndef MACH_FPGA
+#define DBG_PHY_CALIBRATION 1
+#endif
+
+#if CFG_FPGA_PLATFORM
+#include "usb_i2c.h"
+#include "phy-a60810.h"
+#endif
+
+#define USB_DOUBLE_BUF
+
+#define USB_GINTR
+
+#ifdef USB_DEBUG
+/* DEBUG INFO Sections */
+#define DBG_USB_DUMP_DESC 0
+#define DBG_USB_DUMP_DATA 0
+#define DBG_USB_DUMP_SETUP 1
+#define DBG_USB_FIFO 0
+#define DBG_USB_GENERAL 1
+#define DBG_PHY_CALIBRATION 0
+#endif
+
+#define DBG_C(x...) dprintf(CRITICAL, x)
+#define DBG_I(x...) dprintf(INFO, x)
+#define DBG_S(x...) dprintf(SPEW, x)
+
+#if DBG_USB_GENERAL
+#define DBG_IRQ(x...) dprintf(INFO, x)
+#else
+#define DBG_IRQ(x...) do{} while(0)
+#endif
+
+/* bits used in all the endpoint status registers */
+#define EPT_TX(n) (1 << ((n) + 16))
+#define EPT_RX(n) (1 << (n))
+
+/* udc.h wrapper for usbdcore */
+
+static unsigned char usb_config_value = 0;
+EP0_STATE ep0_state = EP0_IDLE;
+int set_address = 0;
+u32 fifo_addr = FIFO_ADDR_START;
+
+#define EP0 0
+
+#define EP0_MAX_PACKET_SIZE 64
+
+/* Request types */
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+/* values used in GET_STATUS requests */
+#define USB_STAT_SELFPOWERED 0x01
+
+/* USB recipients */
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+
+/* Endpoints */
+#define USB_EP_NUM_MASK 0x0f /* in bEndpointAddress */
+#define USB_EP_DIR_MASK 0x80
+
+#define USB_TYPE_MASK 0x60
+#define USB_RECIP_MASK 0x1f
+
+#define URB_BUF_SIZE 512
+
+#ifndef writew
+#define writew(v, a) (*REG16(a) = (v))
+#endif
+#ifndef readw
+#define readw(a) (*REG16(a))
+#endif
+
+static struct udc_endpoint *ep0in, *ep0out;
+static struct udc_request *ep0req;
+/*static unsigned char ep0_buf[4096] __attribute__((aligned(32)));*/
+
+struct urb mt_ep0_urb;
+struct urb mt_tx_urb;
+struct urb mt_rx_urb;
+struct urb *ep0_urb = &mt_ep0_urb;
+struct urb *tx_urb = &mt_tx_urb;
+struct urb *rx_urb = &mt_rx_urb;
+
+static int usb_online = 0;
+
+static u8 dev_address = 0;
+
+static struct udc_device *the_device;
+static struct udc_gadget *the_gadget;
+/* end from hsusb.c */
+
+/* declare ept_complete handle */
+static void handle_ept_complete(struct udc_endpoint *ept);
+
+#if CFG_FPGA_PLATFORM
+#define U2PHYDTM0_2_FORCE_SUSPENDM (0x04)
+void mt_usb_phy_init(void)
+{
+ usb_i2c_v1_init();
+ USBPHY_WRITE8(0x6a, USBPHY_READ8(0x6a)&~U2PHYDTM0_2_FORCE_SUSPENDM);
+ usb_phy_init();
+ spin(800);
+}
+
+void mt_usb_phy_deinit (void)
+{
+ /* no need */
+}
+
+void mt_usb_phy_recover (void)
+{
+ /* no need */
+}
+
+void mt_usb11_phy_savecurrent(void)
+{
+ /* no need */
+}
+
+void Charger_Detect_Init(void)
+{
+ /* no need */
+}
+
+void Charger_Detect_Release(void)
+{
+ /* no need */
+}
+
+#else
+
+void mt_usb_phy_init(void)
+{
+ /*
+ * force_uart_en 1'b0 0x68 26
+ * RG_UART_EN 1'b0 0x6c 16
+ * rg_usb20_gpio_ctl 1'b0 0x20 09
+ * usb20_gpio_mode 1'b0 0x20 08
+
+ * RG_USB20_BC11_SW_EN 1'b0 0x18 23
+ * RG_USB20_INTR_EN 1'b1 0x00 5
+ * RG_SUSPENDM 1'b1 0x68 3
+ * force_suspendm 1'b1 0x68 18
+
+ * RG_VBUSVALID 1 0x6c 5
+ * RG_SESSEND 0 0x6c 4
+ * RG_BVALID 1 0x6c 3
+ * RG_AVALID 1 0x6c 2
+ * RG_IDDIG 1 0x6c 1
+ * force_vbusvalid 1 0x6c 13
+ * force_sessend 1 0x6c 12
+ * force_bvalid 1 0x6c 11
+ * force_avalid 1 0x6c 10
+ * force_iddig 1 0x6c 9
+
+ * force_suspendm 1'b0 0x68 18
+ */
+
+ /* force_uart_en, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 26));
+ /* RG_UART_EN, 1'b0 */
+ USBPHY_CLR32(0x6c, (0x1 << 16));
+ /* rg_usb20_gpio_ctl, 1'b0, usb20_gpio_mode, 1'b0 */
+ USBPHY_CLR32(0x20, ((0x1 << 9) | (0x1 << 8)));
+
+ /* RG_USB20_BC11_SW_EN, 1'b0 */
+ USBPHY_CLR32(0x18, (0x1 << 23));
+
+ /* RG_USB20_INTR_EN, 1'b1 */
+ USBPHY_SET32(0x00, (0x1 << 5));
+
+ /* RG_SUSPENDM, 1'b1 */
+ USBPHY_SET32(0x68, (0x1 << 3));
+
+ /* force_suspendm, 1'b1 */
+ USBPHY_SET32(0x68, (0x1 << 18));
+
+ spin(2000);
+
+ USBPHY_SET32(0x6c, ((0x1 << 5) | (0x1 << 3) | (0x1 << 2) | (0x1 << 1)));
+ USBPHY_CLR32(0x6c, (0x1 << 4));
+
+ USBPHY_SET32(0x6c, ((0x1 << 13) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x1 << 9)));
+
+ spin(2000);
+
+ return;
+}
+
+void mt_usb_phy_deinit(void)
+{
+ /*
+ * RG_VBUSVALID 0
+ * RG_SESSEND 1
+ * RG_BVALID 0
+ * RG_AVALID 0
+ * RG_IDDIG 1
+
+ * Option2:
+ * SSUSB_IP_SW_RST 1
+ * SSUSB_U2_PORT_PHYD_RST 1
+ * delay 1 us
+ * SSUSB_U2_PORT_PHYD_RST 0
+
+ * force_vbusvalid 0
+ * force_sessend 0
+ * force_bvalid 0
+ * force_avalid 0
+ * force_iddig 0
+
+ * RG_SUSPENDM 1'b0
+ * force_suspendm 1'b1
+ */
+
+ USBPHY_SET32(0x6c, ((0x1 << 4) | (0x1 << 1)));
+ USBPHY_CLR32(0x6c, ((0x1 << 5) | (0x1 << 3) | (0x1 << 2)));
+
+ /* SSUSB_U2_PORT_PHYD_RST, 1'b1 */
+ USBPHY_SET32(0x68, (0x1 << 14));
+
+ spin(1);
+
+ /* SSUSB_U2_PORT_PHYD_RST, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 14));
+
+ USBPHY_CLR32(0x6c, ((0x1 << 13) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x1 << 9)));
+
+ /* RG_SUSPENDM, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 3));
+ /* force_suspendm, 1'b1 */
+ USBPHY_SET32(0x68, (0x1 << 18));
+
+ spin(2000);
+
+ return;
+}
+
+void mt_usb_phy_recover(void)
+{
+ /*
+ * 04.force_uart_en 1'b0 0x68 26
+ * 04.RG_UART_EN 1'b0 0x6C 16
+ * 04.rg_usb20_gpio_ctl 1'b0 0x20 09
+ * 04.usb20_gpio_mode 1'b0 0x20 08
+
+ * 05.force_suspendm 1'b0 0x68 18
+
+ * 06.RG_DPPULLDOWN 1'b0 0x68 06
+ * 07.RG_DMPULLDOWN 1'b0 0x68 07
+ * 08.RG_XCVRSEL[1:0] 2'b00 0x68 [04:05]
+ * 09.RG_TERMSEL 1'b0 0x68 02
+ * 10.RG_DATAIN[3:0] 4'b0000 0x68 [10:13]
+ * 11.force_dp_pulldown 1'b0 0x68 20
+ * 12.force_dm_pulldown 1'b0 0x68 21
+ * 13.force_xcversel 1'b0 0x68 19
+ * 14.force_termsel 1'b0 0x68 17
+ * 15.force_datain 1'b0 0x68 23
+ * 16.RG_USB20_BC11_SW_EN 1'b0 0x18 23
+ * 17.RG_USB20_OTG_VBUSCMP_EN 1'b1 0x18 20
+ */
+
+ /* clean PUPD_BIST_EN */
+ /* PUPD_BIST_EN = 1'b0 */
+ /* PMIC will use it to detect charger type */
+ /* NEED?? USBPHY_CLR8(0x1d, 0x10);*/
+ USBPHY_CLR32(0x1c, (0x1 << 12));
+
+ /* force_uart_en, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 26));
+ /* RG_UART_EN, 1'b0 */
+ USBPHY_CLR32(0x6C, (0x1 << 16));
+ /* rg_usb20_gpio_ctl, 1'b0, usb20_gpio_mode, 1'b0 */
+ USBPHY_CLR32(0x20, (0x1 << 9));
+ USBPHY_CLR32(0x20, (0x1 << 8));
+
+ /* force_suspendm, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 18));
+
+ /* RG_DPPULLDOWN, 1'b0, RG_DMPULLDOWN, 1'b0 */
+ USBPHY_CLR32(0x68, ((0x1 << 6) | (0x1 << 7)));
+
+ /* RG_XCVRSEL[1:0], 2'b00. */
+ USBPHY_CLR32(0x68, (0x3 << 4));
+
+ /* RG_TERMSEL, 1'b0 */
+ USBPHY_CLR32(0x68, (0x1 << 2));
+ /* RG_DATAIN[3:0], 4'b0000 */
+ USBPHY_CLR32(0x68, (0xF << 10));
+
+ /* force_dp_pulldown, 1'b0, force_dm_pulldown, 1'b0,
+ * force_xcversel, 1'b0, force_termsel, 1'b0, force_datain, 1'b0
+ */
+ USBPHY_CLR32(0x68, ((0x1 << 20) | (0x1 << 21) | (0x1 << 19) | (0x1 << 17) | (0x1 << 23)));
+
+ /* RG_USB20_BC11_SW_EN, 1'b0 */
+ USBPHY_CLR32(0x18, (0x1 << 23));
+ /* RG_USB20_OTG_VBUSCMP_EN, 1'b1 */
+ USBPHY_SET32(0x18, (0x1 << 20));
+
+ /* RG_USB20_PHY_REV[7:0] = 8'b01000000 */
+ USBPHY_CLR32(0x18, (0xFF << 24));
+ USBPHY_SET32(0x18, (0x40 << 24));
+
+ /* wait 800 usec. */
+ spin(800);
+
+ /* force enter device mode */
+ USBPHY_CLR32(0x6C, (0x10<<0));
+ USBPHY_SET32(0x6C, (0x2F<<0));
+ USBPHY_SET32(0x6C, (0x3F<<8));
+}
+
+void mt_usb11_phy_savecurrent(void)
+{
+#if 0
+ USB11PHY_SET8(0xca, 0x10);
+ USB11PHY_SET8(0xcb, 0x3c);
+ USB11PHY_CLR8(0xc1, 0x08);
+ USB11PHY_CLR8(0xc7, 0x06);
+ USB11PHY_SET8(0xc6, 0x06);
+
+#endif
+}
+
+void Charger_Detect_Init(void)
+{
+ /* RG_USB20_BC11_SW_EN = 1'b1 */
+ USBPHY_SET8(0x1a, 0x80);
+}
+
+void Charger_Detect_Release(void)
+{
+ /* RG_USB20_BC11_SW_EN = 1'b0 */
+ USBPHY_CLR8(0x1a, 0x80);
+}
+#endif
+/* usb phy bring up end */
+
+#if !CFG_FPGA_PLATFORM
+//ALPS00427972, implement the analog register formula
+void mt_usb_phy_calibraion (int case_set, int input_reg)
+{
+#if 0
+ int temp_added=0;
+ int temp_test=0;
+ int temp_mask;
+
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: case_set %d, input_reg = 0x%x \n", __func__, case_set, input_reg);
+#endif
+
+ switch (case_set) {
+ case 1:
+ //case 1
+ //If M_HW_RES3[15:13] !=0
+ //RG_USB20_TERM_VREF_SEL[2:0] <= RG_USB20_TERM_VREF_SEL[2:0] + M_HW_RES3[15:13]
+ temp_mask = 0x07;
+ temp_test = USBPHY_READ8(0x05);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ temp_added = (USBPHY_READ8(0x05)& temp_mask) + input_reg;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+ temp_added &= 0x07;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+
+ USBPHY_CLR8(0x05, temp_mask);
+ USBPHY_SET8(0x05, temp_added);
+
+ temp_test = USBPHY_READ8(0x05);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: final temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ break;
+ case 2:
+ //case 2
+ //If M_HW_RES3[12:10] !=0
+ //RG_USB20_CLKREF_REF[2:0]<= RG_USB20_CLKREF_REF[2:0]+ M_HW_RES3[12:10]
+ temp_mask = 0x07;
+
+ temp_test = USBPHY_READ8(0x07);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ temp_added = (USBPHY_READ8(0x07)& temp_mask) + input_reg;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+ temp_added &= 0x07;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+
+ USBPHY_CLR8(0x07, temp_mask);
+ USBPHY_SET8(0x07, temp_added);
+
+ temp_test = USBPHY_READ8(0x07);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: final temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ break;
+ case 3:
+ //case 3
+ //If M_HW_RES3[9:7] !=0
+ //RG_USB20_VRT_VREF_SEL[2:0]<=RG_USB20_VRT_VREF_SEL[2:0]+ M_HW_RES3[9:7]
+ temp_mask = 0x70;
+
+ temp_test = USBPHY_READ8(0x05);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ temp_added = (USBPHY_READ8(0x05)& temp_mask) >> 4;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+ temp_added += input_reg;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+ temp_added &= 0x07;
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: temp_added = 0x%x \n", __func__, temp_added);
+#endif
+
+ USBPHY_CLR8(0x05, temp_mask);
+ USBPHY_SET8(0x05, temp_added<<4);
+
+ temp_test = USBPHY_READ8(0x05);
+#if DBG_PHY_CALIBRATION
+ DBG_I("%s: final temp_test = 0x%x \n", __func__, temp_test);
+#endif
+ break;
+ }
+#endif
+}
+
+//ALPS00427972, implement the analog register formula
+#endif
+
+void board_usb_init(void)
+{
+ mt_usb_phy_init();
+}
+
+struct udc_descriptor {
+ struct udc_descriptor *next;
+ unsigned short tag; /* ((TYPE << 8) | NUM) */
+ unsigned short len; /* total length */
+ unsigned char data[0];
+};
+
+#if DBG_USB_DUMP_SETUP
+static void dump_setup_packet(const char *str, struct setup_packet *sp)
+{
+ DBG_I("\n");
+ DBG_I(str);
+ DBG_I(" bmRequestType = %x\n", sp->type);
+ DBG_I(" bRequest = %x\n", sp->request);
+ DBG_I(" wValue = %x\n", sp->value);
+ DBG_I(" wIndex = %x\n", sp->index);
+ DBG_I(" wLength = %x\n", sp->length);
+}
+#else
+static void dump_setup_packet(const char *str, struct setup_packet *sp) {}
+#endif
+
+static void copy_desc(struct urb *urb, void *data, int length)
+{
+
+#if DBG_USB_FIFO
+ DBG_I("%s: urb: %x, data %x, length: %d, actual_length: %d\n",
+ __func__, urb->buffer, data, length, urb->actual_length);
+#endif
+
+ //memcpy(urb->buffer + urb->actual_length, data, length);
+ memcpy(urb->buffer, data, length);
+ //urb->actual_length += length;
+ urb->actual_length = length;
+#if DBG_USB_FIFO
+ DBG_I("%s: urb: %x, data %x, length: %d, actual_length: %d\n",
+ __func__, urb, data, length, urb->actual_length);
+#endif
+}
+
+
+struct udc_descriptor *udc_descriptor_alloc(unsigned type, unsigned num,
+ unsigned len)
+{
+ struct udc_descriptor *desc;
+ if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
+ return 0;
+
+ if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
+ return 0;
+
+ desc->next = 0;
+ desc->tag = (type << 8) | num;
+ desc->len = len;
+ desc->data[0] = len;
+ desc->data[1] = type;
+
+ return desc;
+}
+
+static struct udc_descriptor *desc_list = 0;
+static unsigned next_string_id = 1;
+
+void udc_descriptor_register(struct udc_descriptor *desc)
+{
+ desc->next = desc_list;
+ desc_list = desc;
+}
+
+unsigned udc_string_desc_alloc(const char *str)
+{
+ unsigned len;
+ struct udc_descriptor *desc;
+ unsigned char *data;
+
+ if (next_string_id > 255)
+ return 0;
+
+ if (!str)
+ return 0;
+
+ len = strlen(str);
+ desc = udc_descriptor_alloc(TYPE_STRING, next_string_id, len * 2 + 2);
+ if (!desc)
+ return 0;
+ next_string_id++;
+
+ /* expand ascii string to utf16 */
+ data = desc->data + 2;
+ while (len-- > 0) {
+ *data++ = *str++;
+ *data++ = 0;
+ }
+
+ udc_descriptor_register(desc);
+ return desc->tag & 0xff;
+}
+
+static int mt_read_fifo(struct udc_endpoint *endpoint)
+{
+
+ struct urb *urb = endpoint->rcv_urb;
+ int len = 0, count = 0;
+ int ep_num = endpoint->num;
+ int index;
+ unsigned char *cp;
+ u32 *wp;
+#if !CFG_FPGA_PLATFORM
+ u16 dma_cntl = 0;
+#endif
+
+ if (ep_num == EP0)
+ urb = ep0_urb;
+
+ if (urb) {
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+ cp = (u8 *) (urb->buffer + urb->actual_length);
+ wp = (u32 *) cp;
+#if DBG_USB_FIFO
+ DBG_I("%s: ep_num: %d, urb: %x, urb->buffer: %x, urb->actual_length = %d\n",
+ __func__, ep_num, urb, urb->buffer, urb->actual_length);
+#endif
+
+ count = len = readw(IECSR + RXCOUNT);
+ if (ep_num != 0) {
+#if DBG_USB_FIFO
+ DBG_I("%s: ep_num: %d count = %d\n",
+ __func__, ep_num, count);
+#endif
+ }
+
+ /* FIX: DMA has problem write now */
+
+#if !CFG_FPGA_PLATFORM
+ arch_clean_invalidate_cache_range((addr_t) cp, count);
+
+ if (ep_num != 0) {
+ writel((uintptr_t)wp, USB_DMA_ADDR (ep_num));
+ writel(count, USB_DMA_COUNT (ep_num));
+ dma_cntl =
+ USB_DMA_BURST_MODE_3 | (ep_num << USB_DMA_ENDPNT_OFFSET) |
+ USB_DMA_EN;
+ writew(dma_cntl, USB_DMA_CNTL (ep_num));
+ while (readw(USB_DMA_CNTL (ep_num)) & USB_DMA_EN);
+ } else
+
+#endif
+ {
+ while (len > 0) {
+ if (len >= 4) {
+ *wp++ = readl(FIFO(ep_num));
+ cp = (unsigned char *) wp;
+ //DBG_I("USB READ FIFO: wp = %lu, cp = %lu\n", wp, cp);
+ len -= 4;
+ } else {
+ *cp++ = readb(FIFO(ep_num));
+ //DBG_I("USB READ FIFO: wp = %lu, cp = %lu\n", wp, cp);
+ len--;
+ }
+ }
+ }
+
+#if DBG_USB_DUMP_DATA
+ if (ep_num != 0) {
+ DBG_I("%s: &urb->buffer: %x\n", __func__, urb->buffer);
+ DBG_I("[USB] dump data:\n");
+ hexdump8(urb->buffer, count);
+ }
+#endif
+
+ urb->actual_length += count;
+
+ writeb(index, INDEX);
+ }
+
+ return count;
+}
+
+static int mt_write_fifo(struct udc_endpoint *endpoint)
+{
+ struct urb *urb = endpoint->tx_urb;
+ int last = 0, count = 0;
+ int ep_num = endpoint->num;
+ int index;
+ unsigned char *cp = NULL;
+#ifdef USB_TX_DMA_MODE_0
+ u32 *wp;
+ u16 dma_cntl = 0;
+#endif
+
+ if (ep_num == EP0)
+ urb = ep0_urb;
+
+ if (urb) {
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+#if DBG_USB_DUMP_DESC
+ DBG_I("%s: dump desc\n", __func__);
+ hexdump8(urb->buffer, urb->actual_length);
+#endif
+
+
+#if DBG_USB_FIFO
+ DBG_I("%s: ep_num: %d urb: %x, actual_length: %d\n",
+ __func__, ep_num, urb, urb->actual_length);
+ DBG_I("%s: sent: %d, tx_pkt_size: %d\n", __func__, endpoint->sent, endpoint->maxpkt);
+#endif
+
+ count = last = MIN (urb->actual_length - endpoint->sent, endpoint->maxpkt);
+ //count = last = urb->actual_length;
+
+#if DBG_USB_FIFO
+ DBG_I("%s: count: %d\n", __func__, count);
+ DBG_I("%s: urb->actual_length = %d\n", __func__, urb->actual_length);
+ DBG_I("%s: endpoint->sent = %d\n", __func__, endpoint->sent);
+#endif
+
+ if (count < 0) {
+ DBG_C("%s: something is wrong, count < 0", __func__);
+ }
+
+ if (count) {
+ cp = urb->buffer + endpoint->sent;
+#ifdef USB_TX_DMA_MODE_0
+ wp = (u32 *)cp;
+
+ arch_clean_invalidate_cache_range((addr_t) cp, count);
+
+ if (ep_num != 0) {
+ writel(wp, USB_DMA_ADDR(ep_num));
+ writel(count, USB_DMA_COUNT(ep_num));
+ dma_cntl =
+ USB_DMA_BURST_MODE_3 | (ep_num << USB_DMA_ENDPNT_OFFSET) |
+ USB_DMA_EN | USB_DMA_DIR;
+ writew(dma_cntl, USB_DMA_CNTL(ep_num));
+ while (readw(USB_DMA_CNTL (ep_num)) & USB_DMA_EN);
+ } else
+#endif
+ {
+ //DBG("---------write USB fifo---------\n");
+ while (count > 0) {
+ //hexdump8(cp, 1);
+ writeb(*cp, FIFO (ep_num));
+ cp++;
+ count--;
+ }
+ }
+ }
+
+ endpoint->last = last;
+ endpoint->sent += last;
+
+ writeb(index, INDEX);
+ }
+
+ return last;
+}
+
+struct udc_endpoint * mt_find_ep(int ep_num, u8 dir)
+{
+ int i;
+ u8 in = 0;
+
+ /* convert dir to in */
+ if (dir == USB_DIR_IN) /* dir == USB_DIR_IN */
+ in = 1;
+
+ /* for (i = 0; i < udc_device->max_endpoints; i++) */
+ /* for (i = 0; i < the_gadget->ifc_endpoints; i++) */
+ for (i = 0; i < MT_EP_NUM; i++) {
+ if ((ep_list[i].num == ep_num) && (ep_list[i].in == in)) {
+#if DBG_USB_GENERAL
+ DBG_I("%s: find ep!\n", __func__);
+#endif
+ return &ep_list[i];
+ }
+ }
+ return NULL;
+}
+
+static void mt_udc_flush_fifo(u8 ep_num, u8 dir)
+{
+ u16 tmpReg16;
+ u8 index;
+ struct udc_endpoint *endpoint;
+
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+ if (ep_num == 0) {
+ tmpReg16 = readw(IECSR + CSR0);
+ tmpReg16 |= EP0_FLUSH_FIFO;
+ writew(tmpReg16, IECSR + CSR0);
+ writew(tmpReg16, IECSR + CSR0);
+ } else {
+ endpoint = mt_find_ep(ep_num, dir);
+ if (endpoint->in == 0) { /* USB_DIR_OUT */
+ tmpReg16 = readw(IECSR + RXCSR);
+ tmpReg16 |= EPX_RX_FLUSHFIFO;
+ writew(tmpReg16, IECSR + RXCSR);
+ writew(tmpReg16, IECSR + RXCSR);
+ } else {
+ tmpReg16 = readw(IECSR + TXCSR);
+ tmpReg16 |= EPX_TX_FLUSHFIFO;
+ writew(tmpReg16, IECSR + TXCSR);
+ writew(tmpReg16, IECSR + TXCSR);
+ }
+ }
+
+ /* recover index register */
+ writeb(index, INDEX);
+}
+
+/* the endpoint does not support the received command, stall it!! */
+static void udc_stall_ep(unsigned int ep_num, u8 dir)
+{
+ struct udc_endpoint *endpoint = mt_find_ep(ep_num, dir);
+ u8 index;
+ u16 csr;
+
+ DBG_C("[USB] %s\n", __func__);
+
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+ if (ep_num == 0) {
+ csr = readw(IECSR + CSR0);
+ csr |= EP0_SENDSTALL;
+ writew(csr, IECSR + CSR0);
+ mt_udc_flush_fifo(ep_num, USB_DIR_OUT);
+ } else {
+ if (endpoint->in == 0) { /* USB_DIR_OUT */
+ csr = readb(IECSR + RXCSR);
+ csr |= EPX_RX_SENDSTALL;
+ writew(csr, IECSR + RXCSR);
+ mt_udc_flush_fifo(ep_num, USB_DIR_OUT);
+ } else {
+ csr = readb(IECSR + TXCSR);
+ csr |= EPX_TX_SENDSTALL;
+ writew(csr, IECSR + TXCSR);
+ mt_udc_flush_fifo(ep_num, USB_DIR_IN);
+ }
+ }
+ //mt_udc_flush_fifo (ep_num, USB_DIR_OUT);
+ //mt_udc_flush_fifo (ep_num, USB_DIR_IN);
+
+ ep0_state = EP0_IDLE;
+
+ writeb(index, INDEX);
+
+ return;
+}
+
+/*
+ * If abnormal DATA transfer happened, like USB unplugged,
+ * we cannot fix this after mt_udc_reset().
+ * Because sometimes there will come reset twice.
+ */
+static void mt_udc_suspend(void)
+{
+ /* handle abnormal DATA transfer if we had any */
+ struct udc_endpoint *endpoint;
+ int i;
+
+ if (!usb_online)
+ return;
+
+ /* deal with flags */
+ usb_online = 0;
+ usb_config_value = 0;
+ the_gadget->notify(the_gadget, UDC_EVENT_OFFLINE);
+
+ /* error out any pending reqs */
+ for (i = 1; i < MT_EP_NUM; i++) {
+ /* ensure that ept_complete considers
+ * this to be an error state
+ */
+#if DBG_USB_GENERAL
+ DBG_I("%s: ep: %i, in: %s, req: %x\n",
+ __func__, ep_list[i].num, ep_list[i].in ? "IN" : "OUT", ep_list[i].req);
+#endif
+ if ((ep_list[i].req && (ep_list[i].in == 0)) || /* USB_DIR_OUT */
+ (ep_list[i].req && (ep_list[i].in == 1))) { /* USB_DIR_IN */
+ ep_list[i].status = -1; /* HALT */
+ endpoint = &ep_list[i];
+ handle_ept_complete(endpoint);
+ }
+ }
+
+ /* this is required for error handling during data transfer */
+ txn_status = -1;
+
+#if defined(SUPPORT_QMU)
+
+ /* stop qmu engine */
+ mu3d_hal_stop_qmu(1, USB_DIR_IN);
+ mu3d_hal_stop_qmu(1, USB_DIR_OUT);
+
+ /* Disable QMU Tx/Rx. */
+#if 0
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, 0x0);
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, 0x0);
+#endif
+ /* do qmu flush */
+ mu3d_hal_flush_qmu(1, USB_DIR_IN);
+ mu3d_hal_flush_qmu(1, USB_DIR_OUT);
+
+ /* mu3d_hal_reset_ep: we do reset here only, do not start qmu here */
+#if 0
+ mu3d_hal_reset_qmu_ep(1, USB_DIR_IN);
+ mu3d_hal_reset_qmu_ep(1, USB_DIR_OUT);
+#endif
+#endif
+}
+
+static void mt_udc_rxtxmap_recover(void)
+{
+ int i;
+
+ for (i = 1; i < MT_EP_NUM; i++) {
+ if (ep_list[i].num != 0) { /* allocated */
+
+ writeb(ep_list[i].num, INDEX);
+
+ if (ep_list[i].in == 0) /* USB_DIR_OUT */
+ writel(ep_list[i].maxpkt, (IECSR + RXMAP));
+ else
+ writel(ep_list[i].maxpkt, (IECSR + TXMAP));
+ }
+ }
+}
+
+static void mt_udc_reset(void)
+{
+
+ /* MUSBHDRC automatically does the following when reset signal is detected */
+ /* 1. Sets FAddr to 0
+ * 2. Sets Index to 0
+ * 3. Flush all endpoint FIFOs
+ * 4. Clears all control/status registers
+ * 5. Enables all endpoint interrupts
+ * 6. Generates a Rest interrupt
+ */
+
+ DBG_I("[USB] %s\n", __func__);
+
+ /* clear DMA0 and enable DMA0 burst */
+ writew(0, (USB_BASE + 0x0204));
+ writew(0x600, (USB_BASE + 0x0204));
+
+ /* disable all endpoint interrupts */
+ writeb(0, INTRTXE);
+ writeb(0, INTRRXE);
+ writeb(0, INTRUSBE);
+
+ writew(SWRST_SWRST | SWRST_DISUSBRESET, SWRST);
+
+ dev_address = 0;
+
+ /* flush FIFO */
+ mt_udc_flush_fifo(0, USB_DIR_OUT);
+ mt_udc_flush_fifo(1, USB_DIR_OUT);
+ mt_udc_flush_fifo(1, USB_DIR_IN);
+ //mt_udc_flush_fifo (2, USB_DIR_IN);
+
+ /* detect USB speed */
+ if (readb(POWER) & PWR_HS_MODE) {
+ DBG_I("[USB] USB High Speed\n");
+// enable_highspeed();
+ } else {
+ DBG_I("[USB] USB Full Speed\n");
+ }
+
+ /* restore RXMAP and TXMAP if the endpoint has been configured */
+ mt_udc_rxtxmap_recover();
+
+#ifdef SUPPORT_QMU
+ {
+ unsigned int wCsr = 0;
+ unsigned int intr_e = 0;
+
+ wCsr |= EPX_TX_DMAREQEN;
+ writew(wCsr, IECSR + TXCSR);
+
+ //turn off intrTx
+ intr_e = readb(INTRTXE);
+ intr_e = intr_e & (~(1<<(1)));
+ writeb(intr_e, INTRTXE);
+
+ wCsr = 0;
+ intr_e = 0;
+
+ wCsr |= EPX_RX_DMAREQEN;
+ writew(wCsr, IECSR + RXCSR);
+
+ //turn off intrRx
+ intr_e = readb(INTRRXE);
+ intr_e = intr_e & (~(1<<(1)));
+ writeb(intr_e, INTRRXE);
+ }
+#endif
+
+ /* enable suspend */
+ writeb((INTRUSB_SUSPEND | INTRUSB_RESUME | INTRUSB_RESET |INTRUSB_DISCON), INTRUSBE);
+ txn_status = 0;
+}
+
+static void mt_udc_ep0_write(void)
+{
+
+ struct udc_endpoint *endpoint = &ep_list[EP0];
+ int count = 0;
+ u16 csr0 = 0;
+ u8 index = 0;
+
+ index = readb(INDEX);
+ writeb(0, INDEX);
+
+ csr0 = readw(IECSR + CSR0);
+ if (csr0 & EP0_TXPKTRDY) {
+ DBG_I("mt_udc_ep0_write: ep0 is not ready to be written\n");
+ return;
+ }
+
+ count = mt_write_fifo(endpoint);
+
+#if DBG_USB_GENERAL
+ DBG_I("%s: count = %d\n", __func__, count);
+#endif
+
+ if (count < EP0_MAX_PACKET_SIZE) {
+ /* last packet */
+ csr0 |= (EP0_TXPKTRDY | EP0_DATAEND);
+ ep0_urb->actual_length = 0;
+ endpoint->sent = 0;
+ ep0_state = EP0_IDLE;
+ } else {
+ /* more packets are waiting to be transferred */
+ csr0 |= EP0_TXPKTRDY;
+ }
+
+ writew(csr0, IECSR + CSR0);
+ writeb(index, INDEX);
+
+ return;
+}
+
+static void mt_udc_ep0_read(void)
+{
+
+ struct udc_endpoint *endpoint = &ep_list[EP0];
+ int count = 0;
+ u16 csr0 = 0;
+ u8 index = 0;
+
+ index = readb(INDEX);
+ writeb(EP0, INDEX);
+
+ csr0 = readw(IECSR + CSR0);
+
+ /* erroneous ep0 interrupt */
+ if (!(csr0 & EP0_RXPKTRDY)) {
+ return;
+ }
+
+ count = mt_read_fifo(endpoint);
+
+ if (count <= EP0_MAX_PACKET_SIZE) {
+ /* last packet */
+ csr0 |= (EP0_SERVICED_RXPKTRDY | EP0_DATAEND);
+ ep0_state = EP0_IDLE;
+ } else {
+ /* more packets are waiting to be transferred */
+ csr0 |= EP0_SERVICED_RXPKTRDY;
+ }
+
+ writew(csr0, IECSR + CSR0);
+
+ writeb(index, INDEX);
+
+ return;
+}
+
+static int ep0_standard_setup(struct urb *urb)
+{
+ struct setup_packet *request;
+ struct udc_descriptor *desc;
+ //struct udc_device *device;
+ u8 *cp = urb->buffer;
+#if 0
+ if (!urb || !urb->device) {
+ DBG ("\n!urb || !urb->device\n");
+ return 0;
+ }
+#endif
+
+ request = &urb->device_request;
+ //device = urb->device;
+
+ dump_setup_packet("[USB] Device Request\n", request);
+
+ if ((request->type & USB_TYPE_MASK) != 0) {
+ return 0; /* Class-specific requests are handled elsewhere */
+ }
+
+ /* handle all requests that return data (direction bit set on bm RequestType) */
+ if ((request->type & USB_EP_DIR_MASK)) {
+ /* send the descriptor */
+ ep0_state = EP0_TX;
+
+ switch (request->request) {
+ /* data stage: from device to host */
+ case GET_STATUS:
+#if DBG_USB_GENERAL
+ DBG_I("GET_STATUS\n");
+#endif
+ urb->actual_length = 2;
+ cp[0] = cp[1] = 0;
+ switch (request->type & USB_RECIP_MASK) {
+ case USB_RECIP_DEVICE:
+ cp[0] = USB_STAT_SELFPOWERED;
+ break;
+ case USB_RECIP_OTHER:
+ urb->actual_length = 0;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+
+ case GET_DESCRIPTOR:
+#if DBG_USB_GENERAL
+ DBG_I("GET_DESCRIPTOR\n");
+#endif
+ /* usb_highspeed? */
+
+ for (desc = desc_list; desc; desc = desc->next) {
+#if DBG_USB_DUMP_DESC
+ DBG_I("desc->tag: %x: request->value: %x\n", desc->tag, request->value);
+#endif
+ if (desc->tag == request->value) {
+
+#if DBG_USB_DUMP_DESC
+ DBG_I("Find packet!\n");
+#endif
+ unsigned len = desc->len;
+ if (len > request->length)
+ len = request->length;
+
+#if DBG_USB_GENERAL
+ DBG_I("%s: urb: %x, cp: %p\n", __func__, urb, cp);
+#endif
+ copy_desc(urb, desc->data, len);
+ return 0;
+ }
+ }
+ /* descriptor lookup failed */
+ return 0;
+
+ case GET_CONFIGURATION:
+#if DBG_USB_GENERAL
+ DBG_I("GET_CONFIGURATION\n");
+ DBG_I("USB_EP_DIR_MASK\n");
+#endif
+#if 0
+ urb->actual_length = 1;
+ ((char *) urb->buffer)[0] = device->configuration;
+#endif
+// return 0;
+ break;
+
+ case GET_INTERFACE:
+#if DBG_USB_GENERAL
+ DBG_I("GET_INTERFACE\n");
+#endif
+
+#if 0
+ urb->actual_length = 1;
+ ((char *) urb->buffer)[0] = device->alternate;
+ return 0;
+#endif
+ default:
+ DBG_C("Unsupported command with TX data stage\n");
+ break;
+ }
+ } else {
+
+ switch (request->request) {
+
+ case SET_ADDRESS:
+#if DBG_USB_GENERAL
+ DBG_I("SET_ADDRESS\n");
+#endif
+
+ dev_address = (request->value);
+ set_address = 1;
+ return 0;
+
+ case SET_CONFIGURATION:
+#if DBG_USB_GENERAL
+ DBG_I("SET_CONFIGURATION\n");
+#endif
+#if 0
+ device->configuration = (request->value) & 0x7f;
+ device->interface = device->alternate = 0;
+#endif
+ if (request->value == 1) {
+ usb_config_value = 1;
+ the_gadget->notify(the_gadget, UDC_EVENT_ONLINE);
+ } else {
+ usb_config_value = 0;
+ the_gadget->notify(the_gadget, UDC_EVENT_OFFLINE);
+ }
+
+ usb_online = request->value ? 1 : 0;
+ //usb_status(request->value ? 1 : 0, usb_highspeed);
+
+ return 0;
+
+ default:
+ DBG_C("Unsupported command with RX data stage\n");
+ break;
+
+ }
+ }
+ return 0;
+}
+
+static void mt_udc_ep0_setup(void)
+{
+ struct udc_endpoint *endpoint = &ep_list[0];
+ u8 index;
+ u8 stall = 0;
+ u16 csr0;
+ struct setup_packet *request;
+
+#ifdef USB_DEBUG
+ u16 count;
+#endif
+
+ index = readb(INDEX);
+ writeb(0, INDEX);
+ /* Read control status register for endpiont 0 */
+ csr0 = readw(IECSR + CSR0);
+
+ /* check whether RxPktRdy is set? */
+ if (!(csr0 & EP0_RXPKTRDY))
+ return;
+
+ /* unload fifo */
+ ep0_urb->actual_length = 0;
+
+#ifndef USB_DEBUG
+ mt_read_fifo(endpoint);
+#else
+ count = mt_read_fifo(endpoint);
+
+#if DBG_USB_FIFO
+ DBG_I("%s: mt_read_fifo count = %d\n", __func__, count);
+#endif
+#endif
+ /* decode command */
+ request = &ep0_urb->device_request;
+ memcpy(request, ep0_urb->buffer, sizeof(struct setup_packet));
+
+ if (((request->type) & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+#if DBG_USB_GENERAL
+ DBG_I("[USB] Standard Request\n");
+#endif
+ stall = ep0_standard_setup(ep0_urb);
+ if (stall) {
+ dump_setup_packet("[USB] STANDARD REQUEST NOT SUPPORTED\n", request);
+ }
+ } else if (((request->type) & USB_TYPE_MASK) == USB_TYPE_CLASS) {
+#if DBG_USB_GENERAL
+ DBG_I("[USB] Class-Specific Request\n");
+#endif
+// stall = ep0_class_setup(ep0_urb);
+ /* Mark dead code, reported by Coverity. */
+ //if (stall) {
+ // dump_setup_packet("[USB] CLASS REQUEST NOT SUPPORTED\n", request);
+ //}
+ } else if (((request->type) & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
+#if DBG_USB_GENERAL
+ DBG_I("[USB] Vendor-Specific Request\n");
+ /* do nothing now */
+ DBG_I("[USB] ALL VENDOR-SPECIFIC REQUESTS ARE NOT SUPPORTED!!\n");
+#endif
+ }
+
+ if (stall) {
+ /* the received command is not supported */
+ udc_stall_ep(0, USB_DIR_OUT);
+ return;
+ }
+
+ switch (ep0_state) {
+ case EP0_TX:
+ /* data stage: from device to host */
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_TX\n", __func__);
+#endif
+ csr0 = readw(IECSR + CSR0);
+ csr0 |= (EP0_SERVICED_RXPKTRDY);
+ writew(csr0, IECSR + CSR0);
+
+ mt_udc_ep0_write();
+
+ break;
+ case EP0_RX:
+ /* data stage: from host to device */
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_RX\n", __func__);
+#endif
+ csr0 = readw(IECSR + CSR0);
+ csr0 |= (EP0_SERVICED_RXPKTRDY);
+ writew(csr0, IECSR + CSR0);
+
+ break;
+ case EP0_IDLE:
+ /* no data stage */
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_IDLE\n", __func__);
+#endif
+ csr0 = readw(IECSR + CSR0);
+ csr0 |= (EP0_SERVICED_RXPKTRDY | EP0_DATAEND);
+
+ writew(csr0, IECSR + CSR0);
+ writew(csr0, IECSR + CSR0);
+
+ break;
+ default:
+ break;
+ }
+
+ writeb(index, INDEX);
+ return;
+
+}
+
+static void mt_udc_ep0_handler(void)
+{
+
+ u16 csr0;
+ u8 index = 0;
+
+ index = readb(INDEX);
+ writeb(0, INDEX);
+
+ csr0 = readw(IECSR + CSR0);
+
+ if (csr0 & EP0_SENTSTALL) {
+#if DBG_USB_GENERAL
+ DBG_I("USB: [EP0] SENTSTALL\n");
+#endif
+ /* needs implementation for exception handling here */
+ ep0_state = EP0_IDLE;
+ }
+
+ if (csr0 & EP0_SETUPEND) {
+#if DBG_USB_GENERAL
+ DBG_I("USB: [EP0] SETUPEND\n");
+#endif
+ csr0 |= EP0_SERVICE_SETUP_END;
+ writew(csr0, IECSR + CSR0);
+
+ ep0_state = EP0_IDLE;
+ }
+
+ switch (ep0_state) {
+ case EP0_IDLE:
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_IDLE\n", __func__);
+#endif
+ if (set_address) {
+ writeb(dev_address, FADDR);
+ set_address = 0;
+ }
+ mt_udc_ep0_setup();
+ break;
+ case EP0_TX:
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_TX\n", __func__);
+#endif
+ mt_udc_ep0_write();
+ break;
+ case EP0_RX:
+#if DBG_USB_GENERAL
+ DBG_I("%s: EP0_RX\n", __func__);
+#endif
+ mt_udc_ep0_read();
+ break;
+ default:
+ break;
+ }
+
+ writeb(index, INDEX);
+
+ return;
+}
+
+unsigned int uffs(unsigned int x)
+{
+ unsigned int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+/*
+ * udc_setup_ep - setup endpoint
+ *
+ * Associate a physical endpoint with endpoint_instance and initialize FIFO
+ */
+void mt_setup_ep(unsigned int ep, struct udc_endpoint *endpoint)
+{
+ u8 index;
+ u16 csr;
+ u16 csr0;
+ u16 max_packet_size;
+ u8 fifosz = 0;
+
+ /* EP table records in bits hence bit 1 is ep0 */
+ index = readb(INDEX);
+ writeb(ep, INDEX);
+
+ if (ep == EP0) {
+ /* Read control status register for endpiont 0 */
+ csr0 = readw(IECSR + CSR0);
+
+ /* check whether RxPktRdy is set? */
+ if (!(csr0 & EP0_RXPKTRDY))
+ return;
+ }
+
+ /* Configure endpoint fifo */
+ /* Set fifo address, fifo size, and fifo max packet size */
+#if DBG_USB_GENERAL
+ DBG_I("%s: endpoint->in: %d, maxpkt: %d\n",
+ __func__, endpoint->in, endpoint->maxpkt);
+#endif
+ if (endpoint->in == 0) { /* USB_DIR_OUT */
+ /* Clear data toggle to 0 */
+ csr = readw(IECSR + RXCSR);
+ /* pangyen 20090911 */
+ csr |= EPX_RX_CLRDATATOG | EPX_RX_FLUSHFIFO;
+ writew(csr, IECSR + RXCSR);
+ /* Set fifo address */
+ writew(fifo_addr >> 3, RXFIFOADD);
+ /* Set fifo max packet size */
+ max_packet_size = endpoint->maxpkt;
+ writew(max_packet_size, IECSR + RXMAP);
+ /* Set fifo size (double buffering is currently not enabled) */
+ switch (max_packet_size) {
+ case 8:
+ case 16:
+ case 32:
+ case 64:
+ case 128:
+ case 256:
+ case 512:
+ case 1024:
+ case 2048:
+ if (endpoint->mode == DOUBLE_BUF)
+ fifosz |= FIFOSZ_DPB;
+
+ fifosz |= uffs(max_packet_size >> 4);
+ writeb(fifosz, RXFIFOSZ);
+ break;
+ case 4096:
+ fifosz |= uffs(max_packet_size >> 4);
+ writeb(fifosz, RXFIFOSZ);
+ break;
+ case 3072:
+ fifosz = uffs(4096 >> 4);
+ writeb(fifosz, RXFIFOSZ);
+ break;
+
+ default:
+ DBG_C("The max_packet_size for ep %d is not supported\n", ep);
+ }
+ } else {
+ /* Clear data toggle to 0 */
+ csr = readw(IECSR + TXCSR);
+ /* pangyen 20090911 */
+ csr |= EPX_TX_CLRDATATOG | EPX_TX_FLUSHFIFO;
+ writew(csr, IECSR + TXCSR);
+ /* Set fifo address */
+ writew(fifo_addr >> 3, TXFIFOADD);
+ /* Set fifo max packet size */
+ max_packet_size = endpoint->maxpkt;
+ writew(max_packet_size, IECSR + TXMAP);
+ /* Set fifo size(double buffering is currently not enabled) */
+ switch (max_packet_size) {
+ case 8:
+ case 16:
+ case 32:
+ case 64:
+ case 128:
+ case 256:
+ case 512:
+ case 1024:
+ case 2048:
+ if (endpoint->mode == DOUBLE_BUF)
+ fifosz |= FIFOSZ_DPB;
+
+ /* Add for resolve issue reported by Coverity */
+ fifosz |= uffs(max_packet_size >> 4);
+ writeb(fifosz, TXFIFOSZ);
+ break;
+
+ case 4096:
+ fifosz |= uffs(max_packet_size >> 4);
+ writeb(fifosz, TXFIFOSZ);
+ break;
+ case 3072:
+ fifosz = uffs(4096 >> 4);
+ writeb(fifosz, TXFIFOSZ);
+ break;
+
+ default:
+ DBG_C("The max_packet_size for ep %d is not supported\n", ep);
+ }
+ }
+
+ if (endpoint->mode == DOUBLE_BUF)
+ fifo_addr += (max_packet_size << 1);
+ else
+ fifo_addr += max_packet_size;
+
+ /* recover INDEX register */
+ writeb(index, INDEX);
+}
+
+struct udc_endpoint *_udc_endpoint_alloc(unsigned char num, unsigned char in,
+ unsigned short max_pkt)
+{
+ int i;
+
+ /*
+ * find an unused slot in ep_list from EP1 to MAX_EP
+ * for example, EP1 will use 2 slot one for IN and the other for OUT
+ */
+ if (num != EP0) {
+ for (i = 1; i < MT_EP_NUM; i++) {
+ if (ep_list[i].num == 0) /* usable */
+ break;
+ }
+
+ if (i == MT_EP_NUM) /* ep has been exhausted. */
+ return NULL;
+
+ if (in) { /* usb EP1 tx */
+ ep_list[i].tx_urb = tx_urb;
+#ifdef USB_DOUBLE_BUF
+ ep_list[i].mode = DOUBLE_BUF;
+#endif
+ } else { /* usb EP1 rx */
+ ep_list[i].rcv_urb = rx_urb;
+#ifdef USB_DOUBLE_BUF
+ ep_list[i].mode = DOUBLE_BUF;
+#endif
+ }
+ } else {
+ i = EP0; /* EP0 */
+ }
+
+ ep_list[i].maxpkt = max_pkt;
+ ep_list[i].num = num;
+ ep_list[i].in = in;
+ ep_list[i].req = NULL;
+
+ /* store EPT_TX/RX info */
+ if (ep_list[i].in) {
+ ep_list[i].bit = EPT_TX(num);
+ } else {
+ ep_list[i].bit = EPT_RX(num);
+ }
+
+ /* write parameters to this ep (write to hardware) */
+ mt_setup_ep(num, &ep_list[i]);
+
+ DBG_I("[USB] ept%d %s @%p/%p max=%d bit=%x\n",
+ num, in ? "in" : "out", &ep_list[i], &ep_list, max_pkt, ep_list[i].bit);
+
+ return &ep_list[i];
+}
+
+#define SETUP(type,request) (((type) << 8) | (request))
+
+static unsigned long ept_alloc_table = EPT_TX(0) | EPT_RX(0);
+
+struct udc_endpoint *udc_endpoint_alloc(unsigned type, unsigned maxpkt)
+{
+ struct udc_endpoint *ept;
+ unsigned n;
+ unsigned in;
+
+ if (type == UDC_BULK_IN) {
+ in = 1;
+ } else if (type == UDC_BULK_OUT) {
+ in = 0;
+ } else {
+ return 0;
+ }
+
+ /* udc_endpoint_alloc is used for EPx except EP0 */
+ for (n = 1; n < 16; n++) {
+ unsigned long bit = in ? EPT_TX(n) : EPT_RX(n);
+ if (ept_alloc_table & bit)
+ continue;
+ ept = _udc_endpoint_alloc(n, in, maxpkt);
+ if (ept)
+ ept_alloc_table |= bit;
+ return ept;
+ }
+
+ return 0;
+}
+
+static void handle_ept_complete(struct udc_endpoint *ept)
+{
+ unsigned int actual;
+ int status;
+ struct udc_request *req;
+ extern int txn_status;
+
+ req = ept->req;
+ if (req) {
+#if DBG_USB_GENERAL
+ DBG_I("%s: req: %x: req->length: %d: status: %d\n", __func__, req, req->length, ept->status);
+#endif
+ /* release this request for processing next */
+ ept->req = NULL;
+
+ if (ept->status == -1) {
+ actual = 0;
+ status = -1;
+ DBG_C("%s: EP%d/%s FAIL status: %x\n",
+ __func__, ept->num, ept->in ? "in" : "out", status);
+ } else {
+ actual = req->length;
+ status = 0;
+ }
+ if (req->complete)
+ req->complete(req, actual, status);
+ }
+}
+
+static void mt_udc_epx_handler(u8 ep_num, u8 dir)
+{
+ u8 index;
+ u16 csr;
+ u32 count;
+ struct udc_endpoint *endpoint;
+ struct urb *urb;
+ struct udc_request *req; /* for event signaling */
+ u8 intrrxe;
+
+ endpoint = mt_find_ep(ep_num, dir);
+
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+#if DBG_USB_GENERAL
+ DBG_I("EP%d Interrupt\n", ep_num);
+ DBG_I("dir: %x\n", dir);
+#endif
+
+ switch (dir) {
+ case USB_DIR_OUT:
+ /* transfer direction is from host to device */
+ /* from the view of usb device, it's RX */
+ csr = readw(IECSR + RXCSR);
+
+ if (csr & EPX_RX_SENTSTALL) {
+ DBG_C("EP %d(RX): STALL\n", ep_num);
+ /* exception handling: implement this!! */
+ return;
+ }
+
+#ifdef SUPPORT_QMU /* SUPPORT_QMU */
+ count = endpoint->rcv_urb->actual_length;
+ DBG_I("%s: QMU: count: %d\n", __func__, count);
+#else /* PIO MODE */
+
+ if (!(csr & EPX_RX_RXPKTRDY)) {
+#if DBG_USB_GENERAL
+ DBG_I("EP %d: ERRONEOUS INTERRUPT\n", ep_num); // normal
+#endif
+ return;
+ }
+
+ //DBG_C("mt_read_fifo, start\n");
+ count = mt_read_fifo(endpoint);
+ //DBG_C("mt_read_fifo, end\n");
+
+#if DBG_USB_GENERAL
+ DBG_I("EP%d(RX), count = %d\n", ep_num, count);
+#endif
+
+ csr &= ~EPX_RX_RXPKTRDY;
+ writew(csr, IECSR + RXCSR);
+ if (readw(IECSR + RXCSR) & EPX_RX_RXPKTRDY) {
+#if DBG_USB_GENERAL
+ DBG_I("%s: rxpktrdy clear failed\n", __func__);
+#endif
+ }
+#endif /* ifndef SUPPORT_QMU */
+
+ /* do signaling */
+ req = endpoint->req;
+ /* workaround: if req->lenth == 64 bytes (not huge data transmission)
+ * do normal return */
+#if DBG_USB_GENERAL
+ DBG_I("%s: req->length: %x, endpoint->rcv_urb->actual_length: %x\n",
+ __func__, req->length, endpoint->rcv_urb->actual_length);
+#endif
+
+ /* Deal with FASTBOOT command */
+ if ((req->length >= endpoint->rcv_urb->actual_length) && req->length == 64) {
+ req->length = count;
+
+ /* mask EPx INTRRXE */
+ /* The buffer is passed from the AP caller.
+ * It happens that AP is dealing with the buffer filled data by driver,
+ * but the driver is still receiving the next data packets onto the buffer.
+ * Data corrupted happens if the every request use the same buffer.
+ * Mask the EPx to ensure that AP and driver are not accessing the buffer parallely.
+ */
+ intrrxe = readb(INTRRXE);
+ writeb((intrrxe &= ~(1 << ep_num)), INTRRXE);
+ }
+
+ /* Deal with DATA transfer */
+ if ((req->length == endpoint->rcv_urb->actual_length) ||
+ ((req->length >= endpoint->rcv_urb->actual_length) && req->length == 64)) {
+ handle_ept_complete(endpoint);
+
+ /* mask EPx INTRRXE */
+ /* The buffer is passed from the AP caller.
+ * It happens that AP is dealing with the buffer filled data by driver,
+ * but the driver is still receiving the next data packets onto the buffer.
+ * Data corrupted happens if the every request use the same buffer.
+ * Mask the EPx to ensure that AP and driver are not accessing the buffer parallely.
+ */
+ intrrxe = readb(INTRRXE);
+ writeb((intrrxe &= ~(1 << ep_num)), INTRRXE);
+ }
+ break;
+ case USB_DIR_IN:
+ /* transfer direction is from device to host */
+ /* from the view of usb device, it's tx */
+ csr = readw(IECSR + TXCSR);
+
+ if (csr & EPX_TX_SENTSTALL) {
+ DBG_C("EP %d(TX): STALL\n", ep_num);
+ endpoint->status = -1;
+ handle_ept_complete(endpoint);
+ /* exception handling: implement this!! */
+ return;
+ }
+
+#ifndef SUPPORT_QMU
+ if (csr & EPX_TX_TXPKTRDY) {
+ DBG_C
+ ("mt_udc_epx_handler: ep%d is not ready to be written\n",
+ ep_num);
+ return;
+ }
+#endif
+ urb = endpoint->tx_urb;
+ if (endpoint->sent == urb->actual_length) {
+ /* do signaling */
+ handle_ept_complete(endpoint);
+ break;
+ }
+
+ /* send next packet of the same urb */
+#ifndef SUPPORT_QMU
+ count = mt_write_fifo(endpoint);
+#if DBG_USB_GENERAL
+ DBG_I("EP%d(TX), count = %d\n", ep_num, endpoint->sent);
+#endif
+
+ if (count != 0) {
+ /* not the interrupt generated by the last tx packet of the transfer */
+ csr |= EPX_TX_TXPKTRDY;
+ writew(csr, IECSR + TXCSR);
+ }
+#endif
+ break;
+ default:
+ break;
+ }
+
+ writeb(index, INDEX);
+
+ return;
+}
+
+
+void mt_udc_irq(u8 intrtx, u8 intrrx, u8 intrusb, u32 wQmuVal)
+{
+
+ int i;
+
+ DBG_IRQ("[USB] INTERRUPT\n");
+
+ if (intrusb) {
+ if (intrusb & INTRUSB_RESUME) {
+ DBG_IRQ("[USB] INTRUSB: RESUME\n");
+ }
+
+ if (intrusb & INTRUSB_SESS_REQ) {
+ DBG_IRQ("[USB] INTRUSB: SESSION REQUEST\n");
+ }
+
+ if (intrusb & INTRUSB_VBUS_ERROR) {
+ DBG_IRQ("[USB] INTRUSB: VBUS ERROR\n");
+ }
+
+ if (intrusb & INTRUSB_SUSPEND) {
+ DBG_IRQ("[USB] INTRUSB: SUSPEND\n");
+ mt_udc_suspend();
+ }
+
+ if (intrusb & INTRUSB_CONN) {
+ DBG_IRQ("[USB] INTRUSB: CONNECT\n");
+ }
+
+ if (intrusb & INTRUSB_DISCON) {
+ DBG_IRQ("[USB] INTRUSB: DISCONNECT\n");
+ }
+
+ if (intrusb & INTRUSB_RESET) {
+ DBG_IRQ("[USB] INTRUSB: RESET\n");
+ mt_udc_reset();
+ }
+
+ if (intrusb & INTRUSB_SOF) {
+ DBG_IRQ("[USB] INTRUSB: SOF\n");
+ }
+ }
+
+#ifdef SUPPORT_QMU
+ wQmuVal &= ~(DRV_Reg32(USB_QIMR));
+ if ((wQmuVal & DQMU_M_RX_DONE(1))||(wQmuVal & DQMU_M_TX_DONE(1))) {
+ qmu_done_interrupt(wQmuVal);
+
+ if (wQmuVal & DQMU_M_RX_DONE(1)) {
+ DBG_IRQ("[USB] DQMU_M_RX_DONE\n");
+ mt_udc_epx_handler(1, USB_DIR_OUT);
+ }
+
+ if (wQmuVal & DQMU_M_TX_DONE(1)) {
+ DBG_IRQ("[USB] DQMU_M_TX_DONE\n");
+ mt_udc_epx_handler(1, USB_DIR_IN);
+ }
+ }
+ if (wQmuVal) {
+ qmu_handler(wQmuVal);
+ }
+#endif
+
+ /* endpoint 0 interrupt? */
+ if (intrtx & EPMASK (0)) {
+ mt_udc_ep0_handler();
+ intrtx &= ~0x1;
+ }
+
+ if (intrtx) {
+ for (i = 1; i < MT_EP_NUM; i++) {
+ if (intrtx & EPMASK (i)) {
+ mt_udc_epx_handler(i, USB_DIR_IN);
+ }
+ }
+ }
+
+ if (intrrx) {
+ for (i = 1; i < MT_EP_NUM; i++) {
+ if (intrrx & EPMASK (i)) {
+ mt_udc_epx_handler(i, USB_DIR_OUT);
+ }
+ }
+ }
+
+}
+
+static enum handler_return service_interrupts(void *arg)
+{
+
+ volatile u8 intrtx, intrrx, intrusb;
+ volatile u32 wQmuVal;
+
+ /* polling interrupt status for incoming interrupts and service it */
+ intrtx = readb(INTRTX) & readb(INTRTXE);
+ intrrx = readb(INTRRX) & readb(INTRRXE);
+ intrusb = readb(INTRUSB) & readb(INTRUSBE);
+
+ writeb(intrtx, INTRTX);
+ writeb(intrrx, INTRRX);
+ writeb(intrusb, INTRUSB);
+
+ intrusb &= ~INTRUSB_SOF;
+ wQmuVal = 0;
+
+#ifdef SUPPORT_QMU
+ wQmuVal = DRV_Reg32(USB_QISAR);
+ if (wQmuVal) {
+ DRV_WriteReg32(USB_QISAR, wQmuVal);
+ }
+#endif
+
+ if (intrtx | intrrx | intrusb | wQmuVal) {
+ mt_udc_irq(intrtx, intrrx, intrusb, wQmuVal);
+ }
+
+ return INT_RESCHEDULE;
+
+}
+#if 0
+void mt_usb_poll(void)
+{
+ service_interrupts();
+#if 0
+ static enum handler_return ret;
+ ret = INT_RESCHEDULE;
+
+ if (ret == INT_RESCHEDULE) {
+ thread_preempt();
+ }
+#endif
+ return;
+}
+#endif
+
+int mt_usb_irq_init(void)
+{
+ /* disable all endpoint interrupts */
+ writeb(0, INTRTXE);
+ writeb(0, INTRRXE);
+ writeb(0, INTRUSBE);
+
+ /* 2. Ack all gpt irq if needed */
+ //writel(0x3F, GPT_IRQ_ACK);
+
+ /* 3. Register usb irq */
+ mt_irq_set_sens(USB_MCU_IRQ_BIT1_ID, LEVEL_SENSITIVE);
+ mt_irq_set_polarity(USB_MCU_IRQ_BIT1_ID, MT65xx_POLARITY_LOW);
+ register_int_handler(USB_MCU_IRQ_BIT1_ID, service_interrupts, NULL);
+
+ return 0;
+}
+
+/* Turn on the USB connection by enabling the pullup resistor */
+void mt_usb_connect_internal(void)
+{
+ u8 tmpReg8;
+
+ /* connect */
+ tmpReg8 = readb(POWER);
+ tmpReg8 |= PWR_SOFT_CONN;
+ tmpReg8 |= PWR_ENABLE_SUSPENDM;
+
+#ifdef USB_FORCE_FULL_SPEED
+ tmpReg8 &= ~PWR_HS_ENAB;
+#else
+ tmpReg8 |= PWR_HS_ENAB;
+#endif
+ writeb(tmpReg8, POWER);
+}
+
+/* Turn off the USB connection by disabling the pullup resistor */
+void mt_usb_disconnect_internal(void)
+{
+ u8 tmpReg8;
+
+ /* connect */
+ tmpReg8 = readb(POWER);
+ tmpReg8 &= ~PWR_SOFT_CONN;
+ writeb(tmpReg8, POWER);
+}
+
+int udc_init(struct udc_device *dev)
+{
+ struct udc_descriptor *desc = NULL;
+#ifdef USB_GINTR
+#ifdef USB_HSDMA_ISR
+ u32 usb_dmaintr;
+#endif
+ u32 usb_l1intm;
+#endif
+ u8 IntrUSB;
+
+ DBG_I("[USB] %s:\n", __func__);
+
+ DBG_I("[USB] ep0_urb: %p\n", ep0_urb);
+
+ /* usb phy init */
+ board_usb_init();
+
+ /* clear INTRTX, INTRRX and INTRUSB */
+ IntrUSB = readw(INTRTX);
+ writew(IntrUSB, INTRTX); /* writew */
+ IntrUSB = readw(INTRRX);
+ writew(IntrUSB, INTRRX); /* writew */
+ IntrUSB = readb(INTRUSB);
+ writeb(IntrUSB, INTRUSB); /* writeb */
+
+ writeb(0x00, DEVCTL); /* writeb */
+
+ spin(20);
+
+ /* allocate ep0 */
+ ep0out = _udc_endpoint_alloc(EP0, 0, EP0_MAX_PACKET_SIZE);
+ ep0in = _udc_endpoint_alloc(EP0, 1, EP0_MAX_PACKET_SIZE);
+ ep0req = udc_request_alloc();
+ ep0req->buffer = malloc(4096);
+ ep0_urb->buffer = (unsigned char *)memalign(32, 4096);
+
+ {
+ /* create and register a language table descriptor */
+ /* language 0x0409 is US English */
+ desc = udc_descriptor_alloc(TYPE_STRING, EP0, 4);
+ desc->data[2] = 0x09;
+ desc->data[3] = 0x04;
+ udc_descriptor_register(desc);
+ }
+#ifdef USB_HSDMA_ISR
+ /* setting HSDMA interrupt register */
+ usb_dmaintr = (0xff | 0xff << USB_DMA_INTR_UNMASK_SET_OFFSET);
+ writel(usb_dmaintr, USB_DMA_INTR);
+#endif
+
+#ifdef USB_GINTR
+#ifdef SUPPORT_QMU
+ usb_l1intm = (TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS | DMA_INT_STATUS | QINT_STATUS);
+ writel(usb_l1intm, USB_L1INTM);
+#else
+ usb_l1intm = (TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS | DMA_INT_STATUS);
+ writel(usb_l1intm, USB_L1INTM);
+#endif
+#endif
+
+ the_device = dev;
+ return 0;
+}
+
+void udc_endpoint_free(struct udc_endpoint *ept)
+{
+ /* todo */
+}
+
+struct udc_request *udc_request_alloc(void)
+{
+ struct udc_request *req;
+ req = malloc(sizeof(*req));
+ req->buffer = NULL;
+ req->length = 0;
+ return req;
+}
+
+
+void udc_request_free(struct udc_request *req)
+{
+ free(req);
+}
+
+/* Called to start packet transmission. */
+/* It must be applied in udc_request_queue when polling mode is used.
+ * (When USB_GINTR is undefined).
+ * If interrupt mode is used, you can use
+ * mt_udc_epx_handler(ept->num, USB_DIR_IN); to replace mt_ep_write make ISR
+ * do it for you.
+ */
+static int mt_ep_write(struct udc_endpoint *endpoint)
+{
+ int ep_num = endpoint->num;
+ int count;
+ u8 index;
+ u16 csr;
+
+ index = readb(INDEX);
+ writeb(ep_num, INDEX);
+
+ /* udc_endpoint_write: cannot write ep0 */
+ if (ep_num == 0)
+ return 0;
+
+ /* udc_endpoint_write: cannot write USB_DIR_OUT */
+ if (endpoint->in == 0)
+ return 0;
+
+ csr = readw(IECSR + TXCSR);
+ if (csr & EPX_TX_TXPKTRDY) {
+#if DBG_USB_GENERAL
+ DBG_I("[USB]: udc_endpoint_write: ep%d is not ready to be written\n",
+ ep_num);
+
+#endif
+ return 0;
+ }
+ count = mt_write_fifo(endpoint);
+
+ csr |= EPX_TX_TXPKTRDY;
+ writew(csr, IECSR + TXCSR);
+
+ writeb(index, INDEX);
+
+ return count;
+}
+
+int udc_request_queue(struct udc_endpoint *ept, struct udc_request *req)
+{
+#ifdef SUPPORT_QMU
+ u8 *pbuf;
+#else
+ u8 intrrxe;
+#endif
+
+#ifdef SUPPORT_QMU
+ /* don't dump debug message here, will cause ISR fail */
+ /* work around for abnormal disconnect line during qmu transfer */
+ if (!usb_online)
+ return 0;
+#endif
+
+#if DBG_USB_GENERAL
+ DBG_I("[USB] %s: ept%d %s queue req=%p, req->length=%x\n",
+ __func__, ept->num, ept->in ? "in" : "out", req, req->length);
+ DBG_I("[USB] %s: ept%d: %x, ept->in: %s, ept->rcv_urb->buffer: %x, req->buf: %x\n",
+ __func__, ept->num, ept, ept->in ? "IN" : "OUT" , ept->rcv_urb->buffer, req->buf);
+#endif
+
+ ept->req = req;
+ ept->status = 0; /* ACTIVE */
+
+ ept->sent = 0;
+ ept->last = 0;
+
+ /* read */
+ if (!ept->in) {
+ ept->rcv_urb->buffer = req->buffer;
+ ept->rcv_urb->actual_length = 0;
+
+ /* unmask EPx INTRRXE */
+ /*
+ * To avoid the parallely access the buffer,
+ * it is umasked here and umask at complete.
+ */
+#ifdef SUPPORT_QMU /* For QMU, don't enable EP interrupts. */
+ pbuf = ept->rcv_urb->buffer;
+
+ /* FASTBOOT COMMAND */
+ if (req->length <= GPD_BUF_SIZE_ALIGN) {
+ mu3d_hal_insert_transfer_gpd(ept->num, USB_DIR_OUT, pbuf, req->length, true, true, false, (ept->type == USB_EP_XFER_ISO ? 0 : 1), ept->maxpkt);
+
+ } else { /* FASTBOOT DATA */
+ DBG_C("udc_request exceeded the maximum QMU buffer size GPD_BUF_SIZE_ALIGN\n");
+ }
+ /* start transfer */
+ arch_clean_invalidate_cache_range((addr_t) ept->rcv_urb->buffer, req->length);
+ mu3d_hal_resume_qmu(ept->num, USB_DIR_OUT);
+#else /* For PIO, enable EP interrupts */
+ intrrxe = readb(INTRRXE);
+ intrrxe |= (1 << ept->num);
+ writeb(intrrxe, INTRRXE);
+#endif
+ }
+
+ /* write */
+ if (ept->in) {
+ ept->tx_urb->buffer = req->buffer;
+ ept->tx_urb->actual_length = req->length;
+
+#ifdef SUPPORT_QMU /* For QMU, we don't call mt_ep_write() */
+ mu3d_hal_insert_transfer_gpd(ept->num, USB_DIR_IN, ept->tx_urb->buffer, req->length, true, true, false, (ept->type == USB_EP_XFER_ISO ? 0 : 1), ept->maxpkt);
+ arch_clean_invalidate_cache_range((addr_t) ept->tx_urb->buffer, req->length);
+ mu3d_hal_resume_qmu(ept->num, USB_DIR_IN);
+#else /* For PIO, call mt_ep_write() */
+ mt_ep_write(ept);
+#endif
+ }
+
+ return 0;
+}
+
+#if 0
+enum handler_return udc_interrupt(void *arg)
+{
+ struct udc_endpoint *ept;
+ unsigned ret;
+
+ return ret;
+}
+#endif
+
+int udc_register_gadget(struct udc_gadget *gadget)
+{
+ if (the_gadget) {
+ DBG_C("only one gadget supported\n");
+ return 0;
+ }
+ the_gadget = gadget;
+ return 0;
+}
+
+static void udc_ept_desc_fill(struct udc_endpoint *ept, unsigned char *data)
+{
+ data[0] = 7;
+ data[1] = TYPE_ENDPOINT;
+ data[2] = ept->num | (ept->in ? USB_DIR_IN : USB_DIR_OUT);
+ data[3] = 0x02; /* bulk -- the only kind we support */
+ data[4] = ept->maxpkt;
+ data[5] = ept->maxpkt >> 8;
+ data[6] = ept->in ? 0x00 : 0x01;
+}
+
+static unsigned udc_ifc_desc_size(struct udc_gadget *g)
+{
+ return 9 + g->ifc_endpoints * 7;
+}
+
+static void udc_ifc_desc_fill(struct udc_gadget *g, unsigned char *data)
+{
+ unsigned n;
+
+ data[0] = 0x09;
+ data[1] = TYPE_INTERFACE;
+ data[2] = 0x00; /* ifc number */
+ data[3] = 0x00; /* alt number */
+ data[4] = g->ifc_endpoints;
+ data[5] = g->ifc_class;
+ data[6] = g->ifc_subclass;
+ data[7] = g->ifc_protocol;
+ data[8] = udc_string_desc_alloc(g->ifc_string);
+
+ data += 9;
+ for (n = 0; n < g->ifc_endpoints; n++) {
+ udc_ept_desc_fill(g->ept[n], data);
+ data += 7;
+ }
+}
+
+int udc_start(void)
+{
+ struct udc_descriptor *desc;
+ unsigned char *data;
+ unsigned size;
+
+ DBG_C("[USB] %s,%s\n", __func__, __TIME__);
+
+ if (!the_device) {
+ DBG_C("udc cannot start before init\n");
+ return 0;
+ }
+ if (!the_gadget) {
+ DBG_C("udc has no gadget registered\n");
+ return 0;
+ }
+
+ /* create our device descriptor */
+ desc = udc_descriptor_alloc(TYPE_DEVICE, EP0, 18);
+ data = desc->data;
+ data[2] = 0x00; /* usb spec minor rev */
+ data[3] = 0x02; /* usb spec major rev */
+ data[4] = 0x00; /* class */
+ data[5] = 0x00; /* subclass */
+ data[6] = 0x00; /* protocol */
+ data[7] = 0x40; /* max packet size on ept 0 */
+ memcpy(data + 8, &the_device->vendor_id, sizeof(short));
+ memcpy(data + 10, &the_device->product_id, sizeof(short));
+ memcpy(data + 12, &the_device->version_id, sizeof(short));
+ data[14] = udc_string_desc_alloc(the_device->manufacturer);
+ data[15] = udc_string_desc_alloc(the_device->product);
+ data[16] = udc_string_desc_alloc(the_device->serialno);
+ data[17] = 1; /* number of configurations */
+ udc_descriptor_register(desc);
+
+ /* create our configuration descriptor */
+ size = 9 + udc_ifc_desc_size(the_gadget);
+ desc = udc_descriptor_alloc(TYPE_CONFIGURATION, EP0, size);
+ data = desc->data;
+ data[0] = 0x09;
+ data[2] = size;
+ data[3] = size >> 8;
+ data[4] = 0x01; /* number of interfaces */
+ data[5] = 0x01; /* configuration value */
+ data[6] = 0x00; /* configuration string */
+ data[7] = 0x80; /* attributes */
+ data[8] = 0x80; /* max power (250ma) -- todo fix this */
+
+ udc_ifc_desc_fill(the_gadget, data + 9);
+ udc_descriptor_register(desc);
+
+#if DBG_USB_DUMP_DESC
+ DBG_I("%s: dump desc_list\n", __func__);
+ for (desc = desc_list; desc; desc = desc->next) {
+ DBG_I("tag: %04x\n", desc->tag);
+ DBG_I("len: %d\n", desc->len);
+ DBG_I("data:");
+ hexdump8(desc->data, desc->len);
+ }
+#endif
+
+ /* register interrupt handler */
+ mt_usb_irq_init();
+
+#ifdef SUPPORT_QMU
+ usb_qmu_init_and_start();
+#endif
+
+ /* unmask usb irq */
+#ifdef USB_GINTR
+ unmask_interrupt(USB_MCU_IRQ_BIT1_ID);
+#endif
+
+ writeb((INTRUSB_SUSPEND | INTRUSB_RESUME | INTRUSB_RESET |INTRUSB_DISCON), INTRUSBE);
+
+ /* enable the pullup resistor */
+ mt_usb_connect_internal();
+
+#if 0
+ while (1) {
+ volatile u8 intrtx, intrrx, intrusb;
+
+ /* polling interrupt status for incoming interrupts and service it */
+ intrtx = readb(INTRTX);
+ intrrx = readb(INTRRX);
+ intrusb = readb(INTRUSB);
+
+ DBG_C("[USB] %s<%x,%x,%x>\n",
+ __func__,
+ intrtx, intrrx, intrusb);
+
+ /* polling interrupt status for incoming interrupts and service it */
+ intrtx = readb(INTRTXE);
+ intrrx = readb(INTRRXE);
+ intrusb = readb(INTRUSBE);
+
+ DBG_C("[USB] %s<%x,%x,%x>\n",
+ __func__,
+ intrtx, intrrx, intrusb);
+
+ spin(500000);
+ //thread_sleep(1);
+ }
+#endif
+
+ return 0;
+}
+
+int udc_stop(void)
+{
+ spin(10);
+
+ mt_usb_disconnect_internal();
+ mt_usb_phy_deinit();
+
+ return 0;
+}
+
+#ifdef SUPPORT_QMU
+void usb_ep_disable_interrupt(u8 ep_num, u8 dir)
+{
+ unsigned int wCsr = 0;
+ unsigned int intr_e = 0;
+
+ writeb(ep_num, INDEX);
+
+ if(dir == USB_DIR_OUT){
+ wCsr |= EPX_RX_DMAREQEN;
+ writew(wCsr, IECSR + RXCSR);
+
+ //turn off intrRx
+ intr_e = readb(INTRRXE);
+ intr_e = intr_e & (~(1<<(1)));
+ writeb(intr_e, INTRRXE);
+ } else {
+ wCsr |= EPX_TX_DMAREQEN;
+ writew(wCsr, IECSR + TXCSR);
+
+ //turn off intrTx
+ intr_e = readb(INTRTXE);
+ intr_e = intr_e & (~(1<<(1)));
+ writeb(intr_e, INTRTXE);
+ }
+}
+
+void usb_qmu_init(void)
+{
+ /* make sure qmu is stopped */
+ mu3d_hal_stop_qmu(1, USB_DIR_IN);
+ mu3d_hal_stop_qmu(1, USB_DIR_OUT);
+
+ mu3d_hal_alloc_qmu_mem();
+ mu3d_hal_init_qmu();
+ gpd_buf_size = GPD_BUF_SIZE_ALIGN; //max allowable data buffer length. Don't care when linking with BD.
+ g_dma_buffer_size = STRESS_DATA_LENGTH * MAX_GPD_NUM;
+}
+
+void usb_qmu_init_and_start(void)
+{
+ u32 i;
+
+ usb_qmu_init();
+
+ for (i = 1; i <= MAX_QMU_EP; i++) {
+ usb_start_qmu(1, USB_DIR_OUT);
+ usb_start_qmu(1, USB_DIR_IN);
+ }
+
+ for (i = 1; i <= MAX_QMU_EP; i++) {
+ usb_ep_disable_interrupt(i, USB_DIR_OUT);
+ usb_ep_disable_interrupt(i, USB_DIR_IN);
+ }
+}
+
+/*
+ * qmu_handler - handle qmu error events
+ * @args - arg1: ep number
+ */
+void qmu_handler(u32 qmu_val)
+{
+ u32 wRetVal;
+ int i;
+
+ wRetVal= 0;
+
+ //RXQ ERROR
+ if (qmu_val & DQMU_M_RXQ_ERR)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_RQEIR) & (~(MGC_ReadQIRQ32(MGC_O_QIRQ_RQEIMR)));
+
+ DBG_I("Rx Queue error in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=RXQ_NUM; i++)
+ {
+ if (wRetVal & DQMU_M_RX_GPDCS_ERR(i))
+ {
+ DBG_I("Rx %d GPD checksum error!\n", i);
+ }
+ if (wRetVal & DQMU_M_RX_LEN_ERR(i))
+ {
+ DBG_I("Rx %d recieve length error!\n", i);
+ }
+ if (wRetVal & DQMU_M_RX_ZLP_ERR(i))
+ {
+ DBG_I("Rx %d recieve an zlp packet!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_RQEIR, wRetVal);
+ }
+
+ //TXQ ERROR
+ if (qmu_val & DQMU_M_TXQ_ERR)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_TQEIR) & (~(MGC_ReadQIRQ32(MGC_O_QIRQ_TQEIMR)));
+
+ DBG_I("Tx Queue error in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=TXQ_NUM; i++)
+ {
+ if (wRetVal & DQMU_M_TX_BDCS_ERR(i))
+ {
+ DBG_I("Tx %d BD checksum error!\n", i);
+ }
+ if (wRetVal & DQMU_M_TX_GPDCS_ERR(i))
+ {
+ DBG_I("Tx %d GPD checksum error!\n", i);
+ }
+ if (wRetVal & DQMU_M_TX_LEN_ERR(i))
+ {
+ DBG_I("Tx %d buffer length error!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TQEIR, wRetVal);
+ }
+
+ //RX EP ERROR
+ if (qmu_val & DQMU_M_RXEP_ERR)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_REPEIR) & (~(MGC_ReadQIRQ32(MGC_O_QIRQ_REPEIMR)));
+
+ DBG_I("Rx endpoint error in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=RXQ_NUM; i++)
+ {
+ if (wRetVal & DQMU_M_RX_EP_ERR(i))
+ {
+ DBG_I("Rx %d Ep Error!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_REPEIR, wRetVal);
+ }
+
+ //TX EP ERROR
+ if(qmu_val & DQMU_M_TXEP_ERR)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_TEPEIR)& (~(MGC_ReadQIRQ32(MGC_O_QIRQ_TEPEIMR)));
+
+ DBG_I("Tx endpoint error in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=TXQ_NUM; i++){
+ if (wRetVal &DQMU_M_TX_EP_ERR(i))
+ {
+ DBG_I("Tx %d Ep Error!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TEPEIR, wRetVal);
+ }
+
+ //RXQ EMPTY
+ if (qmu_val & DQMU_M_RQ_EMPTY)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_REPEMPR) & (~(MGC_ReadQIRQ32(MGC_O_QIRQ_REPEMPMR)));
+ DBG_I("Rx Empty in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=RXQ_NUM; i++)
+ {
+ if (wRetVal & DQMU_M_RX_EMPTY(i))
+ {
+ DBG_I("Rx %d Empty!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_REPEMPR, wRetVal);
+ }
+
+ //TXQ EMPTY
+ if (qmu_val & DQMU_M_TQ_EMPTY)
+ {
+ wRetVal = MGC_ReadQIRQ32(MGC_O_QIRQ_TEPEMPR) & (~(MGC_ReadQIRQ32(MGC_O_QIRQ_TEPEMPMR)));
+ DBG_I("Tx Empty in QMU mode![0x%x]\n", wRetVal);
+
+ for (i=1; i<=TXQ_NUM; i++)
+ {
+ if (wRetVal & DQMU_M_TX_EMPTY(i))
+ {
+ DBG_I("Tx %d Empty!\n", i);
+ }
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TEPEMPR, wRetVal);
+ }
+}
+
+/*
+ * 1. Find the last gpd HW has executed and update tx_gpd_last[]
+ * 2. Set the flag for txstate to know that TX has been completed
+ * ported from proc_qmu_tx() from test driver.
+ * caller:qmu_interrupt after getting QMU done interrupt and TX is raised
+ */
+void qmu_tx_interrupt(u8 ep_num)
+{
+ struct tgpd *gpd = tx_gpd_last[ep_num];
+ struct tgpd *gpd_current = (struct tgpd*)((uintptr_t)MGC_ReadQMU32(MGC_O_QMU_TQCPR(ep_num)));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+ struct udc_endpoint *ept;
+ ept = mt_find_ep(ep_num, USB_DIR_IN);
+
+ DBG_I("tx_gpd_last 0x%lx, gpd_current 0x%lx, gpd_end 0x%lx, \n", (uintptr_t)gpd, (uintptr_t)gpd_current, (uintptr_t)tx_gpd_end[ep_num]);
+
+ if (gpd == gpd_current) {//gpd_current should at least point to the next GPD to the previous last one.
+ DBG_I("should not happen: %s %d\n", __func__, __LINE__);
+ return;
+ }
+
+ while (gpd != gpd_current && !TGPD_IS_FLAGS_HWO(gpd)) {
+
+ DBG_I("Tx gpd %lx info { HWO %d, BPD %d, Next_GPD %lx , DataBuffer %lx, BufferLen %d, Endpoint %d}\n",
+ (uintptr_t)gpd, (u32)TGPD_GET_FLAG(gpd), (u32)TGPD_GET_FORMAT(gpd), (uintptr_t)TGPD_GET_NEXT(gpd),
+ (uintptr_t)TGPD_GET_DATA(gpd), (u32)TGPD_GET_BUF_LEN(gpd), (u32)TGPD_GET_EPaddr(gpd));
+
+ /* required for mt_udc_epx_handler */
+ ept->sent = (u32)TGPD_GET_BUF_LEN(gpd);
+
+ gpd = TGPD_GET_NEXT(gpd);
+ gpd = (struct tgpd *)(phy_to_virt((uintptr_t)gpd));
+
+ tx_gpd_last[ep_num] = gpd;
+ }
+
+ DBG_I("tx_gpd_last[%d]: 0x%lx\n", ep_num, (uintptr_t)tx_gpd_last[ep_num]);
+ DBG_I("tx_gpd_end[%d]: 0x%lx\n", ep_num, (uintptr_t)tx_gpd_end[ep_num]);
+ DBG_I("Tx %d complete\n", ep_num);
+
+ return;
+
+}
+
+/*
+ * When receiving RXQ done interrupt, qmu_interrupt calls this function.
+ *
+ * 1. Traverse GPD/BD data structures to count actual transferred length.
+ * 2. Set the done flag to notify rxstate_qmu() to report status to upper gadget driver.
+ *
+ * ported from proc_qmu_rx() from test driver.
+ * caller:qmu_interrupt after getting QMU done interrupt and TX is raised
+ */
+void qmu_rx_interrupt(u8 ep_num)
+{
+ u32 recivedlength = 0;
+ struct tgpd *gpd = (struct tgpd*) rx_gpd_last[ep_num];
+ struct tgpd *gpd_current = (struct tgpd*)((uintptr_t)MGC_ReadQMU32(MGC_O_QMU_RQCPR(ep_num)));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+ struct tbd *bd;
+ struct udc_endpoint *ept;
+ struct urb *current_urb;
+
+ ept = mt_find_ep(ep_num, USB_DIR_OUT);
+
+ current_urb = ept->rcv_urb;
+
+ DBG_I("ep_num: %d ,Rx_gpd_last: 0x%lx, gpd_current: 0x%lx, gpd_end: 0x%lx \n",ep_num,(uintptr_t)gpd, (uintptr_t)gpd_current, (uintptr_t)rx_gpd_end[ep_num]);
+
+ if (gpd == gpd_current) {
+ DBG_I("should not happen: %s %d\n", __func__, __LINE__);
+ return;
+ }
+
+ while (gpd != gpd_current && !TGPD_IS_FLAGS_HWO(gpd)) {
+
+ if (TGPD_IS_FORMAT_BDP(gpd)) {
+
+ bd = (struct tbd *)TGPD_GET_DATA(gpd);
+
+ while (1) {
+ DBG_I("BD: 0x%lx\n", (uintptr_t)bd);
+ DBG_I("Buf Len: 0x%x\n", (u32)TBD_GET_BUF_LEN(bd));
+ //req->transferCount += TBD_GET_BUF_LEN(bd);
+ //ept->qmu_done_length += TBD_GET_BUF_LEN(bd);
+ current_urb->actual_length += TBD_GET_BUF_LEN(bd);
+
+ //DBG_I("Total Len : 0x%x\n",ept->qmu_done_length);
+ if (TBD_IS_FLAGS_EOL(bd)) {
+ break;
+ }
+ bd = TBD_GET_NEXT(bd);
+ }
+ } else {
+ recivedlength = (u32)TGPD_GET_BUF_LEN(gpd);
+
+ /* required for mt_udc_epx_handler */
+ current_urb->actual_length += recivedlength;
+ }
+
+ DBG_I("Rx gpd info { HWO %d, Next_GPD %lx ,DataBufferLength %d, DataBuffer %lx, Recived Len %d, Endpoint %d, TGL %d, ZLP %d}\n",
+ (u32)TGPD_GET_FLAG(gpd), (uintptr_t)TGPD_GET_NEXT(gpd),
+ (u32)TGPD_GET_DATABUF_LEN(gpd), (uintptr_t)TGPD_GET_DATA(gpd),
+ (u32)TGPD_GET_BUF_LEN(gpd), (u32)TGPD_GET_EPaddr(gpd),
+ (u32)TGPD_GET_TGL(gpd), (u32)TGPD_GET_ZLP(gpd));
+
+ gpd = TGPD_GET_NEXT(gpd);
+ gpd = (struct tgpd *)(phy_to_virt((uintptr_t)gpd));
+
+ rx_gpd_last[ep_num] = gpd;
+ }
+
+ DBG_I("rx_gpd_last[%d]: 0x%lx\n", ep_num, (uintptr_t)rx_gpd_last[ep_num]);
+ DBG_I("rx_gpd_end[%d]: 0x%lx\n", ep_num, (uintptr_t)rx_gpd_end[ep_num]);
+
+}
+
+void qmu_done_interrupt(u32 qmu_val)
+{
+ int i;
+
+ DBG_I("[USB][QMU] qmu_interrupt\n");
+
+ for (i = 1; i <= MAX_QMU_EP; i++) {
+ if (qmu_val & DQMU_M_RX_DONE(i)) {
+ qmu_rx_interrupt(i);
+ }
+
+ if (qmu_val & DQMU_M_TX_DONE(i)) {
+ qmu_tx_interrupt(i);
+ }
+ }
+}
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.h b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.h
new file mode 100644
index 0000000..d37c1fb
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb.h
@@ -0,0 +1,396 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#pragma once
+
+#include <platform/mt_reg_base.h>
+#include <platform/udc-common.h>
+
+#define SUPPORT_QMU
+
+typedef unsigned char U8;
+typedef unsigned short int U16;
+typedef unsigned int U32;
+typedef signed int S32;
+typedef unsigned char kal_uint8;
+typedef unsigned short int kal_uint16;
+typedef unsigned int kal_uint32;
+typedef unsigned char u8;
+typedef unsigned int u32;
+
+/* USB PHY registers */
+#define USB20_PHY_BASE (USBSIF_BASE + 0x0800)
+#define USB11_PHY_BASE (USBSIF_BASE + 0x0900)
+
+/* hardware spec */
+#define MT_EP_NUM 4
+#define MT_CHAN_NUM 4
+#define MT_EP0_FIFOSIZE 64
+
+#define FIFO_ADDR_START 512
+
+#define MT_BULK_MAXP 512
+#define MT_INT_MAXP 1024
+
+/* USB common registers */
+#define FADDR (USB_BASE + 0x0000) /* Function Address Register */
+#define POWER (USB_BASE + 0x0001) /* Power Management Register */
+#define INTRTX (USB_BASE + 0x0002) /* TX Interrupt Status Register */
+#define INTRRX (USB_BASE + 0x0004) /* RX Interrupt Status Register */
+#define INTRTXE (USB_BASE + 0x0006) /* TX Interrupt Status Enable Register */
+#define INTRRXE (USB_BASE + 0x0008) /* RX Interrupt Status Enable Register */
+#define INTRUSB (USB_BASE + 0x000a) /* Common USB Interrupt Register */
+#define INTRUSBE (USB_BASE + 0x000b) /* Common USB Interrupt Enable Register */
+#define FRAME (USB_BASE + 0x000c) /* Frame Number Register */
+#define INDEX (USB_BASE + 0x000e) /* Endpoint Selecting Index Register */
+#define TESTMODE (USB_BASE + 0x000f) /* Test Mode Enable Register */
+
+/* POWER fields */
+#define PWR_ISO_UPDATE (1<<7)
+#define PWR_SOFT_CONN (1<<6)
+#define PWR_HS_ENAB (1<<5)
+#define PWR_HS_MODE (1<<4)
+#define PWR_RESET (1<<3)
+#define PWR_RESUME (1<<2)
+#define PWR_SUSPEND_MODE (1<<1)
+#define PWR_ENABLE_SUSPENDM (1<<0)
+
+/* INTRUSB fields */
+#define INTRUSB_VBUS_ERROR (1<<7)
+#define INTRUSB_SESS_REQ (1<<6)
+#define INTRUSB_DISCON (1<<5)
+#define INTRUSB_CONN (1<<4)
+#define INTRUSB_SOF (1<<3)
+#define INTRUSB_RESET (1<<2)
+#define INTRUSB_RESUME (1<<1)
+#define INTRUSB_SUSPEND (1<<0)
+
+/* DMA control registers */
+#define USB_DMA_INTR (USB_BASE + 0x0200)
+#define USB_DMA_INTR_UNMASK_SET_OFFSET (24)
+
+#define USB_DMA_CNTL(chan) (USB_BASE + 0x0204 + 0x10*(chan-1))
+#define USB_DMA_ADDR(chan) (USB_BASE + 0x0208 + 0x10*(chan-1))
+#define USB_DMA_COUNT(chan) (USB_BASE + 0x020c + 0x10*(chan-1))
+
+/* Endpoint Control/Status Registers */
+#define IECSR (USB_BASE + 0x0010)
+/* for EP0 */
+#define CSR0 0x2 /* EP0 Control Status Register */
+ /* For Host Mode, it would be 0x2 */
+#define COUNT0 0x8 /* EP0 Received Bytes Register */
+#define NAKLIMIT0 0xB /* NAK Limit Register */
+#define CONFIGDATA 0xF /* Core Configuration Register */
+/* for other endpoints */
+#define TXMAP 0x0 /* TXMAP Register: Max Packet Size for TX */
+#define TXCSR 0x2 /* TXCSR Register: TX Control Status Register */
+#define RXMAP 0x4 /* RXMAP Register: Max Packet Size for RX */
+#define RXCSR 0x6 /* RXCSR Register: RX Control Status Register */
+#define RXCOUNT 0x8 /* RXCOUNT Register */
+#define TXTYPE 0xa /* TX Type Register */
+#define TXINTERVAL 0xb /* TX Interval Register */
+#define RXTYPE 0xc /* RX Type Register */
+#define RXINTERVAL 0xd /* RX Interval Register */
+#define FIFOSIZE 0xf /* configured FIFO size register */
+
+/* control status register fields */
+/* CSR0_DEV */
+#define EP0_FLUSH_FIFO (1<<8)
+#define EP0_SERVICE_SETUP_END (1<<7)
+#define EP0_SERVICED_RXPKTRDY (1<<6)
+#define EP0_SENDSTALL (1<<5)
+#define EP0_SETUPEND (1<<4)
+#define EP0_DATAEND (1<<3)
+#define EP0_SENTSTALL (1<<2)
+#define EP0_TXPKTRDY (1<<1)
+#define EP0_RXPKTRDY (1<<0)
+
+/* TXCSR_DEV */
+#define EPX_TX_AUTOSET (1<<15)
+#define EPX_TX_ISO (1<<14)
+#define EPX_TX_MODE (1<<13)
+#define EPX_TX_DMAREQEN (1<<12)
+#define EPX_TX_FRCDATATOG (1<<11)
+#define EPX_TX_DMAREQMODE (1<<10)
+#define EPX_TX_AUTOSETEN_SPKT (1<<9)
+#define EPX_TX_INCOMPTX (1<<7)
+#define EPX_TX_CLRDATATOG (1<<6)
+#define EPX_TX_SENTSTALL (1<<5)
+#define EPX_TX_SENDSTALL (1<<4)
+#define EPX_TX_FLUSHFIFO (1<<3)
+#define EPX_TX_UNDERRUN (1<<2)
+#define EPX_TX_FIFONOTEMPTY (1<<1)
+#define EPX_TX_TXPKTRDY (1<<0)
+
+/* RXCSR_DEV */
+#define EPX_RX_AUTOCLEAR (1<<15)
+#define EPX_RX_ISO (1<<14)
+#define EPX_RX_DMAREQEN (1<<13)
+#define EPX_RX_DISNYET (1<<12)
+#define EPX_RX_PIDERR (1<<12)
+#define EPX_RX_DMAREQMODE (1<<11)
+#define EPX_RX_AUTOCLRENSPKT (1<<10)
+#define EPX_RX_INCOMPRXINTREN (1<<9)
+#define EPX_RX_INCOMPRX (1<<8)
+#define EPX_RX_CLRDATATOG (1<<7)
+#define EPX_RX_SENTSTALL (1<<6)
+#define EPX_RX_SENDSTALL (1<<5)
+#define EPX_RX_FLUSHFIFO (1<<4)
+#define EPX_RX_DATAERR (1<<3)
+#define EPX_RX_OVERRUN (1<<2)
+#define EPX_RX_FIFOFULL (1<<1)
+#define EPX_RX_RXPKTRDY (1<<0)
+
+/* CONFIGDATA fields */
+#define MP_RXE (1<<7)
+#define MP_TXE (1<<6)
+#define BIGENDIAN (1<<5)
+#define HBRXE (1<<4)
+#define HBTXE (1<<3)
+#define DYNFIFOSIZING (1<<2)
+#define SOFTCONE (1<<1)
+#define UTMIDATAWIDTH (1<<0)
+
+/* FIFO register */
+/*
+ * for endpint 1 ~ 4, writing to these addresses = writing to the
+ * corresponding TX FIFO, reading from these addresses = reading from
+ * corresponding RX FIFO
+ */
+
+#define FIFO(ep_num) (USB_BASE + 0x0020 + ep_num*0x0004)
+
+/* ============================ */
+/* additional control registers */
+/* ============================ */
+
+#define DEVCTL (USB_BASE + 0x0060) /* OTG Device Control Register */
+#define PWRUPCNT (USB_BASE + 0x0061) /* Power Up Counter Register */
+#define TXFIFOSZ (USB_BASE + 0x0062) /* TX FIFO Size Register */
+#define RXFIFOSZ (USB_BASE + 0x0063) /* RX FIFO Size Register */
+#define TXFIFOADD (USB_BASE + 0x0064) /* TX FIFO Address Register */
+#define RXFIFOADD (USB_BASE + 0x0066) /* RX FIFO Address Register */
+#define HWVERS (USB_BASE + 0x006c) /* H/W Version Register */
+#define SWRST (USB_BASE + 0x0074) /* Software Reset Register */
+#define EPINFO (USB_BASE + 0x0078) /* TX and RX Information Register */
+#define RAM_DMAINFO (USB_BASE + 0x0079) /* RAM and DMA Information Register */
+#define LINKINFO (USB_BASE + 0x007a) /* Delay Time Information Register */
+#define VPLEN (USB_BASE + 0x007b) /* VBUS Pulse Charge Time Register */
+#define HSEOF1 (USB_BASE + 0x007c) /* High Speed EOF1 Register */
+#define FSEOF1 (USB_BASE + 0x007d) /* Full Speed EOF1 Register */
+#define LSEOF1 (USB_BASE + 0x007e) /* Low Speed EOF1 Register */
+#define RSTINFO (USB_BASE + 0x007f) /* Reset Information Register */
+
+/* FIFO size register fields and available packet size values */
+#define DOUBLE_BUF 1
+#define FIFOSZ_DPB (1 << 4)
+#define PKTSZ 0x0f
+
+#define PKTSZ_8 (1<<3)
+#define PKTSZ_16 (1<<4)
+#define PKTSZ_32 (1<<5)
+#define PKTSZ_64 (1<<6)
+#define PKTSZ_128 (1<<7)
+#define PKTSZ_256 (1<<8)
+#define PKTSZ_512 (1<<9)
+#define PKTSZ_1024 (1<<10)
+
+#define FIFOSZ_8 (0x0)
+#define FIFOSZ_16 (0x1)
+#define FIFOSZ_32 (0x2)
+#define FIFOSZ_64 (0x3)
+#define FIFOSZ_128 (0x4)
+#define FIFOSZ_256 (0x5)
+#define FIFOSZ_512 (0x6)
+#define FIFOSZ_1024 (0x7)
+#define FIFOSZ_2048 (0x8)
+#define FIFOSZ_4096 (0x9)
+#define FIFOSZ_3072 (0xF)
+
+/* SWRST fields */
+#define SWRST_PHY_RST (1<<7)
+#define SWRST_PHYSIG_GATE_HS (1<<6)
+#define SWRST_PHYSIG_GATE_EN (1<<5)
+#define SWRST_REDUCE_DLY (1<<4)
+#define SWRST_UNDO_SRPFIX (1<<3)
+#define SWRST_FRC_VBUSVALID (1<<2)
+#define SWRST_SWRST (1<<1)
+#define SWRST_DISUSBRESET (1<<0)
+
+/* DMA_CNTL */
+#define USB_DMA_CNTL_ENDMAMODE2 (1 << 13)
+#define USB_DMA_CNTL_PP_RST (1 << 12)
+#define USB_DMA_CNTL_PP_EN (1 << 11)
+#define USB_DMA_BURST_MODE_MASK (3 << 9)
+#define USB_DMA_BURST_MODE_0 (0 << 9)
+#define USB_DMA_BURST_MODE_1 (0x1 << 9)
+#define USB_DMA_BURST_MODE_2 (0x2 << 9)
+#define USB_DMA_BURST_MODE_3 (0x3 << 9)
+#define USB_DMA_BUS_ERROR (0x1 << 8)
+#define USB_DMA_ENDPNT_MASK (0xf << 4)
+#define USB_DMA_ENDPNT_OFFSET (4)
+#define USB_DMA_INTEN (1 << 3)
+#define USB_DMA_DMAMODE (1 << 2)
+#define USB_DMA_DIR (1 << 1)
+#define USB_DMA_EN (1 << 0)
+
+/* USB level 1 interrupt registers */
+
+#define USB_L1INTS (USB_BASE + 0xa0) /* USB level 1 interrupt status register */
+#define USB_L1INTM (USB_BASE + 0xa4) /* USB level 1 interrupt mask register */
+#define USB_L1INTP (USB_BASE + 0xa8) /* USB level 1 interrupt polarity register */
+
+#define TX_INT_STATUS (1 << 0)
+#define RX_INT_STATUS (1 << 1)
+#define USBCOM_INT_STATUS (1 << 2)
+#define DMA_INT_STATUS (1 << 3)
+#define PSR_INT_STATUS (1 << 4)
+#define QINT_STATUS (1 << 5)
+#define QHIF_INT_STATUS (1 << 6)
+#define DPDM_INT_STATUS (1 << 7)
+#define VBUSVALID_INT_STATUS (1 << 8)
+#define IDDIG_INT_STATUS (1 << 9)
+#define DRVVBUS_INT_STATUS (1 << 10)
+#define POWERDWN_INT_STATUS (1 << 11)
+
+#define VBUSVALID_INT_POL (1 << 8)
+#define IDDIG_INT_POL (1 << 9)
+#define DRVVBUS_INT_POL (1 << 10)
+
+/* mt_usb defines */
+typedef enum
+{
+ EP0_IDLE = 0,
+ EP0_RX,
+ EP0_TX,
+} EP0_STATE;
+
+#if 0
+typedef enum
+{
+ CHARGER_UNKNOWN,
+ STANDARD_HOST,
+ STANDARD_CHARGER,
+ NONSTANDARD_CHARGER,
+} USB_CHARGER_TYPE;
+#endif
+
+/* some macros */
+#define EPMASK(X) (1 << X)
+#define CHANMASK(X) (1 << X)
+
+void mt_usb_phy_init(void);
+void mt_usb_phy_deinit(void);
+
+/* mt_usb.c */
+struct udc_endpoint *mt_find_ep(int ep_num, u8 dir);
+void mt_setup_ep(unsigned int ep_num, struct udc_endpoint *endpoint);
+void mt_usb_connect_internal(void);
+void mt_usb_disconnect_internal(void);
+void usb_qmu_init_and_start(void);
+
+#define CHECKSUM_LENGTH 16
+
+/* from preloader */
+#define USB_EP_XFER_CTRL 0
+#define USB_EP_XFER_ISO 1
+#define USB_EP_XFER_BULK 2
+#define USB_EP_XFER_INT 3
+
+/* USB transfer directions */
+#define USB_DIR_IN DEVICE_WRITE /* val: 0x80 */
+#define USB_DIR_OUT DEVICE_READ /* val: 0x00 */
+
+struct urb {
+ struct udc_endpoint *endpoint;
+ struct udc_device *device;
+ struct setup_packet device_request;
+
+ u8 *buffer;
+ unsigned int actual_length;
+
+ u32 qmu_complete;
+};
+
+/* endpoint data - mt_ep */
+struct udc_endpoint {
+ /* rx side */
+ struct urb *rcv_urb; /* active urb */
+
+ /* tx side */
+ struct urb *tx_urb; /* active urb */
+
+ /* info from hsusb */
+ struct udc_request *req;
+ unsigned int bit; /* EPT_TX/EPT_RX */
+ unsigned char num;
+ unsigned char in;
+ unsigned short maxpkt;
+ int status; /* status for error handling */
+
+ unsigned int sent; /* data already sent */
+ unsigned int last; /* data sent in last packet XXX do we need this */
+ unsigned char mode; /* double buffer */
+ unsigned char type; /* Transfer type */
+};
+
+/* from mt_usbtty.h */
+#define NUM_ENDPOINTS 3
+
+/* origin endpoint_array */
+struct udc_endpoint ep_list[NUM_ENDPOINTS + 1]; /* one extra for control endpoint */
+
+/* operation definition */
+#define USBPHY_READ8(offset) readb(USB20_PHY_BASE+offset)
+#define USBPHY_WRITE8(offset, value) writeb(value, USB20_PHY_BASE+offset)
+#define USBPHY_SET8(offset, mask) USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
+#define USBPHY_CLR8(offset, mask) USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~mask))
+#define DRV_USB_Reg32(addr) (*(volatile u32 *)(addr))
+#define DRV_USB_WriteReg32(addr,data) ((*(volatile u32 *)(addr)) = (u32)data)
+#define USBPHYREAD32(offset) DRV_USB_Reg32(USB20_PHY_BASE+offset)
+#define USBPHYWRITE32(offset, value) DRV_USB_WriteReg32(USB20_PHY_BASE+offset, value)
+
+#define USB11PHY_READ8(offset) readb(USB11_PHY_BASE+offset)
+#define USB11PHY_WRITE8(offset, value) writeb(value, USB11_PHY_BASE+offset)
+#define USB11PHY_SET8(offset, mask) USB11PHY_WRITE8(offset, (USB11PHY_READ8(offset)) | (mask))
+#define USB11PHY_CLR8(offset, mask) USB11PHY_WRITE8(offset, (USB11PHY_READ8(offset)) & (~mask))
+
+#define USBPHY_SET32(offset, mask) USBPHYWRITE32(offset, USBPHYREAD32(offset) | mask)
+#define USBPHY_CLR32(offset, mask) USBPHYWRITE32(offset, USBPHYREAD32(offset) & ~mask)
+
+#define DRV_Reg(addr) (*(volatile unsigned short *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile unsigned int *)(addr)) = (unsigned int)data)
+#define DRV_Reg32(addr) (*(volatile unsigned int *)(addr))
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.c b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.c
new file mode 100644
index 0000000..d4d6673
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.c
@@ -0,0 +1,616 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <arch/ops.h>
+#include <platform/timer.h>
+#include <kernel/thread.h>
+
+#include "mt_usb_qmu.h"
+#include "mt_usb.h"
+
+/* USB DEBUG */
+#ifdef DBG_USB_QMU
+#define DBG_C(x...) dprintf(CRITICAL, "[USB][QMU] " x)
+#define DBG_I(x...) dprintf(INFO, "[USB][QMU] " x)
+#define DBG_S(x...) dprintf(SPEW, "[USB][QMU] " x)
+#else
+//#define DBG_C(x...) dprintf(CRITICAL, "[USB][QMU] " x)
+#define DBG_C(x...) do {} while (0)
+#define DBG_I(x...) do {} while (0)
+#define DBG_S(x...) do {} while (0)
+#endif
+
+/*
+ * get_bd - get a null gpd
+ * @args - arg1: dir, arg2: ep number
+ */
+struct tgpd *get_gpd(u8 dir, u32 num)
+{
+ struct tgpd *ptr;
+
+ DBG_I("%s\n", __func__);
+
+ if (dir == USB_DIR_OUT) {
+ ptr = (struct tgpd *)rx_gpd_list[num].pnext;
+ DBG_I("(rx_gpd_list[%d].pnext: %p)\n", num, (void *)(rx_gpd_list[num].pnext));
+ if ((rx_gpd_list[num].pnext +1) < rx_gpd_list[num].pend)
+ rx_gpd_list[num].pnext++;
+ else
+ rx_gpd_list[num].pnext = rx_gpd_list[num].pstart;
+ } else {
+ ptr = (struct tgpd *)tx_gpd_list[num].pnext;
+ DBG_I("(tx_gpd_list[%d].pnext: %p)\n", num, (void *)(tx_gpd_list[num].pnext));
+ tx_gpd_list[num].pnext++;
+ if (tx_gpd_list[num].pnext >= tx_gpd_list[num].pend) {
+ tx_gpd_list[num].pnext = tx_gpd_list[num].pstart;
+ }
+ }
+ return ptr;
+}
+
+/*
+ * get_bd - align gpd ptr to target ptr
+ * @args - arg1: dir, arg2: ep number, arg3: target ptr
+ */
+void gpd_ptr_align(u8 dir, u32 num, struct tgpd *ptr)
+{
+ u32 run_next;
+ run_next = true;
+ while (run_next) {
+ if (ptr == get_gpd(dir, num)) {
+ run_next = false;
+ }
+ }
+}
+
+/*
+ * init_gpd_list - initialize gpd management list
+ * @args - arg1: dir, arg2: ep number, arg3: gpd virtual addr, arg4: gpd ioremap addr, arg5: gpd number
+ */
+void init_gpd_list(u8 dir, int num, struct tgpd *ptr, struct tgpd *io_ptr, u32 size)
+{
+ if (dir == USB_DIR_OUT) {
+ rx_gpd_list[num].pstart = (struct tbd *)io_ptr;
+ rx_gpd_list[num].pend = (struct tbd *)(io_ptr + size);
+ rx_gpd_offset[num] = (uintptr_t)io_ptr - (uintptr_t)ptr;
+
+ io_ptr++;
+ rx_gpd_list[num].pnext = (struct tbd *)io_ptr;
+#if 0
+ DBG_I("rx_gpd_list[%d].pstart: %p\n", num, rx_gpd_list[num].pstart);
+ DBG_I("rx_gpd_list[%d].pnext: %p\n", num, rx_gpd_list[num].pnext);
+ DBG_I("rx_gpd_list[%d].pend: %p\n", num, rx_gpd_list[num].pend);
+ DBG_I("rx_gpd_offset[%d]: %p\n", num, (void *)rx_gpd_offset[num]);
+ DBG_I("phy: %p\n", ptr);
+ DBG_I("phy end: %p\n", ptr + size);
+ DBG_I("io_ptr: %p\n", io_ptr);
+ DBG_I("io_ptr end: %p\n", io_ptr + size);
+#endif
+ } else {
+ tx_gpd_list[num].pstart = (struct tbd *)io_ptr;
+ tx_gpd_list[num].pend = (struct tbd *)((u8 *)(io_ptr + size));
+ tx_gpd_offset[num] = (uintptr_t)io_ptr - (uintptr_t)ptr;
+
+ io_ptr++;
+ tx_gpd_list[num].pnext = (struct tbd *)((u8 *)io_ptr);
+#if 0
+
+ DBG_I("tx_gpd_list[%d].pstart: %p\n", num, tx_gpd_list[num].pstart);
+ DBG_I("tx_gpd_list[%d].pnext: %p\n", num, tx_gpd_list[num].pnext);
+ DBG_I("tx_gpd_list[%d].pend: %p\n", num, tx_gpd_list[num].pend);
+ DBG_I("tx_gpd_offset[%d]: %p\n", num, (void *)tx_gpd_offset[num]);
+ DBG_I("phy: %p\n", ptr);
+ DBG_I("phy end: %p\n", ptr); /* no need to add size? */
+ DBG_I("io_ptr: %p\n", io_ptr);
+ DBG_I("io_ptr end: %p\n", io_ptr+size);
+#endif
+ }
+}
+
+/*
+ * free_gpd - free gpd management list
+ * @args - arg1: dir, arg2: ep number
+ */
+void free_gpd(u8 dir, int num)
+{
+
+ if (dir == USB_DIR_OUT) {
+ memset(rx_gpd_list[num].pstart, 0, MAX_GPD_NUM * sizeof(struct tgpd));
+ } else {
+ memset(tx_gpd_list[num].pstart, 0, MAX_GPD_NUM * sizeof(struct tgpd));
+ }
+}
+
+/*
+ * mu3d_hal_alloc_qmu_mem - allocate gpd and bd memory for all ep
+ *
+ */
+void mu3d_hal_alloc_qmu_mem(void) {
+ u32 i, size;
+ struct tgpd *ptr, *io_ptr;
+
+ for (i = 1; i <= MAX_QMU_EP; i++) {
+ /* alloc RX */
+ size = sizeof(struct tgpd);
+ size *= MAX_GPD_NUM;
+ ptr = (struct tgpd*)memalign(64, size);
+ memset(ptr, 0 , size);
+ io_ptr = (struct tgpd*)ptr;
+
+ init_gpd_list(USB_DIR_OUT, i, ptr, io_ptr, MAX_GPD_NUM);
+ rx_gpd_end[i] = io_ptr;
+ memset(rx_gpd_end[i], 0 , sizeof(struct tgpd));
+ TGPD_CLR_FLAGS_HWO(rx_gpd_end[i]);
+ rx_gpd_head[i] = rx_gpd_last[i] = rx_gpd_end[i];
+ DBG_I("RQSAR[%d]: %p\n", i, rx_gpd_end[i]);
+
+ /* alloc TX */
+ size = sizeof(struct tgpd);
+ size *= MAX_GPD_NUM;
+ ptr = (struct tgpd*)memalign(64, size);
+ memset(ptr, 0, size);
+ io_ptr = (struct tgpd*)ptr;
+
+ init_gpd_list(USB_DIR_IN, i, ptr, io_ptr, MAX_GPD_NUM);
+ tx_gpd_end[i] = io_ptr;
+ memset(tx_gpd_end[i], 0 , sizeof(struct tgpd));
+ TGPD_CLR_FLAGS_HWO(tx_gpd_end[i]);
+ tx_gpd_head[i] = tx_gpd_last[i] = tx_gpd_end[i];
+ DBG_I("TQSAR[%d]: %p\n", i, tx_gpd_end[i]);
+ }
+}
+
+/*
+ * mu3d_hal_init_qmu - initialize qmu
+ *
+ */
+void mu3d_hal_init_qmu(void)
+{
+ DBG_I("%s\n", __func__);
+ u32 i;
+
+ /* Initialize QMU Tx/Rx start address. */
+ for (i = 1; i <= MAX_QMU_EP; i++) {
+ MGC_WriteQMU32(MGC_O_QMU_RQSAR(i), virt_to_phy((uintptr_t)rx_gpd_head[i]));
+ MGC_WriteQMU32(MGC_O_QMU_TQSAR(i), virt_to_phy((uintptr_t)tx_gpd_head[i]));
+ DBG_C("U3D_RXQSAR%d: %x, val: %x\n", i, MGC_O_QMU_RQSAR(i), MGC_ReadQMU32(MGC_O_QMU_RQSAR(i)));
+ DBG_C("U3D_TXQSAR%d: %x, val: %x\n", i, MGC_O_QMU_TQSAR(i), MGC_ReadQMU32(MGC_O_QMU_TQSAR(i)));
+
+ arch_clean_invalidate_cache_range((addr_t) tx_gpd_head[i], MAX_GPD_NUM * sizeof(struct tgpd));
+ arch_clean_invalidate_cache_range((addr_t) rx_gpd_head[i], MAX_GPD_NUM * sizeof(struct tgpd));
+
+ tx_gpd_end[i] = tx_gpd_last[i] = tx_gpd_head[i];
+ rx_gpd_end[i] = rx_gpd_last[i] = rx_gpd_head[i];
+
+ gpd_ptr_align(USB_DIR_OUT, i, rx_gpd_end[i]);
+ gpd_ptr_align(USB_DIR_IN, i, tx_gpd_end[i]);
+
+ /* Enable QMU Tx/Rx. */
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, MGC_ReadQUCS32(MGC_O_QUCS_USBGCSR)|USB_QMU_Rx_EN(i));
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, MGC_ReadQUCS32(MGC_O_QUCS_USBGCSR)|USB_QMU_Tx_EN(i));
+ }
+
+ DBG_I("MGC_O_QUCS_USBGCSR %x\n", MGC_ReadQUCS32(MGC_O_QUCS_USBGCSR));
+}
+
+/*
+ * mu3d_hal_cal_checksum - calculate check sum
+ * @args - arg1: data buffer, arg2: data length
+ */
+u8 mu3d_hal_cal_checksum(u8 *data, int len)
+{
+ u8 *pdata, cksum;
+ int i;
+
+ *(data + 1) = 0x0;
+ pdata = data;
+ cksum = 0;
+ for (i = 0; i < len; i++) {
+ cksum += *(pdata + i);
+ }
+ return 0xFF - cksum;
+}
+
+/*
+ * mu3d_hal_resume_qmu - resume qmu function
+ * @args - arg1: ep number, arg2: dir
+ */
+void mu3d_hal_resume_qmu(int q_ep_num, u8 dir) {
+ DBG_I("%s\n", __func__);
+ if(dir == USB_DIR_OUT) {
+ //DBG_I("USB_QMU_Resume USB_RX %x \n", (USB_HW_QMU_OFF + MGC_O_QMU_RQCSR(ep_num)));
+ MGC_WriteQMU32(MGC_O_QMU_RQCSR(q_ep_num), DQMU_QUE_RESUME);
+ if(!MGC_ReadQMU32(MGC_O_QMU_RQCSR(q_ep_num))){
+ DBG_I("%s: RXQCSR1 val: %x\n", __func__, MGC_ReadQMU32(MGC_O_QMU_RQCSR(q_ep_num)));
+ MGC_WriteQMU32(MGC_O_QMU_RQCSR(q_ep_num), DQMU_QUE_RESUME);
+ }
+ } else {
+ //DBG_I("USB_QMU_Resume USB_TX %x \n", (USB_HW_QMU_OFF + MGC_O_QMU_TQCSR(ep_num)));
+ MGC_WriteQMU32(MGC_O_QMU_TQCSR(q_ep_num), DQMU_QUE_RESUME);
+ if (!MGC_ReadQMU32(MGC_O_QMU_TQCSR(q_ep_num))) { //judge if Queue is still inactive
+ DBG_I("%s: TXQCSR1 val: %x\n", __func__, MGC_ReadQMU32(MGC_O_QMU_TQCSR(q_ep_num)));
+ MGC_WriteQMU32(MGC_O_QMU_TQCSR(q_ep_num), DQMU_QUE_RESUME);
+ }
+ }
+}
+
+/*
+ * mu3d_hal_prepare_tx_gpd - prepare tx gpd/bd
+ * @args - arg1: gpd address, arg2: data buffer address, arg3: data length, arg4: ep number, arg5: with bd or not, arg6: write hwo bit or not, arg7: write ioc bit or not
+ */
+struct tgpd* mu3d_hal_prepare_tx_gpd(struct tgpd *gpd, u8 *pbuf, u32 data_len, u8 ep_num, u8 _is_bdp, u8 ishwo, u8 ioc, u8 bps, u8 zlp) {
+#if defined(SUPPORT_VA)
+ u8 *vbuffer;
+#endif
+
+ DBG_C("%s: ep_num: %d, pbuf: %p, data_len: %x, zlp: %x\n", __func__, (int)ep_num, pbuf, data_len, (u32)zlp);
+
+ arch_clean_invalidate_cache_range((addr_t) gpd, sizeof(struct tgpd));
+
+ if (!_is_bdp) {
+ TGPD_SET_DATA(gpd, (u8 *)(virt_to_phy((uintptr_t)pbuf)));
+ TGPD_CLR_FORMAT_BDP(gpd);
+ } else {
+ DBG_I("_is_bdp error\n");
+ }
+
+ TGPD_SET_BUF_LEN(gpd, data_len);
+ TGPD_SET_EXT_LEN(gpd, 0);
+
+ if (zlp) {
+ TGPD_SET_FORMAT_ZLP(gpd);
+ } else {
+ TGPD_CLR_FORMAT_ZLP(gpd);
+ }
+
+ if (bps) {
+ TGPD_SET_FORMAT_BPS(gpd);
+ } else {
+ TGPD_CLR_FORMAT_BPS(gpd);
+ }
+
+ if (ioc) {
+ TGPD_SET_FORMAT_IOC(gpd);
+ } else {
+ TGPD_CLR_FORMAT_IOC(gpd);
+ }
+
+ /* Create next GPD */
+ tx_gpd_end[ep_num] = get_gpd(USB_DIR_IN, ep_num);
+ DBG_I("Malloc Tx 01 (GPD+EXT) (tx_gpd_end): 0x%x\n", (u32)(uintptr_t)tx_gpd_end[ep_num]);
+
+ arch_clean_invalidate_cache_range((addr_t) tx_gpd_end[ep_num], sizeof(struct tgpd));
+ memset(tx_gpd_end[ep_num], 0 , sizeof(struct tgpd));
+ TGPD_CLR_FLAGS_HWO(tx_gpd_end[ep_num]);
+ TGPD_SET_NEXT(gpd, (struct tgpd *)(virt_to_phy((uintptr_t)tx_gpd_end[ep_num])));
+
+ if (ishwo) {
+ TGPD_SET_CHKSUM(gpd, CHECKSUM_LENGTH);
+ TGPD_SET_FLAGS_HWO(gpd);
+ } else {
+ TGPD_CLR_FLAGS_HWO(gpd);
+ TGPD_SET_CHKSUM_HWO(gpd, CHECKSUM_LENGTH);
+ }
+
+ /* gpd end */
+ arch_clean_invalidate_cache_range((addr_t) gpd, sizeof(struct tgpd));
+
+ return gpd;
+}
+
+/*
+ * mu3d_hal_prepare_rx_gpd - prepare rx gpd/bd
+ * @args - arg1: gpd address, arg2: data buffer address, arg3: data length, arg4: ep number, arg5: with bd or not, arg6: write hwo bit or not, arg7: write ioc bit or not
+ */
+struct tgpd* mu3d_hal_prepare_rx_gpd(struct tgpd *gpd, u8 *pbuf, u32 data_len, u8 ep_num, u8 _is_bdp, u8 ishwo, u8 ioc, u8 bps, u32 max_pkt_size) {
+ DBG_C("%s: GPD: %p, ep_num: %d, pbuf: %p, data_len: %x, _is_bdp: %d, ishwo: %d, ioc: %d, bps: %d\n", __func__, gpd, (int)ep_num, pbuf, data_len, _is_bdp, ishwo, ioc, bps);
+
+ arch_clean_invalidate_cache_range((addr_t) gpd, sizeof(struct tgpd));
+
+ if (!_is_bdp) {
+ TGPD_SET_DATA(gpd, (u8 *)(virt_to_phy((uintptr_t)pbuf)));
+ TGPD_CLR_FORMAT_BDP(gpd);
+ } else {
+ DBG_I("_is_bdp error\n");
+ }
+
+ if (data_len < gpd_buf_size)
+ TGPD_SET_DATABUF_LEN(gpd, data_len); /* or length?? */
+ else
+ TGPD_SET_DATABUF_LEN(gpd, gpd_buf_size);
+
+ TGPD_SET_BUF_LEN(gpd, 0);
+
+ if (bps) {
+ TGPD_SET_FORMAT_BPS(gpd);
+ } else {
+ TGPD_CLR_FORMAT_BPS(gpd);
+ }
+
+ if (ioc) {
+ TGPD_SET_FORMAT_IOC(gpd);
+ } else {
+ TGPD_CLR_FORMAT_IOC(gpd);
+ }
+
+ rx_gpd_end[ep_num] = get_gpd(USB_DIR_OUT, ep_num);
+ memset(rx_gpd_end[ep_num], 0, sizeof(struct tgpd));
+ DBG_I("Rx Next GPD 0x%x\n", (u32)(uintptr_t)rx_gpd_end[ep_num]);
+ TGPD_CLR_FLAGS_HWO(rx_gpd_end[ep_num]);
+
+ TGPD_SET_NEXT(gpd, (struct tgpd *)(virt_to_phy((uintptr_t)rx_gpd_end[ep_num])));
+
+ if (ishwo) {
+ TGPD_SET_CHKSUM(gpd, CHECKSUM_LENGTH);
+ TGPD_SET_FLAGS_HWO(gpd);
+ } else {
+ TGPD_CLR_FLAGS_HWO(gpd);
+ TGPD_SET_CHKSUM_HWO(gpd, CHECKSUM_LENGTH);
+ }
+
+ DBG_I("Rx gpd info { HWO %d, Next_GPD %x ,databuf_length %d, DataBuffer %x, Recived Len %d, Endpoint %d, TGL %d, ZLP %d}\n",
+ (u32)TGPD_GET_FLAG(gpd), (u32)(uintptr_t)TGPD_GET_NEXT(gpd),
+ (u32)TGPD_GET_DATABUF_LEN(gpd), (u32)(uintptr_t)TGPD_GET_DATA(gpd),
+ (u32)TGPD_GET_BUF_LEN(gpd), (u32)TGPD_GET_EPaddr(gpd),
+ (u32)TGPD_GET_TGL(gpd), (u32)TGPD_GET_ZLP(gpd));
+
+ arch_clean_invalidate_cache_range((addr_t) gpd, sizeof(struct tgpd));
+ return gpd;
+}
+
+/*
+ * mu3d_hal_insert_transfer_gpd - insert new gpd/bd
+ * @args - arg1: ep number, arg2: dir, arg3: data buffer, arg4: data length, arg5: write hwo bit or not, arg6: write ioc bit or not
+ */
+void mu3d_hal_insert_transfer_gpd(int ep_num, u8 dir, u8* buf, u32 count, u8 ishwo, u8 ioc, u8 bps, u8 zlp, u32 max_pkt_size) {
+ struct tgpd* gpd;
+
+ DBG_I("%s: ep_num: %d, dir: %d, buf: %x, count: %x, ishwo: %d, ioc: :%d, bps: %d, zlp: %x, maxp: %x\n", __func__, (int)ep_num, dir, (u32)(uintptr_t)buf, count, ishwo, ioc, bps, (u32)zlp, (u32)max_pkt_size);
+
+ if (dir == USB_DIR_IN) {
+ gpd = tx_gpd_end[ep_num];
+ DBG_I("TX gpd: %x\n", (unsigned int)(uintptr_t)gpd);
+ /* is_bdp = 0; We need to use BD because for mass storage, the largest data > GPD limitation */
+ mu3d_hal_prepare_tx_gpd(gpd, buf, count, ep_num, 0, ishwo, ioc, bps, zlp);
+ } else if (dir == USB_DIR_OUT) {
+ gpd = rx_gpd_end[ep_num];
+ DBG_I("RX gpd: %x\n", (unsigned int)(uintptr_t)gpd);
+ /* is_bdp = 0; We need to use BD because for mass storage, the largest data > GPD limitation */
+ mu3d_hal_prepare_rx_gpd(gpd, buf, count, ep_num, 0, ishwo, ioc, bps, max_pkt_size);
+ }
+}
+
+/*
+ * mu3d_hal_start_qmu - start qmu function (QMU flow : mu3d_hal_init_qmu ->mu3d_hal_start_qmu -> mu3d_hal_insert_transfer_gpd -> mu3d_hal_resume_qmu)
+ * @args - arg1: ep number, arg2: dir
+ */
+void usb_start_qmu(int q_ep_num, u8 dir)
+{
+ u32 qcr;
+ u32 txZLP, rxZLP;
+ u32 isEmptyCheck = 0;
+
+ DBG_I("%s: dir: %x\n", __func__, dir);
+
+#ifdef CFG_RX_ZLP_EN
+ rxZLP = 1;
+#else
+ rxZLP = 0;
+#endif
+
+#if (TXZLP == HW_MODE)
+ txZLP = 1;
+ //qcr = readl(U3D_QCR1);
+ //writel(qcr &~ QMU_TX_ZLP(q_ep_num), U3D_QCR1);
+ //qcr = readl(U3D_QCR2);
+ //writel(qcr | QMU_TX_ZLP(q_ep_num), U3D_QCR2);
+#elif (TXZLP == GPD_MODE)
+ txZLP = 0;
+ //qcr = readl(U3D_QCR1);
+ //writel(qcr | QMU_TX_ZLP(q_ep_num), U3D_QCR1);
+#endif
+
+ if (dir == USB_DIR_IN) {
+ qcr= MGC_ReadQMU32(MGC_O_QMU_QCR0);
+ MGC_WriteQMU32(MGC_O_QMU_QCR0, qcr|DQMU_TQCS_EN(q_ep_num));
+
+ if(txZLP){
+ qcr = MGC_ReadQMU32(MGC_O_QMU_QCR2);
+ MGC_WriteQMU32(MGC_O_QMU_QCR2, qcr|DQMU_TX_ZLP(q_ep_num));
+ }
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_QIMCR, DQMU_M_TX_DONE(q_ep_num)|DQMU_M_TQ_EMPTY|DQMU_M_TXQ_ERR|DQMU_M_TXEP_ERR);
+
+ if(isEmptyCheck){
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TEPEMPMCR, DQMU_M_TX_EMPTY(q_ep_num));
+ }else{
+ MGC_WriteQIRQ32(MGC_O_QIRQ_QIMSR, DQMU_M_TQ_EMPTY);
+ }
+
+ qcr = DQMU_M_TX_LEN_ERR(q_ep_num);
+ qcr |= DQMU_M_TX_GPDCS_ERR(q_ep_num) | DQMU_M_TX_BDCS_ERR(q_ep_num);
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TQEIMCR, qcr);
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_TEPEIMCR, DQMU_M_TX_EP_ERR(q_ep_num));
+
+ MGC_WriteQMU32(MGC_O_QMU_TQCSR(q_ep_num), DQMU_QUE_START);
+
+ } else if (dir == USB_DIR_OUT) {
+ qcr = MGC_ReadQMU32(MGC_O_QMU_QCR0);
+ MGC_WriteQMU32(MGC_O_QMU_QCR0, qcr | DQMU_RQCS_EN(q_ep_num));
+#if 0
+ if (rxZLP)
+ {
+ qcr = MGC_ReadQMU32(MGC_O_QMU_QCR3);
+ MGC_WriteQMU32(MGC_O_QMU_QCR3, qcr | DQMU_RX_ZLP(q_ep_num));
+ } else {
+ qcr = MGC_ReadQMU32(MGC_O_QMU_QCR3);
+ MGC_WriteQMU32(MGC_O_QMU_QCR3, qcr &~ DQMU_RX_ZLP(q_ep_num));
+ }
+#endif
+ MGC_WriteQIRQ32(MGC_O_QIRQ_QIMCR, DQMU_M_RX_DONE(q_ep_num)|DQMU_M_RQ_EMPTY|DQMU_M_RXQ_ERR|DQMU_M_RXEP_ERR);
+
+ if(isEmptyCheck){
+ MGC_WriteQIRQ32(MGC_O_QIRQ_REPEMPMCR, DQMU_M_RX_EMPTY(q_ep_num));
+ }else{
+ MGC_WriteQIRQ32(MGC_O_QIRQ_QIMSR, DQMU_M_RQ_EMPTY);
+ }
+
+ qcr = DQMU_M_RX_LEN_ERR(q_ep_num);
+ qcr |= DQMU_M_RX_GPDCS_ERR(q_ep_num);
+ qcr |= rxZLP ? DQMU_M_RX_ZLP_ERR(q_ep_num) : 0;
+ MGC_WriteQIRQ32(MGC_O_QIRQ_RQEIMCR, qcr);
+
+ MGC_WriteQIRQ32(MGC_O_QIRQ_REPEIMCR, DQMU_M_RX_EP_ERR(q_ep_num));
+
+ MGC_WriteQMU32(MGC_O_QMU_RQCSR(q_ep_num), DQMU_QUE_START);
+ }
+}
+
+/*
+ * mu3d_hal_stop_qmu - stop qmu function (after qmu stop, fifo should be flushed)
+ * @args - arg1: ep number, arg2: dir
+ */
+void mu3d_hal_stop_qmu(int q_ep_num, u8 dir) {
+ DBG_I("%s\n", __func__);
+ if(dir == USB_DIR_IN){
+ if(MGC_ReadQMU16(MGC_O_QMU_TQCSR(q_ep_num))&DQMU_QUE_ACTIVE){
+ MGC_WriteQMU32(MGC_O_QMU_TQCSR(q_ep_num), DQMU_QUE_STOP);
+ while(MGC_ReadQMU16(MGC_O_QMU_TQCSR(q_ep_num))&DQMU_QUE_ACTIVE);
+ DBG_I("Stop Tx Queue %d!\n", q_ep_num);
+ }else{
+ DBG_I("Tx Queue %d InActive Now, Don't need to stop!\n", q_ep_num);
+ }
+ } else {
+ if(MGC_ReadQMU16(MGC_O_QMU_RQCSR(q_ep_num))&DQMU_QUE_ACTIVE){
+ MGC_WriteQMU32(MGC_O_QMU_RQCSR(q_ep_num), DQMU_QUE_STOP);
+ while(MGC_ReadQMU16(MGC_O_QMU_RQCSR(q_ep_num))&DQMU_QUE_ACTIVE);
+ DBG_I("Stop Rx Queue %d!\n", q_ep_num);
+ }else{
+ DBG_I("Rx Queue %d InActive Now, Don't need to stop!\n", q_ep_num);
+ }
+ }
+}
+
+/*
+ * mu3d_hal_reset_qmu_ep - clear toggle(or sequence) number
+ * @args - arg1: ep number, arg2: dir
+ */
+void mu3d_hal_reset_qmu_ep(int q_ep_num, u8 dir)
+{
+ DBG_I("%s\n", __func__);
+
+ if (dir == USB_DIR_IN) {
+
+// ep_rst = BIT16 << q_ep_num;
+// MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, MGC_ReadQUCS32(MGC_O_QUCS_USBGCSR)|USB_QMU_Tx_EN(i));
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, DQMU_SW_RESET);
+ spin(1000);
+ } else {
+
+// ep_rst = 1 << q_ep_num;
+// MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, MGC_ReadQUCS32(MGC_O_QUCS_USBGCSR)|USB_QMU_Tx_EN(i));
+ MGC_WriteQUCS32(MGC_O_QUCS_USBGCSR, DQMU_SW_RESET);
+ spin(1000);
+ }
+}
+
+/*
+ * flush_qmu - stop qmu and align qmu start ptr t0 current ptr
+ * @args - arg1: ep number, arg2: dir
+ */
+void mu3d_hal_flush_qmu(int q_ep_num, u8 dir) {
+ struct tgpd *gpd_current;
+ struct udc_endpoint *ept;
+ struct urb *urb;
+ //struct USB_REQ *req = mu3d_hal_get_req(q_ep_num, dir);
+
+ ept = mt_find_ep(q_ep_num, dir);
+
+ DBG_I("%s\n", __func__);
+
+ if (dir == USB_DIR_IN) {
+ DBG_I("flush_qmu USB_DIR_IN\n");
+ urb = ept->tx_urb;
+ mu3d_hal_stop_qmu(q_ep_num, USB_DIR_IN);
+ gpd_current = (struct tgpd*)((uintptr_t)(MGC_ReadQMU32(MGC_O_QMU_TQCPR(q_ep_num))));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+
+ DBG_I("(MGC_O_QMU_TQCPR gpd_current: %p)\n", gpd_current);
+
+ if (!gpd_current) {
+ gpd_current = (struct tgpd*)((uintptr_t)(MGC_ReadQMU32(MGC_O_QMU_TQSAR(q_ep_num))));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+ }
+
+ DBG_I("(MGC_O_QMU_TQSAR gpd_current: %p)\n", gpd_current);
+
+ tx_gpd_end[q_ep_num] = tx_gpd_last[q_ep_num] = gpd_current;
+
+ gpd_ptr_align(dir, q_ep_num, tx_gpd_end[q_ep_num]);
+ free_gpd(dir, q_ep_num);
+
+ arch_clean_invalidate_cache_range((addr_t) tx_gpd_list[q_ep_num].pstart, MAX_GPD_NUM * sizeof(struct tgpd));
+ MGC_WriteQMU32(MGC_O_QMU_TQSAR(q_ep_num), virt_to_phy((uintptr_t)tx_gpd_last[q_ep_num]));
+
+ urb->qmu_complete = true;
+ DBG_I("TxQ %d Flush Now!\n", q_ep_num);
+ } else if (dir == USB_DIR_OUT) {
+ urb = ept->rcv_urb;
+ mu3d_hal_stop_qmu(q_ep_num, USB_DIR_OUT);
+ gpd_current = (struct tgpd *)((uintptr_t)(MGC_ReadQMU32(MGC_O_QMU_RQCPR(q_ep_num))));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+
+ if (!gpd_current) {
+ gpd_current = (struct tgpd *)((uintptr_t)(MGC_ReadQMU32(MGC_O_QMU_RQSAR(q_ep_num))));
+ gpd_current = (struct tgpd *)(phy_to_virt((uintptr_t)gpd_current));
+ }
+
+ rx_gpd_end[q_ep_num] = rx_gpd_last[q_ep_num] = gpd_current;
+
+ gpd_ptr_align(dir, q_ep_num, rx_gpd_end[q_ep_num]);
+ free_gpd(dir, q_ep_num);
+
+ arch_clean_invalidate_cache_range((addr_t) rx_gpd_list[q_ep_num].pstart, MAX_GPD_NUM * sizeof(struct tgpd));
+ MGC_WriteQMU32(MGC_O_QMU_RQSAR(q_ep_num), virt_to_phy((uintptr_t)rx_gpd_end[q_ep_num]));
+
+ urb->qmu_complete = true;
+ DBG_I("RxQ %d Flush Now!\n", q_ep_num);
+ }
+
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.h b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.h
new file mode 100644
index 0000000..42a5226
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/mt_usb_qmu.h
@@ -0,0 +1,492 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2015. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef MTK_QMU_H
+#define MTK_QMU_H
+
+#include <platform/mt_reg_base.h>
+
+#define USB_base USB_BASE
+
+#define USB_HW_QMU_BASE 0x86000800
+#define USB_HW_QMU_LENGTH 0x500
+/// @brief Define DMAQ Register Bass Address
+/// @Author_Name:tianhao.fei 4/29/2010
+/// @{
+
+#define USB_QMUBASE USB_base + 0x800
+#define USB_QISAR USB_base + 0xc00
+#define USB_QIMR USB_base + 0xc04
+
+#define USB_HW_QMU_OFF USB_QMUBASE + 0x0000
+#define USB_HW_QUCS_OFF USB_QMUBASE + 0x0300
+#define USB_HW_QIRQ_OFF USB_QMUBASE + 0x0400
+#define USB_HW_QDBG_OFF USB_QMUBASE + 0x04F0
+
+/// @}
+//#define GPD_LEN_ALIGNED (32) /* Note: ARM should align cache line size */
+#define GPD_LEN_ALIGNED (64) /* > sizeof (TGPD) + sizeof (list_head)*/
+// KOBE , modify
+
+#define RXQ_NUM 1
+#define TXQ_NUM 1
+
+
+/// @brief Define DMAQ Register Offset
+/// @Author_Name:tianhao.fei 4/29/2010
+/// @{
+#define MGC_O_QMU_QCR0 0x0000
+#define MGC_O_QMU_QCR2 0x0008
+#define MGC_O_QMU_QCR3 0x000C
+
+#define MGC_O_QMU_RQCSR0 0x0010
+#define MGC_O_QMU_RQSAR0 0x0014
+#define MGC_O_QMU_RQCPR0 0x0018
+#define MGC_O_QMU_RQCSR(n) (MGC_O_QMU_RQCSR0+0x0010*((n)-1))
+#define MGC_O_QMU_RQSAR(n) (MGC_O_QMU_RQSAR0+0x0010*((n)-1))
+#define MGC_O_QMU_RQCPR(n) (MGC_O_QMU_RQCPR0+0x0010*((n)-1))
+
+
+#define MGC_O_QMU_RQTR_BASE 0x0090
+#define MGC_O_QMU_RQTR(n) (MGC_O_QMU_RQTR_BASE+0x4*((n)-1))
+#define MGC_O_QMU_RQLDPR0 0x0100
+#define MGC_O_QMU_RQLDPR(n) (MGC_O_QMU_RQLDPR0+0x4*((n)-1))
+
+
+#define MGC_O_QMU_TQCSR0 0x0200
+#define MGC_O_QMU_TQSAR0 0x0204
+#define MGC_O_QMU_TQCPR0 0x0208
+#define MGC_O_QMU_TQCSR(n) (MGC_O_QMU_TQCSR0+0x0010*((n)-1))
+#define MGC_O_QMU_TQSAR(n) (MGC_O_QMU_TQSAR0+0x0010*((n)-1))
+#define MGC_O_QMU_TQCPR(n) (MGC_O_QMU_TQCPR0+0x0010*((n)-1))
+
+#define MGC_O_QMU_QAR 0x0300
+#define MGC_O_QUCS_USBGCSR 0x0000
+#ifdef MTK_WDMAQ
+/*wimax only*/
+#define MGC_O_QUCS_TQUSBSC_BASE 0x0080
+#define MGC_O_QUCS_TQUSBSC(n) (MGC_O_QUCS_TQUSBSC_BASE+0x4*((n)-1))
+#define MGC_O_QUCS_FW1 0x0004
+#define MGC_O_QUCS_FW2 0x0008
+/*end*/
+#endif
+#define MGC_O_QIRQ_QISAR 0x0000
+#define MGC_O_QIRQ_QIMR 0x0004
+#define MGC_O_QIRQ_QIMCR 0x0008
+#define MGC_O_QIRQ_QIMSR 0x000C
+#ifdef MTK_WDMAQ
+/*wimax only*/
+#define MGC_O_QIRQ_QSISAR 0x0010
+#define MGC_O_QIRQ_DSIMR 0x0014
+#define MGC_O_QIRQ_DSIMCR 0x0018
+#define MGC_O_QIRQ_DSIMSR 0x001C
+#define MGC_O_QIRQ_DSICR 0x0020
+/*end*/
+#endif
+#define MGC_O_QIRQ_IOCDISR 0x0030
+#define MGC_O_QIRQ_TEPEMPR 0x0060
+#define MGC_O_QIRQ_TEPEMPMR 0x0064
+#define MGC_O_QIRQ_TEPEMPMCR 0x0068
+#define MGC_O_QIRQ_TEPEMPMSR 0x006C
+#define MGC_O_QIRQ_REPEMPR 0x0070
+#define MGC_O_QIRQ_REPEMPMR 0x0074
+#define MGC_O_QIRQ_REPEMPMCR 0x0078
+#define MGC_O_QIRQ_REPEMPMSR 0x007C
+
+#define MGC_O_QIRQ_RQEIR 0x0090
+#define MGC_O_QIRQ_RQEIMR 0x0094
+#define MGC_O_QIRQ_RQEIMCR 0x0098
+#define MGC_O_QIRQ_RQEIMSR 0x009C
+#define MGC_O_QIRQ_REPEIR 0x00A0
+#define MGC_O_QIRQ_REPEIMR 0x00A4
+#define MGC_O_QIRQ_REPEIMCR 0x00A8
+#define MGC_O_QIRQ_REPEIMSR 0x00AC
+#define MGC_O_QIRQ_TQEIR 0x00B0
+#define MGC_O_QIRQ_TQEIMR 0x00B4
+#define MGC_O_QIRQ_TQEIMCR 0x00B8
+#define MGC_O_QIRQ_TQEIMSR 0x00BC
+#define MGC_O_QIRQ_TEPEIR 0x00C0
+#define MGC_O_QIRQ_TEPEIMR 0x00C4
+#define MGC_O_QIRQ_TEPEIMCR 0x00C8
+#define MGC_O_QIRQ_TEPEIMSR 0x00CC
+
+
+#define MGC_O_QDBG_DFCR 0x0000
+#define MGC_O_QDBG_DFMR 0x0004
+/// @}
+
+/// @brief Queue Control value Definition
+/// @Author_Name:tianhao.fei 4/29/2010
+/// @{
+#define DQMU_QUE_START 0x00000001
+#define DQMU_QUE_RESUME 0x00000002
+#define DQMU_QUE_STOP 0x00000004
+#define DQMU_QUE_ACTIVE 0x00008000
+/// @}
+
+/// @brief USB QMU Special Control USBGCSR value Definition
+/// @Author_Name:tianhao.fei 4/29/2010
+/// @{
+#define USB_QMU_Tx0_EN 0x00000001
+#define USB_QMU_Tx_EN(n) (USB_QMU_Tx0_EN<<((n)-1))
+#if 1 //CC_TEST
+#define USB_QMU_Rx0_EN 0x00010000
+#else
+#define USB_QMU_Rx0_EN 0x00000020
+#endif
+#define USB_QMU_Rx_EN(n) (USB_QMU_Rx0_EN<<((n)-1))
+#define USB_QMU_HIFEVT_EN 0x00000100
+#define USB_QMU_HIFCMD_EN 0x01000000
+#define DQMU_SW_RESET 0x00010000
+#define DQMU_CS16B_EN 0x80000000
+#define DQMU_TQ0CS_EN 0x00010000
+#define DQMU_TQCS_EN(n) (DQMU_TQ0CS_EN<<((n)-1))
+#define DQMU_RQ0CS_EN 0x00000001
+#define DQMU_RQCS_EN(n) (DQMU_RQ0CS_EN<<((n)-1))
+#define DQMU_TX0_ZLP 0x01000000
+#define DQMU_TX_ZLP(n) (DQMU_TX0_ZLP<<((n)-1))
+#define DQMU_TX0_MULTIPLE 0x00010000
+#define DQMU_TX_MULTIPLE(n) (DQMU_TX0_MULTIPLE<<((n)-1))
+#ifdef MTK_WDMAQ
+#define DQMU_TX_PADDING 0x00000002
+#define DQMU_TX_SDUHDR 0x00000001
+#endif
+#define DQMU_RX0_MULTIPLE 0x00010000
+#define DQMU_RX_MULTIPLE(n) (DQMU_RX0_MULTIPLE<<((n)-1))
+#ifdef MTK_WDMAQ
+#define DQMU_RX_SDUHDR 0x00000001
+#endif
+#define DQMU_RX0_ZLP 0x01000000
+#define DQMU_RX_ZLP(n) (DQMU_RX0_ZLP<<((n)-1))
+
+#define DQMU_M_TXEP_ERR 0x10000000
+#define DQMU_M_TXQ_ERR 0x08000000
+#define DQMU_M_RXEP_ERR 0x04000000
+#define DQMU_M_RXQ_ERR 0x02000000
+#define DQMU_M_RQ_EMPTY 0x00020000
+#define DQMU_M_TQ_EMPTY 0x00010000
+#define DQMU_M_RX0_EMPTY 0x00000001
+#define DQMU_M_RX_EMPTY(n) (DQMU_M_RX0_EMPTY<<((n)-1))
+#define DQMU_M_TX0_EMPTY 0x00000001
+#define DQMU_M_TX_EMPTY(n) (DQMU_M_TX0_EMPTY<<((n)-1))
+#define DQMU_M_RX0_DONE 0x00000100
+#define DQMU_M_RX_DONE(n) (DQMU_M_RX0_DONE<<((n)-1))
+#define DQMU_M_TX0_DONE 0x00000001
+#define DQMU_M_TX_DONE(n) (DQMU_M_TX0_DONE<<((n)-1))
+
+#define DQMU_M_RX0_ZLP_ERR 0x01000000
+#define DQMU_M_RX_ZLP_ERR(n) (DQMU_M_RX0_ZLP_ERR<<((n)-1))
+#ifdef MTK_WDMAQ
+#define DQMU_M_RX0_HDR_ERR 0x00010000
+#define DQMU_M_RX_HDR_ERR(n) (DQMU_M_RX0_HDR_ERR<<((n)-1))
+#endif
+#define DQMU_M_RX0_LEN_ERR 0x00000100
+#define DQMU_M_RX_LEN_ERR(n) (DQMU_M_RX0_LEN_ERR<<((n)-1))
+#define DQMU_M_RX0_GPDCS_ERR 0x00000001
+#define DQMU_M_RX_GPDCS_ERR(n) (DQMU_M_RX0_GPDCS_ERR<<((n)-1))
+
+#define DQMU_M_TX0_LEN_ERR 0x00010000
+#define DQMU_M_TX_LEN_ERR(n) (DQMU_M_TX0_LEN_ERR<<((n)-1))
+#define DQMU_M_TX0_GPDCS_ERR 0x00000100
+#define DQMU_M_TX_GPDCS_ERR(n) (DQMU_M_TX0_GPDCS_ERR<<((n)-1))
+#define DQMU_M_TX0_BDCS_ERR 0x00000001
+#define DQMU_M_TX_BDCS_ERR(n) (DQMU_M_TX0_BDCS_ERR<<((n)-1))
+
+#define DQMU_M_TX0_EP_ERR 0x00000001
+#define DQMU_M_TX_EP_ERR(n) (DQMU_M_TX0_EP_ERR<<((n)-1))
+
+#define DQMU_M_RX0_EP_ERR 0x00000001
+#define DQMU_M_RX_EP_ERR(n) (DQMU_M_RX0_EP_ERR<<((n)-1))
+#define DQMU_M_RQ_DIS_IOC(n) (0x100<<((n)-1))
+/// @}
+
+
+/**
+ * @brief Read a 8-bit register from the core
+ * @param _pBase core base address in memory
+ * @param _offset offset into the core's register space
+ * @return 16-bit datum
+ */
+#define MGC_ReadQMU8(_offset) \
+ DRV_Reg8((USB_HW_QMU_OFF + _offset))
+
+#define MGC_ReadQUCS8(base,_offset) \
+ DRV_Reg8((USB_HW_QUCS_OFF + _offset))
+
+#define MGC_ReadQIRQ8(base,_offset) \
+ DRV_Reg8((USB_HW_QIRQ_OFF + _offset))
+
+/**
+ * @brief Read a 16-bit register from the core
+ * @param _pBase core base address in memory
+ * @param _offset offset into the core's register space
+ * @return 16-bit datum
+ */
+#define MGC_ReadQMU16(_offset) \
+ DRV_Reg((USB_HW_QMU_OFF + _offset))
+
+#define MGC_ReadQUCS16(_offset) \
+ DRV_Reg((USB_HW_QUCS_OFF + _offset))
+
+#define MGC_ReadQIRQ16(_offset) \
+ DRV_Reg((USB_HW_QIRQ_OFF + _offset))
+
+/**
+ * @brief Read a 32-bit register from the core
+ * @param _pBase core base address in memory
+ * @param _offset offset into the core's register space
+ * @return 32-bit datum
+ */
+#define MGC_ReadQMU32(_offset) \
+ DRV_Reg32((USB_HW_QMU_OFF + _offset))
+
+#define MGC_ReadQUCS32(_offset) \
+ DRV_Reg32((USB_HW_QUCS_OFF + _offset))
+
+#define MGC_ReadQIRQ32(_offset) \
+ DRV_Reg32((USB_HW_QIRQ_OFF + _offset))
+
+/**
+ * @briefWrite a 32-bit core register
+ * @param _pBase core base address in memory
+ * @param _offset offset into the core's register space
+ * @param _data 32-bit datum
+ */
+#define MGC_WriteQMU32(_offset, _data) \
+ DRV_WriteReg32((USB_HW_QMU_OFF + _offset), _data)
+
+#define MGC_WriteQUCS32(_offset, _data) \
+ DRV_WriteReg32((USB_HW_QUCS_OFF + _offset), _data)
+
+#define MGC_WriteQIRQ32(_offset, _data) \
+ DRV_WriteReg32((USB_HW_QIRQ_OFF + _offset), _data)
+
+/**
+ * TGPD
+ */
+typedef struct _TGPD {
+ unsigned char flag;
+ unsigned char chksum;
+ unsigned short DataBufferLen; /*Rx Allow Length*/
+ struct _TGPD* pNext;
+ unsigned char* pBuf;
+ unsigned short bufLen;
+ unsigned char ExtLength;
+ unsigned char ZTepFlag;
+} TGPD, *PGPD;
+
+typedef struct {
+ TGPD gpd[2];
+ unsigned char cur_gpd_index;
+ TGPD *cur_ptr_gpd;
+} gpd_pool;
+
+
+/**
+ * TBD
+ */
+typedef struct _TBD {
+ unsigned char flag;
+ unsigned char chksum;
+ unsigned short reserved1;
+ struct _TBD *pNext;
+ unsigned char* pBuf;
+ unsigned short bufLen;
+ unsigned char extLen;
+ unsigned char reserved2;
+} TBD, *PBD;
+/// @}
+
+#define GPD_BUF_SIZE 65532
+#define GPD_BUF_SIZE_ALIGN 64512 /* 63 * 1024 */
+#define BD_BUF_SIZE 32768 //set to half of 64K of max size
+
+void qmu_done_interrupt(u32 qmu_val);
+void qmu_handler(u32 qmu_val);
+
+
+struct tgpd {
+ u8 flag;
+ u8 chksum;
+ u16 databuf_len; /*Rx Allow Length*/
+ unsigned int pnext;
+ unsigned int pBuf;
+ u16 bufLen;
+ u8 ExtLength;
+ u8 ZTepFlag;
+};
+
+struct tbd {
+ u8 flag;
+ u8 chksum;
+ u16 databuf_len; /* Rx Allow Length */
+ struct tbd *pnext;
+ u8 *pBuf;
+ u16 bufLen;
+ u8 extLen;
+ u8 reserved;
+};
+
+struct gpd_range {
+ struct tbd *pnext;
+ struct tbd *pstart;
+ struct tbd *pend;
+};
+
+#define AT_GPD_EXT_LEN 256
+#define AT_BD_EXT_LEN 256
+//#define MAX_GPD_NUM 30 /* we've got problem when gpd is larger */
+#define MAX_GPD_NUM 4
+//#define MAX_BD_NUM 500
+#define MAX_BD_NUM 3
+#define STRESS_IOC_TH 8
+#define STRESS_GPD_TH 24
+#define RANDOM_STOP_DELAY 80
+#define STRESS_DATA_LENGTH 1024*64 //1024*16
+
+#define NO_ZLP 0
+#define HW_MODE 1
+#define GPD_MODE 2
+
+#define TXZLP HW_MODE
+
+#define MAX_QMU_EP 1
+
+#define TGPD_FLAGS_HWO 0x01
+#define TGPD_IS_FLAGS_HWO(_pd) (((struct tgpd *)_pd)->flag & TGPD_FLAGS_HWO)
+#define TGPD_SET_FLAGS_HWO(_pd) (((struct tgpd *)_pd)->flag |= TGPD_FLAGS_HWO)
+#define TGPD_CLR_FLAGS_HWO(_pd) (((struct tgpd *)_pd)->flag &= (~TGPD_FLAGS_HWO))
+#define TGPD_FORMAT_BDP 0x02
+#define TGPD_IS_FORMAT_BDP(_pd) (((struct tgpd *)_pd)->flag & TGPD_FORMAT_BDP)
+#define TGPD_SET_FORMAT_BDP(_pd) (((struct tgpd *)_pd)->flag |= TGPD_FORMAT_BDP)
+#define TGPD_CLR_FORMAT_BDP(_pd) (((struct tgpd *)_pd)->flag &= (~TGPD_FORMAT_BDP))
+#define TGPD_FORMAT_BPS 0x04
+#define TGPD_IS_FORMAT_BPS(_pd) (((struct tgpd *)_pd)->flag & TGPD_FORMAT_BPS)
+#define TGPD_SET_FORMAT_BPS(_pd) (((struct tgpd *)_pd)->flag |= TGPD_FORMAT_BPS)
+#define TGPD_CLR_FORMAT_BPS(_pd) (((struct tgpd *)_pd)->flag &= (~TGPD_FORMAT_BPS))
+#define TGPD_SET_FLAG(_pd, _flag) ((struct tgpd *)_pd)->flag = (((struct tgpd *)_pd)->flag&(~TGPD_FLAGS_HWO))|(_flag)
+#define TGPD_GET_FLAG(_pd) (((struct tgpd *)_pd)->flag & TGPD_FLAGS_HWO)
+#define TGPD_SET_CHKSUM(_pd, _n) ((struct tgpd *)_pd)->chksum = mu3d_hal_cal_checksum((u8 *)_pd, _n)-1
+#define TGPD_SET_CHKSUM_HWO(_pd, _n) ((struct tgpd *)_pd)->chksum = mu3d_hal_cal_checksum((u8 *)_pd, _n)-1
+#define TGPD_GET_CHKSUM(_pd) ((struct tgpd *)_pd)->chksum
+#define TGPD_SET_FORMAT(_pd, _fmt) ((struct tgpd *)_pd)->flag = (((struct tgpd *)_pd)->flag&(~TGPD_FORMAT_BDP))|(_fmt)
+#define TGPD_GET_FORMAT(_pd) ((((struct tgpd *)_pd)->flag & TGPD_FORMAT_BDP)>>1)
+#define TGPD_SET_DATABUF_LEN(_pd, _len) ((struct tgpd *)_pd)->databuf_len = _len
+#define TGPD_ADD_DATABUF_LEN(_pd, _len) ((struct tgpd *)_pd)->databuf_len += _len
+#define TGPD_GET_DATABUF_LEN(_pd) ((struct tgpd *)_pd)->databuf_len
+#define TGPD_SET_NEXT(_pd, _next) ((struct tgpd *)_pd)->pnext = (u32)(uintptr_t)_next;
+#define TGPD_GET_NEXT(_pd) (struct tgpd *)(uintptr_t)((struct tgpd *)_pd)->pnext
+#define TGPD_SET_TBD(_pd, _tbd) ((struct tgpd *)_pd)->pBuf = (u8 *)_tbd;\
+ TGPD_SET_FORMAT_BDP(_pd)
+#define TGPD_GET_TBD(_pd) (struct tbd *)((struct tgpd *)_pd)->pBuf
+#define TGPD_SET_DATA(_pd, _data) ((struct tgpd *)_pd)->pBuf = (u32)(uintptr_t)_data
+#define TGPD_GET_DATA(_pd) (uintptr_t)(((struct tgpd *)_pd)->pBuf)
+#define TGPD_SET_BUF_LEN(_pd, _len) ((struct tgpd *)_pd)->bufLen = _len
+#define TGPD_ADD_BUF_LEN(_pd, _len) ((struct tgpd *)_pd)->bufLen += _len
+#define TGPD_GET_BUF_LEN(_pd) ((struct tgpd *)_pd)->bufLen
+#define TGPD_SET_EXT_LEN(_pd, _len) ((struct tgpd *)_pd)->ExtLength = _len
+#define TGPD_GET_EXT_LEN(_pd) ((struct tgpd *)_pd)->ExtLength
+#define TGPD_SET_EPaddr(_pd, _EP) ((struct tgpd *)_pd)->ZTepFlag =(((struct tgpd *)_pd)->ZTepFlag&0xF0)|(_EP)
+#define TGPD_GET_EPaddr(_pd) ((struct tgpd *)_pd)->ZTepFlag & 0x0F
+#define TGPD_FORMAT_TGL 0x10
+#define TGPD_IS_FORMAT_TGL(_pd) (((struct tgpd *)_pd)->ZTepFlag & TGPD_FORMAT_TGL)
+#define TGPD_SET_FORMAT_TGL(_pd) (((struct tgpd *)_pd)->ZTepFlag |=TGPD_FORMAT_TGL)
+#define TGPD_CLR_FORMAT_TGL(_pd) (((struct tgpd *)_pd)->ZTepFlag &= (~TGPD_FORMAT_TGL))
+#define TGPD_FORMAT_ZLP 0x20
+#define TGPD_IS_FORMAT_ZLP(_pd) (((struct tgpd *)_pd)->ZTepFlag & TGPD_FORMAT_ZLP)
+#define TGPD_SET_FORMAT_ZLP(_pd) (((struct tgpd *)_pd)->ZTepFlag |=TGPD_FORMAT_ZLP)
+#define TGPD_CLR_FORMAT_ZLP(_pd) (((struct tgpd *)_pd)->ZTepFlag &= (~TGPD_FORMAT_ZLP))
+#define TGPD_FORMAT_IOC 0x80
+#define TGPD_IS_FORMAT_IOC(_pd) (((struct tgpd *)_pd)->flag & TGPD_FORMAT_IOC)
+#define TGPD_SET_FORMAT_IOC(_pd) (((struct tgpd *)_pd)->flag |=TGPD_FORMAT_IOC)
+#define TGPD_CLR_FORMAT_IOC(_pd) (((struct tgpd *)_pd)->flag &= (~TGPD_FORMAT_IOC))
+#define TGPD_SET_TGL(_pd, _TGL) ((struct tgpd *)_pd)->ZTepFlag |=(( _TGL) ? 0x10: 0x00)
+#define TGPD_GET_TGL(_pd) ((struct tgpd *)_pd)->ZTepFlag & 0x10 ? 1:0
+#define TGPD_SET_ZLP(_pd, _ZLP) ((struct tgpd *)_pd)->ZTepFlag |= ((_ZLP) ? 0x20: 0x00)
+#define TGPD_GET_ZLP(_pd) ((struct tgpd *)_pd)->ZTepFlag & 0x20 ? 1:0
+#define TGPD_GET_EXT(_pd) ((u8 *)_pd + sizeof(struct tgpd))
+
+
+#define TBD_FLAGS_EOL 0x01
+#define TBD_IS_FLAGS_EOL(_bd) (((struct tbd *)_bd)->flag & TBD_FLAGS_EOL)
+#define TBD_SET_FLAGS_EOL(_bd) (((struct tbd *)_bd)->flag |= TBD_FLAGS_EOL)
+#define TBD_CLR_FLAGS_EOL(_bd) (((struct tbd *)_bd)->flag &= (~TBD_FLAGS_EOL))
+#define TBD_SET_FLAG(_bd, _flag) ((struct tbd *)_bd)->flag = (u8)_flag
+#define TBD_GET_FLAG(_bd) ((struct tbd *)_bd)->flag
+#define TBD_SET_CHKSUM(_pd, _n) ((struct tbd *)_pd)->chksum = mu3d_hal_cal_checksum((u8 *)_pd, _n)
+#define TBD_GET_CHKSUM(_pd) ((struct tbd *)_pd)->chksum
+#define TBD_SET_DATABUF_LEN(_pd, _len) ((struct tbd *)_pd)->databuf_len = _len
+#define TBD_GET_DATABUF_LEN(_pd) ((struct tbd *)_pd)->databuf_len
+#define TBD_SET_NEXT(_bd, _next) ((struct tbd *)_bd)->pnext = (struct tbd *)_next
+#define TBD_GET_NEXT(_bd) (struct tbd *)((struct tbd *)_bd)->pnext
+#define TBD_SET_DATA(_bd, _data) ((struct tbd *)_bd)->pBuf = (u8 *)_data
+#define TBD_GET_DATA(_bd) (u8*)((struct tbd *)_bd)->pBuf
+#define TBD_SET_BUF_LEN(_bd, _len) ((struct tbd *)_bd)->bufLen = _len
+#define TBD_ADD_BUF_LEN(_bd, _len) ((struct tbd *)_bd)->bufLen += _len
+#define TBD_GET_BUF_LEN(_bd) ((struct tbd *)_bd)->bufLen
+#define TBD_SET_EXT_LEN(_bd, _len) ((struct tbd *)_bd)->extLen = _len
+#define TBD_ADD_EXT_LEN(_bd, _len) ((struct tbd *)_bd)->extLen += _len
+#define TBD_GET_EXT_LEN(_bd) ((struct tbd *)_bd)->extLen
+#define TBD_GET_EXT(_bd) ((u8 *)_bd + sizeof(struct tbd))
+
+u32 gpd_buf_size;
+u32 g_dma_buffer_size;
+struct tgpd *rx_gpd_head[15];
+struct tgpd *tx_gpd_head[15];
+struct tgpd *rx_gpd_end[15];
+struct tgpd *tx_gpd_end[15];
+struct tgpd *rx_gpd_last[15];
+struct tgpd *tx_gpd_last[15];
+struct gpd_range rx_gpd_list[15] __attribute__((aligned(64)));
+struct gpd_range tx_gpd_list[15] __attribute__((aligned(64)));
+
+u32 rx_gpd_offset[15];
+u32 tx_gpd_offset[15];
+
+/*
+ * declare function
+ */
+void mu3d_hal_insert_transfer_gpd(int ep_num, u8 dir, u8* buf, u32 count, u8 ishwo, u8 ioc, u8 bps, u8 zlp, u32 max_pkt_size);
+void mu3d_hal_resume_qmu(int q_ep_num, u8 dir);
+void mu3d_hal_alloc_qmu_mem(void);
+void mu3d_hal_init_qmu(void);
+void usb_start_qmu(int q_ep_num, u8 dir);
+void mu3d_hal_stop_qmu(int q_ep_num, u8 dir);
+void mu3d_hal_flush_qmu(int q_ep_num, u8 dir);
+
+static inline uintptr_t virt_to_phy(uintptr_t addr) {return (addr & 0xffffffff);}
+static inline uintptr_t phy_to_virt(uintptr_t addr) {return (addr | 0xfffffff000000000);}
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.c b/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.c
new file mode 100644
index 0000000..7b19c4a
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.c
@@ -0,0 +1,260 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mtk-phy-a60810.c
+ *
+ * Project:
+ * --------
+ * BOOTROM
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ ****************************************************************************/
+#include <stdlib.h>
+#include <debug.h>
+#include <errno.h>
+#include "usb_i2c.h"
+#include "phy-a60810.h"
+
+void usb_phy_init(void)
+{
+ static struct u3phy_info info;
+ volatile kal_uint32 u3phy_version;
+
+ info.phyd_version_addr = 0x2000e4;
+ u3phy_version = U3PhyReadReg32(info.phyd_version_addr);
+ printf("phy_version:%x\r\n", u3phy_version);
+ info.u2phy_regs_a = (struct u2phy_reg_a *)0x0;
+ info.u3phyd_regs_a = (struct u3phyd_reg_a *)0x100000;
+ info.u3phyd_bank2_regs_a = (struct u3phyd_bank2_reg_a *)0x200000;
+ info.u3phya_regs_a = (struct u3phya_reg_a *)0x300000;
+ info.u3phya_da_regs_a = (struct u3phya_da_reg_a *)0x400000;
+ info.sifslv_chip_regs_a = (struct sifslv_chip_reg_a *)0x500000;
+ info.spllc_regs_a = (struct spllc_reg_a *)0x600000;
+ info.sifslv_fm_regs_a = (struct sifslv_fm_reg_a *)0xf00000;
+
+
+ //BANK 0x00
+ //for U2 hS eye diagram
+ U3PhyWriteField32(((uintptr_t)&info.u2phy_regs_a->usbphyacr1)
+ , A60810_RG_USB20_TERM_VREF_SEL_OFST, A60810_RG_USB20_TERM_VREF_SEL, 0x05);
+ //for U2 hS eye diagram
+ U3PhyWriteField32(((uintptr_t)&info.u2phy_regs_a->usbphyacr1)
+ , A60810_RG_USB20_VRT_VREF_SEL_OFST, A60810_RG_USB20_VRT_VREF_SEL, 0x05);
+ //for U2 sensititvity
+ U3PhyWriteField32(((uintptr_t)&info.u2phy_regs_a->usbphyacr6)
+ , A60810_RG_USB20_SQTH_OFST, A60810_RG_USB20_SQTH, 0x04);
+
+ //BANK 0x10
+ //disable ssusb_p3_entry to work around resume from P3 bug
+ U3PhyWriteField32(((uintptr_t)&info.u3phyd_regs_a->phyd_lfps0)
+ , A60810_RG_SSUSB_P3_ENTRY_OFST, A60810_RG_SSUSB_P3_ENTRY, 0x00);
+ //force disable ssusb_p3_entry to work around resume from P3 bug
+ U3PhyWriteField32(((uintptr_t)&info.u3phyd_regs_a->phyd_lfps0)
+ , A60810_RG_SSUSB_P3_ENTRY_SEL_OFST, A60810_RG_SSUSB_P3_ENTRY_SEL, 0x01);
+
+
+ //BANK 0x40
+ // fine tune SSC delta1 to let SSC min average ~0ppm
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg19)
+ , A60810_RG_SSUSB_PLL_SSC_DELTA1_U3_OFST, A60810_RG_SSUSB_PLL_SSC_DELTA1_U3, 0x46);
+ //U3PhyWriteField32(((PHY_UINT32)&info.u3phya_da_regs_a->reg19)
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg21)
+ , A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST, (U32)A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H, 0x40);
+
+
+ // fine tune SSC delta to let SSC min average ~0ppm
+
+ // Fine tune SYSPLL to improve phase noise
+ // I2C 60 0x08[01:00] 0x03 RW RG_SSUSB_PLL_BC_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg4)
+ , A60810_RG_SSUSB_PLL_BC_U3_OFST, A60810_RG_SSUSB_PLL_BC_U3, 0x3);
+ // I2C 60 0x08[12:10] 0x03 RW RG_SSUSB_PLL_DIVEN_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg4)
+ , A60810_RG_SSUSB_PLL_DIVEN_U3_OFST, A60810_RG_SSUSB_PLL_DIVEN_U3, 0x3);
+ // I2C 60 0x0C[03:00] 0x01 RW RG_SSUSB_PLL_IC_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg5)
+ , A60810_RG_SSUSB_PLL_IC_U3_OFST, A60810_RG_SSUSB_PLL_IC_U3, 0x1);
+ // I2C 60 0x0C[23:22] 0x01 RW RG_SSUSB_PLL_BR_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg5)
+ , A60810_RG_SSUSB_PLL_BR_U3_OFST, A60810_RG_SSUSB_PLL_BR_U3, 0x1);
+ // I2C 60 0x10[03:00] 0x01 RW RG_SSUSB_PLL_IR_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg6)
+ , A60810_RG_SSUSB_PLL_IR_U3_OFST, A60810_RG_SSUSB_PLL_IR_U3, 0x1);
+ // I2C 60 0x14[03:00] 0x0F RW RG_SSUSB_PLL_BP_U3
+ U3PhyWriteField32(((uintptr_t)&info.u3phya_da_regs_a->reg7)
+//// , A60810_RG_SSUSB_PLL_BP_U3, A60810_RG_SSUSB_PLL_BP_U3, 0xF);
+ , A60810_RG_SSUSB_PLL_BP_U3_OFST, A60810_RG_SSUSB_PLL_BP_U3, 0x0f);
+
+ //BANK 0x60
+ //force xtal pwd mode enable
+ U3PhyWriteField32(((uintptr_t)&info.spllc_regs_a->u3d_xtalctl_2)
+ , A60810_RG_SSUSB_FORCE_XTAL_PWD_OFST, A60810_RG_SSUSB_FORCE_XTAL_PWD, 0x1);
+ //force bias pwd mode enable
+ U3PhyWriteField32(((uintptr_t)&info.spllc_regs_a->u3d_xtalctl_2)
+ , A60810_RG_SSUSB_FORCE_BIAS_PWD_OFST, A60810_RG_SSUSB_FORCE_BIAS_PWD, 0x1);
+ //force xtal pwd mode off to work around xtal drv de
+ U3PhyWriteField32(((uintptr_t)&info.spllc_regs_a->u3d_xtalctl_2)
+ , A60810_RG_SSUSB_XTAL_PWD_OFST, A60810_RG_SSUSB_XTAL_PWD, 0x0);
+ //force bias pwd mode off to work around xtal drv de
+ U3PhyWriteField32(((uintptr_t)&info.spllc_regs_a->u3d_xtalctl_2)
+ , A60810_RG_SSUSB_BIAS_PWD_OFST, A60810_RG_SSUSB_BIAS_PWD, 0x0);
+
+ //******** test chip settings ***********
+ //BANK 0x00
+ // slew rate setting
+ U3PhyWriteField32(((uintptr_t)&info.u2phy_regs_a->usbphyacr5)
+ , A60810_RG_USB20_HSTX_SRCTRL_OFST, A60810_RG_USB20_HSTX_SRCTRL, 0x4);
+
+ //BANK 0x50
+
+ // PIPE setting BANK5
+ // PIPE drv = 2
+ U3PhyWriteReg8(((uintptr_t)&info.sifslv_chip_regs_a->gpio_ctla)+2, 0x10);
+ // PIPE phase
+ //U3PhyWriteReg8(((PHY_UINT32)&info.sifslv_chip_regs_a->gpio_ctla)+3, 0xdc);
+ U3PhyWriteReg8(((uintptr_t)&info.sifslv_chip_regs_a->gpio_ctla)+3, 0x24);
+
+ /*************phy chip part******************/
+ //////Power down bias at P3, p3 bias _pwd
+ //////#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
+ ////#if 1
+ ////U3PhyWriteField32(((U32)&info.sifslv_chip_regs_d->syspll1)
+ //// , (24), (0x1<<24), 0x1);
+ ////chkValue= U3PhyReadReg32(((U32)&info.sifslv_chip_regs_d->syspll1));
+ ////phy_print("pll chkvalue:%x\n", chkValue);
+ ////#endif
+ ////
+ ////// PIPE drv = 2
+ ////U3PhyWriteReg8(((U32)&info.sifslv_chip_regs_d->gpio_ctla+2), 0x10);
+ ////chkValue= U3PhyReadReg32(((U32)&info.sifslv_chip_regs_d->gpio_ctla+2));
+ ////phy_print("chkvalue:%x\n", chkValue);
+ ////// PIPE phase
+ //////u3 8c
+ ////U3PhyWriteReg8(((U32)&info.sifslv_chip_regs_d->gpio_ctla+3), 0x44);
+ ////chkValue= U3PhyReadReg32(((U32)&info.sifslv_chip_regs_d->gpio_ctla+3));
+ ////phy_print("chkvalue:%x\n", chkValue);
+}
+
+//U32 u2_slew_rate_calibration_a60810(struct u3phy_info *info){
+// PHY_INT32 i=0;
+// PHY_INT32 fgRet = 0;
+// PHY_INT32 u4FmOut = 0;
+// PHY_INT32 u4Tmp = 0;
+//
+// // => RG_USB20_HSTX_SRCAL_EN = 1
+// // enable HS TX SR calibration
+// U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_a->usbphyacr5)
+// , A60810_RG_USB20_HSTX_SRCAL_EN_OFST, A60810_RG_USB20_HSTX_SRCAL_EN, 1);
+// DRV_MSLEEP(1);
+//
+// // => RG_FRCK_EN = 1
+// // Enable free run clock
+// U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmmonr1)
+// , A60810_RG_FRCK_EN_OFST, A60810_RG_FRCK_EN, 0x1);
+//
+// // => RG_CYCLECNT = 0x400
+// // Setting cyclecnt = 0x400
+// U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmcr0)
+// , A60810_RG_CYCLECNT_OFST, A60810_RG_CYCLECNT, 0x400);
+//
+// // => RG_FREQDET_EN = 1
+// // Enable frequency meter
+// U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmcr0)
+// , A60810_RG_FREQDET_EN_OFST, A60810_RG_FREQDET_EN, 0x1);
+//
+// // wait for FM detection done, set 10ms timeout
+// for(i=0; i<10; i++){
+// // => u4FmOut = USB_FM_OUT
+// // read FM_OUT
+// u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmmonr0));
+// printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
+//
+// // check if FM detection done
+// if (u4FmOut != 0)
+// {
+// fgRet = 0;
+// printk("FM detection done! loop = %d\n", i);
+//
+// break;
+// }
+//
+// fgRet = 1;
+// DRV_MSLEEP(1);
+// }
+// // => RG_FREQDET_EN = 0
+// // disable frequency meter
+// U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmcr0)
+// , A60810_RG_FREQDET_EN_OFST, A60810_RG_FREQDET_EN, 0);
+//
+// // => RG_FRCK_EN = 0
+// // disable free run clock
+// U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs_a->fmmonr1)
+// , A60810_RG_FRCK_EN_OFST, A60810_RG_FRCK_EN, 0);
+//
+// // => RG_USB20_HSTX_SRCAL_EN = 0
+// // disable HS TX SR calibration
+// U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_a->usbphyacr5)
+// , A60810_RG_USB20_HSTX_SRCAL_EN_OFST, A60810_RG_USB20_HSTX_SRCAL_EN, 0);
+// DRV_MSLEEP(1);
+//
+// if(u4FmOut == 0){
+// U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_a->usbphyacr5)
+// , A60810_RG_USB20_HSTX_SRCTRL_OFST, A60810_RG_USB20_HSTX_SRCTRL, 0x4);
+//
+// fgRet = 1;
+// }
+// else{
+// // set reg = (1024/FM_OUT) * REF_CK * U2_SR_COEF_A60810 / 1000 (round to the nearest digits)
+// u4Tmp = (((1024 * REF_CK * U2_SR_COEF_A60810) / u4FmOut) + 500) / 1000;
+// printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
+// U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs_a->usbphyacr5)
+// , A60810_RG_USB20_HSTX_SRCTRL_OFST, A60810_RG_USB20_HSTX_SRCTRL, u4Tmp);
+// }
+//
+// return fgRet;
+//}
+void usb_phy_deinit(void) {}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.h b/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.h
new file mode 100644
index 0000000..473c2bc
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/phy-a60810.h
@@ -0,0 +1,3137 @@
+//#ifdef CONFIG_A60810_SUPPORT
+#ifndef __MTK_PHY_A60810_H
+#define __MTK_PHY_A60810_H
+
+#define U2_SR_COEF_A60810 22
+
+///////////////////////////////////////////////////////////////////////////////
+typedef unsigned int PHY_UINT32;
+typedef int PHY_INT32;
+typedef unsigned short PHY_UINT16;
+typedef short PHY_INT16;
+typedef unsigned char PHY_UINT8;
+typedef char PHY_INT8;
+
+typedef PHY_UINT32 PHY_LE32;
+
+void usb_phy_init(void);
+
+struct u2phy_reg_a {
+ //0x0
+ PHY_LE32 usbphyacr0;
+ PHY_LE32 usbphyacr1;
+ PHY_LE32 usbphyacr2;
+ PHY_LE32 reserve0;
+ //0x10
+ PHY_LE32 usbphyacr4;
+ PHY_LE32 usbphyacr5;
+ PHY_LE32 usbphyacr6;
+ PHY_LE32 u2phyacr3;
+ //0x20
+ PHY_LE32 u2phyacr4;
+ PHY_LE32 u2phyamon0;
+ PHY_LE32 reserve1[2];
+ //0x30~0x50
+ PHY_LE32 reserve2[12];
+ //0x60
+ PHY_LE32 u2phydcr0;
+ PHY_LE32 u2phydcr1;
+ PHY_LE32 u2phydtm0;
+ PHY_LE32 u2phydtm1;
+ //0x70
+ PHY_LE32 u2phydmon0;
+ PHY_LE32 u2phydmon1;
+ PHY_LE32 u2phydmon2;
+ PHY_LE32 u2phydmon3;
+ //0x80
+ PHY_LE32 u2phybc12c;
+ PHY_LE32 u2phybc12c1;
+ PHY_LE32 reserve3[2];
+ //0x90~0xd0
+ PHY_LE32 reserve4[20];
+ //0xe0
+ PHY_LE32 regfppc;
+ PHY_LE32 reserve5[3];
+ //0xf0
+ PHY_LE32 versionc;
+ PHY_LE32 reserve6[2];
+ PHY_LE32 regfcom;
+};
+
+struct u3phy_info {
+ PHY_INT32 phy_version;
+ PHY_INT32 phyd_version_addr;
+
+ //A60810 regs reference
+ struct u2phy_reg_a *u2phy_regs_a;
+ struct u3phya_reg_a *u3phya_regs_a;
+ struct u3phya_da_reg_a *u3phya_da_regs_a;
+ struct u3phyd_reg_a *u3phyd_regs_a;
+ struct u3phyd_bank2_reg_a *u3phyd_bank2_regs_a;
+ struct sifslv_chip_reg_a *sifslv_chip_regs_a;
+ struct spllc_reg_a *spllc_regs_a;
+ struct sifslv_fm_reg_a *sifslv_fm_regs_a;
+};
+
+
+//U3D_USBPHYACR0
+#define A60810_RG_USB20_MPX_OUT_SEL (0x7<<28) //30:28
+#define A60810_RG_USB20_TX_PH_ROT_SEL (0x7<<24) //26:24
+#define A60810_RG_USB20_PLL_DIVEN (0x7<<20) //22:20
+#define A60810_RG_USB20_PLL_BR (0x1<<18) //18:18
+#define A60810_RG_USB20_PLL_BP (0x1<<17) //17:17
+#define A60810_RG_USB20_PLL_BLP (0x1<<16) //16:16
+#define A60810_RG_USB20_USBPLL_FORCE_ON (0x1<<15) //15:15
+#define A60810_RG_USB20_PLL_FBDIV (0x7f<<8) //14:8
+#define A60810_RG_USB20_PLL_PREDIV (0x3<<6) //7:6
+#define A60810_RG_USB20_INTR_EN (0x1<<5) //5:5
+#define A60810_RG_USB20_REF_EN (0x1<<4) //4:4
+#define A60810_RG_USB20_BGR_DIV (0x3<<2) //3:2
+#define A60810_RG_SIFSLV_CHP_EN (0x1<<1) //1:1
+#define A60810_RG_SIFSLV_BGR_EN (0x1<<0) //0:0
+
+//U3D_USBPHYACR1
+#define A60810_RG_USB20_INTR_CAL (0x1f<<19) //23:19
+#define A60810_RG_USB20_OTG_VBUSTH (0x7<<16) //18:16
+#define A60810_RG_USB20_VRT_VREF_SEL (0x7<<12) //14:12
+#define A60810_RG_USB20_TERM_VREF_SEL (0x7<<8) //10:8
+#define A60810_RG_USB20_MPX_SEL (0xff<<0) //7:0
+
+//U3D_USBPHYACR2
+#define A60810_RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
+#define A60810_RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
+#define A60810_RG_USB20_CLKREF_REV (0xffff<<0) //15:0
+
+//U3D_USBPHYACR4
+#define A60810_RG_USB20_DP_ABIST_SOURCE_EN (0x1<<31) //31:31
+#define A60810_RG_USB20_DP_ABIST_SELE (0xf<<24) //27:24
+#define A60810_RG_USB20_ICUSB_EN (0x1<<16) //16:16
+#define A60810_RG_USB20_LS_CR (0x7<<12) //14:12
+#define A60810_RG_USB20_FS_CR (0x7<<8) //10:8
+#define A60810_RG_USB20_LS_SR (0x7<<4) //6:4
+#define A60810_RG_USB20_FS_SR (0x7<<0) //2:0
+
+//U3D_USBPHYACR5
+#define A60810_RG_USB20_DISC_FIT_EN (0x1<<28) //28:28
+#define A60810_RG_USB20_INIT_SQ_EN_DG (0x3<<26) //27:26
+#define A60810_RG_USB20_HSTX_TMODE_SEL (0x3<<24) //25:24
+#define A60810_RG_USB20_SQD (0x3<<22) //23:22
+#define A60810_RG_USB20_DISCD (0x3<<20) //21:20
+#define A60810_RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
+#define A60810_RG_USB20_PHYD_MONEN (0x1<<18) //18:18
+#define A60810_RG_USB20_INLPBK_EN (0x1<<17) //17:17
+#define A60810_RG_USB20_CHIRP_EN (0x1<<16) //16:16
+#define A60810_RG_USB20_HSTX_SRCAL_EN (0x1<<15) //15:15
+#define A60810_RG_USB20_HSTX_SRCTRL (0x7<<12) //14:12
+#define A60810_RG_USB20_HS_100U_U3_EN (0x1<<11) //11:11
+#define A60810_RG_USB20_GBIAS_ENB (0x1<<10) //10:10
+#define A60810_RG_USB20_DM_ABIST_SOURCE_EN (0x1<<7) //7:7
+#define A60810_RG_USB20_DM_ABIST_SELE (0xf<<0) //3:0
+
+//U3D_USBPHYACR6
+#define A60810_RG_USB20_PHY_REV (0xff<<24) //31:24
+#define A60810_RG_USB20_BC11_SW_EN (0x1<<23) //23:23
+#define A60810_RG_USB20_SR_CLK_SEL (0x1<<22) //22:22
+#define A60810_RG_USB20_OTG_VBUSCMP_EN (0x1<<20) //20:20
+#define A60810_RG_USB20_OTG_ABIST_EN (0x1<<19) //19:19
+#define A60810_RG_USB20_OTG_ABIST_SELE (0x7<<16) //18:16
+#define A60810_RG_USB20_HSRX_MMODE_SELE (0x3<<12) //13:12
+#define A60810_RG_USB20_HSRX_BIAS_EN_SEL (0x3<<9) //10:9
+#define A60810_RG_USB20_HSRX_TMODE_EN (0x1<<8) //8:8
+#define A60810_RG_USB20_DISCTH (0xf<<4) //7:4
+#define A60810_RG_USB20_SQTH (0xf<<0) //3:0
+
+//U3D_U2PHYACR3
+#define A60810_RG_USB20_HSTX_DBIST (0xf<<28) //31:28
+#define A60810_RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
+#define A60810_RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
+#define A60810_RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
+#define A60810_RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
+#define A60810_RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
+#define A60810_RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
+#define A60810_RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
+#define A60810_RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
+#define A60810_RG_USB20_EN_PU_DM (0x1<<11) //11:11
+#define A60810_RG_USB20_EN_PD_DM (0x1<<10) //10:10
+#define A60810_RG_USB20_EN_PU_DP (0x1<<9) //9:9
+#define A60810_RG_USB20_EN_PD_DP (0x1<<8) //8:8
+
+//U3D_U2PHYACR4
+#define A60810_RG_USB20_DP_100K_MODE (0x1<<18) //18:18
+#define A60810_RG_USB20_DM_100K_EN (0x1<<17) //17:17
+#define A60810_USB20_DP_100K_EN (0x1<<16) //16:16
+#define A60810_USB20_GPIO_DM_I (0x1<<15) //15:15
+#define A60810_USB20_GPIO_DP_I (0x1<<14) //14:14
+#define A60810_USB20_GPIO_DM_OE (0x1<<13) //13:13
+#define A60810_USB20_GPIO_DP_OE (0x1<<12) //12:12
+#define A60810_RG_USB20_GPIO_CTL (0x1<<9) //9:9
+#define A60810_USB20_GPIO_MODE (0x1<<8) //8:8
+#define A60810_RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
+#define A60810_RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
+#define A60810_RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
+#define A60810_RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
+
+//U3D_U2PHYAMON0
+#define A60810_RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
+#define A60810_RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
+
+//U3D_U2PHYDCR0
+#define A60810_RG_USB20_CDR_TST (0x3<<30) //31:30
+#define A60810_RG_USB20_GATED_ENB (0x1<<29) //29:29
+#define A60810_RG_USB20_TESTMODE (0x3<<26) //27:26
+#define A60810_RG_SIFSLV_USB20_PLL_STABLE (0x1<<25) //25:25
+#define A60810_RG_SIFSLV_USB20_PLL_FORCE_ON (0x1<<24) //24:24
+#define A60810_RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
+#define A60810_RG_USB20_EBTHRLD (0x1<<7) //7:7
+#define A60810_RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
+#define A60810_RG_USB20_TX_TST (0x1<<5) //5:5
+#define A60810_RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
+#define A60810_RG_USB20_CDR_FILT (0xf<<0) //3:0
+
+//U3D_U2PHYDCR1
+#define A60810_RG_USB20_PROBE_SEL (0xff<<24) //31:24
+#define A60810_RG_USB20_DRVVBUS (0x1<<23) //23:23
+#define A60810_RG_DEBUG_EN (0x1<<22) //22:22
+#define A60810_RG_USB20_OTG_PROBE (0x3<<20) //21:20
+#define A60810_RG_USB20_SW_PLLMODE (0x3<<18) //19:18
+#define A60810_RG_USB20_BERTH (0x3<<16) //17:16
+#define A60810_RG_USB20_LBMODE (0x3<<13) //14:13
+#define A60810_RG_USB20_FORCE_TAP (0x1<<12) //12:12
+#define A60810_RG_USB20_TAPSEL (0xfff<<0) //11:0
+
+//U3D_U2PHYDTM0
+#define A60810_RG_UART_MODE (0x3<<30) //31:30
+#define A60810_FORCE_UART_I (0x1<<29) //29:29
+#define A60810_FORCE_UART_BIAS_EN (0x1<<28) //28:28
+#define A60810_FORCE_UART_TX_OE (0x1<<27) //27:27
+#define A60810_FORCE_UART_EN (0x1<<26) //26:26
+#define A60810_FORCE_USB_CLKEN (0x1<<25) //25:25
+#define A60810_FORCE_DRVVBUS (0x1<<24) //24:24
+#define A60810_FORCE_DATAIN (0x1<<23) //23:23
+#define A60810_FORCE_TXVALID (0x1<<22) //22:22
+#define A60810_FORCE_DM_PULLDOWN (0x1<<21) //21:21
+#define A60810_FORCE_DP_PULLDOWN (0x1<<20) //20:20
+#define A60810_FORCE_XCVRSEL (0x1<<19) //19:19
+#define A60810_FORCE_SUSPENDM (0x1<<18) //18:18
+#define A60810_FORCE_TERMSEL (0x1<<17) //17:17
+#define A60810_FORCE_OPMODE (0x1<<16) //16:16
+#define A60810_UTMI_MUXSEL (0x1<<15) //15:15
+#define A60810_RG_RESET (0x1<<14) //14:14
+#define A60810_RG_DATAIN (0xf<<10) //13:10
+#define A60810_RG_TXVALIDH (0x1<<9) //9:9
+#define A60810_RG_TXVALID (0x1<<8) //8:8
+#define A60810_RG_DMPULLDOWN (0x1<<7) //7:7
+#define A60810_RG_DPPULLDOWN (0x1<<6) //6:6
+#define A60810_RG_XCVRSEL (0x3<<4) //5:4
+#define A60810_RG_SUSPENDM (0x1<<3) //3:3
+#define A60810_RG_TERMSEL (0x1<<2) //2:2
+#define A60810_RG_OPMODE (0x3<<0) //1:0
+
+//U3D_U2PHYDTM1
+#define A60810_RG_USB20_PRBS7_EN (0x1<<31) //31:31
+#define A60810_RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
+#define A60810_RG_USB20_CLK48M_EN (0x1<<23) //23:23
+#define A60810_RG_USB20_CLK60M_EN (0x1<<22) //22:22
+#define A60810_RG_UART_I (0x1<<19) //19:19
+#define A60810_RG_UART_BIAS_EN (0x1<<18) //18:18
+#define A60810_RG_UART_TX_OE (0x1<<17) //17:17
+#define A60810_RG_UART_EN (0x1<<16) //16:16
+#define A60810_RG_IP_U2_PORT_POWER (0x1<<15) //15:15
+#define A60810_FORCE_IP_U2_PORT_POWER (0x1<<14) //14:14
+#define A60810_FORCE_VBUSVALID (0x1<<13) //13:13
+#define A60810_FORCE_SESSEND (0x1<<12) //12:12
+#define A60810_FORCE_BVALID (0x1<<11) //11:11
+#define A60810_FORCE_AVALID (0x1<<10) //10:10
+#define A60810_FORCE_IDDIG (0x1<<9) //9:9
+#define A60810_FORCE_IDPULLUP (0x1<<8) //8:8
+#define A60810_RG_VBUSVALID (0x1<<5) //5:5
+#define A60810_RG_SESSEND (0x1<<4) //4:4
+#define A60810_RG_BVALID (0x1<<3) //3:3
+#define A60810_RG_AVALID (0x1<<2) //2:2
+#define A60810_RG_IDDIG (0x1<<1) //1:1
+#define A60810_RG_IDPULLUP (0x1<<0) //0:0
+
+//U3D_U2PHYDMON0
+#define A60810_RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
+
+//U3D_U2PHYDMON1
+#define A60810_USB20_UART_O (0x1<<31) //31:31
+#define A60810_RGO_USB20_LB_PASS (0x1<<30) //30:30
+#define A60810_RGO_USB20_LB_DONE (0x1<<29) //29:29
+#define A60810_AD_USB20_BVALID (0x1<<28) //28:28
+#define A60810_USB20_IDDIG (0x1<<27) //27:27
+#define A60810_AD_USB20_VBUSVALID (0x1<<26) //26:26
+#define A60810_AD_USB20_SESSEND (0x1<<25) //25:25
+#define A60810_AD_USB20_AVALID (0x1<<24) //24:24
+#define A60810_USB20_LINE_STATE (0x3<<22) //23:22
+#define A60810_USB20_HST_DISCON (0x1<<21) //21:21
+#define A60810_USB20_TX_READY (0x1<<20) //20:20
+#define A60810_USB20_RX_ERROR (0x1<<19) //19:19
+#define A60810_USB20_RX_ACTIVE (0x1<<18) //18:18
+#define A60810_USB20_RX_VALIDH (0x1<<17) //17:17
+#define A60810_USB20_RX_VALID (0x1<<16) //16:16
+#define A60810_USB20_DATA_OUT (0xffff<<0) //15:0
+
+//U3D_U2PHYDMON2
+#define A60810_RGO_TXVALID_CNT (0xff<<24) //31:24
+#define A60810_RGO_RXACTIVE_CNT (0xff<<16) //23:16
+#define A60810_RGO_USB20_LB_BERCNT (0xff<<8) //15:8
+#define A60810_USB20_PROBE_OUT (0xff<<0) //7:0
+
+//U3D_U2PHYDMON3
+#define A60810_RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
+#define A60810_RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
+#define A60810_RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
+#define A60810_RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
+#define A60810_RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
+
+//U3D_U2PHYBC12C
+#define A60810_RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
+#define A60810_RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
+#define A60810_RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
+#define A60810_RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
+#define A60810_RG_CHGDT_VDATSRC (0x1<<13) //13:13
+#define A60810_RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
+#define A60810_RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
+#define A60810_RG_CHGDT_ISRC_DP (0x1<<7) //7:7
+#define A60810_RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
+#define A60810_RG_CHGDT_VDAT_DM (0x1<<5) //5:5
+#define A60810_RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
+#define A60810_RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
+#define A60810_RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
+#define A60810_RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
+#define A60810_RG_CHGDT_EN (0x1<<0) //0:0
+
+//U3D_U2PHYBC12C1
+#define A60810_RG_CHGDT_REV (0xff<<0) //7:0
+
+//U3D_REGFPPC
+#define A60810_USB11_OTG_REG (0x1<<4) //4:4
+#define A60810_USB20_OTG_REG (0x1<<3) //3:3
+#define A60810_CHGDT_REG (0x1<<2) //2:2
+#define A60810_USB11_REG (0x1<<1) //1:1
+#define A60810_USB20_REG (0x1<<0) //0:0
+
+//U3D_VERSIONC
+#define A60810_VERSION_CODE_REGFILE (0xff<<24) //31:24
+#define A60810_USB11_VERSION_CODE (0xff<<16) //23:16
+#define A60810_VERSION_CODE_ANA (0xff<<8) //15:8
+#define A60810_VERSION_CODE_DIG (0xff<<0) //7:0
+
+//U3D_REGFCOM
+#define A60810_RG_PAGE (0xff<<24) //31:24
+#define A60810_I2C_MODE (0x1<<16) //16:16
+
+/* OFFSET */
+
+//U3D_USBPHYACR0
+#define A60810_RG_USB20_MPX_OUT_SEL_OFST (28)
+#define A60810_RG_USB20_TX_PH_ROT_SEL_OFST (24)
+#define A60810_RG_USB20_PLL_DIVEN_OFST (20)
+#define A60810_RG_USB20_PLL_BR_OFST (18)
+#define A60810_RG_USB20_PLL_BP_OFST (17)
+#define A60810_RG_USB20_PLL_BLP_OFST (16)
+#define A60810_RG_USB20_USBPLL_FORCE_ON_OFST (15)
+#define A60810_RG_USB20_PLL_FBDIV_OFST (8)
+#define A60810_RG_USB20_PLL_PREDIV_OFST (6)
+#define A60810_RG_USB20_INTR_EN_OFST (5)
+#define A60810_RG_USB20_REF_EN_OFST (4)
+#define A60810_RG_USB20_BGR_DIV_OFST (2)
+#define A60810_RG_SIFSLV_CHP_EN_OFST (1)
+#define A60810_RG_SIFSLV_BGR_EN_OFST (0)
+
+//U3D_USBPHYACR1
+#define A60810_RG_USB20_INTR_CAL_OFST (19)
+#define A60810_RG_USB20_OTG_VBUSTH_OFST (16)
+#define A60810_RG_USB20_VRT_VREF_SEL_OFST (12)
+#define A60810_RG_USB20_TERM_VREF_SEL_OFST (8)
+#define A60810_RG_USB20_MPX_SEL_OFST (0)
+
+//U3D_USBPHYACR2
+#define A60810_RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
+#define A60810_RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
+#define A60810_RG_USB20_CLKREF_REV_OFST (0)
+
+//U3D_USBPHYACR4
+#define A60810_RG_USB20_DP_ABIST_SOURCE_EN_OFST (31)
+#define A60810_RG_USB20_DP_ABIST_SELE_OFST (24)
+#define A60810_RG_USB20_ICUSB_EN_OFST (16)
+#define A60810_RG_USB20_LS_CR_OFST (12)
+#define A60810_RG_USB20_FS_CR_OFST (8)
+#define A60810_RG_USB20_LS_SR_OFST (4)
+#define A60810_RG_USB20_FS_SR_OFST (0)
+
+//U3D_USBPHYACR5
+#define A60810_RG_USB20_DISC_FIT_EN_OFST (28)
+#define A60810_RG_USB20_INIT_SQ_EN_DG_OFST (26)
+#define A60810_RG_USB20_HSTX_TMODE_SEL_OFST (24)
+#define A60810_RG_USB20_SQD_OFST (22)
+#define A60810_RG_USB20_DISCD_OFST (20)
+#define A60810_RG_USB20_HSTX_TMODE_EN_OFST (19)
+#define A60810_RG_USB20_PHYD_MONEN_OFST (18)
+#define A60810_RG_USB20_INLPBK_EN_OFST (17)
+#define A60810_RG_USB20_CHIRP_EN_OFST (16)
+#define A60810_RG_USB20_HSTX_SRCAL_EN_OFST (15)
+#define A60810_RG_USB20_HSTX_SRCTRL_OFST (12)
+#define A60810_RG_USB20_HS_100U_U3_EN_OFST (11)
+#define A60810_RG_USB20_GBIAS_ENB_OFST (10)
+#define A60810_RG_USB20_DM_ABIST_SOURCE_EN_OFST (7)
+#define A60810_RG_USB20_DM_ABIST_SELE_OFST (0)
+
+//U3D_USBPHYACR6
+#define A60810_RG_USB20_PHY_REV_OFST (24)
+#define A60810_RG_USB20_BC11_SW_EN_OFST (23)
+#define A60810_RG_USB20_SR_CLK_SEL_OFST (22)
+#define A60810_RG_USB20_OTG_VBUSCMP_EN_OFST (20)
+#define A60810_RG_USB20_OTG_ABIST_EN_OFST (19)
+#define A60810_RG_USB20_OTG_ABIST_SELE_OFST (16)
+#define A60810_RG_USB20_HSRX_MMODE_SELE_OFST (12)
+#define A60810_RG_USB20_HSRX_BIAS_EN_SEL_OFST (9)
+#define A60810_RG_USB20_HSRX_TMODE_EN_OFST (8)
+#define A60810_RG_USB20_DISCTH_OFST (4)
+#define A60810_RG_USB20_SQTH_OFST (0)
+
+//U3D_U2PHYACR3
+#define A60810_RG_USB20_HSTX_DBIST_OFST (28)
+#define A60810_RG_USB20_HSTX_BIST_EN_OFST (26)
+#define A60810_RG_USB20_HSTX_I_EN_MODE_OFST (24)
+#define A60810_RG_USB20_USB11_TMODE_EN_OFST (19)
+#define A60810_RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
+#define A60810_RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
+#define A60810_RG_USB20_TMODE_FS_LS_MODE_OFST (16)
+#define A60810_RG_USB20_HS_TERM_EN_MODE_OFST (13)
+#define A60810_RG_USB20_PUPD_BIST_EN_OFST (12)
+#define A60810_RG_USB20_EN_PU_DM_OFST (11)
+#define A60810_RG_USB20_EN_PD_DM_OFST (10)
+#define A60810_RG_USB20_EN_PU_DP_OFST (9)
+#define A60810_RG_USB20_EN_PD_DP_OFST (8)
+
+//U3D_U2PHYACR4
+#define A60810_RG_USB20_DP_100K_MODE_OFST (18)
+#define A60810_RG_USB20_DM_100K_EN_OFST (17)
+#define A60810_USB20_DP_100K_EN_OFST (16)
+#define A60810_USB20_GPIO_DM_I_OFST (15)
+#define A60810_USB20_GPIO_DP_I_OFST (14)
+#define A60810_USB20_GPIO_DM_OE_OFST (13)
+#define A60810_USB20_GPIO_DP_OE_OFST (12)
+#define A60810_RG_USB20_GPIO_CTL_OFST (9)
+#define A60810_USB20_GPIO_MODE_OFST (8)
+#define A60810_RG_USB20_TX_BIAS_EN_OFST (5)
+#define A60810_RG_USB20_TX_VCMPDN_EN_OFST (4)
+#define A60810_RG_USB20_HS_SQ_EN_MODE_OFST (2)
+#define A60810_RG_USB20_HS_RCV_EN_MODE_OFST (0)
+
+//U3D_U2PHYAMON0
+#define A60810_RGO_USB20_GPIO_DM_O_OFST (1)
+#define A60810_RGO_USB20_GPIO_DP_O_OFST (0)
+
+//U3D_U2PHYDCR0
+#define A60810_RG_USB20_CDR_TST_OFST (30)
+#define A60810_RG_USB20_GATED_ENB_OFST (29)
+#define A60810_RG_USB20_TESTMODE_OFST (26)
+#define A60810_RG_SIFSLV_USB20_PLL_STABLE_OFST (25)
+#define A60810_RG_SIFSLV_USB20_PLL_FORCE_ON_OFST (24)
+#define A60810_RG_USB20_PHYD_RESERVE_OFST (8)
+#define A60810_RG_USB20_EBTHRLD_OFST (7)
+#define A60810_RG_USB20_EARLY_HSTX_I_OFST (6)
+#define A60810_RG_USB20_TX_TST_OFST (5)
+#define A60810_RG_USB20_NEGEDGE_ENB_OFST (4)
+#define A60810_RG_USB20_CDR_FILT_OFST (0)
+
+//U3D_U2PHYDCR1
+#define A60810_RG_USB20_PROBE_SEL_OFST (24)
+#define A60810_RG_USB20_DRVVBUS_OFST (23)
+#define A60810_RG_DEBUG_EN_OFST (22)
+#define A60810_RG_USB20_OTG_PROBE_OFST (20)
+#define A60810_RG_USB20_SW_PLLMODE_OFST (18)
+#define A60810_RG_USB20_BERTH_OFST (16)
+#define A60810_RG_USB20_LBMODE_OFST (13)
+#define A60810_RG_USB20_FORCE_TAP_OFST (12)
+#define A60810_RG_USB20_TAPSEL_OFST (0)
+
+//U3D_U2PHYDTM0
+#define A60810_RG_UART_MODE_OFST (30)
+#define A60810_FORCE_UART_I_OFST (29)
+#define A60810_FORCE_UART_BIAS_EN_OFST (28)
+#define A60810_FORCE_UART_TX_OE_OFST (27)
+#define A60810_FORCE_UART_EN_OFST (26)
+#define A60810_FORCE_USB_CLKEN_OFST (25)
+#define A60810_FORCE_DRVVBUS_OFST (24)
+#define A60810_FORCE_DATAIN_OFST (23)
+#define A60810_FORCE_TXVALID_OFST (22)
+#define A60810_FORCE_DM_PULLDOWN_OFST (21)
+#define A60810_FORCE_DP_PULLDOWN_OFST (20)
+#define A60810_FORCE_XCVRSEL_OFST (19)
+#define A60810_FORCE_SUSPENDM_OFST (18)
+#define A60810_FORCE_TERMSEL_OFST (17)
+#define A60810_FORCE_OPMODE_OFST (16)
+#define A60810_UTMI_MUXSEL_OFST (15)
+#define A60810_RG_RESET_OFST (14)
+#define A60810_RG_DATAIN_OFST (10)
+#define A60810_RG_TXVALIDH_OFST (9)
+#define A60810_RG_TXVALID_OFST (8)
+#define A60810_RG_DMPULLDOWN_OFST (7)
+#define A60810_RG_DPPULLDOWN_OFST (6)
+#define A60810_RG_XCVRSEL_OFST (4)
+#define A60810_RG_SUSPENDM_OFST (3)
+#define A60810_RG_TERMSEL_OFST (2)
+#define A60810_RG_OPMODE_OFST (0)
+
+//U3D_U2PHYDTM1
+#define A60810_RG_USB20_PRBS7_EN_OFST (31)
+#define A60810_RG_USB20_PRBS7_BITCNT_OFST (24)
+#define A60810_RG_USB20_CLK48M_EN_OFST (23)
+#define A60810_RG_USB20_CLK60M_EN_OFST (22)
+#define A60810_RG_UART_I_OFST (19)
+#define A60810_RG_UART_BIAS_EN_OFST (18)
+#define A60810_RG_UART_TX_OE_OFST (17)
+#define A60810_RG_UART_EN_OFST (16)
+#define A60810_RG_IP_U2_PORT_POWER_OFST (15)
+#define A60810_FORCE_IP_U2_PORT_POWER_OFST (14)
+#define A60810_FORCE_VBUSVALID_OFST (13)
+#define A60810_FORCE_SESSEND_OFST (12)
+#define A60810_FORCE_BVALID_OFST (11)
+#define A60810_FORCE_AVALID_OFST (10)
+#define A60810_FORCE_IDDIG_OFST (9)
+#define A60810_FORCE_IDPULLUP_OFST (8)
+#define A60810_RG_VBUSVALID_OFST (5)
+#define A60810_RG_SESSEND_OFST (4)
+#define A60810_RG_BVALID_OFST (3)
+#define A60810_RG_AVALID_OFST (2)
+#define A60810_RG_IDDIG_OFST (1)
+#define A60810_RG_IDPULLUP_OFST (0)
+
+//U3D_U2PHYDMON0
+#define A60810_RG_USB20_PRBS7_BERTH_OFST (0)
+
+//U3D_U2PHYDMON1
+#define A60810_USB20_UART_O_OFST (31)
+#define A60810_RGO_USB20_LB_PASS_OFST (30)
+#define A60810_RGO_USB20_LB_DONE_OFST (29)
+#define A60810_AD_USB20_BVALID_OFST (28)
+#define A60810_USB20_IDDIG_OFST (27)
+#define A60810_AD_USB20_VBUSVALID_OFST (26)
+#define A60810_AD_USB20_SESSEND_OFST (25)
+#define A60810_AD_USB20_AVALID_OFST (24)
+#define A60810_USB20_LINE_STATE_OFST (22)
+#define A60810_USB20_HST_DISCON_OFST (21)
+#define A60810_USB20_TX_READY_OFST (20)
+#define A60810_USB20_RX_ERROR_OFST (19)
+#define A60810_USB20_RX_ACTIVE_OFST (18)
+#define A60810_USB20_RX_VALIDH_OFST (17)
+#define A60810_USB20_RX_VALID_OFST (16)
+#define A60810_USB20_DATA_OUT_OFST (0)
+
+//U3D_U2PHYDMON2
+#define A60810_RGO_TXVALID_CNT_OFST (24)
+#define A60810_RGO_RXACTIVE_CNT_OFST (16)
+#define A60810_RGO_USB20_LB_BERCNT_OFST (8)
+#define A60810_USB20_PROBE_OUT_OFST (0)
+
+//U3D_U2PHYDMON3
+#define A60810_RGO_USB20_PRBS7_ERRCNT_OFST (16)
+#define A60810_RGO_USB20_PRBS7_DONE_OFST (3)
+#define A60810_RGO_USB20_PRBS7_LOCK_OFST (2)
+#define A60810_RGO_USB20_PRBS7_PASS_OFST (1)
+#define A60810_RGO_USB20_PRBS7_PASSTH_OFST (0)
+
+//U3D_U2PHYBC12C
+#define A60810_RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
+#define A60810_RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
+#define A60810_RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
+#define A60810_RG_CHGDT_ISRC_LEV_OFST (14)
+#define A60810_RG_CHGDT_VDATSRC_OFST (13)
+#define A60810_RG_CHGDT_BGVREF_SEL_OFST (10)
+#define A60810_RG_CHGDT_RDVREF_SEL_OFST (8)
+#define A60810_RG_CHGDT_ISRC_DP_OFST (7)
+#define A60810_RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
+#define A60810_RG_CHGDT_VDAT_DM_OFST (5)
+#define A60810_RG_CHGDT_OPOUT_DP_OFST (4)
+#define A60810_RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
+#define A60810_RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
+#define A60810_RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
+#define A60810_RG_CHGDT_EN_OFST (0)
+
+//U3D_U2PHYBC12C1
+#define A60810_RG_CHGDT_REV_OFST (0)
+
+//U3D_REGFPPC
+#define A60810_USB11_OTG_REG_OFST (4)
+#define A60810_USB20_OTG_REG_OFST (3)
+#define A60810_CHGDT_REG_OFST (2)
+#define A60810_USB11_REG_OFST (1)
+#define A60810_USB20_REG_OFST (0)
+
+//U3D_VERSIONC
+#define A60810_VERSION_CODE_REGFILE_OFST (24)
+#define A60810_USB11_VERSION_CODE_OFST (16)
+#define A60810_VERSION_CODE_ANA_OFST (8)
+#define A60810_VERSION_CODE_DIG_OFST (0)
+
+//U3D_REGFCOM
+#define A60810_RG_PAGE_OFST (24)
+#define A60810_I2C_MODE_OFST (16)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct u3phya_reg_a {
+ //0x0
+ PHY_LE32 reg0;
+ PHY_LE32 reg1;
+ PHY_LE32 reg2;
+ PHY_LE32 reg3;
+ //0x10
+ PHY_LE32 reg4;
+ PHY_LE32 reg5;
+ PHY_LE32 reg6;
+ PHY_LE32 reg7;
+ //0x20
+ PHY_LE32 reg8;
+ PHY_LE32 reg9;
+ PHY_LE32 rega;
+ PHY_LE32 regb;
+ //0x30
+ PHY_LE32 regc;
+};
+
+//U3D_reg0
+#define A60810_RG_SSUSB_BGR_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_CHPEN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_BG_DIV (0x3<<28) //29:28
+#define A60810_RG_SSUSB_INTR_EN (0x1<<26) //26:26
+#define A60810_RG_SSUSB_MPX_EN (0x1<<24) //24:24
+#define A60810_RG_SSUSB_MPX_SEL (0xff<<16) //23:16
+#define A60810_RG_SSUSB_REF_EN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
+#define A60810_RG_SSUSB_BG_MONEN (0x1<<8) //8:8
+#define A60810_RG_SSUSB_INT_BIAS_SEL (0x1<<7) //7:7
+#define A60810_RG_SSUSB_EXT_BIAS_SEL (0x1<<6) //6:6
+#define A60810_RG_PCIE_CLKDRV_OFFSET (0x3<<2) //3:2
+#define A60810_RG_PCIE_CLKDRV_SLEW (0x3<<0) //1:0
+
+//U3D_reg1
+#define A60810_RG_PCIE_CLKDRV_AMP (0x7<<29) //31:29
+#define A60810_RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_XTAL_MON_EN (0x1<<27) //27:27
+#define A60810_RG_SSUSB_XTAL_HYS (0x1<<26) //26:26
+#define A60810_RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<10) //25:10
+#define A60810_RG_SSUSB_SYSPLL_PREDIV (0x3<<8) //9:8
+#define A60810_RG_SSUSB_SYSPLL_POSDIV (0x3<<6) //7:6
+#define A60810_RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<5) //5:5
+#define A60810_RG_SSUSB_SYSPLL_VOD_EN (0x1<<4) //4:4
+#define A60810_RG_SSUSB_SYSPLL_RST_DLY (0x3<<2) //3:2
+#define A60810_RG_SSUSB_SYSPLL_BLP (0x1<<1) //1:1
+#define A60810_RG_SSUSB_SYSPLL_BP (0x1<<0) //0:0
+
+//U3D_reg2
+#define A60810_RG_SSUSB_SYSPLL_BR (0x1<<31) //31:31
+#define A60810_RG_SSUSB_SYSPLL_BC (0x1<<30) //30:30
+#define A60810_RG_SSUSB_SYSPLL_MONCK_EN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_SYSPLL_MONVC_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_SYSPLL_MONREF_EN (0x1<<27) //27:27
+#define A60810_RG_SSUSB_SYSPLL_SDM_IFM (0x1<<26) //26:26
+#define A60810_RG_SSUSB_SYSPLL_SDM_OUT (0x1<<25) //25:25
+#define A60810_RG_SSUSB_SYSPLL_BACK_EN (0x1<<24) //24:24
+
+//U3D_reg3
+#define A60810_RG_SSUSB_SYSPLL_FBDIV (0x7fffffff<<1) //31:1
+#define A60810_RG_SSUSB_SYSPLL_HR_EN (0x1<<0) //0:0
+
+//U3D_reg4
+#define A60810_RG_SSUSB_SYSPLL_SDM_DI_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_SYSPLL_SDM_DI_LS (0x3<<29) //30:29
+#define A60810_RG_SSUSB_SYSPLL_SDM_ORD (0x3<<27) //28:27
+#define A60810_RG_SSUSB_SYSPLL_SDM_MODE (0x3<<25) //26:25
+#define A60810_RG_SSUSB_SYSPLL_RESERVE (0xff<<17) //24:17
+#define A60810_RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<1) //16:1
+
+//U3D_reg5
+#define A60810_RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
+#define A60810_RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
+#define A60810_RG_SSUSB_IDEM_BIAS (0xf<<20) //23:20
+#define A60810_RG_SSUSB_TX_R50_FON (0x1<<19) //19:19
+#define A60810_RG_SSUSB_TX_SR (0x7<<16) //18:16
+#define A60810_RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
+#define A60810_RG_SSUSB_RXDET_UPDN_FORCE (0x1<<13) //13:13
+#define A60810_RG_SSUSB_RXDET_UPDN_SEL (0x1<<12) //12:12
+#define A60810_RG_SSUSB_RXDET_VTHSEL_L (0x3<<10) //11:10
+#define A60810_RG_SSUSB_RXDET_VTHSEL_H (0x3<<8) //9:8
+#define A60810_RG_SSUSB_CKMON_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_TX_VLMON_EN (0x1<<6) //6:6
+#define A60810_RG_SSUSB_TX_VLMON_SEL (0x3<<4) //5:4
+#define A60810_RG_SSUSB_CKMON_SEL (0xf<<0) //3:0
+
+//U3D_reg6
+#define A60810_RG_SSUSB_TX_EIDLE_CM (0xf<<28) //31:28
+#define A60810_RG_SSUSB_RXLBTX_EN (0x1<<27) //27:27
+#define A60810_RG_SSUSB_TXLBRX_EN (0x1<<26) //26:26
+#define A60810_RG_SSUSB_RESERVE (0x3ff<<16) //25:16
+#define A60810_RG_SSUSB_PLL_POSDIV (0x3<<14) //15:14
+#define A60810_RG_SSUSB_PLL_AUTOK_LOAD (0x1<<13) //13:13
+#define A60810_RG_SSUSB_PLL_VOD_EN (0x1<<12) //12:12
+#define A60810_RG_SSUSB_PLL_MONREF_EN (0x1<<11) //11:11
+#define A60810_RG_SSUSB_PLL_MONCK_EN (0x1<<10) //10:10
+#define A60810_RG_SSUSB_PLL_MONVC_EN (0x1<<9) //9:9
+#define A60810_RG_SSUSB_PLL_RLH_EN (0x1<<8) //8:8
+#define A60810_RG_SSUSB_PLL_AUTOK_KS (0x3<<6) //7:6
+#define A60810_RG_SSUSB_PLL_AUTOK_KF (0x3<<4) //5:4
+#define A60810_RG_SSUSB_PLL_RST_DLY (0x3<<2) //3:2
+
+//U3D_reg7
+#define A60810_RG_SSUSB_PLL_RESERVE (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
+
+//U3D_reg8
+#define A60810_RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
+#define A60810_RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
+#define A60810_RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_PLL_DDS_RST_SEL (0x1<<27) //27:27
+#define A60810_RG_SSUSB_PLL_DDS_VADJ (0x1<<26) //26:26
+#define A60810_RG_SSUSB_PLL_DDS_MONEN (0x1<<25) //25:25
+#define A60810_RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<24) //24:24
+#define A60810_RG_SSUSB_PLL_DDS_PI_PL_EN (0x1<<23) //23:23
+#define A60810_RG_SSUSB_PLL_DDS_FRAC_MUTE (0x7<<20) //22:20
+#define A60810_RG_SSUSB_PLL_DDS_HF_EN (0x1<<19) //19:19
+#define A60810_RG_SSUSB_PLL_DDS_C (0x7<<16) //18:16
+#define A60810_RG_SSUSB_PLL_DDS_PREDIV2 (0x1<<15) //15:15
+#define A60810_RG_SSUSB_LFPS_LPF (0x3<<13) //14:13
+
+//U3D_reg9
+#define A60810_RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<31) //31:31
+#define A60810_RG_SSUSB_CDR_PD_DIV_SEL (0x1<<30) //30:30
+#define A60810_RG_SSUSB_CDR_CPBIAS_SEL (0x1<<29) //29:29
+#define A60810_RG_SSUSB_CDR_OSCDET_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_CDR_MONMUX (0x1<<27) //27:27
+#define A60810_RG_SSUSB_CDR_RST_DLY (0x3<<25) //26:25
+#define A60810_RG_SSUSB_CDR_RSTB_MANUAL (0x1<<24) //24:24
+#define A60810_RG_SSUSB_CDR_BYPASS (0x3<<22) //23:22
+#define A60810_RG_SSUSB_CDR_PI_SLEW (0x3<<20) //21:20
+#define A60810_RG_SSUSB_CDR_EPEN (0x1<<19) //19:19
+#define A60810_RG_SSUSB_CDR_AUTOK_LOAD (0x1<<18) //18:18
+#define A60810_RG_SSUSB_CDR_MONEN (0x1<<16) //16:16
+#define A60810_RG_SSUSB_CDR_MONEN_DIG (0x1<<15) //15:15
+#define A60810_RG_SSUSB_CDR_REGOD (0x3<<13) //14:13
+#define A60810_RG_SSUSB_CDR_AUTOK_KS (0x3<<11) //12:11
+#define A60810_RG_SSUSB_CDR_AUTOK_KF (0x3<<9) //10:9
+#define A60810_RG_SSUSB_RX_DAC_EN (0x1<<8) //8:8
+#define A60810_RG_SSUSB_RX_DAC_PWD (0x1<<7) //7:7
+#define A60810_RG_SSUSB_EQ_CURSEL (0x1<<6) //6:6
+#define A60810_RG_SSUSB_RX_DAC_MUX (0x1f<<1) //5:1
+#define A60810_RG_SSUSB_RX_R2T_EN (0x1<<0) //0:0
+
+//U3D_regA
+#define A60810_RG_SSUSB_RX_T2R_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_RX_50_LOWER (0x7<<28) //30:28
+#define A60810_RG_SSUSB_RX_50_TAR (0x3<<26) //27:26
+#define A60810_RG_SSUSB_RX_SW_CTRL (0xf<<21) //24:21
+#define A60810_RG_PCIE_SIGDET_VTH (0x3<<19) //20:19
+#define A60810_RG_PCIE_SIGDET_LPF (0x3<<17) //18:17
+#define A60810_RG_SSUSB_LFPS_MON_EN (0x1<<16) //16:16
+#define A60810_RG_SSUSB_RXAFE_DCMON_SEL (0xf<<12) //15:12
+#define A60810_RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<11) //11:11
+#define A60810_RG_SSUSB_RX_PD_RST (0x1<<10) //10:10
+#define A60810_RG_SSUSB_RX_PD_RST_PASS (0x1<<9) //9:9
+
+//U3D_regB
+#define A60810_RG_SSUSB_CDR_RESERVE (0xff<<24) //31:24
+#define A60810_RG_SSUSB_RXAFE_RESERVE (0xff<<16) //23:16
+#define A60810_RG_PCIE_RX_RESERVE (0xff<<8) //15:8
+#define A60810_RG_SSUSB_VRT_25M_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_RX_PD_PICAL_SWAP (0x1<<6) //6:6
+#define A60810_RG_SSUSB_RX_DAC_MEAS_EN (0x1<<5) //5:5
+#define A60810_RG_SSUSB_MPX_SEL_L0 (0x1<<4) //4:4
+#define A60810_RG_SSUSB_LFPS_SLCOUT_SEL (0x1<<3) //3:3
+#define A60810_RG_SSUSB_LFPS_CMPOUT_SEL (0x1<<2) //2:2
+#define A60810_RG_PCIE_SIGDET_HF (0x3<<0) //1:0
+
+//U3D_regC
+#define A60810_RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
+
+/* OFFSET */
+
+//U3D_reg0
+#define A60810_RG_SSUSB_BGR_EN_OFST (31)
+#define A60810_RG_SSUSB_CHPEN_OFST (30)
+#define A60810_RG_SSUSB_BG_DIV_OFST (28)
+#define A60810_RG_SSUSB_INTR_EN_OFST (26)
+#define A60810_RG_SSUSB_MPX_EN_OFST (24)
+#define A60810_RG_SSUSB_MPX_SEL_OFST (16)
+#define A60810_RG_SSUSB_REF_EN_OFST (15)
+#define A60810_RG_SSUSB_VRT_VREF_SEL_OFST (11)
+#define A60810_RG_SSUSB_BG_MONEN_OFST (8)
+#define A60810_RG_SSUSB_INT_BIAS_SEL_OFST (7)
+#define A60810_RG_SSUSB_EXT_BIAS_SEL_OFST (6)
+#define A60810_RG_PCIE_CLKDRV_OFFSET_OFST (2)
+#define A60810_RG_PCIE_CLKDRV_SLEW_OFST (0)
+
+//U3D_reg1
+#define A60810_RG_PCIE_CLKDRV_AMP_OFST (29)
+#define A60810_RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (28)
+#define A60810_RG_SSUSB_XTAL_MON_EN_OFST (27)
+#define A60810_RG_SSUSB_XTAL_HYS_OFST (26)
+#define A60810_RG_SSUSB_XTAL_TOP_RESERVE_OFST (10)
+#define A60810_RG_SSUSB_SYSPLL_PREDIV_OFST (8)
+#define A60810_RG_SSUSB_SYSPLL_POSDIV_OFST (6)
+#define A60810_RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (5)
+#define A60810_RG_SSUSB_SYSPLL_VOD_EN_OFST (4)
+#define A60810_RG_SSUSB_SYSPLL_RST_DLY_OFST (2)
+#define A60810_RG_SSUSB_SYSPLL_BLP_OFST (1)
+#define A60810_RG_SSUSB_SYSPLL_BP_OFST (0)
+
+//U3D_reg2
+#define A60810_RG_SSUSB_SYSPLL_BR_OFST (31)
+#define A60810_RG_SSUSB_SYSPLL_BC_OFST (30)
+#define A60810_RG_SSUSB_SYSPLL_MONCK_EN_OFST (29)
+#define A60810_RG_SSUSB_SYSPLL_MONVC_EN_OFST (28)
+#define A60810_RG_SSUSB_SYSPLL_MONREF_EN_OFST (27)
+#define A60810_RG_SSUSB_SYSPLL_SDM_IFM_OFST (26)
+#define A60810_RG_SSUSB_SYSPLL_SDM_OUT_OFST (25)
+#define A60810_RG_SSUSB_SYSPLL_BACK_EN_OFST (24)
+
+//U3D_reg3
+#define A60810_RG_SSUSB_SYSPLL_FBDIV_OFST (1)
+#define A60810_RG_SSUSB_SYSPLL_HR_EN_OFST (0)
+
+//U3D_reg4
+#define A60810_RG_SSUSB_SYSPLL_SDM_DI_EN_OFST (31)
+#define A60810_RG_SSUSB_SYSPLL_SDM_DI_LS_OFST (29)
+#define A60810_RG_SSUSB_SYSPLL_SDM_ORD_OFST (27)
+#define A60810_RG_SSUSB_SYSPLL_SDM_MODE_OFST (25)
+#define A60810_RG_SSUSB_SYSPLL_RESERVE_OFST (17)
+#define A60810_RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (1)
+
+//U3D_reg5
+#define A60810_RG_SSUSB_TX250MCK_INVB_OFST (31)
+#define A60810_RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
+#define A60810_RG_SSUSB_IDRV_CALIB_OFST (24)
+#define A60810_RG_SSUSB_IDEM_BIAS_OFST (20)
+#define A60810_RG_SSUSB_TX_R50_FON_OFST (19)
+#define A60810_RG_SSUSB_TX_SR_OFST (16)
+#define A60810_RG_SSUSB_RXDET_RSEL_OFST (14)
+#define A60810_RG_SSUSB_RXDET_UPDN_FORCE_OFST (13)
+#define A60810_RG_SSUSB_RXDET_UPDN_SEL_OFST (12)
+#define A60810_RG_SSUSB_RXDET_VTHSEL_L_OFST (10)
+#define A60810_RG_SSUSB_RXDET_VTHSEL_H_OFST (8)
+#define A60810_RG_SSUSB_CKMON_EN_OFST (7)
+#define A60810_RG_SSUSB_TX_VLMON_EN_OFST (6)
+#define A60810_RG_SSUSB_TX_VLMON_SEL_OFST (4)
+#define A60810_RG_SSUSB_CKMON_SEL_OFST (0)
+
+//U3D_reg6
+#define A60810_RG_SSUSB_TX_EIDLE_CM_OFST (28)
+#define A60810_RG_SSUSB_RXLBTX_EN_OFST (27)
+#define A60810_RG_SSUSB_TXLBRX_EN_OFST (26)
+#define A60810_RG_SSUSB_RESERVE_OFST (16)
+#define A60810_RG_SSUSB_PLL_POSDIV_OFST (14)
+#define A60810_RG_SSUSB_PLL_AUTOK_LOAD_OFST (13)
+#define A60810_RG_SSUSB_PLL_VOD_EN_OFST (12)
+#define A60810_RG_SSUSB_PLL_MONREF_EN_OFST (11)
+#define A60810_RG_SSUSB_PLL_MONCK_EN_OFST (10)
+#define A60810_RG_SSUSB_PLL_MONVC_EN_OFST (9)
+#define A60810_RG_SSUSB_PLL_RLH_EN_OFST (8)
+#define A60810_RG_SSUSB_PLL_AUTOK_KS_OFST (6)
+#define A60810_RG_SSUSB_PLL_AUTOK_KF_OFST (4)
+#define A60810_RG_SSUSB_PLL_RST_DLY_OFST (2)
+
+//U3D_reg7
+#define A60810_RG_SSUSB_PLL_RESERVE_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_PRD_OFST (0)
+
+//U3D_reg8
+#define A60810_RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
+#define A60810_RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
+#define A60810_RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
+#define A60810_RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
+#define A60810_RG_SSUSB_PLL_DDS_RST_SEL_OFST (27)
+#define A60810_RG_SSUSB_PLL_DDS_VADJ_OFST (26)
+#define A60810_RG_SSUSB_PLL_DDS_MONEN_OFST (25)
+#define A60810_RG_SSUSB_PLL_DDS_SEL_EXT_OFST (24)
+#define A60810_RG_SSUSB_PLL_DDS_PI_PL_EN_OFST (23)
+#define A60810_RG_SSUSB_PLL_DDS_FRAC_MUTE_OFST (20)
+#define A60810_RG_SSUSB_PLL_DDS_HF_EN_OFST (19)
+#define A60810_RG_SSUSB_PLL_DDS_C_OFST (16)
+#define A60810_RG_SSUSB_PLL_DDS_PREDIV2_OFST (15)
+#define A60810_RG_SSUSB_LFPS_LPF_OFST (13)
+
+//U3D_reg9
+#define A60810_RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (31)
+#define A60810_RG_SSUSB_CDR_PD_DIV_SEL_OFST (30)
+#define A60810_RG_SSUSB_CDR_CPBIAS_SEL_OFST (29)
+#define A60810_RG_SSUSB_CDR_OSCDET_EN_OFST (28)
+#define A60810_RG_SSUSB_CDR_MONMUX_OFST (27)
+#define A60810_RG_SSUSB_CDR_RST_DLY_OFST (25)
+#define A60810_RG_SSUSB_CDR_RSTB_MANUAL_OFST (24)
+#define A60810_RG_SSUSB_CDR_BYPASS_OFST (22)
+#define A60810_RG_SSUSB_CDR_PI_SLEW_OFST (20)
+#define A60810_RG_SSUSB_CDR_EPEN_OFST (19)
+#define A60810_RG_SSUSB_CDR_AUTOK_LOAD_OFST (18)
+#define A60810_RG_SSUSB_CDR_MONEN_OFST (16)
+#define A60810_RG_SSUSB_CDR_MONEN_DIG_OFST (15)
+#define A60810_RG_SSUSB_CDR_REGOD_OFST (13)
+#define A60810_RG_SSUSB_CDR_AUTOK_KS_OFST (11)
+#define A60810_RG_SSUSB_CDR_AUTOK_KF_OFST (9)
+#define A60810_RG_SSUSB_RX_DAC_EN_OFST (8)
+#define A60810_RG_SSUSB_RX_DAC_PWD_OFST (7)
+#define A60810_RG_SSUSB_EQ_CURSEL_OFST (6)
+#define A60810_RG_SSUSB_RX_DAC_MUX_OFST (1)
+#define A60810_RG_SSUSB_RX_R2T_EN_OFST (0)
+
+//U3D_regA
+#define A60810_RG_SSUSB_RX_T2R_EN_OFST (31)
+#define A60810_RG_SSUSB_RX_50_LOWER_OFST (28)
+#define A60810_RG_SSUSB_RX_50_TAR_OFST (26)
+#define A60810_RG_SSUSB_RX_SW_CTRL_OFST (21)
+#define A60810_RG_PCIE_SIGDET_VTH_OFST (19)
+#define A60810_RG_PCIE_SIGDET_LPF_OFST (17)
+#define A60810_RG_SSUSB_LFPS_MON_EN_OFST (16)
+#define A60810_RG_SSUSB_RXAFE_DCMON_SEL_OFST (12)
+#define A60810_RG_SSUSB_RX_P1_ENTRY_PASS_OFST (11)
+#define A60810_RG_SSUSB_RX_PD_RST_OFST (10)
+#define A60810_RG_SSUSB_RX_PD_RST_PASS_OFST (9)
+
+//U3D_regB
+#define A60810_RG_SSUSB_CDR_RESERVE_OFST (24)
+#define A60810_RG_SSUSB_RXAFE_RESERVE_OFST (16)
+#define A60810_RG_PCIE_RX_RESERVE_OFST (8)
+#define A60810_RG_SSUSB_VRT_25M_EN_OFST (7)
+#define A60810_RG_SSUSB_RX_PD_PICAL_SWAP_OFST (6)
+#define A60810_RG_SSUSB_RX_DAC_MEAS_EN_OFST (5)
+#define A60810_RG_SSUSB_MPX_SEL_L0_OFST (4)
+#define A60810_RG_SSUSB_LFPS_SLCOUT_SEL_OFST (3)
+#define A60810_RG_SSUSB_LFPS_CMPOUT_SEL_OFST (2)
+#define A60810_RG_PCIE_SIGDET_HF_OFST (0)
+
+//U3D_regC
+#define A60810_RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct u3phya_da_reg_a {
+ //0x0
+ PHY_LE32 reg0;
+ PHY_LE32 reg1;
+ PHY_LE32 reg4;
+ PHY_LE32 reg5;
+ //0x10
+ PHY_LE32 reg6;
+ PHY_LE32 reg7;
+ PHY_LE32 reg8;
+ PHY_LE32 reg9;
+ //0x20
+ PHY_LE32 reg10;
+ PHY_LE32 reg12;
+ PHY_LE32 reg13;
+ PHY_LE32 reg14;
+ //0x30
+ PHY_LE32 reg15;
+ PHY_LE32 reg16;
+ PHY_LE32 reg19;
+ PHY_LE32 reg20;
+ //0x40
+ PHY_LE32 reg21;
+ PHY_LE32 reg23;
+ PHY_LE32 reg25;
+ PHY_LE32 reg26;
+ //0x50
+ PHY_LE32 reg28;
+ PHY_LE32 reg29;
+ PHY_LE32 reg30;
+ PHY_LE32 reg31;
+ //0x60
+ PHY_LE32 reg32;
+ PHY_LE32 reg33;
+};
+
+//U3D_reg0
+#define A60810_RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
+#define A60810_RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
+#define A60810_RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
+#define A60810_RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
+#define A60810_RG_PCIE_SPEED_U3 (0x1<<20) //20:20
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
+#define A60810_RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
+
+//U3D_reg1
+#define A60810_RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
+#define A60810_RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
+#define A60810_RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
+#define A60810_RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
+#define A60810_RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
+#define A60810_RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
+#define A60810_RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
+#define A60810_RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
+#define A60810_RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
+#define A60810_RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
+#define A60810_RG_PCIE_MODE_PE2D (0x1<<8) //8:8
+#define A60810_RG_PCIE_MODE_PE2H (0x1<<3) //3:3
+#define A60810_RG_PCIE_MODE_PE1D (0x1<<2) //2:2
+#define A60810_RG_PCIE_MODE_PE1H (0x1<<1) //1:1
+#define A60810_RG_PCIE_MODE_U3 (0x1<<0) //0:0
+
+//U3D_reg4
+#define A60810_RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
+#define A60810_RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
+#define A60810_RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
+#define A60810_RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
+#define A60810_RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
+#define A60810_RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
+#define A60810_RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
+#define A60810_RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
+#define A60810_RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
+#define A60810_RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
+
+//U3D_reg5
+#define A60810_RG_SSUSB_PLL_BR_PE2D (0x3<<30) //31:30
+#define A60810_RG_SSUSB_PLL_BR_PE2H (0x3<<28) //29:28
+#define A60810_RG_SSUSB_PLL_BR_PE1D (0x3<<26) //27:26
+#define A60810_RG_SSUSB_PLL_BR_PE1H (0x3<<24) //25:24
+#define A60810_RG_SSUSB_PLL_BR_U3 (0x3<<22) //23:22
+#define A60810_RG_SSUSB_PLL_IC_PE2D (0xf<<16) //19:16
+#define A60810_RG_SSUSB_PLL_IC_PE2H (0xf<<12) //15:12
+#define A60810_RG_SSUSB_PLL_IC_PE1D (0xf<<8) //11:8
+#define A60810_RG_SSUSB_PLL_IC_PE1H (0xf<<4) //7:4
+#define A60810_RG_SSUSB_PLL_IC_U3 (0xf<<0) //3:0
+
+//U3D_reg6
+#define A60810_RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
+#define A60810_RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
+#define A60810_RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
+#define A60810_RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
+#define A60810_RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
+
+//U3D_reg7
+#define A60810_RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
+#define A60810_RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
+#define A60810_RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
+#define A60810_RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
+#define A60810_RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
+
+//U3D_reg8
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
+#define A60810_RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
+
+//U3D_reg9
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
+
+//U3D_reg10
+#define A60810_RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
+#define A60810_RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
+#define A60810_RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
+#define A60810_RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
+#define A60810_RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
+
+//U3D_reg12
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
+
+//U3D_reg13
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
+
+//U3D_reg14
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
+
+//U3D_reg15
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
+
+//U3D_reg16
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
+
+//U3D_reg19
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H ((U32)0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
+
+//U3D_reg20
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
+
+//U3D_reg21
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
+
+//U3D_reg23
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
+
+//U3D_reg25
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
+
+//U3D_reg26
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
+#define A60810_RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
+
+//U3D_reg28
+#define A60810_RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
+#define A60810_RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
+#define A60810_RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
+#define A60810_RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
+#define A60810_RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
+
+//U3D_reg29
+#define A60810_RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
+#define A60810_RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
+#define A60810_RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
+#define A60810_RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
+#define A60810_RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
+
+//U3D_reg30
+#define A60810_RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
+#define A60810_RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
+#define A60810_RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
+#define A60810_RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
+#define A60810_RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
+
+//U3D_reg31
+#define A60810_RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
+
+//U3D_reg32
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
+#define A60810_RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
+#define A60810_RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
+#define A60810_RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
+#define A60810_RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
+#define A60810_RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
+#define A60810_RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
+#define A60810_RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
+
+//U3D_reg33
+#define A60810_RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
+#define A60810_RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
+#define A60810_RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
+#define A60810_RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
+#define A60810_RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
+#define A60810_RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
+
+/* OFFSET DEFINITION */
+
+//U3D_reg0
+#define A60810_RG_PCIE_SPEED_PE2D_OFST (24)
+#define A60810_RG_PCIE_SPEED_PE2H_OFST (23)
+#define A60810_RG_PCIE_SPEED_PE1D_OFST (22)
+#define A60810_RG_PCIE_SPEED_PE1H_OFST (21)
+#define A60810_RG_PCIE_SPEED_U3_OFST (20)
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
+#define A60810_RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
+#define A60810_RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
+#define A60810_RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
+
+//U3D_reg1
+#define A60810_RG_USB20_REFCK_SEL_PE2D_OFST (30)
+#define A60810_RG_USB20_REFCK_SEL_PE2H_OFST (29)
+#define A60810_RG_USB20_REFCK_SEL_PE1D_OFST (28)
+#define A60810_RG_USB20_REFCK_SEL_PE1H_OFST (27)
+#define A60810_RG_USB20_REFCK_SEL_U3_OFST (26)
+#define A60810_RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
+#define A60810_RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
+#define A60810_RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
+#define A60810_RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
+#define A60810_RG_PCIE_REFCK_DIV4_U3_OFST (16)
+#define A60810_RG_PCIE_MODE_PE2D_OFST (8)
+#define A60810_RG_PCIE_MODE_PE2H_OFST (3)
+#define A60810_RG_PCIE_MODE_PE1D_OFST (2)
+#define A60810_RG_PCIE_MODE_PE1H_OFST (1)
+#define A60810_RG_PCIE_MODE_U3_OFST (0)
+
+//U3D_reg4
+#define A60810_RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
+#define A60810_RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
+#define A60810_RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
+#define A60810_RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
+#define A60810_RG_SSUSB_PLL_DIVEN_U3_OFST (10)
+#define A60810_RG_SSUSB_PLL_BC_PE2D_OFST (8)
+#define A60810_RG_SSUSB_PLL_BC_PE2H_OFST (6)
+#define A60810_RG_SSUSB_PLL_BC_PE1D_OFST (4)
+#define A60810_RG_SSUSB_PLL_BC_PE1H_OFST (2)
+#define A60810_RG_SSUSB_PLL_BC_U3_OFST (0)
+
+//U3D_reg5
+#define A60810_RG_SSUSB_PLL_BR_PE2D_OFST (30)
+#define A60810_RG_SSUSB_PLL_BR_PE2H_OFST (28)
+#define A60810_RG_SSUSB_PLL_BR_PE1D_OFST (26)
+#define A60810_RG_SSUSB_PLL_BR_PE1H_OFST (24)
+#define A60810_RG_SSUSB_PLL_BR_U3_OFST (22)
+#define A60810_RG_SSUSB_PLL_IC_PE2D_OFST (16)
+#define A60810_RG_SSUSB_PLL_IC_PE2H_OFST (12)
+#define A60810_RG_SSUSB_PLL_IC_PE1D_OFST (8)
+#define A60810_RG_SSUSB_PLL_IC_PE1H_OFST (4)
+#define A60810_RG_SSUSB_PLL_IC_U3_OFST (0)
+
+//U3D_reg6
+#define A60810_RG_SSUSB_PLL_IR_PE2D_OFST (24)
+#define A60810_RG_SSUSB_PLL_IR_PE2H_OFST (16)
+#define A60810_RG_SSUSB_PLL_IR_PE1D_OFST (8)
+#define A60810_RG_SSUSB_PLL_IR_PE1H_OFST (4)
+#define A60810_RG_SSUSB_PLL_IR_U3_OFST (0)
+
+//U3D_reg7
+#define A60810_RG_SSUSB_PLL_BP_PE2D_OFST (24)
+#define A60810_RG_SSUSB_PLL_BP_PE2H_OFST (16)
+#define A60810_RG_SSUSB_PLL_BP_PE1D_OFST (8)
+#define A60810_RG_SSUSB_PLL_BP_PE1H_OFST (4)
+#define A60810_RG_SSUSB_PLL_BP_U3_OFST (0)
+
+//U3D_reg8
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
+#define A60810_RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
+#define A60810_RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
+
+//U3D_reg9
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
+#define A60810_RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
+
+//U3D_reg10
+#define A60810_RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
+#define A60810_RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
+#define A60810_RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
+#define A60810_RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
+#define A60810_RG_SSUSB_PLL_PREDIV_U3_OFST (8)
+#define A60810_RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
+
+//U3D_reg12
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
+
+//U3D_reg13
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
+
+//U3D_reg14
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
+
+//U3D_reg15
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
+
+//U3D_reg16
+#define A60810_RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
+
+//U3D_reg19
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
+
+//U3D_reg20
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
+
+//U3D_reg21
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
+
+//U3D_reg23
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
+
+//U3D_reg25
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
+#define A60810_RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
+
+//U3D_reg26
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
+#define A60810_RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
+#define A60810_RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
+
+//U3D_reg28
+#define A60810_RG_SSUSB_CDR_BPA_PE2D_OFST (24)
+#define A60810_RG_SSUSB_CDR_BPA_PE2H_OFST (16)
+#define A60810_RG_SSUSB_CDR_BPA_PE1D_OFST (10)
+#define A60810_RG_SSUSB_CDR_BPA_PE1H_OFST (8)
+#define A60810_RG_SSUSB_CDR_BPA_U3_OFST (0)
+
+//U3D_reg29
+#define A60810_RG_SSUSB_CDR_BPB_PE2D_OFST (24)
+#define A60810_RG_SSUSB_CDR_BPB_PE2H_OFST (16)
+#define A60810_RG_SSUSB_CDR_BPB_PE1D_OFST (6)
+#define A60810_RG_SSUSB_CDR_BPB_PE1H_OFST (3)
+#define A60810_RG_SSUSB_CDR_BPB_U3_OFST (0)
+
+//U3D_reg30
+#define A60810_RG_SSUSB_CDR_BR_PE2D_OFST (24)
+#define A60810_RG_SSUSB_CDR_BR_PE2H_OFST (16)
+#define A60810_RG_SSUSB_CDR_BR_PE1D_OFST (6)
+#define A60810_RG_SSUSB_CDR_BR_PE1H_OFST (3)
+#define A60810_RG_SSUSB_CDR_BR_U3_OFST (0)
+
+//U3D_reg31
+#define A60810_RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
+#define A60810_RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
+#define A60810_RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
+#define A60810_RG_SSUSB_CDR_FBDIV_U3_OFST (0)
+
+//U3D_reg32
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
+#define A60810_RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
+#define A60810_RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
+#define A60810_RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
+#define A60810_RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
+#define A60810_RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
+#define A60810_RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
+#define A60810_RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
+#define A60810_RG_SSUSB_CDR_KVSEL_U3_OFST (7)
+#define A60810_RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
+
+//U3D_reg33
+#define A60810_RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
+#define A60810_RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
+#define A60810_RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
+#define A60810_RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
+#define A60810_RG_SSUSB_RX_CMPWD_U3_OFST (16)
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
+#define A60810_RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
+#define A60810_RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct u3phyd_reg_a {
+ //0x0
+ PHY_LE32 phyd_mix0;
+ PHY_LE32 phyd_mix1;
+ PHY_LE32 phyd_lfps0;
+ PHY_LE32 phyd_lfps1;
+ //0x10
+ PHY_LE32 phyd_impcal0;
+ PHY_LE32 phyd_impcal1;
+ PHY_LE32 phyd_txpll0;
+ PHY_LE32 phyd_txpll1;
+ //0x20
+ PHY_LE32 phyd_txpll2;
+ PHY_LE32 phyd_fl0;
+ PHY_LE32 phyd_mix2;
+ PHY_LE32 phyd_rx0;
+ //0x30
+ PHY_LE32 phyd_t2rlb;
+ PHY_LE32 phyd_cppat;
+ PHY_LE32 phyd_mix3;
+ PHY_LE32 phyd_ebufctl;
+ //0x40
+ PHY_LE32 phyd_pipe0;
+ PHY_LE32 phyd_pipe1;
+ PHY_LE32 phyd_mix4;
+ PHY_LE32 phyd_ckgen0;
+ //0x50
+ PHY_LE32 phyd_mix5;
+ PHY_LE32 phyd_reserved;
+ PHY_LE32 phyd_cdr0;
+ PHY_LE32 phyd_cdr1;
+ //0x60
+ PHY_LE32 phyd_pll_0;
+ PHY_LE32 phyd_pll_1;
+ PHY_LE32 phyd_bcn_det_1;
+ PHY_LE32 phyd_bcn_det_2;
+ //0x70
+ PHY_LE32 eq0;
+ PHY_LE32 eq1;
+ PHY_LE32 eq2;
+ PHY_LE32 eq3;
+ //0x80
+ PHY_LE32 eq_eye0;
+ PHY_LE32 eq_eye1;
+ PHY_LE32 eq_eye2;
+ PHY_LE32 eq_dfe0;
+ //0x90
+ PHY_LE32 eq_dfe1;
+ PHY_LE32 eq_dfe2;
+ PHY_LE32 eq_dfe3;
+ PHY_LE32 reserve0;
+ //0xa0
+ PHY_LE32 phyd_mon0;
+ PHY_LE32 phyd_mon1;
+ PHY_LE32 phyd_mon2;
+ PHY_LE32 phyd_mon3;
+ //0xb0
+ PHY_LE32 phyd_mon4;
+ PHY_LE32 phyd_mon5;
+ PHY_LE32 phyd_mon6;
+ PHY_LE32 phyd_mon7;
+ //0xc0
+ PHY_LE32 phya_rx_mon0;
+ PHY_LE32 phya_rx_mon1;
+ PHY_LE32 phya_rx_mon2;
+ PHY_LE32 phya_rx_mon3;
+ //0xd0
+ PHY_LE32 phya_rx_mon4;
+ PHY_LE32 phya_rx_mon5;
+ PHY_LE32 phyd_cppat2;
+ PHY_LE32 eq_eye3;
+ //0xe0
+ PHY_LE32 kband_out;
+ PHY_LE32 kband_out1;
+};
+
+//U3D_PHYD_MIX0
+#define A60810_RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
+#define A60810_RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
+#define A60810_RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
+#define A60810_RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
+#define A60810_RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
+#define A60810_RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
+#define A60810_RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
+#define A60810_RG_SSUSB_PRBS_EN (0x1<<13) //13:13
+#define A60810_RG_SSUSB_BPSLOCK (0x1<<12) //12:12
+#define A60810_RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
+#define A60810_RG_SSUSB_COMCNT (0xf<<4) //7:4
+#define A60810_RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
+
+//U3D_PHYD_MIX1
+#define A60810_RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
+#define A60810_RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
+#define A60810_RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
+#define A60810_RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
+#define A60810_RG_SSUSB_PDNCTL (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
+#define A60810_RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
+#define A60810_RG_SSUSB_BERT_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_SCP_TH (0x7<<4) //6:4
+#define A60810_RG_SSUSB_SCP_EN (0x1<<3) //3:3
+#define A60810_RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
+
+//U3D_PHYD_LFPS0
+#define A60810_RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
+#define A60810_RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
+#define A60810_RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
+#define A60810_RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
+#define A60810_RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
+#define A60810_RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
+#define A60810_RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
+#define A60810_RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
+#define A60810_RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
+#define A60810_RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
+#define A60810_RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
+#define A60810_RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
+
+//U3D_PHYD_LFPS1
+#define A60810_RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
+#define A60810_RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
+#define A60810_RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_P1_ENTRY_SEL (0x1<<14) //14:14
+#define A60810_RG_SSUSB_P1_ENTRY (0x1<<13) //13:13
+#define A60810_RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
+
+//U3D_PHYD_IMPCAL0
+#define A60810_RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
+#define A60810_RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
+#define A60810_RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
+
+//U3D_PHYD_IMPCAL1
+#define A60810_RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
+#define A60810_RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
+#define A60810_RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
+
+//U3D_PHYD_TXPLL0
+#define A60810_RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
+#define A60810_RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
+#define A60810_RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
+#define A60810_RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
+#define A60810_RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
+#define A60810_RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
+#define A60810_RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
+
+//U3D_PHYD_TXPLL1
+#define A60810_RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
+#define A60810_RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
+#define A60810_RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
+#define A60810_RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
+#define A60810_RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
+#define A60810_RG_SSUSB_PLL_PWD (0x1<<23) //23:23
+#define A60810_RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
+#define A60810_RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
+#define A60810_RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
+#define A60810_RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
+#define A60810_RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
+#define A60810_RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
+#define A60810_RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
+#define A60810_RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
+#define A60810_RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
+#define A60810_RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
+#define A60810_RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
+#define A60810_RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
+
+//U3D_PHYD_TXPLL2
+#define A60810_RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_TX_LFPS (0x1<<29) //29:29
+#define A60810_RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
+#define A60810_RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
+#define A60810_RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
+#define A60810_RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
+#define A60810_RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
+#define A60810_RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
+#define A60810_RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
+#define A60810_RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
+#define A60810_RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
+#define A60810_RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
+#define A60810_RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
+#define A60810_RG_SSUSB_CDR_PWD (0x1<<6) //6:6
+#define A60810_RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
+
+//U3D_PHYD_FL0
+#define A60810_RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
+
+//U3D_PHYD_MIX2
+#define A60810_RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
+#define A60810_RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
+#define A60810_RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
+#define A60810_RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_CDROS_EN (0x1<<18) //18:18
+#define A60810_RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
+#define A60810_RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
+#define A60810_RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
+
+//U3D_PHYD_RX0
+#define A60810_RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
+#define A60810_RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
+#define A60810_RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
+#define A60810_RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
+#define A60810_RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
+#define A60810_RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
+#define A60810_RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
+#define A60810_RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
+#define A60810_RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
+#define A60810_RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
+#define A60810_RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
+#define A60810_RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
+#define A60810_RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
+#define A60810_RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
+#define A60810_RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
+
+//U3D_PHYD_T2RLB
+#define A60810_RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
+#define A60810_RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
+#define A60810_RG_SSUSB_BPANSIENC (0x1<<26) //26:26
+#define A60810_RG_SSUSB_VALID_EN (0x1<<25) //25:25
+#define A60810_RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
+#define A60810_RG_SSUSB_K_EMP (0xf<<20) //23:20
+#define A60810_RG_SSUSB_K_FUL (0xf<<16) //19:16
+#define A60810_RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
+#define A60810_RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
+#define A60810_RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
+#define A60810_RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
+
+//U3D_PHYD_CPPAT
+#define A60810_RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
+#define A60810_RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
+#define A60810_RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
+
+//U3D_PHYD_MIX3
+#define A60810_RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
+#define A60810_RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
+#define A60810_RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
+#define A60810_RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
+#define A60810_RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
+#define A60810_RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
+#define A60810_RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
+#define A60810_RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
+#define A60810_RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
+#define A60810_RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
+#define A60810_RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
+#define A60810_RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
+
+//U3D_PHYD_EBUFCTL
+#define A60810_RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
+
+//U3D_PHYD_PIPE0
+#define A60810_RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
+#define A60810_RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
+#define A60810_RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
+#define A60810_RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
+#define A60810_RG_SSUSB_POWERDOWN (0x3<<24) //25:24
+#define A60810_RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
+#define A60810_RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
+#define A60810_RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
+#define A60810_RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
+#define A60810_RG_SSUSB_TXDATAK (0xf<<16) //19:16
+#define A60810_RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
+#define A60810_RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
+#define A60810_RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
+#define A60810_RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
+#define A60810_RG_SSUSB_FRC_PIPE_POWERDOWN (0x1<<11) //11:11
+#define A60810_RG_SSUSB_P_TXBCN_DIS (0x1<<6) //6:6
+#define A60810_RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
+#define A60810_RG_SSUSB_TXMARGIN (0x7<<1) //3:1
+#define A60810_RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
+
+//U3D_PHYD_PIPE1
+#define A60810_RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
+
+//U3D_PHYD_MIX4
+#define A60810_RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
+#define A60810_RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
+#define A60810_RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
+
+//U3D_PHYD_CKGEN0
+#define A60810_RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
+#define A60810_RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
+#define A60810_RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
+#define A60810_RG_SSUSB_RXCK_INV (0x1<<0) //0:0
+
+//U3D_PHYD_MIX5
+#define A60810_RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
+
+//U3D_PHYD_RESERVED
+#define A60810_RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
+
+//U3D_PHYD_CDR0
+#define A60810_RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
+#define A60810_RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
+#define A60810_RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
+
+//U3D_PHYD_CDR1
+#define A60810_RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
+#define A60810_RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
+
+//U3D_PHYD_PLL_0
+#define A60810_RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
+#define A60810_RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
+#define A60810_RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
+#define A60810_RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
+#define A60810_RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
+#define A60810_RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
+#define A60810_RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
+#define A60810_RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
+#define A60810_RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
+
+//U3D_PHYD_PLL_1
+#define A60810_RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
+#define A60810_RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
+#define A60810_RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
+#define A60810_RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
+
+//U3D_PHYD_BCN_DET_1
+#define A60810_RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
+
+//U3D_PHYD_BCN_DET_2
+#define A60810_RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
+#define A60810_RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
+#define A60810_RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
+
+//U3D_EQ0
+#define A60810_RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
+
+//U3D_EQ1
+#define A60810_RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
+
+//U3D_EQ2
+#define A60810_RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
+#define A60810_RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
+#define A60810_RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
+#define A60810_RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
+#define A60810_RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
+#define A60810_RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
+
+//U3D_EQ3
+#define A60810_RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
+#define A60810_RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
+#define A60810_RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
+
+//U3D_EQ_EYE0
+#define A60810_RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
+#define A60810_RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
+#define A60810_RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
+#define A60810_RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
+#define A60810_RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
+
+//U3D_EQ_EYE1
+#define A60810_RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
+
+//U3D_EQ_EYE2
+#define A60810_RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
+#define A60810_RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
+#define A60810_RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
+#define A60810_RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
+
+//U3D_EQ_DFE0
+#define A60810_RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
+#define A60810_RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
+#define A60810_RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
+#define A60810_RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
+#define A60810_RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
+
+//U3D_EQ_DFE1
+#define A60810_RG_SSUSB_EQ_REV (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
+#define A60810_RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
+#define A60810_RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
+#define A60810_RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
+#define A60810_RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
+#define A60810_RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
+#define A60810_RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
+#define A60810_RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
+
+//U3D_EQ_DFE2
+#define A60810_RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
+#define A60810_RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_EQ_DFE_TOG (0x1<<2) //2:2
+#define A60810_RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
+
+//U3D_EQ_DFE3
+#define A60810_RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
+
+//U3D_PHYD_MON0
+#define A60810_RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
+#define A60810_RGS_SSUSB_LFPS (0xf<<12) //15:12
+#define A60810_RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
+#define A60810_RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
+
+//U3D_PHYD_MON1
+#define A60810_RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
+
+//U3D_PHYD_MON2
+#define A60810_RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
+#define A60810_RGS_SSUSB_RETRACK (0xf<<12) //15:12
+#define A60810_RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
+#define A60810_RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
+#define A60810_RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
+#define A60810_RGS_SSUSB_PDNCTL (0xff<<0) //7:0
+
+//U3D_PHYD_MON3
+#define A60810_RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
+#define A60810_RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
+
+//U3D_PHYD_MON4
+#define A60810_RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
+#define A60810_RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
+#define A60810_RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
+
+//U3D_PHYD_MON5
+#define A60810_RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
+#define A60810_RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
+#define A60810_RGS_SSUSB_SCP_DET (0x1<<14) //14:14
+#define A60810_RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
+#define A60810_RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
+#define A60810_RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
+#define A60810_RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
+#define A60810_RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
+#define A60810_RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
+#define A60810_RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
+#define A60810_RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
+#define A60810_RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
+#define A60810_RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
+#define A60810_RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
+#define A60810_RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
+#define A60810_RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
+
+//U3D_PHYD_MON6
+#define A60810_RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
+#define A60810_RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
+#define A60810_RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
+#define A60810_RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
+#define A60810_RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
+#define A60810_RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
+#define A60810_RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
+
+//U3D_PHYD_MON7
+#define A60810_RGS_SSUSB_FT_OUT (0xff<<8) //15:8
+#define A60810_RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
+
+//U3D_PHYA_RX_MON0
+#define A60810_RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
+#define A60810_RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
+#define A60810_RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
+#define A60810_RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
+
+//U3D_PHYA_RX_MON1
+#define A60810_RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
+#define A60810_RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
+#define A60810_RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
+#define A60810_RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
+
+//U3D_PHYA_RX_MON2
+#define A60810_RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
+#define A60810_RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
+#define A60810_RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
+#define A60810_RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
+#define A60810_RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
+
+//U3D_PHYA_RX_MON3
+#define A60810_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
+
+//U3D_PHYA_RX_MON4
+#define A60810_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
+
+//U3D_PHYA_RX_MON5
+#define A60810_RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
+#define A60810_RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
+#define A60810_RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
+
+//U3D_PHYD_CPPAT2
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
+
+//U3D_EQ_EYE3
+#define A60810_RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
+#define A60810_RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
+
+//U3D_KBAND_OUT
+#define A60810_RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
+#define A60810_RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
+#define A60810_RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
+#define A60810_RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
+
+//U3D_KBAND_OUT1
+#define A60810_RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
+#define A60810_RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
+#define A60810_RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
+#define A60810_RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
+
+/* OFFSET */
+
+//U3D_PHYD_MIX0
+#define A60810_RG_SSUSB_P_P3_TX_NG_OFST (31)
+#define A60810_RG_SSUSB_TSEQ_EN_OFST (30)
+#define A60810_RG_SSUSB_TSEQ_POLEN_OFST (29)
+#define A60810_RG_SSUSB_TSEQ_POL_OFST (28)
+#define A60810_RG_SSUSB_P_P3_PCLK_NG_OFST (27)
+#define A60810_RG_SSUSB_TSEQ_TH_OFST (24)
+#define A60810_RG_SSUSB_PRBS_BERTH_OFST (16)
+#define A60810_RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
+#define A60810_RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
+#define A60810_RG_SSUSB_PRBS_EN_OFST (13)
+#define A60810_RG_SSUSB_BPSLOCK_OFST (12)
+#define A60810_RG_SSUSB_RTCOMCNT_OFST (8)
+#define A60810_RG_SSUSB_COMCNT_OFST (4)
+#define A60810_RG_SSUSB_PRBSEL_CALIB_OFST (0)
+
+//U3D_PHYD_MIX1
+#define A60810_RG_SSUSB_SLEEP_EN_OFST (31)
+#define A60810_RG_SSUSB_PRBSEL_PCS_OFST (28)
+#define A60810_RG_SSUSB_TXLFPS_PRD_OFST (24)
+#define A60810_RG_SSUSB_P_RX_P0S_CK_OFST (23)
+#define A60810_RG_SSUSB_P_TX_P0S_CK_OFST (22)
+#define A60810_RG_SSUSB_PDNCTL_OFST (16)
+#define A60810_RG_SSUSB_TX_DRV_EN_OFST (15)
+#define A60810_RG_SSUSB_TX_DRV_SEL_OFST (14)
+#define A60810_RG_SSUSB_TX_DRV_DLY_OFST (8)
+#define A60810_RG_SSUSB_BERT_EN_OFST (7)
+#define A60810_RG_SSUSB_SCP_TH_OFST (4)
+#define A60810_RG_SSUSB_SCP_EN_OFST (3)
+#define A60810_RG_SSUSB_RXANSIDEC_TEST_OFST (0)
+
+//U3D_PHYD_LFPS0
+#define A60810_RG_SSUSB_LFPS_PWD_OFST (30)
+#define A60810_RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
+#define A60810_RG_SSUSB_RXLFPS_OVF_OFST (24)
+#define A60810_RG_SSUSB_P3_ENTRY_SEL_OFST (23)
+#define A60810_RG_SSUSB_P3_ENTRY_OFST (22)
+#define A60810_RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
+#define A60810_RG_SSUSB_RXLFPS_CDRTH_OFST (16)
+#define A60810_RG_SSUSB_LOCK5G_BLOCK_OFST (15)
+#define A60810_RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
+#define A60810_RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
+#define A60810_RG_SSUSB_RXLFPS_LOB_OFST (8)
+#define A60810_RG_SSUSB_TXLFPS_EN_OFST (7)
+#define A60810_RG_SSUSB_TXLFPS_SEL_OFST (6)
+#define A60810_RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
+#define A60810_RG_SSUSB_RXLFPS_UPB_OFST (0)
+
+//U3D_PHYD_LFPS1
+#define A60810_RG_SSUSB_RX_IMP_BIAS_OFST (28)
+#define A60810_RG_SSUSB_TX_IMP_BIAS_OFST (24)
+#define A60810_RG_SSUSB_FWAKE_TH_OFST (16)
+#define A60810_RG_SSUSB_P1_ENTRY_SEL_OFST (14)
+#define A60810_RG_SSUSB_P1_ENTRY_OFST (13)
+#define A60810_RG_SSUSB_RXLFPS_UDF_OFST (8)
+#define A60810_RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
+
+//U3D_PHYD_IMPCAL0
+#define A60810_RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
+#define A60810_RG_SSUSB_TX_IMPCAL_EN_OFST (30)
+#define A60810_RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
+#define A60810_RG_SSUSB_TX_IMPSEL_OFST (24)
+#define A60810_RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
+#define A60810_RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
+#define A60810_RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
+
+//U3D_PHYD_IMPCAL1
+#define A60810_RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
+#define A60810_RG_SSUSB_RX_IMPCAL_EN_OFST (30)
+#define A60810_RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
+#define A60810_RG_SSUSB_RX_IMPSEL_OFST (24)
+#define A60810_RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
+#define A60810_RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
+#define A60810_RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
+
+//U3D_PHYD_TXPLL0
+#define A60810_RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
+#define A60810_RG_SSUSB_TXPLL_ON_OFST (26)
+#define A60810_RG_SSUSB_FORCE_TXPLLON_OFST (25)
+#define A60810_RG_SSUSB_TXPLL_STBCYC_OFST (16)
+#define A60810_RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
+#define A60810_RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
+#define A60810_RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
+
+//U3D_PHYD_TXPLL1
+#define A60810_RG_SSUSB_PLL_NCPO_EN_OFST (31)
+#define A60810_RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
+#define A60810_RG_SSUSB_PLL_NCPO_CHG_OFST (28)
+#define A60810_RG_SSUSB_PLL_DDS_RSTB_OFST (27)
+#define A60810_RG_SSUSB_PLL_DDS_PWDB_OFST (26)
+#define A60810_RG_SSUSB_PLL_DDSEN_OFST (25)
+#define A60810_RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
+#define A60810_RG_SSUSB_PLL_PWD_OFST (23)
+#define A60810_RG_SSUSB_RX_AFE_PWD_OFST (22)
+#define A60810_RG_SSUSB_PLL_TCADJ_OFST (16)
+#define A60810_RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
+#define A60810_RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
+#define A60810_RG_SSUSB_FORCE_CDR_PWD_OFST (13)
+#define A60810_RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
+#define A60810_RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
+#define A60810_RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
+#define A60810_RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
+#define A60810_RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
+#define A60810_RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
+#define A60810_RG_SSUSB_FORCE_PLL_PWD_OFST (3)
+#define A60810_RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
+
+//U3D_PHYD_TXPLL2
+#define A60810_RG_SSUSB_TX_LFPS_EN_OFST (31)
+#define A60810_RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
+#define A60810_RG_SSUSB_TX_LFPS_OFST (29)
+#define A60810_RG_SSUSB_FORCE_TX_LFPS_OFST (28)
+#define A60810_RG_SSUSB_RXPLL_STB_OFST (27)
+#define A60810_RG_SSUSB_TXPLL_STB_OFST (26)
+#define A60810_RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
+#define A60810_RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
+#define A60810_RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
+#define A60810_RG_SSUSB_RXPLL_STBMODE_OFST (11)
+#define A60810_RG_SSUSB_RXPLL_ON_OFST (10)
+#define A60810_RG_SSUSB_FORCE_RXPLLON_OFST (9)
+#define A60810_RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
+#define A60810_RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
+#define A60810_RG_SSUSB_CDR_PWD_OFST (6)
+#define A60810_RG_SSUSB_CDR_TCADJ_OFST (0)
+
+//U3D_PHYD_FL0
+#define A60810_RG_SSUSB_RX_FL_TARGET_OFST (16)
+#define A60810_RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
+
+//U3D_PHYD_MIX2
+#define A60810_RG_SSUSB_RX_EQ_RST_OFST (31)
+#define A60810_RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
+#define A60810_RG_SSUSB_RXVAL_RST_OFST (29)
+#define A60810_RG_SSUSB_RXVAL_CNT_OFST (24)
+#define A60810_RG_SSUSB_CDROS_EN_OFST (18)
+#define A60810_RG_SSUSB_CDR_LCKOP_OFST (16)
+#define A60810_RG_SSUSB_RX_FL_LOCKTH_OFST (8)
+#define A60810_RG_SSUSB_RX_FL_OFFSET_OFST (0)
+
+//U3D_PHYD_RX0
+#define A60810_RG_SSUSB_T2RLB_BERTH_OFST (24)
+#define A60810_RG_SSUSB_T2RLB_PAT_OFST (16)
+#define A60810_RG_SSUSB_T2RLB_EN_OFST (15)
+#define A60810_RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
+#define A60810_RG_SSUSB_T2RLB_SERIAL_OFST (13)
+#define A60810_RG_SSUSB_T2RLB_MODE_OFST (11)
+#define A60810_RG_SSUSB_RX_SAOSC_EN_OFST (10)
+#define A60810_RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
+#define A60810_RG_SSUSB_RX_DFE_OPTION_OFST (8)
+#define A60810_RG_SSUSB_RX_DFE_EN_OFST (7)
+#define A60810_RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
+#define A60810_RG_SSUSB_RX_EQ_EN_OFST (5)
+#define A60810_RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
+#define A60810_RG_SSUSB_RX_SAOSC_RST_OFST (3)
+#define A60810_RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
+#define A60810_RG_SSUSB_RX_DFE_RST_OFST (1)
+#define A60810_RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
+
+//U3D_PHYD_T2RLB
+#define A60810_RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
+#define A60810_RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
+#define A60810_RG_SSUSB_BPANSIENC_OFST (26)
+#define A60810_RG_SSUSB_VALID_EN_OFST (25)
+#define A60810_RG_SSUSB_EBUF_SRST_OFST (24)
+#define A60810_RG_SSUSB_K_EMP_OFST (20)
+#define A60810_RG_SSUSB_K_FUL_OFST (16)
+#define A60810_RG_SSUSB_T2RLB_BDATRST_OFST (12)
+#define A60810_RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
+#define A60810_RG_SSUSB_T2RLB_PATMODE_OFST (8)
+#define A60810_RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
+
+//U3D_PHYD_CPPAT
+#define A60810_RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
+#define A60810_RG_SSUSB_CPPAT_TOZ_OFST (21)
+#define A60810_RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
+#define A60810_RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
+
+//U3D_PHYD_MIX3
+#define A60810_RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
+#define A60810_RG_SSUSB_P_CDROS_EN_OFST (30)
+#define A60810_RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
+#define A60810_RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
+#define A60810_RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
+#define A60810_RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
+#define A60810_RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
+#define A60810_RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
+#define A60810_RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
+#define A60810_RG_SSUSB_PLL_SSCEN_OFST (14)
+#define A60810_RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
+#define A60810_RG_SSUSB_CDR_PI_PWD_OFST (12)
+#define A60810_RG_SSUSB_CDR_PI_MODE_OFST (11)
+#define A60810_RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
+
+//U3D_PHYD_EBUFCTL
+#define A60810_RG_SSUSB_EBUFCTL_OFST (0)
+
+//U3D_PHYD_PIPE0
+#define A60810_RG_SSUSB_RXTERMINATION_OFST (30)
+#define A60810_RG_SSUSB_RXEQTRAINING_OFST (29)
+#define A60810_RG_SSUSB_RXPOLARITY_OFST (28)
+#define A60810_RG_SSUSB_TXDEEMPH_OFST (26)
+#define A60810_RG_SSUSB_POWERDOWN_OFST (24)
+#define A60810_RG_SSUSB_TXONESZEROS_OFST (23)
+#define A60810_RG_SSUSB_TXELECIDLE_OFST (22)
+#define A60810_RG_SSUSB_TXDETECTRX_OFST (21)
+#define A60810_RG_SSUSB_PIPE_SEL_OFST (20)
+#define A60810_RG_SSUSB_TXDATAK_OFST (16)
+#define A60810_RG_SSUSB_CDR_STABLE_SEL_OFST (15)
+#define A60810_RG_SSUSB_CDR_STABLE_OFST (14)
+#define A60810_RG_SSUSB_CDR_RSTB_SEL_OFST (13)
+#define A60810_RG_SSUSB_CDR_RSTB_OFST (12)
+#define A60810_RG_SSUSB_FRC_PIPE_POWERDOWN_OFST (11)
+#define A60810_RG_SSUSB_P_TXBCN_DIS_OFST (6)
+#define A60810_RG_SSUSB_P_ERROR_SEL_OFST (4)
+#define A60810_RG_SSUSB_TXMARGIN_OFST (1)
+#define A60810_RG_SSUSB_TXCOMPLIANCE_OFST (0)
+
+//U3D_PHYD_PIPE1
+#define A60810_RG_SSUSB_TXDATA_OFST (0)
+
+//U3D_PHYD_MIX4
+#define A60810_RG_SSUSB_CDROS_CNT_OFST (24)
+#define A60810_RG_SSUSB_T2RLB_BER_EN_OFST (16)
+#define A60810_RG_SSUSB_T2RLB_BER_RATE_OFST (0)
+
+//U3D_PHYD_CKGEN0
+#define A60810_RG_SSUSB_RFIFO_IMPLAT_OFST (27)
+#define A60810_RG_SSUSB_TFIFO_PSEL_OFST (24)
+#define A60810_RG_SSUSB_CKGEN_PSEL_OFST (8)
+#define A60810_RG_SSUSB_RXCK_INV_OFST (0)
+
+//U3D_PHYD_MIX5
+#define A60810_RG_SSUSB_PRB_SEL_OFST (16)
+#define A60810_RG_SSUSB_RXPLL_STBCYC_OFST (0)
+
+//U3D_PHYD_RESERVED
+#define A60810_RG_SSUSB_PHYD_RESERVE_OFST (0)
+
+//U3D_PHYD_CDR0
+#define A60810_RG_SSUSB_CDR_BIC_LTR_OFST (28)
+#define A60810_RG_SSUSB_CDR_BIC_LTD0_OFST (24)
+#define A60810_RG_SSUSB_CDR_BC_LTD1_OFST (16)
+#define A60810_RG_SSUSB_CDR_BC_LTR_OFST (8)
+#define A60810_RG_SSUSB_CDR_BC_LTD0_OFST (0)
+
+//U3D_PHYD_CDR1
+#define A60810_RG_SSUSB_CDR_BIR_LTD1_OFST (24)
+#define A60810_RG_SSUSB_CDR_BIR_LTR_OFST (16)
+#define A60810_RG_SSUSB_CDR_BIR_LTD0_OFST (8)
+#define A60810_RG_SSUSB_CDR_BW_SEL_OFST (6)
+#define A60810_RG_SSUSB_CDR_BIC_LTD1_OFST (0)
+
+//U3D_PHYD_PLL_0
+#define A60810_RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
+#define A60810_RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
+#define A60810_RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
+#define A60810_RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
+#define A60810_RG_SSUSB_P_EQ_T_SEL_OFST (15)
+#define A60810_RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
+#define A60810_RG_SSUSB_PLLBAND_RECAL_OFST (4)
+#define A60810_RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
+#define A60810_RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
+
+//U3D_PHYD_PLL_1
+#define A60810_RG_SSUSB_CDR_BAND_5G_OFST (24)
+#define A60810_RG_SSUSB_CDR_BAND_2P5G_OFST (16)
+#define A60810_RG_SSUSB_PLL_BAND_5G_OFST (8)
+#define A60810_RG_SSUSB_PLL_BAND_2P5G_OFST (0)
+
+//U3D_PHYD_BCN_DET_1
+#define A60810_RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
+#define A60810_RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
+
+//U3D_PHYD_BCN_DET_2
+#define A60810_RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
+#define A60810_RG_SSUSB_BCN_DET_DIS_OFST (12)
+#define A60810_RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
+
+//U3D_EQ0
+#define A60810_RG_SSUSB_EQ_DLHL_LFI_OFST (24)
+#define A60810_RG_SSUSB_EQ_DHHL_LFI_OFST (16)
+#define A60810_RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
+#define A60810_RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
+
+//U3D_EQ1
+#define A60810_RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
+#define A60810_RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
+#define A60810_RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
+#define A60810_RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
+
+//U3D_EQ2
+#define A60810_RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
+#define A60810_RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
+#define A60810_RG_SSUSB_EQ_STOPTIME_OFST (14)
+#define A60810_RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
+#define A60810_RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
+#define A60810_RG_SSUSB_EQ_STARTTIME_OFST (6)
+#define A60810_RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
+#define A60810_RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
+
+//U3D_EQ3
+#define A60810_RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
+#define A60810_RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
+#define A60810_RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
+#define A60810_RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
+#define A60810_RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
+#define A60810_RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
+
+//U3D_EQ_EYE0
+#define A60810_RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
+#define A60810_RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
+#define A60810_RG_SSUSB_EQ_EYE0_Y_OFST (16)
+#define A60810_RG_SSUSB_EQ_EYE1_Y_OFST (8)
+#define A60810_RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
+#define A60810_RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
+#define A60810_RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
+
+//U3D_EQ_EYE1
+#define A60810_RG_SSUSB_EQ_SIGDET_OFST (24)
+#define A60810_RG_SSUSB_EQ_EYE_MASK_OFST (7)
+
+//U3D_EQ_EYE2
+#define A60810_RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
+#define A60810_RG_SSUSB_EQ_SD_CNT1_OFST (24)
+#define A60810_RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
+#define A60810_RG_SSUSB_EQ_SD_CNT0_OFST (16)
+
+//U3D_EQ_DFE0
+#define A60810_RG_SSUSB_EQ_LEQMAX_OFST (28)
+#define A60810_RG_SSUSB_EQ_DFEX_EN_OFST (27)
+#define A60810_RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
+#define A60810_RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
+#define A60810_RG_SSUSB_EQ_PIEYE_INI_OFST (16)
+#define A60810_RG_SSUSB_EQ_PI90_INI_OFST (8)
+#define A60810_RG_SSUSB_EQ_PI0_INI_OFST (0)
+
+//U3D_EQ_DFE1
+#define A60810_RG_SSUSB_EQ_REV_OFST (16)
+#define A60810_RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
+#define A60810_RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
+#define A60810_RG_SSUSB_EQ_DFEX_RST_OFST (7)
+#define A60810_RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
+#define A60810_RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
+#define A60810_RG_SSUSB_EQ_DFEX_DIS_OFST (2)
+#define A60810_RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
+#define A60810_RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
+
+//U3D_EQ_DFE2
+#define A60810_RG_SSUSB_EQ_MON_SEL_OFST (24)
+#define A60810_RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
+#define A60810_RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
+#define A60810_RG_SSUSB_EQ_DFE_TOG_OFST (2)
+#define A60810_RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
+
+//U3D_EQ_DFE3
+#define A60810_RG_SSUSB_EQ_RESERVED_OFST (0)
+
+//U3D_PHYD_MON0
+#define A60810_RGS_SSUSB_BERT_BERC_OFST (16)
+#define A60810_RGS_SSUSB_LFPS_OFST (12)
+#define A60810_RGS_SSUSB_TRAINDEC_OFST (8)
+#define A60810_RGS_SSUSB_SCP_PAT_OFST (0)
+
+//U3D_PHYD_MON1
+#define A60810_RGS_SSUSB_RX_FL_OUT_OFST (0)
+
+//U3D_PHYD_MON2
+#define A60810_RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
+#define A60810_RGS_SSUSB_RETRACK_OFST (12)
+#define A60810_RGS_SSUSB_RXPLL_LOCK_OFST (10)
+#define A60810_RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
+#define A60810_RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
+#define A60810_RGS_SSUSB_PDNCTL_OFST (0)
+
+//U3D_PHYD_MON3
+#define A60810_RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
+#define A60810_RGS_SSUSB_PRBS_ERRCNT_OFST (0)
+
+//U3D_PHYD_MON4
+#define A60810_RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
+#define A60810_RGS_SSUSB_SCP_DETCNT_OFST (16)
+#define A60810_RGS_SSUSB_TSEQ_DETCNT_OFST (0)
+
+//U3D_PHYD_MON5
+#define A60810_RGS_SSUSB_EBUFMSG_OFST (16)
+#define A60810_RGS_SSUSB_BERT_LOCK_OFST (15)
+#define A60810_RGS_SSUSB_SCP_DET_OFST (14)
+#define A60810_RGS_SSUSB_TSEQ_DET_OFST (13)
+#define A60810_RGS_SSUSB_EBUF_UDF_OFST (12)
+#define A60810_RGS_SSUSB_EBUF_OVF_OFST (11)
+#define A60810_RGS_SSUSB_PRBS_PASSTH_OFST (10)
+#define A60810_RGS_SSUSB_PRBS_PASS_OFST (9)
+#define A60810_RGS_SSUSB_PRBS_LOCK_OFST (8)
+#define A60810_RGS_SSUSB_T2RLB_ERR_OFST (6)
+#define A60810_RGS_SSUSB_T2RLB_PASSTH_OFST (5)
+#define A60810_RGS_SSUSB_T2RLB_PASS_OFST (4)
+#define A60810_RGS_SSUSB_T2RLB_LOCK_OFST (3)
+#define A60810_RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
+#define A60810_RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
+#define A60810_RGS_SSUSB_RXDETECTED_OFST (0)
+
+//U3D_PHYD_MON6
+#define A60810_RGS_SSUSB_SIGCAL_DONE_OFST (30)
+#define A60810_RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
+#define A60810_RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
+#define A60810_RGS_SSUSB_RX_IMP_SEL_OFST (16)
+#define A60810_RGS_SSUSB_TX_IMP_SEL_OFST (8)
+#define A60810_RGS_SSUSB_TFIFO_MSG_OFST (4)
+#define A60810_RGS_SSUSB_RFIFO_MSG_OFST (0)
+
+//U3D_PHYD_MON7
+#define A60810_RGS_SSUSB_FT_OUT_OFST (8)
+#define A60810_RGS_SSUSB_PRB_OUT_OFST (0)
+
+//U3D_PHYA_RX_MON0
+#define A60810_RGS_SSUSB_EQ_DCLEQ_OFST (24)
+#define A60810_RGS_SSUSB_EQ_DCD0H_OFST (16)
+#define A60810_RGS_SSUSB_EQ_DCD0L_OFST (8)
+#define A60810_RGS_SSUSB_EQ_DCD1H_OFST (0)
+
+//U3D_PHYA_RX_MON1
+#define A60810_RGS_SSUSB_EQ_DCD1L_OFST (24)
+#define A60810_RGS_SSUSB_EQ_DCE0_OFST (16)
+#define A60810_RGS_SSUSB_EQ_DCE1_OFST (8)
+#define A60810_RGS_SSUSB_EQ_DCHHL_OFST (0)
+
+//U3D_PHYA_RX_MON2
+#define A60810_RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
+#define A60810_RGS_SSUSB_EQ_DCLHL_OFST (24)
+#define A60810_RGS_SSUSB_EQ_STATUS_OFST (16)
+#define A60810_RGS_SSUSB_EQ_DCEYE0_OFST (8)
+#define A60810_RGS_SSUSB_EQ_DCEYE1_OFST (0)
+
+//U3D_PHYA_RX_MON3
+#define A60810_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
+
+//U3D_PHYA_RX_MON4
+#define A60810_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
+
+//U3D_PHYA_RX_MON5
+#define A60810_RGS_SSUSB_EQ_DCLEQOS_OFST (8)
+#define A60810_RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
+#define A60810_RGS_SSUSB_EQ_PILPO_OFST (0)
+
+//U3D_PHYD_CPPAT2
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
+#define A60810_RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
+
+//U3D_EQ_EYE3
+#define A60810_RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
+#define A60810_RG_SSUSB_EQ_EYE_CNT_OFST (0)
+
+//U3D_KBAND_OUT
+#define A60810_RGS_SSUSB_CDR_BAND_5G_OFST (24)
+#define A60810_RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
+#define A60810_RGS_SSUSB_PLL_BAND_5G_OFST (8)
+#define A60810_RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
+
+//U3D_KBAND_OUT1
+#define A60810_RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
+#define A60810_RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
+#define A60810_RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
+#define A60810_RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct u3phyd_bank2_reg_a {
+ //0x0
+ PHY_LE32 b2_phyd_top1;
+ PHY_LE32 b2_phyd_top2;
+ PHY_LE32 b2_phyd_top3;
+ PHY_LE32 b2_phyd_top4;
+ //0x10
+ PHY_LE32 b2_phyd_top5;
+ PHY_LE32 b2_phyd_top6;
+ PHY_LE32 b2_phyd_top7;
+ PHY_LE32 b2_phyd_p_sigdet1;
+ //0x20
+ PHY_LE32 b2_phyd_p_sigdet2;
+ PHY_LE32 b2_phyd_p_sigdet_cal1;
+ PHY_LE32 b2_phyd_rxdet1;
+ PHY_LE32 b2_phyd_rxdet2;
+ //0x30
+ PHY_LE32 b2_phyd_misc0;
+ PHY_LE32 b2_phyd_misc2;
+ PHY_LE32 b2_phyd_misc3;
+ PHY_LE32 b2_phyd_l1ss;
+ //0x40
+ PHY_LE32 b2_rosc_0;
+ PHY_LE32 b2_rosc_1;
+ PHY_LE32 b2_rosc_2;
+ PHY_LE32 b2_rosc_3;
+ //0x50
+ PHY_LE32 b2_rosc_4;
+ PHY_LE32 b2_rosc_5;
+ PHY_LE32 b2_rosc_6;
+ PHY_LE32 b2_rosc_7;
+ //0x60
+ PHY_LE32 b2_rosc_8;
+ PHY_LE32 b2_rosc_9;
+ PHY_LE32 b2_rosc_a;
+ PHY_LE32 reserve1;
+ //0x70~0xd0
+ PHY_LE32 reserve2[28];
+ //0xe0
+ PHY_LE32 phyd_version;
+ PHY_LE32 phyd_model;
+};
+
+//U3D_B2_PHYD_TOP1
+#define A60810_RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
+#define A60810_RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
+#define A60810_RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
+#define A60810_RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
+#define A60810_RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
+#define A60810_RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
+#define A60810_RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
+#define A60810_RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
+#define A60810_RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
+#define A60810_RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
+#define A60810_RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
+#define A60810_RG_SSUSB_RATE (0x1<<6) //6:6
+#define A60810_RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
+#define A60810_RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
+#define A60810_RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
+#define A60810_RG_SSUSB_PHY_MODE (0x3<<1) //2:1
+#define A60810_RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
+
+//U3D_B2_PHYD_TOP2
+#define A60810_RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
+#define A60810_RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
+#define A60810_RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
+#define A60810_RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
+#define A60810_RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
+#define A60810_RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
+#define A60810_RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
+#define A60810_RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
+
+//U3D_B2_PHYD_TOP3
+#define A60810_RG_SSUSB_TX_BIASI (0x7<<25) //27:25
+#define A60810_RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
+#define A60810_RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
+#define A60810_RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
+#define A60810_RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
+#define A60810_RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
+
+//U3D_B2_PHYD_TOP4
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
+#define A60810_RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_G1_L1SS_CDR_BW_SEL (0x3<<13) //14:13
+#define A60810_RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_G1_CDR_BW_SEL (0x3<<5) //6:5
+#define A60810_RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
+
+//U3D_B2_PHYD_TOP5
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
+
+//U3D_B2_PHYD_TOP6
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
+#define A60810_RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_G2_L1SS_CDR_BW_SEL (0x3<<13) //14:13
+#define A60810_RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_G2_CDR_BW_SEL (0x3<<5) //6:5
+#define A60810_RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
+
+//U3D_B2_PHYD_TOP7
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
+
+//U3D_B2_PHYD_P_SIGDET1
+#define A60810_RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
+#define A60810_RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
+#define A60810_RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
+#define A60810_RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
+
+//U3D_B2_PHYD_P_SIGDET2
+#define A60810_RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
+#define A60810_RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
+#define A60810_RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
+#define A60810_RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
+#define A60810_RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
+#define A60810_RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
+#define A60810_RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
+#define A60810_RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
+#define A60810_RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
+#define A60810_RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
+#define A60810_RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
+#define A60810_RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
+#define A60810_RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
+
+//U3D_B2_PHYD_P_SIGDET_CAL1
+#define A60810_RG_SSUSB_G2_2EIOS_DET_EN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
+#define A60810_RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
+#define A60810_RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
+#define A60810_RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
+#define A60810_RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
+#define A60810_RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
+#define A60810_RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
+
+//U3D_B2_PHYD_RXDET1
+#define A60810_RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
+#define A60810_RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
+#define A60810_RG_SSUSB_RXDET_EN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
+#define A60810_RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
+#define A60810_RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
+#define A60810_RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
+
+//U3D_B2_PHYD_RXDET2
+#define A60810_RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
+#define A60810_RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
+#define A60810_RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
+#define A60810_RG_SSUSB_LCK2REF_EXT_EN (0x1<<28) //28:28
+#define A60810_RG_SSUSB_G2_LCK2REF_EXT_SEL (0xf<<24) //27:24
+#define A60810_RG_SSUSB_LCK2REF_EXT_SEL (0xf<<20) //23:20
+#define A60810_RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
+#define A60810_RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
+#define A60810_RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
+
+//U3D_B2_PHYD_MISC0
+#define A60810_RG_SSUSB_TX_EIDLE_LP_P0DLYCYC (0x3f<<26) //31:26
+#define A60810_RG_SSUSB_TX_SER_EN (0x1<<25) //25:25
+#define A60810_RG_SSUSB_FORCE_TX_SER_EN (0x1<<24) //24:24
+#define A60810_RG_SSUSB_TXPLL_REFCKSEL (0x1<<23) //23:23
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
+#define A60810_RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
+#define A60810_RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
+#define A60810_RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
+#define A60810_RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
+#define A60810_RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
+#define A60810_RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
+#define A60810_RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
+#define A60810_RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
+#define A60810_RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
+#define A60810_RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
+#define A60810_RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
+#define A60810_RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
+#define A60810_RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
+#define A60810_RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
+#define A60810_RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
+
+//U3D_B2_PHYD_MISC2
+#define A60810_RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
+#define A60810_RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
+#define A60810_RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
+#define A60810_RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
+#define A60810_RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
+#define A60810_RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
+#define A60810_RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
+#define A60810_RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
+#define A60810_RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
+#define A60810_RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
+#define A60810_RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
+
+//U3D_B2_PHYD_MISC3
+#define A60810_RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
+#define A60810_RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
+
+//U3D_B2_PHYD_L1SS
+#define A60810_RG_SSUSB_L1SS_REV1 (0xff<<24) //31:24
+#define A60810_RG_SSUSB_L1SS_REV0 (0xff<<16) //23:16
+#define A60810_RG_SSUSB_P_LTD1_SLOCK_DIS (0x1<<11) //11:11
+#define A60810_RG_SSUSB_PLL_CNT_CLEAN_DIS (0x1<<10) //10:10
+#define A60810_RG_SSUSB_P_PLL_REK_SEL (0x1<<9) //9:9
+#define A60810_RG_SSUSB_TXDRV_MASKDLY (0x1<<8) //8:8
+#define A60810_RG_SSUSB_RXSTS_VAL (0x1<<7) //7:7
+#define A60810_RG_PCIE_PHY_CLKREQ_N_EN (0x1<<6) //6:6
+#define A60810_RG_PCIE_FORCE_PHY_CLKREQ_N_EN (0x1<<5) //5:5
+#define A60810_RG_PCIE_PHY_CLKREQ_N_OUT (0x1<<4) //4:4
+#define A60810_RG_PCIE_FORCE_PHY_CLKREQ_N_OUT (0x1<<3) //3:3
+#define A60810_RG_SSUSB_RXPLL_STB_PX0 (0x1<<2) //2:2
+#define A60810_RG_PCIE_L1SS_EN (0x1<<1) //1:1
+#define A60810_RG_PCIE_FORCE_L1SS_EN (0x1<<0) //0:0
+
+//U3D_B2_ROSC_0
+#define A60810_RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
+#define A60810_RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
+#define A60810_RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
+#define A60810_RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
+#define A60810_RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
+#define A60810_RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
+
+//U3D_B2_ROSC_1
+#define A60810_RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
+#define A60810_RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
+#define A60810_RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
+#define A60810_RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
+#define A60810_RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
+#define A60810_RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
+
+//U3D_B2_ROSC_2
+#define A60810_RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_3
+#define A60810_RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_4
+#define A60810_RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_5
+#define A60810_RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_6
+#define A60810_RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_7
+#define A60810_RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
+
+//U3D_B2_ROSC_8
+#define A60810_RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
+#define A60810_RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
+#define A60810_RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
+#define A60810_RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
+
+//U3D_B2_ROSC_9
+#define A60810_RGS_FM_RING_CNT (0xffff<<16) //31:16
+#define A60810_RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
+#define A60810_RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
+#define A60810_RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
+#define A60810_RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
+
+//U3D_B2_ROSC_A
+#define A60810_RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
+
+//U3D_PHYD_VERSION
+#define A60810_RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
+
+//U3D_PHYD_MODEL
+#define A60810_RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
+
+/* OFFSET */
+
+//U3D_B2_PHYD_TOP1
+#define A60810_RG_SSUSB_PCIE2_K_EMP_OFST (28)
+#define A60810_RG_SSUSB_PCIE2_K_FUL_OFST (24)
+#define A60810_RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
+#define A60810_RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
+#define A60810_RG_SSUSB_SIGDET_EN_OFST (15)
+#define A60810_RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
+#define A60810_RG_SSUSB_CLKRX_EN_OFST (13)
+#define A60810_RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
+#define A60810_RG_SSUSB_CLKTX_EN_OFST (11)
+#define A60810_RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
+#define A60810_RG_SSUSB_CLK_REQ_N_I_OFST (9)
+#define A60810_RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
+#define A60810_RG_SSUSB_RATE_OFST (6)
+#define A60810_RG_SSUSB_FORCE_RATE_OFST (5)
+#define A60810_RG_SSUSB_PCIE_MODE_SEL_OFST (4)
+#define A60810_RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
+#define A60810_RG_SSUSB_PHY_MODE_OFST (1)
+#define A60810_RG_SSUSB_FORCE_PHY_MODE_OFST (0)
+
+//U3D_B2_PHYD_TOP2
+#define A60810_RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
+#define A60810_RG_SSUSB_IDRV_6DB_OFST (24)
+#define A60810_RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
+#define A60810_RG_SSUSB_IDEM_3P5DB_OFST (16)
+#define A60810_RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
+#define A60810_RG_SSUSB_IDRV_3P5DB_OFST (8)
+#define A60810_RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
+#define A60810_RG_SSUSB_IDRV_0DB_OFST (0)
+
+//U3D_B2_PHYD_TOP3
+#define A60810_RG_SSUSB_TX_BIASI_OFST (25)
+#define A60810_RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
+#define A60810_RG_SSUSB_TX_BIASI_EN_OFST (16)
+#define A60810_RG_SSUSB_FORCE_TX_BIASI_OFST (13)
+#define A60810_RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
+#define A60810_RG_SSUSB_IDEM_6DB_OFST (0)
+
+//U3D_B2_PHYD_TOP4
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
+#define A60810_RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
+#define A60810_RG_SSUSB_G1_L1SS_CDR_BW_SEL_OFST (13)
+#define A60810_RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
+#define A60810_RG_SSUSB_G1_CDR_BW_SEL_OFST (5)
+#define A60810_RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
+
+//U3D_B2_PHYD_TOP5
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
+#define A60810_RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
+#define A60810_RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
+
+//U3D_B2_PHYD_TOP6
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
+#define A60810_RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
+#define A60810_RG_SSUSB_G2_L1SS_CDR_BW_SEL_OFST (13)
+#define A60810_RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
+#define A60810_RG_SSUSB_G2_CDR_BW_SEL_OFST (5)
+#define A60810_RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
+
+//U3D_B2_PHYD_TOP7
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
+#define A60810_RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
+#define A60810_RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
+
+//U3D_B2_PHYD_P_SIGDET1
+#define A60810_RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
+#define A60810_RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
+#define A60810_RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
+#define A60810_RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
+#define A60810_RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
+
+//U3D_B2_PHYD_P_SIGDET2
+#define A60810_RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
+#define A60810_RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
+#define A60810_RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
+#define A60810_RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
+#define A60810_RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
+#define A60810_RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
+#define A60810_RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
+#define A60810_RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
+#define A60810_RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
+#define A60810_RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
+#define A60810_RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
+#define A60810_RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
+#define A60810_RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
+
+//U3D_B2_PHYD_P_SIGDET_CAL1
+#define A60810_RG_SSUSB_G2_2EIOS_DET_EN_OFST (29)
+#define A60810_RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
+#define A60810_RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
+#define A60810_RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
+#define A60810_RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
+#define A60810_RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
+#define A60810_RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
+#define A60810_RG_SSUSB_P_SIGDET_REK_OFST (0)
+
+//U3D_B2_PHYD_RXDET1
+#define A60810_RG_SSUSB_RXDET_PRB_SEL_OFST (31)
+#define A60810_RG_SSUSB_FORCE_CMDET_OFST (30)
+#define A60810_RG_SSUSB_RXDET_EN_OFST (29)
+#define A60810_RG_SSUSB_FORCE_RXDET_EN_OFST (28)
+#define A60810_RG_SSUSB_RXDET_K_TWICE_OFST (27)
+#define A60810_RG_SSUSB_RXDET_STB3_SET_OFST (18)
+#define A60810_RG_SSUSB_RXDET_STB2_SET_OFST (9)
+#define A60810_RG_SSUSB_RXDET_STB1_SET_OFST (0)
+
+//U3D_B2_PHYD_RXDET2
+#define A60810_RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
+#define A60810_RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
+#define A60810_RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
+#define A60810_RG_SSUSB_LCK2REF_EXT_EN_OFST (28)
+#define A60810_RG_SSUSB_G2_LCK2REF_EXT_SEL_OFST (24)
+#define A60810_RG_SSUSB_LCK2REF_EXT_SEL_OFST (20)
+#define A60810_RG_SSUSB_PDN_T_SEL_OFST (18)
+#define A60810_RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
+#define A60810_RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
+
+//U3D_B2_PHYD_MISC0
+#define A60810_RG_SSUSB_TX_EIDLE_LP_P0DLYCYC_OFST (26)
+#define A60810_RG_SSUSB_TX_SER_EN_OFST (25)
+#define A60810_RG_SSUSB_FORCE_TX_SER_EN_OFST (24)
+#define A60810_RG_SSUSB_TXPLL_REFCKSEL_OFST (23)
+#define A60810_RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
+#define A60810_RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
+#define A60810_RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
+#define A60810_RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
+#define A60810_RG_SSUSB_LFPS_PSEL_OFST (15)
+#define A60810_RG_SSUSB_RX_SIGDET_EN_OFST (14)
+#define A60810_RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
+#define A60810_RG_SSUSB_RX_PI_CAL_EN_OFST (12)
+#define A60810_RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
+#define A60810_RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
+#define A60810_RG_SSUSB_T2RLB_PSEL_OFST (8)
+#define A60810_RG_SSUSB_PPCTL_PSEL_OFST (5)
+#define A60810_RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
+#define A60810_RG_SSUSB_BERTLB_PSEL_OFST (2)
+#define A60810_RG_SSUSB_RETRACK_DIS_OFST (1)
+#define A60810_RG_SSUSB_PPERRCNT_CLR_OFST (0)
+
+//U3D_B2_PHYD_MISC2
+#define A60810_RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
+#define A60810_RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
+#define A60810_RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
+#define A60810_RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
+#define A60810_RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
+#define A60810_RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
+#define A60810_RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
+#define A60810_RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
+#define A60810_RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
+#define A60810_RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
+#define A60810_RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
+
+//U3D_B2_PHYD_MISC3
+#define A60810_RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
+#define A60810_RGS_SSUSB_PPERRCNT_OFST (0)
+
+//U3D_B2_PHYD_L1SS
+#define A60810_RG_SSUSB_L1SS_REV1_OFST (24)
+#define A60810_RG_SSUSB_L1SS_REV0_OFST (16)
+#define A60810_RG_SSUSB_P_LTD1_SLOCK_DIS_OFST (11)
+#define A60810_RG_SSUSB_PLL_CNT_CLEAN_DIS_OFST (10)
+#define A60810_RG_SSUSB_P_PLL_REK_SEL_OFST (9)
+#define A60810_RG_SSUSB_TXDRV_MASKDLY_OFST (8)
+#define A60810_RG_SSUSB_RXSTS_VAL_OFST (7)
+#define A60810_RG_PCIE_PHY_CLKREQ_N_EN_OFST (6)
+#define A60810_RG_PCIE_FORCE_PHY_CLKREQ_N_EN_OFST (5)
+#define A60810_RG_PCIE_PHY_CLKREQ_N_OUT_OFST (4)
+#define A60810_RG_PCIE_FORCE_PHY_CLKREQ_N_OUT_OFST (3)
+#define A60810_RG_SSUSB_RXPLL_STB_PX0_OFST (2)
+#define A60810_RG_PCIE_L1SS_EN_OFST (1)
+#define A60810_RG_PCIE_FORCE_L1SS_EN_OFST (0)
+
+//U3D_B2_ROSC_0
+#define A60810_RG_SSUSB_RING_OSC_CNTEND_OFST (23)
+#define A60810_RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
+#define A60810_RG_SSUSB_RING_OSC_EN_OFST (3)
+#define A60810_RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
+#define A60810_RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
+#define A60810_RG_SSUSB_RING_BYPASS_DET_OFST (0)
+
+//U3D_B2_ROSC_1
+#define A60810_RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
+#define A60810_RG_SSUSB_RING_OSC_P3_OFST (19)
+#define A60810_RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
+#define A60810_RG_SSUSB_RING_OSC_RECAL_OFST (16)
+#define A60810_RG_SSUSB_RING_OSC_SEL_OFST (8)
+#define A60810_RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
+
+//U3D_B2_ROSC_2
+#define A60810_RG_SSUSB_RING_DET_STRCYC2_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_STRCYC1_OFST (0)
+
+//U3D_B2_ROSC_3
+#define A60810_RG_SSUSB_RING_DET_DETWIN1_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_STRCYC3_OFST (0)
+
+//U3D_B2_ROSC_4
+#define A60810_RG_SSUSB_RING_DET_DETWIN3_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_DETWIN2_OFST (0)
+
+//U3D_B2_ROSC_5
+#define A60810_RG_SSUSB_RING_DET_LBOND1_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_UBOND1_OFST (0)
+
+//U3D_B2_ROSC_6
+#define A60810_RG_SSUSB_RING_DET_LBOND2_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_UBOND2_OFST (0)
+
+//U3D_B2_ROSC_7
+#define A60810_RG_SSUSB_RING_DET_LBOND3_OFST (16)
+#define A60810_RG_SSUSB_RING_DET_UBOND3_OFST (0)
+
+//U3D_B2_ROSC_8
+#define A60810_RG_SSUSB_RING_RESERVE_OFST (16)
+#define A60810_RG_SSUSB_ROSC_PROB_SEL_OFST (2)
+#define A60810_RG_SSUSB_RING_FREQMETER_EN_OFST (1)
+#define A60810_RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
+
+//U3D_B2_ROSC_9
+#define A60810_RGS_FM_RING_CNT_OFST (16)
+#define A60810_RGS_SSUSB_RING_OSC_STATE_OFST (10)
+#define A60810_RGS_SSUSB_RING_OSC_STABLE_OFST (9)
+#define A60810_RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
+#define A60810_RGS_SSUSB_RING_OSC_CAL_OFST (0)
+
+//U3D_B2_ROSC_A
+#define A60810_RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
+
+//U3D_PHYD_VERSION
+#define A60810_RGS_SSUSB_PHYD_VERSION_OFST (0)
+
+//U3D_PHYD_MODEL
+#define A60810_RGS_SSUSB_PHYD_MODEL_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct sifslv_chip_reg_a {
+ //0x0
+ PHY_LE32 gpio_ctla;
+ PHY_LE32 gpio_ctlb;
+ PHY_LE32 gpio_ctlc;
+};
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct sifslv_fm_reg_a {
+ //0x0
+ PHY_LE32 fmcr0;
+ PHY_LE32 fmcr1;
+ PHY_LE32 fmcr2;
+ PHY_LE32 fmmonr0;
+ //0X10
+ PHY_LE32 fmmonr1;
+};
+
+//U3D_FMCR0
+#define A60810_RG_LOCKTH (0xf<<28) //31:28
+#define A60810_RG_MONCLK_SEL (0x3<<26) //27:26
+#define A60810_RG_FM_MODE (0x1<<25) //25:25
+#define A60810_RG_FREQDET_EN (0x1<<24) //24:24
+#define A60810_RG_CYCLECNT (0xffffff<<0) //23:0
+
+//U3D_FMCR1
+#define A60810_RG_TARGET (0xffffffff<<0) //31:0
+
+//U3D_FMCR2
+#define A60810_RG_OFFSET (0xffffffff<<0) //31:0
+
+//U3D_FMMONR0
+#define A60810_USB_FM_OUT (0xffffffff<<0) //31:0
+
+//U3D_FMMONR1
+#define A60810_RG_MONCLK_SEL_2 (0x1<<9) //9:9
+#define A60810_RG_FRCK_EN (0x1<<8) //8:8
+#define A60810_USBPLL_LOCK (0x1<<1) //1:1
+#define A60810_USB_FM_VLD (0x1<<0) //0:0
+
+/* OFFSET */
+
+//U3D_FMCR0
+#define A60810_RG_LOCKTH_OFST (28)
+#define A60810_RG_MONCLK_SEL_OFST (26)
+#define A60810_RG_FM_MODE_OFST (25)
+#define A60810_RG_FREQDET_EN_OFST (24)
+#define A60810_RG_CYCLECNT_OFST (0)
+
+//U3D_FMCR1
+#define A60810_RG_TARGET_OFST (0)
+
+//U3D_FMCR2
+#define A60810_RG_OFFSET_OFST (0)
+
+//U3D_FMMONR0
+#define A60810_USB_FM_OUT_OFST (0)
+
+//U3D_FMMONR1
+#define A60810_RG_MONCLK_SEL_2_OFST (9)
+#define A60810_RG_FRCK_EN_OFST (8)
+#define A60810_USBPLL_LOCK_OFST (1)
+#define A60810_USB_FM_VLD_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+struct spllc_reg_a {
+ //0x0
+ PHY_LE32 u3d_syspll_0;
+ PHY_LE32 u3d_syspll_1;
+ PHY_LE32 u3d_syspll_2;
+ PHY_LE32 u3d_syspll_sdm;
+ //0x10
+ PHY_LE32 u3d_xtalctl_1;
+ PHY_LE32 u3d_xtalctl_2;
+ PHY_LE32 u3d_xtalctl3;
+};
+
+//U3D_SYSPLL_0
+#define A60810_RG_SSUSB_SPLL_DDSEN_CYC (0x1f<<27) //31:27
+#define A60810_RG_SSUSB_SPLL_NCPOEN_CYC (0x3<<25) //26:25
+#define A60810_RG_SSUSB_SPLL_STBCYC (0x1ff<<16) //24:16
+#define A60810_RG_SSUSB_SPLL_NCPOCHG_CYC (0xf<<12) //15:12
+#define A60810_RG_SSUSB_SYSPLL_ON (0x1<<11) //11:11
+#define A60810_RG_SSUSB_FORCE_SYSPLLON (0x1<<10) //10:10
+#define A60810_RG_SSUSB_SPLL_DDSRSTB_CYC (0x7<<0) //2:0
+
+//U3D_SYSPLL_1
+#define A60810_RG_SSUSB_PLL_BIAS_CYC (0xff<<24) //31:24
+#define A60810_RG_SSUSB_SYSPLL_STB (0x1<<23) //23:23
+#define A60810_RG_SSUSB_FORCE_SYSPLL_STB (0x1<<22) //22:22
+#define A60810_RG_SSUSB_SPLL_DDS_ISO_EN (0x1<<21) //21:21
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_ISO_EN (0x1<<20) //20:20
+#define A60810_RG_SSUSB_SPLL_DDS_PWR_ON (0x1<<19) //19:19
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_PWR_ON (0x1<<18) //18:18
+#define A60810_RG_SSUSB_PLL_BIAS_PWD (0x1<<17) //17:17
+#define A60810_RG_SSUSB_FORCE_PLL_BIAS_PWD (0x1<<16) //16:16
+#define A60810_RG_SSUSB_FORCE_SPLL_NCPO_EN (0x1<<15) //15:15
+#define A60810_RG_SSUSB_FORCE_SPLL_FIFO_START_MAN (0x1<<14) //14:14
+#define A60810_RG_SSUSB_FORCE_SPLL_NCPO_CHG (0x1<<12) //12:12
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_RSTB (0x1<<11) //11:11
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_PWDB (0x1<<10) //10:10
+#define A60810_RG_SSUSB_FORCE_SPLL_DDSEN (0x1<<9) //9:9
+#define A60810_RG_SSUSB_FORCE_SPLL_PWD (0x1<<8) //8:8
+#define A60810_RG_SSUSB_SPLL_NCPO_EN (0x1<<7) //7:7
+#define A60810_RG_SSUSB_SPLL_FIFO_START_MAN (0x1<<6) //6:6
+#define A60810_RG_SSUSB_SPLL_NCPO_CHG (0x1<<4) //4:4
+#define A60810_RG_SSUSB_SPLL_DDS_RSTB (0x1<<3) //3:3
+#define A60810_RG_SSUSB_SPLL_DDS_PWDB (0x1<<2) //2:2
+#define A60810_RG_SSUSB_SPLL_DDSEN (0x1<<1) //1:1
+#define A60810_RG_SSUSB_SPLL_PWD (0x1<<0) //0:0
+
+//U3D_SYSPLL_2
+#define A60810_RG_SSUSB_SPLL_P_ON_SEL (0x1<<11) //11:11
+#define A60810_RG_SSUSB_SPLL_FBDIV_CHG (0x1<<10) //10:10
+#define A60810_RG_SSUSB_SPLL_DDS_ISOEN_CYC (0x3ff<<0) //9:0
+
+//U3D_SYSPLL_SDM
+#define A60810_RG_SSUSB_SPLL_SDM_ISO_EN_CYC (0x3ff<<14) //23:14
+#define A60810_RG_SSUSB_SPLL_FORCE_SDM_ISO_EN (0x1<<13) //13:13
+#define A60810_RG_SSUSB_SPLL_SDM_ISO_EN (0x1<<12) //12:12
+#define A60810_RG_SSUSB_SPLL_SDM_PWR_ON_CYC (0x3ff<<2) //11:2
+#define A60810_RG_SSUSB_SPLL_FORCE_SDM_PWR_ON (0x1<<1) //1:1
+#define A60810_RG_SSUSB_SPLL_SDM_PWR_ON (0x1<<0) //0:0
+
+//U3D_XTALCTL_1
+#define A60810_RG_SSUSB_BIAS_STBCYC (0x3fff<<17) //30:17
+#define A60810_RG_SSUSB_XTAL_CLK_REQ_N (0x1<<16) //16:16
+#define A60810_RG_SSUSB_XTAL_FORCE_CLK_REQ_N (0x1<<15) //15:15
+#define A60810_RG_SSUSB_XTAL_STBCYC (0x7fff<<0) //14:0
+
+//U3D_XTALCTL_2
+#define A60810_RG_SSUSB_INT_XTAL_SEL (0x1<<29) //29:29
+#define A60810_RG_SSUSB_BG_LPF_DLY (0x3<<27) //28:27
+#define A60810_RG_SSUSB_BG_LPF_EN (0x1<<26) //26:26
+#define A60810_RG_SSUSB_FORCE_BG_LPF_EN (0x1<<25) //25:25
+#define A60810_RG_SSUSB_P3_BIAS_PWD (0x1<<24) //24:24
+#define A60810_RG_SSUSB_PCIE_CLKDET_HIT (0x1<<20) //20:20
+#define A60810_RG_SSUSB_PCIE_CLKDET_EN (0x1<<19) //19:19
+#define A60810_RG_SSUSB_FRC_PCIE_CLKDET_EN (0x1<<18) //18:18
+#define A60810_RG_SSUSB_USB20_BIAS_EN (0x1<<17) //17:17
+#define A60810_RG_SSUSB_USB20_SLEEP (0x1<<16) //16:16
+#define A60810_RG_SSUSB_OSC_ONLY (0x1<<9) //9:9
+#define A60810_RG_SSUSB_OSC_EN (0x1<<8) //8:8
+#define A60810_RG_SSUSB_XTALBIAS_STB (0x1<<5) //5:5
+#define A60810_RG_SSUSB_FORCE_XTALBIAS_STB (0x1<<4) //4:4
+#define A60810_RG_SSUSB_BIAS_PWD (0x1<<3) //3:3
+#define A60810_RG_SSUSB_XTAL_PWD (0x1<<2) //2:2
+#define A60810_RG_SSUSB_FORCE_BIAS_PWD (0x1<<1) //1:1
+#define A60810_RG_SSUSB_FORCE_XTAL_PWD (0x1<<0) //0:0
+
+//U3D_XTALCTL3
+#define A60810_RG_SSUSB_XTALCTL_REV (0xf<<12) //15:12
+#define A60810_RG_SSUSB_BIASIMR_EN (0x1<<11) //11:11
+#define A60810_RG_SSUSB_FORCE_BIASIMR_EN (0x1<<10) //10:10
+#define A60810_RG_SSUSB_XTAL_RX_PWD (0x1<<9) //9:9
+#define A60810_RG_SSUSB_FRC_XTAL_RX_PWD (0x1<<8) //8:8
+#define A60810_RG_SSUSB_CKBG_PROB_SEL (0x3<<6) //7:6
+#define A60810_RG_SSUSB_XTAL_PROB_SEL (0x3<<4) //5:4
+#define A60810_RG_SSUSB_XTAL_VREGBIAS_LPF_ENB (0x1<<3) //3:3
+#define A60810_RG_SSUSB_XTAL_FRC_VREGBIAS_LPF_ENB (0x1<<2) //2:2
+#define A60810_RG_SSUSB_XTAL_VREGBIAS_PWD (0x1<<1) //1:1
+#define A60810_RG_SSUSB_XTAL_FRC_VREGBIAS_PWD (0x1<<0) //0:0
+
+
+/* SSUSB_SIFSLV_SPLLC FIELD OFFSET DEFINITION */
+
+//U3D_SYSPLL_0
+#define A60810_RG_SSUSB_SPLL_DDSEN_CYC_OFST (27)
+#define A60810_RG_SSUSB_SPLL_NCPOEN_CYC_OFST (25)
+#define A60810_RG_SSUSB_SPLL_STBCYC_OFST (16)
+#define A60810_RG_SSUSB_SPLL_NCPOCHG_CYC_OFST (12)
+#define A60810_RG_SSUSB_SYSPLL_ON_OFST (11)
+#define A60810_RG_SSUSB_FORCE_SYSPLLON_OFST (10)
+#define A60810_RG_SSUSB_SPLL_DDSRSTB_CYC_OFST (0)
+
+//U3D_SYA60810_SPLL_1
+#define A60810_RG_SSUSB_PLL_BIAS_CYC_OFST (24)
+#define A60810_RG_SSUSB_SYSPLL_STB_OFST (23)
+#define A60810_RG_SSUSB_FORCE_SYSPLL_STB_OFST (22)
+#define A60810_RG_SSUSB_SPLL_DDS_ISO_EN_OFST (21)
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_ISO_EN_OFST (20)
+#define A60810_RG_SSUSB_SPLL_DDS_PWR_ON_OFST (19)
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_PWR_ON_OFST (18)
+#define A60810_RG_SSUSB_PLL_BIAS_PWD_OFST (17)
+#define A60810_RG_SSUSB_FORCE_PLL_BIAS_PWD_OFST (16)
+#define A60810_RG_SSUSB_FORCE_SPLL_NCPO_EN_OFST (15)
+#define A60810_RG_SSUSB_FORCE_SPLL_FIFO_START_MAN_OFST (14)
+#define A60810_RG_SSUSB_FORCE_SPLL_NCPO_CHG_OFST (12)
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_RSTB_OFST (11)
+#define A60810_RG_SSUSB_FORCE_SPLL_DDS_PWDB_OFST (10)
+#define A60810_RG_SSUSB_FORCE_SPLL_DDSEN_OFST (9)
+#define A60810_RG_SSUSB_FORCE_SPLL_PWD_OFST (8)
+#define A60810_RG_SSUSB_SPLL_NCPO_EN_OFST (7)
+#define A60810_RG_SSUSB_SPLL_FIFO_START_MAN_OFST (6)
+#define A60810_RG_SSUSB_SPLL_NCPO_CHG_OFST (4)
+#define A60810_RG_SSUSB_SPLL_DDS_RSTB_OFST (3)
+#define A60810_RG_SSUSB_SPLL_DDS_PWDB_OFST (2)
+#define A60810_RG_SSUSB_SPLL_DDSEN_OFST (1)
+#define A60810_RG_SSUSB_SPLL_PWD_OFST (0)
+
+//U3D_SYSPLL_2
+#define A60810_RG_SSUSB_SPLL_P_ON_SEL_OFST (11)
+#define A60810_RG_SSUSB_SPLL_FBDIV_CHG_OFST (10)
+#define A60810_RG_SSUSB_SPLL_DDS_ISOEN_CYC_OFST (0)
+
+//U3D_SYSPLL_SDM
+#define A60810_RG_SSUSB_SPLL_SDM_ISO_EN_CYC_OFST (14)
+#define A60810_RG_SSUSB_SPLL_FORCE_SDM_ISO_EN_OFST (13)
+#define A60810_RG_SSUSB_SPLL_SDM_ISO_EN_OFST (12)
+#define A60810_RG_SSUSB_SPLL_SDM_PWR_ON_CYC_OFST (2)
+#define A60810_RG_SSUSB_SPLL_FORCE_SDM_PWR_ON_OFST (1)
+#define A60810_RG_SSUSB_SPLL_SDM_PWR_ON_OFST (0)
+
+//U3D_XTALCTL_1
+#define A60810_RG_SSUSB_BIAS_STBCYC_OFST (17)
+#define A60810_RG_SSUSB_XTAL_CLK_REQ_N_OFST (16)
+#define A60810_RG_SSUSB_XTAL_FORCE_CLK_REQ_N_OFST (15)
+#define A60810_RG_SSUSB_XTAL_STBCYC_OFST (0)
+
+//U3D_XTALCTL_2
+#define A60810_RG_SSUSB_INT_XTAL_SEL_OFST (29)
+#define A60810_RG_SSUSB_BG_LPF_DLY_OFST (27)
+#define A60810_RG_SSUSB_BG_LPF_EN_OFST (26)
+#define A60810_RG_SSUSB_FORCE_BG_LPF_EN_OFST (25)
+#define A60810_RG_SSUSB_P3_BIAS_PWD_OFST (24)
+#define A60810_RG_SSUSB_PCIE_CLKDET_HIT_OFST (20)
+#define A60810_RG_SSUSB_PCIE_CLKDET_EN_OFST (19)
+#define A60810_RG_SSUSB_FRC_PCIE_CLKDET_EN_OFST (18)
+#define A60810_RG_SSUSB_USB20_BIAS_EN_OFST (17)
+#define A60810_RG_SSUSB_USB20_SLEEP_OFST (16)
+#define A60810_RG_SSUSB_OSC_ONLY_OFST (9)
+#define A60810_RG_SSUSB_OSC_EN_OFST (8)
+#define A60810_RG_SSUSB_XTALBIAS_STB_OFST (5)
+#define A60810_RG_SSUSB_FORCE_XTALBIAS_STB_OFST (4)
+#define A60810_RG_SSUSB_BIAS_PWD_OFST (3)
+#define A60810_RG_SSUSB_XTAL_PWD_OFST (2)
+#define A60810_RG_SSUSB_FORCE_BIAS_PWD_OFST (1)
+#define A60810_RG_SSUSB_FORCE_XTAL_PWD_OFST (0)
+
+//U3D_XTALCTL3
+#define A60810_RG_SSUSB_XTALCTL_REV_OFST (12)
+#define A60810_RG_SSUSB_BIASIMR_EN_OFST (11)
+#define A60810_RG_SSUSB_FORCE_BIASIMR_EN_OFST (10)
+#define A60810_RG_SSUSB_XTAL_RX_PWD_OFST (9)
+#define A60810_RG_SSUSB_FRC_XTAL_RX_PWD_OFST (8)
+#define A60810_RG_SSUSB_CKBG_PROB_SEL_OFST (6)
+#define A60810_RG_SSUSB_XTAL_PROB_SEL_OFST (4)
+#define A60810_RG_SSUSB_XTAL_VREGBIAS_LPF_ENB_OFST (3)
+#define A60810_RG_SSUSB_XTAL_FRC_VREGBIAS_LPF_ENB_OFST (2)
+#define A60810_RG_SSUSB_XTAL_VREGBIAS_PWD_OFST (1)
+#define A60810_RG_SSUSB_XTAL_FRC_VREGBIAS_PWD_OFST (0)
+
+///////////////////////////////////////////////////////////////////////////////
+
+#endif
+//#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/rules.mk b/src/bsp/lk/platform/mt2731/drivers/musb/rules.mk
new file mode 100644
index 0000000..8e0c0fe
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/rules.mk
@@ -0,0 +1,12 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+MODULE := $(LOCAL_DIR)
+
+USB_PHY ?= realchip
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/mt_usb.c \
+ $(LOCAL_DIR)/mt_usb_qmu.c \
+ $(LOCAL_DIR)/usb_i2c.c \
+ $(LOCAL_DIR)/phy-a60810.c \
+
+include make/module.mk
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.c b/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.c
new file mode 100644
index 0000000..84d6022
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.c
@@ -0,0 +1,819 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * usb_i2c_v1.c
+ *
+ * Project:
+ * --------
+ * BOOTROM
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ ****************************************************************************/
+#include "usb_i2c.h"
+#include "mt_usb.h"
+#include <stdlib.h>
+#include <debug.h>
+#include <errno.h>
+
+/*-----------------------------------------------------------------------
+ * Set I2C Speend interface: Set internal I2C speed,
+ * Goal is that get sample_cnt_div and step_cnt_div
+ * clock: Depends on the current MCU/AHB/APB clock frequency
+ * mode: ST_MODE. (fixed setting for stable I2C transaction)
+ * khz: MAX_ST_MODE_SPEED. (fixed setting for stable I2C transaction)
+ *
+ * Returns: ERROR_CODE
+ *-----------------------------------------------------------------------*/
+U32 usb_i2c_v1_set_speed (unsigned long clock, I2C_SPD_MODE mode, unsigned long khz)
+{
+ U32 ret_code = B_OK;
+ unsigned short sample_cnt_div, step_cnt_div;
+ unsigned short max_step_cnt_div = (mode == HS_MODE) ? MAX_HS_STEP_CNT_DIV : MAX_STEP_CNT_DIV;
+ unsigned long tmp, sclk;
+
+ {
+ unsigned long diff, min_diff = I2C_CLK_RATE;
+ unsigned short sample_div = MAX_SAMPLE_CNT_DIV;
+ unsigned short step_div = max_step_cnt_div;
+ for (sample_cnt_div = 1; sample_cnt_div <= MAX_SAMPLE_CNT_DIV; sample_cnt_div++) {
+
+ for (step_cnt_div = 2; step_cnt_div <= max_step_cnt_div; step_cnt_div++) {
+ sclk = (clock >> 1) / (sample_cnt_div * step_cnt_div);
+ if (sclk > khz)
+ continue;
+ diff = khz - sclk;
+
+ if (diff < min_diff) {
+ min_diff = diff;
+ sample_div = sample_cnt_div;
+ step_div = step_cnt_div;
+ }
+ }
+ }
+ sample_cnt_div = sample_div;
+ step_cnt_div = step_div;
+ }
+
+ sclk = clock / (2 * sample_cnt_div * step_cnt_div);
+ if (sclk > khz) {
+ ret_code = E_I2C_SET_SPEED_FAIL_OVER_SPEED;
+ return ret_code;
+ }
+
+ step_cnt_div--;
+ sample_cnt_div--;
+
+ if (mode == HS_MODE) {
+ tmp = __raw_readw(MT_I2C_HS) & ((0x7 << 12) | (0x7 << 8));
+ tmp = (sample_cnt_div & 0x7) << 12 | (step_cnt_div & 0x7) << 8 | tmp;
+ __raw_writew(tmp, MT_I2C_HS);
+ USB_I2C_SET_HS_MODE(1);
+ }
+ else {
+ tmp = __raw_readw(MT_I2C_TIMING) & ~((0x7 << 8) | (0x1f << 0));
+ tmp = (sample_cnt_div & 0x7) << 8 | (step_cnt_div & 0x1f) << 0 | tmp;
+ __raw_writew(tmp, MT_I2C_TIMING);
+ USB_I2C_SET_HS_MODE(0);
+ }
+
+ return ret_code;
+}
+
+/*-----------------------------------------------------------------------
+* Initializa the HW I2C module
+* Returns: ERROR_CODE
+ *-----------------------------------------------------------------------*/
+U32 usb_i2c_v1_init (void)
+{
+ U32 ret_code = B_OK;
+
+ /* Power On I2C Duel */
+ //PDN_Power_CONA_DOWN(PDN_PERI_I2C, KAL_FALSE); // wait PLL API release
+
+ /* Reset the HW I2C module */
+ I2C_SOFTRESET;
+
+ /* Set I2C control register */
+ USB_I2C_SET_TRANS_CTRL(ACK_ERR_DET_EN | CLK_EXT);
+
+ /* Sset I2C speed mode */
+ ret_code = usb_i2c_v1_set_speed(I2C_CLK_RATE, ST_MODE, MAX_ST_MODE_SPEED);
+ if( ret_code != B_OK)
+ {
+ return ret_code;
+ }
+
+ /* Clear Interrupt status */
+ USB_I2C_CLR_INTR_STATUS(I2C_TRANSAC_COMP | I2C_ACKERR | I2C_HS_NACKERR);
+ __raw_writel(0, MT_I2C_TRAFFIC);
+ __raw_writel(0, MT_I2C_SHAPE);
+ __raw_writel(0x404, MT_I2C_CLOCK_DIV);
+ __raw_writel(0x10, MT_I2C_DELAY_LEN);
+ __raw_writel(0x280d, MT_I2C_LTIMING);
+
+ /* Double Reset the I2C START bit*/
+ __raw_writel(0, MT_I2C_START);
+
+ return ret_code;
+}
+
+/*-----------------------------------------------------------------------
+* De-Initializa the HW I2C module
+* Returns: ERROR_CODE
+ *-----------------------------------------------------------------------*/
+U32 usb_i2c_v1_deinit (void)
+{
+ U32 ret_code = B_OK;
+
+ /* Reset the HW I2C module */
+ I2C_SOFTRESET;
+
+ return ret_code;
+}
+
+/*-----------------------------------------------------------------------
+ * Read interface: Read bytes
+ * chip: I2C chip address, range 0..127
+ * e.g. Smart Battery chip number is 0xAA
+ * buffer: Where to read/write the data (device address is regarded as data)
+ * len: How many bytes to read/write
+ *
+ * Returns: ERROR_CODE
+ *-----------------------------------------------------------------------*/
+U32 usb_i2c_v1_read(U8 chip, U8 *buffer, int len)
+{
+ U32 ret_code = B_OK;
+ U8 *ptr = buffer;
+ unsigned short status;
+ int ret = len;
+
+ /* CHECKME. mt65xx doesn't support len = 0. */
+ if (!len) {
+ return E_I2C_READ_FAIL_ZERO_LENGTH;
+ }
+
+ /* for read, bit 0 is to indicate read REQ or write REQ */
+ chip = (chip | 0x1);
+
+ /* control registers */
+ USB_I2C_SET_SLAVE_ADDR(chip);
+ USB_I2C_SET_TRANS_LEN(len);
+ USB_I2C_SET_TRANSAC_LEN(1);
+ USB_I2C_SET_INTR_MASK(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP);
+ I2C_FIFO_CLR_ADDR;
+
+ USB_I2C_SET_TRANS_CTRL(ACK_ERR_DET_EN | CLK_EXT | STOP_FLAG);
+
+ /* start trnasfer transaction */
+ I2C_START_TRANSAC;
+
+ /* polling mode : see if transaction complete */
+ while (1)
+ {
+ status = I2C_INTR_STATUS;
+
+ if ( status & I2C_TRANSAC_COMP && (!I2C_FIFO_IS_EMPTY) )
+ {
+ ret = 0;
+ ret_code = B_OK; // 0
+ break;
+ }
+ else if ( status & I2C_HS_NACKERR)
+ {
+ ret = 1;
+ ret_code = E_I2C_READ_FAIL_HS_NACKERR;
+ break;
+ }
+ else if ( status & I2C_ACKERR)
+ {
+ ret = 2;
+ ret_code = E_I2C_READ_FAIL_ACKERR;
+ break;
+ }
+ }
+
+ USB_I2C_CLR_INTR_STATUS(I2C_TRANSAC_COMP | I2C_ACKERR | I2C_HS_NACKERR);
+
+ if (!ret)
+ {
+ while (len--)
+ {
+ USB_I2C_READ_BYTE(*ptr);
+ ptr++;
+ }
+ }
+
+ /* clear bit mask */
+ USB_I2C_CLR_INTR_MASK(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP);
+
+ return ret_code;
+}
+
+/*-----------------------------------------------------------------------
+ * Read interface: Write bytes
+ * chip: I2C chip address, range 0..127
+ * e.g. Smart Battery chip number is 0xAA
+ * buffer: Where to read/write the data (device address is regarded as data)
+ * len: How many bytes to read/write
+ *
+ * Returns: ERROR_CODE
+ *-----------------------------------------------------------------------*/
+U32 usb_i2c_v1_write (U8 chip, U8 *buffer, int len)
+{
+ U32 ret_code = B_OK;
+ U8 *ptr = buffer;
+
+ unsigned short status;
+
+ /* CHECKME. mt65xx doesn't support len = 0. */
+ if (!len)
+ { return E_I2C_WRITE_FAIL_ZERO_LENGTH;
+ }
+
+ /* bit 0 is to indicate read REQ or write REQ */
+ chip = (chip & ~0x1);
+
+ /* control registers */
+ USB_I2C_SET_SLAVE_ADDR(chip);
+ USB_I2C_SET_TRANS_LEN(len);
+ USB_I2C_SET_TRANSAC_LEN(1);
+ USB_I2C_SET_INTR_MASK(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP);
+ I2C_FIFO_CLR_ADDR;
+
+ USB_I2C_SET_TRANS_CTRL(ACK_ERR_DET_EN | CLK_EXT | STOP_FLAG);
+
+ /* start to write data */
+ while (len--) {
+ USB_I2C_WRITE_BYTE(*ptr);
+ ptr++;
+ }
+
+ /* start trnasfer transaction */
+ I2C_START_TRANSAC;
+
+ /* set timer to calculate time avoid timeout without any reaction */
+
+ /* polling mode : see if transaction complete */
+ while (1) {
+ status = I2C_INTR_STATUS;
+
+ if ( status & I2C_TRANSAC_COMP) {
+ ret_code = B_OK;
+ break;
+ }
+ else if ( status & I2C_HS_NACKERR) {
+ ret_code = E_I2C_WRITE_FAIL_HS_NACKERR;
+ break;
+ }
+ else if ( status & I2C_ACKERR) {
+ ret_code = E_I2C_WRITE_FAIL_ACKERR;
+ break;
+ }
+ }
+
+ USB_I2C_CLR_INTR_STATUS(I2C_TRANSAC_COMP | I2C_ACKERR | I2C_HS_NACKERR);
+
+ /* clear bit mask */
+ USB_I2C_CLR_INTR_MASK(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP);
+
+ return ret_code;
+}
+
+U32 usb_i2c_read8_v1 (U8 *cmdBuffer, U8 *dataBuffer)
+{
+ U32 ret_code = B_OK;
+
+ ret_code = USB_I2C_WRITE(0xc0, cmdBuffer, 1); // set register command
+
+ if (ret_code != B_OK)
+ return ret_code;
+
+ ret_code = USB_I2C_READ(0xc0, dataBuffer, 1);
+
+ return ret_code;
+}
+
+U32 usb_i2c_write8_v1 (U8 *cmdBuffer, U8 *dataBuffer)
+{
+ U32 ret_code = B_OK;
+ U8 write_data[2];
+
+ write_data[0]= cmdBuffer[0];
+ write_data[1] = dataBuffer[0];
+
+ ret_code = USB_I2C_WRITE(0xc0, write_data, 2);
+
+ return ret_code;
+}
+
+#define REG_I2C_START_BIT 0x1
+#define I2C_READ_BIT 0x1
+
+#define PHY_I2C_BASE USB_I2C_BASE
+#define REG_I2C_DATA_PORT (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x00)))
+#define REG_I2C_SLAVE_ADDR (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x04)))
+#define REG_I2C_TRANSFER_LEN (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x14)))
+#define REG_I2C_TRANSAC_LEN (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x18)))
+#define REG_I2C_START (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x24)))
+#define REG_I2C_SOFT_RESET (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x50)))
+#define REG_I2C_CONTROL (*((volatile unsigned short int *) (PHY_I2C_BASE + 0x10)))
+
+#if !defined(__USE_USB_I2C__)
+U32 I2cWriteReg(U8 dev_id, U8 addr, U8 val)
+{
+ printf("I2C Write@%x [%x]=%x\n", dev_id, addr, val);
+
+ REG_I2C_SLAVE_ADDR = dev_id<<1;
+ REG_I2C_TRANSFER_LEN = 2;
+ REG_I2C_TRANSAC_LEN = 1;
+
+ REG_I2C_DATA_PORT = addr;
+ REG_I2C_DATA_PORT = val;
+
+ REG_I2C_START = REG_I2C_START_BIT;
+
+ while((REG_I2C_START & REG_I2C_START_BIT))
+ ;
+ return 1;
+}
+
+U32 I2cReadReg(U8 dev_id, U8 addr, U8 *data)
+{
+ printf("I2C Read@%x [%x]\n", dev_id, addr);
+
+ REG_I2C_SLAVE_ADDR = dev_id<<1;
+ REG_I2C_TRANSFER_LEN = 0x01;
+ REG_I2C_TRANSAC_LEN = 0x01;
+ REG_I2C_DATA_PORT = addr;
+ REG_I2C_START = REG_I2C_START_BIT;
+
+ while((REG_I2C_START & REG_I2C_START_BIT))
+ ;
+
+ REG_I2C_SLAVE_ADDR = (dev_id<<1) | I2C_READ_BIT;
+ REG_I2C_TRANSFER_LEN = 0x01;
+ REG_I2C_TRANSAC_LEN = 0x01;
+ REG_I2C_START = REG_I2C_START_BIT;
+
+ while((REG_I2C_START & REG_I2C_START_BIT))
+ ;
+
+ *data = REG_I2C_DATA_PORT;
+
+ printf("I2C Read [%x]=%x\n", addr, *data);
+
+ return 1;//!!(PHY_INT32)*data;
+}
+
+#else
+
+/* TEST CHIP PHY define, edit this in different platform */
+#define U3_PHY_I2C_DEV 0x60
+#define U3_PHY_PAGE 0xff
+//0x10005000
+//fffffffff1280700
+#define GPIO_BASE 0x11280700//0x80080000
+#define SSUSB_I2C_OUT GPIO_BASE+0xd0
+#define SSUSB_I2C_IN GPIO_BASE+0xd4
+
+/////////////////////////////////////////////////////////////////
+
+#define OUTPUT 1
+#define INPUT 0
+
+#define SDA 0 /// GPIO #0: I2C data pin
+#define SCL 1 /// GPIO #1: I2C clock pin
+
+/////////////////////////////////////////////////////////////////
+
+#define SDA_OUT (1<<0)
+#define SDA_OEN (1<<1)
+#define SCL_OUT (1<<2)
+#define SCL_OEN (1<<3)
+
+#define SDA_IN_OFFSET 0
+#define SCL_IN_OFFSET 1
+
+//#define GPIO_PULLEN1_SET (GPIO_BASE+0x0030+0x04)
+//#define GPIO_DIR1_SET (GPIO_BASE+0x0000+0x04)
+//#define GPIO_PULLEN1_CLR (GPIO_BASE+0x0030+0x08)
+//#define GPIO_DIR1_CLR (GPIO_BASE+0x0000+0x08)
+//#define GPIO_DOUT1_SET (GPIO_BASE+0x00C0+0x04)
+//#define GPIO_DOUT1_CLR (GPIO_BASE+0x00C0+0x08)
+//#define GPIO_DIN1 (GPIO_BASE+0x00F0)
+
+void gpio_dir_set(U32 pin){
+ U32 addr, temp;
+ addr = SSUSB_I2C_OUT;
+ temp = DRV_Reg32(addr);
+ if(pin == SDA){
+ temp |= SDA_OEN;
+ DRV_WriteReg32(addr,temp);
+ }
+ else{
+ temp |= SCL_OEN;
+ DRV_WriteReg32(addr,temp);
+ }
+}
+
+void gpio_dir_clr(U32 pin){
+ U32 addr, temp;
+ addr = SSUSB_I2C_OUT;
+ temp = DRV_Reg32(addr);
+ if(pin == SDA){
+ temp &= ~SDA_OEN;
+ DRV_WriteReg32(addr,temp);
+ }
+ else{
+ temp &= ~SCL_OEN;
+ DRV_WriteReg32(addr,temp);
+ }
+}
+
+void gpio_dout_set(U32 pin){
+ U32 addr, temp;
+ addr = SSUSB_I2C_OUT;
+ temp = DRV_Reg32(addr);
+ if(pin == SDA){
+ temp |= SDA_OUT;
+ DRV_WriteReg32(addr,temp);
+ }
+ else{
+ temp |= SCL_OUT;
+ DRV_WriteReg32(addr,temp);
+ }
+}
+
+void gpio_dout_clr(U32 pin){
+ U32 addr, temp;
+ addr = SSUSB_I2C_OUT;
+ temp = DRV_Reg32(addr);
+ if(pin == SDA){
+ temp &= ~SDA_OUT;
+ DRV_WriteReg32(addr,temp);
+ }
+ else{
+ temp &= ~SCL_OUT;
+ DRV_WriteReg32(addr,temp);
+ }
+}
+
+S32 gpio_din(U32 pin){
+ U32 addr, temp;
+ addr = SSUSB_I2C_IN;
+ temp = DRV_Reg32(addr);
+ if(pin == SDA){
+ temp = (temp >> SDA_IN_OFFSET) & 1;
+ }
+ else{
+ temp = (temp >> SCL_IN_OFFSET) & 1;
+ }
+ return temp;
+}
+
+//#define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+#define GPIO_DIR_SET(pin) gpio_dir_set(pin)
+#define GPIO_DOUT_SET(pin) gpio_dout_set(pin);
+//#define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+#define GPIO_DIR_CLR(pin) gpio_dir_clr(pin)
+#define GPIO_DOUT_CLR(pin) gpio_dout_clr(pin)
+#define GPIO_DIN(pin) gpio_din(pin)
+
+
+//#define __I2_DUMMY_DELAY__
+#if defined(__I2_DUMMY_DELAY__)
+static U32 i2c_dummy_cnt;
+#define I2C_DUMMY_DELAY(_delay) for (i2c_dummy_cnt = ((_delay)) ; i2c_dummy_cnt!=0; i2c_dummy_cnt--)
+#else
+#define I2C_DUMMY_DELAY(_delay)
+#endif
+
+#define I2C_DELAY 10
+
+void GPIO_InitIO(U32 dir, U32 pin)
+{
+ if (dir == OUTPUT)
+ {
+// DRV_WriteReg16(GPIO_PULLEN_SET(no),(1 << remainder));
+ GPIO_DIR_SET(pin);
+ }
+ else
+ {
+// DRV_WriteReg16(GPIO_PULLEN_CLR(no),(1 << remainder));
+ GPIO_DIR_CLR(pin);
+ }
+ I2C_DUMMY_DELAY(100);
+}
+
+void GPIO_WriteIO(U32 data, U32 pin)
+{
+ if (data == 1){
+ GPIO_DOUT_SET(pin);
+ }
+ else{
+ GPIO_DOUT_CLR(pin);
+ }
+}
+
+U32 GPIO_ReadIO( U32 pin)
+{
+ U16 data;
+ data=GPIO_DIN(pin);
+ return (U32)data;
+}
+
+
+
+void SerialCommStop(void)
+{
+ GPIO_InitIO(OUTPUT,SDA);
+ GPIO_WriteIO(0,SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(0,SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1,SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1,SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_InitIO(INPUT,SCL);
+ GPIO_InitIO(INPUT,SDA);
+}
+
+void SerialCommStart(void) /* Prepare the SDA and SCL for sending/receiving */
+{
+ GPIO_InitIO(OUTPUT,SCL);
+ GPIO_InitIO(OUTPUT,SDA);
+ GPIO_WriteIO(1,SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1,SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(0,SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(0,SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+}
+
+U32 SerialCommTxByte(U8 data) /* return 0 --> ack */
+{
+ S32 i, ack;
+
+ GPIO_InitIO(OUTPUT,SDA);
+
+ for(i=8; --i>0;){
+ GPIO_WriteIO((data>>i)&0x01, SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO( 1, SCL); /* high */
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO( 0, SCL); /* low */
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ }
+ GPIO_WriteIO((data>>i)&0x01, SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO( 1, SCL); /* high */
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO( 0, SCL); /* low */
+ I2C_DUMMY_DELAY(I2C_DELAY);
+
+ GPIO_WriteIO(0, SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_InitIO(INPUT,SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ ack = GPIO_ReadIO(SDA); /// ack 1: error , 0:ok
+ GPIO_WriteIO(0, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+
+ if(ack==1)
+ return 0;
+ else
+ return 1;
+}
+
+void SerialCommRxByte(U8 *data, U8 ack)
+{
+ S32 i;
+ U32 dataCache;
+
+ dataCache = 0;
+ GPIO_InitIO(INPUT,SDA);
+ for(i=8; --i>=0;){
+ dataCache <<= 1;
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ dataCache |= GPIO_ReadIO(SDA);
+ GPIO_WriteIO(0, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ }
+ GPIO_InitIO(OUTPUT,SDA);
+ GPIO_WriteIO(ack, SDA);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(1, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ GPIO_WriteIO(0, SCL);
+ I2C_DUMMY_DELAY(I2C_DELAY);
+ *data = (unsigned char)dataCache;
+}
+
+
+/* U32 I2cWriteReg(U8 dev_id, U8 addr, U8 val) */
+U32 I2cWriteReg(U8 dev_id, U8 Addr, U8 Data)
+{
+ U32 acknowledge=0;
+
+ printf("I2C Write@%x [%x]=%x\n", dev_id, Addr, Data);
+
+ SerialCommStart();
+ acknowledge=SerialCommTxByte((dev_id<<1) & 0xff);
+ if(acknowledge)
+ acknowledge=SerialCommTxByte(Addr);
+ else
+ return 0;
+ acknowledge=SerialCommTxByte(Data);
+ if(acknowledge)
+ {
+ SerialCommStop();
+ return 0;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+/* U32 I2cReadReg(U8 dev_id, U8 addr, U8 *data) */
+U32 I2cReadReg(U8 dev_id, U8 Addr, U8 *Data)
+{
+ U32 acknowledge=0;
+ printf("I2C Read@%x [%x]\n", dev_id, Addr);
+ SerialCommStart();
+ acknowledge=SerialCommTxByte((dev_id<<1) & 0xff);
+ if(acknowledge)
+ acknowledge=SerialCommTxByte(Addr);
+ else
+ return 0;
+ SerialCommStart();
+ acknowledge=SerialCommTxByte(((dev_id<<1) & 0xff) | 0x01);
+ if(acknowledge)
+ SerialCommRxByte(Data, 1); // ack 0: ok , 1 error
+ else
+ return 0;
+ SerialCommStop();
+
+ printf("I2C Read [%x]=%x\n", Addr, *Data);
+ return acknowledge;
+}
+#endif
+
+
+#define U3_PHY_I2C_DEV 0x60
+#if 0 // pibben
+U32 usb_i2c_read8 (U8 cmdBuffer, U8 *dataBuffer)
+{
+ U32 ret_code = B_OK;
+/*
+ ret_code = USB_I2C_WRITE(U3_PHY_I2C_DEV, (U8)cmdBuffer, 1); // set register command
+
+ if (ret_code != B_OK)
+ return ret_code;
+*/
+ ret_code = USB_I2C_READ(U3_PHY_I2C_DEV, (U8)cmdBuffer, dataBuffer);
+
+ return ret_code;
+}
+
+U32 usb_i2c_write8 (U8 cmdBuffer, U8 dataBuffer)
+{
+ U32 ret_code = B_OK;
+
+ ret_code = USB_I2C_WRITE(U3_PHY_I2C_DEV, cmdBuffer, dataBuffer);
+
+ return ret_code;
+}
+#endif
+
+#define U3_PHY_PAGE 0xff
+
+U32 _U3Read_Reg(kal_uint32 address){
+ U8 cmdBuffer = address;
+ U8 dataBuffer = 0;
+ usb_i2c_read8_v1(&cmdBuffer, &dataBuffer);
+ return dataBuffer;
+}
+
+void _U3Write_Reg(kal_uint32 address, kal_uint32 value){
+ U8 cmdBuffer = address;
+ U8 dataBuffer = value;
+ usb_i2c_write8_v1(&cmdBuffer, &dataBuffer);
+}
+
+void _U3_Write_Bank(kal_uint32 bankValue){
+ U8 cmdBuffer = U3_PHY_PAGE;
+ U8 dataBuffer = bankValue;
+ usb_i2c_write8_v1(&cmdBuffer, &dataBuffer);
+}
+
+U32 U3PhyWriteReg8(kal_uint32 addr, kal_uint8 data)
+{
+ kal_uint32 bank;
+ kal_uint32 addr8;
+ bank = (addr >> 16) & 0xff;
+ addr8 = addr & 0xff;
+ _U3_Write_Bank(bank);
+ _U3Write_Reg(addr8, data);
+
+ return 0;
+}
+
+U32 U3PhyWriteReg32(kal_uint32 addr, kal_uint32 data){
+ kal_uint32 bank;
+ kal_uint32 addr8;
+ kal_uint32 data_0, data_1, data_2, data_3;
+
+ bank = (addr >> 16) & 0xff;
+ addr8 = addr & 0xff;
+ data_0 = data & 0xff;
+ data_1 = (data>>8) & 0xff;
+ data_2 = (data>>16) & 0xff;
+ data_3 = (data>>24) & 0xff;
+
+ _U3_Write_Bank(bank);
+ _U3Write_Reg(addr8, data_0);
+ _U3Write_Reg(addr8+1, data_1);
+ _U3Write_Reg(addr8+2, data_2);
+ _U3Write_Reg(addr8+3, data_3);
+
+ return 0;
+}
+
+U32 U3PhyReadReg32(kal_uint32 addr){
+ kal_uint32 bank;
+ kal_uint32 addr8;
+ kal_uint32 data;
+
+ bank = (addr >> 16) & 0xff;
+ addr8 = addr & 0xff;
+
+ _U3_Write_Bank(bank);
+ data = _U3Read_Reg(addr8);
+ data |= (_U3Read_Reg(addr8+1) << 8);
+ data |= (_U3Read_Reg(addr8+2) << 16);
+ data |= (_U3Read_Reg(addr8+3) << 24);
+ return data;
+}
+
+U32 U3PhyWriteField32(kal_uint32 addr, kal_uint32 offset, kal_uint32 mask, kal_uint32 value){
+ kal_uint32 cur_value;
+ kal_uint32 new_value;
+ cur_value = U3PhyReadReg32(addr);
+ new_value = (cur_value & (~mask)) | ((value << offset) & mask);
+ //udelay(i2cdelayus);
+ U3PhyWriteReg32(addr, new_value);
+ return 0;
+}
+
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.h b/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.h
new file mode 100644
index 0000000..ff1a2c2
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/musb/usb_i2c.h
@@ -0,0 +1,285 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * usb_i2c_v1.h
+ *
+ * Project:
+ * --------
+ * BOOTROM
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __I2C_V1_H__
+#define __I2C_V1_H__
+
+//==============================================================================
+// I2C Register
+//==============================================================================
+#include <platform/mt_reg_base.h>
+#include "mt_usb.h"
+
+#define MT_I2C_DATA_PORT (USB_I2C_BASE + 0x0000)
+#define MT_I2C_SLAVE_ADDR (USB_I2C_BASE + 0x0004)
+#define MT_I2C_INTR_MASK (USB_I2C_BASE + 0x0008)
+#define MT_I2C_INTR_STAT (USB_I2C_BASE + 0x000c)
+#define MT_I2C_CONTROL (USB_I2C_BASE + 0x0010)
+#define MT_I2C_TRANSFER_LEN (USB_I2C_BASE + 0x0014)
+#define MT_I2C_TRANSAC_LEN (USB_I2C_BASE + 0x0018)
+#define MT_I2C_DELAY_LEN (USB_I2C_BASE + 0x001c)
+#define MT_I2C_TIMING (USB_I2C_BASE + 0x0020)
+#define MT_I2C_LTIMING (USB_I2C_BASE + 0x002c)
+#define MT_I2C_START (USB_I2C_BASE + 0x0024)
+#define MT_I2C_FIFO_STAT (USB_I2C_BASE + 0x00f4)
+#define MT_I2C_FIFO_THRESH (USB_I2C_BASE + 0x00f8)
+#define MT_I2C_FIFO_ADDR_CLR (USB_I2C_BASE + 0x0038)
+#define MT_I2C_IO_CONFIG (USB_I2C_BASE + 0x0034)
+#define MT_I2C_DEBUG (USB_I2C_BASE + 0x0044)
+#define MT_I2C_CLOCK_DIV (USB_I2C_BASE + 0x0048)
+#define MT_I2C_HS (USB_I2C_BASE + 0x0030)
+#define MT_I2C_SOFTRESET (USB_I2C_BASE + 0x0050)
+#define MT_I2C_TRAFFIC (USB_I2C_BASE + 0x0054)
+#define MT_I2C_SHAPE (USB_I2C_BASE + 0x006c)
+#define MT_I2C_HW_CG_EN (USB_I2C_BASE + 0x0f88)
+#define MT_I2C_DEBUGSTAT (USB_I2C_BASE + 0x00e4)
+#define MT_I2C_DEBUGCTRL (USB_I2C_BASE + 0x00e8)
+
+#define I2C_TRANS_LEN_MASK (0xff)
+#define I2C_TRANS_AUX_LEN_MASK (0x1f << 8)
+#define I2C_CONTROL_MASK (0x3f << 1)
+
+//----------- Register mask -------------------//
+#define I2C_3_BIT_MASK 0x07
+#define I2C_4_BIT_MASK 0x0f
+#define I2C_6_BIT_MASK 0x3f
+#define I2C_8_BIT_MASK 0xff
+#define I2C_FIFO_THRESH_MASK 0x07
+#define I2C_AUX_LEN_MASK 0x1f00
+#define I2C_MASTER_READ 0x01
+#define I2C_MASTER_WRITE 0x00
+#define I2C_CTL_RS_STOP_BIT 0x02
+#define I2C_CTL_DMA_EN_BIT 0x04
+#define I2C_CTL_CLK_EXT_EN_BIT 0x08
+#define I2C_CTL_DIR_CHANGE_BIT 0x10
+#define I2C_CTL_ACK_ERR_DET_BIT 0x20
+#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
+#define I2C_DATA_READ_ADJ_BIT 0x8000
+#define I2C_SCL_MODE_BIT 0x01
+#define I2C_SDA_MODE_BIT 0x02
+#define I2C_BUS_DETECT_EN_BIT 0x04
+#define I2C_ARBITRATION_BIT 0x01
+#define I2C_CLOCK_SYNC_BIT 0x02
+#define I2C_BUS_BUSY_DET_BIT 0x04
+#define I2C_HS_EN_BIT 0x01
+#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
+#define I2C_HS_MASTER_CODE_MASK 0x70
+#define I2C_HS_STEP_CNT_DIV_MASK 0x700
+#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
+#define I2C_FIFO_FULL_STATUS 0x01
+#define I2C_FIFO_EMPTY_STATUS 0x02
+
+#define I2C_DEBUG (1 << 3)
+#define I2C_HS_NACKERR (1 << 2)
+#define I2C_ACKERR (1 << 1)
+#define I2C_TRANSAC_COMP (1 << 0)
+
+#define I2C_TX_THR_OFFSET 8
+#define I2C_RX_THR_OFFSET 0
+
+/* i2c control bits */
+#define TRANS_LEN_CHG (1 << 6)
+#define ACK_ERR_DET_EN (1 << 5)
+#define DIR_CHG (1 << 4)
+#define CLK_EXT (1 << 3)
+#define DMA_EN (1 << 2)
+#define REPEATED_START_FLAG (1 << 1)
+#define STOP_FLAG (0 << 1)
+
+#define DCM_EN (1 << 0)
+//==============================================================================
+// I2C Configuration
+//==============================================================================
+
+#define I2C_CLK_RATE 13000
+#define I2C_FIFO_SIZE 8
+
+#define MAX_ST_MODE_SPEED 100 /* khz */
+#define MAX_FS_MODE_SPEED 400 /* khz */
+#define MAX_HS_MODE_SPEED 3400 /* khz */
+
+#define MAX_DMA_TRANS_SIZE 252 /* Max(255) aligned to 4 bytes = 252 */
+#define MAX_DMA_TRANS_NUM 256
+
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV 8
+
+#define I2C_TIMEOUT_TH 200 // i2c wait for response timeout value, 200ms
+
+
+//==============================================================================
+// I2C Macro
+//==============================================================================
+#define I2C_START_TRANSAC __raw_writel(0x1,MT_I2C_START)
+#define I2C_FIFO_CLR_ADDR __raw_writel(0x1,MT_I2C_FIFO_ADDR_CLR)
+#define I2C_FIFO_OFFSET (__raw_readl(MT_I2C_FIFO_STAT)>>4&0xf)
+#define I2C_FIFO_IS_EMPTY (__raw_readw(MT_I2C_FIFO_STAT)>>10&0x1)
+
+#define I2C_SOFTRESET __raw_writel(0x1,MT_I2C_SOFTRESET)
+#define I2C_INTR_STATUS __raw_readw(MT_I2C_INTR_STAT)
+
+#define USB_I2C_SET_BITS(BS,REG) ((*(volatile u32*)(REG)) |= (u32)(BS))
+#define USB_I2C_CLR_BITS(BS,REG) ((*(volatile u32*)(REG)) &= ~((u32)(BS)))
+
+#define USB_I2C_SET_FIFO_THRESH(tx,rx) \
+ do { u32 tmp = (((tx) & 0x7) << I2C_TX_THR_OFFSET) | \
+ (((rx) & 0x7) << I2C_RX_THR_OFFSET); \
+ __raw_writel(tmp, MT_I2C_FIFO_THRESH); \
+ } while(0)
+
+#define USB_I2C_SET_INTR_MASK(mask) __raw_writel(mask, MT_I2C_INTR_MASK)
+
+#define USB_I2C_CLR_INTR_MASK(mask)\
+ do { U32 tmp = __raw_readl(MT_I2C_INTR_MASK); \
+ tmp &= ~(mask); \
+ __raw_writel(tmp, MT_I2C_INTR_MASK); \
+ } while(0)
+
+#define USB_I2C_SET_SLAVE_ADDR(addr) __raw_writel(addr, MT_I2C_SLAVE_ADDR)
+
+#define USB_I2C_SET_TRANS_LEN(len) \
+ do { U32 tmp = __raw_readl(MT_I2C_TRANSFER_LEN) & \
+ ~I2C_TRANS_LEN_MASK; \
+ tmp |= ((len) & I2C_TRANS_LEN_MASK); \
+ __raw_writel(tmp, MT_I2C_TRANSFER_LEN); \
+ } while(0)
+
+#define USB_I2C_SET_TRANS_AUX_LEN(len) \
+ do { U32 tmp = __raw_readl(MT_I2C_TRANSFER_LEN) & \
+ ~(I2C_TRANS_AUX_LEN_MASK); \
+ tmp |= (((len) << 8) & I2C_TRANS_AUX_LEN_MASK); \
+ __raw_writel(tmp, MT_I2C_TRANSFER_LEN); \
+ } while(0)
+
+#define USB_I2C_SET_TRANSAC_LEN(len) __raw_writel(len, MT_I2C_TRANSAC_LEN)
+#define USB_I2C_SET_TRANS_DELAY(delay) __raw_writel(delay, MT_I2C_DELAY_LEN)
+
+#define USB_I2C_SET_TRANS_CTRL(ctrl)\
+ do { U32 tmp = __raw_readl(MT_I2C_CONTROL) & ~I2C_CONTROL_MASK; \
+ tmp |= ((ctrl) & I2C_CONTROL_MASK); \
+ __raw_writel(tmp, MT_I2C_CONTROL); \
+ } while(0)
+
+#define USB_I2C_SET_HS_MODE(on_off) \
+ do { U32 tmp = __raw_readl(MT_I2C_HS) & ~0x1; \
+ tmp |= (on_off & 0x1); \
+ __raw_writel(tmp, MT_I2C_HS); \
+ } while(0)
+
+#define USB_I2C_READ_BYTE(byte) \
+ do { byte = __raw_readb(MT_I2C_DATA_PORT); } while(0)
+
+#define USB_I2C_WRITE_BYTE(byte) \
+ do { __raw_writeb(byte, MT_I2C_DATA_PORT); } while(0)
+
+#define USB_I2C_CLR_INTR_STATUS(status) \
+ do { __raw_writew(status, MT_I2C_INTR_STAT); } while(0)
+
+typedef enum __BR_PACKED {
+ ST_MODE=0,
+ FS_MODE,
+ HS_MODE
+} I2C_SPD_MODE;
+
+//==============================================================================
+// I2C Status Code
+//==============================================================================
+#define B_OK 0
+#define E_I2C_SET_SPEED_FAIL_OVER_SPEED 0xA001
+#define E_I2C_READ_FAIL_ZERO_LENGTH 0xA002
+#define E_I2C_READ_FAIL_HS_NACKERR 0xA003
+#define E_I2C_READ_FAIL_ACKERR 0xA004
+#define E_I2C_READ_FAIL_TIMEOUT 0xA005
+#define E_I2C_WRITE_FAIL_ZERO_LENGTH 0xA006
+#define E_I2C_WRITE_FAIL_HS_NACKERR 0xA007
+#define E_I2C_WRITE_FAIL_ACKERR 0xA008
+#define E_I2C_WRITE_FAIL_TIMEOUT 0xA009
+
+//==============================================================================
+// I2C Exported Function
+//==============================================================================
+#define USB_I2C_INIT usb_i2c_v1_init
+#define USB_I2C_READ usb_i2c_v1_read
+#define USB_I2C_WRITE usb_i2c_v1_write
+#define USB_I2C_DEINIT usb_i2c_v1_deinit
+#define USB_I2C_SET_SPEED usb_i2c_v1_set_speed
+
+U32 usb_i2c_v1_init (void);
+U32 usb_i2c_v1_deinit (void);
+U32 usb_i2c_v1_set_speed (unsigned long clock, I2C_SPD_MODE mode, unsigned long khz);
+U32 usb_i2c_v1_read(U8 chip, U8 *buffer, int len);
+U32 usb_i2c_v1_write (U8 chip, U8 *buffer, int len);
+U32 usb_i2c_read8 (U8 cmdBuffer, U8 *dataBuffer);
+U32 usb_i2c_write8 (U8 cmdBuffer, U8 dataBuffer);
+U32 _U3Read_Reg(kal_uint32 address);
+void _U3Write_Reg(kal_uint32 address, kal_uint32 value);
+
+void _U3_Write_Bank(kal_uint32 bankValue);
+U32 U3PhyWriteReg8(kal_uint32 addr, kal_uint8 data);
+
+U32 U3PhyWriteReg32(kal_uint32 addr, kal_uint32 data);
+
+U32 U3PhyReadReg32(kal_uint32 addr);
+U32 U3PhyWriteField32(kal_uint32 addr, kal_uint32 offset, kal_uint32 mask, kal_uint32 value);
+
+#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
+#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
+#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
+#define __raw_writeb(data, addr) ((*(volatile unsigned char *)(addr)) = (unsigned char)data)
+#define __raw_writew(data, addr) ((*(volatile unsigned short *)(addr)) = (unsigned short)data)
+#define __raw_writel(data, addr) ((*(volatile unsigned int *)(addr)) = (unsigned int)data)
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_ecc_hal.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_ecc_hal.c
new file mode 100644
index 0000000..3b07c2f
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_ecc_hal.c
@@ -0,0 +1,547 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <arch/ops.h>
+#include <errno.h>
+#include <kernel/event.h>
+#include <kernel/mutex.h>
+#include <kernel/vm.h>
+#include <malloc.h>
+#include <platform/interrupts.h>
+#include <platform/mt_irq.h>
+#include <platform/mt_reg_base.h>
+#include <platform/nand/mtk_ecc_hal.h>
+#include <platform/nand/mtk_nand_common.h>
+#include <reg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+static inline void mtk_ecc_wait_ioready(struct mtk_ecc *ecc)
+{
+ if (!check_with_timeout((readl(ecc->regs + ECC_PIO_DIRDY) & PIO_DI_RDY), ECC_TIMEOUT))
+ dprintf(CRITICAL, "ecc io not ready\n");
+
+ return;
+}
+
+static void mtk_ecc_runtime_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
+{
+ u32 ecc_bit = ECC_CNFG_4BIT, dec_sz, enc_sz;
+ u32 reg;
+
+ switch (config->strength) {
+ case 4:
+ ecc_bit = ECC_CNFG_4BIT;
+ break;
+ case 6:
+ ecc_bit = ECC_CNFG_6BIT;
+ break;
+ case 8:
+ ecc_bit = ECC_CNFG_8BIT;
+ break;
+ case 10:
+ ecc_bit = ECC_CNFG_10BIT;
+ break;
+ case 12:
+ ecc_bit = ECC_CNFG_12BIT;
+ break;
+ case 14:
+ ecc_bit = ECC_CNFG_14BIT;
+ break;
+ case 16:
+ ecc_bit = ECC_CNFG_16BIT;
+ break;
+ case 18:
+ ecc_bit = ECC_CNFG_18BIT;
+ break;
+ case 20:
+ ecc_bit = ECC_CNFG_20BIT;
+ break;
+ case 22:
+ ecc_bit = ECC_CNFG_22BIT;
+ break;
+ case 24:
+ ecc_bit = ECC_CNFG_24BIT;
+ break;
+ case 28:
+ ecc_bit = ECC_CNFG_28BIT;
+ break;
+ case 32:
+ ecc_bit = ECC_CNFG_32BIT;
+ break;
+ case 36:
+ ecc_bit = ECC_CNFG_36BIT;
+ break;
+ case 40:
+ ecc_bit = ECC_CNFG_40BIT;
+ break;
+ case 44:
+ ecc_bit = ECC_CNFG_44BIT;
+ break;
+ case 48:
+ ecc_bit = ECC_CNFG_48BIT;
+ break;
+ case 52:
+ ecc_bit = ECC_CNFG_52BIT;
+ break;
+ case 56:
+ ecc_bit = ECC_CNFG_56BIT;
+ break;
+ case 60:
+ ecc_bit = ECC_CNFG_60BIT;
+ break;
+ case 68:
+ ecc_bit = ECC_CNFG_68BIT;
+ break;
+ case 72:
+ ecc_bit = ECC_CNFG_72BIT;
+ break;
+ case 80:
+ ecc_bit = ECC_CNFG_80BIT;
+ break;
+ default:
+ dprintf(CRITICAL, "invalid strength %d, default to 4 bits\n",
+ config->strength);
+ break;
+ }
+
+ if (config->op == ECC_ENCODE) {
+ /* configure ECC encoder (in bits) */
+ enc_sz = config->len << 3;
+
+ reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
+ reg |= (enc_sz << ECC_MS_SHIFT);
+ writel(reg, ecc->regs + ECC_ENCCNFG);
+
+ if (config->mode == ECC_DMA_MODE) {
+ if (config->addr & 0x3)
+ dprintf(CRITICAL, "ecc encode address(0x%x) is not 4B aligned !!\n", config->addr);
+ writel(config->addr, ecc->regs + ECC_ENCDIADDR);
+ }
+
+ } else {
+ /* configure ECC decoder (in bits) */
+ dec_sz = (config->len << 3) + config->strength * ECC_PARITY_BITS;
+
+ reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
+ reg |= (dec_sz << ECC_MS_SHIFT) | (config->deccon << DEC_CON_SHIFT);
+ reg |= DEC_EMPTY_EN;
+ writel(reg, ecc->regs + ECC_DECCNFG);
+
+ if (config->mode == ECC_DMA_MODE) {
+ if (config->addr & 0x3)
+ dprintf(CRITICAL, "ecc decode address(0x%x) is not 4B aligned !!\n", config->addr);
+ writel(config->addr, ecc->regs + ECC_DECDIADDR);
+ }
+
+ if (config->sectors)
+ ecc->sectors = 1 << (config->sectors - 1);
+ }
+
+ return;
+}
+
+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
+ enum mtk_ecc_operation op)
+{
+ if (!check_with_timeout(readl(ecc->regs + ECC_IDLE_REG(op)) & ECC_IDLE_MASK, ECC_TIMEOUT))
+ dprintf(CRITICAL, "%s NOT idle\n", op == ECC_ENCODE ? "encoder" : "decoder");
+
+ return;
+}
+
+static int mtk_ecc_irq_wait(struct mtk_ecc *ecc, lk_time_t timeout)
+{
+ int ret;
+
+ ret = event_wait_timeout(&ecc->irq_event, timeout);
+ if (ret != 0) {
+ dprintf(CRITICAL, "[%s]: failed to get event\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static enum handler_return mtk_ecc_interrupt_handler(void *arg)
+{
+ struct mtk_ecc *ecc = arg;
+ enum mtk_ecc_operation op;
+ u32 dec, enc;
+
+ dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
+ if (dec) {
+ op = ECC_DECODE;
+ dec = readw(ecc->regs + ECC_DECDONE);
+ if (dec & ecc->sectors) {
+ ecc->sectors = 0;
+ event_signal(&ecc->irq_event, false);
+ } else {
+ return INT_NO_RESCHEDULE;
+ }
+ } else {
+ enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
+ if (enc) {
+ op = ECC_ENCODE;
+ event_signal(&ecc->irq_event, false);
+ } else {
+ return INT_NO_RESCHEDULE;
+ }
+ }
+
+ writel(0, ecc->regs + ECC_IRQ_REG(op));
+
+ return INT_RESCHEDULE;
+}
+
+static int mtk_ecc_request_irq(struct mtk_ecc *ecc)
+{
+ mt_irq_set_sens(NFIECC_IRQ_BIT_ID, LEVEL_SENSITIVE);
+ mt_irq_set_polarity(NFIECC_IRQ_BIT_ID, MT65xx_POLARITY_LOW);
+ event_init(&ecc->irq_event, false, EVENT_FLAG_AUTOUNSIGNAL);
+ register_int_handler(NFIECC_IRQ_BIT_ID, mtk_ecc_interrupt_handler, ecc);
+ unmask_interrupt(NFIECC_IRQ_BIT_ID);
+
+ return 0;
+}
+
+int mtk_ecc_hw_init(struct mtk_ecc **ext_ecc)
+{
+ struct mtk_ecc *ecc;
+
+ ecc = (struct mtk_ecc *)malloc(sizeof(*ecc));
+ if (!ecc)
+ return -ENOMEM;
+
+ memset(ecc, 0, sizeof(*ecc));
+
+ *ext_ecc = ecc;
+
+ ecc->regs = NFIECC_BASE;
+
+ mtk_ecc_wait_idle(ecc, ECC_ENCODE);
+ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
+
+ mtk_ecc_wait_idle(ecc, ECC_DECODE);
+ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
+
+ mutex_init(&ecc->lock);
+
+ /* register interrupt handler */
+ mtk_ecc_request_irq(ecc);
+
+ return 0;
+}
+
+
+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config, int polling)
+{
+ enum mtk_ecc_operation op = config->op;
+
+ mutex_acquire(&ecc->lock);
+
+ mtk_ecc_wait_idle(ecc, op);
+ mtk_ecc_runtime_config(ecc, config);
+
+ if (!polling) {
+ writew(ECC_IRQ_EN, ecc->regs + ECC_IRQ_REG(op));
+ }
+
+ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
+
+ return 0;
+}
+
+void mtk_ecc_disable(struct mtk_ecc *ecc)
+{
+ enum mtk_ecc_operation op = ECC_ENCODE;
+
+ /* find out the running operation */
+ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
+ op = ECC_DECODE;
+
+ /* disable it */
+ mtk_ecc_wait_idle(ecc, op);
+ writew(0, ecc->regs + ECC_IRQ_REG(op));
+ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
+
+ mutex_release(&ecc->lock);
+
+ return;
+}
+
+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
+ u32 sectors)
+{
+ u32 offset, i, err;
+ u32 bitflips = 0;
+
+ stats->corrected = 0;
+ stats->failed = 0;
+
+ for (i = 0; i < sectors; i++) {
+ offset = (i >> 2);
+ err = readl(ecc->regs + ECC_DECENUM(offset));
+ err = err >> ((i % 4) * 8);
+ err &= ERR_MASK;
+ if (err == ERR_MASK) {
+ /* uncorrectable errors */
+ stats->failed++;
+ dprintf(ALWAYS, "sector %d is uncorrect\n", i);
+ continue;
+ }
+
+ stats->corrected += err;
+ bitflips = MAX(bitflips, err);
+ }
+
+ stats->bitflips = bitflips;
+
+ return;
+}
+
+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op, int polling)
+{
+ int ret = 0;
+
+ if (!polling) {
+ ret = mtk_ecc_irq_wait(ecc, ECC_TIMEOUT);
+ if (!ret) {
+ dprintf(CRITICAL, "mtk_ecc_wait_done timeout\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ if (op == ECC_ENCODE) {
+ if (!check_with_timeout((readl(ecc->regs + ECC_ENCSTA) & ENC_IDLE), ECC_TIMEOUT)) {
+ dprintf(CRITICAL, "encoder timeout\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ if (!check_with_timeout((readw(ecc->regs + ECC_DECDONE) & ecc->sectors), ECC_TIMEOUT)) {
+ dprintf(CRITICAL, "decoder timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int mtk_ecc_wait_decode_fsm_idle(struct mtk_ecc *ecc)
+{
+ /* decode done does not stands for ecc all work done.
+ * we need check syn, bma, chien, autoc all idle.
+ * just check it when ECC_DECCNFG[13:12] is 3, which means auto correct.*/
+ if (!check_with_timeout(((readl(ecc->regs + ECC_DECFSM) & FSM_MASK) == FSM_IDLE), ECC_TIMEOUT)) {
+ dprintf(CRITICAL, "decode fsm(0x%x) is not idle\n", readl(ecc->regs + ECC_DECFSM));
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
+ u8 *data, u32 bytes, int polling)
+{
+ uintptr_t addr;
+ u8 *p;
+ u8 *buf = data;
+ u32 len, i, val = 0;
+ int ret = 0;
+
+ /* encoder memory address should be 4B aligned */
+ if ((config->mode == ECC_DMA_MODE) && ((uintptr_t)buf & 0x3)) {
+ buf = memalign(4, bytes);
+ if (!buf)
+ return -ENOMEM;
+ memcpy(buf, data, bytes);
+ }
+#ifdef WITH_KERNEL_VM
+ addr = (uintptr_t)kvaddr_to_paddr(buf);
+#else
+ addr = (uintptr_t)buf;
+#endif
+ if (config->mode == ECC_DMA_MODE)
+ arch_clean_cache_range((addr_t)buf, (size_t)bytes);
+
+ config->op = ECC_ENCODE;
+ config->addr = (u32)addr;
+ config->len = bytes;
+
+ ret = mtk_ecc_enable(ecc, config, polling);
+ if (ret)
+ goto freebuf;
+
+ if (config->mode == ECC_PIO_MODE) {
+ for (i = 0; i < ((config->len + 3) >> 2); i++) {
+ mtk_ecc_wait_ioready(ecc);
+ writel(*((u32 *)data + i), ecc->regs + ECC_PIO_DI);
+ }
+ }
+
+ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE, polling);
+ if (ret)
+ goto timeout;
+
+ mtk_ecc_wait_idle(ecc, ECC_ENCODE);
+
+ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
+ len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
+ p = data + bytes;
+
+ /* write the parity bytes generated by the ECC back to the OOB region */
+ for (i = 0; i < len; i++) {
+ if ((i % 4) == 0)
+ val = readl(ecc->regs + ECC_ENCPAR(i / 4));
+ p[i] = (val >> ((i % 4) * 8)) & 0xff;
+ }
+
+timeout:
+ mtk_ecc_disable(ecc);
+freebuf:
+ if (config->mode == ECC_DMA_MODE)
+ arch_invalidate_cache_range((addr_t)buf, (size_t)bytes);
+ if (buf != data)
+ free(buf);
+ return ret;
+}
+
+int mtk_ecc_decode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
+ u8 *data, u32 len, int polling)
+{
+ struct mtk_ecc_stats stats;
+ u8 *buf = data;
+ uintptr_t addr;
+ u32 decodesize, i;
+ int ret;
+
+ decodesize = len + ((config->strength * ECC_PARITY_BITS + 7) >> 3);
+ if ((decodesize & 0x3)
+ || ((config->mode == ECC_DMA_MODE) && ((uintptr_t)buf & 0x3))) {
+ decodesize += 4 - (decodesize & 0x3);
+ buf = memalign(4, decodesize);
+ if (!buf)
+ return -ENOMEM;
+ }
+ if (config->mode == ECC_DMA_MODE)
+ arch_invalidate_cache_range((addr_t)buf, (size_t)decodesize);
+#ifdef WITH_KERNEL_VM
+ addr = (uintptr_t)kvaddr_to_paddr(buf);
+#else
+ addr = (uintptr_t)buf;
+#endif
+ config->op = ECC_DECODE;
+ config->addr = (u32)addr;
+ config->len = len;
+ ret = mtk_ecc_enable(ecc, config, polling);
+ if (ret)
+ goto freebuf;
+
+ if (config->mode == ECC_PIO_MODE) {
+ for (i = 0; i < (decodesize >> 2); i++) {
+ mtk_ecc_wait_ioready(ecc);
+ writel(*((u32 *)buf + i), ecc->regs + ECC_PIO_DI);
+ }
+ }
+
+ stats.bitflips = 0;
+ ret = mtk_ecc_cpu_correct(ecc, &stats, buf, 0, polling);
+ if (ret)
+ goto disecc;
+
+ if (config->mode == ECC_DMA_MODE)
+ arch_invalidate_cache_range((addr_t)buf, (size_t)decodesize);
+ if (buf != data)
+ memcpy(data, buf, len);
+
+disecc:
+ mtk_ecc_disable(ecc);
+
+freebuf:
+ if (buf != data)
+ free(buf);
+
+ return ret;
+}
+
+int mtk_ecc_cpu_correct(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, u8 *data, u32 sector, int polling)
+{
+ u32 err, offset, i;
+ u32 loc, byteloc, bitloc;
+ int ret;
+
+ ecc->sectors = 1 << sector;
+ ret = mtk_ecc_wait_done(ecc, ECC_DECODE, polling);
+ if (ret)
+ return ret;
+
+ stats->corrected = 0;
+ stats->failed = 0;
+
+ offset = (sector >> 2);
+ err = readl(ecc->regs + ECC_DECENUM(offset));
+ err = err >> ((sector % 4) * 8);
+ err &= ERR_MASK;
+ if (err == ERR_MASK) {
+ /* uncorrectable errors */
+ stats->failed++;
+ return 0;
+ }
+
+ stats->corrected += err;
+ stats->bitflips = MAX(stats->bitflips, err);
+
+ for (i = 0; i < err; i++) {
+ loc = readl(ecc->regs + ECC_DECEL(i >> 1));
+ loc >>= ((i & 0x1) << 4);
+ loc &= DECEL_MASK;
+ byteloc = loc >> 3;
+ bitloc = loc & 0x7;
+ data[byteloc] ^= (1 << bitloc);
+ }
+
+ return 0;
+}
+
+void mtk_ecc_adjust_strength(u32 *p)
+{
+ u32 ecc[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
+ 40, 44, 48, 52, 56, 60, 68, 72, 80
+ };
+ u32 i;
+
+ for (i = 0; i < sizeof(ecc) / sizeof(u32); i++) {
+ if (*p <= ecc[i]) {
+ if (!i)
+ *p = ecc[i];
+ else if (*p != ecc[i])
+ *p = ecc[i - 1];
+ return;
+ }
+ }
+
+ *p = ecc[sizeof(ecc) / sizeof(u32) - 1];
+
+ return;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_bbt.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_bbt.c
new file mode 100644
index 0000000..49f831b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_bbt.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <errno.h>
+#include <malloc.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define BBT_BLOCK_GOOD 0x03
+#define BBT_BLOCK_WORN 0x02
+#define BBT_BLOCK_RESERVED 0x01
+#define BBT_BLOCK_FACTORY_BAD 0x00
+
+#define BBT_ENTRY_MASK 0x03
+#define BBT_ENTRY_SHIFT 2
+
+#define SCAN_BBT_MAXBLOCKS 4
+#define BBT_PATTERN_LEN 4
+#define BBT_VERSION_LEN 1
+
+static int check_pattern(u8 *buf)
+{
+ uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
+ uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+ if (!memcmp(buf, bbt_pattern, BBT_PATTERN_LEN))
+ return 0;
+ if (!memcmp(buf, mirror_pattern, BBT_PATTERN_LEN))
+ return 0;
+
+ return 1;
+}
+
+static void bbt_mark_entry(struct mtk_nand_chip *chip, int block, u8 mask)
+{
+ u32 offset = BBT_PATTERN_LEN + BBT_VERSION_LEN;
+
+ mask = (mask & BBT_ENTRY_MASK) << ((block & BBT_ENTRY_MASK) * 2);
+ offset += block >> BBT_ENTRY_SHIFT;
+
+ chip->bbt[offset] &= ~(BBT_ENTRY_MASK << ((block & BBT_ENTRY_MASK) * 2));
+ chip->bbt[offset] |= mask;
+}
+
+static u8 bbt_get_entry(struct mtk_nand_chip *chip, int block)
+{
+ u32 offset = BBT_PATTERN_LEN + BBT_VERSION_LEN;
+ u8 entry;
+
+ offset += block >> BBT_ENTRY_SHIFT;
+ entry = chip->bbt[offset];
+ entry >>= (block & BBT_ENTRY_MASK) * 2;
+
+ return entry & BBT_ENTRY_MASK;
+}
+
+static int search_bbt(struct mtk_nand_chip *chip, int bbt_len)
+{
+ int block, i;
+ struct mtk_nand_ops ops;
+
+ memset(&ops, 0, sizeof(ops));
+
+ block = chip->totalsize / chip->blocksize;
+
+ for (i = 1; i < SCAN_BBT_MAXBLOCKS; i++) {
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = (u64)(block-i) * chip->blocksize;
+ ops.len = (u64)bbt_len;
+ ops.readbuf = chip->bbt;
+
+ mtk_nand_read(chip, &ops);
+ if (!check_pattern(chip->bbt)) {
+ chip->bbt_block = block - i;
+ dprintf(CRITICAL, "found bbt at block %d, version 0x%02X\n",
+ block - i, chip->bbt[BBT_PATTERN_LEN]);
+ return 0;
+ }
+ }
+
+ dprintf(CRITICAL, "failed to find bbt!\n");
+ return -1;
+}
+
+static int create_bbt(struct mtk_nand_chip *chip, int bbt_len)
+{
+ int i, blocks = chip->totalsize / chip->blocksize;
+
+ memset(chip->bbt, 0xff, bbt_len);
+
+ for (i = 0; i < blocks; i++) {
+ if (mtk_nand_block_checkbad(chip, i * chip->page_per_block)) {
+ bbt_mark_entry(chip, i, BBT_BLOCK_FACTORY_BAD);
+ dprintf(CRITICAL, "block %d is bad\n", i);
+ }
+ }
+
+ dprintf(ALWAYS, "create bbt done!\n");
+
+ return 0;
+}
+
+static void print_bad(struct mtk_nand_chip *chip)
+{
+ int blocks = chip->totalsize / chip->blocksize;
+ u8 entry;
+ int i;
+
+ for (i = 0; i < blocks; i++) {
+ entry = bbt_get_entry(chip, i);
+ if (entry == BBT_BLOCK_FACTORY_BAD)
+ dprintf(CRITICAL, "block %d is factory bad\n");
+ else if(entry == BBT_BLOCK_WORN)
+ dprintf(CRITICAL, "block %d is worn bad\n");
+ else if(entry == BBT_BLOCK_RESERVED)
+ dprintf(CRITICAL, "block %d is reserved\n");
+ }
+}
+
+int mtk_nand_scan_bbt(struct mtk_nand_chip *chip)
+{
+ int len;
+ int ret = 0;
+
+ len = (chip->totalsize / chip->blocksize + 3) >> 2;
+ len += BBT_PATTERN_LEN + BBT_VERSION_LEN;
+ /* allocate bbt memory */
+ chip->bbt = malloc(len);
+ if (!chip->bbt)
+ return -ENOMEM;
+ memset(chip->bbt, 0xff, len);
+ chip->bbt_block = -1;
+
+ if (search_bbt(chip, len)) {
+ ret = create_bbt(chip, len);
+ }
+
+ print_bad(chip);
+
+ return ret;
+}
+
+int mtk_nand_isbad_bbt(struct mtk_nand_chip *chip, u32 page)
+{
+ int block = page / chip->page_per_block;
+ u8 mask;
+
+ mask = bbt_get_entry(chip, block);
+
+ return mask != BBT_BLOCK_GOOD;
+}
+
+int mtk_nand_markbad_bbt(struct mtk_nand_chip *chip, u32 page)
+{
+ struct mtk_nand_ops ops;
+ int len, write_len;
+ int ret = 0, block = page / chip->page_per_block;
+
+ bbt_mark_entry(chip, block, BBT_BLOCK_WORN);
+
+ if (chip->bbt_block > 0) {
+ memset(&ops, 0, sizeof(struct mtk_nand_ops));
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = (u64)chip->bbt_block * chip->blocksize;
+ ops.len = chip->blocksize;
+ ret = mtk_nand_erase(chip, &ops);
+ if (ret)
+ goto err;
+
+ /* increase bbt version */
+ chip->bbt[BBT_PATTERN_LEN]++;
+
+ len = (chip->totalsize / chip->blocksize + 3) >> 2;
+ len += BBT_PATTERN_LEN + BBT_VERSION_LEN;
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.len = chip->pagesize;
+ ops.writebuf = chip->databuf;
+ while (len) {
+ write_len = MIN((u32)len, chip->pagesize);
+ memset(chip->databuf, 0, chip->pagesize);
+ memcpy(chip->databuf, chip->bbt, write_len);
+ ret = mtk_nand_write(chip, &ops);
+ if (ret)
+ goto err;
+ len -= write_len;
+ ops.offset += chip->pagesize;
+ }
+ }
+
+err:
+ return ret;
+}
+
+int mtk_nand_unmarkbad_bbt(struct mtk_nand_chip *chip, u32 page)
+{
+ struct mtk_nand_ops ops;
+ int len, write_len;
+ int ret = 0, block = page / chip->page_per_block;
+
+ bbt_mark_entry(chip, block, BBT_BLOCK_GOOD);
+
+ if (chip->bbt_block > 0) {
+ memset(&ops, 0, sizeof(struct mtk_nand_ops));
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = (u64)chip->bbt_block * chip->blocksize;
+ ops.len = chip->blocksize;
+ ret = mtk_nand_erase(chip, &ops);
+ if (ret)
+ goto err;
+
+ /* increase bbt version */
+ chip->bbt[BBT_PATTERN_LEN]++;
+
+ len = (chip->totalsize / chip->blocksize + 3) >> 2;
+ len += BBT_PATTERN_LEN + BBT_VERSION_LEN;
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.len = chip->pagesize;
+ ops.writebuf = chip->databuf;
+ while (len) {
+ write_len = MIN((u32)len, chip->pagesize);
+ memset(chip->databuf, 0, chip->pagesize);
+ memcpy(chip->databuf, chip->bbt, write_len);
+ ret = mtk_nand_write(chip, &ops);
+ if (ret)
+ goto err;
+ len -= write_len;
+ ops.offset += chip->pagesize;
+ }
+ }
+
+err:
+ return ret;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_device.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_device.c
new file mode 100644
index 0000000..1bb1acf
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_device.c
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018 MediaTek Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining
+* a copy of this software and associated documentation files
+* (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be
+* included in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#include <platform/nand/mtk_nand_common.h>
+#include <platform/nand/mtk_nand_nal.h>
+
+#define NAND_OPTIONS_NONE (0)
+
+struct mtk_nand_flash_dev nand_flash_devs[] = {
+ {"F59D4G81A-45TG-18V", {0xc8, 0xac, 0x90, 0x15, 0x54, 0, 0, 0}, 5, KB(512), KB(128), 2048, 64, 1, 1, 0, 0x10804011, 1024, 4, NAND_OPTIONS_NONE, NAND_OPTIONS_NONE},
+ {"MT29F16G08ADBCA", {0x2c, 0xa5, 0xd1, 0x26, 0x68, 0, 0, 0}, 5, KB(2048), KB(256), 4096, 224, 1, 1, 0, 0x10404011, 1024, 24, NAND_OPTIONS_NONE, NAND_CACHEREAD | NAND_CACHEPRG},
+ /* MCP-LP4:MT29GZ5A3BPGGA-53AAT */
+ {"MT29F4G08ABBFAH", {0x2c, 0xac, 0x80, 0x26, 0x62, 0, 0, 0}, 5, KB(512), KB(256), 4096, 256, 1, 1, 0x53, 0x10805111, 512, 12, NAND_OPTIONS_NONE, NAND_OPTIONS_NONE},
+ /* MCP-LP2:MT29AZ5A3CHHWD-18AAT */
+ {"MT29F4G08ABBDA", {0x2c, 0xac, 0x90, 0x15, 0x56, 0, 0, 0}, 5, KB(512), KB(128), 2048, 64, 1, 1, 0x63, 0x10806111, 512, 4, NAND_OPTIONS_NONE, NAND_OPTIONS_NONE},
+ /* MCP-LP4:MT29GZ5A5BPGGA-53IT.87J */
+ {"MT29F4G08ABAFA", {0x2c, 0xdc, 0x80, 0xa6, 0x62, 0, 0, 0}, 5, KB(512), KB(256), 4096, 256, 1, 1, 0x53, 0x10805111, 512, 12, NAND_OPTIONS_NONE, NAND_OPTIONS_NONE},
+ /* MCP-LP4:MT29GZ6A6BPIET-53AIT.112 or MT29GZ6A6BPIET-53AAT.112*/
+ {"MT29F8G08ADBFA", {0x2c, 0xa3, 0xd0, 0x26, 0x66, 0, 0, 0}, 5, KB(1024), KB(256), 4096, 256, 1, 1, 0x53, 0x10805111, 512, 12, NAND_OPTIONS_NONE, NAND_OPTIONS_NONE},
+ {NULL}
+};
+
+#if MT2731_SUPPORT_SPI_NAND
+struct mtk_nand_flash_dev snand_flash_devs[] = {
+ /* FPGA use - SPI NAND */
+ {"MT29F4G01ABAFD", {0x2c, 0x34, 0, 0, 0, 0, 0, 0}, 2, KB(512), KB(256), 4096, 256, 1, 1, 0, 0x10804011, 512, 12, NAND_OPTIONS_NONE, NAND_SINGLE_PLANE},
+ {"MT29F8G01ADBFD", {0x2c, 0x46, 0, 0, 0, 0, 0, 0}, 2, KB(512), KB(256), 4096, 256, 1, 1, 0, 0x10404011, 512, 12, NAND_OPTIONS_NONE, NAND_SINGLE_PLANE_TWO_DIE},
+ /* Bring-up use - SPI:MT29F4G01ABBFD12-AAT */
+ {"MT29F4G01ABBFD", {0x2c, 0x37, 0, 0, 0, 0, 0, 0}, 2, KB(512), KB(256), 4096, 256, 1, 1, 0, 0x10404011, 512, 12, NAND_OPTIONS_NONE, NAND_SINGLE_PLANE},
+ {NULL}
+};
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nal.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nal.c
new file mode 100644
index 0000000..0a55885
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nal.c
@@ -0,0 +1,1540 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <debug.h>
+#include <errno.h>
+#include <kernel/mutex.h>
+#include <malloc.h>
+#include <platform/nand/mtk_nand_bbt.h>
+#include <platform/nand/mtk_nand_common.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <platform/nand/mtk_nfi_hal.h>
+#include <stdlib.h>
+#include <string.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <platform/pll.h>
+
+static struct mtk_nand_chip *nandchip;
+
+#if MT2731_SUPPORT_SPI_NAND
+static struct mtk_nand_chip *spinandchip;
+
+static int mtk_snand_do_read_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops);
+static int mtk_snand_do_erase_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops);
+static int mtk_snand_do_write_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops);
+
+static int mtk_snand_read_oob_raw(struct mtk_nand_chip *chip, uint8_t *buf,
+ int page_addr, int len);
+
+#endif
+
+static int mtk_nand_do_read_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops);
+static int mtk_nand_do_erase_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops, int force_erase);
+static int mtk_nand_do_write_ops(struct mtk_nand_chip *chip,
+ struct mtk_nand_ops *ops);
+
+static int mtk_nand_get_controller(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mutex_acquire(&nfc->lock);
+
+ return 0;
+}
+
+static int mtk_nand_release_controller(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mutex_release(&nfc->lock);
+
+ return 0;
+}
+
+static int mtk_nand_wait_func(struct mtk_nand_chip *chip, int polling)
+{
+ int status;
+ unsigned long timeo = 1000000;
+
+ chip->cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
+
+ if (!polling) {
+ if (chip->wait_busy_irq(chip))
+ dprintf(CRITICAL, "nand dev ready timeout\n");
+ } else {
+ if (!check_with_timeout(chip->dev_ready(chip), timeo))
+ dprintf(CRITICAL, "nand dev ready timeout\n");
+ }
+
+ status = (int)chip->read_byte(chip);
+
+ return status;
+}
+
+void mtk_nand_wait_ready(struct mtk_nand_chip *chip)
+{
+ unsigned long timeo = 1000000;
+
+ if (!check_with_timeout(chip->dev_ready(chip), timeo))
+ dprintf(CRITICAL, "nand dev ready timeout\n");
+
+ return;
+}
+
+static int mtk_nand_check_wp(struct mtk_nand_chip *chip)
+{
+ /* Check the WP bit */
+ chip->cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
+ return (chip->read_byte(chip) & NAND_STATUS_WP) ? 0 : 1;
+}
+
+static int mtk_nand_block_bad(struct mtk_nand_chip *chip, u64 ofs)
+{
+ int page, res = 0, i = 0;
+ u16 bad;
+
+ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+ ofs += chip->blocksize - chip->pagesize;
+
+ page = (int)(ofs / chip->pagesize) % chip->page_per_chip;
+
+ do {
+ chip->cmdfunc(chip, NAND_CMD_READOOB, chip->badblockpos, page);
+ bad = chip->read_byte(chip);
+
+ if (chip->badblockbits == 8)
+ res = bad != 0xFF;
+
+ ofs += chip->pagesize;
+ page = (int)(ofs / chip->pagesize) % chip->page_per_chip;
+ i++;
+ } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+
+ return res;
+}
+
+int mtk_nand_block_checkbad(struct mtk_nand_chip *chip, u32 page)
+{
+ struct mtk_nand_ops ops;
+ int ret = 0;
+
+ /* block align */
+ page = page / chip->page_per_block * chip->page_per_block;
+
+ if (!(chip->options & NAND_NEED_SCRAMBLING)) {
+ ret = chip->block_bad(chip, (u64)page * chip->pagesize);
+ } else {
+ /*
+ * The output data is randomized if randomizer is on,
+ * we will get a wrong result if just read one byte data.
+ * So, should read page directly.
+ */
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = (u64)page * chip->pagesize;
+ ops.len = chip->pagesize;
+ ops.readbuf = chip->databuf;
+
+ if (chip->bIsPNAND)
+ ret = mtk_nand_do_read_ops(chip, &ops);
+#if MT2731_SUPPORT_SPI_NAND
+ else
+ ret = mtk_snand_do_read_ops(chip, &ops);
+#endif
+ if (ret < 0)
+ ret = 1;
+ else
+ ret = chip->oob_poi[chip->badblockpos] != 0xFF;
+ }
+
+ return ret;
+}
+
+static int mtk_nand_block_isbad_lowlevel(struct mtk_nand_chip *chip, u32 page)
+{
+ if (chip->bbt)
+ return mtk_nand_isbad_bbt(chip, page);
+ else
+ return mtk_nand_block_checkbad(chip, page);
+}
+
+int mtk_nand_block_isbad(struct mtk_nand_chip *chip, u32 page)
+{
+ int ret;
+
+ mtk_nand_get_controller(chip);
+ ret = mtk_nand_block_isbad_lowlevel(chip, page);
+ mtk_nand_release_controller(chip);
+
+ return ret;
+}
+
+int mtk_nand_block_markbad(struct mtk_nand_chip *chip, u32 page)
+{
+ struct mtk_nand_ops ops;
+ u32 i = 0;
+ int ret = 0;
+
+ mtk_nand_get_controller(chip);
+ /* block align */
+ page = page / chip->page_per_block * chip->page_per_block;
+
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = (u64)(page * chip->pagesize);
+ ops.len = chip->blocksize;
+ mtk_nand_do_erase_ops(chip, &ops, 0);
+
+ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+ ops.offset += chip->blocksize - chip->pagesize;
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.writebuf = chip->databuf;
+ ops.len = chip->pagesize;
+ ops.oobeccbuf = &chip->oob_poi[chip->oob_free_ecc_size
+ + chip->oob_free_raw_size];
+ ops.oobecclen = chip->ecc_steps * chip->fdm_ecc_size;
+ ops.oobeccoffs = 0;
+ ops.oobrawbuf = NULL;
+ memset(chip->databuf, 0, chip->pagesize);
+ memset(ops.oobeccbuf, 0, ops.oobecclen);
+ do {
+ ops.offset += chip->pagesize;
+ mtk_nand_do_write_ops(chip, &ops);
+ i++;
+ } while (i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+
+ mtk_nand_release_controller(chip);
+
+ if (chip->bbt)
+ ret = mtk_nand_markbad_bbt(chip, page);
+
+ return ret;
+}
+
+int mtk_nand_block_unmarkbad(struct mtk_nand_chip *chip, u32 page)
+{
+ struct mtk_nand_ops ops;
+ int ret = 0;
+
+ memset(&ops, 0, sizeof(ops));
+ /* block align */
+ page = page / chip->page_per_block * chip->page_per_block;
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = (u64)(page * chip->pagesize);
+ ops.len = chip->blocksize;
+ mtk_nand_force_erase(chip, &ops);
+
+ if (chip->bbt)
+ ret = mtk_nand_unmarkbad_bbt(chip, page);
+
+ return ret;
+}
+
+int nand_reset(struct mtk_nand_chip *chip, int chipnr)
+{
+ /* power on sequence delay */
+ spin(300);
+
+ /*
+ * The CS line has to be released before we can apply the new NAND
+ * interface settings, hence this weird ->select_chip() dance.
+ */
+ chip->select_chip(chip, chipnr);
+ chip->cmdfunc(chip, NAND_CMD_RESET, -1, -1);
+ chip->select_chip(chip, -1);
+
+ return 0;
+}
+
+static inline int mtk_nand_opcode_8bits(unsigned int command)
+{
+ switch (command) {
+ case NAND_CMD_READID:
+ case NAND_CMD_PARAM:
+ case NAND_CMD_GET_FEATURES:
+ case NAND_CMD_SET_FEATURES:
+ return 1;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void mtk_nand_command_lp(struct mtk_nand_chip *chip, unsigned int command,
+ int column, int page_addr)
+{
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += chip->pagesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Command latch cycle */
+ chip->cmd_ctrl(chip, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ if (column != -1 || page_addr != -1) {
+ int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
+
+ /* Serially input address */
+ if (column != -1) {
+ chip->cmd_ctrl(chip, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+
+ /* Only output a single addr cycle for 8bits opcodes. */
+ if (!mtk_nand_opcode_8bits(command))
+ chip->cmd_ctrl(chip, column >> 8, ctrl);
+ }
+ if (page_addr != -1) {
+ chip->cmd_ctrl(chip, page_addr, ctrl);
+ chip->cmd_ctrl(chip, page_addr >> 8, NAND_NCE | NAND_ALE);
+ /* One more address cycle for devices > 128MiB */
+ if (chip->chipsize > (128 << 20))
+ chip->cmd_ctrl(chip, page_addr >> 16, NAND_NCE | NAND_ALE);
+ }
+ }
+ chip->cmd_ctrl(chip, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Program and erase have their own busy handlers status, sequential
+ * in and status need no delay.
+ */
+ switch (command) {
+ case NAND_CMD_CACHEDPROG:
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ case NAND_CMD_SEQIN:
+ case NAND_CMD_STATUS:
+ return;
+
+ case NAND_CMD_RNDOUT:
+ /* No ready / busy check necessary */
+ chip->cmd_ctrl(chip, NAND_CMD_RNDOUTSTART, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ chip->cmd_ctrl(chip, NAND_CMD_NONE,
+ NAND_NCE | NAND_CTRL_CHANGE);
+ return;
+
+ case NAND_CMD_READ0:
+ chip->cmd_ctrl(chip, NAND_CMD_READSTART, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ chip->cmd_ctrl(chip, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /* This applies to read commands */
+ default:
+ break;
+ }
+
+ mtk_nand_wait_ready(chip);
+
+ return;
+}
+
+static void mtk_nand_set_defaults(struct mtk_nand_chip *chip)
+{
+ /* chip_delay setup set 20us if not */
+ chip->chip_delay = 20;
+
+ /* command function*/
+ chip->cmdfunc = mtk_nand_command_lp;
+
+ /* wait function */
+ chip->waitfunc = mtk_nand_wait_func;
+
+ /* bad block check */
+ chip->block_bad = mtk_nand_block_bad;
+
+ /* variable defalut value */
+ chip->badblockbits = 8;
+ chip->badblockpos = 0;
+
+ chip->activechip = -1;
+
+ return;
+}
+
+int mtk_nand_flash_get(struct mtk_nand_chip *chip, int maxchips)
+{
+ int i;
+ u8 id_data[8];
+ struct mtk_nand_flash_dev *type = nand_flash_devs;
+
+ nand_reset(chip, 0);
+
+ /* Select the device */
+ chip->select_chip(chip, 0);
+
+ /* Send the command for reading device ID */
+ chip->cmdfunc(chip, NAND_CMD_READID, 0x00, -1);
+
+ /* Read entire ID string */
+ for (i = 0; i < 8; i++) {
+ id_data[i] = chip->read_byte(chip);
+ dprintf(ALWAYS, "nand id[%d] [%x] \n", i, id_data[i]);
+ }
+
+ for (; type->name != NULL; type++) {
+ if (!strncmp((char const*)type->id, (char const*)id_data, type->id_len)) {
+ dprintf(ALWAYS, "nand found [%s] \n", type->name);
+ break;
+ }
+ }
+
+ chip->select_chip(chip, -1);
+ if (!type->name) {
+ return -ENODEV;
+ }
+
+ chip->numchips = 1;
+
+ /* Check for a chip array */
+ for (i = 1; i < maxchips; i++) {
+ /* See comment in nand_get_flash_type for reset */
+ nand_reset(chip, i);
+
+ chip->select_chip(chip, i);
+ /* Send the command for reading device ID */
+ chip->cmdfunc(chip, NAND_CMD_READID, 0x00, -1);
+ /* Read manufacturer and device IDs */
+ if (id_data[0] != chip->read_byte(chip) ||
+ id_data[1] != chip->read_byte(chip)) {
+ chip->select_chip(chip, -1);
+ break;
+ }
+ dprintf(ALWAYS, "chip %d is found\n", i);
+ chip->select_chip(chip, -1);
+ chip->numchips++;
+ }
+
+ /* set acc timing */
+ chip->freq_map = type->freq_map;
+ chip->acctiming = type->acctiming;
+
+ /* set nand chip parameters */
+ chip->pagesize = type->pagesize;
+ chip->oobsize = type->oobsize;
+ chip->bits_per_cell = type->bits_per_cell;
+ /* KB to B */
+ chip->chipsize = ((u64)type->chipsize) << 10;
+ chip->blocksize = type->erasesize;
+ chip->bbt_options |= type->bbt_options;
+ chip->options |= type->options;
+ chip->ecc_size = type->ecc_size;
+ chip->ecc_strength = type->ecc_strength;
+ chip->fdm_ecc_size = type->fdmeccsize;
+
+ chip->totalsize = i * chip->chipsize;
+
+ chip->ecc_steps = chip->pagesize / chip->ecc_size;
+ if (nand_is_slc(chip)) {
+ if (chip->ecc_steps == 2)
+ chip->subpagesize = chip->pagesize / 2;
+ else if (chip->ecc_steps > 2)
+ chip->subpagesize = chip->pagesize / 4;
+ else
+ chip->subpagesize = chip->pagesize;
+ }
+ chip->page_per_block = chip->blocksize / chip->pagesize;
+ chip->page_per_chip = chip->chipsize / chip->pagesize;
+
+ chip->databuf = (u8 *)memalign(16, chip->pagesize + chip->oobsize);
+ if (!chip->databuf)
+ return -ENOMEM;
+ chip->oob_poi = chip->databuf + chip->pagesize;
+
+ return 0;
+}
+
+int mtk_nand_scan(struct mtk_nand_chip *chip, int maxchips)
+{
+ int ret;
+
+ /* Set the defaults */
+ mtk_nand_set_defaults(chip);
+
+ ret = mtk_nand_flash_get(chip, maxchips);
+ if (ret) {
+ dprintf(CRITICAL, "no nand device found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_nand_scan_tail(struct mtk_nand_chip *chip)
+{
+ int ret;
+
+ /* scan bad block table */
+ ret = mtk_nand_scan_bbt(chip);
+
+ return ret;
+}
+
+static int mtk_nand_transfer_oob(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret = 0;
+ u32 parity_size;
+
+ parity_size = chip->oobsize - chip->oob_free_raw_size
+ - chip->oob_free_ecc_size;
+
+ if (ops->oobeccbuf && chip->transfer_oob_ecc) {
+ if (ops->oobeccoffs >= chip->oob_free_ecc_size
+ || ops->oobecclen > chip->oob_free_ecc_size - ops->oobeccoffs)
+ return -EINVAL;
+ ret = chip->transfer_oob_ecc(chip, ops->oobeccbuf, ops->oobeccoffs,
+ ops->oobecclen);
+ if (ret)
+ return ret;
+ }
+
+ if (ops->oobrawbuf && chip->transfer_oob_raw) {
+ if (ops->oobrawoffs >= chip->oob_free_raw_size
+ || ops->oobrawlen > chip->oob_free_raw_size - ops->oobrawoffs)
+ return -EINVAL;
+ ret = chip->transfer_oob_raw(chip, ops->oobrawbuf, ops->oobrawoffs,
+ ops->oobrawlen);
+ }
+
+ if (ops->oobparitybuf && chip->transfer_oob_parity) {
+ if (ops->oobparityoffs >= parity_size
+ || ops->oobparitylen > parity_size - ops->oobparityoffs)
+ return -EINVAL;
+ ret = chip->transfer_oob_parity(chip, ops->oobparitybuf, ops->oobparityoffs,
+ ops->oobparitylen);
+ }
+
+ return ret;
+}
+
+static int mtk_nand_do_read_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int chipnr, page, realpage, col, aligned;
+ u8 *buf, *bufpoi;
+ u64 readlen = ops->len, from = ops->offset;
+ u32 bytes, ecc_failures = chip->stats.failed;
+ int ret = 0, ecc_fail = 0, max_bitflips = 0;
+ bool enable_cache = false;
+
+ chipnr = (int)(from / chip->chipsize);
+ chip->select_chip(chip, chipnr);
+
+ realpage = (int)(from / chip->pagesize);
+ page = realpage % chip->page_per_chip;
+ if (readlen == 0)
+ return 0;
+ if (NAND_HAS_CACHEREAD(chip) && (int)((from + readlen - 1) / chip->pagesize) > realpage)
+ enable_cache = true;
+
+ col = (int)(from & (chip->pagesize - 1));
+
+ buf = ops->readbuf;
+
+ while (1) {
+ bytes = MIN(chip->pagesize - col, readlen);
+ aligned = (bytes == chip->pagesize);
+ bufpoi = aligned ? buf : chip->databuf;
+
+ memset(chip->oob_poi, 0xff, chip->oobsize);
+
+ /* send read page command */
+ dprintf(INFO, "[nand] read page %d chip %d\n", page, chipnr);
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->enable_randomizer(chip, page, RAND_DECODE, 0);
+ #endif
+
+ if (!enable_cache || realpage == (int)(from / chip->pagesize))
+ chip->cmdfunc(chip, NAND_CMD_READ0, 0x00, page);
+
+ if (enable_cache) {
+ if ((readlen - bytes) == 0)
+ chip->cmdfunc(chip, NAND_CMD_READCACHELAST, -1, -1);
+ else
+ chip->cmdfunc(chip, NAND_CMD_READCACHESEQ, -1, -1);
+ }
+
+ if (!aligned) {
+ if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->read_subpage_ecc_dma_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->read_subpage_ecc_dma_polling(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->read_subpage_ecc_pio_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->read_subpage_ecc_pio_polling(chip, col, bytes, bufpoi, page);
+ } else {
+ if (ops->mode == NAND_OPS_RAW_DMA_IRQ)
+ ret = chip->read_page_raw_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_DMA_POLL)
+ ret = chip->read_page_raw_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_IRQ)
+ ret = chip->read_page_raw_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_POLL)
+ ret = chip->read_page_raw_pio_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->read_page_ecc_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->read_page_ecc_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->read_page_ecc_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->read_page_ecc_pio_polling(chip, bufpoi, page);
+ }
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->disable_randomizer(chip);
+ #endif
+ if (ret < 0)
+ break;
+
+ max_bitflips = MAX(max_bitflips, ret);
+
+ ret = mtk_nand_transfer_oob(chip, ops);
+ if (ret) {
+ max_bitflips = ret;
+ break;
+ }
+
+ if (chip->stats.failed - ecc_failures) {
+ ecc_fail = 1;
+ break;
+ }
+
+ if (!aligned)
+ memcpy(buf, chip->databuf + col, bytes);
+
+ readlen -= bytes;
+ buf += bytes;
+
+ if (!readlen)
+ break;
+
+ /* For subsequent reads align to page boundary */
+ col = 0;
+ /* Increment page address */
+ realpage++;
+
+ page = realpage % chip->page_per_chip;
+ /* Check, if we cross a chip boundary */
+ if (!page) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+ }
+ chip->select_chip(chip, -1);
+
+ if (ecc_fail)
+ return -EBADMSG;
+
+ return max_bitflips;
+}
+
+int mtk_nand_read(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret = 0;
+
+ mtk_nand_get_controller(chip);
+ if (chip->bIsPNAND) {
+ ret = mtk_nand_do_read_ops(chip, ops);
+ }
+#if MT2731_SUPPORT_SPI_NAND
+ else {
+ ret = mtk_snand_do_read_ops(chip, ops);
+ }
+#endif
+ mtk_nand_release_controller(chip);
+
+ return ret;
+}
+
+static int mtk_nand_fill_oob(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret = 0;
+ u32 parity_size;
+
+ parity_size = chip->oobsize - chip->oob_free_raw_size
+ - chip->oob_free_ecc_size;
+
+ memset(chip->oob_poi, 0xff, chip->oobsize);
+
+ if (ops->oobeccbuf && chip->fill_oob_ecc) {
+ if (ops->oobeccoffs >= chip->oob_free_ecc_size
+ || ops->oobecclen > chip->oob_free_ecc_size - ops->oobeccoffs)
+ return -EINVAL;
+ ret = chip->fill_oob_ecc(chip, ops->oobeccbuf, ops->oobeccoffs,
+ ops->oobecclen);
+ if (ret)
+ return ret;
+ }
+
+ if (ops->oobrawbuf && chip->fill_oob_raw) {
+ if (ops->oobrawoffs >= chip->oob_free_raw_size
+ || ops->oobrawlen > chip->oob_free_raw_size - ops->oobrawoffs)
+ return -EINVAL;
+ ret = chip->fill_oob_raw(chip, ops->oobrawbuf, ops->oobrawoffs,
+ ops->oobrawlen);
+ }
+
+ if (ops->oobparitybuf && chip->fill_oob_parity) {
+ if (ops->oobparityoffs >= parity_size
+ || ops->oobparitylen > parity_size - ops->oobparityoffs)
+ return -EINVAL;
+ ret = chip->fill_oob_parity(chip, ops->oobparitybuf, ops->oobparityoffs,
+ ops->oobparitylen);
+ }
+
+ return ret;
+}
+
+static int mtk_nand_do_write_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int chipnr, realpage, page, col, aligned;
+ u32 bytes, writelen = ops->len;
+ u64 to = ops->offset;
+ const u8 *buf = ops->writebuf;
+ const u8 *bufpoi;
+ int ret = 0, status, polling_wait = 1;
+ bool enable_cache = false;
+
+ /* Reject writes, which are not subpage aligned */
+ if (!IS_ALIGNED(to, chip->subpagesize) || !IS_ALIGNED(ops->len, chip->subpagesize)) {
+ dprintf(CRITICAL, "attempt to write non page aligned data (offset 0x%llx, len 0x%llx)\n", to, ops->len);
+ return -EINVAL;
+ }
+
+ col = to & (chip->pagesize - 1);
+ chipnr = (int)(to / chip->chipsize);
+ chip->select_chip(chip, chipnr);
+
+ /* Check, if it is write protected */
+ if (mtk_nand_check_wp(chip)) {
+ ret = -EIO;
+ dprintf(CRITICAL, "write protected!\n");
+ goto err_out;
+ }
+
+ realpage = (int)(to / chip->pagesize);
+ page = realpage % chip->page_per_chip;
+ if (NAND_HAS_CACHEPROG(chip) && (int)((to + writelen) / chip->pagesize) > realpage)
+ enable_cache = true;
+
+ while (1) {
+ bytes = MIN(chip->pagesize - col, writelen);
+ aligned = (bytes == chip->pagesize);
+ bufpoi = aligned ? buf : chip->databuf;
+
+ if (!aligned) {
+ memset(chip->databuf, 0xff, chip->pagesize);
+ memcpy(chip->databuf + col, buf, bytes);
+ }
+
+ ret = mtk_nand_fill_oob(chip, ops);
+ if (ret)
+ break;
+
+ dprintf(INFO, "[nand] write page %d chip %d\n", page, chipnr);
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->enable_randomizer(chip, page, RAND_ENCODE, 0);
+ #endif
+ chip->cmdfunc(chip, NAND_CMD_SEQIN, 0x00, page);
+
+ if (!aligned) {
+ if (ops->mode == NAND_OPS_ECC_DMA_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_subpage_ecc_dma_irq(chip, col, bytes, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->write_subpage_ecc_dma_polling(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_subpage_ecc_pio_irq(chip, col, bytes, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->write_subpage_ecc_pio_polling(chip, col, bytes, bufpoi, page);
+ }
+ else {
+ if (ops->mode == NAND_OPS_RAW_DMA_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_page_raw_dma_irq(chip, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_RAW_DMA_POLL)
+ ret = chip->write_page_raw_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_page_raw_pio_irq(chip, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_RAW_PIO_POLL)
+ ret = chip->write_page_raw_pio_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_page_ecc_dma_irq(chip, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->write_page_ecc_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ) {
+ polling_wait = 0;
+ ret = chip->write_page_ecc_pio_irq(chip, bufpoi, page);
+ }
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->write_page_ecc_pio_polling(chip, bufpoi, page);
+ }
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->disable_randomizer(chip);
+ #endif
+ if (ret < 0)
+ break;
+
+ if (!enable_cache || (writelen - bytes) == 0)
+ chip->cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
+ else
+ chip->cmdfunc(chip, NAND_CMD_CACHEDPROG, -1, -1);
+ status = chip->waitfunc(chip, polling_wait);
+ if (status & NAND_STATUS_FAIL) {
+ ret = -EIO;
+ dprintf(CRITICAL, "write failed at page 0x%x\n", realpage);
+ goto err_out;
+ }
+
+ writelen -= bytes;
+ if (!writelen)
+ break;
+
+ col = 0;
+ buf += bytes;
+ realpage++;
+
+ page = realpage % chip->page_per_chip;
+ /* Check, if we cross a chip boundary */
+ if (!page) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+ }
+
+err_out:
+ chip->select_chip(chip, -1);
+
+ return ret;
+}
+
+int mtk_nand_write(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret = 0;
+
+ mtk_nand_get_controller(chip);
+
+ if (chip->bIsPNAND) {
+ ret = mtk_nand_do_write_ops(chip, ops);
+ }
+#if MT2731_SUPPORT_SPI_NAND
+ else {
+ ret = mtk_snand_do_write_ops(chip, ops);
+ }
+#endif
+
+ mtk_nand_release_controller(chip);
+
+ return ret;
+}
+
+static int mtk_nand_do_erase_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops, int force_erase)
+{
+ u64 offset = ops->offset;
+ u64 eraselen = ops->len;
+ int page, status, ret = 0, chipnr, polling_wait = 0;
+
+ if ((offset % chip->blocksize) || (eraselen % chip->blocksize)) {
+ dprintf(CRITICAL, "erase is not aligned (off 0x%llx, len 0x%llx)\n", offset, eraselen);
+ return -EINVAL;
+ }
+
+ page = (int)(offset / chip->pagesize);
+ chipnr = (int)(offset / chip->chipsize);
+
+ chip->select_chip(chip, chipnr);
+
+ /* Check, if it is write protected */
+ if (mtk_nand_check_wp(chip)) {
+ ret = -EIO;
+ dprintf(CRITICAL, "write protected!\n");
+ goto err_out;
+ }
+
+ while (1) {
+ if (!force_erase && mtk_nand_block_isbad_lowlevel(chip, page)) {
+ ret = -EIO;
+ dprintf(CRITICAL, "attempt to erase bad block at page 0x%x\n", page);
+ goto err_out;
+ }
+
+ dprintf(INFO, "[nand] erase page %d chip %d\n", page, chipnr);
+ chip->cmdfunc(chip, NAND_CMD_ERASE1, -1, (page % chip->page_per_chip));
+ chip->cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
+ if (ops->mode == NAND_OPS_ERASE_IRQ)
+ polling_wait = 0;
+ else if (ops->mode == NAND_OPS_ERASE_POLL)
+ polling_wait = 1;
+ status = chip->waitfunc(chip, polling_wait);
+
+ if (status & NAND_STATUS_FAIL) {
+ ret = -EIO;
+ dprintf(CRITICAL, "erase failed at page 0x%x, status 0x%x\n",
+ page, status);
+ goto err_out;
+ }
+
+ eraselen -= chip->blocksize;
+ if (!eraselen)
+ break;
+ page += chip->page_per_block;
+
+ if (eraselen && !(page % chip->page_per_chip)) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+ }
+err_out:
+ chip->select_chip(chip, -1);
+
+ return ret;
+}
+
+int mtk_nand_erase(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret = 0;
+
+ mtk_nand_get_controller(chip);
+
+
+ if (chip->bIsPNAND) {
+ ret = mtk_nand_do_erase_ops(chip, ops, 0);
+ }
+#if MT2731_SUPPORT_SPI_NAND
+ else {
+ ret = mtk_snand_do_erase_ops(chip, ops);
+ }
+#endif
+
+ mtk_nand_release_controller(chip);
+
+ return ret;
+}
+
+int mtk_nand_force_erase(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int ret;
+
+ mtk_nand_get_controller(chip);
+ ret = mtk_nand_do_erase_ops(chip, ops, 1);
+ mtk_nand_release_controller(chip);
+
+ return ret;
+}
+
+int mtk_nand_init(void)
+{
+ return mtk_nfc_nand_chip_init(&nandchip);
+}
+
+void mtk_nand_deinit(void)
+{
+ u8 mask = 7;
+ u8 kernel_freq = (nandchip->freq_map & mask);
+
+ /* nfc re-set clock before enter kernel, setting freq from 'freq_map' at device table */
+ if (kernel_freq != 0) {
+ dprintf(ALWAYS, "[nand] deinit >>> CLK_CFG_5 0x%x\n", DRV_Reg32(CLK_CFG_5));
+ DRV_WriteReg32(CLK_CFG_5_CLR, mask << 24);
+ DRV_WriteReg32(CLK_CFG_5_SET, kernel_freq << 24);
+ DRV_WriteReg32(CLK_CFG_UPDATE, 0x1000000);
+ dprintf(ALWAYS, "[nand] deinit <<< CLK_CFG_5 0x%x\n", DRV_Reg32(CLK_CFG_5));
+
+ dprintf(ALWAYS, "[nand] deinit >>> NFI_ACCCON 0x%x\n", DRV_Reg32(NFI_BASE + NFI_ACCCON));
+ DRV_WriteReg32(NFI_BASE + NFI_ACCCON, 0xF3FFFFFF);
+ dprintf(ALWAYS, "[nand] deinit <<< NFI_ACCCON 0x%x\n", DRV_Reg32(NFI_BASE + NFI_ACCCON));
+ }
+}
+
+struct mtk_nand_chip *mtk_get_nand_chip(void)
+{
+ return nandchip;
+}
+
+int nand_get_device_id(u8 *id, u32 len)
+{
+ u8 id_data[len];
+ u32 idx = 0;
+ u8 status;
+ u32 timeout = MTK_RESET_TIMEOUT;
+
+ if (!id)
+ return -1;
+
+ if (len > 16)
+ len = 16;
+ else if(len == 0)
+ return -1;
+
+ DRV_WriteReg32(NFI_BASE + NFI_ACCCON, 0xF3FFFFFF);
+
+ /* Reset NFI & NAND */
+ DRV_WriteReg32(NFI_BASE + NFI_CMD, 0xFF);
+ while (DRV_Reg32(NFI_BASE + NFI_STA) & STA_CMD);
+
+ /* Reset NFI & read status */
+ do {
+ DRV_WriteReg32(NFI_BASE + NFI_CON, CON_NFI_RST | CON_FIFO_FLUSH);
+ DRV_WriteReg32(NFI_BASE + NFI_CNFG, CNFG_OP_SINGLE_READ | CNFG_READ_EN);
+ DRV_WriteReg32(NFI_BASE + NFI_CMD, NAND_CMD_STATUS);
+ DRV_WriteReg32(NFI_BASE + NFI_CON, CON_SRD | (1<<CON_NOB_SHIFT));
+ status = DRV_Reg32(NFI_BASE + NFI_DATAR);
+ if(status == 0x40)
+ break;
+ else
+ timeout--;
+ } while(timeout > 0);
+
+ /* Reset NFI & read ID*/
+ DRV_WriteReg32(NFI_BASE + NFI_CON, CON_NFI_RST | CON_FIFO_FLUSH);
+ DRV_WriteReg32(NFI_BASE + NFI_CNFG, CNFG_OP_SINGLE_READ |
+ CNFG_BYTE_RW | CNFG_READ_EN);
+ DRV_WriteReg32(NFI_BASE + NFI_CMD, NAND_CMD_READID);
+ while (DRV_Reg32(NFI_BASE + NFI_STA) & STA_CMD);
+ DRV_WriteReg32(NFI_BASE + NFI_COLADDR, 0);
+ DRV_WriteReg32(NFI_BASE + NFI_ROWADDR, 0);
+ DRV_WriteReg(NFI_BASE + NFI_ADDRNOB, 1);
+ while (DRV_Reg32(NFI_BASE + NFI_STA) & STA_ADDR);
+ DRV_SetReg32(NFI_BASE + NFI_CON, CON_SRD | (0<<CON_NOB_SHIFT));
+
+ for(idx=0; idx<len; idx++){
+ while(!(0x1 & (DRV_Reg(NFI_BASE + NFI_PIO_DIRDY))));
+ id_data[idx] = DRV_Reg32(NFI_BASE + NFI_DATAR);
+ dprintf(CRITICAL, "NANDID: 0x%x\n", id_data[idx]);
+ }
+
+ memcpy(id, id_data, len);
+
+ return 0;
+}
+
+/*****************************/
+/* MT2731 support SPI NAND */
+/*****************************/
+
+#if MT2731_SUPPORT_SPI_NAND
+
+
+static int mtk_snand_read_oob_raw(struct mtk_nand_chip *chip, uint8_t *buf,
+ int page_addr, int len)
+{
+ int bRet = 1;
+ u32 num_sec;
+ u32 i;
+
+ struct mtk_nand_ops ops;
+
+ num_sec = len / NFI_FDM_MAX_SIZE;
+
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = (u64)page_addr * chip->pagesize;
+ ops.len = chip->pagesize;
+ ops.readbuf = chip->databuf;
+
+ bRet = mtk_snand_do_read_ops(chip, &ops);
+
+ num_sec = num_sec * NFI_FDM_MAX_SIZE;
+ for (i = 0; i < num_sec; i++)
+ buf[i] = chip->databuf[i+chip->pagesize];
+
+ return bRet;
+}
+
+
+int snand_reset(struct mtk_nand_chip *chip, int chipnr)
+{
+ int ret;
+ u8 dev_status;
+ u8 cmd = SNAND_CMD_SW_RESET;
+
+ /* power on sequence delay */
+ //spin(300);
+ dprintf(CRITICAL, "%s\n", __func__);
+
+
+ /* Send the command for reading device ID */
+ chip->s_mode = SPI;
+ ret = chip->snand_cmd_ext(chip, &cmd, NULL, 1, 0);
+ if (!ret)
+ ret = chip->snand_wait_idel(chip, &dev_status);
+
+ return ret;
+}
+
+static int mtk_snand_do_read_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int chipnr, page, realpage, col, aligned;
+ u8 *buf, *bufpoi;
+ u64 readlen = ops->len, from = ops->offset;
+ u32 bytes, ecc_failures = chip->stats.failed;
+ int ret = 0, ecc_fail = 0, max_bitflips = 0;
+ //bool enable_cache = false;
+
+
+ chipnr = (int)(from / chip->chipsize);
+
+#if 1 // TT_NOTE: implement two die by select_chip
+ chip->select_chip(chip, chipnr);
+#endif
+
+ realpage = (int)(from / chip->pagesize);
+ page = realpage % chip->page_per_chip;
+ if (readlen == 0)
+ return 0;
+
+ //if (NAND_HAS_CACHEREAD(chip) && (int)((from + readlen - 1) / chip->pagesize) > realpage)
+ // enable_cache = true;
+
+ col = (int)(from & (chip->pagesize - 1));
+ buf = ops->readbuf;
+
+ while (1) {
+ bytes = MIN(chip->pagesize - col, readlen);
+ aligned = (bytes == chip->pagesize);
+ bufpoi = aligned ? buf : chip->databuf;
+
+ memset(chip->oob_poi, 0xff, chip->oobsize);
+
+ /* send read page command */
+ dprintf(INFO, "[snand] read page %d chip %d\n", page, chipnr);
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->enable_randomizer(chip, page, RAND_DECODE, 0);
+ #endif
+
+ /* SPI setting - DRAFT */
+ ret = chip->snand_pre_read(chip, col, bytes, page);
+
+ if (!aligned) {
+ if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->read_subpage_ecc_dma_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->read_subpage_ecc_dma_polling(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->read_subpage_ecc_pio_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->read_subpage_ecc_pio_polling(chip, col, bytes, bufpoi, page);
+ } else {
+ if (ops->mode == NAND_OPS_RAW_DMA_IRQ)
+ ret = chip->read_page_raw_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_DMA_POLL)
+ ret = chip->read_page_raw_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_IRQ)
+ ret = chip->read_page_raw_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_POLL)
+ ret = chip->read_page_raw_pio_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->read_page_ecc_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->read_page_ecc_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->read_page_ecc_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->read_page_ecc_pio_polling(chip, bufpoi, page);
+ }
+ //chip->disable_randomizer(chip);
+ if (ret < 0)
+ break;
+
+ max_bitflips = MAX(max_bitflips, ret);
+
+ ret = mtk_nand_transfer_oob(chip, ops);
+ if (ret) {
+ max_bitflips = ret;
+ break;
+ }
+
+ if (chip->stats.failed - ecc_failures) {
+ ecc_fail = 1;
+ break;
+ }
+
+ if (!aligned)
+ memcpy(buf, chip->databuf + col, bytes);
+
+ readlen -= bytes;
+ buf += bytes;
+
+ if (!readlen)
+ break;
+
+ /* For subsequent reads align to page boundary */
+ col = 0;
+ /* Increment page address */
+ realpage++;
+
+ page = realpage % chip->page_per_chip;
+ /* Check, if we cross a chip boundary */
+
+#if 0 // TT_NOTE: implement two die by select_chip
+ if (!page) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+#endif
+ }
+
+ if (ecc_fail)
+ return -EBADMSG;
+
+ return max_bitflips;
+}
+
+static int mtk_snand_do_write_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ int chipnr, realpage, page, col, aligned;
+ u32 bytes, writelen = ops->len;
+ u64 to = ops->offset;
+ const u8 *buf = ops->writebuf;
+ const u8 *bufpoi;
+ int ret = 0, status;
+ //bool enable_cache = false;
+
+ /* Reject writes, which are not subpage aligned */
+ if (!IS_ALIGNED(to, chip->subpagesize) || !IS_ALIGNED(ops->len, chip->subpagesize)) {
+ dprintf(CRITICAL, "attempt to write non page aligned data (offset 0x%llx, len 0x%llx)\n", to, ops->len);
+ return -EINVAL;
+ }
+
+ col = to & (chip->pagesize - 1);
+ chipnr = (int)(to / chip->chipsize);
+ chip->select_chip(chip, chipnr);
+
+ realpage = (int)(to / chip->pagesize);
+ page = realpage % chip->page_per_chip;
+ //if (NAND_HAS_CACHEPROG(chip) && (int)((to + writelen) / chip->pagesize) > realpage)
+ //enable_cache = true;
+
+ while (1) {
+ bytes = MIN(chip->pagesize - col, writelen);
+ aligned = (bytes == chip->pagesize);
+ bufpoi = aligned ? buf : chip->databuf;
+
+ if (!aligned) {
+ memset(chip->databuf, 0xff, chip->pagesize);
+ memcpy(chip->databuf + col, buf, bytes);
+ }
+
+ ret = mtk_nand_fill_oob(chip, ops);
+ if (ret)
+ break;
+
+ dprintf(INFO, "[snand] write page %d chip %d\n", page, chipnr);
+ #if MT2731_DISABLE_RANDOMIZER
+ chip->enable_randomizer(chip, page, RAND_ENCODE, 0);
+ #endif
+
+ ret = chip->snand_pre_write(chip, col, bytes, page);
+
+ if (!aligned) {
+ if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->write_subpage_ecc_dma_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->write_subpage_ecc_dma_polling(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->write_subpage_ecc_pio_irq(chip, col, bytes, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->write_subpage_ecc_pio_polling(chip, col, bytes, bufpoi, page);
+ }
+ else {
+ if (ops->mode == NAND_OPS_RAW_DMA_IRQ)
+ ret = chip->write_page_raw_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_DMA_POLL)
+ ret = chip->write_page_raw_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_IRQ)
+ ret = chip->write_page_raw_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_RAW_PIO_POLL)
+ ret = chip->write_page_raw_pio_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_IRQ)
+ ret = chip->write_page_ecc_dma_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_DMA_POLL)
+ ret = chip->write_page_ecc_dma_polling(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_IRQ)
+ ret = chip->write_page_ecc_pio_irq(chip, bufpoi, page);
+ else if (ops->mode == NAND_OPS_ECC_PIO_POLL)
+ ret = chip->write_page_ecc_pio_polling(chip, bufpoi, page);
+ }
+ //chip->disable_randomizer(chip);
+ if (ret < 0)
+ break;
+
+ status = chip->snand_post_write(chip, page);
+
+ if ((status & SNAND_STATUS_PROGRAM_FAIL) != 0) {
+ ret = -EIO;
+ dprintf(CRITICAL, "write failed at page 0x%x\n", realpage);
+ goto err_out;
+ }
+
+ writelen -= bytes;
+ if (!writelen)
+ break;
+
+ col = 0;
+ buf += bytes;
+ realpage++;
+
+ page = realpage % chip->page_per_chip;
+ /* Check, if we cross a chip boundary */
+
+#if 0 // TT_NOTE: implement two die by select_chip
+ if (!page) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+#endif
+ }
+
+err_out:
+ return ret;
+}
+
+static int mtk_snand_do_erase_ops(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops)
+{
+ u64 offset = ops->offset;
+ u64 eraselen = ops->len;
+ int page, status, ret = 0, chipnr;
+
+ if ((offset % chip->blocksize) || (eraselen % chip->blocksize)) {
+ dprintf(CRITICAL, "erase is not aligned (off 0x%llx, len 0x%llx)\n", offset, eraselen);
+ return -EINVAL;
+ }
+
+ page = (int)(offset / chip->pagesize);
+ chipnr = (int)(offset / chip->chipsize);
+ chip->select_chip(chip, chipnr);
+
+ while (1) {
+ if (mtk_nand_block_checkbad(chip, page)) {
+ ret = -EIO;
+ dprintf(CRITICAL, "attempt to erase bad block at page 0x%x\n", page);
+ goto err_out;
+ }
+
+ //dprintf(CRITICAL, "[snand] erase page %d chip %d\n", page, chipnr);
+
+ status = chip->snand_auto_erase(chip, page);
+ if (status & NAND_STATUS_FAIL) {
+ ret = -EIO;
+ dprintf(CRITICAL, "erase failed at page 0x%x\n", page);
+ goto err_out;
+ }
+
+ eraselen -= chip->blocksize;
+ if (!eraselen)
+ break;
+ page += chip->page_per_block;
+
+#if 0 // TT_NOTE: implement two die by select_chip
+ if (eraselen && !(page % chip->page_per_chip)) {
+ chipnr++;
+ chip->select_chip(chip, -1);
+ chip->select_chip(chip, chipnr);
+ }
+#endif
+ }
+err_out:
+
+ return ret;
+}
+
+
+static int mtk_snand_block_bad(struct mtk_nand_chip *chip, u64 ofs)
+{
+ int page_addr = (int)(ofs / chip->pagesize);
+ unsigned int page_per_block = chip->page_per_block;
+ unsigned char oob_buf[64];
+ u32 u4SecNum = chip->ecc_steps;
+ unsigned int offset = (u4SecNum - 1) * NFI_FDM_MAX_SIZE;
+
+ page_addr &= ~(page_per_block - 1);
+
+ if (mtk_snand_read_oob_raw(chip, oob_buf, page_addr, u4SecNum * NFI_FDM_MAX_SIZE)) {
+ dprintf(CRITICAL, "mtk_snand_read_oob_raw return error\n");
+ return 1;
+ }
+
+ if (oob_buf[offset] != 0xff) {
+ dprintf(CRITICAL, "%s Bad block at 0x%x (blk:%d), Badmark is 0x%x\n", __func__,
+ page_addr, page_addr / page_per_block, oob_buf[offset]);
+ return 1;
+ }
+
+ /* everything is OK, good block */
+ return 0;
+}
+
+static void mtk_snand_set_defaults(struct mtk_nand_chip *chip)
+{
+ /* chip_delay setup set 20us if not */
+ chip->chip_delay = 20;
+
+ /* bad block check */
+ chip->block_bad = mtk_snand_block_bad;
+
+ /* variable defalut value */
+ chip->badblockbits = 8;
+ chip->badblockpos = 0;
+
+ chip->activechip = -1;
+
+ return;
+}
+
+int mtk_snand_flash_get(struct mtk_nand_chip *chip, int maxchips)
+{
+ int i;
+ u8 cmd = SNAND_CMD_READ_ID;
+ u8 id_data[SNAND_FLASH_ID_LENGTH+1];
+ struct mtk_nand_flash_dev *type = snand_flash_devs;
+
+ dprintf(CRITICAL, "%s\n", __func__);
+
+ snand_reset(chip, 0);
+
+ // TT_NOTE: implement two die by select_chip
+ /* Select the device */
+ chip->select_chip(chip, 0);
+
+ /* Send the command for reading device ID */
+ chip->s_mode = SPI;
+ chip->snand_cmd_ext(chip, &cmd, id_data, 1, SNAND_FLASH_ID_LENGTH + 1);
+
+ /* Read entire ID string */
+ for (i = 0; i < 3; i++) {
+ dprintf(CRITICAL, "spi nand id[%d] [%x] \n", i, id_data[i]);
+ }
+
+ for (; type->name != NULL; type++) {
+ if (!strncmp((char const*)type->id, (char const*)(id_data+1), type->id_len)) {
+ dprintf(CRITICAL, "spi nand found [%s] \n", type->name);
+ break;
+ }
+ }
+
+ if (!type->name) {
+ return -ENODEV;
+ }
+
+ chip->numchips = 1;
+
+#if 0 // TT_NOTE: implement two die by select_chip
+ /* Check for a chip array */
+ for (i = 1; i < maxchips; i++) {
+ /* See comment in nand_get_flash_type for reset */
+ snand_reset(chip, i);
+
+ //chip->select_chip(chip, i);
+ /* Send the command for reading device ID */
+ chip->cmdfunc(chip, NAND_CMD_READID, 0x00, -1);
+ /* Read manufacturer and device IDs */
+ if (id_data[0] != chip->read_byte(chip) ||
+ id_data[1] != chip->read_byte(chip)) {
+ chip->select_chip(chip, -1);
+ break;
+ }
+ dprintf(ALWAYS, "chip %d is found\n", i);
+ chip->select_chip(chip, -1);
+ chip->numchips++;
+ }
+#endif
+
+ /* set nand chip parameters */
+ chip->pagesize = type->pagesize;
+ chip->oobsize = type->oobsize;
+ chip->bits_per_cell = type->bits_per_cell;
+ /* KB to B */
+ chip->chipsize = ((u64)type->chipsize) << 10;
+ chip->blocksize = type->erasesize;
+ chip->bbt_options |= type->bbt_options;
+ chip->options |= type->options;
+ chip->ecc_size = type->ecc_size;
+ chip->ecc_strength = type->ecc_strength;
+ chip->fdm_ecc_size = type->fdmeccsize;
+
+ chip->totalsize = chip->numchips * chip->chipsize;
+
+ chip->ecc_steps = chip->pagesize / chip->ecc_size;
+ if (nand_is_slc(chip)) {
+ if (chip->ecc_steps == 2)
+ chip->subpagesize = chip->pagesize / 2;
+ else if (chip->ecc_steps > 2)
+ chip->subpagesize = chip->pagesize / 4;
+ else
+ chip->subpagesize = chip->pagesize;
+ }
+ chip->page_per_block = chip->blocksize / chip->pagesize;
+ chip->page_per_chip = chip->chipsize / chip->pagesize;
+
+ chip->databuf = (u8 *)memalign(16, chip->pagesize + chip->oobsize);
+ if (!chip->databuf)
+ return -ENOMEM;
+ chip->oob_poi = chip->databuf + chip->pagesize;
+
+ return 0;
+}
+
+
+int mtk_snand_scan(struct mtk_nand_chip *chip, int maxchips)
+{
+ int ret;
+
+ /* Set the defaults */
+ mtk_snand_set_defaults(chip);
+
+ ret = mtk_snand_flash_get(chip, maxchips);
+ if (ret) {
+ dprintf(CRITICAL, "no nand device found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_snand_init(void)
+{
+ return mtk_snfc_nand_chip_init(&spinandchip);
+}
+
+struct mtk_nand_chip *mtk_get_snand_chip(void)
+{
+ return spinandchip;
+}
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nftl.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nftl.c
new file mode 100644
index 0000000..bafef6e
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_nftl.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <err.h>
+#include <errno.h>
+#include <lib/nftl.h>
+#include <malloc.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <pow2.h>
+#include <string.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mtk_bio_ioctl.h>
+
+struct mtk_nand_chip *chip;
+
+void TT_TEST_FUNC(struct nftl_info *info);
+
+
+static ssize_t nand_write(struct nftl_info *info, const void *buf, off_t offset,
+ ssize_t len)
+{
+ struct mtk_nand_ops ops;
+ int ret;
+ /* dprintf(CRITICAL, "%s - 0x%llx 0x%llx\n", __func__, (u64)offset, (u64)len); */
+
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ //ops.mode = NAND_OPS_ECC_PIO_POLL;
+ ops.offset = (u64)offset;
+ ops.len = (u64)len;
+ ops.writebuf = buf;
+
+ ret = mtk_nand_write(chip, &ops);
+
+ return (ret < 0) ? ret : len;
+}
+
+static ssize_t nand_read(struct nftl_info *info, void *buf, off_t offset,
+ ssize_t len)
+{
+ struct mtk_nand_ops ops;
+ int ret;
+ /* dprintf(CRITICAL, "%s - 0x%llx 0x%llx\n", __func__, (u64)offset, (u64)len); */
+
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ //ops.mode = NAND_OPS_ECC_PIO_POLL;
+ ops.offset = (u64)offset;
+ ops.len = (u64)len;
+ ops.readbuf = buf;
+
+ ret = mtk_nand_read(chip, &ops);
+
+ return (ret < 0) ? ret : len;
+}
+
+static ssize_t nand_erase(struct nftl_info *info, off_t offset, ssize_t len)
+{
+ struct mtk_nand_ops ops;
+ int ret;
+
+ /* dprintf(CRITICAL, "%s - 0x%llx 0x%llx\n", __func__, (u64)offset, (u64)len); */
+
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = (u64)offset;
+ ops.len = (u64)len;
+
+ ret = (ssize_t)mtk_nand_erase(chip, &ops);
+
+ return (ret < 0) ? ret : len;
+}
+
+static int nand_block_isbad(struct nftl_info *info, u32 page)
+{
+ return mtk_nand_block_isbad(chip, page);
+}
+
+static int nand_ioctl(struct nftl_info *info, int request, void *argp)
+{
+ int ret = 0;
+
+ switch (request) {
+ case BIO_IOCTL_QUERY_CAP_REWRITABLE:
+ ret = NO_ERROR;
+ *(void **)argp = (void *)false;
+ break;
+ default:
+ ret = ERR_INVALID_ARGS;
+ break;
+ }
+ return ret;
+}
+
+int nand_init_device(void)
+{
+ struct nftl_info *info;
+ int ret;
+
+ dprintf(CRITICAL, "nand_init_device !\n");
+
+ /* for now, default run Parallel NAND */
+ ret = mtk_nand_init();
+ if (ret) {
+ dprintf(CRITICAL, "nand device init error (%d)!\n", ret);
+ return ret;
+ }
+
+ chip = mtk_get_nand_chip();
+
+ info = nftl_add_master("nand0");
+ if (!info)
+ return -ENOMEM;
+
+ /* SPI already de-feature at mt2731 */
+#if 0 //MT2731_SUPPORT_SPI_NAND
+ ret = mtk_snand_init();
+ if (ret) {
+ dprintf(CRITICAL, "spi nand device init error (%d)!\n", ret);
+ return ret;
+ }
+
+ chip = mtk_get_snand_chip();
+
+ info = nftl_add_master("spi_nand0");
+ if (!info)
+ return -ENOMEM;
+#endif
+
+ info->erase_size = chip->blocksize;
+ info->write_size = chip->pagesize;
+ info->total_size = chip->totalsize;
+ info->block_isbad = nand_block_isbad;
+ info->read = nand_read;
+ info->write = nand_write;
+ info->erase = nand_erase;
+ info->ioctl = nand_ioctl;
+
+ ret = nftl_mount_bdev(info);
+
+ return ret;
+}
+
+void nand_dump_device_info(void)
+{
+ dprintf(ALWAYS, "chip size: %#llx B\n", chip->chipsize);
+ dprintf(ALWAYS, "block size: %u B\n", chip->blocksize);
+ dprintf(ALWAYS, "page size: %u B\n", chip->pagesize);
+ dprintf(ALWAYS, "oob size: %u B\n", chip->oobsize);
+ dprintf(ALWAYS, "bits per cell: %d\n", chip->bits_per_cell);
+ dprintf(ALWAYS, "ecc size: %d\n", chip->ecc_size);
+ dprintf(ALWAYS, "ecc strength: %d\n", chip->ecc_strength);
+ dprintf(ALWAYS, "all fdm ecc size: %d\n", chip->oob_free_ecc_size);
+ dprintf(ALWAYS, "all fdm raw size: %d\n", chip->oob_free_raw_size);
+}
+
+void nand_prepare_goto_kernel(void)
+{
+ mtk_nand_deinit();
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_test.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_test.c
new file mode 100644
index 0000000..562dc3c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nand_test.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <errno.h>
+#include <lib/bio.h>
+#include <lib/console.h>
+#include <lib/mempool.h>
+#include <platform.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <platform/nand/nand.h>
+#include <rand.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#if WITH_LIB_CONSOLE
+#define TEST_BUFFER_SIZE (0x80000)
+
+static void gen_rand_data(u8 *buf, size_t len)
+{
+ u32 i;
+
+ for (i = 0; i < len; i++)
+ buf[i] = (u8)rand();
+}
+
+static int compare_data(u8 *src, u8 *dest, size_t len)
+{
+ u32 i;
+
+ for (i = 0; i < len; i++) {
+ if (src[i] != dest[i]) {
+ printf("ERROR at %d: should be 0x%x, is 0x%x\n", i, src[i], dest[i]);
+ return ERR_IO;
+ }
+ }
+
+ return 0;
+}
+
+static int nand_speed_test(const char *device)
+{
+ int ret = 0;
+ u8 *wbuf, *rbuf;
+ bdev_t *dev;
+ ssize_t valid_total_size, left, test_size;
+ lk_bigtime_t delta_time, start_time;
+
+ dev = bio_open(device);
+ if (!dev) {
+ dev = bio_open_by_label(device);
+ if (!dev) {
+ printf("error opening block device: %s\n", device);
+ return ERR_NOT_FOUND;
+ }
+ }
+
+ wbuf = mempool_alloc(TEST_BUFFER_SIZE, MEMPOOL_ANY);
+ if (wbuf == NULL) {
+ ret = ERR_NO_MEMORY;
+ goto closedev;
+ }
+
+ rbuf = mempool_alloc(TEST_BUFFER_SIZE, MEMPOOL_ANY);
+ if (rbuf == NULL) {
+ ret = ERR_NO_MEMORY;
+ goto freewbuf;
+ }
+
+ gen_rand_data(wbuf, TEST_BUFFER_SIZE);
+
+ printf("begin erase test!\n");
+ delta_time = current_time_hires();
+ valid_total_size = bio_erase(dev, 0, dev->total_size);
+ delta_time = current_time_hires() - delta_time;
+ printf("erase speed is: %llu KB/s\n", (valid_total_size * 1000000) / (delta_time * 1024));
+
+ printf("begin write test!\n");
+ left = valid_total_size;
+ delta_time = current_time_hires();
+ while (left) {
+ test_size = MIN(TEST_BUFFER_SIZE, left);
+ ret = bio_write(dev, wbuf, valid_total_size - left, test_size);
+ if (ret < 0)
+ goto freerbuf;
+ left -= test_size;
+ };
+ delta_time = current_time_hires() - delta_time;
+ printf("write speed is: %llu KB/s\n", (valid_total_size * 1000000) / (delta_time * 1024));
+
+ printf("begin read test!\n");
+ left = valid_total_size;
+ delta_time = 0;
+ while (left) {
+ start_time = current_time_hires();
+ test_size = MIN(TEST_BUFFER_SIZE, left);
+ ret = bio_read(dev, rbuf, valid_total_size - left, test_size);
+ if (ret < 0)
+ goto freerbuf;
+ delta_time += current_time_hires() - start_time;
+ ret = compare_data(wbuf, rbuf, test_size);
+ if (ret < 0)
+ goto freerbuf;
+ left -= test_size;
+ }
+ printf("read speed is: %llu KB/s\n", (valid_total_size * 1000000) / (delta_time * 1024));
+
+freerbuf:
+ mempool_free(rbuf);
+freewbuf:
+ mempool_free(wbuf);
+closedev:
+ bio_close(dev);
+
+ return ret;
+}
+
+#define CBIT(v, n) ((v) & (1 << (n)))
+#define BCLR(v, n) ((v) = (v) & ~(1 << (n)))
+static u32 insert_biterrors(u32 byte, u32 boundary, u32 errors, u8 *buf)
+{
+ int bit;
+
+ while (byte < boundary && errors) {
+ for (bit = 7; bit >= 0; bit--) {
+ if (CBIT(buf[byte], bit)) {
+ BCLR(buf[byte], bit);
+ printf("%s: Inserted biterror @ %u/%u\n", __func__, byte, bit);
+ if (--errors == 0)
+ break;
+ }
+ }
+ byte++;
+ }
+
+ return errors;
+}
+
+static int nand_bit_errors_test(u32 page, u32 error_num)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ u8 *rbuf, *wbuf;
+ u32 buf_size, i, byte, parity_per_sector;
+ u32 parity_bytes = chip->ecc_strength * ECC_PARITY_BITS / 8 - 1;
+ u32 errs;
+ int ret;
+
+ /* error num 0 means full ecc strength */
+ if (error_num == 0)
+ error_num = chip->ecc_strength;
+ errs = error_num;
+
+ buf_size = chip->pagesize + chip->oobsize;
+
+ rbuf = mempool_alloc(buf_size, MEMPOOL_ANY);
+ if (rbuf == NULL)
+ return ERR_NO_MEMORY;
+ memset(rbuf, 0xff, buf_size);
+
+ wbuf = mempool_alloc(buf_size, MEMPOOL_ANY);
+ if (wbuf == NULL) {
+ ret = ERR_NO_MEMORY;
+ goto freerbuf;
+ }
+ memset(wbuf, 0xff, buf_size);
+
+ if (mtk_nand_block_isbad(chip, page)) {
+ printf("%s: page %u is bad!\n", __func__, page);
+ ret = ERR_FAULT;
+ goto freewbuf;
+ }
+
+ memset(&ops, 0, sizeof(ops));
+
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = (u64)page * chip->pagesize;
+ ops.len = (u64)chip->pagesize;
+ ops.readbuf = rbuf;
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0)
+ goto freewbuf;
+ printf("%s: max bit errors before rewrite: %d\n", __func__, ret);
+
+ memset(rbuf, 0xff, buf_size);
+ ops.mode = NAND_OPS_RAW_DMA_POLL;
+ ops.oobeccbuf = ops.readbuf + chip->pagesize;
+ ops.oobeccoffs = 0;
+ ops.oobecclen = chip->oob_free_ecc_size;
+ ops.oobrawbuf = ops.oobeccbuf + chip->oob_free_ecc_size;
+ ops.oobrawoffs = 0;
+ ops.oobrawlen = chip->oob_free_raw_size;
+ ops.oobparitybuf = ops.oobrawbuf + chip->oob_free_raw_size;
+ ops.oobparityoffs = 0;
+ ops.oobparitylen = chip->oobsize - chip->oob_free_ecc_size
+ - chip->oob_free_raw_size;
+ parity_per_sector = ops.oobparitylen / chip->ecc_steps;
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0)
+ goto freewbuf;
+ memcpy(wbuf, rbuf, chip->pagesize + chip->oobsize);
+
+ /* introduce deliberate bit errors */
+ for (i = 0; i < chip->ecc_steps; i++) {
+ errs = error_num;
+
+ /* one bit error in fdm data area */
+ printf("%s: sector %u insert fdm data area error\n", __func__, i);
+ byte = (u32)rand() % chip->fdm_ecc_size;
+ byte += i * chip->fdm_ecc_size;
+ ret = insert_biterrors(byte, (i + 1) * chip->fdm_ecc_size, 1,
+ ops.oobeccbuf);
+ errs -= (1 - ret);
+
+ if (errs == 0)
+ continue;
+
+ /* one bit error in parity data area */
+ printf("%s: sector %u insert parity data area error\n", __func__, i);
+ byte = (u32)rand() % parity_bytes;
+ byte += i * parity_per_sector;
+ ret = insert_biterrors(byte, (i + 1) * parity_per_sector, 1,
+ ops.oobparitybuf);
+
+ errs -= (1 - ret);
+
+ if (errs == 0)
+ continue;
+
+ /* error in main data area */
+ printf("%s: sector %u insert main data area error\n", __func__, i);
+ byte = (u32)rand() % chip->ecc_size;
+ byte += i * chip->ecc_size;
+ ret = insert_biterrors(byte, (i + 1) * chip->ecc_size, errs,
+ ops.readbuf);
+ errs -= (errs - ret);
+
+ if (errs)
+ printf("%s: sector %d insert errors not enough, left %u\n",
+ __func__, i, errs);
+ }
+
+ ops.writebuf = rbuf;
+ ret = mtk_nand_write(chip, &ops);
+ if (ret < 0)
+ goto freewbuf;
+
+ /* readback */
+ memset(rbuf, 0xff, chip->pagesize + chip->oobsize);
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.oobrawbuf = NULL;
+ ops.oobparitybuf = NULL;
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0)
+ goto freewbuf;
+ else
+ printf("%s: max bit errors after rewrite: %d\n", __func__, ret);
+
+ /* verify data */
+ for (i = 0; i < chip->pagesize + chip->oob_free_ecc_size; i++) {
+ if (wbuf[i] != rbuf[i]) {
+ printf("%s: byte %d is different: 0x%x != 0x%x, %p %p\n",
+ __func__, i, wbuf[i], rbuf[i], &wbuf[i], &rbuf[i]);
+ hexdump(rbuf, chip->pagesize + chip->oobsize);
+ ret = ERR_IO;
+ goto freewbuf;
+ }
+ }
+
+freewbuf:
+ mempool_free(wbuf);
+freerbuf:
+ mempool_free(rbuf);
+
+ printf("%s: %u bit errors test %s\n", __func__, error_num,
+ ret < 0 ? "Failed" : "OK");
+
+ return ret;
+}
+
+static int cmd_nand(int argc, const cmd_args *argv)
+{
+ int ret = 0;
+
+ if (argc < 2) {
+notenoughargs:
+ printf("not enough arguments:\n");
+usage:
+ printf("%s info\n", argv[0].str);
+ printf("%s list\n", argv[0].str);
+ printf("%s speedtest <device>\n", argv[0].str);
+ printf("%s biterrstest <page> <error num>\n", argv[0].str);
+ return -1;
+ }
+
+ if (!strcmp(argv[1].str, "info")) {
+ nand_dump_device_info();
+ } else if (!strcmp(argv[1].str, "list")) {
+ bio_dump_devices();
+ } else if (!strcmp(argv[1].str, "speedtest")) {
+ if (argc < 3) goto notenoughargs;
+
+ ret = nand_speed_test(argv[2].str);
+ } else if (!strcmp(argv[1].str, "biterrstest")) {
+ if (argc < 4) goto notenoughargs;
+
+ ret = nand_bit_errors_test(argv[2].u, argv[3].u);
+ } else {
+ printf("error: command %s not support\n", argv[1].str);
+ goto usage;
+ }
+
+ return ret;
+}
+
+STATIC_COMMAND_START
+STATIC_COMMAND("nand", "nand driver test & debug commands", &cmd_nand)
+STATIC_COMMAND_END(nand);
+
+#endif /* WITH_LIB_CONSOLE */
+
+
+#ifdef NAND_DEBUG
+void nand_show_bad(void)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ u32 page_max = chip->totalsize / chip->pagesize;
+ u32 page, is_bad, bad_count;
+
+ page = 0;
+ bad_count = 0;
+ while (page < page_max) {
+ is_bad = mtk_nand_block_isbad(chip, page);
+ if (is_bad) {
+ printf("bad block: %d, addr:0x%x\n", page / chip->page_per_block, page * chip->pagesize);
+ bad_count += is_bad;
+ }
+ page += chip->page_per_block;
+ }
+ printf("total bad block count: %d\n", bad_count);
+}
+
+void nand_erase_block(const char *arg, void *data, unsigned sz)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ u32 len = strlen(arg) + 1;
+ char *buf, *argument;
+ int block;
+ int ret;
+
+ buf = malloc(len);
+ if (!buf) {
+ printf("ERROR: no enough memory!");
+ return;
+ }
+ memset(buf, 0, len);
+ strcpy(buf, arg);
+ argument = strtok(buf, " ");
+ if (argument == NULL) {
+ printf("ERROR: the argument is invalid, argument format: [block]\n");
+ goto EXIT;
+ }
+ memset(&ops, 0, sizeof(ops));
+ ops.mode = NAND_OPS_ERASE_POLL;
+ if (!strncmp(argument, "all", 3)) {
+ ops.offset = 0;
+ ops.len = chip->totalsize;
+ printf("INFO: Erase all blocks\n");
+ } else {
+ block = atoi(argument);
+ if (block >= chip->totalsize / chip->blocksize) {
+ printf("ERROR: block(%d) number is not valid, totalsize:0x%llx, blocksize:0x%x\n",
+ block, chip->totalsize, chip->blocksize);
+ goto EXIT;
+ }
+
+ printf("INFO: block:%d\n", block);
+ ops.offset = block * chip->blocksize;
+ ops.len = chip->blocksize;
+ }
+ ret = mtk_nand_force_erase(chip, &ops);
+ if (ret < 0)
+ printf("ERROR: erase offset:0x%llx, len:0x%x, ret:%d\n", ops.offset, ops.len, ret);
+ else
+ printf("SUCCESS: erase offset:0x%llx, len:0x%x\n", ops.offset, ops.len);
+
+EXIT:
+ free(buf);
+}
+
+void nand_read_page(const char *arg, void *data, unsigned sz)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ u32 len = strlen(arg) + 1;
+ char *buf, *argument, *page_buf;
+ int page, i;
+ int ret;
+
+ buf = malloc(len);
+ if (!buf) {
+ printf("ERROR: no enough memory!");
+ return;
+ }
+ memset(buf, 0, len);
+ strcpy(buf, arg);
+
+ argument = strtok(buf, " ");
+ if (argument == NULL) {
+ printf("ERROR: the argument is invalid, argument format: [page]\n");
+ goto EXIT;
+ }
+ page = atoi(argument);
+ if (page < 0 || page >= chip->totalsize / chip->pagesize) {
+ printf("ERROR: page(%d) number is not valid\n", page);
+ goto EXIT;
+ }
+
+ printf("INFO: page:%d\n", page);
+
+ memset(&ops, 0, sizeof(ops));
+ page_buf = malloc(chip->pagesize);
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = page * chip->pagesize;
+ ops.len = chip->pagesize;
+ ops.readbuf = page_buf;
+
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0) {
+ printf("ERROR: read page(%d) fail, ret:%d\n", page, ret);
+ } else {
+ for (i = 0; i < chip->pagesize; i += 4) {
+ if ((i % 16) == 0) {
+ printf("\n%4x:", i);
+ }
+ printf(" %8x", *(u32 *)(page_buf + i));
+ }
+ }
+
+ free(page_buf);
+
+EXIT:
+ free(buf);
+}
+
+/**
+ * nand_write_page - write a page with assigned pattern
+ * @arg: arg from fastboot command
+ *
+ * arg format:
+ * <page> <pattern>
+ * page: page index of the NAND.
+ * pattern: 0x00 ~ 0xFF
+ *
+ */
+void nand_write_page(const char *arg, void *data, unsigned sz)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ u32 len = strlen(arg) + 1;
+ char *buf, *argument, *page_buf;
+ char pattern;
+ int page, i;
+ int ret;
+
+ buf = malloc(len);
+ if (!buf) {
+ printf("ERROR: no enough memory!");
+ return;
+ }
+ memset(buf, 0, len);
+ strcpy(buf, arg);
+
+ argument = strtok(buf, " ");
+ if (argument == NULL) {
+ printf("ERROR: the argument is invalid, argument format: [page] [pattern]\n");
+ goto EXIT;
+ }
+
+ page = atoi(argument);
+ if (page < 0 || page >= chip->totalsize / chip->pagesize) {
+ printf("ERROR: page(%d) number is not valid\n", page);
+ goto EXIT;
+ }
+ argument = strtok(NULL, " ");
+ if (argument == NULL) {
+ printf("ERROR: the argument is invalid, argument format: [page] [pattern]\n");
+ goto EXIT;
+ }
+ pattern = (char)atoi(argument);
+ printf("INFO: write 0x%x on page:%d\n", pattern, page);
+
+ memset(&ops, 0, sizeof(ops));
+ page_buf = malloc(chip->pagesize);
+ memset(page_buf, pattern, chip->pagesize);
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = page * chip->pagesize;
+ ops.len = chip->pagesize;
+ ops.writebuf = page_buf;
+
+ ret = mtk_nand_write(chip, &ops);
+ if (ret < 0) {
+ printf("ERROR: write page(%d) fail, ret:%d\n", page, ret);
+ } else {
+ memset(page_buf, 0, chip->pagesize);
+ ops.readbuf = page_buf;
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0) {
+ printf("ERROR: read page(%d) fail, ret:%d\n", page, ret);
+ } else {
+ for (i = 0; i < chip->pagesize; i++) {
+ if (page_buf[i] != pattern)
+ printf("ERROR: data[%d] = 0x%x is not pattern 0x%x\n", i, page_buf[i], pattern);
+ }
+ }
+ }
+
+ free(page_buf);
+
+EXIT:
+ free(buf);
+}
+
+/**
+ * nand_mark_block - mark a block as bad or good
+ * @arg: arg from fastboot command
+ *
+ * arg format:
+ * <block> <good/bad>
+ * block: block index of the NAND.
+ *
+ */
+void nand_mark_block(const char *arg, void *data, unsigned sz)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ u32 len = strlen(arg) + 1;
+ char *buf, *argument, *page_buf;
+ int block, i;
+ int ret;
+
+ buf = malloc(len);
+ if (!buf) {
+ printf("ERROR: no enough memory!");
+ return;
+ }
+ memset(buf, 0, len);
+ strcpy(buf, arg);
+ argument = strtok(buf, " ");
+ if (argument == NULL) {
+ printf("ERROR: the argument is invalid, argument format: [block] [good/bad]\n");
+ goto EXIT;
+ }
+ block = atoi(argument);
+ if ((block >= chip->totalsize / chip->blocksize) || (block < 0 && (block != -1))) {
+ printf("ERROR: block(%d) number is not valid\n", block);
+ goto EXIT;
+ }
+
+ argument = strtok(NULL, " ");
+ if (strncmp(argument, "good", 4) && strncmp(argument, "bad", 3)) {
+ printf("ERROR: the argument is invalid, argument format: [block] [good/bad]\n");
+ goto EXIT;
+ }
+ printf("INFO: mark block(%d) as %s\n", block, argument);
+
+ if (!strncmp(argument, "good", 4)) {
+ ret = mtk_nand_block_unmarkbad(chip, block * chip->page_per_block);
+ if (ret < 0)
+ printf("ERROR: Fail to mark block (%d) as good !!!\n", block);
+ else
+ printf("SUCCESS: mark block (%d) as good.\n", block);
+ } else {
+ ret = mtk_nand_block_markbad(chip, block * chip->page_per_block);
+ if (ret < 0)
+ printf("ERROR: Fail to mark block (%d) as bad fail!!!\n", block);
+ else
+ printf("SUCCESS: mark block (%d) as bad.\n", block);
+ }
+
+EXIT:
+ free(buf);
+}
+
+void nand_stress_test(void)
+{
+ struct mtk_nand_chip *chip = mtk_get_nand_chip();
+ struct mtk_nand_ops ops;
+ char *page_buf;
+ char pattern;
+ u64 offset;
+ int i;
+ int ret = 0;
+
+ for (offset = 0; offset < chip->totalsize; offset += chip->pagesize) {
+ if ((offset % chip->blocksize) == 0) {
+ ops.mode = NAND_OPS_ERASE_POLL;
+ ops.offset = offset;
+ ops.len = chip->blocksize;
+
+ ret = mtk_nand_erase(chip, &ops);
+ if (ret != 0)
+ printf("Fail to erase block(%lld), error(%d)\n", (u64)(offset / chip->blocksize), ret);
+ else
+ printf("Success to erase block(%lld)\n", (u64)(offset / chip->blocksize));
+ }
+
+ if (ret == 0) {
+ memset(&ops, 0, sizeof(ops));
+ page_buf = malloc(chip->pagesize);
+ pattern = rand() & 0xFF;
+ memset(page_buf, pattern, chip->pagesize);
+ ops.mode = NAND_OPS_ECC_DMA_POLL;
+ ops.offset = offset;
+ ops.len = chip->pagesize;
+ ops.writebuf = page_buf;
+
+ ret = mtk_nand_write(chip, &ops);
+ if (ret < 0) {
+ printf("Fail to write 0x%x on page(%lld), error:%d\n", pattern, offset / chip->pagesize, ret);
+ } else {
+ printf("Success to write 0x%x on page(%lld)\n", pattern, offset / chip->pagesize);
+ memset(page_buf, 0, chip->pagesize);
+ ops.readbuf = page_buf;
+ ret = mtk_nand_read(chip, &ops);
+ if (ret < 0) {
+ printf("Fail to read page(%lld), error:%d\n", offset / chip->pagesize, ret);
+ } else {
+ printf("Success to read page(%lld)\n", offset / chip->pagesize);
+ for (i = 0; i < chip->pagesize; i++) {
+ if (page_buf[i] != pattern) {
+ printf("ERROR: data[%d] = 0x%x is not pattern 0x%x\n", i, page_buf[i], pattern);
+ break;
+ }
+ }
+ if (i == chip->pagesize) {
+ printf("compare data pass~\n");
+ }
+ }
+ }
+
+ free(page_buf);
+ }
+ }
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nfi_hal.c b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nfi_hal.c
new file mode 100644
index 0000000..fc77d25
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/mtk_nfi_hal.c
@@ -0,0 +1,2662 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <arch/ops.h>
+#include <errno.h>
+#include <kernel/event.h>
+#include <kernel/mutex.h>
+#include <kernel/vm.h>
+#include <malloc.h>
+#include <platform/interrupts.h>
+#include <platform/mt_irq.h>
+#include <platform/mt_reg_base.h>
+#include <platform/nand/mtk_ecc_hal.h>
+#include <platform/nand/mtk_nand_common.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <platform/nand/mtk_nfi_hal.h>
+#include <reg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+/* add for setting clock */
+#include <platform/pll.h>
+
+static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct mtk_nand_chip *chip)
+{
+ return containerof(chip, struct mtk_nfc_nand_chip, chip);
+}
+
+static inline u8 *data_ptr(struct mtk_nand_chip *chip, const u8 *p, int i)
+{
+ return (u8 *)p + i * chip->ecc_size;
+}
+
+static inline int mtk_data_len(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+
+ return chip->ecc_size + mtk_nand->spare_per_sector;
+}
+
+static inline u8 *mtk_data_ptr(struct mtk_nand_chip *chip, int i)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ return nfc->buffer + i * mtk_data_len(chip);
+}
+
+static inline u8 *oob_ptr(struct mtk_nand_chip *chip, u32 i)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ u8 *poi;
+
+ /* map the sector's FDM data to free oob:
+ * the beginning of the oob area stores the FDM data of bad mark sectors
+ */
+ if (i < mtk_nand->bad_mark.sec)
+ poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
+ else if (i == mtk_nand->bad_mark.sec)
+ poi = chip->oob_poi;
+ else
+ poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
+
+ return poi;
+}
+
+static inline u8 *oob_parity_ptr(struct mtk_nand_chip *chip, u32 i)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ u32 parity_size = mtk_nand->spare_per_sector - mtk_nand->fdm.reg_size;
+ u32 fdm_total_size = mtk_nand->fdm.reg_size * chip->ecc_steps;
+ u8 *poi;
+
+ poi = chip->oob_poi + fdm_total_size;
+
+ if (i < mtk_nand->bad_mark.sec)
+ poi += (i + 1) * parity_size;
+ else if (i > mtk_nand->bad_mark.sec)
+ poi += i * parity_size;
+
+ return poi;
+}
+
+static inline u8 *mtk_oob_ptr(struct mtk_nand_chip *chip, int i)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ return nfc->buffer + i * mtk_data_len(chip) + chip->ecc_size;
+}
+
+static inline u8 *mtk_oob_parity_ptr(struct mtk_nand_chip *chip, int i)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+
+ return mtk_oob_ptr(chip, i) + mtk_nand->fdm.reg_size;
+}
+
+static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
+{
+ writel(val, nfc->regs + reg);
+
+ return;
+}
+
+static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
+{
+ (*REG16(nfc->regs + reg) = (val));
+
+ return;
+}
+
+static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
+{
+ writeb(val, nfc->regs + reg);
+
+ return;
+}
+
+static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
+{
+ return readl(nfc->regs + reg);
+}
+
+static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
+{
+ return *REG16(nfc->regs + reg);
+}
+
+static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
+{
+ return readb(nfc->regs + reg);
+}
+
+static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
+{
+ /* reset all registers and force the NFI master to terminate */
+ nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
+
+ /* wait for the master to finish the last transaction */
+ if (!check_with_timeout(!(nfi_readl(nfc, NFI_STA) & (NFI_FSM_MASK|NAND_FSM_MASK)),
+ MTK_RESET_TIMEOUT))
+ dprintf(CRITICAL, "NFI HW reset timeout! NFI_STA:0x%x\n", nfi_readl(nfc, NFI_STA));
+
+ /* ensure any status register affected by the NFI master is reset */
+ nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
+ nfi_writew(nfc, STAR_DE, NFI_STRDATA);
+
+ return;
+}
+
+static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
+{
+ nfi_writel(nfc, command, NFI_CMD);
+
+ if (!check_with_timeout(!(nfi_readl(nfc, NFI_STA) & STA_CMD), MTK_TIMEOUT))
+ dprintf(CRITICAL, "send cmd 0x%x timeout\n", command);
+
+ return 0;
+}
+
+static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
+{
+ nfi_writel(nfc, addr, NFI_COLADDR);
+ nfi_writel(nfc, 0, NFI_ROWADDR);
+ nfi_writew(nfc, 1, NFI_ADDRNOB);
+
+ if (!check_with_timeout(!(nfi_readl(nfc, NFI_STA) & STA_ADDR), MTK_TIMEOUT))
+ dprintf(CRITICAL, "send addr 0x%x timeout\n", addr);
+
+ return 0;
+}
+
+static int mtk_nfc_irq_wait(struct mtk_nfc *nfc, lk_time_t timeout)
+{
+ int ret;
+
+ ret = event_wait_timeout(&nfc->irq_event, timeout);
+ if (ret != 0) {
+ dprintf(CRITICAL, "[%s]: failed to get event INT=0x%x\n",
+ __func__, nfi_readw(nfc, NFI_INTR_EN));
+ return ret;
+ }
+
+ return 0;
+}
+
+static enum handler_return mtk_nfc_interrupt_handler(void *arg)
+{
+ struct mtk_nfc *nfc = arg;
+ u16 sta, ien;
+
+ sta = nfi_readw(nfc, NFI_INTR_STA);
+ ien = nfi_readw(nfc, NFI_INTR_EN);
+ if (!(sta & ien))
+ return INT_NO_RESCHEDULE;
+
+ nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
+
+ /* MUST BE *false*! otherwise, schedule in interrupt */
+ event_signal(&nfc->irq_event, false);
+
+ return INT_RESCHEDULE;
+}
+
+static int mtk_nfc_request_irq(struct mtk_nfc *nfc)
+{
+ mt_irq_set_sens(NFI_IRQ_BIT_ID, LEVEL_SENSITIVE);
+ mt_irq_set_polarity(NFI_IRQ_BIT_ID, MT65xx_POLARITY_LOW);
+ event_init(&nfc->irq_event, false, EVENT_FLAG_AUTOUNSIGNAL);
+ register_int_handler(NFI_IRQ_BIT_ID, mtk_nfc_interrupt_handler, nfc);
+ unmask_interrupt(NFI_IRQ_BIT_ID);
+
+ return 0;
+}
+
+static int mtk_nfc_hw_runtime_config(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ u32 fmt, spare;
+
+ if (!chip->pagesize)
+ return -EINVAL;
+
+ spare = mtk_nand->spare_per_sector;
+
+ switch (chip->pagesize) {
+ case 512:
+ fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
+ break;
+ case KB(2):
+ if (chip->ecc_size == 512)
+ fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
+ else
+ fmt = PAGEFMT_512_2K;
+ break;
+ case KB(4):
+ if (chip->ecc_size == 512)
+ fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
+ else
+ fmt = PAGEFMT_2K_4K;
+ break;
+ case KB(8):
+ if (chip->ecc_size == 512)
+ fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
+ else
+ fmt = PAGEFMT_4K_8K;
+ break;
+ case KB(16):
+ fmt = PAGEFMT_8K_16K;
+ break;
+ default:
+ dprintf(CRITICAL, "invalid page len: %d\n", chip->pagesize);
+ return -EINVAL;
+ }
+
+ /*
+ * the hardware will double the value for this eccsize, so we need to
+ * halve it
+ */
+ if (chip->ecc_size == 1024)
+ spare >>= 1;
+
+ switch (spare) {
+ case 16:
+ fmt |= (PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 26:
+ fmt |= (PAGEFMT_SPARE_26 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 27:
+ fmt |= (PAGEFMT_SPARE_27 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 28:
+ fmt |= (PAGEFMT_SPARE_28 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 32:
+ fmt |= (PAGEFMT_SPARE_32 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 36:
+ fmt |= (PAGEFMT_SPARE_36 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 40:
+ fmt |= (PAGEFMT_SPARE_40 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 44:
+ fmt |= (PAGEFMT_SPARE_44 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 48:
+ fmt |= (PAGEFMT_SPARE_48 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 49:
+ fmt |= (PAGEFMT_SPARE_49 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 50:
+ fmt |= (PAGEFMT_SPARE_50 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 51:
+ fmt |= (PAGEFMT_SPARE_51 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 52:
+ fmt |= (PAGEFMT_SPARE_52 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 62:
+ fmt |= (PAGEFMT_SPARE_62 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 63:
+ fmt |= (PAGEFMT_SPARE_63 << PAGEFMT_SPARE_SHIFT);
+ break;
+ case 64:
+ fmt |= (PAGEFMT_SPARE_64 << PAGEFMT_SPARE_SHIFT);
+ break;
+ default:
+ dprintf(CRITICAL, "invalid spare per sector %d\n", spare);
+ return -EINVAL;
+ }
+
+ fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
+ fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
+ nfi_writel(nfc, fmt, NFI_PAGEFMT);
+
+ nfc->ecc_cfg.strength = chip->ecc_strength;
+ nfc->ecc_cfg.len = chip->ecc_size + mtk_nand->fdm.ecc_size;
+
+ return 0;
+}
+
+static void mtk_nfc_select_chip(struct mtk_nand_chip *chip, int chip_num)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ if ((chip_num < 0) || (chip_num == chip->activechip))
+ return;
+
+ if (!mtk_nfc_hw_runtime_config(chip)) {
+ chip->activechip = chip_num;
+ }
+
+ nfi_writel(nfc, chip_num, NFI_CSEL);
+
+ return;
+}
+
+static int mtk_nfc_dev_ready(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
+ return 0;
+
+ return 1;
+}
+
+static int mtk_nfc_wait_busy_irq(struct mtk_nand_chip *chip)
+{
+ int ret;
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ /* set wait busy interrupt */
+ nfi_writew(nfc, INTR_BUSY_RETURN_EN, NFI_INTR_EN);
+
+ /* wait interrupt */
+ ret = mtk_nfc_irq_wait(nfc, MTK_TIMEOUT);
+ if (!ret) {
+ dprintf(CRITICAL, "wait busy interrupt timeout\n");
+ nfi_writew(nfc, 0, NFI_INTR_EN);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void mtk_nfc_cmd_ctrl(struct mtk_nand_chip *chip, int dat, unsigned int ctrl)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u16 reg;
+
+ if (ctrl & NAND_ALE) {
+ mtk_nfc_send_address(nfc, dat);
+ } else if (ctrl & NAND_CLE) {
+ mtk_nfc_hw_reset(nfc);
+
+ reg = nfi_readw(nfc, NFI_CNFG);
+ reg &= CNFG_RAND_MASK;
+ reg |= CNFG_OP_CUST;
+ nfi_writew(nfc, reg, NFI_CNFG);
+ mtk_nfc_send_command(nfc, dat);
+ }
+
+ return;
+}
+
+static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
+{
+ if (!check_with_timeout((nfi_readl(nfc, NFI_PIO_DIRDY) & PIO_DI_RDY), MTK_TIMEOUT)) {
+ dprintf(CRITICAL, "data not ready\n");
+ dprintf(CRITICAL, "cntr 0x%x cnfg 0x%x fmt 0x%x con 0x%x\n", nfi_readl(nfc, NFI_BYTELEN),
+ nfi_readl(nfc, NFI_CNFG), nfi_readl(nfc, NFI_PAGEFMT), nfi_readl(nfc, NFI_CON));
+ }
+
+ return;
+}
+
+static inline u8 mtk_nfc_read_byte(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 reg;
+
+ /* after each byte read, the NFI_STA reg is reset by the hardware */
+ reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
+ if (reg != NFI_FSM_CUSTDATA) {
+ reg = nfi_readw(nfc, NFI_CNFG);
+ reg |= CNFG_BYTE_RW | CNFG_READ_EN;
+ nfi_writew(nfc, reg, NFI_CNFG);
+
+ /*
+ * set to max sector to allow the HW to continue reading over
+ * unaligned accesses
+ */
+ reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
+ nfi_writel(nfc, reg, NFI_CON);
+
+ /* trigger to fetch data */
+ nfi_writew(nfc, STAR_EN, NFI_STRDATA);
+ }
+
+ mtk_nfc_wait_ioready(nfc);
+
+ return nfi_readb(nfc, NFI_DATAR);
+}
+
+static void mtk_nfc_read_buf(struct mtk_nand_chip *chip, u8 *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ buf[i] = mtk_nfc_read_byte(chip);
+
+ return;
+}
+
+static void mtk_nfc_write_byte(struct mtk_nand_chip *chip, u8 byte)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 reg;
+
+ reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
+
+ if (reg != NFI_FSM_CUSTDATA) {
+ reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
+ nfi_writew(nfc, reg, NFI_CNFG);
+
+ reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
+ nfi_writel(nfc, reg, NFI_CON);
+
+ nfi_writew(nfc, STAR_EN, NFI_STRDATA);
+ }
+
+ mtk_nfc_wait_ioready(nfc);
+ nfi_writeb(nfc, byte, NFI_DATAW);
+
+ return;
+}
+
+static void mtk_nfc_write_buf(struct mtk_nand_chip *chip, const u8 *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ mtk_nfc_write_byte(chip, buf[i]);
+
+ return;
+}
+
+static int mtk_nfc_sector_encode(struct mtk_nand_chip *chip, u8 *data, int dma, int polling)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ int size = chip->ecc_size + mtk_nand->fdm.reg_size;
+
+ if (dma)
+ nfc->ecc_cfg.mode = ECC_DMA_MODE;
+ else
+ nfc->ecc_cfg.mode = ECC_PIO_MODE;
+ nfc->ecc_cfg.op = ECC_ENCODE;
+
+ return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size, polling);
+}
+
+static void mtk_nfc_no_bad_mark_swap(struct mtk_nand_chip *a, u8 *b, int c)
+{
+ /* nop */
+ return;
+}
+
+static void mtk_nfc_bad_mark_swap(struct mtk_nand_chip *chip, u8 *buf, int raw)
+{
+ struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
+ u32 bad_pos = nand->bad_mark.pos;
+
+ if (raw)
+ bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
+ else
+ bad_pos += nand->bad_mark.sec * chip->ecc_size;
+
+ swap(chip->oob_poi[0], buf[bad_pos]);
+
+ return;
+}
+
+static int mtk_nfc_format_subpage(struct mtk_nand_chip *chip, u32 offset,
+ u32 len, const u8 *buf, int dma, int polling)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 start, end, i;
+ int ret;
+
+ start = offset / chip->ecc_size;
+ end = DIV_ROUND_UP(offset + len, chip->ecc_size);
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), chip->ecc_size);
+
+ if (start > i || i >= end)
+ continue;
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
+
+ /* program the CRC back to the OOB */
+ ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i), dma, polling);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mtk_nfc_format_page(struct mtk_nand_chip *chip, const u8 *buf)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 parity_size = mtk_nand->spare_per_sector - fdm->reg_size;
+ u32 i;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ for (i = 0; i < chip->ecc_steps; i++) {
+ if (buf)
+ memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
+ chip->ecc_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
+ memcpy(mtk_oob_parity_ptr(chip, i), oob_parity_ptr(chip, i),
+ parity_size);
+ }
+
+ return;
+}
+
+static inline void mtk_nfc_read_fdm(struct mtk_nand_chip *chip, u32 start,
+ u32 sectors)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 vall, valm, i, j;
+ u8 *oobptr;
+
+ for (i = 0; i < sectors; i++) {
+ oobptr = oob_ptr(chip, start + i);
+ vall = nfi_readl(nfc, NFI_FDML(i));
+ valm = nfi_readl(nfc, NFI_FDMM(i));
+
+ for (j = 0; j < fdm->reg_size; j++)
+ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
+ }
+
+ return;
+}
+
+static inline void mtk_nfc_write_fdm(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 vall, valm, i, j;
+ u8 *oobptr;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ oobptr = oob_ptr(chip, i);
+ vall = 0;
+ valm = 0;
+ for (j = 0; j < 8; j++) {
+ if (j < 4)
+ vall |= (j < fdm->reg_size ? oobptr[j] : 0xff)
+ << (j * 8);
+ else
+ valm |= (j < fdm->reg_size ? oobptr[j] : 0xff)
+ << ((j - 4) * 8);
+ }
+ nfi_writel(nfc, vall, NFI_FDML(i));
+ nfi_writel(nfc, valm, NFI_FDMM(i));
+ }
+
+ return;
+}
+
+static int mtk_nfc_do_write_page(struct mtk_nand_chip *chip,
+ const u8 *buf, int page, int len, int raw, int dma, int polling)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 *buf32 = (u32 *)buf;
+ uintptr_t addr;
+ u32 reg, i;
+ u32 data_len = chip->ecc_size;
+ int ret = 0, byterw;
+
+#ifdef WITH_KERNEL_VM
+ addr = (uintptr_t)kvaddr_to_paddr((void *)buf);
+#else
+ addr = (uintptr_t)buf;
+#endif
+
+ if (dma) {
+ reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
+ nfi_writew(nfc, reg, NFI_CNFG);
+ arch_clean_cache_range((addr_t)buf, (size_t)len);
+ }
+ nfi_writel(nfc, chip->ecc_steps << CON_SEC_SHIFT, NFI_CON);
+ nfi_writel(nfc, (u32)addr, NFI_STRADDR);
+
+ if (dma && (!polling)) {
+ nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
+ }
+
+#if MT2731_SUPPORT_SPI_NAND
+ if (!chip->bIsPNAND)
+ mtk_nfc_send_command(nfc, NAND_CMD_SEQIN);
+#endif
+
+ reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
+ nfi_writel(nfc, reg, NFI_CON);
+ nfi_writew(nfc, STAR_EN, NFI_STRDATA);
+
+ if (!dma) {
+ if (raw)
+ data_len = mtk_data_len(chip);
+ data_len *= chip->ecc_steps;
+
+ if (data_len & 0x3) {
+ reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
+ nfi_writew(nfc, reg, NFI_CNFG);
+ byterw = 1;
+ } else {
+ data_len >>= 2;
+ byterw = 0;
+ }
+
+ for (i = 0; i < data_len; i++) {
+ mtk_nfc_wait_ioready(nfc);
+ if (!byterw)
+ nfi_writel(nfc, buf32[i],NFI_DATAW);
+ else
+ nfi_writeb(nfc, buf[i], NFI_DATAW);
+ }
+ }
+
+ if (dma && (!polling)) {
+ ret = mtk_nfc_irq_wait(nfc, MTK_TIMEOUT);
+ if (!ret) {
+ dprintf(CRITICAL, "program ahb done timeout\n");
+ nfi_writew(nfc, 0, NFI_INTR_EN);
+ ret = -ETIMEDOUT;
+ goto timeout;
+ }
+ }
+
+ if (!check_with_timeout(ADDRCNTR_SEC(nfi_readl(nfc, NFI_ADDRCNTR)) >= chip->ecc_steps, MTK_TIMEOUT))
+ dprintf(CRITICAL, "do page write timeout\n");
+
+timeout:
+ if (dma)
+ arch_invalidate_cache_range((addr_t)buf, (size_t)len);
+
+ nfi_writel(nfc, 0, NFI_CON);
+
+ return ret;
+}
+
+static int mtk_nfc_write_page(struct mtk_nand_chip *chip,
+ const u8 *buf, int page, int raw, int dma, int polling)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ u32 len;
+ const u8 *bufpoi;
+ u32 reg;
+ int ret;
+
+ if (!raw) {
+ /* OOB => FDM: from register, ECC: from HW */
+ reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
+ nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
+
+ nfc->ecc_cfg.op = ECC_ENCODE;
+ nfc->ecc_cfg.mode = ECC_NFI_MODE;
+ ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg, polling);
+ if (ret) {
+ /* clear NFI config */
+ reg = nfi_readw(nfc, NFI_CNFG);
+ reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
+ nfi_writew(nfc, reg, NFI_CNFG);
+
+ return ret;
+ }
+
+ memcpy(nfc->buffer, buf, chip->pagesize);
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, raw);
+ bufpoi = nfc->buffer;
+
+ /* write OOB into the FDM registers (OOB area in MTK NAND) */
+ mtk_nfc_write_fdm(chip);
+ } else {
+ bufpoi = buf;
+ }
+
+ len = chip->pagesize + (raw ? chip->oobsize : 0);
+ ret = mtk_nfc_do_write_page(chip, bufpoi, page, len, raw, dma, polling);
+
+ if (!raw)
+ mtk_ecc_disable(nfc->ecc);
+
+ return ret;
+}
+
+static int mtk_nfc_write_page_ecc_dma_polling(struct mtk_nand_chip *chip, const u8 *buf,
+ int page)
+{
+ return mtk_nfc_write_page(chip, buf, page, 0, 1, 1);
+}
+
+static int mtk_nfc_write_page_ecc_dma_irq(struct mtk_nand_chip *chip, const u8 *buf,
+ int page)
+{
+ return mtk_nfc_write_page(chip, buf, page, 0, 1, 0);
+}
+
+static int mtk_nfc_write_page_ecc_pio_polling(struct mtk_nand_chip *chip, const u8 *buf,
+ int page)
+{
+ return mtk_nfc_write_page(chip, buf, page, 0, 0, 1);
+}
+
+static int mtk_nfc_write_page_ecc_pio_irq(struct mtk_nand_chip *chip, const u8 *buf,
+ int page)
+{
+ return mtk_nfc_write_page(chip, buf, page, 0, 0, 0);
+}
+
+static int mtk_nfc_write_page_raw_dma_polling(struct mtk_nand_chip *chip,
+ const u8 *buf, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mtk_nfc_format_page(chip, buf);
+ return mtk_nfc_write_page(chip, nfc->buffer, pg, 1, 1, 1);
+}
+
+static int mtk_nfc_write_page_raw_dma_irq(struct mtk_nand_chip *chip,
+ const u8 *buf, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mtk_nfc_format_page(chip, buf);
+ return mtk_nfc_write_page(chip, nfc->buffer, pg, 1, 1, 0);
+}
+
+static int mtk_nfc_write_page_raw_pio_polling(struct mtk_nand_chip *chip,
+ const u8 *buf, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mtk_nfc_format_page(chip, buf);
+ return mtk_nfc_write_page(chip, nfc->buffer, pg, 1, 0, 1);
+}
+
+static int mtk_nfc_write_page_raw_pio_irq(struct mtk_nand_chip *chip,
+ const u8 *buf, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mtk_nfc_format_page(chip, buf);
+ return mtk_nfc_write_page(chip, nfc->buffer, pg, 1, 0, 0);
+}
+
+static int mtk_nfc_write_subpage_ecc_dma_polling(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int ret;
+
+ ret = mtk_nfc_format_subpage(chip, offset, data_len, buf, 1, 1);
+ if (ret < 0)
+ return ret;
+
+ /* use the data in the private buffer (now with FDM and CRC) */
+ return mtk_nfc_write_page(chip, nfc->buffer, page, 1, 1, 1);
+}
+
+static int mtk_nfc_write_subpage_ecc_dma_irq(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int ret;
+
+ ret = mtk_nfc_format_subpage(chip, offset, data_len, buf, 1, 0);
+ if (ret < 0)
+ return ret;
+
+ /* use the data in the private buffer (now with FDM and CRC) */
+ return mtk_nfc_write_page(chip, nfc->buffer, page, 1, 1, 0);
+}
+
+static int mtk_nfc_write_subpage_ecc_pio_polling(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int ret;
+
+ ret = mtk_nfc_format_subpage(chip, offset, data_len, buf, 0, 1);
+ if (ret < 0)
+ return ret;
+
+ /* use the data in the private buffer (now with FDM and CRC) */
+ return mtk_nfc_write_page(chip, nfc->buffer, page, 1, 0, 1);
+}
+
+static int mtk_nfc_write_subpage_ecc_pio_irq(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int ret;
+
+ ret = mtk_nfc_format_subpage(chip, offset, data_len, buf, 0, 0);
+ if (ret < 0)
+ return ret;
+
+ /* use the data in the private buffer (now with FDM and CRC) */
+ return mtk_nfc_write_page(chip, nfc->buffer, page, 1, 0, 0);
+}
+
+static int mtk_nfc_update_ecc_stats(struct mtk_nand_chip *chip, u8 *buf, u32 sectors)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_ecc_stats stats;
+ u32 rc, i;
+#if MT2731_SUPPORT_SPI_NAND
+ u32 decfer_mask = ((1<<sectors)-1);
+#endif
+
+ /* Only Parallel NAND : will check empty flag and make fake buffer */
+ rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
+ if (rc) {
+#if MT2731_SUPPORT_SPI_NAND
+ if (!chip->bIsPNAND)
+ dprintf(CRITICAL, " Warnning : SPI should not enter here ... CHECK IT !! 0x%x\n", rc);
+#endif
+ memset(buf, 0xff, sectors * chip->ecc_size);
+ for (i = 0; i < sectors; i++)
+ memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
+ return 0;
+ }
+
+ mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
+
+#if MT2731_SUPPORT_SPI_NAND
+ /* Only SPI NAND : use DECFER and Error Num to check empty page */
+ if ((!chip->bIsPNAND) && (0 == stats.corrected) &&
+ (decfer_mask == (readl(nfc->ecc->regs + ECC_DECFER) & decfer_mask))) {
+ dprintf(CRITICAL, "SPI : DMA mode page is empty\n");
+ memset(buf, 0xff, sectors * chip->ecc_size);
+ for (i = 0; i < sectors; i++)
+ memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
+ return 0;
+ }
+#endif
+
+ chip->stats.corrected += stats.corrected;
+ chip->stats.failed += stats.failed;
+
+ return stats.bitflips;
+}
+
+static int mtk_nfc_read_subpage(struct mtk_nand_chip *chip,
+ u32 data_offs, u32 readlen,
+ u8 *bufpoi, int page, int raw, int dma, int polling)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_ecc_stats stats;
+ u32 spare = mtk_nand->spare_per_sector;
+ u32 column, sectors, start, end, reg;
+ uintptr_t addr;
+ u32 i, j;
+ int bitflips = 0;
+ u32 len, correct = 0, fail = 0;
+ u8 *buf;
+ u32 *buf32;
+ u32 data_len = chip->ecc_size;
+#if MT2731_SUPPORT_SPI_NAND
+ u32 decfer_mask;
+#endif
+ int rc, byterw;
+
+ start = data_offs / chip->ecc_size;
+ end = DIV_ROUND_UP(data_offs + readlen, chip->ecc_size);
+
+ sectors = end - start;
+ column = start * (chip->ecc_size + spare);
+
+ len = sectors * chip->ecc_size + ((raw || !dma) ? sectors * spare : 0);
+ buf = bufpoi + start * (chip->ecc_size + ((raw || !dma) ? sectors * spare : 0));
+ buf32 = (u32 *)buf;
+
+ //dprintf(CRITICAL, "%s - data_offs 0x%x readlen 0x%x page %d raw %d dma %d polling %d\n",
+ // __func__, data_offs, readlen, page, raw, dma, polling);
+
+ if ((column != 0) && (chip->bIsPNAND))
+ chip->cmdfunc(chip, NAND_CMD_RNDOUT, column, -1);
+
+#ifdef WITH_KERNEL_VM
+ addr = (uintptr_t)kvaddr_to_paddr(buf);
+#else
+ addr = (uintptr_t)buf;
+#endif
+
+ reg = nfi_readw(nfc, NFI_CNFG);
+ reg |= CNFG_READ_EN;
+ if (dma)
+ reg |= CNFG_DMA_BURST_EN | CNFG_AHB;
+ if (!raw) {
+ reg |= CNFG_HW_ECC_EN;
+ if (dma)
+ reg |= CNFG_AUTO_FMT_EN;
+ nfi_writew(nfc, reg, NFI_CNFG);
+
+ nfc->ecc_cfg.mode = ECC_NFI_MODE;
+ nfc->ecc_cfg.sectors = sectors;
+ nfc->ecc_cfg.op = ECC_DECODE;
+ if (dma) {
+ nfc->ecc_cfg.deccon = ECC_DEC_CORRECT;
+ } else {
+ nfc->ecc_cfg.deccon = ECC_DEC_LOCATE;
+ }
+ rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg, polling);
+ if (rc) {
+ dprintf(CRITICAL, "ecc enable failed\n");
+ /* clear NFI_CNFG */
+ reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
+ CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
+ nfi_writew(nfc, reg, NFI_CNFG);
+
+ return rc;
+ }
+ } else {
+ nfi_writew(nfc, reg, NFI_CNFG);
+ }
+
+ if (dma)
+ arch_invalidate_cache_range((addr_t)buf, (size_t)len);
+ nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
+ nfi_writel(nfc, (u32)addr, NFI_STRADDR);
+
+ if (dma && (!polling)) {
+ nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
+ }
+ reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
+ nfi_writel(nfc, reg, NFI_CON);
+ nfi_writew(nfc, STAR_EN, NFI_STRDATA);
+
+ if (!dma) {
+ data_len = mtk_data_len(chip);
+
+ if (data_len & 0x3) {
+ reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
+ nfi_writew(nfc, reg, NFI_CNFG);
+ byterw = 1;
+ } else {
+ data_len >>= 2;
+ byterw = 0;
+ }
+ if (!raw) {
+ stats.bitflips = 0;
+ correct = chip->stats.corrected;
+ fail = chip->stats.failed;
+ }
+ for (i = 0; i < sectors; i++) {
+ for (j = 0; j < data_len; j++) {
+ mtk_nfc_wait_ioready(nfc);
+ if (!byterw)
+ *(buf32 + (i * data_len) + j) = nfi_readl(nfc, NFI_DATAR);
+ else
+ *(buf + (i * data_len) + j) = nfi_readb(nfc, NFI_DATAR);
+ }
+ if (!raw) {
+ rc = mtk_ecc_cpu_correct(nfc->ecc, &stats, buf + (i * (byterw ? data_len : (data_len << 2))), i, polling);
+ if (rc < 0)
+ goto disecc;
+ chip->stats.corrected += stats.corrected;
+ chip->stats.failed += stats.failed;
+ if (stats.failed)
+ dprintf(CRITICAL, "sectoer %d uncorrect\n", i);
+ }
+ }
+ if (!raw) {
+ bitflips = stats.bitflips;
+ rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
+ if (rc) {
+#if MT2731_SUPPORT_SPI_NAND
+ if (!chip->bIsPNAND)
+ dprintf(CRITICAL, " Warnning : SPI should not enter here ... CHECK IT !! 0x%x\n", rc);
+#endif
+ dprintf(CRITICAL, "page is empty, 0x%x\n", nfi_readl(nfc, NFI_STA));
+ memset(buf, 0xff, sectors * mtk_data_len(chip));
+ bitflips = 0;
+ chip->stats.corrected = correct;
+ chip->stats.failed = fail;
+ }
+#if MT2731_SUPPORT_SPI_NAND
+ /* Only SPI NAND : use DECFER and Error Num to check empty page */
+ decfer_mask = ((1<<sectors)-1);
+ if ((!chip->bIsPNAND) && (0 == stats.corrected) &&
+ (decfer_mask == (readl(nfc->ecc->regs + ECC_DECFER) & decfer_mask))) {
+ dprintf(CRITICAL, "SPI : PIO Mode page 0x% is empty\n", page);
+ memset(buf, 0xff, sectors * mtk_data_len(chip));
+ bitflips = 0;
+ chip->stats.corrected = correct;
+ chip->stats.failed = fail;
+ }
+#endif
+ }
+ }
+
+ if (dma && (!polling)) {
+ rc = mtk_nfc_irq_wait(nfc, MTK_TIMEOUT);
+ if (!rc) {
+ dprintf(CRITICAL, "read ahb/dma done timeout\n");
+ nfi_writew(nfc, 0, NFI_INTR_EN);
+ }
+ }
+
+ rc = check_with_timeout(ADDRCNTR_SEC(nfi_readl(nfc, NFI_BYTELEN)) >= sectors, MTK_TIMEOUT);
+ if (rc && polling)
+ rc = check_with_timeout((nfi_readl(nfc, NFI_MASTER_STA) & MASTER_BUS_BUSY) == 0, MTK_TIMEOUT);
+ if (!rc) {
+ dprintf(CRITICAL, "subpage done timeout %d\n", nfi_readl(nfc, NFI_BYTELEN));
+ dprintf(CRITICAL, "cnfg 0x%x fmt 0x%x con 0x%x master_sta 0x%x\n",
+ nfi_readl(nfc, NFI_CNFG), nfi_readl(nfc, NFI_PAGEFMT), nfi_readl(nfc, NFI_CON),
+ nfi_readl(nfc, NFI_MASTER_STA));
+ bitflips = -EIO;
+ } else {
+ if ((!raw) && dma) {
+ bitflips = 0;
+ rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE, polling);
+ if (!rc)
+ rc = mtk_ecc_wait_decode_fsm_idle(nfc->ecc);
+ arch_invalidate_cache_range((addr_t)buf, (size_t)len);
+ mtk_nfc_read_fdm(chip, start, sectors);
+ bitflips = rc < 0 ? -ETIMEDOUT :
+ mtk_nfc_update_ecc_stats(chip, buf, sectors);
+ }
+ }
+
+ if (raw)
+ goto done;
+
+disecc:
+ mtk_ecc_disable(nfc->ecc);
+
+ if (!dma)
+ goto done;
+
+ if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, bufpoi, raw);
+done:
+ nfi_writel(nfc, 0, NFI_CON);
+ nfi_writel(nfc, 0, NFI_CNFG);
+
+ return bitflips;
+}
+
+static int mtk_nfc_read_subpage_ecc_dma_polling(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg)
+{
+ return mtk_nfc_read_subpage(chip, off, len, p, pg, 0, 1, 1);
+}
+
+static int mtk_nfc_read_subpage_ecc_dma_irq(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg)
+{
+ return mtk_nfc_read_subpage(chip, off, len, p, pg, 0, 1, 0);
+}
+
+static int mtk_nfc_read_subpage_ecc_pio_polling(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 start, end, i;
+ int ret;
+
+ start = off / chip->ecc_size;
+ end = DIV_ROUND_UP(off + len, chip->ecc_size);
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, off, len, nfc->buffer, pg, 0, 0, 1);
+ if (ret < 0)
+ return ret;
+
+ for (i = start; i < end; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (p)
+ memcpy(data_ptr(chip, p, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_subpage_ecc_pio_irq(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 start, end, i;
+ int ret;
+
+ start = off / chip->ecc_size;
+ end = DIV_ROUND_UP(off + len, chip->ecc_size);
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, off, len, nfc->buffer, pg, 0, 0, 0);
+ if (ret < 0)
+ return ret;
+
+ for (i = start; i < end; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (p)
+ memcpy(data_ptr(chip, p, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_ecc_dma_polling(struct mtk_nand_chip *chip, u8 *p,
+ int pg)
+{
+ return mtk_nfc_read_subpage(chip, 0, chip->pagesize, p, pg, 0, 1, 1);
+}
+
+static int mtk_nfc_read_page_ecc_dma_irq(struct mtk_nand_chip *chip, u8 *p,
+ int pg)
+{
+ return mtk_nfc_read_subpage(chip, 0, chip->pagesize, p, pg, 0, 1, 0);
+}
+
+static int mtk_nfc_read_page_ecc_pio_polling(struct mtk_nand_chip *chip, u8 *p,
+ int pg)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 i;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer, pg, 0, 0, 1);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (p)
+ memcpy(data_ptr(chip, p, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_ecc_pio_irq(struct mtk_nand_chip *chip, u8 *p,
+ int pg)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 i;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer, pg, 0, 0, 0);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (p)
+ memcpy(data_ptr(chip, p, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_raw_dma_polling(struct mtk_nand_chip *chip,
+ u8 *buf, int page)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 i;
+ u32 parity_size = mtk_nand->spare_per_sector - fdm->reg_size;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer,
+ page, 1, 1, 1);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+ memcpy(oob_parity_ptr(chip, i), mtk_oob_parity_ptr(chip, i),
+ parity_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (buf)
+ memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_raw_dma_irq(struct mtk_nand_chip *chip,
+ u8 *buf, int page)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 i;
+ u32 parity_size = mtk_nand->spare_per_sector - fdm->reg_size;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer,
+ page, 1, 1, 0);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+ memcpy(oob_parity_ptr(chip, i), mtk_oob_parity_ptr(chip, i),
+ parity_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (buf)
+ memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_raw_pio_polling(struct mtk_nand_chip *chip,
+ u8 *buf, int page)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 i;
+ u32 parity_size = mtk_nand->spare_per_sector - fdm->reg_size;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer,
+ page, 1, 0, 1);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+ memcpy(oob_parity_ptr(chip, i), mtk_oob_parity_ptr(chip, i),
+ parity_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (buf)
+ memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+static int mtk_nfc_read_page_raw_pio_irq(struct mtk_nand_chip *chip,
+ u8 *buf, int page)
+{
+ struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
+ u32 parity_size = mtk_nand->spare_per_sector - fdm->reg_size;
+ u32 i;
+ int ret;
+
+ memset(nfc->buffer, 0xff, chip->pagesize + chip->oobsize);
+ ret = mtk_nfc_read_subpage(chip, 0, chip->pagesize, nfc->buffer,
+ page, 1, 0, 0);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < chip->ecc_steps; i++) {
+ memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
+ memcpy(oob_parity_ptr(chip, i), mtk_oob_parity_ptr(chip, i),
+ parity_size);
+
+ if (i == mtk_nand->bad_mark.sec)
+ mtk_nand->bad_mark.bm_swap(chip, nfc->buffer, 1);
+
+ if (buf)
+ memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
+ chip->ecc_size);
+ }
+
+ return ret;
+}
+
+#define GPIO_DIR4 (GPIO_BASE + 0x040)
+#define GPIO_DIR5 (GPIO_BASE + 0x050)
+#define GPIO_DOUT4 (GPIO_BASE + 0x140)
+#define GPIO_DOUT5 (GPIO_BASE + 0x150)
+
+#define GPIO_MODE18 (GPIO_BASE + 0x420)
+#define GPIO_MODE19 (GPIO_BASE + 0x430)
+#define GPIO_MODE20 (GPIO_BASE + 0x440)
+
+#define IO_CFG_SMT_CFG0 (IO_CFG_TL_BASE + 0x80)
+#define IO_CFG_PU_CFG0 (IO_CFG_TL_BASE + 0x50)
+#define IO_CFG_PD_CFG0 (IO_CFG_TL_BASE + 0x40)
+
+static void nand_set_gpio(u64 addr, u32 mask, u32 val)
+{
+ u32 reg_val;
+
+ reg_val = readl(addr);
+ reg_val &= ~mask;
+ reg_val |= val;
+ writel(reg_val, addr);
+}
+
+static int mtk_nfc_gpio_init(void)
+{
+ /* AuxFunc.1 : parallel nand, AuxFunc.2: spi nand */
+ /* set gpio 147 ~ 151, func:1 */
+ nand_set_gpio(GPIO_MODE18, 0xFFFFF000, 0x11111000);
+ /* set gpio 152 ~ 159, func:1 */
+ nand_set_gpio(GPIO_MODE19, 0xFFFFFFFF, 0x11111111);
+ /* set gpio 160, func:1 */
+ nand_set_gpio(GPIO_MODE20, 0x0000000F, 0x00000001);
+
+ /* set gpio 147 ~ 160, smt:1 */
+ nand_set_gpio(IO_CFG_SMT_CFG0, 0x00003FFF, 0x00003FFF);
+ /* set gpio 157 ~ 160, pull up:1*/
+ nand_set_gpio(IO_CFG_PU_CFG0, 0x00003A00, 0x00003A00);
+ /* set gpio 147 ~ 156, pull down:1*/
+ nand_set_gpio(IO_CFG_PD_CFG0, 0x000005FF, 0x000005FF);
+
+ /* set gpio 147 ~ 159, dout:0 */
+ nand_set_gpio(GPIO_DOUT4, 0xFFF80000, 0x00000000);
+ /* set gpio 160, dout:0 */
+ nand_set_gpio(GPIO_DOUT5, 0x00000001, 0x00000000);
+
+ /* set gpio 147 ~ 159, dir:0 */
+ nand_set_gpio(GPIO_DIR4, 0xFFF80000, 0x00000000);
+ /* set gpio 160, dir:0 */
+ nand_set_gpio(GPIO_DIR5, 0x00000001, 0x00000000);
+
+ dprintf(ALWAYS, "%s check nfi io 0x%x 0x%x 0x%x - 0x%x 0x%x\n",
+ __func__, readl(GPIO_MODE18), readl(GPIO_MODE19), readl(GPIO_MODE20),
+ readl(IO_CFG_PU_CFG0), readl(IO_CFG_PD_CFG0));
+
+ return 0;
+}
+
+#define SS_SEED_NUM 128
+static u16 ss_randomizer_seed[SS_SEED_NUM] = {
+ 0x576A, 0x05E8, 0x629D, 0x45A3, 0x649C, 0x4BF0, 0x2342, 0x272E,
+ 0x7358, 0x4FF3, 0x73EC, 0x5F70, 0x7A60, 0x1AD8, 0x3472, 0x3612,
+ 0x224F, 0x0454, 0x030E, 0x70A5, 0x7809, 0x2521, 0x48F4, 0x5A2D,
+ 0x492A, 0x043D, 0x7F61, 0x3969, 0x517A, 0x3B42, 0x769D, 0x0647,
+ 0x7E2A, 0x1383, 0x49D9, 0x07B8, 0x2578, 0x4EEC, 0x4423, 0x352F,
+ 0x5B22, 0x72B9, 0x367B, 0x24B6, 0x7E8E, 0x2318, 0x6BD0, 0x5519,
+ 0x1783, 0x18A7, 0x7B6E, 0x7602, 0x4B7F, 0x3648, 0x2C53, 0x6B99,
+ 0x0C23, 0x67CF, 0x7E0E, 0x4D8C, 0x5079, 0x209D, 0x244A, 0x747B,
+ 0x350B, 0x0E4D, 0x7004, 0x6AC3, 0x7F3E, 0x21F5, 0x7A15, 0x2379,
+ 0x1517, 0x1ABA, 0x4E77, 0x15A1, 0x04FA, 0x2D61, 0x253A, 0x1302,
+ 0x1F63, 0x5AB3, 0x049A, 0x5AE8, 0x1CD7, 0x4A00, 0x30C8, 0x3247,
+ 0x729C, 0x5034, 0x2B0E, 0x57F2, 0x00E4, 0x575B, 0x6192, 0x38F8,
+ 0x2F6A, 0x0C14, 0x45FC, 0x41DF, 0x38DA, 0x7AE1, 0x7322, 0x62DF,
+ 0x5E39, 0x0E64, 0x6D85, 0x5951, 0x5937, 0x6281, 0x33A1, 0x6A32,
+ 0x3A5A, 0x2BAC, 0x743A, 0x5E74, 0x3B2E, 0x7EC7, 0x4FD2, 0x5D28,
+ 0x751F, 0x3EF8, 0x39B1, 0x4E49, 0x746B, 0x6EF6, 0x44BE, 0x6DB7
+};
+
+static void mtk_nfc_randomizer_init(struct mtk_nand_chip *chip)
+{
+#define TRAP_RANDOM_CFG (IO_PHYS + 0x434)
+#define TRAR_RANDOM_ENABLE (NAND_BIT(2))
+ if (readl(TRAP_RANDOM_CFG) & TRAR_RANDOM_ENABLE) {
+ chip->options |= NAND_NEED_SCRAMBLING;
+ dprintf(ALWAYS, "nand randomizer trapping on!\n");
+ } else {
+ dprintf(ALWAYS, "nand randomizer trapping off!\n");
+ };
+}
+
+static void mtk_nfc_randomizer_enable(struct mtk_nand_chip *chip, int page,
+ enum mtk_randomizer_operation rand, int repage)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 reg = 0, index;
+
+ if (!(chip->options & NAND_NEED_SCRAMBLING))
+ return;
+
+ /* randomizer type and reseed type setup */
+ reg = nfi_readl(nfc, NFI_CNFG) | CNFG_RAND_SEL;
+ if (repage)
+ reg &= ~CNFG_RESEED_SEC_EN;
+ else
+ reg |= CNFG_RESEED_SEC_EN;
+ nfi_writel(nfc, reg, NFI_CNFG);
+
+ /* randomizer seed and type setup */
+ index = page % chip->page_per_block;
+ index &= SS_SEED_NUM - 1;
+ reg = (ss_randomizer_seed[index] & RAN_SEED_MASK) << RAND_SEED_SHIFT(rand);
+ reg |= RAND_EN(rand);
+
+ nfi_writel(nfc, reg, NFI_RANDOM_CNFG);
+}
+
+static void mtk_nfc_randomizer_disable(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ if (!(chip->options & NAND_NEED_SCRAMBLING))
+ return;
+
+ nfi_writel(nfc, 0, NFI_RANDOM_CNFG);
+}
+
+static inline void mtk_nfc_acctiming(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u8 mask = 7;
+ u8 lk_freq = (chip->freq_map >> 4) & mask;
+
+ /* nfc set clock by self, setting freq from 'freq_map' at device table */
+ if (lk_freq != 0) {
+ dprintf(ALWAYS, "[nand] init >>> CLK_CFG_5 0x%x\n", readl(CLK_CFG_5));
+
+ writel(mask << 24, CLK_CFG_5_CLR);
+ writel(lk_freq << 24, CLK_CFG_5_SET);
+ writel(0x1000000, CLK_CFG_UPDATE);
+
+ dprintf(ALWAYS, "[nand] init <<< CLK_CFG_5 0x%x\n", readl(CLK_CFG_5));
+ }
+
+ /*
+ * ACCON: access timing control register
+ * -------------------------------------
+ * 31:28: minimum required time for CS post pulling down after accessing
+ * the device
+ * 27:22: minimum required time for CS pre pulling down before accessing
+ * the device
+ * 21:16: minimum required time from NCEB low to NREB low
+ * 15:12: minimum required time from NWEB high to NREB low.
+ * 11:08: write enable hold time
+ * 07:04: write wait states
+ * 03:00: read wait states
+ */
+
+ dprintf(ALWAYS, "[nand] init >>> acctiming 0x%x\n", nfi_readl(nfc, NFI_ACCCON));
+
+ if (chip->acctiming)
+ nfi_writel(nfc, chip->acctiming, NFI_ACCCON);
+ else
+ nfi_writel(nfc, 0xF3FFFFFF, NFI_ACCCON);
+
+ dprintf(ALWAYS, "[nand] init <<< acctiming 0x%x\n", nfi_readl(nfc, NFI_ACCCON));
+}
+
+static inline void mtk_nfc_hw_init(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+
+ mtk_nfc_acctiming(chip);
+
+ /* set default config value */
+ nfi_writew(nfc, 0x0, SNF_SNF_CNFG);
+
+ /*
+ * CNRNB: nand ready/busy register
+ * -------------------------------
+ * 7:4: timeout register for polling the NAND busy/ready signal
+ * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
+ */
+ nfi_writew(nfc, 0xf1, NFI_CNRNB);
+ nfi_writew(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
+
+ mtk_nfc_hw_reset(nfc);
+
+#if MT2731_SUPPORT_SPI_NAND
+ if (!chip->bIsPNAND)
+ mtk_snfc_hw_reset(nfc);
+#endif
+
+ nfi_readl(nfc, NFI_INTR_STA);
+ nfi_writel(nfc, 0, NFI_INTR_EN);
+
+#if MT2731_SUPPORT_SPI_NAND
+ if (!chip->bIsPNAND) {
+ /* enable SNF config */
+ nfi_writew(nfc, 0x01, SNF_SNF_CNFG);
+ /* SPI can't use empty threshold, disable it */
+ nfi_writew(nfc, 0x00, NFI_EMPTY_THRESH);
+ }
+#endif
+
+ return;
+}
+
+static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtk_nand_chip *nand)
+{
+ struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
+ u32 ecc_bytes;
+
+ ecc_bytes = DIV_ROUND_UP(nand->ecc_strength * ECC_PARITY_BITS, 8);
+
+ fdm->reg_size = chip->spare_per_sector - ecc_bytes;
+ if (fdm->reg_size > NFI_FDM_MAX_SIZE)
+ fdm->reg_size = NFI_FDM_MAX_SIZE;
+
+ /* bad block mark storage */
+ fdm->ecc_size = nand->fdm_ecc_size > NFI_FDM_MAX_SIZE ? NFI_FDM_MAX_SIZE : nand->fdm_ecc_size;
+
+ nand->fdm_ecc_size = fdm->ecc_size;
+ nand->oob_free_ecc_size = nand->fdm_ecc_size * nand->ecc_steps;
+ nand->oob_free_raw_size = (fdm->reg_size - fdm->ecc_size) * nand->ecc_steps;
+
+ return;
+}
+
+static int mtk_nfc_deal_oob_ecc(struct mtk_nand_chip *nand, u8 *buf, u32 offset,
+ u32 len, bool fill_oob)
+{
+ struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
+ struct mtk_nfc_fdm *fdm = &chip->fdm;
+ u32 copy_len, done = 0, sector = offset / fdm->ecc_size;
+ u8 *to, *from;
+
+ while (len) {
+ offset %= fdm->ecc_size;
+ copy_len = MIN(len, fdm->ecc_size - offset);
+ if (fill_oob) {
+ to = oob_ptr(nand, sector) + offset;
+ from = buf + done;
+ } else {
+ to = buf + done;
+ from = oob_ptr(nand, sector) + offset;
+ }
+ memcpy(to, from, copy_len);
+ done += copy_len;
+ len -= copy_len;
+ sector++;
+ offset += copy_len;
+ };
+
+ return 0;
+}
+
+static int mtk_nfc_deal_oob_raw(struct mtk_nand_chip *nand, u8 *buf, u32 offset,
+ u32 len, bool fill_oob)
+{
+ struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
+ struct mtk_nfc_fdm *fdm = &chip->fdm;
+ u32 copy_len, done = 0, sector;
+ u32 fdm_raw_size = fdm->reg_size - fdm->ecc_size;
+ u8 *to, *from;
+
+ sector = offset / fdm_raw_size;
+ while (len) {
+ offset %= fdm_raw_size;
+ copy_len = MIN(len, fdm_raw_size - offset);
+ if (fill_oob) {
+ to = oob_ptr(nand, sector) + fdm->ecc_size + offset;
+ from = buf + done;
+ } else {
+ to = buf + done;
+ from = oob_ptr(nand, sector) + fdm->ecc_size + offset;
+ }
+ memcpy(to, from, copy_len);
+ done += copy_len;
+ len -= copy_len;
+ sector++;
+ offset += copy_len;
+ };
+
+ return 0;
+}
+
+static int mtk_nfc_deal_oob_parity(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len, bool fill_oob)
+{
+ struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
+ struct mtk_nfc_fdm *fdm = &chip->fdm;
+ u32 copy_len, done = 0, sector;
+ u32 parity_size = chip->spare_per_sector - fdm->reg_size;
+ u8 *to, *from;
+
+ sector = offset / parity_size;
+ while (len) {
+ offset %= parity_size;
+ copy_len = MIN(len, parity_size - offset);
+ if (fill_oob) {
+ to = oob_parity_ptr(nand, sector) + offset;
+ from = buf + done;
+ } else {
+ to = buf + done;
+ from = oob_parity_ptr(nand, sector) + offset;
+ }
+ memcpy(to, from, copy_len);
+ done += copy_len;
+ len -= copy_len;
+ sector++;
+ offset += copy_len;
+ };
+
+ return 0;
+}
+
+static int mtk_nfc_transfer_oob_ecc(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_ecc(nand, buf, offset, len, false);
+}
+
+static int mtk_nfc_transfer_oob_raw(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_raw(nand, buf, offset, len, false);
+}
+
+static int mtk_nfc_transfer_oob_parity(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_parity(nand, buf, offset, len, false);
+}
+
+static int mtk_nfc_fill_oob_ecc(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_ecc(nand, buf, offset, len, true);
+}
+
+static int mtk_nfc_fill_oob_raw(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_raw(nand, buf, offset, len, true);
+}
+
+static int mtk_nfc_fill_oob_parity(struct mtk_nand_chip *nand, u8 *buf,
+ u32 offset, u32 len)
+{
+ return mtk_nfc_deal_oob_parity(nand, buf, offset, len, true);
+}
+
+static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
+ struct mtk_nand_chip *nand)
+{
+ if (nand->pagesize == 512) {
+ bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
+ } else {
+ bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
+ bm_ctl->sec = nand->pagesize / mtk_data_len(nand);
+ bm_ctl->pos = nand->pagesize % mtk_data_len(nand);
+ }
+
+ return;
+}
+
+static void mtk_nfc_set_spare_per_sector(u32 *sps, struct mtk_nand_chip *nand)
+{
+ u32 spare[] = {16, 26, 27, 28, 32, 36, 40, 44,
+ 48, 49, 50, 51, 52, 62, 63, 64
+ };
+ u32 eccsteps, i;
+
+ eccsteps = nand->pagesize / nand->ecc_size;
+ *sps = nand->oobsize / eccsteps;
+
+ if (nand->ecc_size == 1024)
+ *sps >>= 1;
+
+ for (i = 0; i < sizeof(spare) / sizeof(u32); i++) {
+ if (*sps <= spare[i]) {
+ if (*sps == spare[i])
+ *sps = spare[i];
+ else if (i != 0)
+ *sps = spare[i - 1];
+ break;
+ }
+ }
+
+ if (i >= sizeof(spare) / sizeof(u32))
+ *sps = spare[sizeof(spare) / sizeof(u32) - 1];
+
+ if (nand->ecc_size == 1024)
+ *sps <<= 1;
+
+ return;
+}
+
+int mtk_nfc_nand_chip_init(struct mtk_nand_chip **ext_nand)
+{
+ struct mtk_nfc *nfc;
+ struct mtk_nfc_nand_chip *chip;
+ struct mtk_nand_chip *nand;
+ int ret = 0;
+
+ nfc = (struct mtk_nfc *)malloc(sizeof(*nfc));
+ if (!nfc)
+ return -ENOMEM;
+ memset(nfc, 0, sizeof(*nfc));
+ nfc->regs = NFI_BASE;
+
+ chip = (struct mtk_nfc_nand_chip *)malloc(sizeof(*chip));
+ if (!chip) {
+ goto free_nfc;
+ ret = -ENOMEM;
+ }
+ memset(chip, 0, sizeof(*chip));
+
+ /* register interrupt handler */
+ mtk_nfc_request_irq(nfc);
+
+ nand = &chip->chip;
+ *ext_nand = nand;
+
+ nand_set_controller_data(nand, nfc);
+
+ nand->bIsPNAND = true;
+ nand->dev_ready = mtk_nfc_dev_ready;
+ nand->wait_busy_irq = mtk_nfc_wait_busy_irq;
+ nand->select_chip = mtk_nfc_select_chip;
+ nand->write_byte = mtk_nfc_write_byte;
+ nand->write_buf = mtk_nfc_write_buf;
+ nand->read_byte = mtk_nfc_read_byte;
+ nand->read_buf = mtk_nfc_read_buf;
+ nand->cmd_ctrl = mtk_nfc_cmd_ctrl;
+
+ nand->write_page_ecc_dma_irq = mtk_nfc_write_page_ecc_dma_irq;
+ nand->write_page_ecc_dma_polling = mtk_nfc_write_page_ecc_dma_polling;
+ nand->write_page_ecc_pio_irq = mtk_nfc_write_page_ecc_pio_irq;
+ nand->write_page_ecc_pio_polling = mtk_nfc_write_page_ecc_pio_polling;
+ nand->write_page_raw_dma_irq = mtk_nfc_write_page_raw_dma_irq;
+ nand->write_page_raw_dma_polling = mtk_nfc_write_page_raw_dma_polling;
+ nand->write_page_raw_pio_irq = mtk_nfc_write_page_raw_pio_irq;
+ nand->write_page_raw_pio_polling = mtk_nfc_write_page_raw_pio_polling;
+ nand->write_subpage_ecc_dma_irq = mtk_nfc_write_subpage_ecc_dma_irq;
+ nand->write_subpage_ecc_dma_polling = mtk_nfc_write_subpage_ecc_dma_polling;
+ nand->write_subpage_ecc_pio_irq = mtk_nfc_write_subpage_ecc_pio_irq;
+ nand->write_subpage_ecc_pio_polling = mtk_nfc_write_subpage_ecc_pio_polling;
+
+ nand->read_subpage_ecc_dma_irq = mtk_nfc_read_subpage_ecc_dma_irq;
+ nand->read_subpage_ecc_dma_polling = mtk_nfc_read_subpage_ecc_dma_polling;
+ nand->read_subpage_ecc_pio_irq = mtk_nfc_read_subpage_ecc_pio_irq;
+ nand->read_subpage_ecc_pio_polling = mtk_nfc_read_subpage_ecc_pio_polling;
+ nand->read_page_ecc_dma_irq = mtk_nfc_read_page_ecc_dma_irq;
+ nand->read_page_ecc_dma_polling = mtk_nfc_read_page_ecc_dma_polling;
+ nand->read_page_ecc_pio_irq = mtk_nfc_read_page_ecc_pio_irq;
+ nand->read_page_ecc_pio_polling = mtk_nfc_read_page_ecc_pio_polling;
+ nand->read_page_raw_dma_irq = mtk_nfc_read_page_raw_dma_irq;
+ nand->read_page_raw_dma_polling = mtk_nfc_read_page_raw_dma_polling;
+ nand->read_page_raw_pio_irq = mtk_nfc_read_page_raw_pio_irq;
+ nand->read_page_raw_pio_polling = mtk_nfc_read_page_raw_pio_polling;
+
+#if MT2731_DISABLE_RANDOMIZER
+ nand->enable_randomizer = mtk_nfc_randomizer_enable;
+ nand->disable_randomizer = mtk_nfc_randomizer_disable;
+#endif
+
+ nand->fill_oob_ecc = mtk_nfc_fill_oob_ecc;
+ nand->fill_oob_raw = mtk_nfc_fill_oob_raw;
+ nand->fill_oob_parity = mtk_nfc_fill_oob_parity;
+ nand->transfer_oob_ecc = mtk_nfc_transfer_oob_ecc;
+ nand->transfer_oob_raw = mtk_nfc_transfer_oob_raw;
+ nand->transfer_oob_parity = mtk_nfc_transfer_oob_parity;
+
+ mtk_nfc_gpio_init();
+#if MT2731_DISABLE_RANDOMIZER
+ mtk_nfc_randomizer_init(nand);
+#endif
+ mtk_nfc_hw_init(nand);
+
+ ret = mtk_ecc_hw_init(&nfc->ecc);
+ if (ret)
+ goto free_chip;
+
+ ret = mtk_nand_scan(nand, 1 /*MTK_NAND_MAX_NSELS*/);
+ if (ret)
+ goto free_ecc;
+
+ mtk_nfc_acctiming(nand);
+
+ mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, nand);
+ mtk_nfc_set_fdm(&chip->fdm, nand);
+ mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, nand);
+
+ nfc->buffer = (u8 *)memalign(16, nand->pagesize + nand->oobsize);
+ if (!nfc->buffer) {
+ ret = -ENOMEM;
+ goto free_databuf;
+ }
+
+ mutex_init(&nfc->lock);
+
+ ret = mtk_nand_scan_tail(nand);
+ if (ret)
+ goto free_buffer;
+
+ dprintf(INFO, "nand chip init done\n");
+ return 0;
+
+free_buffer:
+ free(nfc->buffer);
+free_databuf:
+ free(nand->databuf);
+free_ecc:
+ free(nfc->ecc);
+free_chip:
+ free(chip);
+free_nfc:
+ free(nfc);
+
+ return ret;
+}
+
+#if MT2731_SUPPORT_SPI_NAND
+
+static void mtk_snfc_select_chip(struct mtk_nand_chip *chip, int chip_num)
+{
+ if ((chip_num < 0) || (chip_num == chip->activechip))
+ return;
+
+ if (!mtk_nfc_hw_runtime_config(chip)) {
+ chip->activechip = chip_num;
+ }
+
+ return;
+}
+
+
+void mtk_snfc_hw_reset(struct mtk_nfc *nfc)
+{
+ u32 reg;
+
+ /* reset the SNF, trigger SW_RST bit to reset state machine */
+ reg = nfi_readl(nfc, SNF_MISC_CTL);
+ reg |= SNF_SW_RST;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+ reg &= ~SNF_SW_RST;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+}
+
+
+static void snand_mac_enable(struct mtk_nand_chip *chip, snand_mode mode)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 mac;
+
+ mac = nfi_readl(nfc, SNF_MAC_CTL);
+
+ /* SPI */
+ if (SPI == mode)
+ {
+ mac &= ~MAC_SIO_SEL; // Clear SIO_SEL to send command in SPI style
+ mac |= MAC_EN; // Enable Macro Mode
+ }
+ /* QPI */
+ else
+ {
+ /*
+ * SFI V2: QPI_EN only effects direct read mode, and it is moved into DIRECT_CTL in V2
+ * There's no need to clear the bit again.
+ */
+
+ /* Set SIO_SEL to send command in QPI style, and enable Macro Mode */
+ mac |= (MAC_SIO_SEL | MAC_EN);
+ }
+ nfi_writel(nfc, mac, SNF_MAC_CTL);
+}
+
+static int snand_mac_trigger(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = 0;
+
+ u32 mac;
+
+ mac = nfi_readl(nfc, SNF_MAC_CTL);
+
+ /* Trigger SFI: Set TRIG and enable Macro mode */
+ mac |= (TRIG | MAC_EN);
+ nfi_writel(nfc, mac, SNF_MAC_CTL);
+
+ /*
+ * Wait for SFI ready
+ * Step 1. Wait for WIP_READY becoming 1 (WIP register is ready)
+ */
+ if (!check_with_timeout((nfi_readl(nfc, SNF_MAC_CTL) & WIP_READY), MTK_TIMEOUT))
+ dprintf(CRITICAL, "Wait WIP timeout SNF_MAC_CTL:0x%x\n", nfi_readl(nfc, SNF_MAC_CTL));
+
+ /*
+ * Step 2. Wait for WIP becoming 0 (Controller finishes command write process)
+ */
+ if (!check_with_timeout(!(nfi_readl(nfc, SNF_MAC_CTL) & WIP), MTK_TIMEOUT))
+ dprintf(CRITICAL, "Wait WIP timeout SNF_MAC_CTL:0x%x\n", nfi_readl(nfc, SNF_MAC_CTL));
+
+ return s_ret;
+}
+
+static void snand_mac_leave(struct mtk_nand_chip *chip)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ u32 mac;
+
+ /* clear SF_TRIG and leave mac mode */
+ mac = nfi_readl(nfc, SNF_MAC_CTL);
+
+ /*
+ * Clear following bits
+ * TRIG: Confirm the macro command sequence is completed
+ * MAC_EN: Leaves macro mode, and enters direct read mode
+ * MAC_SIO_SEL: Always reset quad macro control bit at the end
+ */
+ mac &= ~(TRIG | MAC_EN | MAC_SIO_SEL);
+ nfi_writel(nfc, mac, SNF_MAC_CTL);
+}
+
+static void mtk_snfc_dev_ecc_control(struct mtk_nand_chip *chip, u8 dev_ecc)
+{
+ int s_ret = -1;
+ u8 otp = 0;
+ u8 otp_new = 0;
+ u8 retry_times = 2;
+
+ /* get OTP status before modify */
+ s_ret = chip->snand_get_feature(chip, SNAND_CMD_FEATURES_OTP, &otp);
+ if (-1 == s_ret)
+ retry_times = 0; /* set 0 for don't execute while loop */
+
+ if (dev_ecc)
+ otp_new = otp | SNAND_OTP_ECC_ENABLE;
+ else
+ otp_new = otp & ~SNAND_OTP_ECC_ENABLE;
+
+ while ((otp != otp_new) && retry_times)
+ {
+ /* write enable */
+ s_ret = chip->snand_cmd(chip, SNAND_CMD_WRITE_ENABLE, 1);
+ if (-1 == s_ret) {
+ dprintf(CRITICAL, " Warning : WRITE ENABLE FAIL s_ret:%d\n", s_ret);
+ break;
+ }
+
+ /* set OTP status */
+ s_ret = chip->snand_set_feature(chip, SNAND_CMD_FEATURES_OTP, otp_new);
+ if (-1 == s_ret)
+ break;
+
+ /* get OTP status after modify */
+ s_ret = chip->snand_get_feature(chip, SNAND_CMD_FEATURES_OTP, &otp);
+ if (-1 == s_ret)
+ break;
+ retry_times--;
+ }
+
+ if ((-1 == s_ret) || (otp != otp_new))
+ dprintf(CRITICAL, " Warning : %s ECC Control FAIL (0x%x != 0x%x)\n",
+ (dev_ecc)?"Enable":"Disable", otp, otp_new);
+ else
+ dprintf(ALWAYS, " Init : %s ECC Control SUCCESS \n", (dev_ecc)?"Enable":"Disable");
+
+ return;
+}
+
+static void mtk_snfc_dev_unlock_blocks(struct mtk_nand_chip *chip)
+{
+ int s_ret = -1;
+ u8 lock = 0;
+ u8 lock_new = 0;
+ u8 retry_times = 2;
+
+ /* get BLOCK LOCK status before modify */
+ s_ret = chip->snand_get_feature(chip, SNAND_CMD_FEATURES_BLOCK_LOCK, &lock);
+ if (-1 == s_ret)
+ retry_times = 0; /* set 0 for don't execute while loop */
+
+ lock_new = lock & ~SNAND_BLOCK_LOCK_BITS;
+
+ while ((lock != lock_new) && retry_times)
+ {
+ /* write enable */
+ s_ret = chip->snand_cmd(chip, SNAND_CMD_WRITE_ENABLE, 1);
+ if (-1 == s_ret) {
+ dprintf(CRITICAL, " Warning : WRITE ENABLE FAIL s_ret:%d\n", s_ret);
+ break;
+ }
+
+ /* set BLOCK LOCK status */
+ s_ret = chip->snand_set_feature(chip, SNAND_CMD_FEATURES_BLOCK_LOCK, lock_new);
+ if (-1 == s_ret)
+ break;
+
+ /* get BLOCK LOCK status after modify */
+ s_ret = chip->snand_get_feature(chip, SNAND_CMD_FEATURES_BLOCK_LOCK, &lock);
+ if (-1 == s_ret)
+ break;
+ retry_times--;
+ }
+
+ if ((-1 == s_ret) || (lock != lock_new))
+ dprintf(CRITICAL, " Warning : Unlock block FAIL (0x%x != 0x%x)\n", lock, lock_new);
+ else
+ dprintf(ALWAYS, " Init : Unlock block SUCCESS \n");
+
+ return;
+}
+
+
+u32 snand_gpram_write_c1a3(const u32 cmd, const u32 address)
+{
+ u32 val = 0;
+
+ val |= ((address >> 24) & 0x000000FF);
+ val |= ((address >> 8) & 0x0000FF00);
+ val |= ((address << 8) & 0x00FF0000);
+ val |= ((address << 24) & 0xFF000000);
+
+ return ((val & 0xFFFFFF00) | (cmd & 0xFF));
+}
+
+static int mtk_snfc_pre_read_setting(struct mtk_nand_chip *chip, u32 off,
+ u32 len, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u8 dev_status;
+ u32 cmd, reg;
+ u32 spare = chip->oobsize/chip->ecc_steps;
+ u32 column, sectors, start, end;
+
+ mtk_nfc_hw_reset(nfc);
+ mtk_snfc_hw_reset(nfc);
+ //dprintf(CRITICAL, "%s - off 0x%x len 0x%x pg 0x%x\n", __func__, off,len,pg);
+
+ start = off / chip->ecc_size;
+ end = DIV_ROUND_UP(off + len, chip->ecc_size);
+
+ sectors = end - start;
+ column = start * (chip->ecc_size + spare);
+
+ len = sectors * (chip->ecc_size + spare);
+
+ /* 1. Read page to cache */
+ cmd = snand_gpram_write_c1a3(SNAND_CMD_PAGE_READ, pg); // PAGE_READ command + 3-byte address
+ s_ret = chip->snand_cmd(chip, cmd, 4);
+ if (s_ret == -1) {
+ dprintf(CRITICAL, "%s - Read CMD FAIL s_ret:%d\n", __func__, s_ret);
+ goto RD_ERR;
+ }
+
+ /* 2. Get features chekc status */
+ s_ret = chip->snand_wait_idel(chip, (u8*)(&dev_status));
+ if (s_ret == -1) {
+ dprintf(CRITICAL, "%s - Device NOT Ready 0x%x s_ret:%d\n",
+ __func__, dev_status, s_ret);
+ goto RD_ERR;
+ }
+
+ /* 3. Setting SNAND Register related config */
+ reg = nfi_readl(nfc, SNF_RD_CTL2);
+ reg &= ~DATA_READ_CMD_MASK;
+ reg |= SNAND_CMD_RANDOM_READ & DATA_READ_CMD_MASK;
+ nfi_writel(nfc, reg, SNF_RD_CTL2);
+
+ // set DATA READ address
+ nfi_writel(nfc, (column & DATA_READ_ADDRESS_MASK), SNF_RD_CTL3);
+
+ // set SNF data length
+ reg = (len << RD_DATA_BYTE_LEN_OFFSET) | (len << PG_LOAD_BYTE_LEN_OFFSET);
+ nfi_writel(nfc, reg, SNF_MISC_CTL2);
+
+ /* 4. config Custom Read mode */
+ reg = nfi_readl(nfc, SNF_MISC_CTL);
+
+ reg &= ~(SNF_PG_LOAD_X4_EN|SNF_PG_LOAD_CUSTOM_EN|SNF_DUAL_MASK);
+ reg |= SNF_DATARD_CUSTOM_EN;
+ reg &= ~SNF_DATA_READ_MODE_MASK;
+ reg |=SNF_DATA_READ_MODE_X1;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+
+ /* 5. set read custom mode */
+ reg = nfi_readl(nfc, NFI_CNFG);
+ reg |= CNFG_OP_CUST;
+ nfi_writel(nfc, reg, NFI_CNFG);
+ mtk_nfc_send_command(nfc, NAND_CMD_READSTART);
+
+RD_ERR:
+ return s_ret;
+}
+
+static int mtk_snfc_auto_read_setting(struct mtk_nand_chip *chip, u32 off,
+ u32 len, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u32 reg, page_spare_size;
+
+ mtk_nfc_hw_reset(nfc);
+ mtk_snfc_hw_reset(nfc);
+ dprintf(CRITICAL, "%s - off 0x%x len 0x%x pg 0x%x\n", __func__, off,len,pg);
+
+ page_spare_size = chip->pagesize + chip->oobsize;
+
+
+
+ reg =( (0xF << 24) | (0xC0 << 16) | (1 << 8));
+ nfi_writel(nfc, reg, SNF_GF_CTL1);
+
+
+ reg = nfi_readl(nfc, SNF_GF_CTL3);
+ reg &= ~0xF;
+ reg |= (0xF << 16);
+ nfi_writel(nfc, reg, SNF_GF_CTL3);
+
+
+ reg = (0x13 << 24);
+ reg |= pg;
+ nfi_writel(nfc, reg, SNF_RD_CTL1);
+
+ nfi_writel(nfc, 0x803, SNF_RD_CTL2);
+ nfi_writel(nfc, 0, SNF_RD_CTL3);
+
+
+ // set SNF data length
+ reg = (page_spare_size << RD_DATA_BYTE_LEN_OFFSET) | (page_spare_size << PG_LOAD_BYTE_LEN_OFFSET);
+ nfi_writel(nfc, reg, SNF_MISC_CTL2);
+
+
+ /* 4. config Custom Read mode */
+ //reg = nfi_readl(nfc, SNF_MISC_CTL);
+ //reg &= ~(SNF_PG_LOAD_X4_EN|SNF_PG_LOAD_CUSTOM_EN|SNF_DUAL_MASK);
+ //reg &= ~SNF_DATARD_CUSTOM_EN;
+ //reg &= ~SNF_DATA_READ_MODE_MASK;
+ nfi_writel(nfc, 0xa, SNF_MISC_CTL);
+
+
+RD_ERR:
+ return s_ret;
+}
+
+static int mtk_snfc_pre_write_setting(struct mtk_nand_chip *chip, u32 off,
+ u32 len, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u32 reg, page_spare_size;
+
+ mtk_nfc_hw_reset(nfc);
+ mtk_snfc_hw_reset(nfc);
+ //dprintf(CRITICAL, "%s - off 0x%x len 0x%x pg 0x%x\n", __func__, off,len,pg);
+
+ page_spare_size = chip->pagesize + chip->oobsize;
+
+ /* Write Enable */
+ s_ret = chip->snand_cmd(chip, SNAND_CMD_WRITE_ENABLE, 1);
+ if (-1 == s_ret) {
+ dprintf(CRITICAL, " Warning : WRITE ENABLE FAIL s_ret:%d\n", s_ret);
+ return s_ret;
+ }
+
+ /* set snf program command */
+ reg = SNAND_CMD_WRITE_ENABLE | (SNAND_CMD_PROGRAM_LOAD << PG_LOAD_CMD_OFFSET) | (SNAND_CMD_PROGRAM_EXECUTE << PG_EXE_CMD_OFFSET);
+ nfi_writel(nfc, reg, SNF_PG_CTL1);
+
+ /* set column address */
+ reg = off & PG_LOAD_ADDR_MASK;
+ nfi_writel(nfc, reg, SNF_PG_CTL2);
+
+ /* set row address */
+ nfi_writel(nfc, pg, SNF_PG_CTL3);
+
+ /* set program(read) length */
+ reg = (page_spare_size << RD_DATA_BYTE_LEN_OFFSET) | (page_spare_size << PG_LOAD_BYTE_LEN_OFFSET);
+ nfi_writel(nfc, reg, SNF_MISC_CTL2);
+
+ /* set SNF timing */
+ reg = nfi_readl(nfc, SNF_MISC_CTL);
+ reg &= ~SNF_DATARD_CUSTOM_EN;
+ reg |= SNF_PG_LOAD_CUSTOM_EN;
+ reg &= ~SNF_DATA_READ_MODE_MASK;
+ reg |= ((SNF_DATA_READ_MODE_X1 << SNF_DATA_READ_MODE_OFFSET) & SNF_DATA_READ_MODE_MASK);
+ reg &= ~SNF_DATA_READ_MODE_X4;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+
+ /* set NFI config to program operation mode */
+ reg = nfi_readl(nfc, NFI_CNFG);
+ reg &= ~CNFG_OP_MASK;
+ reg |= CNFG_OP_PRGM;
+ nfi_writel(nfc, reg, NFI_CNFG);
+
+ return 0;
+}
+
+static int mtk_snfc_post_write_setting(struct mtk_nand_chip *chip, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = 0;
+ u8 dev_status;
+ u32 cmd, reg;
+
+ //dprintf(CRITICAL, "%s - pg 0x%x\n", __func__, pg);
+
+ /* clear snf sta customer program flag */
+ reg = nfi_readl(nfc, SNF_STA_CTL1);
+ reg |= CUSTOM_PROGRAM;
+ nfi_writel(nfc, reg, SNF_STA_CTL1);
+ nfi_writel(nfc, 0, SNF_STA_CTL1);
+
+ /* clear snf customer program setting */
+ reg = nfi_readl(nfc, SNF_MISC_CTL);
+ reg &= ~SNF_PG_LOAD_CUSTOM_EN;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+
+ //mtk_nfc_hw_reset(nfc);
+
+ /* program execute */
+ cmd = snand_gpram_write_c1a3(SNAND_CMD_PROGRAM_EXECUTE, pg); // PAGE_WRITE command + 3-byte address
+ s_ret = chip->snand_cmd(chip, cmd, 4);
+ if (s_ret == -1) {
+ dprintf(CRITICAL, "%s - Program CMD FAIL s_ret:%d\n", __func__, s_ret);
+ goto PG_ERR;
+ }
+
+ /* get features check status */
+ s_ret = chip->snand_wait_idel(chip, (u8*)(&dev_status));
+ if (s_ret == -1)
+ dprintf(CRITICAL, "%s - Device NOT Ready s_ret:%d 0x%x\n", __func__, s_ret, dev_status);
+
+ nfi_writel(nfc, 0, NFI_CNFG);
+ //dprintf(CRITICAL, "%s - dev_status 0x%x\n", __func__, dev_status);
+
+PG_ERR:
+ return (s_ret == -1) ? s_ret : dev_status;
+}
+
+static int mtk_snfc_auto_erase_setting(struct mtk_nand_chip *chip, int pg)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u8 dev_status;
+ u32 reg;
+
+ //dprintf(CRITICAL, "%s - pg 0x%x\n", __func__, pg);
+
+ mtk_nfc_hw_reset(nfc);
+
+ /* erase address */
+ nfi_writel(nfc, pg, SNF_ER_CTL2);
+
+ /* set loop limit and polling cycles */
+ reg = (GF_LOOP_LIMIT_NO_LIMIT << GF_LOOP_LIMIT_OFFSET) | 0x20;
+ nfi_writel(nfc, reg, SNF_GF_CTL3);
+
+ /* set erase command */
+ reg = SNAND_CMD_BLOCK_ERASE << ER_CMD_OFFSET;
+ nfi_writel(nfc, reg, SNF_ER_CTL);
+
+ /* set SNF timing */
+ reg = nfi_readl(nfc, SNF_MISC_CTL);
+ reg &= ~SNF_DATARD_CUSTOM_EN;
+ reg &= ~SNF_DATA_READ_MODE_MASK;
+ reg &= ~SNF_PG_LOAD_X4_EN;
+ nfi_writel(nfc, reg, SNF_MISC_CTL);
+
+ /* trigger auto erase */
+ reg = nfi_readl(nfc, SNF_ER_CTL);
+ reg |= AUTO_ERASE_TRIGGER;
+ nfi_writel(nfc, reg, SNF_ER_CTL);
+
+ /*
+ * Wait for SFI ready
+ * Step 1. Wait for WIP_READY becoming 1 (WIP register is ready)
+ */
+ if (!check_with_timeout((nfi_readl(nfc, SNF_STA_CTL1) & AUTO_BLKER), MTK_TIMEOUT)) {
+ dprintf(CRITICAL, "Wait WIP timeout SNF_STA_CTL1:0x%x\n", nfi_readl(nfc, SNF_STA_CTL1));
+ s_ret = -1;
+ }
+
+ nfi_writel(nfc, 0, SNF_ER_CTL);
+
+ /* get features check status */
+ s_ret = chip->snand_wait_idel(chip, (u8*)(&dev_status));
+ if (s_ret == -1)
+ dprintf(CRITICAL, "%s - Device NOT Ready s_ret:%d 0x%x\n", __func__, s_ret, dev_status);
+
+ return (s_ret == -1) ? s_ret : dev_status;
+}
+
+static int mtk_snfc_cmd_ctrl(struct mtk_nand_chip *chip, u32 cmd, u8 outlen)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ //dprintf(CRITICAL, "%s - cmd 0x%x\n", __func__, cmd);
+
+ nfi_writel(nfc, cmd, SNF_GPRAM_ADDR);
+ nfi_writel(nfc, outlen, SNF_MAC_OUTL);
+ nfi_writel(nfc, 0, SNF_MAC_INL);
+
+ snand_mac_enable(chip, SPI);
+ s_ret = snand_mac_trigger(chip);
+ snand_mac_leave(chip);
+
+ return s_ret;
+}
+
+static int mtk_snfc_cmd_ext_ctrl(struct mtk_nand_chip *chip, u8 *cmd, u8 *data, u32 outlen, u32 inlen)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u8 *p_tmp;
+ u32 i, j, tmp_data, gpram_addr;
+
+ //dprintf(CRITICAL, "%s\n", __func__);
+
+ p_tmp=(u8 *)(&tmp_data);
+
+ // Moving commands into SFI GPRAM
+ for (i = 0, gpram_addr = SNF_GPRAM_ADDR; i < outlen; gpram_addr += 4)
+ {
+ // Using 4 bytes aligned copy, by moving the data into the temp buffer and then write to GPRAM
+ for (j = 0, tmp_data = 0; i < outlen && j < 4; i++, j++)
+ p_tmp[j] = cmd[i];
+
+ nfi_writel(nfc, tmp_data, gpram_addr);
+ }
+
+ nfi_writel(nfc, outlen, SNF_MAC_OUTL);
+ nfi_writel(nfc, inlen, SNF_MAC_INL);
+ snand_mac_enable(chip, chip->s_mode);
+ s_ret = snand_mac_trigger(chip);
+ snand_mac_leave(chip);
+
+ /* for NULL data, this loop will be skipped */
+ for (i = 0, gpram_addr = (SNF_GPRAM_ADDR + outlen); i < inlen; ++i, ++data, ++gpram_addr)
+ *data = nfi_readb(nfc, gpram_addr);
+
+ return s_ret;
+}
+
+static int mtk_snfc_set_feature(struct mtk_nand_chip *chip, u8 Address, u8 InValue)
+{
+ int s_ret = -1;
+ u32 cmd;
+
+ /* set features */
+ cmd = SNAND_CMD_SET_FEATURES | (Address << 8) | (InValue << 16);
+ s_ret = chip->snand_cmd(chip, cmd, 3);
+ if (s_ret == -1)
+ dprintf(CRITICAL, " Warning : SET FEATURE FAIL s_ret:%d\n", s_ret);
+
+ return s_ret;
+}
+
+static int mtk_snfc_get_feature(struct mtk_nand_chip *chip, u8 Address, u8 *OutValue)
+{
+ int s_ret = -1;
+ u32 cmd;
+
+ *OutValue = 0;
+
+ /* get features (status polling) */
+ cmd = SNAND_CMD_GET_FEATURES | (Address << 8);
+
+ s_ret = chip->snand_cmd_ext(chip, (u8*)(&cmd), OutValue, 2, 1);
+ if (-1 == s_ret)
+ dprintf(CRITICAL, " Warning : GET FEATURE FAIL s_ret:%d Status:0x%x\n", s_ret, *OutValue);
+
+ dprintf(CRITICAL, "%s - Status 0x%x\n", __func__, *OutValue);
+
+ return s_ret;
+}
+
+
+static int mtk_snfc_wait_dev_idel(struct mtk_nand_chip *chip, u8 *dev_status)
+{
+ struct mtk_nfc *nfc = nand_get_controller_data(chip);
+ int s_ret = -1;
+ u32 cmd;
+ u32 i;
+
+ *dev_status = 0;
+
+ /* get features (status polling) */
+ cmd = SNAND_CMD_GET_FEATURES | (SNAND_CMD_FEATURES_STATUS << 8);
+
+ nfi_writel(nfc, cmd, SNF_GPRAM_ADDR);
+ nfi_writel(nfc, 2, SNF_MAC_OUTL);
+ nfi_writel(nfc, 1, SNF_MAC_INL);
+
+ /* polling status register */
+ for (i = 0; i < MTK_TIMEOUT; i++)
+ {
+ snand_mac_enable(chip, SPI);
+ s_ret = snand_mac_trigger(chip);
+ if (-1 == s_ret)
+ break;
+ snand_mac_leave(chip);
+ *dev_status = nfi_readb(nfc, SNF_GPRAM_ADDR + (2*sizeof(u8)));
+
+ if (0 == (*dev_status & SNAND_STATUS_OIP))
+ {
+ s_ret = 0;
+ break;
+ }
+ }
+
+ if (-1 == s_ret)
+ dprintf(CRITICAL, " Warning : get status timeout ! dev_status still 0x%x !!", *dev_status);
+
+ //dprintf(CRITICAL, "%s - dev_status 0x%x\n", __func__, *dev_status);
+
+ return s_ret;
+}
+
+
+int mtk_snfc_nand_chip_init(struct mtk_nand_chip **ext_nand)
+{
+ struct mtk_nfc *nfc;
+ struct mtk_nfc_nand_chip *chip;
+ struct mtk_nand_chip *nand;
+ int ret = 0;
+
+ dprintf(CRITICAL, "%s\n", __func__);
+
+ nfc = (struct mtk_nfc *)malloc(sizeof(*nfc));
+ if (!nfc)
+ return -ENOMEM;
+ memset(nfc, 0, sizeof(*nfc));
+ nfc->regs = NFI_BASE;
+
+ chip = (struct mtk_nfc_nand_chip *)malloc(sizeof(*chip));
+ if (!chip) {
+ goto free_nfc;
+ ret = -ENOMEM;
+ }
+ memset(chip, 0, sizeof(*chip));
+
+ /* register interrupt handler */
+ mtk_nfc_request_irq(nfc);
+
+ nand = &chip->chip;
+ *ext_nand = nand;
+
+ nand_set_controller_data(nand, nfc);
+
+ nand->bIsPNAND = false;
+
+ nand->select_chip = mtk_snfc_select_chip;
+
+#if 0 /* MT2731_NOT_YET */
+ nand->dev_ready = mtk_nfc_dev_ready;
+ nand->wait_busy_irq = mtk_nfc_wait_busy_irq;
+
+ nand->write_byte = mtk_nfc_write_byte;
+ nand->write_buf = mtk_nfc_write_buf;
+ nand->read_byte = mtk_nfc_read_byte;
+ nand->read_buf = mtk_nfc_read_buf;
+#endif
+
+ /* SPI function */
+ nand->snand_cmd = mtk_snfc_cmd_ctrl;
+ nand->snand_cmd_ext = mtk_snfc_cmd_ext_ctrl;
+ nand->snand_wait_idel = mtk_snfc_wait_dev_idel;
+
+ nand->snand_pre_read = mtk_snfc_pre_read_setting;
+ //nand->snand_pre_read = mtk_snfc_auto_read_setting;
+ nand->snand_pre_write = mtk_snfc_pre_write_setting;
+ nand->snand_post_write = mtk_snfc_post_write_setting;
+ nand->snand_auto_erase = mtk_snfc_auto_erase_setting;
+ nand->snand_get_feature = mtk_snfc_get_feature;
+ nand->snand_set_feature = mtk_snfc_set_feature;
+ /* SPI function */
+
+ nand->write_page_ecc_dma_irq = mtk_nfc_write_page_ecc_dma_irq;
+ nand->write_page_ecc_dma_polling = mtk_nfc_write_page_ecc_dma_polling;
+ nand->write_page_ecc_pio_irq = mtk_nfc_write_page_ecc_pio_irq;
+ nand->write_page_ecc_pio_polling = mtk_nfc_write_page_ecc_pio_polling;
+ nand->write_page_raw_dma_irq = mtk_nfc_write_page_raw_dma_irq;
+ nand->write_page_raw_dma_polling = mtk_nfc_write_page_raw_dma_polling;
+ nand->write_page_raw_pio_irq = mtk_nfc_write_page_raw_pio_irq;
+ nand->write_page_raw_pio_polling = mtk_nfc_write_page_raw_pio_polling;
+ nand->write_subpage_ecc_dma_irq = mtk_nfc_write_subpage_ecc_dma_irq;
+ nand->write_subpage_ecc_dma_polling = mtk_nfc_write_subpage_ecc_dma_polling;
+ nand->write_subpage_ecc_pio_irq = mtk_nfc_write_subpage_ecc_pio_irq;
+ nand->write_subpage_ecc_pio_polling = mtk_nfc_write_subpage_ecc_pio_polling;
+
+ nand->read_subpage_ecc_dma_irq = mtk_nfc_read_subpage_ecc_dma_irq;
+ nand->read_subpage_ecc_dma_polling = mtk_nfc_read_subpage_ecc_dma_polling;
+ nand->read_subpage_ecc_pio_irq = mtk_nfc_read_subpage_ecc_pio_irq;
+ nand->read_subpage_ecc_pio_polling = mtk_nfc_read_subpage_ecc_pio_polling;
+ nand->read_page_ecc_dma_irq = mtk_nfc_read_page_ecc_dma_irq;
+ nand->read_page_ecc_dma_polling = mtk_nfc_read_page_ecc_dma_polling;
+ nand->read_page_ecc_pio_irq = mtk_nfc_read_page_ecc_pio_irq;
+ nand->read_page_ecc_pio_polling = mtk_nfc_read_page_ecc_pio_polling;
+ nand->read_page_raw_dma_irq = mtk_nfc_read_page_raw_dma_irq;
+ nand->read_page_raw_dma_polling = mtk_nfc_read_page_raw_dma_polling;
+ nand->read_page_raw_pio_irq = mtk_nfc_read_page_raw_pio_irq;
+ nand->read_page_raw_pio_polling = mtk_nfc_read_page_raw_pio_polling;
+
+#if MT2731_DISABLE_RANDOMIZER
+ nand->enable_randomizer = mtk_nfc_randomizer_enable;
+ nand->disable_randomizer = mtk_nfc_randomizer_disable;
+#endif
+
+ nand->fill_oob_ecc = mtk_nfc_fill_oob_ecc;
+ nand->fill_oob_raw = mtk_nfc_fill_oob_raw;
+ nand->fill_oob_parity = mtk_nfc_fill_oob_parity;
+
+ nand->transfer_oob_ecc = mtk_nfc_transfer_oob_ecc;
+ nand->transfer_oob_raw = mtk_nfc_transfer_oob_raw;
+ nand->transfer_oob_parity = mtk_nfc_transfer_oob_parity;
+
+#if 0 /* MT2731_NOT_YET */
+ //mtk_nfc_gpio_init();
+#endif
+#if MT2731_DISABLE_RANDOMIZER
+ //mtk_nfc_randomizer_init(nand);
+#endif
+ mtk_nfc_hw_init(nand);
+
+ ret = mtk_ecc_hw_init(&nfc->ecc);
+ if (ret)
+ goto free_chip;
+
+ ret = mtk_snand_scan(nand, 1 /*MTK_NAND_MAX_NSELS*/);
+ if (ret)
+ goto free_ecc;
+
+ mtk_snfc_dev_ecc_control(nand, 0);
+ mtk_snfc_dev_unlock_blocks(nand);
+
+ mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, nand);
+ mtk_nfc_set_fdm(&chip->fdm, nand);
+ mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, nand);
+
+ nfc->buffer = (u8 *)memalign(16, nand->pagesize + nand->oobsize);
+ if (!nfc->buffer) {
+ ret = -ENOMEM;
+ goto free_databuf;
+ }
+
+ mutex_init(&nfc->lock);
+
+ ret = mtk_nand_scan_tail(nand);
+ if (ret)
+ goto free_buffer;
+
+ dprintf(INFO, "spi nand chip init done\n");
+ return 0;
+
+free_buffer:
+ free(nfc->buffer);
+free_databuf:
+ free(nand->databuf);
+free_ecc:
+ free(nfc->ecc);
+free_chip:
+ free(chip);
+free_nfc:
+ free(nfc);
+
+ return ret;
+}
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/drivers/nand/rules.mk b/src/bsp/lk/platform/mt2731/drivers/nand/rules.mk
new file mode 100644
index 0000000..161e76c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/nand/rules.mk
@@ -0,0 +1,18 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+MODULE := $(LOCAL_DIR)
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/mtk_ecc_hal.c \
+ $(LOCAL_DIR)/mtk_nfi_hal.c \
+ $(LOCAL_DIR)/mtk_nand_bbt.c \
+ $(LOCAL_DIR)/mtk_nand_device.c \
+ $(LOCAL_DIR)/mtk_nand_nal.c \
+ $(LOCAL_DIR)/mtk_nand_nftl.c \
+ $(LOCAL_DIR)/mtk_nand_test.c \
+
+MODULE_DEPS += \
+ lib/bio \
+ lib/nftl \
+ lib/partition \
+
+include make/module.mk
diff --git a/src/bsp/lk/platform/mt2731/drivers/pll/pll.c b/src/bsp/lk/platform/mt2731/drivers/pll/pll.c
new file mode 100644
index 0000000..878e8f4
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pll/pll.c
@@ -0,0 +1,427 @@
+#include <debug.h>
+#include <platform/pll.h>
+//#include <platform/spm.h>
+//#include <platform/spm_mtcmos.h>
+#include <platform/mt_typedefs.h>
+#include <platform/audio_clk_enable.h> /* for audio register */
+#include <reg.h>
+
+#define ALL_CLK_ON 1
+#define FMETER_EN 0
+
+/*
+ * mainpll/armpll is initialized in BROM. it's unnecessary to initialized again.
+ * here it is added temporary for DE simulation test.
+ */
+#define PLL_BROM_INIT 0
+
+#define udelay(x) spin(x)
+#define mdelay(x) udelay((x) * 1000)
+
+#define BIT(nr) (1UL << (nr))
+
+#define DRV_WriteReg32_Mask(addr, mask, val) \
+ DRV_WriteReg32(addr, (DRV_Reg32(addr) & ~(mask)) | (val))
+
+/* From Cervino. */
+static unsigned int mt_get_abist_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int temp, clk26cali_0, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1;
+
+ clk_dbg_cfg = DRV_Reg32(CLK_DBG_CFG);
+ //sel abist_cksw and enable freq meter sel abist
+ DRV_WriteReg32(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16));
+ clk_misc_cfg_0 = DRV_Reg32(CLK_MISC_CFG_0);
+ // select divider, WAIT CONFIRM, div 3, then output *4.
+ DRV_WriteReg32(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (0x3 << 24));
+ clk26cali_0 = DRV_Reg32(CLK26CALI_0);
+ clk26cali_1 = DRV_Reg32(CLK26CALI_1);
+ DRV_WriteReg32(CLK26CALI_0, 0x1000);
+ DRV_WriteReg32(CLK26CALI_0, 0x1010);
+
+ /* wait frequency meter finish */
+ while (DRV_Reg32(CLK26CALI_0) & 0x10)
+ {
+ mdelay(10);
+ i++;
+ if(i > 10) {
+ printf("<freqmeter>abist(%d), timeout\n", ID);
+ break;
+ }
+ }
+
+ temp = DRV_Reg32(CLK26CALI_1) & 0xFFFF;
+
+ output = ((temp * 26000) ) / 1024; // Khz
+
+ DRV_WriteReg32(CLK_DBG_CFG, clk_dbg_cfg);
+ DRV_WriteReg32(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ DRV_WriteReg32(CLK26CALI_0, clk26cali_0);
+ DRV_WriteReg32(CLK26CALI_1, clk26cali_1);
+
+ return output * 4;
+}
+
+static unsigned int mt_get_ckgen_freq(unsigned int ID)
+{
+ int output = 0, i = 0;
+ unsigned int temp, clk26cali_0, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1;
+
+ clk_dbg_cfg = DRV_Reg32(CLK_DBG_CFG);
+ //sel ckgen_cksw[22] and enable freq meter sel ckgen[21:16], 01:hd_faxi_ck
+ DRV_WriteReg32(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1));
+ clk_misc_cfg_0 = DRV_Reg32(CLK_MISC_CFG_0);
+ // select divider?dvt set zero
+ DRV_WriteReg32(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF));
+ clk26cali_0 = DRV_Reg32(CLK26CALI_0);
+ clk26cali_1 = DRV_Reg32(CLK26CALI_1);
+ DRV_WriteReg32(CLK26CALI_0, 0x1000);
+ DRV_WriteReg32(CLK26CALI_0, 0x1010);
+
+ /* wait frequency meter finish */
+ while (DRV_Reg32(CLK26CALI_0) & 0x10)
+ {
+ mdelay(10);
+ i++;
+ if(i > 10) {
+ printf("<freqmeter>ckgen(%d), timeout\n", ID);
+ break;
+ }
+ }
+
+ temp = DRV_Reg32(CLK26CALI_1) & 0xFFFF;
+
+ output = ((temp * 26000) ) / 1024; // Khz
+
+ DRV_WriteReg32(CLK_DBG_CFG, clk_dbg_cfg);
+ DRV_WriteReg32(CLK_MISC_CFG_0, clk_misc_cfg_0);
+ DRV_WriteReg32(CLK26CALI_0, clk26cali_0);
+ DRV_WriteReg32(CLK26CALI_1, clk26cali_1);
+
+ return output;
+}
+
+#if PLL_BROM_INIT
+/* Only for armpll and mainpll. */
+static void pll_brom_init(void)
+{
+ u32 temp;
+
+ /* xPLL PWR ON */
+ temp = DRV_Reg32(ARMPLL_CON3);
+ DRV_WriteReg32(ARMPLL_CON3, temp | 0x1); // [0]=1 (ARMPLL_PWR_ON)
+
+ temp = DRV_Reg32(MAINPLL_CON3);
+ DRV_WriteReg32(MAINPLL_CON3, temp | 0x1); // [0]=1 (MAINPLL_PWR_ON)
+
+ udelay(30); /* wait 30us */
+
+ temp = DRV_Reg32(ARMPLL_CON3);
+ DRV_WriteReg32(ARMPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (ARMPLL_ISO_EN)
+
+ temp = DRV_Reg32(MAINPLL_CON3);
+ DRV_WriteReg32(MAINPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (MAINPLL_ISO_EN)
+
+ udelay(1); /* wait 30us */
+ DRV_WriteReg32(ARMPLL_CON1, 0x8119F627); // [25:0] (ARMPLL_N_INFO, 1350MHz)
+ DRV_WriteReg32(MAINPLL_CON1, 0x81150000); // [21:0] (MAINPLL_N_INFO, 1092MHz)
+
+ /* xPLL Frequency Enable */
+ temp = DRV_Reg32(ARMPLL_CON0);
+ DRV_WriteReg32(ARMPLL_CON0, temp | 0x1); // [0]=1 (ARMPLL_EN)
+
+ temp = DRV_Reg32(MAINPLL_CON0);
+ DRV_WriteReg32(MAINPLL_CON0, temp | 0x1); // [0]=1 (MAINPLL_EN)
+
+ temp = DRV_Reg32(MAINPLL_CON0);
+ DRV_WriteReg32(MAINPLL_CON0, temp | 0xFF000000); // [0]=1 (MAINPLL_DIV_EN)
+
+ udelay(20); /* wait 20us */
+
+ temp = DRV_Reg32(MAINPLL_CON0);
+ DRV_WriteReg32(MAINPLL_CON0, temp | 0x00800000); // [0]=1 (MAINPLL_DIV_RSTB
+
+ /* ARM PLL */
+ DRV_WriteReg32_Mask(ACLKEN_DIV, ACLKEN_DIV_SEL_MASK, ACLKEN_DIV_SEL_HALF);
+ DRV_WriteReg32_Mask(BUS_PLL_DIVIDER_CFG, BUS_PLLDIV_MUX1SEL_MASK,
+ BUS_PLLDIV_MUX1SEL_ARMPLL);
+ //mb();
+}
+#endif
+
+static void pll_all_init(void)
+{
+ u32 temp;
+
+ temp = DRV_Reg32(AP_PLL_CON0);
+ DRV_WriteReg32(AP_PLL_CON0, temp | 0x01); // [0]=1 (CLKSQ_EN)
+
+ udelay(100); /* wait 100us */
+
+ temp = DRV_Reg32(AP_PLL_CON0);
+ DRV_WriteReg32(AP_PLL_CON0, temp | 0x2); // [1]=1 (CLKSQ_LPF_EN)
+
+#if PLL_BROM_INIT
+ pll_brom_init();
+#endif
+
+ /* xPLL PWR ON . ARMPLL has already been ok in BROM. */
+ //temp = DRV_Reg32(ARMPLL_CON3);
+ //DRV_WriteReg32(ARMPLL_CON3, temp | 0x1); // [0]=1 (ARMPLL_PWR_ON)
+
+ /* remove mpll operation */
+ //temp = DRV_Reg32(MPLL_CON3);
+ //DRV_WriteReg32(MPLL_CON3, temp | 0x1); // [0]=1 (MPLL_PWR_ON)
+
+ //temp = DRV_Reg32(MAINPLL_CON3);
+ //DRV_WriteReg32(MAINPLL_CON3, temp | 0x1); // [0]=1 (MAINPLL_PWR_ON)
+
+ temp = DRV_Reg32(UNIVPLL_CON3);
+ DRV_WriteReg32(UNIVPLL_CON3, temp | 0x1); // [0]=1 (UNIVPLL_PWR_ON)
+
+ temp = DRV_Reg32(MSDCPLL_CON3);
+ DRV_WriteReg32(MSDCPLL_CON3, temp | 0x1); // [0]=1 (MSDCPLL_PWR_ON)
+
+ temp = DRV_Reg32(APLL1_CON4);
+ DRV_WriteReg32(APLL1_CON4, temp | 0x1); // [0]=1 (APLL1_PWR_ON)
+
+ temp = DRV_Reg32(APLL2_CON4);
+ DRV_WriteReg32(APLL2_CON4, temp | 0x1); // [0]=1 (APLL1_PWR_ON)
+
+ temp = DRV_Reg32(ETHERPLL_CON3);
+ DRV_WriteReg32(ETHERPLL_CON3, temp | 0x1); // [0]=1 (APLL1_PWR_ON)
+
+ udelay(30); /* wait 30us */
+
+ //temp = DRV_Reg32(ARMPLL_CON3);
+ //DRV_WriteReg32(ARMPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (ARMPLL_ISO_EN)
+
+ /* remove mpll operation */
+ //temp = DRV_Reg32(MPLL_CON3);
+ //DRV_WriteReg32(MPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (MPLL_ISO_EN)
+
+ //temp = DRV_Reg32(MAINPLL_CON3);
+ //DRV_WriteReg32(MAINPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (MAINPLL_ISO_EN)
+
+ temp = DRV_Reg32(UNIVPLL_CON3);
+ DRV_WriteReg32(UNIVPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (UNIVPLL_ISO_EN)
+
+ temp = DRV_Reg32(MSDCPLL_CON3);
+ DRV_WriteReg32(MSDCPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (MSDCPLL_ISO_EN)
+
+ temp = DRV_Reg32(APLL1_CON4);
+ DRV_WriteReg32(APLL1_CON4, temp & 0xFFFFFFFD); // [1]=0 (APLL1_ISO_EN)
+
+ temp = DRV_Reg32(APLL2_CON4);
+ DRV_WriteReg32(APLL2_CON4, temp & 0xFFFFFFFD); // [1]=0 (APLL1_ISO_EN)
+
+ temp = DRV_Reg32(ETHERPLL_CON3);
+ DRV_WriteReg32(ETHERPLL_CON3, temp & 0xFFFFFFFD); // [1]=0 (MMPLL_ISO_EN)
+
+ udelay(1); /* wait 30us */
+
+ /* xPLL Frequency Set */
+ //DRV_WriteReg32(ARMPLL_CON1, 0x8119F627); // [25:0] (ARMPLL_N_INFO, 1350MHz)
+ /* remove mpll operation */
+ //DRV_WriteReg32(MPLL_CON1, 0x83100000); // [21:0] (MPLL_N_INFO, 208MHz)
+ //DRV_WriteReg32(MAINPLL_CON1, 0x81150000); // [21:0] (MAINPLL_N_INFO, 1092MHz)
+ DRV_WriteReg32(UNIVPLL_CON1, 0x80180000); // [21:0] (UNIVPLL_N_INFO, 1248MHz)
+ DRV_WriteReg32(MSDCPLL_CON1, 0x831C4EC4); // [21:0] (MSDCPLL_N_INFO,
+ // 400MHz->384->368M, for MSDC1/2)
+
+ //cervino: 0x83000000.
+ DRV_WriteReg32(APLL1_CON1, 0x84000000); // [21:0] = LSB of APLL1_N_INFO, postdiv
+ DRV_WriteReg32(APLL1_CON2, 0x78FD5265); // [23:14] = MSB of APLL1_N_INFO, 196.608MHz
+ DRV_WriteReg32(APLL2_CON1, 0x84000000); // [21:0] = LSB of APLL1_N_INFO,postdiv
+ DRV_WriteReg32(APLL2_CON2, 0x6F28BD4C); // [23:14] = MSB of APLL1_N_INFO, 180.6336MHz
+ DRV_WriteReg32(APLL1_TUNER_CON0, 0x3C7EA933); // [23:14] = MSB of APLL1_N_INFO,
+
+ DRV_WriteReg32(ETHERPLL_CON1, 0x82133B13); // [21:0] = LSB of APLL1_N_INFO, 500MHz
+
+ /* xPLL Frequency Enable */
+ //temp = DRV_Reg32(ARMPLL_CON0);
+ //DRV_WriteReg32(ARMPLL_CON0, temp | 0x1); // [0]=1 (ARMPLL_EN)
+
+ /* remove mpll operation */
+ //temp = DRV_Reg32(MPLL_CON0);
+ //DRV_WriteReg32(MPLL_CON0, temp | 0x1); // [0]=1 (MPLL_EN)
+
+ //temp = DRV_Reg32(MAINPLL_CON0);
+ //DRV_WriteReg32(MAINPLL_CON0, temp | 0x1); // [0]=1 (MAINPLL_EN)
+
+ temp = DRV_Reg32(UNIVPLL_CON0);
+ DRV_WriteReg32(UNIVPLL_CON0, temp | 0x1); // [0]=1 (UNIVPLL_EN)
+
+ temp = DRV_Reg32(MSDCPLL_CON0);
+ DRV_WriteReg32(MSDCPLL_CON0, temp | 0x1); // [0]=1 (MSDCPLL_EN)
+
+ temp = DRV_Reg32(APLL1_CON0);
+ DRV_WriteReg32(APLL1_CON0, temp | 0x1); // [0]=1 (APLL1_EN)
+
+ temp = DRV_Reg32(APLL2_CON0);
+ DRV_WriteReg32(APLL2_CON0, temp | 0x1); // [0]=1 (APLL1_EN)
+
+ temp = DRV_Reg32(ETHERPLL_CON0);
+ DRV_WriteReg32(ETHERPLL_CON0, temp | 0x1); // [0]=1 (ETHHERPLL_EN)
+
+ //temp = DRV_Reg32(MAINPLL_CON0);
+ //DRV_WriteReg32(MAINPLL_CON0, temp | 0xFF000000); // [0]=1 (MAINPLL_DIV_EN)
+
+ temp = DRV_Reg32(UNIVPLL_CON0);
+ DRV_WriteReg32(UNIVPLL_CON0, temp | 0xFF000000); // [0]=1 (UNIVPLL_DIV_EN)
+
+ udelay(20); /* wait 20us */
+
+ //temp = DRV_Reg32(MAINPLL_CON0);
+ //DRV_WriteReg32(MAINPLL_CON0, temp | 0x00800000); // [0]=1 (MAINPLL_DIV_RSTB
+
+ temp = DRV_Reg32(UNIVPLL_CON0);
+ DRV_WriteReg32(UNIVPLL_CON0, temp | 0x00800000); // [0]=1 (UNIVPLL_DIV_RSTB)
+
+ udelay(20); /* wait 20us */
+ /* xPLL HW Control */
+ temp = DRV_Reg32(PLLON_CON1);
+ DRV_WriteReg32(PLLON_CON1, temp & 0xfffffffb); // [2]=0 use HW delay mode (by_maindiv_dly)
+}
+
+/* Only _CLR, _SET is allowed.*/
+static void _clk_mux_sel(unsigned long cfg_clr, unsigned long cfg_set,
+ unsigned int bits_nr, unsigned int shift,
+ unsigned int sel_id, //No shift
+ unsigned int pdn_bit)
+{
+ u32 mask = (1 << bits_nr) - 1;
+
+ DRV_WriteReg32(cfg_clr, mask << shift);
+ DRV_WriteReg32(cfg_set, sel_id << shift);
+ //DRV_WriteReg32(cfg_clr, pdn_bit); //pdn bit default is 0(clk on). No need.
+}
+
+#define CLK_MUX_SEL(cfg, bits_nr, shift, sel_id, pdn_bit) \
+ _clk_mux_sel(cfg##_CLR, cfg##_SET, bits_nr, shift, sel_id, pdn_bit)
+
+static void clk_mux_init(void)
+{
+#if PLL_BROM_INIT
+ // config AXI clock first..bootrom do this.
+ CLK_MUX_SEL(CLK_CFG_0, 3, 0, 1, 7); //axi: syspll2_d2
+ DRV_WriteReg32(CLK_CFG_UPDATE, 0x1); //update axi
+#endif
+ CLK_MUX_SEL(CLK_CFG_0, 1, 8, 0, 15); //uart: univpll2_d8
+ CLK_MUX_SEL(CLK_CFG_0, 2, 16, 1, 23); //spi: syspll3_d2
+ CLK_MUX_SEL(CLK_CFG_0, 2, 24, 1, 31); //msd50_0_hclk_sel: syspll1_d2
+
+ CLK_MUX_SEL(CLK_CFG_1, 3, 0, 4, 7); //msdc50_0 : univpll1_d2
+ CLK_MUX_SEL(CLK_CFG_1, 3, 8, 1, 15); //msdc30_1: msdcpll_d2
+ CLK_MUX_SEL(CLK_CFG_1, 2, 16, 1, 23); //audio_sel: syspll3_d4
+ CLK_MUX_SEL(CLK_CFG_1, 2, 24, 1, 31); //aud_intbus_sel: syspll1_d4
+
+ CLK_MUX_SEL(CLK_CFG_2, 1, 0, 1, 7); //aud_1_sel: ad_apll1_ck
+ CLK_MUX_SEL(CLK_CFG_2, 1, 8, 1, 15); //aud_2_sel: ad_apll2_ck
+ CLK_MUX_SEL(CLK_CFG_2, 2, 16, 3, 23); //aud_engen1_sel: apll1_d8
+ CLK_MUX_SEL(CLK_CFG_2, 2, 24, 3, 31); //aud_engen2_sel: apll2_d8
+
+ CLK_MUX_SEL(CLK_CFG_3, 2, 0, 1, 7); //dxcc: syspll1_d2
+ CLK_MUX_SEL(CLK_CFG_3, 2, 8, 3, 15); //hsm_crypto_sel: univpll1_d2
+ CLK_MUX_SEL(CLK_CFG_3, 2, 16, 3, 23); //hsm_arc_sel: syspll2_d2
+ CLK_MUX_SEL(CLK_CFG_3, 2, 24, 3, 31); //gcpu_sel: syspll_d3
+
+ CLK_MUX_SEL(CLK_CFG_4, 2, 0, 3, 7); //ecc_sel: univpll_d3
+ CLK_MUX_SEL(CLK_CFG_4, 2, 8, 2, 15); //usb_top_sel: usb20_192m_d2
+ CLK_MUX_SEL(CLK_CFG_4, 1, 16, 1, 23); //spm_sel: syspll1_d8
+ CLK_MUX_SEL(CLK_CFG_4, 3, 24, 2, 31); //i2c_sel: univpll3_d2
+
+ CLK_MUX_SEL(CLK_CFG_5, 1, 0, 0, 7); //pwrap_ulposc_sel: top_ap_clk_ctrl_f26m_ck
+ CLK_MUX_SEL(CLK_CFG_5, 2, 8, 1, 15); //msdc50_2_hclk_sel: syspll1_d2
+ CLK_MUX_SEL(CLK_CFG_5, 3, 16, 1, 23); //msdc30_2_sel: msdcpll_ck
+ CLK_MUX_SEL(CLK_CFG_5, 3, 24, 6, 31); //nfi1x_bclk_sel: syspll2_d4
+
+ CLK_MUX_SEL(CLK_CFG_6, 3, 0, 0, 7); //spinfi_bclk_sel: top_ap_clk_ctrl_f26m_ck
+ CLK_MUX_SEL(CLK_CFG_6, 2, 8, 3, 15); //pcie_mac_sel: syspll1_d4
+ CLK_MUX_SEL(CLK_CFG_6, 2, 16, 2, 23); //ssusb_top_sel: univpll3_d2
+ CLK_MUX_SEL(CLK_CFG_6, 3, 24, 7, 31); //spislv_sel: univpll_d3
+
+ CLK_MUX_SEL(CLK_CFG_7, 1, 0, 1, 7); //ether_125_sel: etherpll_d4
+ CLK_MUX_SEL(CLK_CFG_7, 1, 8, 1, 15); //ether_50m_rmii_sel: etherpp_d10
+ CLK_MUX_SEL(CLK_CFG_7, 1, 16, 1, 23); //ether_62p4m_sel: univpll3_d4
+ CLK_MUX_SEL(CLK_CFG_7, 1, 24, 1, 31); //pwm_sel: univpll3_d4
+
+ //cervino bit1: mem: 0xFFFF_FFFC.
+ DRV_WriteReg32(CLK_CFG_UPDATE, 0xFFFFFFFE); //update all clocks except "axi"
+}
+
+static void clk_cg_all_on(void)
+{
+ //arm-div-pll0 is off.
+ DRV_WriteReg32_Mask(CLK_MISC_CFG_0, 0xf30, 0xf30);
+ DRV_WriteReg32_Mask(CLK_AUDDIV_0, 0xfc, 0);
+ //DRV_WriteReg32_Mask(PERI_BUS_DCM_CTRL, 0x4, 0);
+ //PERIAXI_SI0_CTL: PERIAXI_CG_DISABLE
+
+ DRV_WriteReg32_Mask(GCE_CTL_INT0, 0x10000, 0x0);
+ DRV_WriteReg32_Mask(AUDIO_TOP_CON0, 0x1f0c0304, 0x0);
+ DRV_WriteReg32_Mask(AUDIO_TOP_CON1, 0x3f0, 0x0);
+
+ //bit31: BTIF:de-feature
+ DRV_WriteReg32(MODULE_SW_CG_0_SET, BIT(31) | 0x20);
+ DRV_WriteReg32(MODULE_SW_CG_0_CLR, 0x1bffff40);//skip pmic-cg
+ //disable AUX/CPUM/XIU and enable TRNG.
+ DRV_WriteReg32(MODULE_SW_CG_1_SET, BIT(10)| BIT(9)|BIT(14)|BIT(19));
+ DRV_WriteReg32(MODULE_SW_CG_1_CLR, 0xfd97b9b6);
+ //disable I2C4/5:bit7,18..24;bit28:BIST2FPC
+ DRV_WriteReg32(MODULE_SW_CG_2_SET, 0x11fc0080);
+ DRV_WriteReg32(MODULE_SW_CG_2_CLR, 0x70007cb);
+ //no SSPM:bit3/4;ccif3:bit20/21.
+ //disable MSDC self bit0/1/2; AP/MD MSDC0 bit7/8
+ DRV_WriteReg32(MODULE_SW_CG_3_SET, 0x30019f);
+ DRV_WriteReg32(MODULE_SW_CG_3_CLR, 0x01cffe40);
+
+ /* Defaultly all clock on. Disable HSM clock if it has no HSM. */
+ #if !defined(ENABLE_HSM_CLK)
+ DRV_WriteReg32(MODULE_SW_CG_1_SET, BIT(27)| BIT(28));
+ DRV_WriteReg32(CLK_CFG_3_SET, BIT(15)| BIT(23));
+ #endif
+}
+
+/* after pmic_init */
+void mt_pll_post_init(void)
+{
+#if FMETER_EN
+ unsigned int freq_out, i;
+
+ //abist.
+ for (i = 1; i < 64; i++) {
+ if (i >= 36 && i <= 59)
+ continue;//1'b0
+ //TODO: i:23: mcusys_arm_clk_out_all.
+ //divider and test.
+ freq_out = mt_get_abist_freq(i);
+ printf("<freqmeter>abist: %d, freq %d\n", i, freq_out);
+ }
+ //ckgen.
+ for (i = 1; i < 59; i++) {
+ if ((i >= 33 && i <= 49) || i == 54)
+ continue;//1'b0
+
+ freq_out = mt_get_ckgen_freq(i);
+ printf("<freqmeter>ckgen: %d, freq %d\n", i, freq_out);
+ }
+#endif
+}
+
+void mt_pll_init(void)
+{
+ pll_all_init();
+
+ //armpll div is in BROM
+
+ // [22] set this register before AXI clock switch to fast clock (26MHz => 156MHz)
+ //DRV_WriteReg32(INFRA_BUS_DCM_CTRL, DRV_Reg32(INFRA_BUS_DCM_CTRL) | (1 << 21) | (1 << 22));
+ //spm axi dcm enable. mt2731 move the setting to VDNR.
+ DRV_WriteReg32_Mask(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
+ 0x3, 0x3);
+
+ clk_mux_init();
+ clk_cg_all_on();
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mt6389.c b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mt6389.c
new file mode 100755
index 0000000..90532e8
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mt6389.c
@@ -0,0 +1,622 @@
+#include <sys/types.h>
+#include <platform.h>
+#include <platform/MT6389/pmic.h>
+#include <platform/MT6389/mt6389.h>
+#include <platform/regulator/mtk_regulator.h>
+
+#ifdef LDO_SUPPORT
+static const unsigned int vgp3_volts[] = {
+ 1200000,
+ 1300000,
+ 1400000,
+ 1500000,
+ 1600000,
+ 1700000,
+ 1800000,
+};
+
+static const unsigned int vdram2_volts[] = {
+ 600000,
+ 1800000,
+};
+
+static const unsigned int vsim1_volts[] = {
+ 1700000,
+ 1800000,
+ 2700000,
+ 3000000,
+ 3100000,
+};
+
+static const unsigned int vusb_volts[] = {
+ 3000000,
+};
+
+static const unsigned int vgp1_volts[] = {
+ 1200000,
+ 1300000,
+ 1500000,
+ 1700000,
+ 1800000,
+ 2000000,
+ 2800000,
+ 3000000,
+ 3300000,
+};
+
+static const unsigned int vmch_volts[] = {
+ 2900000,
+ 3000000,
+ 3100000,
+ 3300000,
+};
+
+static const unsigned int vgp2_volts[] = {
+ 1200000,
+ 1300000,
+ 1500000,
+ 1700000,
+ 1800000,
+ 2000000,
+ 2800000,
+ 3000000,
+ 3300000,
+};
+
+static const unsigned int vsim2_volts[] = {
+ 1700000,
+ 1800000,
+ 2700000,
+ 3000000,
+ 3100000,
+};
+
+static const unsigned int vgp3_idxs[] = {
+ 6, 7, 8, 9, 10, 11, 12,
+};
+
+static const unsigned int vdram2_idxs[] = {
+ 0, 12,
+};
+
+static const unsigned int vsim1_idxs[] = {
+ 3, 4, 8, 11, 12,
+};
+
+static const unsigned int vusb_idxs[] = {
+ 12,
+};
+
+static const unsigned int vgp1_idxs[] = {
+ 0, 1, 2, 3, 4, 5, 9, 11, 13,
+};
+
+static const unsigned int vmch_idxs[] = {
+ 10, 11, 12, 13,
+};
+
+static const unsigned int vgp2_idxs[] = {
+ 0, 1, 2, 3, 4, 5, 9, 11, 13,
+};
+
+static const unsigned int vsim2_idxs[] = {
+ 3, 4, 8, 11, 12,
+};
+
+static struct mt6389_ldo_info ldo_ext_info[] = {
+ mt6389_ldo_decl(vgp3_volts, vgp3_idxs),
+ mt6389_ldo_decl(vdram2_volts, vdram2_idxs),
+ mt6389_ldo_decl(vsim1_volts, vsim1_idxs),
+ mt6389_ldo_decl(vusb_volts, vusb_idxs),
+ mt6389_ldo_decl(vgp1_volts, vgp1_idxs),
+ mt6389_ldo_decl(vmch_volts, vmch_idxs),
+ mt6389_ldo_decl(vgp2_volts, vgp2_idxs),
+ mt6389_ldo_decl(vsim2_volts, vsim2_idxs),
+};
+#endif /*--LDO_SUPPORT--*/
+
+
+#ifdef LDO_VOTRIM_SUPPORT
+static const int votrim_1_type[] = {
+ 0, (-1)*20000, (-1)*40000, (-1)*60000, (-1)*80000, (-1)*100000, (-1)*120000, (-1)*140000,
+ 160000, 140000, 1200000, 100000, 80000, 60000, 40000, 20000,
+};
+
+static const int votrim_2_type[] = {
+ 0, (-1)*10000, (-1)*20000, (-1)*30000, (-1)*40000, (-1)*50000, (-1)*60000, (-1)*70000,
+ 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000,
+};
+
+static struct mt6389_ldo_trim_info ldo_trim_info[] = {
+ mt6389_ldo_trim_decl(vio28, votrim_1_type),
+ mt6389_ldo_trim_decl(vio18, votrim_2_type),
+ mt6389_ldo_trim_decl(va12, votrim_2_type),
+ mt6389_ldo_trim_decl(vusb, votrim_1_type),
+};
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+
+static struct mt6389_regulator_info mt6389_regu_info[] = {
+/*--NON SSPM MODE--*/
+ mt6389_decl(vs1),
+ mt6389_decl(vdram1),
+ mt6389_decl(vmodem),
+ mt6389_decl(vcore),
+ mt6389_decl(vsram_others),
+ mt6389_decl(vproc),
+ mt6389_decl(vs2),
+#ifdef LDO_SUPPORT
+ mt6389_decl(vgp3),
+ mt6389_decl(vdram2),
+ mt6389_decl(vsim1),
+ mt6389_decl(vusb),
+ mt6389_decl(vsram_proc),
+ mt6389_decl(vgp1),
+ mt6389_decl(vmch),
+ mt6389_decl(vgp2),
+ mt6389_decl(vsim2),
+#endif /*--LDO_SUPPORT--*/
+};
+
+static unsigned char regu_size = ARRAY_SIZE(mt6389_regu_info);
+
+static int mt6389_set_voltage(unsigned char id, unsigned int volt, unsigned int max_volt) {
+ unsigned short selector = 0;
+ int ret = 0;
+
+ if (volt > mt6389_regu_info[id].max_uV ||
+ volt < mt6389_regu_info[id].min_uV) {
+ mreg_dbg_print("vp\n");
+ return -1;
+ }
+
+ if (mt6389_regu_info[id].rtype == REGULAR_VOLTAGE) {
+ selector = DIV_ROUND_UP((volt - mt6389_regu_info[id].min_uV),
+ mt6389_regu_info[id].step_uV);
+#ifdef LDO_SUPPORT
+ } else if (mt6389_regu_info[id].rtype == NON_REGULAR_VOLTAGE) {
+ selector = mt6389_ldo_convert_data(id, volt, VOLTOSEL);
+ if (selector == 0xFFFF) {
+ mreg_dbg_print("vnf\n"); /* voltage not found */
+ return -1;
+ }
+ } else if (mt6389_regu_info[id].rtype == FIXED_REGULAR_VOLTAGE) {
+ if (mt6389_ldo_convert_data(id, volt, VOLTOSEL) == 0)
+ return 0;
+ else {
+ mreg_dbg_print("vswf\n");
+ return -1;
+ }
+ }
+#else
+ } else {
+ mreg_dbg_print("ldo not support\n");
+ return -1;
+ }
+#endif /*--LDO_SUPPORT--*/
+
+ mreg_dbg_print("1 %d,%d\n", id, selector);
+
+ ret = pmic_config_interface(mt6389_regu_info[id].vol_reg, selector,
+ mt6389_regu_info[id].vol_mask,
+ mt6389_regu_info[id].vol_shift);
+ return ret;
+}
+
+static int mt6389_get_voltage(unsigned char id)
+{
+ unsigned int selector = 0;
+ unsigned int volt = 0;
+ int ret = 0;
+
+ if (mt6389_regu_info[id].da_vol_reg != 0) {
+ ret = pmic_read_interface(
+ mt6389_regu_info[id].da_vol_reg, &selector,
+ mt6389_regu_info[id].da_vol_mask,
+ mt6389_regu_info[id].da_vol_shift);
+ } else {
+ ret = pmic_read_interface(
+ mt6389_regu_info[id].vol_reg, &selector,
+ mt6389_regu_info[id].vol_mask,
+ mt6389_regu_info[id].vol_shift);
+ }
+
+ if (ret)
+ return -1;
+
+ if (mt6389_regu_info[id].rtype == REGULAR_VOLTAGE)
+ volt = ((selector * mt6389_regu_info[id].step_uV) + mt6389_regu_info[id].min_uV);
+#ifdef LDO_SUPPORT
+ else if (mt6389_regu_info[id].rtype == NON_REGULAR_VOLTAGE)
+ volt = mt6389_ldo_convert_data(id, selector, SELTOVOL);
+ else if (mt6389_regu_info[id].rtype == FIXED_REGULAR_VOLTAGE) {
+ volt = *((int *)(mt6389_regu_info[id].extinfo->pvoltages));
+ }
+#else
+ else
+ return -1;
+#endif /*--LDO_SUPPORT--*/
+
+ mreg_dbg_print("get volt %d, %d, %d\n", id, selector, volt);
+ if (volt > mt6389_regu_info[id].max_uV || volt < mt6389_regu_info[id].min_uV) {
+ mreg_dbg_print("vgw\n");
+ return -1;
+ }
+
+ return volt;
+}
+
+static int mt6389_enable(unsigned char id, unsigned char en)
+{
+ int ret = 0;
+
+ if (mt6389_regu_info[id].enable_reg == 0)
+ return -1;
+ mreg_dbg_print("2 %d,%d\n", id, en);
+ ret = pmic_config_interface(mt6389_regu_info[id].enable_reg, en, 0x1,
+ mt6389_regu_info[id].enable_shift);
+
+ return ret;
+}
+
+static int mt6389_is_enabled(unsigned char id)
+{
+ unsigned int en = 0;
+ unsigned int ret = 0;
+
+ if (mt6389_regu_info[id].enable_reg == 0)
+ return -1;
+ ret = pmic_read_interface(mt6389_regu_info[id].enable_reg, &en, 0x1,
+ mt6389_regu_info[id].enable_shift);
+ mreg_dbg_print("3 %d,%d\n", id, en);
+
+ return (ret ? ret : en) ;
+}
+
+static int mt6389_set_mode(unsigned char id, unsigned char mode)
+{
+ int ret = 0;
+
+ if (mt6389_regu_info[id].mode_reg == 0)
+ return -1;
+ mreg_dbg_print("4 %d,%d\n", id, mode);
+ ret = pmic_config_interface(mt6389_regu_info[id].mode_reg, mode, 0x1,
+ mt6389_regu_info[id].mode_shift);
+
+ return ret;
+}
+
+static int mt6389_get_mode(unsigned char id)
+{
+ int mode = 0;
+ int ret = 0;
+
+ if (mt6389_regu_info[id].mode_reg == 0)
+ return -1;
+ ret = pmic_read_interface(mt6389_regu_info[id].mode_reg, &mode, 0x1,
+ mt6389_regu_info[id].mode_shift);
+ mreg_dbg_print("5 %d,%d\n", id, mode);
+
+ return (ret ? ret: mode);
+}
+
+#ifdef LDO_VOTRIM_SUPPORT
+static int mt6389_ldo_votrim_convert_data(unsigned char id, int cnvdata, trimseltran transtype)
+{
+ int i = 0, trim_size = 0, choice = -1;
+ const int *trim_Voltage;
+
+ if ((mt6389_regu_info[id].triminfo->trim_voltages != NULL)) {
+ trim_Voltage = mt6389_regu_info[id].triminfo->trim_voltages;
+ trim_size = mt6389_regu_info[id].triminfo->trim_size;
+ mreg_dbg_print("votrim_size %d, cnvdata %d\n", trim_size, cnvdata);
+ switch (transtype) {
+ case TRIMTOSEL:
+ if (cnvdata > 0) {
+ for (i = trim_size/2; i < trim_size; i++) {
+ choice = i;
+ if (trim_Voltage[i] <= cnvdata) {
+ dbg_print("trim_Voltage:%d, cnvdata:%d\n", trim_Voltage[i], cnvdata);
+ break;
+ }
+ }
+ } else if (cnvdata < 0) {
+ for (i = trim_size/2 - 1; i >= 0; i--) {
+ choice = i;
+ if (trim_Voltage[i] >= cnvdata) {
+ dbg_print("trim_Voltage:%d, cnvdata:%d\n", trim_Voltage[i], cnvdata);
+ break;
+ }
+ }
+ } else
+ choice = 0;
+ break;
+ case SELTOTRIM:
+ choice = trim_Voltage[cnvdata];
+ break;
+ default:
+ break;
+ }
+ }
+
+ return choice;
+}
+
+static int mt6389_set_votrim(unsigned char id, int trim_volt) {
+ int selector = 0;
+ int ret = 0;
+
+ selector = mt6389_ldo_votrim_convert_data(id, trim_volt, TRIMTOSEL);
+ if (selector == -1)
+ return -1;
+
+ if ((mt6389_regu_info[id].triminfo->trim_voltages != NULL)) {
+ mreg_dbg_print("6 %d,%d\n", id, selector);
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9CA6,
+ PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+ ret = pmic_config_interface(
+ mt6389_regu_info[id].triminfo->trim_reg,
+ (unsigned int)selector, 0xF, 0);
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0,
+ PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+ }
+
+ return ret;
+}
+
+static int mt6389_get_votrim(unsigned char id)
+{
+ unsigned int selector = 0;
+ int ret = 0;
+
+ ret = pmic_read_interface(mt6389_regu_info[id].triminfo->trim_reg,
+ &selector, 0xF, 0);
+ if (ret)
+ return -1;
+
+ ret = mt6389_ldo_votrim_convert_data(id, selector, SELTOTRIM);
+
+ mreg_dbg_print("7 %d,%d,%d\n", id, selector,ret);
+
+ return ret;
+}
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+
+#ifdef LDO_SUPPORT
+static unsigned int mt6389_ldo_convert_data(unsigned char id, unsigned int cnvdata, volseltran transtype)
+{
+ int i = 0, n_size = 0;
+ unsigned int choice = 0xFFFF;
+ const unsigned int *pVoltage;
+ const unsigned int *iDx;
+
+ if ((mt6389_regu_info[id].extinfo->pvoltages != NULL) && (mt6389_regu_info[id].extinfo->idxs != NULL)) {
+ pVoltage = mt6389_regu_info[id].extinfo->pvoltages;
+ iDx = mt6389_regu_info[id].extinfo->idxs;
+ n_size = mt6389_regu_info[id].extinfo->n_size;
+ mreg_dbg_print("cnvdata %d, n_size %d\n", cnvdata, n_size);
+ for (i = 0; i <= n_size; i++) {
+ if (transtype == VOLTOSEL && pVoltage[i] == cnvdata) {
+ choice = iDx[i];
+ break;
+ } else if (transtype == SELTOVOL && iDx[i] == cnvdata) {
+ choice = pVoltage[i];
+ break;
+ }
+ }
+ }
+
+ return choice;
+}
+#endif /*--LDO_SUPPORT--*/
+
+static struct regulator_ctrl mt6389_regulator_ctrl = {
+ .set_voltage = mt6389_set_voltage,
+ .get_voltage = mt6389_get_voltage,
+ .enable = mt6389_enable,
+ .is_enabled = mt6389_is_enabled,
+ .set_mode = mt6389_set_mode,
+ .get_mode = mt6389_get_mode,
+#ifdef LDO_VOTRIM_SUPPORT
+ .set_votrim = mt6389_set_votrim,
+ .get_votrim = mt6389_get_votrim,
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+};
+
+static struct mtk_regulator mt6389_regulator[] = {
+ /*--NON SSPM MODE--*/
+ {
+ .name = "vs1",
+ .id = MTK_REGULATOR_VS1,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vdram1",
+ .id = MTK_REGULATOR_VDRAM1,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vmodem",
+ .id = MTK_REGULATOR_VMODEM,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vcore",
+ .id = MTK_REGULATOR_VCORE,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vsram_others",
+ .id = MTK_REGULATOR_VSRAM_OTHERS,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vproc",
+ .id = MTK_REGULATOR_VPROC,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vs2",
+ .id = MTK_REGULATOR_VS2,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+#ifdef LDO_SUPPORT
+ {
+ .name = "vgp3",
+ .id = MTK_REGULATOR_VGP3,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vdram2",
+ .id = MTK_REGULATOR_VDRAM2,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vsim1",
+ .id = MTK_REGULATOR_VSIM1,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vusb",
+ .id = MTK_REGULATOR_VUSB,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vfe28",
+ .id = MTK_REGULATOR_VFE28,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vsram_proc",
+ .id = MTK_REGULATOR_VSRAM_PROC,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vgp1",
+ .id = MTK_REGULATOR_VGP1,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vmch",
+ .id = MTK_REGULATOR_VMCH,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vgp2",
+ .id = MTK_REGULATOR_VGP2,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+ {
+ .name = "vsim2",
+ .id = MTK_REGULATOR_VSIM2,
+ .reg_ops = &mt6389_regulator_ctrl,
+ },
+#endif /*--LDO_SUPPORT--*/
+};
+
+#if 0
+struct mtk_regulator_track_info {
+ struct mtk_regulator *mreg;
+ unsigned char sram_id;
+ unsigned short offset_reg;
+ unsigned short offset_mask;
+ unsigned short offset_shift;
+ unsigned short lb_reg;
+ unsigned short lb_mask;
+ unsigned short lb_shift;
+ unsigned short hb_reg;
+ unsigned short hb_mask;
+ unsigned short hb_shift;
+ unsigned short track_en_reg;
+ unsigned short track_en_mask;
+ unsigned short track_en_shift;
+};
+
+static struct mtk_regulator_track_info mreg_track_info = {
+ {
+ .mreg = &mt6389_regulator[MTK_REGULATOR_VPROC],
+ .sram_id = MTK_REGULATOR_VSRAM_PROC,
+ .offset_reg = PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_ADDR,
+ .offset_mask = PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_MASK,
+ .offset_shift = PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_SHIFT,
+ .lb_reg = PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_ADDR,
+ .lb_mask = PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_MASK,
+ .lb_shift = PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_SHIFT,
+ .hb_reg = PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_ADDR,
+ .hb_mask = PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_MASK,
+ .hb_shift = PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_SHIFT,
+ .track_en_reg = PMIC_RG_LDO_VSRAM_PROC_TRACK_EN_ADDR,
+ .track_en_mask = 0x3,
+ .track_en_shift = 0,
+ },
+};
+
+int hw_tracking_set(const char *name, bool en,
+ int offset, unsigned int lb, unsigned int hb)
+{
+ int i;
+ unsigned char id, sram_id;
+ struct mt6389_regulator_info *vproc_info = NULL, *vsram_info = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(mreg_track_info); i++) {
+ if (strcmp(mreg_track_info.mreg->name, name) == 0) {
+ id = mreg_track_info.mreg->id;
+ sram_id = mreg_track_info.sram_id;
+ vproc_info = &mt6389_regu_info[id];
+ vsram_info = &mt6389_regu_info[sram_id];
+ break;
+ }
+ }
+ if (vproc_info == NULL)
+ return -1;
+
+ pmic_config_interface(mreg_track_info.offset_reg,
+ (offset - (vsram_info->min_uV - vproc_info->min_uV)) / vsram_info->step_uV,
+ mreg_track_info.offset_mask,
+ mreg_track_info.offset_shift);
+
+ pmic_config_interface(mreg_track_info.lb_reg,
+ (lb - vsram_info->min_uV) / vsram_info->step_uV,
+ mreg_track_info.lb_mask,
+ mreg_track_info.lb_shift);
+
+ pmic_config_interface(mreg_track_info.hb_reg,
+ (hb - vsram_info->min_uV) / vsram_info->step_uV,
+ mreg_track_info.hb_mask,
+ mreg_track_info.hb_shift);
+
+ pmic_config_interface(mreg_track_info.track_en_reg,
+ en ? mreg_track_info.track_en_mask : 0,
+ mreg_track_info.track_en_mask,
+ mreg_track_info.track_en_shift);
+ return 0;
+}
+#endif
+
+/* ====================
+ * Driver operations
+ * ====================
+ */
+int mt6389_probe(void)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < regu_size; i++) {
+#ifdef LDO_SUPPORT
+ if (mt6389_regu_info[i].rtype != REGULAR_VOLTAGE && i >= MTK_REGULATOR_LDO_SUPPORT)
+ mt6389_regu_info[i].extinfo = &ldo_ext_info[(i-MTK_REGULATOR_LDO_SUPPORT)];
+#endif /*--LDO_SUPPORT--*/
+#ifdef LDO_VOTRIM_SUPPORT
+ if (mt6389_regu_info[i].rtype != REGULAR_VOLTAGE && i >= MTK_REGULATOR_LDO_SUPPORT)
+ mt6389_regu_info[i].triminfo = &ldo_trim_info[(i-MTK_REGULATOR_LDO_SUPPORT)];
+#endif /*--LDO_SUPPORT--*/
+ ret = mtk_simple_regulator_register(&mt6389_regulator[i]);
+ if (ret < 0) {
+ /* register mtk regulator error */
+ mreg_dbg_print("[PMIC] regulator %s\n", mt6389_regulator[i].name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mtk_regulator_core.c b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mtk_regulator_core.c
new file mode 100644
index 0000000..3756721
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/mtk_regulator_core.c
@@ -0,0 +1,95 @@
+#include <string.h>
+#include <debug.h>
+#include <platform/MT6389/mtk_regulator_core.h>
+#include <platform/regulator/mtk_regulator.h>
+
+static struct mtk_regulator mtk_regulator_table[MTK_REGULATOR_MAX_NR];
+
+int mtk_regulator_get(const char *id, struct mtk_regulator *mreg)
+{
+ int i = 0;
+
+ for (i = 0; i < MTK_REGULATOR_MAX_NR; i++) {
+ if (mtk_regulator_table[i].name != 0) {
+ if (strcmp(mtk_regulator_table[i].name, id) == 0) {
+ memcpy(mreg, &mtk_regulator_table[i],
+ sizeof(struct mtk_regulator));
+ return 0;
+ }
+ }
+ }
+ dprintf(CRITICAL,"get %s fail\n", id);
+ return -1;
+}
+
+int mtk_simple_regulator_register(struct mtk_regulator *mreg)
+{
+ if (mreg == 0)
+ return -1;
+ memcpy(&mtk_regulator_table[mreg->id], mreg,
+ sizeof(struct mtk_regulator));
+ dprintf(CRITICAL,"register %s OK\n", mreg->name);
+ return 0;
+}
+
+int mtk_regulator_enable(struct mtk_regulator *mreg, unsigned char enable)
+{
+ int ret = 0;
+
+ ret = mreg->reg_ops->enable(mreg->id, enable);
+ return ret;
+}
+
+int mtk_regulator_is_enabled(struct mtk_regulator *mreg)
+{
+ int ret = 0;
+
+ ret = mreg->reg_ops->is_enabled(mreg->id);
+ return ret;
+}
+
+int mtk_regulator_set_voltage(struct mtk_regulator *mreg, int min_uv, int max_uv)
+{
+ int ret = 0;
+
+ ret = mreg->reg_ops->set_voltage(mreg->id, min_uv, max_uv);
+ return ret;
+}
+
+int mtk_regulator_get_voltage(struct mtk_regulator *mreg)
+{
+ int ret = 0;
+
+ ret = mreg->reg_ops->get_voltage(mreg->id);
+ return ret;
+}
+
+int mtk_regulator_set_mode(struct mtk_regulator *mreg, unsigned char mode)
+{
+ int ret = 0;
+ ret = mreg->reg_ops->set_mode(mreg->id, mode);
+ return ret;
+}
+
+int mtk_regulator_get_mode(struct mtk_regulator *mreg)
+{
+ int ret = 0;
+ ret = mreg->reg_ops->get_mode(mreg->id);
+ return ret;
+}
+
+#ifdef LDO_VOTRIM_SUPPORT
+int mtk_regulator_set_votrim(struct mtk_regulator *mreg, int trim_uv)
+{
+ int ret = 0;
+ ret = mreg->reg_ops->set_votrim(mreg->id, trim_uv);
+ return ret;
+}
+
+int mtk_regulator_get_votrim(struct mtk_regulator *mreg)
+{
+ int ret = 0;
+ ret = mreg->reg_ops->get_votrim(mreg->id);
+ return ret;
+}
+#endif /*--LDO_VOTRIM_SUPPORT--*/
diff --git a/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic.c b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic.c
new file mode 100644
index 0000000..3b1e011
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic.c
@@ -0,0 +1,671 @@
+#include <sys/types.h>
+#include <platform/pmic_wrap_init.h>
+#include <platform/MT6389/pmic.h>
+#include <platform/MT6389/mt6389.h>
+#include <platform/regulator/mtk_regulator.h>
+#include <assert.h>
+
+#define MT6389_CID_CODE 0x8900
+
+#if PMIC_REDUCE_CODE_SIZE
+/* Bianco only API which is used to check VCORE not lower 0.8V */
+void wk_vcore_check(void)
+{
+ struct mtk_regulator reg_vcore;
+ int ret = 0;
+
+ ret = mtk_regulator_get("vcore", ®_vcore);
+ if (ret)
+ dprintf(CRITICAL,"mtk_regulator_get reg_vcore failed\n");
+ dprintf(CRITICAL,"vcore = %d uV\n", mtk_regulator_get_voltage(®_vcore));
+}
+#endif
+
+/*===========================
+ PMIC access API
+===========================*/
+unsigned int pmic_read_interface (unsigned int RegNum, unsigned int *val, unsigned int MASK, unsigned int SHIFT)
+{
+ unsigned int return_value = 0;
+ unsigned int pmic_reg = 0;
+ unsigned int rdata;
+
+ return_value = pwrap_read(RegNum, &rdata);
+ pmic_reg = rdata;
+ if (return_value != 0) {
+ dprintf(CRITICAL,"[PMIC]Reg[0x%x] pmic_wrap read data fail\n", RegNum);
+ return return_value;
+ }
+
+ // dprintf(CRITICAL,"[pmic_config_interface] Reg[%x]=0x%x\n", RegNum, pmic_reg);
+ pmic_reg &= (MASK << SHIFT);
+ *val = (pmic_reg >> SHIFT);
+ // dprintf(CRITICAL,"[pmic_read_interface] val=0x%x\n", *val);
+
+ return return_value;
+}
+
+unsigned int pmic_config_interface (unsigned int RegNum, unsigned int val, unsigned int MASK, unsigned int SHIFT)
+{
+ unsigned int return_value = 0;
+ unsigned int pmic_reg = 0;
+ unsigned int rdata;
+
+ return_value = pwrap_read(RegNum, &rdata);
+ pmic_reg = rdata;
+ if (return_value != 0) {
+ dprintf(CRITICAL,"[PMIC]Reg[0x%x] pmic_wrap read data fail\n", RegNum);
+ return return_value;
+ }
+ // dprintf(CRITICAL,"[pmic_config_interface] Reg[%x]=0x%x\n", RegNum, pmic_reg);
+ pmic_reg &= ~(MASK << SHIFT);
+ pmic_reg |= (val << SHIFT);
+
+ /* 2. mt_write_byte(RegNum, pmic_reg); */
+ return_value = pwrap_write(RegNum, pmic_reg);
+ if (return_value != 0) {
+ dprintf(CRITICAL,"[PMIC]Reg[0x%x] pmic_wrap write 0x%x fail\n", RegNum, pmic_reg);
+ return return_value;
+ }
+ // dprintf(CRITICAL,"[pmic_config_interface] write Reg[%x]=0x%x\n", RegNum, pmic_reg);
+
+ return return_value;
+}
+
+unsigned int pmic_get_register_value(struct pmuflag_t pmureg)
+{
+ unsigned int val;
+ unsigned int ret;
+
+ ret = pmic_read_interface(pmureg.addr, &val, pmureg.mask, pmureg.shift);
+
+ return val;
+}
+
+unsigned int pmic_set_register_value(struct pmuflag_t pmureg, unsigned int val)
+{
+ unsigned int ret;
+
+ ret = pmic_config_interface(pmureg.addr, val, pmureg.mask, pmureg.shift);
+
+ return ret;
+}
+
+unsigned int upmu_get_reg_value(unsigned int reg)
+{
+ unsigned int ret = 0;
+ unsigned int reg_val = 0;
+
+ ret = pmic_read_interface(reg, ®_val, 0xFFFF, 0x0);
+
+ return reg_val;
+}
+
+unsigned int upmu_set_reg_value(unsigned int reg, unsigned int reg_val)
+{
+ unsigned int ret = 0;
+
+ ret = pmic_config_interface(reg, reg_val, 0xFFFF, 0x0);
+
+ return ret;
+}
+
+/*
+ * PMIC Usage APIs
+ */
+unsigned int get_dram_type(void)
+{
+ unsigned int val = 0;
+
+ pmic_read_interface(PMIC_VM_MODE_ADDR, &val,
+ PMIC_VM_MODE_MASK, PMIC_VM_MODE_SHIFT);
+
+ return val;
+}
+
+unsigned int get_PMIC_chip_version(void)
+{
+ unsigned int ret = 0;
+ unsigned int val = 0;
+
+ ret = pmic_read_interface((unsigned int)(PMIC_SWCID_ADDR), (&val),
+ (unsigned int)(PMIC_SWCID_MASK),
+ (unsigned int)(PMIC_SWCID_SHIFT));
+
+ return val;
+}
+
+int pmic_detect_powerkey(void)
+{
+ unsigned int ret = 0;
+ unsigned int val = 0;
+
+ ret = pmic_read_interface((unsigned int)(PMIC_PWRKEY_DEB_ADDR), (&val),
+ (unsigned int)(PMIC_PWRKEY_DEB_MASK),
+ (unsigned int)(PMIC_PWRKEY_DEB_SHIFT));
+ return (1 - val);
+}
+
+int pmic_detect_homekey(void)
+{
+ unsigned int ret = 0;
+ unsigned int val = 0;
+
+ ret = pmic_read_interface((unsigned int)(PMIC_HOMEKEY_DEB_ADDR), (&val),
+ (unsigned int)(PMIC_HOMEKEY_DEB_MASK),
+ (unsigned int)(PMIC_HOMEKEY_DEB_SHIFT));
+
+ return (1 - val);
+}
+
+unsigned int pmic_upmu_set_baton_tdet_en(unsigned int val)
+{
+ unsigned int ret = 0;
+
+ ret = pmic_config_interface((unsigned int)(PMIC_RG_BATON_TDET_EN_ADDR), (unsigned int)(val),
+ (unsigned int)(PMIC_RG_BATON_TDET_EN_MASK),
+ (unsigned int)(PMIC_RG_BATON_TDET_EN_SHIFT));
+
+ return ret;
+}
+
+unsigned int upmu_is_chr_det(void)
+{
+ unsigned int ret = 0;
+ unsigned int val = 0;
+
+ ret = pmic_read_interface((unsigned int)(PMIC_RGS_CHRDET_ADDR), (&val),
+ (unsigned int)(PMIC_RGS_CHRDET_MASK),
+ (unsigned int)(PMIC_RGS_CHRDET_SHIFT));
+ dprintf(CRITICAL,"[PMIC]IsUsbCableIn %d\n", val);
+ return val;
+}
+
+void PMIC_enable_long_press_reboot(void)
+{
+#if CFG_LPRST_SUPPORT
+ #if ONEKEY_REBOOT_NORMAL_MODE_PL
+ /* PWRKEY */
+ pmic_config_interface(PMIC_RG_PWRKEY_KEY_MODE_ADDR, 0x00,
+ PMIC_RG_PWRKEY_KEY_MODE_MASK,
+ PMIC_RG_PWRKEY_KEY_MODE_SHIFT);
+ #else
+ /* PWRKEY + HOMEKEY */
+ pmic_config_interface(PMIC_RG_PWRKEY_KEY_MODE_ADDR, 0x01,
+ PMIC_RG_PWRKEY_KEY_MODE_MASK,
+ PMIC_RG_PWRKEY_KEY_MODE_SHIFT);
+ #endif /* ONEKEY_REBOOT_NORMAL_MODE_PL */
+ pmic_config_interface(PMIC_RG_PWRKEY_RST_EN_ADDR, 0x01,
+ PMIC_RG_PWRKEY_RST_EN_MASK,
+ PMIC_RG_PWRKEY_RST_EN_SHIFT);
+ pmic_config_interface(PMIC_RG_PWRKEY_RST_TD_ADDR,
+ (unsigned int)KPD_PMIC_LPRST_TD,
+ PMIC_RG_PWRKEY_RST_TD_MASK,
+ PMIC_RG_PWRKEY_RST_TD_SHIFT);
+#else
+ pmic_config_interface(PMIC_RG_PWRKEY_RST_EN_ADDR, 0x00,
+ PMIC_RG_PWRKEY_RST_EN_MASK,
+ PMIC_RG_PWRKEY_RST_EN_SHIFT);
+#endif /* CFG_LPRST_SUPPORT */
+}
+
+unsigned int PMIC_VUSB_EN(void)
+{
+ int ret = 0;
+
+ ret = pmic_config_interface((unsigned int)(PMIC_RG_LDO_VUSB_EN_ADDR), 1,
+ (unsigned int)(PMIC_RG_LDO_VUSB_EN_MASK),
+ (unsigned int)(PMIC_RG_LDO_VUSB_EN_SHIFT));
+
+ return ret;
+}
+
+/*
+ * PMIC Export API
+ */
+static unsigned int g_sts_crst;
+static unsigned int g_just_rst;
+static unsigned int g_pwrkey_release;
+static unsigned int g_pmic_boot_status;
+
+void pmic_cold_reset(void)
+{
+ pmic_config_interface(PMIC_RG_CRST_ADDR, 1,
+ PMIC_RG_CRST_MASK, PMIC_RG_CRST_SHIFT);
+}
+
+/* check if PMIC cold reset at previous power off */
+unsigned int is_pmic_cold_reset(void)
+{
+ return g_sts_crst;
+}
+
+unsigned int is_pmic_long_press_reset(void)
+{
+ return g_just_rst;
+}
+
+unsigned int get_pmic_boot_status(void)
+{
+ return g_pmic_boot_status;
+}
+
+static void pmic_check_rst(unsigned int poff_sts)
+{
+ unsigned int val;
+
+ /*
+ * TOP_RST_STATUS is used to indicate which reset happened
+ * If a reset happened, the corresponding bit will be clear
+ */
+ val = upmu_get_reg_value(MT6389_TOP_RST_STATUS);
+ if (val != 0x7F) {
+ if (val == 0)
+ dprintf(CRITICAL,"[%s] PORSTB\n", __func__);
+ else if (((val >> 1) & 1) == 0 && (poff_sts >> 9) & 1)
+ dprintf(CRITICAL,"[%s] DDLO_RSTB\n", __func__);
+ else if (((val >> 2) & 1) == 0 && (poff_sts >> 0) & 1)
+ dprintf(CRITICAL,"[%s] UVLO_RSTB\n", __func__);
+ val = upmu_set_reg_value(MT6389_TOP_RST_STATUS_SET, 0x78 | val);
+ }
+ if ((poff_sts >> 8) & 1)
+ dprintf(CRITICAL,"[%s] BWDT\n", __func__);
+ if ((poff_sts >> 6) & 1)
+ dprintf(CRITICAL,"[%s] Long press shutdown\n", __func__);
+ if ((poff_sts >> 5) & 1)
+ dprintf(CRITICAL,"[%s] Cold Reset\n", __func__);
+ if ((poff_sts >> 13) & 1)
+ dprintf(CRITICAL,"[%s] PWRKEY short press\n", __func__);
+ if ((poff_sts >> 10) & 1)
+ dprintf(CRITICAL,"[%s] AP Watchdog\n", __func__);
+}
+
+static void record_pmic_boot_status(unsigned int pon_sts, unsigned int poff_sts)
+{
+ if (poff_sts & 0x6)
+ g_pmic_boot_status = 1; /* OC/PG */
+ else if (poff_sts & 0x40 || g_just_rst)
+ g_pmic_boot_status = 2; /* Long press */
+ else if (poff_sts & 0x1 || poff_sts & 0x200)
+ g_pmic_boot_status = 3; /* UVLO/DDLO */
+}
+
+void pmic_dbg_status(unsigned char option)
+{
+ /*--option = 1--*/
+ /* UVLO off */
+ /* power not good */
+ /* buck oc */
+ /* thermal shutdown 150 */
+ /* long press shutdown */
+ /* WDTRST */
+ /* CLK TRIM */
+ /* WDTDBG_VOSEL */
+ /*--option = 0--*/
+ /* Clear PONSTS, POFFSTS and other exception status */
+ int ret_val = 0;
+ unsigned int poff_sts = 0;
+
+ if (option) {
+ /*--UVLO off--*/
+ dprintf(CRITICAL,"[PMIC]TOP_RST_STATUS[0x%x]=0x%x\n",
+ MT6389_TOP_RST_STATUS, upmu_get_reg_value(MT6389_TOP_RST_STATUS));
+ /*special for cold rest*/
+ poff_sts = upmu_get_reg_value(MT6389_POFFSTS);
+ g_sts_crst = (poff_sts >> PMIC_STS_CRST_SHIFT) & PMIC_STS_CRST_MASK;
+ dprintf(CRITICAL,"[PMIC]POFFSTS[0x%x]=0x%x\n",
+ MT6389_POFFSTS, poff_sts);
+ /*--power not good--*/
+ dprintf(CRITICAL,"[PMIC]PG_SDN_STS0[0x%x]=0x%x\n",
+ MT6389_PG_SDN_STS0, upmu_get_reg_value(MT6389_PG_SDN_STS0));
+ dprintf(CRITICAL,"[PMIC]PG_SDN_STS1[0x%x]=0x%x\n",
+ MT6389_PG_SDN_STS1, upmu_get_reg_value(MT6389_PG_SDN_STS1));
+ /*--buck oc--*/
+ dprintf(CRITICAL,"[PMIC]OC_SDN_STS0[0x%x]=0x%x\n",
+ MT6389_OC_SDN_STS0, upmu_get_reg_value(MT6389_OC_SDN_STS0));
+ dprintf(CRITICAL,"[PMIC]OC_SDN_STS1[0x%x]=0x%x\n",
+ MT6389_OC_SDN_STS1, upmu_get_reg_value(MT6389_OC_SDN_STS1));
+ dprintf(CRITICAL,"[PMIC]BUCK_OC_SDN_STATUS[0x%x]=0x%x\n",
+ MT6389_BUCK_TOP_OC_CON0, upmu_get_reg_value(MT6389_BUCK_TOP_OC_CON0));
+ dprintf(CRITICAL,"[PMIC]BUCK_OC_SDN_EN[0x%x]=0x%x\n",
+ MT6389_BUCK_TOP_ELR0, upmu_get_reg_value(MT6389_BUCK_TOP_ELR0));
+ /*--thermal shutdown 150--*/
+ dprintf(CRITICAL,"[PMIC]THERMALSTATUS[0x%x]=0x%x\n",
+ MT6389_THERMALSTATUS, upmu_get_reg_value(MT6389_THERMALSTATUS));
+ /*--long press shutdown--*/
+ dprintf(CRITICAL,"[PMIC]STRUP_CON4[0x%x]=0x%x\n",
+ MT6389_STRUP_CON4, upmu_get_reg_value(MT6389_STRUP_CON4));
+ /*--WDTRST--*/
+ dprintf(CRITICAL,"[PMIC]TOP_RST_MISC[0x%x]=0x%x\n",
+ MT6389_TOP_RST_MISC, upmu_get_reg_value(MT6389_TOP_RST_MISC));
+ /*--CLK TRIM--*/
+ dprintf(CRITICAL,"[PMIC]TOP_CLK_TRIM[0x%x]=0x%x\n",
+ MT6389_TOP_CLK_TRIM, upmu_get_reg_value(MT6389_TOP_CLK_TRIM));
+ /*--WDTRSTB_STATUS will be clear in kernel--*/
+
+ /*--Check PMIC reset reason--*/
+ pmic_check_rst(poff_sts);
+
+ //record_pmic_boot_status(pon_sts, poff_sts);
+ } else {
+ /*--Clear PONSTS and POFFSTS(include PG status and BUCK OC status)--*/
+ ret_val = pmic_config_interface(PMIC_RG_POFFSTS_CLR_ADDR, 0x1,
+ PMIC_RG_POFFSTS_CLR_MASK, PMIC_RG_POFFSTS_CLR_SHIFT);
+ ret_val = pmic_config_interface(PMIC_RG_PONSTS_CLR_ADDR, 0x1,
+ PMIC_RG_PONSTS_CLR_MASK, PMIC_RG_PONSTS_CLR_SHIFT);
+ ret_val = pmic_config_interface(PMIC_RG_POFFSTS_CLR_ADDR, 0x0,
+ PMIC_RG_POFFSTS_CLR_MASK, PMIC_RG_POFFSTS_CLR_SHIFT);
+ ret_val = pmic_config_interface(PMIC_RG_PONSTS_CLR_ADDR, 0x0,
+ PMIC_RG_PONSTS_CLR_MASK, PMIC_RG_PONSTS_CLR_SHIFT);
+ /*--clear OC_SDN_STATUS--*/
+ ret_val = pmic_config_interface(MT6389_BUCK_TOP_OC_CON0, 0xFF, 0xFF, 0);
+ /*--Clear thermal shutdown--*/
+ ret_val = pmic_config_interface(PMIC_RG_STRUP_THR_CLR_ADDR, 0x1,
+ PMIC_RG_STRUP_THR_CLR_MASK, PMIC_RG_STRUP_THR_CLR_SHIFT);
+ ret_val = pmic_config_interface(PMIC_RG_STRUP_THR_CLR_ADDR, 0x0,
+ PMIC_RG_STRUP_THR_CLR_MASK, PMIC_RG_STRUP_THR_CLR_SHIFT);
+ /*--Long press shutdown will be clear by pmic_check_rst()--*/
+ }
+}
+
+void pmic_wdt_set(void)
+{
+ unsigned int ret_val = 0;
+ /*--Reset digital only--*/
+ /*--Enable WDT--*/
+ ret_val |= pmic_config_interface(PMIC_TOP_RST_MISC_SET_ADDR, 0x0020, 0xFFFF, 0); /*--[5]=1, RG_WDTRSTB_DEB--*/
+ ret_val |= pmic_config_interface(PMIC_TOP_RST_MISC_CLR_ADDR, 0x0002, 0xFFFF, 0); /*--[1]=0, RG_WDTRSTB_MODE--*/
+ ret_val |= pmic_config_interface(PMIC_TOP_RST_MISC_SET_ADDR, 0x0001, 0xFFFF, 0); /*--[0]=1, RG_WDTRSTB_EN--*/
+
+ if (ret_val != 0)
+ dprintf(CRITICAL,"[%s] TOP_RST_MISC=0x%x\n", __func__,
+ upmu_get_reg_value(MT6389_TOP_RST_MISC));
+}
+
+static void pmic_default_voltage(void)
+{
+ int ret = 0;
+ struct mtk_regulator reg_vsram_proc;
+ struct mtk_regulator reg_vsram_others;
+ struct mtk_regulator reg_vproc;
+ struct mtk_regulator reg_vcore;
+ struct mtk_regulator reg_vmodem;
+ struct mtk_regulator reg_vgp3;
+ int vcore_vol = 0;
+ int vmodem_vol = 0;
+ int vgp3_vol = 0;
+
+ /* change vmodem & vcore to 0.8V, by MD DVFS */
+ vcore_vol = 800000;
+ vmodem_vol = 800000;
+
+ /* Set vgp3 to 1.8V for RF IO */
+ vgp3_vol = 1800000;
+
+ /*--Get regulator handle--*/
+ if (mtk_regulator_get("vsram_proc", ®_vsram_proc))
+ ret |= (1 << MTK_REGULATOR_VSRAM_PROC);
+
+ if (mtk_regulator_get("vsram_others", ®_vsram_others))
+ ret |= (1 << MTK_REGULATOR_VSRAM_OTHERS);
+
+ if (mtk_regulator_get("vproc", ®_vproc))
+ ret |= (1 << MTK_REGULATOR_VSRAM_PROC);
+
+ if (mtk_regulator_get("vcore", ®_vcore))
+ ret |= (1 << MTK_REGULATOR_VCORE);
+
+ if (mtk_regulator_get("vmodem", ®_vmodem))
+ ret |= (1 << MTK_REGULATOR_VMODEM);
+
+ if (mtk_regulator_get("vgp3", ®_vgp3))
+ ret |= (1 << MTK_REGULATOR_VGP3);
+
+ if (ret) {
+ dprintf(CRITICAL,"mtk_regulator_get (%d)\n", ret);
+ return;
+ }
+ /*--Set voltage--*/
+ if (mtk_regulator_set_voltage(®_vcore, vcore_vol, vcore_max_uV))
+ ret |= (1 << MTK_REGULATOR_VCORE);
+
+ if (mtk_regulator_set_voltage(®_vmodem, vmodem_vol, vmodem_max_uV))
+ ret |= (1 << MTK_REGULATOR_VMODEM);
+
+ if (mtk_regulator_set_voltage(®_vgp3, vgp3_vol, vgp3_max_uV))
+ ret |= (1 << MTK_REGULATOR_VGP3);
+
+ if (ret) {
+ dprintf(CRITICAL,"mtk_regulator_set_voltage(%d)\n", ret);
+ return;
+ }
+
+ /*--Get voltage--*/
+ dprintf(CRITICAL,"vsram_proc = %d uV\n", mtk_regulator_get_voltage(®_vsram_proc));
+ dprintf(CRITICAL,"vproc = %d uV\n", mtk_regulator_get_voltage(®_vproc));
+ dprintf(CRITICAL,"vsram_others = %d uV\n", mtk_regulator_get_voltage(®_vsram_others));
+ dprintf(CRITICAL,"vcore = %d uV\n", mtk_regulator_get_voltage(®_vcore));
+ dprintf(CRITICAL,"vmodem = %d uV\n", mtk_regulator_get_voltage(®_vmodem));
+ dprintf(CRITICAL,"vgp3 = %d uV\n", mtk_regulator_get_voltage(®_vgp3));
+
+ /*--Enable regulator--*/
+ if (mtk_regulator_enable(®_vgp3, 1))
+ ret |= (1 << MTK_REGULATOR_VGP3);
+ if (ret) {
+ dprintf(CRITICAL,"mtk_regulator_enable(%d)\n", ret);
+ return;
+ }
+}
+
+/******************************************************************************************************
+* AUXADC
+******************************************************************************************************/
+/* extend r_val to 10 times from PMIC MT6389 */
+struct pmic_auxadc_channel_new pmic_auxadc_channel[] = {
+ /* BATADC */
+ PMIC_AUXADC_GEN(15, 3, 0, PMIC_AUXADC_RQST_CH0,
+ PMIC_AUXADC_ADC_RDY_CH0_BY_AP, PMIC_AUXADC_ADC_OUT_CH0_BY_AP),
+ /* VCDT */
+ PMIC_AUXADC_GEN(12, 1, 2, PMIC_AUXADC_RQST_CH2,
+ PMIC_AUXADC_ADC_RDY_CH2, PMIC_AUXADC_ADC_OUT_CH2),
+ /* channel 4 */
+ /* CHIP TEMP */
+ PMIC_AUXADC_GEN(12, 1, 4, PMIC_AUXADC_RQST_CH4,
+ PMIC_AUXADC_ADC_RDY_CH4, PMIC_AUXADC_ADC_OUT_CH4),
+ /* VCORE_TEMP */
+ PMIC_AUXADC_GEN(12, 1, 4, PMIC_AUXADC_RQST_CH4_BY_THR1,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR1, PMIC_AUXADC_ADC_OUT_CH4_BY_THR1),
+ /* VPROC_TEMP */
+ PMIC_AUXADC_GEN(12, 1, 4, PMIC_AUXADC_RQST_CH4_BY_THR2,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR2, PMIC_AUXADC_ADC_OUT_CH4_BY_THR2),
+ /* VGPU_TEMP */
+ PMIC_AUXADC_GEN(12, 1, 4, PMIC_AUXADC_RQST_CH4_BY_THR3,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR3, PMIC_AUXADC_ADC_OUT_CH4_BY_THR3),
+ /* channel 6 */
+ /* VS2_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER1_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER1_DIV, PMIC_AUXADC_ADC_OUT_INTER1_DIV),
+ /* DCXO_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER2_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER2_DIV, PMIC_AUXADC_ADC_OUT_INTER2_DIV),
+ /* VRFCK_1_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER3_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER3_DIV, PMIC_AUXADC_ADC_OUT_INTER3_DIV),
+ /* VRFCK_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER4_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER4_DIV, PMIC_AUXADC_ADC_OUT_INTER4_DIV),
+ /* VAUD28_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER5_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER5_DIV, PMIC_AUXADC_ADC_OUT_INTER5_DIV),
+ /* VIO18_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER6_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER6_DIV, PMIC_AUXADC_ADC_OUT_INTER6_DIV),
+ /* VIO33_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER7_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER6_DIV, PMIC_AUXADC_ADC_OUT_INTER7_DIV),
+ /* VEMC_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER8_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER8_DIV, PMIC_AUXADC_ADC_OUT_INTER8_DIV),
+ /* VUSB_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER9_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER9_DIV, PMIC_AUXADC_ADC_OUT_INTER9_DIV),
+ /* VRTC28_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER10_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER10_DIV, PMIC_AUXADC_ADC_OUT_INTER10_DIV),
+ /* VDIG18_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER11_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER11_DIV, PMIC_AUXADC_ADC_OUT_INTER11_DIV),
+ /* VDIG18_AO_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER12_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER12_DIV, PMIC_AUXADC_ADC_OUT_INTER12_DIV),
+ /* VS1_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER13_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER13_DIV, PMIC_AUXADC_ADC_OUT_INTER13_DIV),
+ /* VDRAM2_VOLT */
+ PMIC_AUXADC_GEN(12, 2.5, 6, PMIC_AUXADC_RQST_INTER14_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER14_DIV, PMIC_AUXADC_ADC_OUT_INTER14_DIV),
+ /* TSX_TEMP(GPS) */
+ PMIC_AUXADC_GEN(15, 1, 7, PMIC_AUXADC_RQST_CH7_BY_GPS,
+ PMIC_AUXADC_ADC_RDY_CH7_BY_GPS, PMIC_AUXADC_ADC_OUT_CH7_BY_GPS),
+ /* channel 8 */
+ /* VPROC_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER1,
+ PMIC_AUXADC_ADC_RDY_INTER1, PMIC_AUXADC_ADC_OUT_INTER1),
+ /* VCORE_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER2,
+ PMIC_AUXADC_ADC_RDY_INTER2, PMIC_AUXADC_ADC_OUT_INTER2),
+ /* VMODEM_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER3,
+ PMIC_AUXADC_ADC_RDY_INTER3, PMIC_AUXADC_ADC_OUT_INTER3),
+ /* VSRAM_OTHERS_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER4,
+ PMIC_AUXADC_ADC_RDY_INTER4, PMIC_AUXADC_ADC_OUT_INTER4),
+ /* VDRAM1_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER5,
+ PMIC_AUXADC_ADC_RDY_INTER5, PMIC_AUXADC_ADC_OUT_INTER5),
+ /* VBBCK_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER6,
+ PMIC_AUXADC_ADC_RDY_INTER6, PMIC_AUXADC_ADC_OUT_INTER6),
+ /* VA12_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER7,
+ PMIC_AUXADC_ADC_RDY_INTER7, PMIC_AUXADC_ADC_OUT_INTER7),
+ /* VA09_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER8,
+ PMIC_AUXADC_ADC_RDY_INTER8, PMIC_AUXADC_ADC_OUT_INTER8),
+ /* VSRAM_PROC_VOLT */
+ PMIC_AUXADC_GEN(12, 1, 8, PMIC_AUXADC_RQST_INTER9,
+ PMIC_AUXADC_ADC_RDY_INTER9, PMIC_AUXADC_ADC_OUT_INTER9),
+ /* HPOFS_CAL */
+ PMIC_AUXADC_GEN(15, 1, 9, PMIC_AUXADC_RQST_CH9,
+ PMIC_AUXADC_ADC_RDY_CH9, PMIC_AUXADC_ADC_OUT_CH9),
+ /* DCXO_TEMP */
+ PMIC_AUXADC_GEN(15, 1, 10, PMIC_AUXADC_RQST_DCXO_BY_GPS,
+ PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS, PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS),
+ /* channel 12 */
+ /* Tref _VOLT */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_TREF,
+ PMIC_AUXADC_ADC_RDY_TREF, PMIC_AUXADC_ADC_OUT_TREF),
+ /* AP_HT_Thermal */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_EXT1,
+ PMIC_AUXADC_ADC_RDY_EXT1, PMIC_AUXADC_ADC_OUT_EXT1),
+ /* RF_PA_Thermal */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_EXT2,
+ PMIC_AUXADC_ADC_RDY_EXT2, PMIC_AUXADC_ADC_OUT_EXT2),
+ /* AP_LT_Thermal */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_EXT3,
+ PMIC_AUXADC_ADC_RDY_EXT3, PMIC_AUXADC_ADC_OUT_EXT3),
+ /* DRAM_HT_Thermal */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_EXT4,
+ PMIC_AUXADC_ADC_RDY_EXT4, PMIC_AUXADC_ADC_OUT_EXT4),
+ /* AUXIN9_DRDI */
+ PMIC_AUXADC_GEN(12, 1, 12, PMIC_AUXADC_RQST_EXT8,
+ PMIC_AUXADC_ADC_RDY_EXT8, PMIC_AUXADC_ADC_OUT_EXT8),
+ /* channel 13 */
+ /* GPS _ANT */
+ PMIC_AUXADC_GEN(12, 1, 13, PMIC_AUXADC_RQST_EXT5,
+ PMIC_AUXADC_ADC_RDY_EXT5, PMIC_AUXADC_ADC_OUT_EXT5),
+ /* MAIN_ANT */
+ PMIC_AUXADC_GEN(12, 1, 13, PMIC_AUXADC_RQST_EXT6,
+ PMIC_AUXADC_ADC_RDY_EXT6, PMIC_AUXADC_ADC_OUT_EXT6),
+ /* DRX_ANT */
+ PMIC_AUXADC_GEN(12, 1, 13, PMIC_AUXADC_RQST_EXT7,
+ PMIC_AUXADC_ADC_RDY_EXT7, PMIC_AUXADC_ADC_OUT_EXT7),
+};
+
+static int count_time_out = 15;
+#define VOLT_FULL 1800
+
+int pmic_get_auxadc_value(unsigned short channel)
+{
+ int count = 0;
+ signed int adc_result = 0, reg_val = 0;
+ struct pmic_auxadc_channel_new *auxadc_channel;
+
+ if (channel < AUXADC_LIST_BATADC || channel >= AUXADC_LIST_MAX) {
+ dprintf(CRITICAL,"[%s] Invalid channel(%d)\n", __func__, channel);
+ return -1;
+ }
+ auxadc_channel = &pmic_auxadc_channel[channel];
+
+ pmic_set_register_value(auxadc_channel->channel_rqst, 1);
+ udelay(10);
+
+ while (pmic_get_register_value(auxadc_channel->channel_rdy) != 1) {
+ udelay(1300);
+ count++;
+ if (count > count_time_out) {
+ dprintf(CRITICAL,"[%s] (%d) Time out!\n",
+ __func__, auxadc_channel->ch_num);
+ break;
+ }
+ }
+ reg_val = pmic_get_register_value(auxadc_channel->channel_out);
+
+ /* Audio request HPOFS to return raw data */
+ /* V = (reg_val * r_val * 1800 / 10) >> (resolution bits) */
+ if (channel == AUXADC_LIST_HPOFS_CAL)
+ adc_result = reg_val;
+ else
+ adc_result = ((reg_val * auxadc_channel->r_val * VOLT_FULL) / 10)
+ >> auxadc_channel->resolution;
+
+ dprintf(CRITICAL,"[%s] channel = %d, reg_val = 0x%x, adc_result = %d\n",
+ __func__, auxadc_channel->ch_num, reg_val, adc_result);
+ return adc_result;
+}
+
+/*
+ * PMIC Init Code
+ */
+unsigned int pmic_init (void)
+{
+ unsigned int ret_code = PMIC_TEST_PASS;
+ int ret_val = 0, val;
+ unsigned int id = 0;
+
+ id = get_PMIC_chip_version();
+ dprintf(CRITICAL,"[PMIC]CHIP Code:0x%x\n", id);
+ id &= 0xFF00;
+ if (id != MT6389_CID_CODE) {
+ dprintf(CRITICAL,"[PMIC] CHIP ID mismach! Please select a valid load or ask for help\n");
+ ASSERT(0);
+ }
+
+ /* Boot debug status */
+ pmic_dbg_status(1);
+
+ /* Enable PMIC WDTRST function (depends on main chip RST function)*/
+ pmic_wdt_set();
+
+ pmic_dbg_status(0);
+
+ /* Regulator init */
+ mt6389_probe();
+
+ pmic_default_voltage();
+
+ dprintf(CRITICAL,"[PMIC]Init done\n");
+
+ return ret_code;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_efuse.c b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_efuse.c
new file mode 100644
index 0000000..0638903
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_efuse.c
@@ -0,0 +1,45 @@
+#include <sys/types.h>
+#include <platform.h>
+#include <platform/pmic.h>
+
+#define pmic_set_register_value(flagname, val) \
+ pmic_config_interface(flagname##_ADDR, (val), flagname##_MASK, flagname##_SHIFT)
+
+#define pmic_get_register_value(flagname) \
+({ \
+ unsigned int val; \
+ pmic_read_interface(flagname##_ADDR, &val, flagname##_MASK, flagname##_SHIFT); \
+ val; \
+})
+
+unsigned int pmic_read_efuse_nolock(int i)
+{
+ unsigned int efuse_data = 0;
+
+ /* start from i == 104 */
+ i += 104;
+ /* 1. enable efuse ctrl engine clock */
+ pmic_set_register_value(PMIC_TOP_CKHWEN_CON0_CLR, 1 << PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT);
+ pmic_set_register_value(PMIC_TOP_CKPDN_CON0_CLR, 1 << PMIC_RG_EFUSE_CK_PDN_SHIFT);
+ /* 2. */
+ pmic_set_register_value(PMIC_RG_OTP_RD_SW, 1);
+ /* 3. Set row to read */
+ pmic_set_register_value(PMIC_RG_OTP_PA, i * 2);
+ /* 4. Toggle RG_OTP_RD_TRIG */
+ if (pmic_get_register_value(PMIC_RG_OTP_RD_TRIG) == 0)
+ pmic_set_register_value(PMIC_RG_OTP_RD_TRIG, 1);
+ else
+ pmic_set_register_value(PMIC_RG_OTP_RD_TRIG, 0);
+ /* 5. Polling RG_OTP_RD_BUSY = 0 */
+ udelay(300);
+ while (pmic_get_register_value(PMIC_RG_OTP_RD_BUSY) == 1)
+ ;
+ /* 6. Read RG_OTP_DOUT_SW */
+ udelay(100);
+ efuse_data = pmic_get_register_value(PMIC_RG_OTP_DOUT_SW);
+ /* 7. disable efuse ctrl engine clock */
+ pmic_set_register_value(PMIC_TOP_CKHWEN_CON0_SET, 1 << PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT);
+ pmic_set_register_value(PMIC_TOP_CKPDN_CON0_SET, 1 << PMIC_RG_EFUSE_CK_PDN_SHIFT);
+
+ return efuse_data;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_initial_setting.c b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_initial_setting.c
new file mode 100644
index 0000000..858ac25
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pmic/MT6389/pmic_initial_setting.c
@@ -0,0 +1,266 @@
+#include <sys/types.h>
+#include <debug.h>
+#include <platform.h>
+#include <platform/MT6389/pmic.h>
+
+/* Enable this option when pmic initial setting is verified */
+#define INIT_SETTING_VERIFIED 1
+#define HW_TRACKING 0
+
+/* Enable this option when pmic need efuse sw load */
+/* if enable, please also check pmic_efuse.c or pmic_efuse_xxxx.c */
+#define EFUSE_SW_LOAD 0
+
+#define PMICE1ID 0x8910
+
+static void wk_disable_VPA_OC_shutdown() {
+ // w.k. disable LDO OC shutdown mechanisim for VPA 1.2V issue
+ pmic_config_interface(0x15C6, 0, 0x80, 0);
+}
+static void wk_dvs_timing_down() {
+ pmic_config_interface(PMIC_RG_VPROC_RSV2_ADDR, 0x3010, 0xFFFF, 0);
+ pmic_config_interface(PMIC_RG_VCORE_RSV2_ADDR, 0x3010, 0xFFFF, 0);
+ pmic_config_interface(PMIC_RG_VMODEM_RSV2_ADDR, 0x3010, 0xFFFF, 0);
+ pmic_config_interface(PMIC_RG_VSRAM_OTHERS_RSV2_ADDR, 0x3010, 0xFFFF, 0);
+}
+
+#ifdef INIT_SETTING_VERIFIED
+static struct pmic_setting init_setting[] = {
+ {0x20, 0xA, 0xA, 0},
+ {0x24, 0x1F00, 0x1F00, 0},
+ {0x30, 0x1, 0x1, 0},
+ {0x32, 0x1, 0x1, 0},
+ {0x94, 0x0, 0xFFFF, 0},
+ {0x10C, 0x10, 0x10, 0},
+ {0x112, 0x4, 0x4, 0},
+ {0x118, 0x8, 0x8, 0},
+ {0x14A, 0x21, 0x21, 0},
+ {0x198, 0x0, 0x1FF, 0},
+ {0x1B2, 0x3, 0x3, 0},
+ {0x3C0, 0x0, 0x300, 0},
+ {0x50C, 0x1, 0x1, 0},
+ {0x7A6, 0xE000, 0xE000, 0},
+ {0x7A8, 0x0, 0x200, 0},
+ {0x7AE, 0x0, 0xFF00, 0},
+ {0x98A, 0x40, 0x40, 0},
+ {0xA12, 0x0, 0x4000, 0},
+ {0xA20, 0xFFFF, 0xFFFF, 0},
+ {0xA22, 0xF000, 0xF000, 0},
+ {0xA94, 0x1, 0x1, 0},
+ {0xF8C, 0x115, 0x115, 0},
+ {0x1188, 0x0, 0x8000, 0},
+ {0x125C, 0x0, 0x2, 0},
+ {0x125E, 0x8000, 0x8000, 0},
+ {0x1262, 0x4, 0x4, 0},
+ {0x1268, 0x0, 0x2, 0},
+ {0x1274, 0x0, 0x2, 0},
+ {0x1330, 0x0, 0x2, 0},
+ {0x1342, 0x0, 0x2, 0},
+ {0x1354, 0x0, 0x2, 0},
+ {0x1366, 0x0, 0x2, 0},
+ {0x1378, 0x0, 0x2, 0},
+ {0x1398, 0x0, 0x2, 0},
+ {0x13AA, 0x0, 0x2, 0},
+ {0x13BC, 0x0, 0x2, 0},
+ {0x13CE, 0x0, 0x2, 0},
+ {0x13E0, 0x0, 0x2, 0},
+ {0x13F2, 0x0, 0x2, 0},
+ {0x1418, 0x0, 0x2, 0},
+ {0x142A, 0x0, 0x2, 0},
+ {0x143C, 0x0, 0x2, 0},
+ {0x144E, 0x0, 0x2, 0},
+ {0x1460, 0x0, 0x2, 0},
+ {0x1472, 0x0, 0x2, 0},
+ {0x1498, 0x0, 0x2, 0},
+ {0x14AA, 0x0, 0x2, 0},
+ {0x14BC, 0x0, 0x2, 0},
+ {0x14CE, 0x0, 0x2, 0},
+ {0x14E0, 0x0, 0x2, 0},
+ {0x14F2, 0x0, 0x2, 0},
+ {0x1592, 0x8, 0x8, 0},
+ {0x160E, 0x8, 0x7F, 0},
+ {0x1612, 0xF0F, 0x7F7F, 0},
+ {0x168E, 0x8, 0x7F, 0},
+ {0x1692, 0x1616, 0x7F7F, 0},
+ {0x170E, 0x10, 0x7F, 0},
+ {0x1712, 0x720, 0x7F7F, 0},
+ {0x178E, 0x8, 0x7F, 0},
+ {0x1792, 0x70D, 0x7F7F, 0},
+ {0x1892, 0x1968, 0x7F7F, 0},
+ {0x1996, 0x2810, 0x7F7F, 0},
+ {0x1998, 0x800, 0x7F00, 0},
+ {0x199A, 0x700, 0x701, 0},
+ {0x1A0C, 0x3C00, 0x3C00, 0},
+ {0x1A0E, 0x700, 0x700, 0},
+ {0x1A10, 0x2010, 0xFFFF, 0},
+ {0x1A14, 0x1700, 0x1FE0, 0},
+ {0x1A18, 0x3C00, 0x3C00, 0},
+ {0x1A1A, 0x700, 0x700, 0},
+ {0x1A1C, 0x2010, 0xFFFF, 0},
+ {0x1A20, 0x1100, 0x1FE0, 0},
+ {0x1A8A, 0x3C00, 0x3C00, 0},
+ {0x1A8C, 0x1E00, 0x3F00, 0},
+ {0x1A8E, 0x2010, 0xFFFF, 0},
+ {0x1A92, 0x1700, 0x1FE0, 0},
+ {0x1A94, 0x3C, 0x3D, 0},
+ {0x1A96, 0xAC40, 0xFFFF, 0},
+ {0x1A9A, 0x810, 0x838, 0},
+ {0x1A9E, 0x3C, 0x3D, 0},
+ {0x1AA0, 0x2C40, 0xFFFF, 0},
+ {0x1AA4, 0x10, 0x38, 0},
+ {0x1AA8, 0x540, 0xFC0, 0},
+ {0x1AAA, 0x3C, 0x3C, 0},
+ {0x1AAC, 0x1C00, 0xFF00, 0},
+ {0x1AAE, 0x88, 0xFF, 0},
+ {0x1AB0, 0x6020, 0xFF20, 0},
+ {0x1AB2, 0x2900, 0xF900, 0},
+ {0x1AB4, 0xD00, 0xF00, 0},
+ {0x1AB6, 0x3C, 0x3D, 0},
+ {0x1AB8, 0xAC40, 0xFFFF, 0},
+ {0x1ABC, 0xC10, 0xC38, 0},
+ {0x1AC2, 0x3C00, 0x3C00, 0},
+ {0x1AC4, 0x600, 0x700, 0},
+ {0x1AC6, 0x2010, 0xFFFF, 0},
+ {0x1ACA, 0x1700, 0x1FE0, 0},
+ {0x1C8E, 0xE, 0xE, 0},
+ {0x1C90, 0x1, 0x1, 0},
+ {0x1C92, 0xFFFF, 0xFFFF, 0},
+ {0x1CA2, 0xFF, 0xFF, 0},
+ {0x1CA8, 0x0, 0xFF, 0},
+ {0x1D0A, 0x30, 0x8030, 0},
+ {0x1D1C, 0x30, 0x8030, 0},
+ {0x1D2E, 0x30, 0x8030, 0},
+ {0x1D40, 0x30, 0x8030, 0},
+ {0x1D52, 0x30, 0x8030, 0},
+ {0x1D66, 0x30, 0x8030, 0},
+ {0x1D8A, 0x10, 0x8030, 0},
+ {0x1D9C, 0x10, 0x8030, 0},
+ {0x1DAE, 0x10, 0x8030, 0},
+ {0x1DB2, 0x8, 0x8, 0},
+ {0x1DC0, 0x10, 0x8030, 0},
+ {0x1DD2, 0x10, 0x8030, 0},
+ {0x1DE4, 0x10, 0x8030, 0},
+ {0x1E0A, 0x30, 0x8030, 0},
+ {0x1E1C, 0x30, 0x8030, 0},
+ {0x1E2E, 0x10, 0x8030, 0},
+ {0x1E40, 0x30, 0x8030, 0},
+ {0x1E54, 0x10, 0x8030, 0},
+ {0x1E66, 0x30, 0x8030, 0},
+ {0x1E8A, 0x30, 0x8030, 0},
+ {0x1E9E, 0x10, 0x8030, 0},
+ {0x1EB0, 0x0, 0x8000, 0},
+ {0x1EC0, 0x0, 0x1, 0},
+ {0x1EC2, 0x0, 0x8000, 0},
+ {0x1EC6, 0x8, 0x8008, 0},
+ {0x1ED2, 0x0, 0x1, 0},
+ {0x1ED4, 0x0, 0x8000, 0},
+ {0x1ED8, 0x8, 0x8008, 0},
+ {0x1F0A, 0x10, 0x8030, 0},
+ {0x1F12, 0xF0F, 0x7F7F, 0},
+ {0x1F9A, 0x2, 0x2, 0},
+ {0x201C, 0x80, 0xC0, 0},
+};
+#endif
+
+void pmic_init_setting(void)
+{
+ unsigned int ret = 0, i = 0, val = 0;
+
+
+ dprintf(CRITICAL,"[PMIC_INIT_SETTING] start\n");
+
+#if INIT_SETTING_VERIFIED
+ /* Unlock protect key for init. setting*/
+
+ /* for D type efuse */
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9C76,
+ PMIC_TMA_KEY_MASK,
+ PMIC_TMA_KEY_SHIFT);
+ /* for Buck */
+ pmic_config_interface(PMIC_BUCK_TOP_WRITE_KEY_ADDR, 0x5543,
+ PMIC_BUCK_TOP_WRITE_KEY_MASK,
+ PMIC_BUCK_TOP_WRITE_KEY_SHIFT);
+ /* for AuxADC */
+ pmic_config_interface(PMIC_HK_AUXADC_KEY_ADDR, 0x6389,
+ PMIC_HK_AUXADC_KEY_MASK,
+ PMIC_HK_AUXADC_KEY_SHIFT);
+ /* for LDO key */
+ pmic_config_interface(PMIC_LDO_WRITE_KEY_ADDR, 0x931C,
+ PMIC_LDO_WRITE_KEY_MASK,
+ PMIC_LDO_WRITE_KEY_SHIFT);
+ /* for PSC */
+ pmic_config_interface(PMIC_RG_MBS_PSC_KEY_ADDR, 0x6389,
+ PMIC_RG_MBS_PSC_KEY_MASK,
+ PMIC_RG_MBS_PSC_KEY_SHIFT);
+#if 0 // PT has not request unlock these protect RG in the init. setting
+ /* for Power off sequence */
+ pmic_config_interface(PMIC_RG_CPS_W_KEY_ADDR, 0x4729,
+ PMIC_RG_CPS_W_KEY_MASK,
+ PMIC_RG_CPS_W_KEY_SHIFT);
+ /* for SPISLV(wrapper init.)*/
+ pmic_config_interface(PMIC_SPISLV_KEY_ADDR, 0xBADE,
+ PMIC_SPISLV_KEY_MASK,
+ PMIC_SPISLV_KEY_SHIFT);
+#endif
+ for (i = 0; i < ARRAY_SIZE(init_setting); i++)
+ pmic_config_interface(
+ init_setting[i].addr, init_setting[i].val,
+ init_setting[i].mask, init_setting[i].shift);
+
+#if EFUSE_SW_LOAD
+ /* PMIC SW load EFUSE to target register */
+ pmic_efuse_sw_load();
+#else
+ dprintf(CRITICAL,"No EFUSE SW Load\n");
+#endif
+
+ if (get_PMIC_chip_version() == PMICE1ID) {
+ wk_dvs_timing_down();
+ wk_disable_VPA_OC_shutdown();
+ }
+
+ /* Adjust vgp3 soft start time for suspend power optimization*/
+ pmic_config_interface(PMIC_RG_LDO_VGP3_STBTD_ADDR, 0,
+ PMIC_RG_LDO_VGP3_STBTD_MASK,
+ PMIC_RG_LDO_VGP3_STBTD_SHIFT);
+
+ /* Lock protect key for init. setting*/
+ /* for D type efuse */
+ pmic_config_interface(PMIC_TMA_KEY_ADDR, 0,
+ PMIC_TMA_KEY_MASK,
+ PMIC_TMA_KEY_SHIFT);
+ /* for Buck */
+ pmic_config_interface(PMIC_BUCK_TOP_WRITE_KEY_ADDR, 0,
+ PMIC_BUCK_TOP_WRITE_KEY_MASK,
+ PMIC_BUCK_TOP_WRITE_KEY_SHIFT);
+ /* for AuxADC */
+ pmic_config_interface(PMIC_HK_AUXADC_KEY_ADDR, 0,
+ PMIC_HK_AUXADC_KEY_MASK,
+ PMIC_HK_AUXADC_KEY_SHIFT);
+ /* for LDO key */
+ pmic_config_interface(PMIC_LDO_WRITE_KEY_ADDR, 0,
+ PMIC_LDO_WRITE_KEY_MASK,
+ PMIC_LDO_WRITE_KEY_SHIFT);
+ /* for PSC */
+ pmic_config_interface(PMIC_RG_MBS_PSC_KEY_ADDR, 0,
+ PMIC_RG_MBS_PSC_KEY_MASK,
+ PMIC_RG_MBS_PSC_KEY_SHIFT);
+#if 0 // PT has not request unlock these protect RG in the init. setting
+ /* for Power off sequence */
+ pmic_config_interface(PMIC_RG_CPS_W_KEY_ADDR, 0,
+ PMIC_RG_CPS_W_KEY_MASK,
+ PMIC_RG_CPS_W_KEY_SHIFT);
+ /* for SPISLV(wrapper init.)*/
+ pmic_config_interface(PMIC_SPISLV_KEY_ADDR, 0,
+ PMIC_SPISLV_KEY_MASK,
+ PMIC_SPISLV_KEY_SHIFT);
+#endif
+#endif
+
+#if HW_TRACKING
+ /* MT6389 HW tracking init and default voltage */
+ hw_tracking_set("vproc", vproc1_track, vproc1_offset, vproc1_lb, vproc1_hb);
+#endif
+
+ dprintf(CRITICAL,"[PMIC] init_setting end. v190402\n");
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/pwrap/pwrap.c b/src/bsp/lk/platform/mt2731/drivers/pwrap/pwrap.c
new file mode 100644
index 0000000..6b2a01c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/pwrap/pwrap.c
@@ -0,0 +1,1370 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+/******************************************************************************
+ * MTK PMIC Wrapper Driver
+ *
+ * Copyright 2019 MediaTek Co.,Ltd.
+ *
+ * DESCRIPTION:
+ * This file provides API for other drivers to access PMIC registers
+ *
+ ******************************************************************************/
+
+#include <platform/pmic_wrap_init.h>
+#include <platform/pll.h>
+#if (PMIC_WRAP_PRELOADER)
+#elif (PMIC_WRAP_LK)
+#elif (PMIC_WRAP_KERNEL)
+#elif (PMIC_WRAP_CTP)
+#include <gpio.h>
+#include <upmu_hw.h>
+#else
+### Compile error, check SW ENV define
+#endif
+
+
+/************* marco ******************************************************/
+#if (PMIC_WRAP_PRELOADER)
+#elif (PMIC_WRAP_LK)
+#elif (PMIC_WRAP_KERNEL)
+#elif (PMIC_WRAP_SCP)
+#elif (PMIC_WRAP_CTP)
+#else
+### Compile error, check SW ENV define
+#endif
+
+#ifdef PMIC_WRAP_NO_PMIC
+#if !(PMIC_WRAP_KERNEL)
+signed int pwrap_wacs2(unsigned int write, unsigned int adr,
+ unsigned int wdata, unsigned int *rdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+signed int pwrap_read(unsigned int adr, unsigned int *rdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+signed int pwrap_write(unsigned int adr, unsigned int wdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+#endif
+signed int pwrap_wacs2_read(unsigned int adr, unsigned int *rdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+/* Provide PMIC write API */
+signed int pwrap_wacs2_write(unsigned int adr, unsigned int wdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+signed int pwrap_read_nochk(unsigned int adr, unsigned int *rdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+signed int pwrap_write_nochk(unsigned int adr, unsigned int wdata)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+/*
+ *pmic_wrap init,init wrap interface
+ */
+signed int pwrap_init(void)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+signed int pwrap_init_preloader(void)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+ return 0;
+}
+
+void pwrap_dump_all_register(void)
+{
+ PWRAPLOG("[PMIC_WRAP]PMIC_WRAP do Nothing.\n");
+}
+
+
+#else /* #ifdef PMIC_WRAP_NO_PMIC */
+/*********************start ---internal API***********************************/
+static int _pwrap_timeout_ns(unsigned long long start_time_ns,
+ unsigned long long timeout_time_ns);
+static unsigned long long _pwrap_get_current_time(void);
+static unsigned long long _pwrap_time2ns(unsigned long long time_us);
+static signed int _pwrap_reset_spislv(void);
+static signed int _pwrap_init_dio(unsigned int dio_en);
+static signed int _pwrap_init_reg_clock(unsigned int regck_sel);
+static void _pwrap_enable(void);
+static void _pwrap_starve_set(void);
+static signed int _pwrap_wacs2_nochk(unsigned int write, unsigned int adr,
+ unsigned int wdata, unsigned int *rdata);
+/*********************test API************************************************/
+static inline void pwrap_dump_ap_register(void);
+static unsigned int pwrap_write_test(void);
+static unsigned int pwrap_read_test(void);
+signed int pwrap_wacs2_read(unsigned int adr, unsigned int *rdata);
+signed int pwrap_wacs2_write(unsigned int adr, unsigned int wdata);
+/************* end--internal API**********************************************/
+/*********************** external API for pmic_wrap user *********************/
+signed int pwrap_wacs2_read(unsigned int adr, unsigned int *rdata)
+{
+ pwrap_wacs2(0, adr, 0, rdata);
+ return 0;
+}
+
+/* Provide PMIC write API */
+signed int pwrap_wacs2_write(unsigned int adr, unsigned int wdata)
+{
+#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
+ unsigned int flag;
+
+ flag = WRITE_CMD | (1 << WRITE_PMIC);
+ pwrap_wacs2_ipi(adr, wdata, flag);
+#else
+ pwrap_wacs2(1, adr, wdata, 0);
+#endif
+ return 0;
+}
+
+signed int pwrap_read(unsigned int adr, unsigned int *rdata)
+{
+ return pwrap_wacs2(0,adr,0,rdata);
+}
+
+signed int pwrap_write(unsigned int adr, unsigned int wdata)
+{
+ return pwrap_wacs2(1,adr,wdata,0);
+}
+/******************************************************************************
+ *wrapper timeout
+ *****************************************************************************/
+/*use the same API name with kernel driver
+ *however,the timeout API in uboot use tick instead of ns
+ */
+
+#ifdef PWRAP_TIMEOUT
+static unsigned long long _pwrap_get_current_time(void)
+{
+ /* TBD return gpt4_get_current_tick(); */
+ return 0;
+}
+
+static int _pwrap_timeout_ns(unsigned long long start_time_ns,
+ unsigned long long timeout_time_ns)
+{
+ /* TBD return gpt4_timeout_tick(start_time_ns, timeout_time_ns); */
+ return 0;
+}
+
+static unsigned long long _pwrap_time2ns(unsigned long long time_us)
+{
+ /* TBD return gpt4_time2tick_us(time_us); */
+ return 0;
+}
+
+#else
+static unsigned long long _pwrap_get_current_time(void)
+{
+ return 0;
+}
+static int _pwrap_timeout_ns(unsigned long long start_time_ns,
+ unsigned long long elapse_time)
+{
+ return 0;
+}
+
+static unsigned long long _pwrap_time2ns(unsigned long long time_us)
+{
+ return 0;
+}
+
+#endif
+
+/* ##################################################################### */
+/* define macro and inline function (for do while loop) */
+/* ##################################################################### */
+typedef unsigned int(*loop_condition_fp) (unsigned int);
+
+static inline unsigned int wait_for_fsm_idle(unsigned int x)
+{
+ return GET_WACS2_FSM(x) != WACS_FSM_IDLE;
+}
+
+static inline unsigned int wait_for_fsm_vldclr(unsigned int x)
+{
+ return GET_WACS2_FSM(x) != WACS_FSM_WFVLDCLR;
+}
+
+static inline unsigned int wait_for_sync(unsigned int x)
+{
+ return GET_SYNC_IDLE2(x) != WACS_SYNC_IDLE;
+}
+
+static inline unsigned int wait_for_idle_and_sync(unsigned int x)
+{
+ return (GET_WACS2_FSM(x) != WACS_FSM_IDLE) ||
+ (GET_SYNC_IDLE2(x) != WACS_SYNC_IDLE);
+}
+
+static inline unsigned int wait_for_wrap_idle(unsigned int x)
+{
+ return (GET_WRAP_FSM(x) != 0x0) || (GET_WRAP_CH_DLE_RESTCNT(x) != 0x0);
+}
+
+static inline unsigned int wait_for_wrap_state_idle(unsigned int x)
+{
+ return GET_WRAP_AG_DLE_RESTCNT(x) != 0;
+}
+
+static inline unsigned int wait_for_man_idle_and_noreq(unsigned int x)
+{
+ return (GET_MAN_REQ(x) != MAN_FSM_NO_REQ) ||
+ (GET_MAN_FSM(x) != MAN_FSM_IDLE);
+}
+
+static inline unsigned int wait_for_man_vldclr(unsigned int x)
+{
+ return GET_MAN_FSM(x) != MAN_FSM_WFVLDCLR;
+}
+
+static inline unsigned int wait_for_cipher_ready(unsigned int x)
+{
+ return x != 3;
+}
+
+static inline unsigned int wait_for_stdupd_idle(unsigned int x)
+{
+ return GET_STAUPD_FSM(x) != 0x0;
+}
+
+/**************used at _pwrap_wacs2_nochk*************************************/
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+static inline unsigned int wait_for_state_ready_init(loop_condition_fp fp,
+ unsigned int timeout_us, void *wacs_register, unsigned int *read_reg)
+#else
+static inline unsigned int wait_for_state_ready_init(loop_condition_fp fp, unsigned int timeout_us,
+ volatile unsigned int *wacs_register, unsigned int *read_reg)
+#endif
+{
+ unsigned long long start_time_ns = 0, timeout_ns = 0;
+ unsigned int reg_rdata = 0x0;
+
+ start_time_ns = _pwrap_get_current_time();
+ timeout_ns = _pwrap_time2ns(timeout_us);
+
+ do {
+ if (_pwrap_timeout_ns(start_time_ns, timeout_ns)) {
+ PWRAPERR("ready_init timeout\n");
+ pwrap_dump_ap_register();
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+ reg_rdata = WRAP_RD32(wacs_register);
+ } while (fp(reg_rdata));
+
+ if (read_reg)
+ *read_reg = reg_rdata;
+
+ return 0;
+}
+
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+static inline unsigned int wait_for_state_idle(loop_condition_fp fp,
+ unsigned int timeout_us, void *wacs_register,
+ void *wacs_vldclr_register, unsigned int *read_reg)
+#else
+static inline unsigned int wait_for_state_idle(loop_condition_fp fp, unsigned int timeout_us,
+ volatile unsigned int *wacs_register, volatile unsigned int *wacs_vldclr_register, unsigned int *read_reg)
+#endif
+{
+ unsigned long long start_time_ns = 0, timeout_ns = 0;
+ unsigned int reg_rdata;
+
+ start_time_ns = _pwrap_get_current_time();
+ timeout_ns = _pwrap_time2ns(timeout_us);
+
+ do {
+ if (_pwrap_timeout_ns(start_time_ns, timeout_ns)) {
+ PWRAPERR("state_idle timeout\n");
+ pwrap_dump_ap_register();
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+ reg_rdata = WRAP_RD32(wacs_register);
+ if (GET_WACS2_INIT_DONE2(reg_rdata) != WACS_INIT_DONE) {
+ PWRAPERR("init isn't finished\n");
+ return E_PWR_NOT_INIT_DONE;
+ }
+ switch (GET_WACS2_FSM(reg_rdata)) {
+ case WACS_FSM_WFVLDCLR:
+ WRAP_WR32(wacs_vldclr_register, 1);
+ PWRAPERR("WACS_FSM = VLDCLR\n");
+ break;
+ case WACS_FSM_WFDLE:
+ PWRAPERR("WACS_FSM = WFDLE\n");
+ break;
+ case WACS_FSM_REQ:
+ PWRAPERR("WACS_FSM = REQ\n");
+ break;
+ default:
+ break;
+ }
+ } while (fp(reg_rdata));
+ if (read_reg)
+ *read_reg = reg_rdata;
+
+ return 0;
+}
+
+/**************used at pwrap_wacs2********************************************/
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+static inline unsigned int wait_for_state_ready(loop_condition_fp fp,
+ unsigned int timeout_us, void *wacs_register, unsigned int *read_reg)
+#else
+static inline unsigned int wait_for_state_ready(loop_condition_fp fp, unsigned int timeout_us,
+ volatile unsigned int *wacs_register, unsigned int *read_reg)
+#endif
+{
+ unsigned long long start_time_ns = 0, timeout_ns = 0;
+ unsigned int reg_rdata;
+
+ start_time_ns = _pwrap_get_current_time();
+ timeout_ns = _pwrap_time2ns(timeout_us);
+
+ do {
+ if (_pwrap_timeout_ns(start_time_ns, timeout_ns)) {
+ PWRAPERR("state_ready timeout\n");
+ pwrap_dump_ap_register();
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+ reg_rdata = WRAP_RD32(wacs_register);
+ if (GET_WACS2_INIT_DONE2(reg_rdata) != WACS_INIT_DONE) {
+ PWRAPERR("init isn't finished\n");
+ return E_PWR_NOT_INIT_DONE;
+ }
+ } while (fp(reg_rdata));
+ if (read_reg)
+ *read_reg = reg_rdata;
+
+ return 0;
+}
+
+/******************************************************
+ * Function : pwrap_wacs2()
+ * Description :
+ * Parameter :
+ * Return :
+ ******************************************************/
+signed int pwrap_wacs2(unsigned int write, unsigned int adr,
+ unsigned int wdata, unsigned int *rdata)
+{
+ unsigned int reg_rdata = 0;
+ unsigned int wacs_write = 0;
+ unsigned int wacs_adr = 0;
+ unsigned int wacs_cmd = 0;
+ unsigned int return_value = 0;
+
+ /* Check argument validation */
+ if ((write & ~(0x1)) != 0)
+ return E_PWR_INVALID_RW;
+ if ((adr & ~(0xffff)) != 0)
+ return E_PWR_INVALID_ADDR;
+ if ((wdata & ~(0xffff)) != 0)
+ return E_PWR_INVALID_WDAT;
+
+ /* Check IDLE & INIT_DONE in advance */
+ return_value =
+ wait_for_state_idle(wait_for_fsm_idle, TIMEOUT_WAIT_IDLE,
+ PMIC_WRAP_WACS2_RDATA, PMIC_WRAP_WACS2_VLDCLR, 0);
+ if (return_value != 0) {
+ PWRAPERR("fsm_idle fail,ret=%d\n", return_value);
+ goto FAIL;
+ }
+ wacs_write = write << 31;
+ wacs_adr = (adr >> 1) << 16;
+ wacs_cmd = wacs_write | wacs_adr | wdata;
+
+ WRAP_WR32(PMIC_WRAP_WACS2_CMD, wacs_cmd);
+ if (write == 0) {
+ if (rdata == NULL) {
+ PWRAPERR("rdata NULL\n");
+ return_value = E_PWR_INVALID_ARG;
+ goto FAIL;
+ }
+ return_value =
+ wait_for_state_ready(wait_for_fsm_vldclr, TIMEOUT_READ,
+ PMIC_WRAP_WACS2_RDATA, ®_rdata);
+ if (return_value != 0) {
+ PWRAPERR("fsm_vldclr fail,ret=%d\n", return_value);
+ return_value += 1;
+ goto FAIL;
+ }
+ *rdata = GET_WACS2_RDATA(reg_rdata);
+ WRAP_WR32(PMIC_WRAP_WACS2_VLDCLR, 1);
+ }
+
+FAIL:
+ if (return_value != 0) {
+ PWRAPCRI("%s fail,ret=%d\n", __func__, return_value);
+ PWRAPERR("BUG_ON\n");
+ }
+
+ return return_value;
+}
+
+
+/*********************internal API for pwrap_init***************************/
+
+/**********************************
+ * Function : _pwrap_wacs2_nochk()
+ * Description :
+ * Parameter :
+ * Return :
+ ***********************************/
+signed int pwrap_read_nochk(unsigned int adr, unsigned int *rdata)
+{
+ return _pwrap_wacs2_nochk(0, adr, 0, rdata);
+}
+
+signed int pwrap_write_nochk(unsigned int adr, unsigned int wdata)
+{
+ return _pwrap_wacs2_nochk(1, adr, wdata, 0);
+}
+
+static signed int _pwrap_wacs2_nochk(unsigned int write, unsigned int adr,
+ unsigned int wdata, unsigned int *rdata)
+{
+ unsigned int reg_rdata = 0x0;
+ unsigned int wacs_write = 0x0;
+ unsigned int wacs_adr = 0x0;
+ unsigned int wacs_cmd = 0x0;
+ unsigned int return_value = 0x0;
+
+ /* Check argument validation */
+ if ((write & ~(0x1)) != 0)
+ return E_PWR_INVALID_RW;
+ if ((adr & ~(0xffff)) != 0)
+ return E_PWR_INVALID_ADDR;
+ if ((wdata & ~(0xffff)) != 0)
+ return E_PWR_INVALID_WDAT;
+
+ /* Check IDLE */
+ return_value =
+ wait_for_state_ready_init(wait_for_fsm_idle, TIMEOUT_WAIT_IDLE,
+ PMIC_WRAP_WACS2_RDATA, 0);
+ if (return_value != 0) {
+ PWRAPERR("write fail,ret=%x\n", return_value);
+ return return_value;
+ }
+
+ wacs_write = write << 31;
+ wacs_adr = (adr >> 1) << 16;
+ wacs_cmd = wacs_write | wacs_adr | wdata;
+ WRAP_WR32(PMIC_WRAP_WACS2_CMD, wacs_cmd);
+
+ if (write == 0) {
+ if (rdata == NULL) {
+ PWRAPERR("rdata NULL\n");
+ return_value = E_PWR_INVALID_ARG;
+ return return_value;
+ }
+ return_value =
+ wait_for_state_ready_init(wait_for_fsm_vldclr,
+ TIMEOUT_READ, PMIC_WRAP_WACS2_RDATA, ®_rdata);
+ if (return_value != 0) {
+ PWRAPERR("fsm_vldclr fail,ret=%d\n", return_value);
+ return_value += 1;
+ return return_value;
+ }
+ *rdata = GET_WACS2_RDATA(reg_rdata);
+ WRAP_WR32(PMIC_WRAP_WACS2_VLDCLR, 1);
+ }
+
+ return 0;
+}
+static void __pwrap_soft_reset(void)
+{
+ PWRAPLOG("start reset wrapper\n");
+ WRAP_WR32(INFRA_GLOBALCON_RST2_SET, 0x1);
+ WRAP_WR32(INFRA_GLOBALCON_RST2_CLR, 0x1);
+}
+
+static void __pwrap_spi_clk_set(void)
+{
+#if MTK_PLATFORM_MT6763
+ PWRAPLOG("pwrap_spictl reset ok\n");
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+ WRAP_WR32(CLK_CFG_5_CLR, 0x00000093);
+ WRAP_WR32(CLK_CFG_5_SET, CLK_SPI_CK_26M);
+#endif
+#endif /*end of MTK_PLATFORM_MT6763 */
+ /*sys_ck cg enable, turn off clock*/
+ WRAP_WR32(MODULE_SW_CG_0_SET, 0x0000000f);
+ /* turn off clock*/
+ WRAP_WR32(MODULE_SW_CG_2_SET, 0x00000100);
+
+#if MTK_PLATFORM_MT2731
+ PWRAPLOG("pwrap_spictl reset ok\n");
+
+ /* Disable Fixed 26M Clock Control by SPM */
+ PWRAPLOG("PMICW_CLOCK_CTRL(before):0x%x\r\n", WRAP_RD32(PMICW_CLOCK_CTRL));
+ WRAP_WR32(PMICW_CLOCK_CTRL, WRAP_RD32(PMICW_CLOCK_CTRL) & 0xfffffffb);
+ PWRAPLOG("PMICW_CLOCK_CTRL(after):0x%x\r\n", WRAP_RD32(PMICW_CLOCK_CTRL));
+#endif /* end of MTK_PLATFORM_MT2731 */
+ /* toggle PMIC_WRAP and pwrap_spictl reset */
+ __pwrap_soft_reset();
+
+ /*sys_ck cg enable, turn on clock*/
+ WRAP_WR32(MODULE_SW_CG_0_CLR, 0x0000000f);
+ /* turn on clock*/
+ WRAP_WR32(MODULE_SW_CG_2_CLR, 0x00000100);
+ PWRAPLOG("spi clk set ....\n");
+}
+
+/************************************************
+ * Function : _pwrap_init_dio()
+ * Description :call it in pwrap_init,mustn't check init done
+ * Parameter :
+ * Return :
+ ************************************************/
+static signed int _pwrap_init_dio(unsigned int dio_en)
+{
+ unsigned int rdata = 0x0;
+
+ pwrap_write_nochk(PMIC_DEW_DIO_EN_ADDR, dio_en);
+#ifdef DUAL_PMICS
+ pwrap_write_nochk(EXT_DEW_DIO_EN, dio_en);
+#endif
+
+ do {
+ rdata = WRAP_RD32(PMIC_WRAP_WACS2_RDATA);
+ } while ((GET_WACS2_FSM(rdata) != WACS_FSM_IDLE) ||
+ (GET_SYNC_IDLE2(rdata) != WACS_SYNC_IDLE));
+
+#ifndef DUAL_PMICS
+ WRAP_WR32(PMIC_WRAP_DIO_EN, dio_en);
+#else
+ WRAP_WR32(PMIC_WRAP_DIO_EN, 0x2 | dio_en);
+#endif
+
+ return 0;
+}
+
+static void _pwrap_InitStaUpd(void)
+{
+
+#ifndef DUAL_PMICS
+ WRAP_WR32(PMIC_WRAP_STAUPD_GRPEN, 0x34);
+#else
+ WRAP_WR32(PMIC_WRAP_STAUPD_GRPEN, 0xfc);
+#endif
+
+#ifdef PMIC_WRAP_CRC_SUPPORT
+ /* CRC */
+#ifndef DUAL_PMICS
+ pwrap_write_nochk(PMIC_DEW_CRC_EN_ADDR, 0x1);
+ WRAP_WR32(PMIC_WRAP_CRC_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_SIG_ADR, PMIC_DEW_CRC_VAL_ADDR);
+#else
+ pwrap_write_nochk(PMIC_DEW_CRC_EN_ADDR, 0x1);
+ pwrap_write_nochk(EXT_DEW_CRC_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_CRC_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_SIG_ADR, (PMIC_EXT_DEW_CRC_VAL_ADDR << 16 | PMIC_DEW_CRC_VAL_ADDR));
+#endif
+#else
+ /* Signature */
+#ifndef DUAL_PMICS
+ WRAP_WR32(PMIC_WRAP_SIG_MODE, 0x1);
+ WRAP_WR32(PMIC_WRAP_SIG_ADR, PMIC_DEW_CRC_VAL_ADDR);
+ WRAP_WR32(PMIC_WRAP_SIG_VALUE, 0x83);
+#else
+ WRAP_WR32(PMIC_WRAP_SIG_MODE, 0x3);
+ WRAP_WR32(PMIC_WRAP_SIG_ADR, (PMIC_EXT_DEW_CRC_VAL_ADDR << 16 | PMIC_DEW_CRC_VAL_ADDR));
+ WRAP_WR32(PMIC_WRAP_SIG_VALUE, (0x83 << 16) | 0x83);
+#endif
+#endif /* end of crc */
+
+ WRAP_WR32(PMIC_WRAP_EINT_STA0_ADR, PMIC_CPU_INT_STA_ADDR);
+#ifdef DUAL_PMICS
+ WRAP_WR32(PMIC_WRAP_EINT_STA1_ADR, EXT_INT_STA);
+#endif
+
+
+#if MTK_PLATFORM_MT6356
+ /* MD ADC Interface */
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_LATEST_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_WP_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_0_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_1_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_2_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_3_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_4_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_5_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_6_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_7_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_8_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_9_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_10_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_11_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_12_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_13_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_14_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_15_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_16_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_17_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_18_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_19_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_20_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_21_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_22_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_23_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_24_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_25_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_26_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_27_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_28_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_29_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_30_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_31_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_ADDR);
+#elif MTK_PLATFORM_MT6389
+ /* MD ADC Interface */
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_LATEST_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_WP_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_0_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_1_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_2_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_3_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_4_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_5_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_6_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_7_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_8_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_9_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_10_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_11_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_12_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_13_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_14_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_15_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_16_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_17_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_18_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_19_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_20_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_21_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_22_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_23_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_24_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_25_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_26_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_27_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_28_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_29_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_30_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+ WRAP_WR32(PMIC_WRAP_MD_AUXADC_RDATA_31_ADDR, (PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR << 16) + PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR);
+#endif /* end of MTK_PLATFORM_MT6356 */
+
+}
+
+static void _pwrap_starve_set(void)
+{
+ WRAP_WR32(PMIC_WRAP_HARB_HPRIO, 0xf);
+#if MTK_PLATFORM_MT2731
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_0, 0x400);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_1, 0x402);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_2, 0x402);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_3, 0x40e);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_4, 0x402);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_5, 0x427);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_6, 0x427);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_7, 0x4a4);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_8, 0x413);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_9, 0x417);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_10, 0x417);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_11, 0x47b);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_12, 0x47b);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_13, 0x45b);
+#elif MTK_PLATFORM_MT6763
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_0, 0x402);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_1, 0x403);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_2, 0x403);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_3, 0x403);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_4, 0x40f);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_5, 0x420);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_6, 0x428);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_7, 0x428);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_8, 0x413);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_9, 0x417);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_10, 0x417);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_11, 0x47c);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_12, 0x47c);
+ WRAP_WR32(PMIC_WRAP_STARV_COUNTER_13, 0x740);
+#endif
+
+}
+
+static void _pwrap_enable(void)
+{
+
+#if (MTK_PLATFORM_MT2731)
+ WRAP_WR32(PMIC_WRAP_HPRIO_ARB_EN, 0x66D27);
+#elif MTK_PLATFORM_MT6763
+ WRAP_WR32(PMIC_WRAP_HPRIO_ARB_EN, 0x3fa65);
+#endif /* end of MTK_PLATFORM_MT2731 */
+ WRAP_WR32(PMIC_WRAP_WACS0_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_WACS1_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_WACS2_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_WACS3_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_STAUPD_CTRL, 0x5); /* 100us */
+ WRAP_WR32(PMIC_WRAP_WDT_UNIT, 0xf);
+ WRAP_WR32(PMIC_WRAP_WDT_SRC_EN_0, 0xffffffff);
+ WRAP_WR32(PMIC_WRAP_WDT_SRC_EN_1, 0xffffffff);
+#if (MTK_PLATFORM_MT2731)
+ WRAP_WR32(PMIC_WRAP_TIMER_CTRL, 0x3);
+#elif MTK_PLATFORM_MT6763
+ WRAP_WR32(PMIC_WRAP_TIMER_EN, 0x1);
+#endif /* end of MTK_PLATFORM_MT2731 */
+ WRAP_WR32(PMIC_WRAP_INT0_EN, 0xffffffff);
+ WRAP_WR32(PMIC_WRAP_INT1_EN, 0x000017ff); /* disable Matching interrupt for bit 13 */
+}
+
+/************************************************
+ * Function : _pwrap_init_sistrobe()
+ * scription : Initialize SI_CK_CON and SIDLY
+ * Parameter :
+ * Return :
+ ************************************************/
+static signed int _pwrap_init_sistrobe(int dual_si_sample_settings)
+{
+ unsigned int rdata;
+ int si_en_sel, si_ck_sel, si_dly, si_sample_ctrl;
+ char result_faulty = 0;
+ char found;
+ int test_data[30] = {0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669,
+ 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A,
+ 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27
+ };
+ int i;
+ int error = 0;
+
+ /* TINFO = "[DrvPWRAP_InitSiStrobe] SI Strobe Calibration For PMIC 0............" */
+ /* TINFO = "[DrvPWRAP_InitSiStrobe] Scan For The First Valid Sampling Clock Edge......" */
+ found = 0;
+ for (si_en_sel = 0; si_en_sel < 8; si_en_sel++) {
+ for (si_ck_sel = 0; si_ck_sel < 2; si_ck_sel++) {
+ si_sample_ctrl = (si_en_sel << 6) | (si_ck_sel << 5);
+ WRAP_WR32(PMIC_WRAP_SI_SAMPLE_CTRL, si_sample_ctrl);
+
+ pwrap_read_nochk(PMIC_DEW_READ_TEST_ADDR, &rdata);
+ if (rdata == DEFAULT_VALUE_READ_TEST) {
+ PWRAPLOG("First Valid Sampling Clock Found!!!\n");
+ PWRAPLOG("si_en_sel = %x, si_ck_sel = %x\n",
+ si_en_sel, si_ck_sel);
+ PWRAPLOG("si_sample_ctrl = %x, rdata = %x\n",
+ si_sample_ctrl, rdata);
+ found = 1;
+ break;
+ }
+ PWRAPCRI("si_en_sel = %x, si_ck_sel = %x\n",
+ si_en_sel, si_ck_sel);
+ PWRAPCRI("si_sample_ctrl = %x, rdata = %x\n",
+ si_sample_ctrl, rdata);
+ }
+ if (found == 1)
+ break;
+ }
+ if (found == 0) {
+ result_faulty |= 0x1;
+ PWRAPCRI("result_faulty (not found) = %d\n", result_faulty);
+ }
+ if((si_en_sel == 7) && (si_ck_sel == 1)) {
+ result_faulty |= 0x2;
+ PWRAPCRI("result_faulty (last setting) = %d\n", result_faulty);
+ }
+ for (si_dly = 0; si_dly < 10; si_dly++) {
+ pwrap_write_nochk(PMIC_RG_SPI_DLY_SEL_ADDR, si_dly);
+
+ error = 0;
+#ifndef SPEED_UP_PWRAP_INIT
+ for (i = 0; i < 30; i++)
+#else
+ for (i = 0; i < 1; i++)
+#endif
+ {
+ pwrap_write_nochk(PMIC_DEW_WRITE_TEST_ADDR, test_data[i]);
+ pwrap_read_nochk(PMIC_DEW_WRITE_TEST_ADDR, &rdata);
+ if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) {
+ PWRAPERR("Data Boundary is Found !!!\n");
+ PWRAPCRI("si_dly = %x, rdata = %x\n", si_dly, rdata);
+ error = 1;
+ break;
+ }
+ }
+ if (error == 1)
+ break;
+ PWRAPLOG("si_dly = %x, *RG_SPI_CON2 = %x, rdata = %x\n",
+ si_dly, si_dly, rdata);
+ }
+
+ PWRAPCRI("si_sample_ctrl=0x%x(before)\n", si_sample_ctrl);
+ /* si_sample_ctrl = (((si_en_sel << 1) | si_ck_sel) + 1) << 2;*/
+ si_sample_ctrl = si_sample_ctrl + 0x20;
+ WRAP_WR32(PMIC_WRAP_SI_SAMPLE_CTRL, si_sample_ctrl);
+ if (si_dly == 10) {
+ PWRAPLOG("SI Strobe Calibration For PMIC 0 Done\n");
+ PWRAPLOG("si_sample_ctrl = %x, si_dly = %x\n",
+ si_sample_ctrl, si_dly);
+ si_dly--;
+ }
+ PWRAPERR("SI Strobe Calibration For PMIC 0 Done\n");
+ PWRAPCRI("si_sample_ctrl = %x, si_dly = %x\n",
+ si_sample_ctrl, si_dly);
+
+ if (result_faulty != 0)
+ return result_faulty;
+
+ /* Read Test */
+ pwrap_read_nochk(PMIC_DEW_READ_TEST_ADDR, &rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ PWRAPERR("_pwrap_init_sistrobe Read Test Failed\n");
+ PWRAPCRI("Failed, rdata = %x, exp = 0x5aa5\n", rdata);
+ return 0x10;
+ }
+ PWRAPLOG("_pwrap_init_sistrobe Read Test ok\n");
+
+ return 0;
+}
+
+static int __pwrap_InitSPISLV(void)
+{
+ pwrap_write_nochk(PMIC_RG_SPI_CLK_FILTER_EN_ADDR, 0xf0); /* turn on IO filter function */
+ pwrap_write_nochk(PMIC_RG_SMT_SPI_CLK_ADDR, 0xf); /* turn on IO SMT function to improve noise immunity */
+ pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR_ADDR, 0xf0); /* turn off IO pull function for power saving */
+#if MTK_PLATFORM_MT6356
+ pwrap_write_nochk(PMIC_RG_SLP_RW_EN_ADDR, 0x1); /* turn off IO pull function for power saving */
+ /* set PMIC driving to 4mA */
+ pwrap_write_nochk(PMIC_RG_OCTL_SPI_CLK_ADDR, 0x8888);
+#elif MTK_PLATFORM_MT6389
+ /* enable SPI in SODI-3.0 */
+ pwrap_write_nochk(PMIC_RG_SPI_MISO_MODE_SEL_ADDR, 0x1);
+#endif /* end of MTK_PLATFORM_MT6356 */
+
+
+ return 0;
+}
+
+/******************************************************
+ * Function : _pwrap_reset_spislv()
+ * Description :
+ * Parameter :
+ * Return :
+ ******************************************************/
+static signed int _pwrap_reset_spislv(void)
+{
+ unsigned int ret = 0;
+ unsigned int return_value = 0;
+
+ WRAP_WR32(PMIC_WRAP_HPRIO_ARB_EN, DISABLE_ALL);
+ WRAP_WR32(PMIC_WRAP_WRAP_EN, 0x0);
+ WRAP_WR32(PMIC_WRAP_MUX_SEL, MANUAL_MODE);
+ WRAP_WR32(PMIC_WRAP_MAN_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_DIO_EN, 0x0);
+
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_CSL << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_OUTS << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_CSH << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_OUTS << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_OUTS << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_OUTS << 8));
+ WRAP_WR32(PMIC_WRAP_MAN_CMD, (OP_WR << 13) | (OP_OUTS << 8));
+ return_value =
+ wait_for_state_ready_init(wait_for_sync, TIMEOUT_WAIT_IDLE,
+ PMIC_WRAP_WACS2_RDATA, 0);
+
+ if (return_value != 0) {
+ PWRAPERR("reset_spislv fail,ret=%x\n", return_value);
+ ret = E_PWR_TIMEOUT;
+ goto timeout;
+ }
+
+ WRAP_WR32(PMIC_WRAP_MAN_EN, 0x0);
+ WRAP_WR32(PMIC_WRAP_MUX_SEL, WRAPPER_MODE);
+
+timeout:
+ WRAP_WR32(PMIC_WRAP_MAN_EN, 0x0);
+ WRAP_WR32(PMIC_WRAP_MUX_SEL, WRAPPER_MODE);
+ return ret;
+}
+
+static signed int _pwrap_init_reg_clock(unsigned int regck_sel)
+{
+ unsigned int rdata;
+
+ WRAP_WR32(PMIC_WRAP_EXT_CK_WRITE, 0x1);
+ pwrap_read_nochk(PMIC_GPIO_PULLEN0_ADDR, &rdata);
+ PWRAPLOG("PMIC_GPIO_PULLEN0_ADDR:0x%x\n", rdata);
+ pwrap_write_nochk(PMIC_GPIO_PULLEN0_ADDR, 0x0);
+ pwrap_read_nochk(PMIC_GPIO_PULLEN0_ADDR, &rdata);
+ PWRAPLOG("PMIC_GPIO_PULLEN0_ADDR:0x%x\n", rdata);
+
+#ifndef SLV_CLK_1M
+#ifndef DUAL_PMICS
+ /* Set Read Dummy Cycle Number (Slave Clock is 18MHz) */
+ _pwrap_wacs2_nochk(1, PMIC_DEW_RDDMY_NO_ADDR, 0x8, &rdata);
+ WRAP_WR32(PMIC_WRAP_RDDMY, 0x8);
+ PWRAPLOG("Set Read Dummy Cycle ok\n");
+#else
+ _pwrap_wacs2_nochk(1, PMIC_DEW_RDDMY_NO_ADDR, 0x8, &rdata);
+ _pwrap_wacs2_nochk(1, EXT_DEW_RDDMY_NO, 0x8, &rdata);
+ WRAP_WR32(PMIC_WRAP_RDDMY, 0x0808);
+ PWRAPLOG("NO_SLV_CLK_1M Set Read Dummy Cycle dual_pmics\n");
+#endif
+#else
+#ifndef DUAL_PMICS
+ /* Set Read Dummy Cycle Number (Slave Clock is 1MHz) */
+ _pwrap_wacs2_nochk(1, PMIC_DEW_RDDMY_NO_ADDR, 0x68, &rdata);
+ WRAP_WR32(PMIC_WRAP_RDDMY, 0x68);
+ PWRAPLOG("SLV_CLK_1M Set Read Dummy Cycle\n");
+#else
+ _pwrap_wacs2_nochk(1, PMIC_DEW_RDDMY_NO_ADDR, 0x68, &rdata);
+ _pwrap_wacs2_nochk(1, EXT_DEW_RDDMY_NO, 0x68, &rdata);
+ WRAP_WR32(PMIC_WRAP_RDDMY, 0x6868);
+ PWRAPLOG("Set Read Dummy Cycle dual_pmic ok\n");
+#endif
+#endif
+
+ /* Config SPI Waveform according to reg clk */
+ if (regck_sel == 1) { /* Slave Clock is 18MHz */
+ /* wait data written into register => 4T_PMIC:
+ * CSHEXT_WRITE_START+EXT_CK+CSHEXT_WRITE_END+CSLEXT_START
+ */
+ WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE, 0x0);
+ WRAP_WR32(PMIC_WRAP_CSHEXT_READ, 0x0);
+ WRAP_WR32(PMIC_WRAP_CSLEXT_WRITE, 0x0);
+ WRAP_WR32(PMIC_WRAP_CSLEXT_READ, 0x0); //TBD
+ } else { /*Safe Mode*/
+ WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE, 0x0f0f);
+ WRAP_WR32(PMIC_WRAP_CSHEXT_READ, 0x0f0f);
+ WRAP_WR32(PMIC_WRAP_CSLEXT_WRITE, 0x0f0f);
+ WRAP_WR32(PMIC_WRAP_CSLEXT_READ, 0x0f0f);
+ }
+
+ return 0;
+}
+
+static int _pwrap_wacs2_write_test(int pmic_no)
+{
+ unsigned int rdata;
+
+ if (pmic_no == 0) {
+ pwrap_write_nochk(PMIC_DEW_WRITE_TEST_ADDR, 0xa55a);
+ pwrap_read_nochk(PMIC_DEW_WRITE_TEST_ADDR, &rdata);
+ if (rdata != 0xa55a) {
+ PWRAPERR("Error: w_rdata = 0x%x, exp = 0xa55a\n", rdata);
+ return E_PWR_WRITE_TEST_FAIL;
+ }
+ }
+
+ return 0;
+}
+
+static unsigned int pwrap_read_test(void)
+{
+ unsigned int rdata = 0;
+ unsigned int return_value = 0;
+ /* Read Test */
+ PWRAPLOG("start pwrap_read_test\n");
+ return_value = pwrap_wacs2_read(PMIC_DEW_READ_TEST_ADDR, &rdata);
+ PWRAPLOG("rdata=0x%x\n", rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ PWRAPERR("Error: r_rdata = 0x%x, exp = 0x5aa5\n", rdata);
+ PWRAPERR("Error: return_value = 0x%x\n", return_value);
+ return E_PWR_READ_TEST_FAIL;
+ }
+ PWRAPLOG("Read Test pass, return_value = 0x%d\n", return_value);
+
+ return 0;
+}
+static unsigned int pwrap_write_test(void)
+{
+ unsigned int rdata = 0;
+ unsigned int sub_return = 0;
+ unsigned int sub_return1 = 0;
+
+ /* Write test using WACS2 */
+ PWRAPLOG("start pwrap_write_test\n");
+ sub_return = pwrap_wacs2_write(PMIC_DEW_WRITE_TEST_ADDR,
+ DEFAULT_VALUE_WRITE_TEST);
+ PWRAPLOG("after pwrap_write\n");
+
+ sub_return1 = pwrap_wacs2_read(PMIC_DEW_WRITE_TEST_ADDR, &rdata);
+ PWRAPLOG("rdata=0x%x (read back)\n", rdata);
+ if ((rdata != DEFAULT_VALUE_WRITE_TEST) ||
+ (sub_return != 0) || (sub_return1 != 0)) {
+ PWRAPERR("Error: w_rdata = 0x%x, exp = 0xa55a\n", rdata);
+ PWRAPERR("Error: sub_return = 0x%x\n", sub_return);
+ PWRAPERR("Error: sub_return1 = 0x%x\n", sub_return1);
+ return E_PWR_INIT_WRITE_TEST;
+ }
+ PWRAPLOG("write Test pass\n");
+
+ return 0;
+}
+static void pwrap_ut(unsigned int ut_test)
+{
+#ifdef PMIC_WRAP_DEBUG
+ unsigned int sub_return = 0;
+#endif
+ switch (ut_test) {
+ case 1:
+ pwrap_write_test();
+ break;
+ case 2:
+ pwrap_read_test();
+ break;
+ case 3:
+#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
+ pwrap_wacs2_ipi(0x10010000 + 0xD8, 0xffffffff, (WRITE_CMD | WRITE_PMIC_WRAP));
+ break;
+#endif
+ case 4:
+#ifdef PMIC_WRAP_DEBUG
+ sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST_ADDR, 0x1234);
+ sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST_ADDR, 0x4321);
+ sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST_ADDR, 0xF0F0);
+ PWRAPLOG("%x\n", sub_return);
+#endif
+ break;
+ default:
+ PWRAPLOG("default test.\n");
+ break;
+ }
+}
+
+signed int pwrap_init(void)
+{
+ signed int sub_return = 0;
+ unsigned int rdata = 0;
+
+ PWRAPLOG("pwrap_init start!!!!!!!!!!!!!\n");
+#if MTK_PLATFORM_MT2731
+ /* Set SoC SPI IO Driving Strength to 4 mA */
+ WRAP_WR32(IOCFG_RB_DRV_CFG1_CLR, (0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0));
+ WRAP_WR32(IOCFG_RB_DRV_CFG1_SET, (0x1<<9)|(0x1<<6)|(0x1<<3)|(0x1<<0));
+
+ /* Set SPI MI IO to Pull Down */
+ WRAP_WR32(IOCFG_RB_PU_CFG0_CLR, (0x1 << 12));
+ WRAP_WR32(IOCFG_RB_PD_CFG0_SET, (0x1 << 12));
+#elif MTK_PLATFORM_MT6763
+#define PWRAP_GPIO_DRIVING_ADDR 0x11F200A0
+ WRAP_WR32(PWRAP_GPIO_DRIVING_ADDR, WRAP_RD32(PWRAP_GPIO_DRIVING_ADDR)|(0x1<<16));
+ PWRAPLOG("Preloader GPIO144-147 driving = 0x%x\n", WRAP_RD32(PWRAP_GPIO_DRIVING_ADDR));
+#endif /* end of #if MTK_PLATFORM_MT2731 */
+ __pwrap_spi_clk_set();
+
+ PWRAPLOG("__pwrap_spi_clk_set ok\n");
+
+ /* Enable DCM */
+ PWRAPLOG("Not need to enable DCM\n");
+
+ /* Reset SPISLV */
+ sub_return = _pwrap_reset_spislv();
+ if (sub_return != 0) {
+ PWRAPERR("reset_spislv fail,ret=%x\n", sub_return);
+ return E_PWR_INIT_RESET_SPI;
+ }
+ PWRAPLOG("Reset SPISLV ok\n");
+
+ /* Enable WRAP */
+ WRAP_WR32(PMIC_WRAP_WRAP_EN, 0x1);
+ PWRAPLOG("Enable WRAP ok\n");
+
+ /* Enable WACS2 */
+ WRAP_WR32(PMIC_WRAP_WACS2_EN, 0x1);
+ WRAP_WR32(PMIC_WRAP_HPRIO_ARB_EN, 0x4); /* ONLY WACS2 */
+
+ PWRAPLOG("Enable WACS2 ok\n");
+
+ /* SPI Waveform Configuration. 0: Safe Mode, 1: SPISLV Clock is 18MHz */
+ sub_return = _pwrap_init_reg_clock(1);
+ if (sub_return != 0) {
+ PWRAPERR("init_reg_clock fail,ret=%x\n", sub_return);
+ return E_PWR_INIT_REG_CLOCK;
+ }
+ PWRAPLOG("_pwrap_init_reg_clock ok\n");
+
+ /* SPI Slave Configuration */
+ sub_return = __pwrap_InitSPISLV();
+ if (sub_return != 0) {
+ PWRAPERR("InitSPISLV Failed, ret = %x", sub_return);
+ return -1;
+ }
+
+ /* Enable DIO mode */
+ sub_return = _pwrap_init_dio(1);
+ if (sub_return != 0) {
+ PWRAPERR("dio test error,err=%x, ret=%x\n", 0x11, sub_return);
+ return E_PWR_INIT_DIO;
+ }
+ PWRAPLOG("_pwrap_init_dio ok\n");
+
+ /* Input data calibration flow; */
+ sub_return = _pwrap_init_sistrobe(0);
+ if (sub_return != 0) {
+ PWRAPERR("InitSiStrobe fail,ret=%x\n", sub_return);
+ return E_PWR_INIT_SIDLY;
+ }
+ PWRAPLOG("_pwrap_init_sistrobe ok\n");
+
+ PWRAPLOG("PMIC_WRAP_SI_SAMPLE_CTRL = 0x%x\n", WRAP_RD32(PMIC_WRAP_SI_SAMPLE_CTRL));
+ PWRAPLOG("PMIC_WRAP_SI_SAMPLE_CTRL_ULPOSC = 0x%x\n", WRAP_RD32(PMIC_WRAP_SI_SAMPLE_CTRL_ULPOSC));
+
+#if 0
+ /* Enable Encryption */
+ sub_return = _pwrap_init_cipher();
+ if (sub_return != 0) {
+ PWRAPERR("Encryption fail, ret=%x\n", sub_return);
+ return E_PWR_INIT_CIPHER;
+ }
+ PWRAPLOG("_pwrap_init_cipher ok\n");
+#endif
+ /* Write test using WACS2. Check write test default value */
+ sub_return = _pwrap_wacs2_write_test(0);
+ if (sub_return != 0) {
+ PWRAPERR("write test fail\n");
+ return E_PWR_INIT_WRITE_TEST;
+ }
+ PWRAPLOG("_pwrap_wacs2_write_test ok\n");
+
+ /* Status update function initialization
+ * 1. Signature Checking using CRC (CRC 0 only)
+ * 2. EINT update
+ * 3. Read back Auxadc thermal data for GPS
+ */
+ _pwrap_InitStaUpd();
+ PWRAPLOG("_pwrap_InitStaUpd ok\n");
+
+ /* PMIC_WRAP starvation setting */
+ _pwrap_starve_set();
+ PWRAPLOG("_pwrap_starve_set ok\n");
+
+ /* PMIC_WRAP enables */
+ _pwrap_enable();
+ PWRAPLOG("_pwrap_enable ok\n");
+
+ /* Backward Compatible Settings */
+ /* WRAP_WR32(PMIC_WRAP_BWC_OPTIONS, WRAP_RD32(PMIC_WRAP_BWC_OPTIONS) | 0x8); */
+
+ /* Initialization Done */
+ WRAP_WR32(PMIC_WRAP_INIT_DONE0, 0x1);
+ WRAP_WR32(PMIC_WRAP_INIT_DONE1, 0x1);
+ WRAP_WR32(PMIC_WRAP_INIT_DONE2, 0x1);
+ WRAP_WR32(PMIC_WRAP_INIT_DONE3, 0x1);
+
+ PWRAPLOG("pwrap_init Done!!!!!!!!!\n");
+
+#ifdef PMIC_WRAP_DEBUG
+ /* WACS2 UT */
+ pwrap_ut(2);
+ pwrap_ut(1);
+#endif
+ PWRAPLOG("channel pass\n");
+
+ PWRAPLOG("channel pass \n\r ");
+
+ /* Read Last three command */
+ pwrap_read_nochk(PMIC_RECORD_CMD0_ADDR, &rdata);
+ PWRAPCRI("RECORD_CMD0: 0x%x (Last one command addr)\n", (rdata & 0x3fff));
+ pwrap_read_nochk(PMIC_RECORD_WDATA0_ADDR, &rdata);
+ PWRAPCRI("RECORD_WDATA0:0x%x (Last one command wdata)\n", rdata);
+ pwrap_read_nochk(PMIC_RECORD_CMD1_ADDR, &rdata);
+ PWRAPCRI("RECORD_CMD1: 0x%x (Last second command addr)\n", (rdata & 0x3fff));
+ pwrap_read_nochk(PMIC_RECORD_WDATA1_ADDR, &rdata);
+ PWRAPCRI("RECORD_WDATA1:0x%x (Last second command wdata)\n", rdata);
+ pwrap_read_nochk(PMIC_RECORD_CMD2_ADDR, &rdata);
+ PWRAPCRI("RECORD_CMD2: 0x%x (Last third command addr)\n", (rdata & 0x3fff));
+ pwrap_read_nochk(PMIC_RECORD_WDATA2_ADDR, &rdata);
+ PWRAPCRI("RECORD_WDATA2:0x%x (Last third command wdata)\n", rdata);
+
+ /* Enable Command Recording */
+ sub_return = pwrap_write_nochk(PMIC_RG_SPI_RSV_ADDR, 0x3);
+ if (sub_return != 0)
+ PWRAPERR("enable spi debug fail, ret=%x\n", sub_return);
+ PWRAPLOG("enable spi debug ok\n");
+
+ /* Clear Last three record command */
+ sub_return = pwrap_write_nochk(PMIC_RG_SPI_RECORD_CLR_ADDR, 0x1);
+ if (sub_return != 0)
+ PWRAPERR("clear record command fail, ret=%x\n", sub_return);
+ sub_return = pwrap_write_nochk(PMIC_RG_SPI_RECORD_CLR_ADDR, 0x0);
+ if (sub_return != 0)
+ PWRAPERR("clear record command fail, ret=%x\n", sub_return);
+ PWRAPLOG("clear record command ok\n\r");
+
+ /* WRAP RG monitor */
+#ifdef PMIC_WRAP_MATCH_SUPPORT
+ /* enable matching mode */
+ PWRAPLOG("PMIC_WRAP_MONITOR_MODE = Matching Mode\n");
+
+ /* enable Matching interrupt for bit 13 */
+ WRAP_WR32(PMIC_WRAP_INT1_EN, WRAP_RD32(PMIC_WRAP_INT1_EN) | 0x2000);
+ PWRAPLOG("PMIC_WRAP_INT1_EN = 0x%x\n", WRAP_RD32(PMIC_WRAP_INT1_EN));
+
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_1, 0x1ffff);
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_2, 0xffff8A8B); /* 0x8A8B = monitor write addr 0x1516 >> 1 = 0xA8B */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_3, 0x00020000); /* 0x0100 = monitor bit 1 when 0x1 -> 0x0 */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_0, 0x8); /* clear log */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_0, 0x5); /* Matching mode and Stop recording after interrupt trigger */
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_0 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_0));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_1 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_1));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_2 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_2));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_3 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_3));
+#else
+ /* enable logging mode */
+ PWRAPLOG("PMIC_WRAP_MONITOR_MODE = Logging Mode\n");
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_1, 0x1feff); /* disable monitor MD HW channel (CH8) */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_2, 0x0); /* record all addr (mask+addr) */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_3, 0x0); /* record all wdata (mask+addr) */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_0, 0x8); /* clear log */
+ WRAP_WR32(PMIC_WRAP_MONITOR_CTRL_0, 0x1); /* reenable (Matching mode and Continue recording after interrupt trigger) */
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_0 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_0));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_1 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_1));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_2 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_2));
+ PWRAPLOG("PMIC_WRAP_MONITOR_CTRL_3 = 0x%x\n", WRAP_RD32(PMIC_WRAP_MONITOR_CTRL_3));
+#endif
+#if 0
+ unsigned int rgdata=0;
+ pwrap_read(MT6356_PPCCTL0, &rgdata);
+ rgdata |= 0x1;
+ pwrap_write(MT6356_PPCCTL0, rgdata);
+ pwrap_read(MT6356_PPCCTL0, &rgdata);
+ PWRAPLOG("PMIC_RG_PWRHOLD=%x(should be 1)\n", rgdata);
+#endif
+ return 0;
+}
+
+/*-------------------pwrap debug---------------------*/
+static inline void pwrap_dump_ap_register(void)
+{
+ unsigned int i = 0, offset = 0;
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+ unsigned int *reg_addr;
+#else
+ volatile unsigned int *reg_addr;
+#endif
+ unsigned int reg_value = 0;
+
+ PWRAPERR("dump reg\n");
+ for (i = 0; i <= PMIC_WRAP_REG_RANGE; i++) {
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+ reg_addr = (unsigned int *)(PWRAP_BASE + i * 4);
+ reg_value = WRAP_RD32(reg_addr);
+ PWRAPERR("addr:0x%p = 0x%x\n", reg_addr, reg_value);
+#else
+ reg_addr = (unsigned int *)(uintptr_t)(PWRAP_BASE + i * 4);
+ reg_value = WRAP_RD32(reg_addr);
+ PWRAPERR("addr:0x%p = 0x%x\n", reg_addr, reg_value);
+#endif
+ }
+ for (i = 0; i <= 14; i++) {
+ offset = 0xc00 + i * 4;
+#if (PMIC_WRAP_KERNEL) || (PMIC_WRAP_CTP)
+ reg_addr = (unsigned int *) (PWRAP_BASE + offset);
+ reg_value = WRAP_RD32(reg_addr);
+ PWRAPERR("addr:0x%p = 0x%x\n", reg_addr, reg_value);
+#else
+ reg_addr = (unsigned int *)(uintptr_t)(PWRAP_BASE + offset);
+ reg_value = WRAP_RD32(reg_addr);
+ PWRAPERR("addr:0x%p = 0x%x\n", reg_addr, reg_value);
+#endif
+ }
+}
+
+void pwrap_dump_all_register(void)
+{
+ pwrap_dump_ap_register();
+}
+
+static int is_pwrap_init_done(void)
+{
+ int ret = 0;
+
+ ret = WRAP_RD32(PMIC_WRAP_INIT_DONE2);
+ PWRAPLOG("is_pwrap_init_done %d\n", ret);
+ if ((ret & 0x1) == 1)
+ return 0;
+ return -1;
+}
+
+signed int pwrap_init_preloader(void)
+{
+ unsigned int pwrap_ret = 0, i = 0;
+
+ PWRAPFUC();
+ if (0 == is_pwrap_init_done()) {
+ PWRAPLOG("[PMIC_WRAP]wrap_init already init, do nothing\n");
+ return 0;
+ }
+ for (i = 0; i < 3; i++) {
+ pwrap_ret = pwrap_init();
+ if (pwrap_ret != 0) {
+ PWRAPERR("init fail, ret=%x.\n",pwrap_ret);
+ if (i >= 2)
+ PWRAPERR("init fail, ret=%x.\n",pwrap_ret);
+ } else {
+ PWRAPERR("init pass, ret=%x.\n\r",pwrap_ret);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+#endif /*endif PMIC_WRAP_NO_PMIC */
diff --git a/src/bsp/lk/platform/mt2731/drivers/rules.mk b/src/bsp/lk/platform/mt2731/drivers/rules.mk
new file mode 100644
index 0000000..69af02a
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/rules.mk
@@ -0,0 +1,74 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+MODULE := $(LOCAL_DIR)
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/dcm/dcm.c \
+ $(LOCAL_DIR)/dcm/dcm_ctrl.c \
+ $(LOCAL_DIR)/gpio/mt_gpio.c \
+ $(LOCAL_DIR)/key/mtk_key.c \
+ $(LOCAL_DIR)/pll/pll.c \
+ $(LOCAL_DIR)/spm/spm_mtcmos.c \
+ $(LOCAL_DIR)/trng/mtk_trng.c \
+ $(LOCAL_DIR)/uart/uart.c \
+ $(LOCAL_DIR)/musb/mt_usb.c \
+ $(LOCAL_DIR)/musb/mt_usb_qmu.c \
+ $(LOCAL_DIR)/musb/usb_i2c.c \
+ $(LOCAL_DIR)/musb/phy-a60810.c \
+ $(LOCAL_DIR)/wdt/mtk_wdt.c \
+ $(LOCAL_DIR)/wdt/mtk_drm.c \
+ $(LOCAL_DIR)/pwrap/pwrap.c \
+ $(LOCAL_DIR)/timer/mt_gpt_v4.c \
+ $(LOCAL_DIR)/emi/emi_mpu_v1.c \
+ $(LOCAL_DIR)/i2c/mtk_i2c.c
+
+# GCE
+MODULE_SRCS += $(LOCAL_DIR)/gce/mtk_gce.c
+
+ifeq ("$(PMIC)","MT6389")
+MODULE_SRCS += \
+ $(LOCAL_DIR)/pmic/$(PMIC)/pmic.c \
+ $(LOCAL_DIR)/pmic/$(PMIC)/pmic_initial_setting.c \
+ $(LOCAL_DIR)/pmic/$(PMIC)/mtk_regulator_core.c \
+ $(LOCAL_DIR)/pmic/$(PMIC)/mt6389.c \
+ $(LOCAL_DIR)/clkbuf/clkbuf_ctl.c \
+
+endif
+
+MODULE_DEPS += \
+ lib/bio \
+ lib/cksum \
+ lib/fdt \
+ lib/mempool \
+ lib/partition \
+
+ifeq ($(LK_AS_BL33),0)
+MODULE_SRCS += \
+ $(LOCAL_DIR)/bgr/bgr.c
+
+MODULE_DEPS += \
+ $(LOCAL_DIR)/../../../../dramk_2731
+endif
+
+MODULE_SRCS += \
+ $(LOCAL_DIR)/vefuse/vefuse.c
+
+ifeq ($(ARCH),arm64)
+MODULE_EXTRA_OBJS += $(LOCAL_DIR)/../../../../lk_ext_mod/platform/mt2731/drivers/efuse/arm64/libefuse.o
+endif
+ifeq ($(ARCH),arm)
+MODULE_EXTRA_OBJS += $(LOCAL_DIR)/../../../../lk_ext_mod/platform/mt2731/drivers/efuse/arm/libefuse.o
+endif
+
+ifeq ($(strip $(ENABLE_MODEM_LOAD)),1)
+MODULES += \
+ $(LOCAL_DIR)/md
+endif
+
+ifeq ($(strip $(HSM_OS_SUPPORT)),yes)
+MODULES += \
+ $(LOCAL_DIR)/hsm
+GLOBAL_DEFINES += ENABLE_HSM_CLK
+endif
+
+include make/module.mk
+include $(LOCAL_DIR)/audio/rules.mk
diff --git a/src/bsp/lk/platform/mt2731/drivers/spm/spm_mtcmos.c b/src/bsp/lk/platform/mt2731/drivers/spm/spm_mtcmos.c
new file mode 100644
index 0000000..40e10fb
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/spm/spm_mtcmos.c
@@ -0,0 +1,137 @@
+#include <platform/pll.h>
+#include <platform/spm.h>
+#include <platform/spm_mtcmos.h>
+#include <platform/spm_mtcmos_internal.h>
+
+#define udelay(x) spin(x)
+
+/**************************************
+ * for NON-CPU MTCMOS
+ **************************************/
+/* Define MTCMOS Power Status Mask */
+#define MD1_PWR_STA_MASK (0x1 << 0)
+
+/* Define MTCMOS Bus Protect Mask */
+#define MD1_PROT_STEP1_0_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP1_0_ACK_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP2_0_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+#define MD1_PROT_STEP2_0_ACK_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+int spm_mtcmos_ctrl_md1(int state)
+{
+ int err = 0;
+
+ /* TINFO="enable SPM register control" */
+ spm_write(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | (0x1 << 0));
+
+ if (state == STA_POWER_DOWN) {
+ /* TINFO="Start to turn off MD1" */
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Set bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP1_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) & MD1_PROT_STEP1_0_ACK_MASK) != MD1_PROT_STEP1_0_ACK_MASK) {
+ }
+#endif
+ /* TINFO="Set bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP2_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) & MD1_PROT_STEP2_0_ACK_MASK) != MD1_PROT_STEP2_0_ACK_MASK) {
+ }
+#endif
+ /* TINFO="MD_EXTRA_PWR_CON[0]=1"*/
+ spm_write(MD_EXTRA_PWR_CON, spm_read(MD_EXTRA_PWR_CON) | (0x1 << 0));
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+ /* TINFO="Set PWR_ISO = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ISO);
+ /* TINFO="MD_SRAM_ISO_CON[0]=0"*/
+ spm_write(MD1_SRAM_ISOINT_B, spm_read(MD1_SRAM_ISOINT_B) & ~(0x1 << 0));
+ /* TINFO="Set SRAM_PDN = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | (0x1 << 8));
+#ifndef IGNORE_MTCMOS_CHECK
+#endif
+ /* TINFO="Set PWR_ON = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ /* TINFO="Wait until MD1_PWR_STA_MASK = 0" */
+ while (spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) {
+ /* No logic between pwr_on and pwr_ack. Print SRAM / MTCMOS control and PWR_ACK for debug. */
+ }
+#endif
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 3));
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Finish to turn off MD1" */
+ } else { /* STA_POWER_ON */
+ /* TINFO="Start to turn on MD1" */
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Set PWR_ON = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ /* TINFO="Wait until PWR_STATUS = 1 and PWR_STATUS_2ND = 1" */
+ while (((spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) != MD1_PWR_STA_MASK)
+ || ((spm_read(PWR_STATUS_2ND) & MD1_PWR_STA_MASK) != MD1_PWR_STA_MASK)) {
+ /* No logic between pwr_on and pwr_ack. Print SRAM / MTCMOS control and PWR_ACK for debug. */
+ }
+#endif
+ /* TINFO="Set SRAM_PDN = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~(0x1 << 8));
+ /* TINFO="MD_SRAM_ISO_CON[0]=1"*/
+ spm_write(MD1_SRAM_ISOINT_B, spm_read(MD1_SRAM_ISOINT_B) | (0x1 << 0));
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ while ((spm_read(MD1_PWR_CON) & PWR_CLK_DIS) == PWR_CLK_DIS);
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+
+ /* TINFO="Set PWR_ISO = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ISO);
+
+ /* TINFO="Set PWR_RST_B = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B);
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ /* TINFO="Set PWR_RST_B = 1" */
+ /* spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B); */
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON, spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 3));
+ /* TINFO="MD_EXTRA_PWR_CON[0]=0"*/
+ spm_write(MD_EXTRA_PWR_CON, spm_read(MD_EXTRA_PWR_CON) & ~(0x1 << 0));
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Release bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP2_0_MASK);
+ /* TINFO="Release bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP1_0_MASK);
+ /* TINFO="Finish to turn on MD1" */
+
+ /* From DE, the 93MD need a delay after power-on...*/
+ udelay(250);
+ }
+ return err;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/timer/mt_gpt_v4.c b/src/bsp/lk/platform/mt2731/drivers/timer/mt_gpt_v4.c
new file mode 100644
index 0000000..6dd945f
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/timer/mt_gpt_v4.c
@@ -0,0 +1,385 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2018. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*/
+
+#include <sys/types.h>
+#include <debug.h>
+#include <err.h>
+#include <reg.h>
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_irq.h>
+#include <platform/mt_gpt_v4.h>
+//#include <mt_gic.h>
+//#include <mt_gpt_common.h>
+
+typedef volatile unsigned int* P_U32;
+
+#define GPT4_CON ((P_U32)(APXGPT_BASE+0x0040))
+#define GPT4_CLK ((P_U32)(APXGPT_BASE+0x0044))
+#define GPT4_DAT ((P_U32)(APXGPT_BASE+0x0048))
+
+#define GPT4_EN 0x0001
+#define GPT4_FREERUN 0x0030
+#define GPT4_SYS_CLK 0x0000
+
+#define GPT4_MAX_TICK_CNT ((U32)0xFFFFFFFF)
+
+// 13MHz setting
+#define GPT4_MAX_US_TIMEOUT ((U32)330382100) // 0xFFFFFFFF /13d
+#define GPT4_MAX_MS_TIMEOUT ((U32)330382) // 0xFFFFFFFF /13000d
+
+#define GPT4_1US_TICK ((U32)13) // 1000 / 76.92ns = 13.000
+#define GPT4_1MS_TICK ((U32)13000) // 1000000 / 76.92ns = 13000.520
+// 13MHz: 1us = 13.000 ticks
+#define TIME_TO_TICK_US(us) ((us)*GPT4_1US_TICK + ((us)*0 + (1000-1))/1000)
+// 13MHz: 1ms = 13000.520 ticks
+#define TIME_TO_TICK_MS(ms) ((ms)*GPT4_1MS_TICK + ((ms)*520 + (1000-1))/1000)
+
+#define MS_TO_US 1000
+#define CFG_HZ 100
+#define MAX_REG_MS GPT4_MAX_MS_TIMEOUT
+
+#define GPT_SET_BITS(BS,REG) ((*(volatile U32*)(REG)) |= (U32)(BS))
+#define GPT_CLR_BITS(BS,REG) ((*(volatile U32*)(REG)) &= ~((U32)(BS)))
+
+static volatile U32 timestamp;
+static volatile U32 lastinc;
+
+//extern BOOT_ARGUMENT *g_boot_arg;
+
+//===========================================================================
+// GPT4 fixed 13MHz counter
+//===========================================================================
+static void gpt4_start (void)
+{
+ *GPT4_CLK = (GPT4_SYS_CLK);
+ *GPT4_CON = (GPT4_EN|GPT4_FREERUN);
+}
+
+static void gpt4_stop (void)
+{
+ *GPT4_CON = 0x0; // disable
+ *GPT4_CON = 0x2; // clear counter
+}
+
+static void gpt4_init (bool bStart)
+{
+ // power on GPT
+ //gpt_power_on (TRUE);
+
+ // clear GPT4 first
+ gpt4_stop ();
+
+ // enable GPT4 without lock
+ if (bStart) {
+ gpt4_start ();
+ }
+}
+
+U32 gpt4_get_current_tick (void)
+{
+ U32 cnt1, cnt2, cnt3,value1;
+
+ cnt1 = (*GPT4_DAT);
+ cnt2 = (*GPT4_DAT);
+ cnt3 = (*GPT4_DAT);
+ if (cnt2 < cnt1) {
+ if (cnt1 < cnt3)
+ value1 = cnt1;
+ else {
+ value1 = ((cnt2 > cnt3) ? cnt2 :cnt3);
+ }
+ } else {
+ if (cnt2 < cnt3)
+ value1 = cnt2;
+ else {
+ value1= ((cnt1 > cnt3) ? cnt1 :cnt3);
+ }
+ }
+ return value1;
+ //return (*GPT4_DAT);
+}
+
+bool gpt4_timeout_tick (U32 start_tick, U32 timeout_tick)
+{
+ register U32 cur_tick;
+ register U32 elapse_tick;
+
+ // get current tick
+ cur_tick = gpt4_get_current_tick ();
+
+ // check elapse time
+ if (start_tick <= cur_tick) {
+ elapse_tick = cur_tick - start_tick;
+ } else {
+ elapse_tick = (GPT4_MAX_TICK_CNT - start_tick) + cur_tick;
+ }
+
+ // check if timeout
+ if (timeout_tick <= elapse_tick) {
+ // timeout
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+//===========================================================================
+// us interface
+//===========================================================================
+U32 gpt4_tick2time_us (U32 tick)
+{
+ return ((tick + (GPT4_1US_TICK - 1)) / GPT4_1US_TICK);
+}
+
+U32 gpt4_time2tick_us (U32 time_us)
+{
+ if (GPT4_MAX_US_TIMEOUT <= time_us) {
+ return GPT4_MAX_US_TIMEOUT;
+ } else {
+ return TIME_TO_TICK_US (time_us);
+ }
+}
+
+//===========================================================================
+// ms interface
+//===========================================================================
+U32 gpt4_tick2time_ms (U32 tick)
+{
+ return ((tick + (GPT4_1MS_TICK - 1)) / GPT4_1MS_TICK);
+}
+
+U32 global_tick2time_ms (void)
+{
+ volatile U32 now;
+#if 0
+ if (g_boot_arg->boot_mode == DOWNLOAD_BOOT) {
+ register U32 cur_tick;
+ // get current tick from APXGPT because DOWNLOAD_BOOT do not ATF init
+ cur_tick = gpt4_get_current_tick ();
+ now = gpt4_tick2time_ms (cur_tick);
+ } else {
+#endif
+ register U64 cur_tick;
+ // get current tick from ARM generic timer which is enabled on ATF before LK for boottime measure
+ cur_tick = arch_counter_get_cntpct();
+ now = ((cur_tick & CNTPCT_BIT_MASK_L) + (CNTPCT_1MS_TICK - 1)) / CNTPCT_1MS_TICK;
+// }
+ return now;
+}
+
+U32 gpt4_time2tick_ms (U32 time_ms)
+{
+ if (GPT4_MAX_MS_TIMEOUT <= time_ms) {
+ return GPT4_MAX_MS_TIMEOUT;
+ } else {
+ return TIME_TO_TICK_MS (time_ms);
+ }
+}
+
+//===========================================================================
+// bust wait
+//===========================================================================
+void gpt_busy_wait_us (U32 timeout_us)
+{
+ U32 start_tick, timeout_tick;
+
+ // get timeout tick
+ timeout_tick = gpt4_time2tick_us (timeout_us);
+ start_tick = gpt4_get_current_tick ();
+
+ // wait for timeout
+ while (!gpt4_timeout_tick (start_tick, timeout_tick));
+}
+
+void gpt_busy_wait_ms (U32 timeout_ms)
+{
+ U32 start_tick, timeout_tick;
+
+ // get timeout tick
+ timeout_tick = gpt4_time2tick_ms (timeout_ms);
+ start_tick = gpt4_get_current_tick ();
+
+ // wait for timeout
+ while (!gpt4_timeout_tick (start_tick, timeout_tick));
+}
+
+//======================================================================
+
+
+void reset_timer_masked (void)
+{
+ lastinc = global_tick2time_ms();
+ timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+ volatile U32 now;
+
+ now = global_tick2time_ms();
+
+ if (now >= lastinc) {
+ timestamp = timestamp + now - lastinc; /* normal */
+ } else {
+ timestamp = timestamp + MAX_REG_MS - lastinc + now; /* overflow */
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+#define MAX_TIMESTAMP_MS 0xffffffff
+
+ulong get_timer (ulong base)
+{
+ ulong current_timestamp = 0;
+ ulong temp = 0;
+
+ current_timestamp = get_timer_masked ();
+
+ if (current_timestamp >= base) {
+ /* timestamp normal */
+ return (current_timestamp - base);
+ }
+ /* timestamp overflow */
+ //dbg_print("return = 0x%x\n",MAX_TIMESTAMP_MS - ( base - current_timestamp ));
+ temp = base - current_timestamp;
+
+ return (MAX_TIMESTAMP_MS - temp);
+}
+
+void set_timer (ulong ticks)
+{
+ timestamp = ticks;
+}
+
+/* delay msec mseconds */
+//void mdelay (unsigned long msec)
+//{
+// gpt_busy_wait_ms(msec);
+//}
+
+/* delay usec useconds */
+//void udelay (unsigned long usec)
+//{
+// gpt_busy_wait_us(usec);
+//}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return (unsigned long long) get_timer (0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+void mtk_timer_init (void)
+{
+ gpt4_init (TRUE);
+ // init timer system
+ reset_timer ();
+}
+
+/*********************************************************************************************
+ * This following is used to wake up system for battery charge in u-boot.
+ * Note, the maximux "ms" value of function "gpt_one_shot_irq" is 131071
+ *********************************************************************************************/
+#define GPT6_CON (APXGPT_BASE+0x0060)
+#define GPT6_CLK (APXGPT_BASE+0x0064)
+#define GPT6_CMP_L (APXGPT_BASE+0x006C)
+#define GPT6_CMP_H (APXGPT_BASE+0x007C)
+#define GPT_IRQ_EN (APXGPT_BASE+0x0000)
+#define GPT_IRQ_ACK (APXGPT_BASE+0x0008)
+
+#define GPT6_ONE_SHOT_EN 0x0001
+#define GPT6_RTC_CLK 0x0010
+#define GPT6_IRQ_BIT (1<<5)
+#define GPT6_STOP_CLEAR (1<<1)
+void gpt_one_shot_irq(unsigned int ms)
+{
+ // Using GPT6 as trigger source
+
+ // 1. Stop and clear GPT
+ DRV_WriteReg32(GPT6_CON, GPT6_STOP_CLEAR);
+
+ // 2. Clear pending irq
+ DRV_WriteReg32(GPT_IRQ_ACK, GPT6_IRQ_BIT);
+
+ // 3. Configure GPT divider to 1 and using 32K clock source
+ DRV_WriteReg32(GPT6_CLK, GPT6_RTC_CLK);
+
+ // 4. Calculate and Set compare value
+ DRV_WriteReg32(GPT6_CMP_L, 32768*ms/1000);
+
+ // 5. Enabel IRQ En
+ DRV_SetReg32(GPT_IRQ_EN, GPT6_IRQ_BIT);
+
+ // 6. Start GPT one-shot
+ DRV_WriteReg32(GPT6_CON, GPT6_ONE_SHOT_EN);
+}
+
+int gpt_irq_init(void)
+{
+ //1. Disable all gpt irq bits
+ DRV_WriteReg32(GPT_IRQ_EN, 0);
+
+ //2. Ack all gpt irq if needed
+ DRV_WriteReg32(GPT_IRQ_ACK, 0x3F);
+
+ //3. Register gpt irq for GIC
+ mt_irq_set_sens(MT_GPT_IRQ_ID, LEVEL_SENSITIVE);
+ mt_irq_set_polarity(MT_GPT_IRQ_ID, MT65xx_POLARITY_LOW);
+
+ return 0;
+}
+
+void gpt_irq_ack(void)
+{
+ DRV_WriteReg32(GPT_IRQ_ACK, GPT6_IRQ_BIT);
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/trng/mtk_trng.c b/src/bsp/lk/platform/mt2731/drivers/trng/mtk_trng.c
new file mode 100644
index 0000000..fac63ae
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/trng/mtk_trng.c
@@ -0,0 +1,61 @@
+#include <debug.h>
+#include <reg.h>
+#include <platform/mt_reg_base.h>
+#include <platform/pll.h>
+#include <string.h>
+
+#define TRNG_CTRL_REG (TRNG_BASE+0x00)
+#define TRNG_DATA_REG (TRNG_BASE+0x08)
+#define TRNG_CONF_REG (TRNG_BASE+0x0C)
+
+/* TRNG_CTRL_REG */
+#define TRNG_RDY (0x80000000)
+#define TRNG_START (0x00000001)
+
+#define TRNG_PDN_VALUE (0x200)
+
+/* Assume clock setting for trng is on */
+s32 trng_drv_get_random_data(u8 *buf, u32 len)
+{
+ s32 retval = 0;
+
+ if (0 == len)
+ return 0;
+
+ if (NULL == buf) {
+ dprintf(CRITICAL, "[TRNG] Error: input buffer is NULL\n");
+ return -1;
+ }
+
+ /* ungate */
+ writel(TRNG_PDN_VALUE, TRNG_PDN_CLR);
+
+ if (TRNG_START != (readl(TRNG_CTRL_REG) & TRNG_START)) {
+ writel(TRNG_START, TRNG_CTRL_REG);
+ if (TRNG_START != (readl(TRNG_CTRL_REG) & TRNG_START)) {
+ dprintf(CRITICAL, "[TRNG] Error: fail to start TRNG because clock is disabled\n");
+ return -2;
+ }
+ }
+
+ /* clear output buffer */
+ memset(buf, 0, len);
+
+ /* generate random data with default rings */
+ while (len >= sizeof(u32)) {
+ if(TRNG_RDY != (readl(TRNG_CTRL_REG) & TRNG_RDY)) {
+ spin(1);
+ continue;
+ }
+
+ *(u32 *)buf = readl(TRNG_DATA_REG);
+ retval += sizeof(u32);
+ buf += sizeof(u32);
+ len -= sizeof(u32);
+ }
+
+ /* gate */
+ writel(TRNG_PDN_VALUE, TRNG_PDN_SET);
+
+ return retval;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/uart/uart.c b/src/bsp/lk/platform/mt2731/drivers/uart/uart.c
new file mode 100644
index 0000000..4f9df66
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/uart/uart.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <debug.h>
+#include <reg.h>
+#include <dev/uart.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_uart.h>
+#include <string.h>
+
+typedef enum {
+ UART1 = UART1_BASE,
+ UART2 = UART2_BASE,
+ UART3 = UART3_BASE,
+ UART4 = UART4_BASE
+} MTK_UART;
+
+/* FCR */
+#define UART_FCR_FIFOE (1 << 0)
+#define UART_FCR_CLRR (1 << 1)
+#define UART_FCR_CLRT (1 << 2)
+#define UART_FCR_DMA1 (1 << 3)
+#define UART_FCR_RXFIFO_1B_TRI (0 << 6)
+#define UART_FCR_RXFIFO_6B_TRI (1 << 6)
+#define UART_FCR_RXFIFO_12B_TRI (2 << 6)
+#define UART_FCR_RXFIFO_RX_TRI (3 << 6)
+#define UART_FCR_TXFIFO_1B_TRI (0 << 4)
+#define UART_FCR_TXFIFO_4B_TRI (1 << 4)
+#define UART_FCR_TXFIFO_8B_TRI (2 << 4)
+#define UART_FCR_TXFIFO_14B_TRI (3 << 4)
+
+#define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
+#define UART_FCR_NORMAL (UART_FCR_FIFO_INIT | \
+ UART_FCR_TXFIFO_4B_TRI| \
+ UART_FCR_RXFIFO_12B_TRI)
+
+/* LCR */
+#define UART_LCR_BREAK (1 << 6)
+#define UART_LCR_DLAB (1 << 7)
+
+#define UART_WLS_5 (0 << 0)
+#define UART_WLS_6 (1 << 0)
+#define UART_WLS_7 (2 << 0)
+#define UART_WLS_8 (3 << 0)
+#define UART_WLS_MASK (3 << 0)
+
+#define UART_1_STOP (0 << 2)
+#define UART_2_STOP (1 << 2)
+#define UART_1_5_STOP (1 << 2) /* Only when WLS=5 */
+#define UART_STOP_MASK (1 << 2)
+
+#define UART_NONE_PARITY (0 << 3)
+#define UART_ODD_PARITY (0x1 << 3)
+#define UART_EVEN_PARITY (0x3 << 3)
+#define UART_MARK_PARITY (0x5 << 3)
+#define UART_SPACE_PARITY (0x7 << 3)
+#define UART_PARITY_MASK (0x7 << 3)
+
+/* MCR */
+#define UART_MCR_DTR (1 << 0)
+#define UART_MCR_RTS (1 << 1)
+#define UART_MCR_OUT1 (1 << 2)
+#define UART_MCR_OUT2 (1 << 3)
+#define UART_MCR_LOOP (1 << 4)
+#define UART_MCR_XOFF (1 << 7) /* read only */
+#define UART_MCR_NORMAL (UART_MCR_DTR|UART_MCR_RTS)
+
+/* LSR */
+#define UART_LSR_DR (1 << 0)
+#define UART_LSR_OE (1 << 1)
+#define UART_LSR_PE (1 << 2)
+#define UART_LSR_FE (1 << 3)
+#define UART_LSR_BI (1 << 4)
+#define UART_LSR_THRE (1 << 5)
+#define UART_LSR_TEMT (1 << 6)
+#define UART_LSR_FIFOERR (1 << 7)
+
+/* MSR */
+#define UART_MSR_DCTS (1 << 0)
+#define UART_MSR_DDSR (1 << 1)
+#define UART_MSR_TERI (1 << 2)
+#define UART_MSR_DDCD (1 << 3)
+#define UART_MSR_CTS (1 << 4)
+#define UART_MSR_DSR (1 << 5)
+#define UART_MSR_RI (1 << 6)
+#define UART_MSR_DCD (1 << 7)
+
+#define CONFIG_BAUDRATE 921600
+
+#define UART_BASE(uart) (uart)
+
+#define UART_RBR(uart) (UART_BASE(uart)+0x0) /* Read only */
+#define UART_THR(uart) (UART_BASE(uart)+0x0) /* Write only */
+#define UART_IER(uart) (UART_BASE(uart)+0x4)
+#define UART_IIR(uart) (UART_BASE(uart)+0x8) /* Read only */
+#define UART_FCR(uart) (UART_BASE(uart)+0x8) /* Write only */
+#define UART_LCR(uart) (UART_BASE(uart)+0xc)
+#define UART_MCR(uart) (UART_BASE(uart)+0x10)
+#define UART_LSR(uart) (UART_BASE(uart)+0x14)
+#define UART_MSR(uart) (UART_BASE(uart)+0x18)
+#define UART_SCR(uart) (UART_BASE(uart)+0x1c)
+#define UART_DLL(uart) (UART_BASE(uart)+0x0) /* Only when LCR.DLAB = 1 */
+#define UART_DLH(uart) (UART_BASE(uart)+0x4) /* Only when LCR.DLAB = 1 */
+#define UART_EFR(uart) (UART_BASE(uart)+0x8) /* Only when LCR = 0xbf */
+#define UART_XON1(uart) (UART_BASE(uart)+0x10) /* Only when LCR = 0xbf */
+#define UART_XON2(uart) (UART_BASE(uart)+0x14) /* Only when LCR = 0xbf */
+#define UART_XOFF1(uart) (UART_BASE(uart)+0x18) /* Only when LCR = 0xbf */
+#define UART_XOFF2(uart) (UART_BASE(uart)+0x1c) /* Only when LCR = 0xbf */
+#define UART_AUTOBAUD_EN(uart) (UART_BASE(uart)+0x20)
+#define UART_HIGHSPEED(uart) (UART_BASE(uart)+0x24)
+#define UART_SAMPLE_COUNT(uart) (UART_BASE(uart)+0x28)
+#define UART_SAMPLE_POINT(uart) (UART_BASE(uart)+0x2c)
+#define UART_AUTOBAUD_REG(uart) (UART_BASE(uart)+0x30)
+#define UART_RATE_FIX_AD(uart) (UART_BASE(uart)+0x34)
+#define UART_AUTOBAUD_SAMPLE(uart) (UART_BASE(uart)+0x38)
+#define UART_GUARD(uart) (UART_BASE(uart)+0x3c)
+#define UART_ESCAPE_DAT(uart) (UART_BASE(uart)+0x40)
+#define UART_ESCAPE_EN(uart) (UART_BASE(uart)+0x44)
+#define UART_SLEEP_EN(uart) (UART_BASE(uart)+0x48)
+#define UART_VFIFO_EN(uart) (UART_BASE(uart)+0x4c)
+#define UART_RXTRI_AD(uart) (UART_BASE(uart)+0x50)
+
+// output uart port
+volatile addr_t g_uart;
+
+//extern unsigned int mtk_get_bus_freq(void);
+#if CFG_FPGA_PLATFORM
+ #define UART_SRC_CLK 10000000
+#else
+ #define UART_SRC_CLK 26000000
+#endif
+
+static void uart_setbrg(void)
+{
+ unsigned int byte,speed;
+ unsigned int highspeed;
+ unsigned int quot, divisor, remainder;
+ unsigned int uartclk;
+ unsigned short data, high_speed_div, sample_count, sample_point;
+ unsigned int tmp_div;
+
+ speed = CONFIG_BAUDRATE;
+ uartclk = UART_SRC_CLK;
+ //uartclk = (unsigned int)(mtk_get_bus_freq()*1000/4);
+ if (speed <= 115200 ) {
+ highspeed = 0;
+ quot = 16;
+ } else {
+ highspeed = 3;
+ quot = 1;
+ }
+
+ if (highspeed < 3) { /*0~2*/
+ /* Set divisor DLL and DLH */
+ divisor = uartclk / (quot * speed);
+ remainder = uartclk % (quot * speed);
+
+ if (remainder >= (quot / 2) * speed)
+ divisor += 1;
+
+ writel(highspeed, UART_HIGHSPEED(g_uart));
+ byte = readl(UART_LCR(g_uart)); /* DLAB start */
+ writel((byte | UART_LCR_DLAB), UART_LCR(g_uart));
+ writel((divisor & 0x00ff), UART_DLL(g_uart));
+ writel(((divisor >> 8)&0x00ff), UART_DLH(g_uart));
+ writel(byte, UART_LCR(g_uart)); /* DLAB end */
+ } else {
+ data=(unsigned short)(uartclk/speed);
+ high_speed_div = (data>>8) + 1; // divided by 256
+
+ tmp_div=uartclk/(speed*high_speed_div);
+ divisor = (unsigned short)tmp_div;
+
+ remainder = (uartclk)%(high_speed_div*speed);
+ /*get (sample_count+1)*/
+ if (remainder >= ((speed)*(high_speed_div))>>1)
+ divisor = (unsigned short)(tmp_div+1);
+ else
+ divisor = (unsigned short)tmp_div;
+
+ sample_count=divisor-1;
+
+ /*get the sample point*/
+ sample_point=(sample_count-1)>>1;
+
+ /*configure register*/
+ writel(highspeed, UART_HIGHSPEED(g_uart));
+
+ byte = readl(UART_LCR(g_uart)); /* DLAB start */
+ writel((byte | UART_LCR_DLAB), UART_LCR(g_uart));
+ writel((high_speed_div & 0x00ff), UART_DLL(g_uart));
+ writel(((high_speed_div >> 8)&0x00ff), UART_DLH(g_uart));
+ writel(sample_count, UART_SAMPLE_COUNT(g_uart));
+ writel(sample_point, UART_SAMPLE_POINT(g_uart));
+ writel(byte, UART_LCR(g_uart)); /* DLAB end */
+ }
+}
+
+static void mtk_set_current_uart(MTK_UART uart_base)
+{
+ g_uart = uart_base;
+}
+
+void uart_init_early(void)
+{
+ mtk_set_current_uart(UART1);
+ /* clear fifo */
+ writel(readl(UART_FCR(g_uart)) + UART_FCR_FIFO_INIT, UART_FCR(g_uart));
+ writel(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
+ uart_setbrg();
+}
+
+void uart_init(void)
+{
+}
+
+int uart_putc(int port, char c)
+{
+ while (!(readl(UART_LSR(g_uart)) & UART_LSR_THRE));
+
+ if (c == '\n')
+ writel((unsigned int)'\r', UART_THR(g_uart));
+
+ writel((unsigned int)c, UART_THR(g_uart));
+
+ return 0;
+}
+
+int uart_getc(int port, bool wait)
+{
+ do {
+ if (readl(UART_LSR(g_uart)) & UART_LSR_DR)
+ return (int)(readl(UART_RBR(g_uart)) & 0xFF);
+ } while (wait);
+
+ return -1; /* no data available */
+}
+
+int uart_pputc(int port, char c)
+{
+ return uart_putc(port, c);
+}
+
+int uart_pgetc(int port)
+{
+ return uart_getc(port, 0);
+}
+
+bool check_uart_enter(void)
+{
+ if ((int)readl(UART_RBR(g_uart)) == 13)
+ return true;
+ else
+ return false;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/vefuse/vefuse.c b/src/bsp/lk/platform/mt2731/drivers/vefuse/vefuse.c
new file mode 100644
index 0000000..f66951e
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/vefuse/vefuse.c
@@ -0,0 +1,488 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#if ARCH_ARM
+#include <arch/arm.h>
+#endif
+#if ARCH_ARM64
+#include <arch/arm64.h>
+#endif
+
+#include <endian.h>
+#include <malloc.h>
+#include <printf.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+#include <reg.h>
+
+#include <platform/pmic.h>
+
+#define ENABLE_LOG 0
+#define VEFUSE_LOG(args...) do { \
+ if(ENABLE_LOG) \
+ { \
+ { dprintf(CRITICAL, "[VEFUSE]"args); } \
+ } \
+} while (0)
+
+//For MT6356 PMIC
+// VCN18=efuse1; VCAMIO=efuse2
+// For MT6389 PMIC
+// VGP1=efuse1; VGP2=efuse2
+
+
+#if defined(PMIC_CHIP_MT6356)
+
+#define efuse1_VOSEL_ADDR PMIC_RG_VCN18_VOSEL_ADDR
+#define efuse1_VOSEL_MASK PMIC_RG_VCN18_VOSEL_MASK
+#define efuse1_VOSEL_SHIFT PMIC_RG_VCN18_VOSEL_SHIFT
+#define efuse1_VOCAL_ADDR PMIC_RG_VCN18_VOCAL_ADDR
+#define efuse1_VOCAL_MASK PMIC_RG_VCN18_VOCAL_MASK
+#define efuse1_VOCAL_SHIFT PMIC_RG_VCN18_VOCAL_SHIFT
+#define efuse1_VOTRIM_ADDR PMIC_RG_VCN18_VOTRIM_ADDR
+#define efuse1_VOTRIM_MASK PMIC_RG_VCN18_VOTRIM_MASK
+#define efuse1_VOTRIM_SHIFT PMIC_RG_VCN18_VOTRIM_SHIFT
+#define efuse1_EN_ADDR PMIC_RG_LDO_VCN18_EN_ADDR
+#define efuse1_EN_MASK PMIC_RG_LDO_VCN18_EN_MASK
+#define efuse1_EN_SHIFT PMIC_RG_LDO_VCN18_EN_SHIFT
+
+#define efuse2_VOSEL_ADDR PMIC_RG_VCAMIO_VOSEL_ADDR
+#define efuse2_VOSEL_MASK PMIC_RG_VCAMIO_VOSEL_MASK
+#define efuse2_VOSEL_SHIFT PMIC_RG_VCAMIO_VOSEL_SHIFT
+#define efuse2_VOCAL_ADDR PMIC_RG_VCAMIO_VOCAL_ADDR
+#define efuse2_VOCAL_MASK PMIC_RG_VCAMIO_VOCAL_MASK
+#define efuse2_VOCAL_SHIFT PMIC_RG_VCAMIO_VOCAL_SHIFT
+#define efuse2_VOTRIM_ADDR PMIC_RG_VCAMIO_VOTRIM_ADDR
+#define efuse2_VOTRIM_MASK PMIC_RG_VCAMIO_VOTRIM_MASK
+#define efuse2_VOTRIM_SHIFT PMIC_RG_VCAMIO_VOTRIM_SHIFT
+#define efuse2_EN_ADDR PMIC_RG_LDO_VCAMIO_EN_ADDR
+#define efuse2_EN_MASK PMIC_RG_LDO_VCAMIO_EN_MASK
+#define efuse2_EN_SHIFT PMIC_RG_LDO_VCAMIO_EN_SHIFT
+
+#elif defined(PMIC_CHIP_MT6389)
+
+#define efuse1_VOSEL_ADDR PMIC_RG_VGP1_VOSEL_ADDR
+#define efuse1_VOSEL_MASK PMIC_RG_VGP1_VOSEL_MASK
+#define efuse1_VOSEL_SHIFT PMIC_RG_VGP1_VOSEL_SHIFT
+#define efuse1_VOCAL_ADDR PMIC_RG_VGP1_VOCAL_ADDR
+#define efuse1_VOCAL_MASK PMIC_RG_VGP1_VOCAL_MASK
+#define efuse1_VOCAL_SHIFT PMIC_RG_VGP1_VOCAL_SHIFT
+#define efuse1_VOTRIM_ADDR PMIC_RG_VGP1_VOTRIM_ADDR
+#define efuse1_VOTRIM_MASK PMIC_RG_VGP1_VOTRIM_MASK
+#define efuse1_VOTRIM_SHIFT PMIC_RG_VGP1_VOTRIM_SHIFT
+#define efuse1_EN_ADDR PMIC_RG_LDO_VGP1_EN_ADDR
+#define efuse1_EN_MASK PMIC_RG_LDO_VGP1_EN_MASK
+#define efuse1_EN_SHIFT PMIC_RG_LDO_VGP1_EN_SHIFT
+
+#define efuse2_VOSEL_ADDR PMIC_RG_VGP2_VOSEL_ADDR
+#define efuse2_VOSEL_MASK PMIC_RG_VGP2_VOSEL_MASK
+#define efuse2_VOSEL_SHIFT PMIC_RG_VGP2_VOSEL_SHIFT
+#define efuse2_VOCAL_ADDR PMIC_RG_VGP2_VOCAL_ADDR
+#define efuse2_VOCAL_MASK PMIC_RG_VGP2_VOCAL_MASK
+#define efuse2_VOCAL_SHIFT PMIC_RG_VGP2_VOCAL_SHIFT
+#define efuse2_VOTRIM_ADDR PMIC_RG_VGP2_VOTRIM_ADDR
+#define efuse2_VOTRIM_MASK PMIC_RG_VGP2_VOTRIM_MASK
+#define efuse2_VOTRIM_SHIFT PMIC_RG_VGP2_VOTRIM_SHIFT
+#define efuse2_EN_ADDR PMIC_RG_LDO_VGP2_EN_ADDR
+#define efuse2_EN_MASK PMIC_RG_LDO_VGP2_EN_MASK
+#define efuse2_EN_SHIFT PMIC_RG_LDO_VGP2_EN_SHIFT
+
+#endif
+
+struct op_entry {
+ int mVol;
+ int VOSEL;
+ int VOCAL;
+ int VOTRIM;
+};
+
+#if defined(PMIC_CHIP_MT6356)
+
+//AP VEFUSE
+static struct op_entry op_tbl_vefuse[] = {
+ {171, 0xB, 1, 0}, //0
+ {172, 0xB, 2, 0}, //1
+ {173, 0xB, 3, 0}, //2
+ {174, 0xB, 4, 0}, //3
+ {175, 0xB, 5, 0}, //4
+ {176, 0xB, 6, 0}, //5
+ {177, 0xB, 7, 0}, //6
+ {178, 0xB, 8, 0}, //7
+ {179, 0xB, 9, 0}, //8
+ {180, 0xC, 0, 0}, //9
+ {181, 0xC, 1, 0},
+ {182, 0xC, 2, 0},
+ {183, 0xC, 3, 0},
+ {184, 0xC, 4, 0},
+ {185, 0xC, 5, 0},
+ {186, 0xC, 6, 0},
+ {187, 0xC, 7, 0},
+ {188, 0xC, 8, 0},
+ {189, 0xC, 9, 0}
+};
+
+#elif defined(PMIC_CHIP_MT6389)
+
+//AP VEFUSE
+static struct op_entry op_tbl_vefuse[] = {
+ {171, 0x3, 1, 0}, //0
+ {172, 0x3, 2, 0}, //1
+ {173, 0x3, 3, 0}, //2
+ {174, 0x3, 4, 0}, //3
+ {175, 0x3, 5, 0}, //4
+ {176, 0x3, 6, 0}, //5
+ {177, 0x3, 7, 0}, //6
+ {178, 0x3, 8, 0}, //7
+ {179, 0x3, 9, 0}, //8
+ {180, 0x4, 0, 0}, //9
+ {181, 0x4, 1, 0},
+ {182, 0x4, 2, 0},
+ {183, 0x4, 3, 0},
+ {184, 0x4, 4, 0},
+ {185, 0x4, 5, 0},
+ {186, 0x4, 6, 0},
+ {187, 0x4, 7, 0},
+ {188, 0x4, 8, 0},
+ {189, 0x4, 9, 0}
+};
+
+#endif
+
+//HSM VEFUSE
+static struct op_entry *op_tbl_vefuse1 = op_tbl_vefuse;
+
+//VCORE
+static struct op_entry op_tbl_vcore[] = {
+ {72, 0, 0, 0}, //0
+ {73, 0, 0, 0}, //1
+ {74, 0, 0, 0}, //2
+ {75, 0, 0, 0}, //3
+ {76, 0, 0, 0}, //4
+ {77, 0, 0, 0}, //5
+ {78, 0, 0, 0}, //6
+ {79, 0, 0, 0}, //7
+ {80, 0, 0, 0}, //8
+ {81, 0, 0, 0},
+ {82, 0, 0, 0},
+ {83, 0, 0, 0},
+ {84, 0, 0, 0},
+ {85, 0, 0, 0},
+ {86, 0, 0, 0},
+ {87, 0, 0, 0},
+ {88, 0, 0, 0}
+};
+
+static unsigned int cur_op_idx_vefuse = 9; //V1.8
+static unsigned int cur_op_idx_vefuse1 = 9; //V1.8
+static unsigned int cur_op_idx_vcore = 8; //V0.8
+
+static unsigned int base_op_idx_vefuse = 9; //V1.8
+static unsigned int base_op_idx_vefuse1 = 9; //V1.8
+
+//********************************
+// internal functions
+
+static int vefuse_startblow_ap(void)
+{
+ unsigned int ret_val = 0;
+
+ if( op_tbl_vefuse[cur_op_idx_vefuse].VOSEL == -1 ||
+ op_tbl_vefuse[cur_op_idx_vefuse].VOCAL == -1 ||
+ op_tbl_vefuse[cur_op_idx_vefuse].VOTRIM == -1) {
+ VEFUSE_LOG("VEFUSE mVol %d is not supported\n", op_tbl_vefuse[cur_op_idx_vefuse].mVol);
+ return -1;
+ }
+
+//PMIC 6356
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOSEL_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse].VOSEL),
+ (unsigned int)(efuse1_VOSEL_MASK),
+ (unsigned int)(efuse1_VOSEL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOCAL_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse].VOCAL),
+ (unsigned int)(efuse1_VOCAL_MASK),
+ (unsigned int)(efuse1_VOCAL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOTRIM_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse].VOTRIM),
+ (unsigned int)(efuse1_VOTRIM_MASK),
+ (unsigned int)(efuse1_VOTRIM_SHIFT)
+ );
+
+
+ /* enabled */
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_EN_ADDR),
+ (unsigned int)(1),
+ (unsigned int)(efuse1_EN_MASK),
+ (unsigned int)(efuse1_EN_SHIFT));
+
+ mdelay(10);
+
+ //by DE's request, VEFUSE is adjust to v1.8 first, and then adjust to other voltage
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOSEL_ADDR),
+ (unsigned int)(op_tbl_vefuse[cur_op_idx_vefuse].VOSEL),
+ (unsigned int)(efuse1_VOSEL_MASK),
+ (unsigned int)(efuse1_VOSEL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOCAL_ADDR),
+ (unsigned int)(op_tbl_vefuse[cur_op_idx_vefuse].VOCAL),
+ (unsigned int)(efuse1_VOCAL_MASK),
+ (unsigned int)(efuse1_VOCAL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_VOTRIM_ADDR),
+ (unsigned int)(op_tbl_vefuse[cur_op_idx_vefuse].VOTRIM),
+ (unsigned int)(efuse1_VOTRIM_MASK),
+ (unsigned int)(efuse1_VOTRIM_SHIFT)
+ );
+
+ mdelay(10);
+
+ return ret_val;
+}
+
+static int vefuse_startblow_hsm(void)
+{
+ unsigned int ret_val = 0;
+
+ if( op_tbl_vefuse1[cur_op_idx_vefuse1].VOSEL == -1 ||
+ op_tbl_vefuse1[cur_op_idx_vefuse1].VOCAL == -1 ||
+ op_tbl_vefuse1[cur_op_idx_vefuse1].VOTRIM == -1) {
+ VEFUSE_LOG("VEFUSE1 mVol %d is not supported\n", op_tbl_vefuse1[cur_op_idx_vefuse1].mVol);
+ return -1;
+ }
+
+//PMIC 6356
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOSEL_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse1].VOSEL),
+ (unsigned int)(efuse2_VOSEL_MASK),
+ (unsigned int)(efuse2_VOSEL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOCAL_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse1].VOCAL),
+ (unsigned int)(efuse2_VOCAL_MASK),
+ (unsigned int)(efuse2_VOCAL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOTRIM_ADDR),
+ (unsigned int)(op_tbl_vefuse[base_op_idx_vefuse1].VOTRIM),
+ (unsigned int)(efuse2_VOTRIM_MASK),
+ (unsigned int)(efuse2_VOTRIM_SHIFT)
+ );
+
+
+ /* enabled */
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_EN_ADDR),
+ (unsigned int)(1),
+ (unsigned int)(efuse2_EN_MASK),
+ (unsigned int)(efuse2_EN_SHIFT));
+
+ mdelay(10);
+
+ //by DE's request, VEFUSE is adjust to v1.8 first, and then adjust to other voltage
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOSEL_ADDR),
+ (unsigned int)(op_tbl_vefuse[cur_op_idx_vefuse1].VOSEL),
+ (unsigned int)(efuse2_VOSEL_MASK),
+ (unsigned int)(efuse2_VOSEL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOCAL_ADDR),
+ (unsigned int)(op_tbl_vefuse1[cur_op_idx_vefuse1].VOCAL),
+ (unsigned int)(efuse2_VOCAL_MASK),
+ (unsigned int)(efuse2_VOCAL_SHIFT)
+ );
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_VOTRIM_ADDR),
+ (unsigned int)(op_tbl_vefuse1[cur_op_idx_vefuse1].VOTRIM),
+ (unsigned int)(efuse2_VOTRIM_MASK),
+ (unsigned int)(efuse2_VOTRIM_SHIFT)
+ );
+
+ mdelay(10);
+
+ return ret_val;
+}
+
+static unsigned int vefuse_is_enabled(void) {
+ unsigned int regVal;
+
+ pmic_read_interface((unsigned int)(efuse1_VOSEL_ADDR),
+ ®Val,
+ (unsigned int)(efuse1_VOSEL_MASK),
+ (unsigned int)(efuse1_VOSEL_SHIFT)
+ );
+ VEFUSE_LOG("efuse1 VOSEL %x\n", regVal);
+
+ pmic_read_interface((unsigned int)(efuse1_VOCAL_ADDR),
+ ®Val,
+ (unsigned int)(efuse1_VOCAL_MASK),
+ (unsigned int)(efuse1_VOCAL_SHIFT)
+ );
+ VEFUSE_LOG("efuse1 VOCAL %x\n", regVal);
+
+ pmic_read_interface((unsigned int)(efuse1_VOTRIM_ADDR),
+ ®Val,
+ (unsigned int)(efuse1_VOTRIM_MASK),
+ (unsigned int)(efuse1_VOTRIM_SHIFT)
+ );
+ VEFUSE_LOG("efuse1 VOTRIM %x\n", regVal);
+
+ /* Check Fsource(VEFUSE or VMIPI) Status */
+ pmic_read_interface((unsigned int)(efuse1_EN_ADDR),
+ ®Val,
+ (unsigned int)(efuse1_EN_MASK),
+ (unsigned int)(efuse1_EN_SHIFT)
+ );
+
+ VEFUSE_LOG("efuse1 EN %x\n", regVal);
+
+ return regVal;
+}
+
+static int vefuse_startblow(void)
+{
+ unsigned int ret_val = 0;
+
+ ret_val |= vefuse_startblow_ap();
+ ret_val |= vefuse_startblow_hsm();
+
+ VEFUSE_LOG("vefuse_startblow: ret %d, enabled %d\n", ret_val, vefuse_is_enabled());
+ return ret_val;
+}
+
+static int vefuse_endblow(void)
+{
+ unsigned int ret_val = 0;
+
+//PMIC 6356
+ /* disable */
+ ret_val |= pmic_config_interface((unsigned int)(efuse1_EN_ADDR),
+ (unsigned int)(0),
+ (unsigned int)(efuse1_EN_MASK),
+ (unsigned int)(efuse1_EN_SHIFT));
+
+ ret_val |= pmic_config_interface((unsigned int)(efuse2_EN_ADDR),
+ (unsigned int)(0),
+ (unsigned int)(efuse2_EN_MASK),
+ (unsigned int)(efuse2_EN_SHIFT));
+
+ VEFUSE_LOG("vefuse_endblow: ret %d\n", ret_val);
+ return ret_val;
+}
+
+static int vcore_startblow(void)
+{
+ int ret = 0;
+
+ struct mtk_regulator reg_vcore;
+ //struct mtk_regulator reg_vsram_others;
+
+//TODO: check if vsram need to be adjust too
+#if 0
+ /* ---------- Control the vsram_others ---------- */
+ ret = mtk_regulator_get("vsram_others", ®_vsram_others);
+ if (ret)
+ FUSE_ERR("Err: vg1\n");
+
+ /*
+ * The function mtk_regulator_set_voltage selects the lowest matching vsram_others
+ * from the given min_uV to max_uV. It is suggested to set max to vsram_others_max_uV.
+ */
+ ret |= mtk_regulator_set_voltage(®_vsram_others, EFUSE_VSRAM_UVOL, vsram_others_max_uV);
+ if (ret)
+ FUSE_ERR("Err: vs1\n");
+
+ FUSE_INFO("vc1 %d, %d\n",
+ mtk_regulator_get_voltage(®_vsram_others), mtk_regulator_is_enabled(®_vsram_others));
+#endif
+
+ /* ---------- Control the vcore ---------- */
+ ret = mtk_regulator_get("vcore", ®_vcore);
+ if (ret)
+ VEFUSE_LOG("Err: vg2\n");
+
+ /*
+ * The function mtk_regulator_set_voltage selects the lowest matching VCORE
+ * from the given min_uV to max_uV. It is suggested to set max to vcore_max_uV.
+ */
+ ret |= mtk_regulator_set_voltage(®_vcore, op_tbl_vcore[cur_op_idx_vcore].mVol * 10000, vcore_max_uV);
+ if (ret)
+ VEFUSE_LOG("Err: vs2\n");
+
+ VEFUSE_LOG("vc2 %d, %d\n",
+ mtk_regulator_get_voltage(®_vcore), mtk_regulator_is_enabled(®_vcore));
+
+ /*
+ * VCORE and VSRAM are enabled by default.
+ * No need to enable VCORE and VSRAM again.
+ * The system cannot work with VCORE or VSRAM disabled.
+ */
+
+ mdelay(10);
+
+ return ret;
+}
+
+static int vcore_endblow(void)
+{
+ return 0;
+}
+
+//****************************************************************
+// fastboot interface functions
+
+void enable_vefuse(void)
+{
+ vefuse_startblow();
+ vcore_startblow();
+}
+
+void disable_vefuse(void)
+{
+ vcore_endblow();
+ vefuse_endblow();
+}
+
+void set_op_vefuse(unsigned int vefuse_op, unsigned int vcore_op)
+{
+ if (vefuse_op < ARRAY_SIZE(op_tbl_vefuse) && vcore_op < ARRAY_SIZE(op_tbl_vcore)) {
+ cur_op_idx_vefuse = cur_op_idx_vefuse1 = vefuse_op;
+ cur_op_idx_vcore = vcore_op;
+ } else {
+ VEFUSE_LOG("invalid value, vefuse_op %d, vcore_op %d\n", vefuse_op, vcore_op);
+ }
+
+ VEFUSE_LOG("For efuse writer: VEFUSE set to %dmV, VCORE set to %dmV\n", op_tbl_vefuse[cur_op_idx_vefuse].mVol, op_tbl_vcore[cur_op_idx_vcore].mVol);
+ VEFUSE_LOG("For efuse writer: VEFUSE1 set to %dmV\n", op_tbl_vefuse1[cur_op_idx_vefuse1].mVol);
+}
+
+void get_op_vefuse(int *vefuse, int *vcore) {
+ *vefuse = op_tbl_vefuse[cur_op_idx_vefuse].mVol;
+ *vcore = op_tbl_vcore[cur_op_idx_vcore].mVol;
+}
diff --git a/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_drm.c b/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_drm.c
new file mode 100644
index 0000000..77a1119
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_drm.c
@@ -0,0 +1,306 @@
+#include <platform/mtk_drm.h>
+#include <reg.h>
+#include <platform/mt_gpt_v4.h>
+
+#define udelay(x) gpt_busy_wait_us(x)
+#define mdelay(x) gpt_busy_wait_us(x*1000)
+
+static unsigned int mtk_drm_get_debug_ctl(void)
+{
+ static unsigned int drm_debug_ctl = 0;
+
+ /*
+ * Note:
+ * Because some bits in register DEBUG_CTL will be cleared after
+ * writing DRM_MODE, we use a static variable to keep original DEBUG_CTL.
+ *
+ * Effected Bits:
+ * 16: ddr_reserve_success
+ * 18: emi_dcs_success
+ * 20: dvfsrc_success
+ */
+ if (drm_debug_ctl == 0)
+ drm_debug_ctl = readl(MTK_DRM_DEBUG_CTL);
+
+ return drm_debug_ctl;
+}
+
+static void mtk_drm_keep_essential_info(void)
+{
+ mtk_drm_get_debug_ctl();
+}
+
+int drm_dram_reserved(int enable)
+{
+ volatile unsigned int tmp = 0, ret = 0;
+
+ /*
+ * DDR reserved mode may be switched on/off anytime by caller.
+ *
+ * DDR reserved mode switch on/off flow will modify register MODE.
+ * Since register STATUS and some bits in DEBUG_CTL will be reset
+ * if register MODE has any changes. Keep those register values first
+ * before register MODE is written later.
+ */
+ mtk_drm_keep_essential_info();
+
+ if (enable == 1) {
+ /* enable ddr reserved mode */
+ tmp = readl(MTK_DRM_MODE);
+ tmp |= (MTK_DRM_MODE_DDR_RESERVE|MTK_DRM_MODE_KEY);
+ writel(tmp, MTK_DRM_MODE);
+ } else if (enable == 0) {
+ /* disable ddr reserved mode, set reset mode,
+ disable watchdog output reset signal */
+ tmp = readl(MTK_DRM_MODE);
+ tmp &= (~MTK_DRM_MODE_DDR_RESERVE);
+ tmp |= MTK_DRM_MODE_KEY;
+ writel(tmp, MTK_DRM_MODE);
+ } else {
+ printf("Wrong input %d, should be 1(enable) or 0(disable) in %s\n", enable, __func__);
+ ret = -1;
+ }
+
+ printf("%s: MTK_DRM_MODE(%x)\n", __func__, tmp);
+ return ret;
+}
+
+int drm_is_reserve_ddr_enabled(void)
+{
+ unsigned int drm_mode;
+
+ drm_mode = readl(MTK_DRM_MODE);
+
+ if (drm_mode & 0x1)
+ return 1;
+ else
+ return 0;
+}
+
+int drm_is_dram_slf(void)
+{
+ unsigned int drm_dbg_ctrl;
+
+ drm_dbg_ctrl = readl(MTK_DRM_DEBUG_CTL);
+
+ if (drm_dbg_ctrl & MTK_DRM_DDR_SREF_STA) {
+ printf("DDR is in self-refresh. %x\n", drm_dbg_ctrl);
+ return 1;
+ } else {
+ printf("DDR is not in self-refresh. %x\n", drm_dbg_ctrl);
+ return 0;
+ }
+}
+
+int drm_wait_for_reg_update_done(unsigned int reg_addr, unsigned mask, unsigned target_val)
+{
+ unsigned timeout_ms = 5;
+ unsigned int read_val;
+ unsigned int read_times = 0;
+ unsigned int elapsed_ms = 0;
+
+ while (1) {
+ read_val = readl(reg_addr);
+
+ if (target_val == (read_val & mask))
+ break;
+
+ read_times++;
+
+ if (read_times && 0 == (read_times % 100)) {
+
+ mdelay(1);
+ elapsed_ms += 1;
+
+ if (elapsed_ms > timeout_ms) {
+ printf("%s: ERROR! Update reg 0x%x timeout! Mask: 0x%x Target: 0x%x\n",
+ __func__, reg_addr, mask, target_val);
+
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int drm_update_reg(unsigned int reg, unsigned int func, unsigned int bits)
+{
+ volatile unsigned int val;
+ int ret;
+
+ val = readl(reg);
+
+ if (func == DRM_REG_SET)
+ val |= bits;
+ else if (func == DRM_REG_CLR)
+ val &= (~bits);
+ else
+ return -1;
+
+ /* add unlock key */
+ if (reg == MTK_DRM_DEBUG_CTL)
+ val |= MTK_DRM_DEBUG_CTL_KEY;
+ else if (reg == MTK_DRM_DEBUG_CTL2)
+ val |= MTK_DRM_DEBUG_CTL2_KEY;
+ else {
+ printf("DRM: Invalid! Set bit 0x%x in reg 0x%x fail!\n", bits, reg);
+ return -1;
+ }
+
+ /* update register */
+ writel(val, reg);
+
+ /* wait until register updating done */
+ if (func == DRM_REG_SET)
+ val = bits;
+ else
+ val = 0;
+
+ /*
+ * Must ensure waiting-done API has timeout mechanism
+ * because in some scenarios with security feature toggled,
+ * below registers will be read-only. Writting operation
+ * will get timeout here.
+ *
+ * DEBUG_CTL / DEBUG_CLT2 / DDR_RESERVE_MODE bit in MODE
+ */
+ ret = drm_wait_for_reg_update_done(reg, bits, val);
+
+ printf("%s: %d, bits: 0x%x, addr: 0x%x, val: 0x%x\n", __func__,
+ func, bits, reg, readl(reg));
+
+ return ret;
+}
+
+int drm_is_reserve_ddr_mode_success(void)
+{
+ unsigned int drm_dbg_ctrl;
+
+ /*
+ * MTK_DRM_DDR_RESERVE_RTA bit will be reset by modifying register MODE.
+ * Read DEBUG_CTL value kept by mtk_drm_get_debug_ctl().
+ */
+ drm_dbg_ctrl = mtk_drm_get_debug_ctl();
+
+ if (drm_dbg_ctrl & MTK_DRM_DDR_RESERVE_STA) {
+ printf("DRM DDR reserve mode success! %x\n", drm_dbg_ctrl);
+ return 1;
+ } else {
+ printf("DRM DDR reserve mode FAIL! %x\n", drm_dbg_ctrl);
+ return 0;
+ }
+}
+
+int drm_release_rg_dramc_conf_iso(void)
+{
+ int ret;
+ int success;
+
+ ret = drm_update_reg(MTK_DRM_DEBUG_CTL,
+ DRM_REG_CLR, MTK_DRM_DRAMC_CONF_ISO);
+
+ success = drm_is_reserve_ddr_mode_success();
+
+ printf("DDR RESERVE Success %d\n", success);
+
+ return ret;
+}
+
+int drm_release_rg_dramc_iso(void)
+{
+ return drm_update_reg(MTK_DRM_DEBUG_CTL, DRM_REG_CLR, MTK_DRM_DRAMC_ISO);
+}
+
+int drm_release_rg_dramc_sref(void)
+{
+ return drm_update_reg(MTK_DRM_DEBUG_CTL, DRM_REG_CLR, MTK_DRM_DRAMC_SREF);
+}
+
+int drm_is_dvfsrc_success(void)
+{
+ unsigned int drm_dbg_ctrl;
+ unsigned int success;
+
+ drm_dbg_ctrl = mtk_drm_get_debug_ctl();
+ success = (drm_dbg_ctrl & MTK_DRM_DVFSRC_SUCCESS)? 1 : 0;
+
+ printf("DVFSRC_SUCCESS %d\n", success);
+
+ return success;
+}
+
+int drm_is_dvfsrc_enable(void)
+{
+ unsigned int reg;
+
+ reg = readl(MTK_DRM_DEBUG_CTL2);
+
+ if (reg & MTK_DRM_DVFSRC_EN)
+ return 1;
+ else
+ return 0;
+}
+
+void mtk_drm_init(void)
+{
+#if !LK_AS_BL33
+ unsigned int latch_ctrl;
+
+ /* Save DRM debug info */
+ printf("Save DRM_DEBUG_CTL(0x%x)\n", mtk_drm_get_debug_ctl());
+
+ /* Configure DRM_LATCH_CTL */
+ latch_ctrl = readl(MTK_DRM_LATCH_CTL);
+ latch_ctrl |= MTK_DRM_LATCH_CTL_KEY;
+ latch_ctrl |= MTK_DRM_LATCH_EN;
+ latch_ctrl |= MTK_DRM_MCU_LATCH_EN;
+ latch_ctrl |= MTK_DRM_SPM_LATCH_EN;
+ latch_ctrl |= MTK_DRM_GPU_EXT_OFF_EN;
+ latch_ctrl |= MTK_DRM_MD_EXT_OFF_EN;
+ latch_ctrl &= ~(MTK_DRM_MCU_LATCH_SELECT | MTK_DRM_SPM_LATCH_SELECT);
+ latch_ctrl |= MTK_DRM_DRAMC_LATCH_EN;
+ latch_ctrl |= MTK_DRM_DVFSRC_LATCH_EN;
+ latch_ctrl |= MTK_DRM_DEBUGSYS_LATCH_EN;
+ latch_ctrl |= (MTK_DRM_DRAMC_RD_TEST_EN | MTK_DRM_DRAMC_RDWT_TEST_EN);
+ writel(latch_ctrl, MTK_DRM_LATCH_CTL);
+
+ /* Configure DRM_LATCH_CTL2 */
+ latch_ctrl = readl(MTK_DRM_LATCH_CTL2);
+ latch_ctrl |= MTK_DRM_LATCH_CTL2_KEY;
+
+ /* DFD feature */
+ //latch_ctrl |= MTK_DRM_MCU_DFD_EN;
+ latch_ctrl &= ~(MTK_DRM_MCU_DFD_TIMEOUT_MASK << MTK_DRM_MCU_DFD_TIMEOUT_OFS);
+ latch_ctrl |= (MTK_DRM_MCU_DFD_TIMEOUT_VALUE << MTK_DRM_MCU_DFD_TIMEOUT_OFS);
+
+ writel(latch_ctrl, MTK_DRM_LATCH_CTL2);
+
+ /* Dump DRM control regs */
+ printf("DRM_LATCH_CTL : 0x%x\n", readl(MTK_DRM_LATCH_CTL));
+ printf("DRM_LATCH_CTL2: 0x%x\n", readl(MTK_DRM_LATCH_CTL2));
+
+ /*
+ * Configure DRM_DEBUG_CTL
+ *
+ * Release DDR reserve mode related control.
+ *
+ * NOTE: This job must be done earlier than DVS/DVFSRC initialization.
+ */
+ drm_update_reg(MTK_DRM_DEBUG_CTL, DRM_REG_CLR,
+ MTK_DRM_DVFSRC_PAUSE);
+
+ drm_update_reg(MTK_DRM_DEBUG_CTL2, DRM_REG_CLR,
+ MTK_DRM_DVFSRC_EN);
+
+ drm_update_reg(MTK_DRM_DEBUG_CTL, DRM_REG_CLR,
+ MTK_DRM_EMI_DCS_PAUSE);
+
+ drm_update_reg(MTK_DRM_DEBUG_CTL2, DRM_REG_CLR,
+ MTK_DRM_EMI_DCS_EN);
+
+ printf("MTK_DRM_DEBUG_CTL : 0x%x\n", readl(MTK_DRM_DEBUG_CTL));
+ printf("MTK_DRM_DEBUG_CTL2: 0x%x\n", readl(MTK_DRM_DEBUG_CTL2));
+#endif
+}
+
diff --git a/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_wdt.c b/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_wdt.c
new file mode 100644
index 0000000..21fec67
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/drivers/wdt/mtk_wdt.c
@@ -0,0 +1,382 @@
+#include <debug.h>
+#include <platform/mtk_wdt.h>
+#include <reg.h>
+#include <platform/upmu_hw.h>
+#include <platform/pmic.h>
+#include <boot_args.h>
+
+/* Use PMIC common API for PMIC full reset detection */
+#define CFG_APWDT_PMIC_FULL_RST_COMMON_API 1
+
+#if CFG_APWDT_PMIC_FULL_RST_COMMON_API
+#include <platform/pmic.h>
+
+#if LK_AS_BL33 == 1
+extern BOOT_ARGUMENT *g_boot_arg;
+#endif /* LK_AS_BL33 */
+
+#endif /* CFG_APWDT_PMIC_FULL_RST_COMMON_API */
+
+#if ENABLE_WDT_MODULE
+
+static bool mtk_wd_CheckNonResetReg2(unsigned int offset)
+{
+ u32 tmp;
+ tmp = readl(MTK_WDT_NONRST_REG2);
+ if (tmp & (1U << offset))
+ return true;
+ else
+ return false;
+}
+
+static void mtk_wd_SetNonResetReg2(unsigned int offset, bool value)
+{
+ u32 reg;
+
+ reg = readl(MTK_WDT_NONRST_REG2);
+ if (value)
+ reg |= (1U << offset);
+ else
+ reg &= ~(1U << offset);
+
+ writel(reg, MTK_WDT_NONRST_REG2);
+}
+
+int mtk_wdt_is_pmic_full_reset(void)
+{
+#if CFG_APWDT_PMIC_FULL_RST_COMMON_API
+
+ unsigned int val;
+
+ /* Use PMIC common API for PMIC full reset detection */
+
+#if LK_AS_BL33 == 1
+ val = g_boot_arg->cold_reset;
+#else
+ /* Use PMIC common API for PMIC full reset detection */
+ val = is_pmic_cold_reset();
+#endif
+
+#else
+
+ static unsigned int val = 0;
+ static unsigned int handled = 0;
+
+ /*
+ * PMIC common API may be failed in some platforms.
+ *
+ * Use a non-volatile register (reset only after battery is removed)
+ * for PMIC full reset detection.
+ *
+ * In such platforms, use bit 0 in register PMIC_RG_RSV_SWREG.
+ */
+
+ if (!handled) {
+
+ pmic_read_interface(PMIC_RG_RSV_SWREG_ADDR, &val, 0x1, 0);
+
+ if (val)
+ pmic_config_interface(PMIC_RG_RSV_SWREG_ADDR, 0, 0x1, 0);
+
+ dprintf(INFO, "PMIC full rst: %d\n", val);
+
+ handled = 1;
+ }
+
+#endif
+ return val ? 1 : 0;
+}
+
+void set_clr_fastboot_mode(bool flag)
+{
+ if (flag == true)
+ mtk_wd_SetNonResetReg2(0x2, 1);
+ else if (flag == false)
+ mtk_wd_SetNonResetReg2(0x2, 0);
+
+ dprintf(INFO, "set_clr_fastboot_mode\n");
+}
+
+void set_clr_recovery_mode(bool flag)
+{
+ if (flag == true)
+ mtk_wd_SetNonResetReg2(0x1, 1);
+ else if (flag == false)
+ mtk_wd_SetNonResetReg2(0x1, 0);
+
+ dprintf(INFO, "set_clr_recovery_mode\n");
+}
+
+bool check_fastboot_mode(void)
+{
+ return mtk_wd_CheckNonResetReg2(0x2);
+}
+
+bool check_recovery_mode(void)
+{
+ return mtk_wd_CheckNonResetReg2(0x1);
+}
+
+void mtk_wdt_disable(void)
+{
+ u32 tmp;
+
+ tmp = readl(MTK_WDT_MODE);
+ tmp &= ~MTK_WDT_MODE_ENABLE; /* disable watchdog */
+ tmp |= (MTK_WDT_MODE_KEY); /* need key then write is allowed */
+ writel(tmp, MTK_WDT_MODE);
+}
+
+static void mtk_wdt_reset(char mode)
+{
+ /* Watchdog Rest */
+ unsigned int wdt_mode_val;
+ writel(MTK_WDT_RESTART_KEY, MTK_WDT_RESTART);
+
+ wdt_mode_val = readl(MTK_WDT_MODE);
+ /* clear autorestart bit: autoretart: 1, bypass power key, 0: not bypass power key */
+ wdt_mode_val &=(~MTK_WDT_MODE_AUTO_RESTART);
+ /* make sure WDT mode is hw reboot mode, can not config isr mode */
+ wdt_mode_val &= ~(MTK_WDT_MODE_IRQ | MTK_WDT_MODE_ENABLE | MTK_WDT_MODE_DUAL_MODE);
+
+ wdt_mode_val |= (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN);
+
+ if (mode) /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
+ wdt_mode_val |= MTK_WDT_MODE_AUTO_RESTART;
+
+ writel(wdt_mode_val, MTK_WDT_MODE);
+
+ spin(100);
+ writel(MTK_WDT_SWRST_KEY, MTK_WDT_SWRST);
+}
+
+unsigned int mtk_wdt_check_status(void)
+{
+ static unsigned int status = 0;
+
+ /*
+ * Because WDT_STA register will be cleared after writing WDT_MODE,
+ * we use a static variable to store WDT_STA.
+ * After reset, static varialbe will always be clear to 0,
+ * so only read WDT_STA when static variable is 0 is OK
+ */
+ if (0 == status)
+ status = readl(MTK_WDT_STATUS);
+
+ return status;
+}
+
+static void mtk_wdt_mode_config(bool dual_mode_en,
+ bool irq,
+ bool ext_en,
+ bool ext_pol,
+ bool wdt_en)
+{
+ unsigned int tmp;
+
+ tmp = readl(MTK_WDT_MODE);
+ tmp |= MTK_WDT_MODE_KEY;
+
+ // Bit 0 : Whether enable watchdog or not
+ if (wdt_en == true)
+ tmp |= MTK_WDT_MODE_ENABLE;
+ else
+ tmp &= ~MTK_WDT_MODE_ENABLE;
+
+ // Bit 1 : Configure extern reset signal polarity.
+ if (ext_pol == true)
+ tmp |= MTK_WDT_MODE_EXT_POL;
+ else
+ tmp &= ~MTK_WDT_MODE_EXT_POL;
+
+ // Bit 2 : Whether enable external reset signal
+ if (ext_en == true)
+ tmp |= MTK_WDT_MODE_EXTEN;
+ else
+ tmp &= ~MTK_WDT_MODE_EXTEN;
+
+ // Bit 3 : Whether generating interrupt instead of reset signal
+ if (irq == true)
+ tmp |= MTK_WDT_MODE_IRQ;
+ else
+ tmp &= ~MTK_WDT_MODE_IRQ;
+
+ // Bit 6 : Whether enable debug module reset
+ if (dual_mode_en == true)
+ tmp |= MTK_WDT_MODE_DUAL_MODE;
+ else
+ tmp &= ~MTK_WDT_MODE_DUAL_MODE;
+
+ // Bit 4: WDT_Auto_restart, this is a reserved bit, we use it as bypass powerkey flag.
+ // Because HW reboot always need reboot to kernel, we set it always.
+ tmp |= MTK_WDT_MODE_AUTO_RESTART;
+
+ writel(tmp, MTK_WDT_MODE);
+ //dual_mode(1); //always dual mode
+ //mdelay(100);
+ dprintf(INFO,"mtk_wdt_mode_config LK mode value=%x", readl(MTK_WDT_MODE));
+}
+
+static void mtk_wdt_set_time_out_value(uint32_t value)
+{
+ static unsigned int timeout;
+
+ /*
+ * TimeOut = BitField 15:5
+ * Key = BitField 4:0 = 0x08
+ */
+
+ // sec * 32768 / 512 = sec * 64 = sec * 1 << 6
+ timeout = (unsigned int)(value * ( 1 << 6) );
+ timeout = timeout << 5;
+ writel((timeout | MTK_WDT_LENGTH_KEY), MTK_WDT_LENGTH);
+}
+
+void mtk_wdt_restart(void)
+{
+ // Reset WatchDogTimer's counting value to time out value
+ // ie., keepalive()
+ writel(MTK_WDT_RESTART_KEY, MTK_WDT_RESTART);
+}
+
+static void mtk_wdt_sw_reset(void)
+{
+ printf ("UB WDT SW RESET\n");
+ mtk_wdt_reset(1); /* NOTE here, this reset will cause by pass power key */
+
+ while (1) {
+ printf ("UB SW reset fail ... \n");
+ }
+}
+
+static void mtk_wdt_hw_reset(void)
+{
+ dprintf(INFO,"UB WDT_HW_Reset\n");
+
+ // 1. set WDT timeout 1 secs, 1*64*512/32768 = 1sec
+ mtk_wdt_set_time_out_value(1);
+
+ // 2. enable WDT debug reset enable, generating irq disable, ext reset disable
+ // ext reset signal low, wdt enalbe
+ mtk_wdt_mode_config(true, false, false, false, true);
+
+ // 3. reset the watch dog timer to the value set in WDT_LENGTH register
+ mtk_wdt_restart();
+
+ // 4. system will reset
+ while (1);
+}
+
+void mtk_wdt_init(void)
+{
+ unsigned int tmp;
+
+ /* This function will store the reset reason: Time out/ SW trigger */
+ dprintf(ALWAYS, "RGU STA: %x\n", mtk_wdt_check_status());
+
+ mtk_wdt_mode_config(false, false, false, false, false);
+
+ /* clear dbg_ctl3[15] to enable ddr reserved mode */
+ tmp = readl(MTK_WDT_DEBUG_CTL3);
+ tmp &= ~MTK_WDT_DEBUG_CTL3_DIS_DDR_RSV;
+ writel(tmp | MTK_WDT_DEBUG_CTL3_KEY, MTK_WDT_DEBUG_CTL3);
+
+#if (!LK_WDT_DISABLE)
+ mtk_wdt_set_time_out_value(10);
+ mtk_wdt_mode_config(true, true, true, false, true);
+ mtk_wdt_restart();
+#endif
+}
+
+static bool mtk_is_rgu_trigger_reset(void)
+{
+ if (mtk_wdt_check_status())
+ return true;
+ return false;
+}
+
+void mtk_arch_reset(char mode)
+{
+ dprintf(INFO,"UB mtk_arch_reset\n");
+
+ mtk_wdt_reset(mode);
+
+ while (1);
+}
+
+static void rgu_swsys_reset(WD_SYS_RST_TYPE reset_type)
+{
+ if (WD_MD_RST == reset_type) {
+ unsigned int wdt_dbg_ctrl;
+ wdt_dbg_ctrl = readl(MTK_WDT_SWSYSRST);
+ wdt_dbg_ctrl |= MTK_WDT_SWSYS_RST_KEY;
+ wdt_dbg_ctrl |= 0x80;// 1<<7
+ writel(wdt_dbg_ctrl, MTK_WDT_SWSYSRST);
+ spin(1000);
+ wdt_dbg_ctrl = readl(MTK_WDT_SWSYSRST);
+ wdt_dbg_ctrl |= MTK_WDT_SWSYS_RST_KEY;
+ wdt_dbg_ctrl &= (~0x80);// ~(1<<7)
+ writel(wdt_dbg_ctrl, MTK_WDT_SWSYSRST);
+ dprintf(INFO,"rgu pl md reset\n");
+ }
+}
+
+#else
+
+int mtk_wdt_is_pmic_full_reset(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_is_pmic_full_reset called\n");
+}
+
+void mtk_wdt_init(void)
+{
+ dprintf(INFO,"UB WDT Dummy init called\n");
+}
+
+static bool mtk_is_rgu_trigger_reset()
+{
+ dprintf(INFO,"UB Dummy mtk_is_rgu_trigger_reset called\n");
+ return FALSE;
+}
+
+void mtk_arch_reset(char mode)
+{
+ dprintf(INFO,"UB WDT Dummy arch reset called\n");
+}
+
+int mtk_wdt_boot_check(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_boot_check called\n");
+ return WDT_NOT_WDT_REBOOT;
+}
+
+void mtk_wdt_disable(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_disable called\n");
+}
+
+unsigned int mtk_wdt_check_status(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_check_status called\n");
+}
+
+static void mtk_wdt_restart(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_restart called\n");
+}
+
+static void mtk_wdt_sw_reset(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_sw_reset called\n");
+}
+
+static void mtk_wdt_hw_reset(void)
+{
+ dprintf(INFO,"UB WDT Dummy mtk_wdt_hw_reset called\n");
+}
+
+static void rgu_swsys_reset(WD_SYS_RST_TYPE reset_type)
+{
+ dprintf(INFO,"UB WDT Dummy rgu_swsys_reset called\n");
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/fixup/plat_fixup.c b/src/bsp/lk/platform/mt2731/fixup/plat_fixup.c
new file mode 100644
index 0000000..c199fe2
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/fixup/plat_fixup.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <assert.h>
+#include <compiler.h>
+#include <err.h>
+#include <libfdt.h>
+#include <lib/kcmdline.h>
+#include <malloc.h>
+#include <stdlib.h>
+#include <string.h>
+#include <trace.h>
+#include <lib/bio.h>
+#include <platform/nand/nand.h>
+
+#define LOCAL_TRACE 0
+
+extern __WEAK void mrdump_append_cmdline(void);
+
+#if ENABLE_MODEM_LOAD
+extern int extract_fdt(void *fdt, int size);
+static void md_append_fdt(void *fdt_dtb)
+{
+ /* extract fdt */
+ if (extract_fdt(fdt_dtb, MAX_DTB_SIZE)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "extract_fdt");
+ return;
+ }
+
+ extern int ccci_update_md_arg_info_to_dt(void *boot_dtb);
+ if (ccci_update_md_arg_info_to_dt(fdt_dtb)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "md_arg_fdt");
+ return;
+ }
+
+ if (fdt_pack(fdt_dtb)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "fdt_pack");
+ return;
+ }
+}
+#endif
+
+#if OPTION_RESERVE_HSM_MEMORY_FLAG
+extern int extract_fdt(void *fdt, int size);
+static void hsm_append_fdt(void *fdt_dtb)
+{
+ /* extract fdt */
+ if (extract_fdt(fdt_dtb, MAX_DTB_SIZE)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "extract_fdt");
+ return;
+ }
+
+ extern int hsm_update_info_to_dt(void *boot_dtb);
+ if (hsm_update_info_to_dt(fdt_dtb)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "hsm_info_fdt");
+ return;
+ }
+
+ if (fdt_pack(fdt_dtb)) {
+ dprintf(CRITICAL, "%s failed: %s\n", __func__, "fdt_pack");
+ return;
+ }
+}
+#endif
+
+#if defined(AB_OTA_UPDATER)
+static void ab_fixup(const char *ab_suffix)
+{
+ int rc;
+ char *suffix_arg;
+
+ if (!ab_suffix)
+ return;
+
+ suffix_arg = (char *)malloc(strlen("androidboot.slot_suffix=") +
+ strlen(ab_suffix) + 1);
+ if (!suffix_arg) {
+ LTRACEF("Not enough memory for suffix cmdline\n");
+ return;
+ }
+
+ sprintf(suffix_arg, "androidboot.slot_suffix=%s", ab_suffix);
+ rc = kcmdline_append(suffix_arg);
+ assert(rc == NO_ERROR);
+ free(suffix_arg);
+}
+#endif
+
+static void project_fixup_hook(uint32_t boot_mode, const char *ab_suffix)
+{
+#if defined(AB_OTA_UPDATER)
+ bdev_t *bdev;
+ char *part_name;
+ char *part_uuid;
+ char *part_rootfs; //for nand
+ const char *suffix = ab_suffix ? : "";
+
+ part_name = (char *)malloc(strlen(ROOTFS_PART_NAME) +
+ strlen(suffix) + 1);
+ if (!part_name) {
+ LTRACEF("Not enough memory for part_name\n");
+ return;
+ }
+
+ sprintf(part_name, "%s%s", ROOTFS_PART_NAME, suffix);
+
+ bdev = bio_open_by_label(part_name);
+ if (!bdev) {
+ LTRACEF("Partition not exist: %s\n", part_name);
+ goto err;
+ }
+
+#if defined(MTK_NAND_PAGE_SIZE)
+ LTRACEF("This is nand, bdev->name == %s. \n", bdev->name);
+ part_rootfs = (char *)malloc(strlen("ubi.mtd=") + strlen(bdev->name) - strlen("nand0p") + 1);
+
+ sprintf(part_rootfs, "ubi.mtd=%d", atoi(bdev->name + strlen("nand0p"))-1);
+ kcmdline_subst("ubi.mtd=13",part_rootfs);
+ LTRACEF("This is nand, part_rootfs == %s. \n", part_rootfs);
+
+ free(part_rootfs);
+#else
+ part_uuid = (char *)malloc(strlen("root=PARTUUID=") +
+ strlen(bdev->unique_uuid) + 1);
+ if (!part_uuid) {
+ LTRACEF("Not enough memory for part_uuid\n");
+ goto err;
+ }
+
+ sprintf(part_uuid, "root=PARTUUID=%s", bdev->unique_uuid);
+ kcmdline_append(part_uuid);
+ free(part_uuid);
+#endif
+err:
+ free(part_name);
+ bio_close(bdev);
+#endif
+}
+/* need to do fixup when bl2 or bl33 lk will load kernel image */
+#if (defined(ENABLE_BUILTIN_BL33) && (ENABLE_BUILTIN_BL33 == 1)) || \
+ (defined(LK_AS_BL33) && (LK_AS_BL33 == 1))
+int plat_fixup_init(void)
+{
+ return kcmdline_init();
+}
+
+void plat_fixup_append(char *append_str)
+{
+ if (kcmdline_append(append_str) != NO_ERROR) {
+ LTRACEF("append str failed: %s\n", append_str);
+ }
+}
+
+void plat_fixup_hook(uint32_t boot_mode, const char *ab_suffix,
+ void *dtb, size_t dtb_size)
+{
+ /* feature related fixup */
+#if defined(AB_OTA_UPDATER)
+ ab_fixup(ab_suffix);
+#endif
+
+#if defined(MTK_NAND_PAGE_SIZE)
+ nand_prepare_goto_kernel();
+#endif
+
+ extern void bootargs_init(void *fdt) __attribute__((weak));
+ if (bootargs_init)
+ bootargs_init(dtb);
+
+ if (mrdump_append_cmdline)
+ mrdump_append_cmdline();
+
+ /* android or yocto project specific fixup */
+ project_fixup_hook(boot_mode, ab_suffix);
+
+#if ENABLE_MODEM_LOAD
+ md_append_fdt(dtb);
+#endif
+
+#if OPTION_RESERVE_HSM_MEMORY_FLAG
+ hsm_append_fdt(dtb);
+#endif
+
+ /* finalized fixup */
+ if (kcmdline_finalized(dtb, dtb_size)) {
+ LTRACEF("kcmdline finalized failed.\n");
+ }
+}
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/MT6389/mt6389.h b/src/bsp/lk/platform/mt2731/include/platform/MT6389/mt6389.h
new file mode 100755
index 0000000..4d85391
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/MT6389/mt6389.h
@@ -0,0 +1,515 @@
+#ifndef __LINUX_REGULATOR_MT6389_H_
+#define __LINUX_REGULATOR_MT6389_H_
+
+#include <sys/types.h>
+#include <debug.h>
+#include <platform/MT6389/mtk_regulator_core.h>
+#include <platform/MT6389/upmu_hw.h>
+#include <platform/MT6389/mt6389.h>
+
+#define PMIC_PRELOADER 1
+#define LDO_SUPPORT
+/*#define LDO_VOTRIM_SUPPORT*/
+#define MT6389_DEBUG 1
+
+#if MT6389_DEBUG
+#define PMUTAG "[MT6389] "
+#define mreg_dbg_print(fmt, arg...) dprintf(CRITICAL,PMUTAG fmt, ##arg)
+#else
+#define mreg_dbg_print(fmt, arg...)
+#endif
+
+#define udelay(x) spin(x)
+#define mdelay(x) udelay((x) * 1000)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+typedef enum {
+ DISABLE_REGULATOR,
+ ENABLE_REGULATOR,
+} enset;
+
+typedef enum {
+ AUTOMODE,
+ PWMMODE,
+} modeset;
+
+#ifdef LDO_SUPPORT
+typedef enum {
+ VOLTOSEL,
+ SELTOVOL,
+} volseltran;
+#endif /*--LDO_SUPPORT--*/
+
+#ifdef LDO_VOTRIM_SUPPORT
+typedef enum {
+ TRIMTOSEL,
+ SELTOTRIM,
+} trimseltran;
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+
+typedef enum {
+ NON_REGULAR_VOLTAGE,
+ FIXED_REGULAR_VOLTAGE,
+ REGULAR_VOLTAGE,
+} regulator_type;
+
+typedef enum {
+ ONE_STEP_VOLT,
+ TWO_STEP_VOLT,
+ SPE_STEP_VOLT,
+ NON_STEP_VOLT,
+} step_uV_type;
+
+typedef enum {
+ VSPOS_ONE,
+ VSPOS_TWO,
+ VSPOS_NONE,
+} vol_shift_pos;
+
+typedef enum {
+ VMPOS_ONE,
+ VMPOS_TWO,
+ VMPOS_THREE,
+ VMPOS_NONE,
+} vol_mask_pos;
+
+
+typedef enum {
+ EPOS_ONE,
+ EPOS_NONE,
+} enable_bit_pos;
+
+typedef enum {
+ MPOS_ONE,
+ MPOS_TWO,
+ MPOS_THREE,
+ MPOS_FOUR,
+ MPOS_NONE,
+} mode_bit_pos;
+
+#ifdef LDO_VOTRIM_SUPPORT
+struct mt6389_ldo_trim_info {
+ unsigned short trim_reg;
+ unsigned short trim_mask;
+ unsigned short trim_shift;
+ const void *trim_voltages;
+ unsigned int trim_size;
+};
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+
+#ifdef LDO_SUPPORT
+static unsigned int mt6389_ldo_convert_data(unsigned char id,
+ unsigned int cnvdata, volseltran transtype);
+
+struct mt6389_ldo_info {
+ const void *pvoltages;
+ const void *idxs;
+ unsigned int n_size;
+};
+#endif /*--LDO_SUPPORT--*/
+
+/*--abstrac the same parameter--*/
+struct mt6389_regulator_info {
+ unsigned int min_uV;
+ unsigned int max_uV;
+ unsigned short vol_reg;
+ unsigned short vol_mask;
+ unsigned short vol_shift;
+ unsigned short da_vol_reg;
+ unsigned short da_vol_mask;
+ unsigned short da_vol_shift;
+ unsigned short enable_reg;
+ unsigned short enable_shift;
+ unsigned short mode_reg;
+ unsigned short mode_shift;
+#ifdef LDO_SUPPORT
+ struct mt6389_ldo_info *extinfo;
+#endif /*--LDO_SUPPORT--*/
+#ifdef LDO_VOTRIM_SUPPORT
+ struct mt6389_ldo_trim_info *triminfo;
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+ unsigned short step_uV;
+ regulator_type rtype;
+};
+
+#ifdef LDO_VOTRIM_SUPPORT
+#define mt6389_ldo_trim_decl(_name, trim_array)\
+{ \
+ .trim_reg = _name##_trim_reg, \
+ .trim_mask = _name##_trim_mask, \
+ .trim_shift = _name##_trim_shift, \
+ .trim_voltages = (void *)(trim_array), \
+ .trim_size = ARRAY_SIZE(trim_array), \
+}
+#endif /*--LDO_VOTRIM_SUPPORT--*/
+
+#ifdef LDO_SUPPORT
+#define mt6389_ldo_decl(volt_array, idx_array)\
+{ \
+ .pvoltages = (void *)(volt_array), \
+ .idxs = (void *)(idx_array), \
+ .n_size = ARRAY_SIZE(volt_array), \
+}
+#endif /*--LDO_SUPPORT--*/
+
+#define mt6389_decl(_name)\
+{ \
+ .min_uV = _name##_min_uV, \
+ .max_uV = _name##_max_uV, \
+ .vol_reg = _name##_vol_reg, \
+ .vol_mask = _name##_vol_mask, \
+ .vol_shift = _name##_vol_shift, \
+ .da_vol_reg = _name##_da_vol_reg, \
+ .da_vol_mask = _name##_da_vol_mask, \
+ .da_vol_shift = _name##_da_vol_shift, \
+ .enable_reg = _name##_enable_reg, \
+ .enable_shift = _name##_enable_shift, \
+ .mode_reg = _name##_mode_reg, \
+ .mode_shift = _name##_mode_shift, \
+ .step_uV = _name##_step_uV, \
+ .rtype = _name##_volt_type, \
+}
+
+/* -------Code Gen Start-------*/
+#define vs1_vol_reg PMIC_RG_BUCK_VS1_VOSEL_ADDR
+#define vs1_vol_mask PMIC_RG_BUCK_VS1_VOSEL_MASK
+#define vs1_vol_shift PMIC_RG_BUCK_VS1_VOSEL_SHIFT
+#define vs1_da_vol_reg PMIC_DA_VS1_VOSEL_ADDR
+#define vs1_da_vol_mask PMIC_DA_VS1_VOSEL_MASK
+#define vs1_da_vol_shift PMIC_DA_VS1_VOSEL_SHIFT
+#define vs1_enable_reg PMIC_RG_BUCK_VS1_EN_ADDR
+#define vs1_enable_shift PMIC_RG_BUCK_VS1_EN_SHIFT
+#define vs1_mode_reg PMIC_RG_VS1_FCCM_ADDR
+#define vs1_mode_shift PMIC_RG_VS1_FCCM_SHIFT
+#define vs1_trim_reg 0
+#define vs1_trim_mask 0
+#define vs1_trim_shift 0
+#define vs1_min_uV 1400000
+#define vs1_max_uV 2200000
+#define vs1_step_uV 12500
+#define vs1_volt_type REGULAR_VOLTAGE
+#define vs1_stb 1000
+
+
+#define vdram1_vol_reg PMIC_RG_BUCK_VDRAM1_VOSEL_ADDR
+#define vdram1_vol_mask PMIC_RG_BUCK_VDRAM1_VOSEL_MASK
+#define vdram1_vol_shift PMIC_RG_BUCK_VDRAM1_VOSEL_SHIFT
+#define vdram1_da_vol_reg PMIC_DA_VDRAM1_VOSEL_ADDR
+#define vdram1_da_vol_mask PMIC_DA_VDRAM1_VOSEL_MASK
+#define vdram1_da_vol_shift PMIC_DA_VDRAM1_VOSEL_SHIFT
+#define vdram1_enable_reg PMIC_RG_BUCK_VDRAM1_EN_ADDR
+#define vdram1_enable_shift PMIC_RG_BUCK_VDRAM1_EN_SHIFT
+#define vdram1_mode_reg PMIC_RG_VDRAM1_FCCM_ADDR
+#define vdram1_mode_shift PMIC_RG_VDRAM1_FCCM_SHIFT
+#define vdram1_trim_reg 0
+#define vdram1_trim_mask 0
+#define vdram1_trim_shift 0
+#define vdram1_min_uV 700000
+#define vdram1_max_uV 1493750
+#define vdram1_step_uV 6250
+#define vdram1_volt_type REGULAR_VOLTAGE
+#define vdram1_stb 1000
+
+
+#define vmodem_vol_reg PMIC_RG_BUCK_VMODEM_VOSEL_ADDR
+#define vmodem_vol_mask PMIC_RG_BUCK_VMODEM_VOSEL_MASK
+#define vmodem_vol_shift PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT
+#define vmodem_da_vol_reg PMIC_DA_VMODEM_VOSEL_ADDR
+#define vmodem_da_vol_mask PMIC_DA_VMODEM_VOSEL_MASK
+#define vmodem_da_vol_shift PMIC_DA_VMODEM_VOSEL_SHIFT
+#define vmodem_enable_reg PMIC_RG_BUCK_VMODEM_EN_ADDR
+#define vmodem_enable_shift PMIC_RG_BUCK_VMODEM_EN_SHIFT
+#define vmodem_mode_reg PMIC_RG_VMODEM_FCCM_ADDR
+#define vmodem_mode_shift PMIC_RG_VMODEM_FCCM_SHIFT
+#define vmodem_trim_reg 0
+#define vmodem_trim_mask 0
+#define vmodem_trim_shift 0
+#define vmodem_min_uV 500000
+#define vmodem_max_uV 1293750
+#define vmodem_step_uV 6250
+#define vmodem_volt_type REGULAR_VOLTAGE
+#define vmodem_stb 1000
+
+
+#define vcore_vol_reg PMIC_RG_BUCK_VCORE_VOSEL_ADDR
+#define vcore_vol_mask PMIC_RG_BUCK_VCORE_VOSEL_MASK
+#define vcore_vol_shift PMIC_RG_BUCK_VCORE_VOSEL_SHIFT
+#define vcore_da_vol_reg PMIC_DA_VCORE_VOSEL_ADDR
+#define vcore_da_vol_mask PMIC_DA_VCORE_VOSEL_MASK
+#define vcore_da_vol_shift PMIC_DA_VCORE_VOSEL_SHIFT
+#define vcore_enable_reg PMIC_RG_BUCK_VCORE_EN_ADDR
+#define vcore_enable_shift PMIC_RG_BUCK_VCORE_EN_SHIFT
+#define vcore_mode_reg PMIC_RG_VCORE_FCCM_ADDR
+#define vcore_mode_shift PMIC_RG_VCORE_FCCM_SHIFT
+#define vcore_trim_reg 0
+#define vcore_trim_mask 0
+#define vcore_trim_shift 0
+#define vcore_min_uV 500000
+#define vcore_max_uV 1293750
+#define vcore_step_uV 6250
+#define vcore_volt_type REGULAR_VOLTAGE
+#define vcore_stb 1000
+
+
+#define vsram_others_vol_reg PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_ADDR
+#define vsram_others_vol_mask PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_MASK
+#define vsram_others_vol_shift PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SHIFT
+#define vsram_others_da_vol_reg PMIC_DA_VSRAM_OTHERS_VOSEL_ADDR
+#define vsram_others_da_vol_mask PMIC_DA_VSRAM_OTHERS_VOSEL_MASK
+#define vsram_others_da_vol_shift PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT
+#define vsram_others_enable_reg PMIC_RG_BUCK_VSRAM_OTHERS_EN_ADDR
+#define vsram_others_enable_shift PMIC_RG_BUCK_VSRAM_OTHERS_EN_SHIFT
+#define vsram_others_mode_reg PMIC_RG_VSRAM_OTHERS_FCCM_ADDR
+#define vsram_others_mode_shift PMIC_RG_VSRAM_OTHERS_FCCM_SHIFT
+#define vsram_others_trim_reg 0
+#define vsram_others_trim_mask 0
+#define vsram_others_trim_shift 0
+#define vsram_others_min_uV 500000
+#define vsram_others_max_uV 1293750
+#define vsram_others_step_uV 6250
+#define vsram_others_volt_type REGULAR_VOLTAGE
+#define vsram_others_stb 1000
+
+
+#define vproc_vol_reg PMIC_RG_BUCK_VPROC_VOSEL_ADDR
+#define vproc_vol_mask PMIC_RG_BUCK_VPROC_VOSEL_MASK
+#define vproc_vol_shift PMIC_RG_BUCK_VPROC_VOSEL_SHIFT
+#define vproc_da_vol_reg PMIC_DA_VPROC_VOSEL_ADDR
+#define vproc_da_vol_mask PMIC_DA_VPROC_VOSEL_MASK
+#define vproc_da_vol_shift PMIC_DA_VPROC_VOSEL_SHIFT
+#define vproc_enable_reg PMIC_RG_BUCK_VPROC_EN_ADDR
+#define vproc_enable_shift PMIC_RG_BUCK_VPROC_EN_SHIFT
+#define vproc_mode_reg PMIC_RG_VPROC_FCCM_ADDR
+#define vproc_mode_shift PMIC_RG_VPROC_FCCM_SHIFT
+#define vproc_trim_reg 0
+#define vproc_trim_mask 0
+#define vproc_trim_shift 0
+#define vproc_min_uV 500000
+#define vproc_max_uV 1293750
+#define vproc_step_uV 6250
+#define vproc_volt_type REGULAR_VOLTAGE
+#define vproc_stb 1000
+
+
+#define vs2_vol_reg PMIC_RG_BUCK_VS2_VOSEL_ADDR
+#define vs2_vol_mask PMIC_RG_BUCK_VS2_VOSEL_MASK
+#define vs2_vol_shift PMIC_RG_BUCK_VS2_VOSEL_SHIFT
+#define vs2_da_vol_reg PMIC_DA_VS2_VOSEL_ADDR
+#define vs2_da_vol_mask PMIC_DA_VS2_VOSEL_MASK
+#define vs2_da_vol_shift PMIC_DA_VS2_VOSEL_SHIFT
+#define vs2_enable_reg PMIC_RG_BUCK_VS2_EN_ADDR
+#define vs2_enable_shift PMIC_RG_BUCK_VS2_EN_SHIFT
+#define vs2_mode_reg PMIC_RG_VS2_FCCM_ADDR
+#define vs2_mode_shift PMIC_RG_VS2_FCCM_SHIFT
+#define vs2_trim_reg 0
+#define vs2_trim_mask 0
+#define vs2_trim_shift 0
+#define vs2_min_uV 700000
+#define vs2_max_uV 1493750
+#define vs2_step_uV 6250
+#define vs2_volt_type REGULAR_VOLTAGE
+#define vs2_stb 1000
+
+
+#define vgp3_vol_reg PMIC_RG_VGP3_VOSEL_ADDR
+#define vgp3_vol_mask PMIC_RG_VGP3_VOSEL_MASK
+#define vgp3_vol_shift PMIC_RG_VGP3_VOSEL_SHIFT
+#define vgp3_da_vol_reg 0
+#define vgp3_da_vol_mask 0
+#define vgp3_da_vol_shift 0
+#define vgp3_enable_reg PMIC_RG_LDO_VGP3_EN_ADDR
+#define vgp3_enable_shift PMIC_RG_LDO_VGP3_EN_SHIFT
+#define vgp3_mode_reg 0
+#define vgp3_mode_shift 0
+#define vgp3_trim_reg PMIC_RG_VGP3_VOTRIM_ADDR
+#define vgp3_trim_mask PMIC_RG_VGP3_VOTRIM_MASK
+#define vgp3_trim_shift PMIC_RG_VGP3_VOTRIM_SHIFT
+#define vgp3_min_uV 1200000
+#define vgp3_max_uV 1800000
+#define vgp3_step_uV 0
+#define vgp3_volt_type NON_REGULAR_VOLTAGE
+#define vgp3_stb 240
+
+
+#define vdram2_vol_reg PMIC_RG_VDRAM2_VOSEL_0_ADDR
+#define vdram2_vol_mask PMIC_RG_VDRAM2_VOSEL_0_MASK
+#define vdram2_vol_shift PMIC_RG_VDRAM2_VOSEL_0_SHIFT
+#define vdram2_da_vol_reg 0
+#define vdram2_da_vol_mask 0
+#define vdram2_da_vol_shift 0
+#define vdram2_enable_reg PMIC_RG_LDO_VDRAM2_EN_ADDR
+#define vdram2_enable_shift PMIC_RG_LDO_VDRAM2_EN_SHIFT
+#define vdram2_mode_reg 0
+#define vdram2_mode_shift 0
+#define vdram2_trim_reg PMIC_RG_VDRAM2_VOTRIM_ADDR
+#define vdram2_trim_mask PMIC_RG_VDRAM2_VOTRIM_MASK
+#define vdram2_trim_shift PMIC_RG_VDRAM2_VOTRIM_SHIFT
+#define vdram2_min_uV 600000
+#define vdram2_max_uV 1800000
+#define vdram2_step_uV 0
+#define vdram2_volt_type NON_REGULAR_VOLTAGE
+#define vdram2_stb 5280
+
+
+#define vsim1_vol_reg PMIC_RG_VSIM1_VOSEL_ADDR
+#define vsim1_vol_mask PMIC_RG_VSIM1_VOSEL_MASK
+#define vsim1_vol_shift PMIC_RG_VSIM1_VOSEL_SHIFT
+#define vsim1_da_vol_reg 0
+#define vsim1_da_vol_mask 0
+#define vsim1_da_vol_shift 0
+#define vsim1_enable_reg PMIC_RG_LDO_VSIM1_EN_ADDR
+#define vsim1_enable_shift PMIC_RG_LDO_VSIM1_EN_SHIFT
+#define vsim1_mode_reg 0
+#define vsim1_mode_shift 0
+#define vsim1_trim_reg PMIC_RG_VSIM1_VOTRIM_ADDR
+#define vsim1_trim_mask PMIC_RG_VSIM1_VOTRIM_MASK
+#define vsim1_trim_shift PMIC_RG_VSIM1_VOTRIM_SHIFT
+#define vsim1_min_uV 1700000
+#define vsim1_max_uV 3100000
+#define vsim1_step_uV 0
+#define vsim1_volt_type NON_REGULAR_VOLTAGE
+#define vsim1_stb 1140
+
+
+#define vusb_vol_reg PMIC_RG_VUSB_VOSEL_ADDR
+#define vusb_vol_mask PMIC_RG_VUSB_VOSEL_MASK
+#define vusb_vol_shift PMIC_RG_VUSB_VOSEL_SHIFT
+#define vusb_da_vol_reg 0
+#define vusb_da_vol_mask 0
+#define vusb_da_vol_shift 0
+#define vusb_enable_reg PMIC_RG_LDO_VUSB_EN_ADDR
+#define vusb_enable_shift PMIC_RG_LDO_VUSB_EN_SHIFT
+#define vusb_mode_reg 0
+#define vusb_mode_shift 0
+#define vusb_trim_reg PMIC_RG_VUSB_VOTRIM_ADDR
+#define vusb_trim_mask PMIC_RG_VUSB_VOTRIM_MASK
+#define vusb_trim_shift PMIC_RG_VUSB_VOTRIM_SHIFT
+#define vusb_min_uV 3000000
+#define vusb_max_uV 3000000
+#define vusb_step_uV 0
+#define vusb_volt_type FIXED_REGULAR_VOLTAGE
+#define vusb_stb 1140
+
+
+#define vsram_proc_vol_reg PMIC_RG_LDO_VSRAM_PROC_VOSEL_ADDR
+#define vsram_proc_vol_mask PMIC_RG_LDO_VSRAM_PROC_VOSEL_MASK
+#define vsram_proc_vol_shift PMIC_RG_LDO_VSRAM_PROC_VOSEL_SHIFT
+#define vsram_proc_da_vol_reg PMIC_DA_VSRAM_PROC_VOSEL_ADDR
+#define vsram_proc_da_vol_mask PMIC_DA_VSRAM_PROC_VOSEL_MASK
+#define vsram_proc_da_vol_shift PMIC_DA_VSRAM_PROC_VOSEL_SHIFT
+#define vsram_proc_enable_reg PMIC_RG_LDO_VSRAM_PROC_EN_ADDR
+#define vsram_proc_enable_shift PMIC_RG_LDO_VSRAM_PROC_EN_SHIFT
+#define vsram_proc_mode_reg 0
+#define vsram_proc_mode_shift 0
+#define vsram_proc_trim_reg 0
+#define vsram_proc_trim_mask 0
+#define vsram_proc_trim_shift 0
+#define vsram_proc_min_uV 500000
+#define vsram_proc_max_uV 1293750
+#define vsram_proc_step_uV 6250
+#define vsram_proc_volt_type REGULAR_VOLTAGE
+#define vsram_proc_stb 240
+
+
+#define vgp1_vol_reg PMIC_RG_VGP1_VOSEL_ADDR
+#define vgp1_vol_mask PMIC_RG_VGP1_VOSEL_MASK
+#define vgp1_vol_shift PMIC_RG_VGP1_VOSEL_SHIFT
+#define vgp1_da_vol_reg 0
+#define vgp1_da_vol_mask 0
+#define vgp1_da_vol_shift 0
+#define vgp1_enable_reg PMIC_RG_LDO_VGP1_EN_ADDR
+#define vgp1_enable_shift PMIC_RG_LDO_VGP1_EN_SHIFT
+#define vgp1_mode_reg 0
+#define vgp1_mode_shift 0
+#define vgp1_trim_reg PMIC_RG_VGP1_VOTRIM_ADDR
+#define vgp1_trim_mask PMIC_RG_VGP1_VOTRIM_MASK
+#define vgp1_trim_shift PMIC_RG_VGP1_VOTRIM_SHIFT
+#define vgp1_min_uV 1200000
+#define vgp1_max_uV 3300000
+#define vgp1_step_uV 0
+#define vgp1_volt_type NON_REGULAR_VOLTAGE
+#define vgp1_stb 1140
+
+
+#define vmch_vol_reg PMIC_RG_VMCH_VOSEL_ADDR
+#define vmch_vol_mask PMIC_RG_VMCH_VOSEL_MASK
+#define vmch_vol_shift PMIC_RG_VMCH_VOSEL_SHIFT
+#define vmch_da_vol_reg 0
+#define vmch_da_vol_mask 0
+#define vmch_da_vol_shift 0
+#define vmch_enable_reg PMIC_RG_LDO_VMCH_EN_ADDR
+#define vmch_enable_shift PMIC_RG_LDO_VMCH_EN_SHIFT
+#define vmch_mode_reg 0
+#define vmch_mode_shift 0
+#define vmch_trim_reg PMIC_RG_VMCH_VOTRIM_ADDR
+#define vmch_trim_mask PMIC_RG_VMCH_VOTRIM_MASK
+#define vmch_trim_shift PMIC_RG_VMCH_VOTRIM_SHIFT
+#define vmch_min_uV 2900000
+#define vmch_max_uV 3300000
+#define vmch_step_uV 0
+#define vmch_volt_type NON_REGULAR_VOLTAGE
+#define vmch_stb 1140
+
+
+#define vgp2_vol_reg PMIC_RG_VGP2_VOSEL_ADDR
+#define vgp2_vol_mask PMIC_RG_VGP2_VOSEL_MASK
+#define vgp2_vol_shift PMIC_RG_VGP2_VOSEL_SHIFT
+#define vgp2_da_vol_reg 0
+#define vgp2_da_vol_mask 0
+#define vgp2_da_vol_shift 0
+#define vgp2_enable_reg PMIC_RG_LDO_VGP2_EN_ADDR
+#define vgp2_enable_shift PMIC_RG_LDO_VGP2_EN_SHIFT
+#define vgp2_mode_reg 0
+#define vgp2_mode_shift 0
+#define vgp2_trim_reg PMIC_RG_VGP2_VOTRIM_ADDR
+#define vgp2_trim_mask PMIC_RG_VGP2_VOTRIM_MASK
+#define vgp2_trim_shift PMIC_RG_VGP2_VOTRIM_SHIFT
+#define vgp2_min_uV 1200000
+#define vgp2_max_uV 3300000
+#define vgp2_step_uV 0
+#define vgp2_volt_type NON_REGULAR_VOLTAGE
+#define vgp2_stb 1140
+
+
+#define va09_vol_reg PMIC_RG_VA09_VOSEL_ADDR
+#define va09_vol_mask PMIC_RG_VA09_VOSEL_MASK
+#define va09_vol_shift PMIC_RG_VA09_VOSEL_SHIFT
+#define va09_da_vol_reg 0
+#define va09_da_vol_mask 0
+#define va09_da_vol_shift 0
+#define va09_enable_reg PMIC_RG_LDO_VA09_EN_ADDR
+#define va09_enable_shift PMIC_RG_LDO_VA09_EN_SHIFT
+#define va09_mode_reg 0
+#define va09_mode_shift 0
+#define va09_trim_reg PMIC_RG_VA09_VOTRIM_ADDR
+#define va09_trim_mask PMIC_RG_VA09_VOTRIM_MASK
+#define va09_trim_shift PMIC_RG_VA09_VOTRIM_SHIFT
+#define va09_min_uV 800000
+#define va09_max_uV 1000000
+#define va09_step_uV 0
+#define va09_volt_type NON_REGULAR_VOLTAGE
+#define va09_stb 1140
+
+
+#define vsim2_vol_reg PMIC_RG_VSIM2_VOSEL_ADDR
+#define vsim2_vol_mask PMIC_RG_VSIM2_VOSEL_MASK
+#define vsim2_vol_shift PMIC_RG_VSIM2_VOSEL_SHIFT
+#define vsim2_da_vol_reg 0
+#define vsim2_da_vol_mask 0
+#define vsim2_da_vol_shift 0
+#define vsim2_enable_reg PMIC_RG_LDO_VSIM2_EN_ADDR
+#define vsim2_enable_shift PMIC_RG_LDO_VSIM2_EN_SHIFT
+#define vsim2_mode_reg 0
+#define vsim2_mode_shift 0
+#define vsim2_trim_reg PMIC_RG_VSIM2_VOTRIM_ADDR
+#define vsim2_trim_mask PMIC_RG_VSIM2_VOTRIM_MASK
+#define vsim2_trim_shift PMIC_RG_VSIM2_VOTRIM_SHIFT
+#define vsim2_min_uV 1700000
+#define vsim2_max_uV 3100000
+#define vsim2_step_uV 0
+#define vsim2_volt_type NON_REGULAR_VOLTAGE
+#define vsim2_stb 1140
+
+extern int mt6389_probe(void);
+
+#endif /* __LINUX_REGULATOR_MT6389_H_ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/MT6389/mtk_regulator_core.h b/src/bsp/lk/platform/mt2731/include/platform/MT6389/mtk_regulator_core.h
new file mode 100644
index 0000000..3f9b309
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/MT6389/mtk_regulator_core.h
@@ -0,0 +1,49 @@
+#ifndef __SSPM_MTK_REGULATOR_CORE_H
+#define __SSPM_MTK_REGULATOR_CORE_H
+
+#include <platform/regulator/mtk_regulator.h>
+
+#define LDO_SUPPORT
+/*#define LDO_VOTRIM_SUPPORT*/
+
+enum {
+ MTK_REGULATOR_VS1,
+ MTK_REGULATOR_VDRAM1,
+ MTK_REGULATOR_VMODEM,
+ MTK_REGULATOR_VCORE,
+ MTK_REGULATOR_VSRAM_OTHERS,
+ MTK_REGULATOR_VPROC,
+ MTK_REGULATOR_VS2,
+#ifdef LDO_SUPPORT
+ MTK_REGULATOR_VGP3,
+ MTK_REGULATOR_LDO_SUPPORT = MTK_REGULATOR_VGP3,
+ MTK_REGULATOR_VDRAM2,
+ MTK_REGULATOR_VUSB,
+ MTK_REGULATOR_VFE28,
+ MTK_REGULATOR_VSRAM_PROC,
+ MTK_REGULATOR_VGP1,
+ MTK_REGULATOR_VGP2,
+ MTK_REGULATOR_VMCH,
+ MTK_REGULATOR_VSIM1,
+ MTK_REGULATOR_VSIM2,
+#endif /*--LDO_SUPPORT--*/
+ MTK_REGULATOR_MAX_NR,
+};
+
+struct regulator_ctrl {
+ int (*set_voltage)(unsigned char id, unsigned int min_vol, unsigned int max_vol);
+ int (*get_voltage)(unsigned char id);
+ /* enable/disable regulator */
+ int (*enable)(unsigned char id, unsigned char en);
+ int (*is_enabled)(unsigned char id);
+ int (*set_mode)(unsigned char id, unsigned char mode);
+ int (*get_mode)(unsigned char id);
+#ifdef LDO_VOTRIM_SUPPORT
+ int (*set_votrim)(unsigned char id, int trim_volt);
+ int (*get_votrim)(unsigned char id);
+#endif /*--LDO_TRIM_SUPPORT--*/
+};
+
+extern int mtk_simple_regulator_register(struct mtk_regulator *mreg);
+
+#endif /* __SSPM_MTK_REGULATOR_CORE_H */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/MT6389/pmic.h b/src/bsp/lk/platform/mt2731/include/platform/MT6389/pmic.h
new file mode 100644
index 0000000..cb10b79
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/MT6389/pmic.h
@@ -0,0 +1,138 @@
+#ifndef _PL_MT_PMIC_H_
+#define _PL_MT_PMIC_H_
+
+#include <debug.h>
+#include <platform/MT6389/mtk_regulator_core.h>
+#include <platform/MT6389/mt6389.h>
+#include <sys/types.h>
+#include <string.h>
+
+#define PMIC_REDUCE_CODE_SIZE 0
+
+struct pmic_setting {
+ unsigned short addr;
+ unsigned short val;
+ unsigned short mask;
+ unsigned char shift;
+};
+
+struct pmuflag_t {
+ unsigned int addr;
+ unsigned int mask;
+ unsigned int shift;
+};
+
+struct pmic_auxadc_channel_new {
+ u8 resolution;
+ u8 r_val;
+ u8 ch_num;
+ struct pmuflag_t channel_rqst;
+ struct pmuflag_t channel_rdy;
+ struct pmuflag_t channel_out;
+};
+
+#define PMIC_AUXADC_GEN(_rel, _r_val, _ch_num, _rqst, _rdy, _out) \
+ { \
+ .resolution = _rel, \
+ .r_val = _r_val, \
+ .ch_num = _ch_num, \
+ .channel_rqst = { \
+ .addr = _rqst##_ADDR, \
+ .mask = _rqst##_MASK, \
+ .shift = _rqst##_SHIFT, \
+ }, \
+ .channel_rdy = { \
+ .addr = _rdy##_ADDR, \
+ .mask = _rdy##_MASK, \
+ .shift = _rdy##_SHIFT, \
+ }, \
+ .channel_out = { \
+ .addr = _out##_ADDR, \
+ .mask = _out##_MASK, \
+ .shift = _out##_SHIFT, \
+ }, \
+ }
+//==============================================================================
+// PMIC define
+//==============================================================================
+enum {
+ AUXADC_LIST_BATADC,
+ AUXADC_LIST_VCDT,
+ AUXADC_LIST_CHIP_TEMP,
+ AUXADC_LIST_VCORE_TEMP,
+ AUXADC_LIST_VPROC_TEMP,
+ AUXADC_LIST_VGPU_TEMP,
+ AUXADC_LIST_VS2_VOLT,
+ AUXADC_LIST_DCXO_VOLT,
+ AUXADC_LIST_VFRCK_1_VOLT,
+ AUXADC_LIST_VRFCK_VOLT,
+ AUXADC_LIST_AUD28_VOLT,
+ AUXADC_LIST_DIO18_VOLT,
+ AUXADC_LIST_DIO33_VOLT,
+ AUXADC_LIST_DEMC_VOLT,
+ AUXADC_LIST_DUSB_VOLT,
+ AUXADC_LIST_DRTC28_VOLT,
+ AUXADC_LIST_DDIG18_VOLT,
+ AUXADC_LIST_DDIG18_AO_VOLT,
+ AUXADC_LIST_VS1_VOLT,
+ AUXADC_LIST_VDRAM2_VOLT,
+ AUXADC_LIST_TSX,
+ AUXADC_LIST_VPROC_VOLT,
+ AUXADC_LIST_VCORE_VOLT,
+ AUXADC_LIST_VMODEM_VOLT,
+ AUXADC_LIST_VSRAM_OTHERS_VOLT,
+ AUXADC_LIST_VDRAM1_VOLT,
+ AUXADC_LIST_VBBCK_VOLT,
+ AUXADC_LIST_VA12_VOLT,
+ AUXADC_LIST_VA09_VOLT,
+ AUXADC_LIST_VSRAM_PROC_VOLT,
+ AUXADC_LIST_HPOFS_CAL,
+ AUXADC_LIST_DCXO_TEMP,
+ AUXADC_LIST_TREF_VOLT,
+ AUXADC_LIST_AP_HT_THR,
+ AUXADC_LIST_RF_PA_THR,
+ AUXADC_LIST_AP_LT_THR,
+ AUXADC_LIST_DRAM_HT_THR,
+ AUXADC_LIST_AUXIN9_DRDI,
+ AUXADC_LIST_GPS_ANT,
+ AUXADC_LIST_MAIN_ANT,
+ AUXADC_LIST_DRX_ANT,
+ AUXADC_LIST_MAX,
+};
+
+//==============================================================================
+// PMIC Status Code
+//==============================================================================
+#define PMIC_TEST_PASS 0x0000
+#define PMIC_TEST_FAIL 0xB001
+#define PMIC_EXCEED_I2C_FIFO_LENGTH 0xB002
+#define PMIC_CHRDET_EXIST 0xB003
+#define PMIC_CHRDET_NOT_EXIST 0xB004
+//==============================================================================
+// PMIC Exported Function
+//==============================================================================
+extern unsigned int pmic_read_interface(unsigned int RegNum, unsigned int *val, unsigned int MASK, unsigned int SHIFT);
+extern unsigned int pmic_config_interface(unsigned int RegNum, unsigned int val, unsigned int MASK, unsigned int SHIFT);
+extern int pmic_detect_powerkey(void);
+extern int pmic_detect_homekey(void);
+extern void hw_set_cc(int cc_val);
+extern void pl_charging(int en_chr);
+extern void pl_kick_chr_wdt(void);
+extern void pl_close_pre_chr_led(void);
+extern void pl_hw_ulc_det(void);
+extern unsigned int pmic_init (void);
+extern int pmic_get_auxadc_value(unsigned short channel);
+extern unsigned int is_pmic_cold_reset(void);
+extern unsigned int is_pmic_long_press_reset(void);
+extern unsigned int is_pwrkey_short_press(void);
+extern unsigned int get_pmic_boot_status(void);
+extern unsigned int pmic_read_efuse_nolock(int i);
+extern void pmic_cold_reset(void);
+extern void pmic_efuse_sw_load(void);
+extern void pmic_init_setting(void);
+extern void pmic_dbg_status(unsigned char option);
+extern unsigned int get_dram_type(void);
+extern unsigned int get_PMIC_chip_version(void);
+
+#endif // #ifndef _PMIC_H_
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/MT6389/upmu_hw.h b/src/bsp/lk/platform/mt2731/include/platform/MT6389/upmu_hw.h
new file mode 100755
index 0000000..fb06ecc
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/MT6389/upmu_hw.h
@@ -0,0 +1,31402 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+
+#ifndef _MT_PMIC_UPMU_HW_MT6389_H_
+#define _MT_PMIC_UPMU_HW_MT6389_H_
+
+#define PMU_FLAG_TABLE_ENTRY struct pmu_flag_table_entry_t
+#define PMU_FLAGS_LIST_ENUM enum PMU_FLAGS_LIST
+
+#define MT6389_PMIC_REG_BASE ((unsigned int)(0x0))
+
+#define MT6389_TOP0_ID (MT6389_PMIC_REG_BASE+0x0)
+#define MT6389_TOP0_REV0 (MT6389_PMIC_REG_BASE+0x2)
+#define MT6389_TOP0_DSN_DBI (MT6389_PMIC_REG_BASE+0x4)
+#define MT6389_TOP0_DSN_DXI (MT6389_PMIC_REG_BASE+0x6)
+#define MT6389_HWCID (MT6389_PMIC_REG_BASE+0x8)
+#define MT6389_SWCID (MT6389_PMIC_REG_BASE+0xa)
+#define MT6389_PONSTS (MT6389_PMIC_REG_BASE+0xc)
+#define MT6389_POFFSTS (MT6389_PMIC_REG_BASE+0xe)
+#define MT6389_PSTSCTL (MT6389_PMIC_REG_BASE+0x10)
+#define MT6389_PG_DEB_STS0 (MT6389_PMIC_REG_BASE+0x12)
+#define MT6389_PG_DEB_STS1 (MT6389_PMIC_REG_BASE+0x14)
+#define MT6389_PG_SDN_STS0 (MT6389_PMIC_REG_BASE+0x16)
+#define MT6389_PG_SDN_STS1 (MT6389_PMIC_REG_BASE+0x18)
+#define MT6389_OC_SDN_STS0 (MT6389_PMIC_REG_BASE+0x1a)
+#define MT6389_OC_SDN_STS1 (MT6389_PMIC_REG_BASE+0x1c)
+#define MT6389_THERMALSTATUS (MT6389_PMIC_REG_BASE+0x1e)
+#define MT6389_TOP_CON (MT6389_PMIC_REG_BASE+0x20)
+#define MT6389_TEST_OUT (MT6389_PMIC_REG_BASE+0x22)
+#define MT6389_TEST_CON0 (MT6389_PMIC_REG_BASE+0x24)
+#define MT6389_TEST_CON1 (MT6389_PMIC_REG_BASE+0x26)
+#define MT6389_TESTMODE_SW (MT6389_PMIC_REG_BASE+0x28)
+#define MT6389_TOPSTATUS (MT6389_PMIC_REG_BASE+0x2a)
+#define MT6389_TDSEL_CON (MT6389_PMIC_REG_BASE+0x2c)
+#define MT6389_RDSEL_CON (MT6389_PMIC_REG_BASE+0x2e)
+#define MT6389_SMT_CON0 (MT6389_PMIC_REG_BASE+0x30)
+#define MT6389_SMT_CON1 (MT6389_PMIC_REG_BASE+0x32)
+#define MT6389_TOP_RSV0 (MT6389_PMIC_REG_BASE+0x34)
+#define MT6389_TOP_RSV1 (MT6389_PMIC_REG_BASE+0x36)
+#define MT6389_DRV_CON0 (MT6389_PMIC_REG_BASE+0x38)
+#define MT6389_DRV_CON1 (MT6389_PMIC_REG_BASE+0x3a)
+#define MT6389_DRV_CON2 (MT6389_PMIC_REG_BASE+0x3c)
+#define MT6389_DRV_CON3 (MT6389_PMIC_REG_BASE+0x3e)
+#define MT6389_DRV_CON4 (MT6389_PMIC_REG_BASE+0x40)
+#define MT6389_FILTER_CON0 (MT6389_PMIC_REG_BASE+0x42)
+#define MT6389_FILTER_CON1 (MT6389_PMIC_REG_BASE+0x44)
+#define MT6389_FILTER_CON2 (MT6389_PMIC_REG_BASE+0x46)
+#define MT6389_FILTER_CON3 (MT6389_PMIC_REG_BASE+0x48)
+#define MT6389_TOP_STATUS (MT6389_PMIC_REG_BASE+0x4a)
+#define MT6389_TOP_STATUS_SET (MT6389_PMIC_REG_BASE+0x4c)
+#define MT6389_TOP_STATUS_CLR (MT6389_PMIC_REG_BASE+0x4e)
+#define MT6389_TOP_TRAP (MT6389_PMIC_REG_BASE+0x50)
+#define MT6389_TOP1_ID (MT6389_PMIC_REG_BASE+0x80)
+#define MT6389_TOP1_REV0 (MT6389_PMIC_REG_BASE+0x82)
+#define MT6389_TOP1_DSN_DBI (MT6389_PMIC_REG_BASE+0x84)
+#define MT6389_TOP1_DSN_DXI (MT6389_PMIC_REG_BASE+0x86)
+#define MT6389_GPIO_DIR0 (MT6389_PMIC_REG_BASE+0x88)
+#define MT6389_GPIO_DIR0_SET (MT6389_PMIC_REG_BASE+0x8a)
+#define MT6389_GPIO_DIR0_CLR (MT6389_PMIC_REG_BASE+0x8c)
+#define MT6389_GPIO_DIR1 (MT6389_PMIC_REG_BASE+0x8e)
+#define MT6389_GPIO_DIR1_SET (MT6389_PMIC_REG_BASE+0x90)
+#define MT6389_GPIO_DIR1_CLR (MT6389_PMIC_REG_BASE+0x92)
+#define MT6389_GPIO_PULLEN0 (MT6389_PMIC_REG_BASE+0x94)
+#define MT6389_GPIO_PULLEN0_SET (MT6389_PMIC_REG_BASE+0x96)
+#define MT6389_GPIO_PULLEN0_CLR (MT6389_PMIC_REG_BASE+0x98)
+#define MT6389_GPIO_PULLEN1 (MT6389_PMIC_REG_BASE+0x9a)
+#define MT6389_GPIO_PULLEN1_SET (MT6389_PMIC_REG_BASE+0x9c)
+#define MT6389_GPIO_PULLEN1_CLR (MT6389_PMIC_REG_BASE+0x9e)
+#define MT6389_GPIO_PULLSEL0 (MT6389_PMIC_REG_BASE+0xa0)
+#define MT6389_GPIO_PULLSEL0_SET (MT6389_PMIC_REG_BASE+0xa2)
+#define MT6389_GPIO_PULLSEL0_CLR (MT6389_PMIC_REG_BASE+0xa4)
+#define MT6389_GPIO_PULLSEL1 (MT6389_PMIC_REG_BASE+0xa6)
+#define MT6389_GPIO_PULLSEL1_SET (MT6389_PMIC_REG_BASE+0xa8)
+#define MT6389_GPIO_PULLSEL1_CLR (MT6389_PMIC_REG_BASE+0xaa)
+#define MT6389_GPIO_DINV0 (MT6389_PMIC_REG_BASE+0xac)
+#define MT6389_GPIO_DINV0_SET (MT6389_PMIC_REG_BASE+0xae)
+#define MT6389_GPIO_DINV0_CLR (MT6389_PMIC_REG_BASE+0xb0)
+#define MT6389_GPIO_DINV1 (MT6389_PMIC_REG_BASE+0xb2)
+#define MT6389_GPIO_DINV1_SET (MT6389_PMIC_REG_BASE+0xb4)
+#define MT6389_GPIO_DINV1_CLR (MT6389_PMIC_REG_BASE+0xb6)
+#define MT6389_GPIO_DOUT0 (MT6389_PMIC_REG_BASE+0xb8)
+#define MT6389_GPIO_DOUT0_SET (MT6389_PMIC_REG_BASE+0xba)
+#define MT6389_GPIO_DOUT0_CLR (MT6389_PMIC_REG_BASE+0xbc)
+#define MT6389_GPIO_DOUT1 (MT6389_PMIC_REG_BASE+0xbe)
+#define MT6389_GPIO_DOUT1_SET (MT6389_PMIC_REG_BASE+0xc0)
+#define MT6389_GPIO_DOUT1_CLR (MT6389_PMIC_REG_BASE+0xc2)
+#define MT6389_GPIO_PI0 (MT6389_PMIC_REG_BASE+0xc4)
+#define MT6389_GPIO_PI1 (MT6389_PMIC_REG_BASE+0xc6)
+#define MT6389_GPIO_POE0 (MT6389_PMIC_REG_BASE+0xc8)
+#define MT6389_GPIO_POE1 (MT6389_PMIC_REG_BASE+0xca)
+#define MT6389_GPIO_MODE0 (MT6389_PMIC_REG_BASE+0xcc)
+#define MT6389_GPIO_MODE0_SET (MT6389_PMIC_REG_BASE+0xce)
+#define MT6389_GPIO_MODE0_CLR (MT6389_PMIC_REG_BASE+0xd0)
+#define MT6389_GPIO_MODE1 (MT6389_PMIC_REG_BASE+0xd2)
+#define MT6389_GPIO_MODE1_SET (MT6389_PMIC_REG_BASE+0xd4)
+#define MT6389_GPIO_MODE1_CLR (MT6389_PMIC_REG_BASE+0xd6)
+#define MT6389_GPIO_MODE2 (MT6389_PMIC_REG_BASE+0xd8)
+#define MT6389_GPIO_MODE2_SET (MT6389_PMIC_REG_BASE+0xda)
+#define MT6389_GPIO_MODE2_CLR (MT6389_PMIC_REG_BASE+0xdc)
+#define MT6389_GPIO_MODE3 (MT6389_PMIC_REG_BASE+0xde)
+#define MT6389_GPIO_MODE3_SET (MT6389_PMIC_REG_BASE+0xe0)
+#define MT6389_GPIO_MODE3_CLR (MT6389_PMIC_REG_BASE+0xe2)
+#define MT6389_GPIO_MODE4 (MT6389_PMIC_REG_BASE+0xe4)
+#define MT6389_GPIO_MODE4_SET (MT6389_PMIC_REG_BASE+0xe6)
+#define MT6389_GPIO_MODE4_CLR (MT6389_PMIC_REG_BASE+0xe8)
+#define MT6389_GPIO_RSV (MT6389_PMIC_REG_BASE+0xea)
+#define MT6389_TOP2_ID (MT6389_PMIC_REG_BASE+0x100)
+#define MT6389_TOP2_REV0 (MT6389_PMIC_REG_BASE+0x102)
+#define MT6389_TOP2_DSN_DBI (MT6389_PMIC_REG_BASE+0x104)
+#define MT6389_TOP2_DSN_DXI (MT6389_PMIC_REG_BASE+0x106)
+#define MT6389_TOP_PAM0 (MT6389_PMIC_REG_BASE+0x108)
+#define MT6389_TOP_PAM1 (MT6389_PMIC_REG_BASE+0x10a)
+#define MT6389_TOP_CKPDN_CON0 (MT6389_PMIC_REG_BASE+0x10c)
+#define MT6389_TOP_CKPDN_CON0_SET (MT6389_PMIC_REG_BASE+0x10e)
+#define MT6389_TOP_CKPDN_CON0_CLR (MT6389_PMIC_REG_BASE+0x110)
+#define MT6389_TOP_CKPDN_CON1 (MT6389_PMIC_REG_BASE+0x112)
+#define MT6389_TOP_CKPDN_CON1_SET (MT6389_PMIC_REG_BASE+0x114)
+#define MT6389_TOP_CKPDN_CON1_CLR (MT6389_PMIC_REG_BASE+0x116)
+#define MT6389_TOP_CKSEL_CON0 (MT6389_PMIC_REG_BASE+0x118)
+#define MT6389_TOP_CKSEL_CON0_SET (MT6389_PMIC_REG_BASE+0x11a)
+#define MT6389_TOP_CKSEL_CON0_CLR (MT6389_PMIC_REG_BASE+0x11c)
+#define MT6389_TOP_CKSEL_CON1 (MT6389_PMIC_REG_BASE+0x11e)
+#define MT6389_TOP_CKSEL_CON1_SET (MT6389_PMIC_REG_BASE+0x120)
+#define MT6389_TOP_CKSEL_CON1_CLR (MT6389_PMIC_REG_BASE+0x122)
+#define MT6389_TOP_CKDIVSEL_CON0 (MT6389_PMIC_REG_BASE+0x124)
+#define MT6389_TOP_CKDIVSEL_CON0_SET (MT6389_PMIC_REG_BASE+0x126)
+#define MT6389_TOP_CKDIVSEL_CON0_CLR (MT6389_PMIC_REG_BASE+0x128)
+#define MT6389_TOP_CKHWEN_CON0 (MT6389_PMIC_REG_BASE+0x12a)
+#define MT6389_TOP_CKHWEN_CON0_SET (MT6389_PMIC_REG_BASE+0x12c)
+#define MT6389_TOP_CKHWEN_CON0_CLR (MT6389_PMIC_REG_BASE+0x12e)
+#define MT6389_TOP_CKTST_CON0 (MT6389_PMIC_REG_BASE+0x130)
+#define MT6389_TOP_CKTST_CON1 (MT6389_PMIC_REG_BASE+0x132)
+#define MT6389_TOP_CLK_CON0 (MT6389_PMIC_REG_BASE+0x134)
+#define MT6389_TOP_CLK_CON1 (MT6389_PMIC_REG_BASE+0x136)
+#define MT6389_TOP_CLK_DCM0 (MT6389_PMIC_REG_BASE+0x138)
+#define MT6389_TOP_RST_CON0 (MT6389_PMIC_REG_BASE+0x13a)
+#define MT6389_TOP_RST_CON0_SET (MT6389_PMIC_REG_BASE+0x13c)
+#define MT6389_TOP_RST_CON0_CLR (MT6389_PMIC_REG_BASE+0x13e)
+#define MT6389_TOP_RST_CON1 (MT6389_PMIC_REG_BASE+0x140)
+#define MT6389_TOP_RST_CON1_SET (MT6389_PMIC_REG_BASE+0x142)
+#define MT6389_TOP_RST_CON1_CLR (MT6389_PMIC_REG_BASE+0x144)
+#define MT6389_TOP_RST_CON2 (MT6389_PMIC_REG_BASE+0x146)
+#define MT6389_TOP_RST_CON3 (MT6389_PMIC_REG_BASE+0x148)
+#define MT6389_TOP_RST_MISC (MT6389_PMIC_REG_BASE+0x14a)
+#define MT6389_TOP_RST_MISC_SET (MT6389_PMIC_REG_BASE+0x14c)
+#define MT6389_TOP_RST_MISC_CLR (MT6389_PMIC_REG_BASE+0x14e)
+#define MT6389_TOP_RST_STATUS (MT6389_PMIC_REG_BASE+0x150)
+#define MT6389_TOP_RST_STATUS_SET (MT6389_PMIC_REG_BASE+0x152)
+#define MT6389_TOP_RST_STATUS_CLR (MT6389_PMIC_REG_BASE+0x154)
+#define MT6389_TOP2_ELR_NUM (MT6389_PMIC_REG_BASE+0x156)
+#define MT6389_TOP2_ELR0 (MT6389_PMIC_REG_BASE+0x158)
+#define MT6389_TOP2_ELR1 (MT6389_PMIC_REG_BASE+0x15a)
+#define MT6389_TOP3_ID (MT6389_PMIC_REG_BASE+0x180)
+#define MT6389_TOP3_REV0 (MT6389_PMIC_REG_BASE+0x182)
+#define MT6389_TOP3_DSN_DBI (MT6389_PMIC_REG_BASE+0x184)
+#define MT6389_TOP3_DSN_DXI (MT6389_PMIC_REG_BASE+0x186)
+#define MT6389_MISC_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x188)
+#define MT6389_MISC_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x18a)
+#define MT6389_MISC_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x18c)
+#define MT6389_MISC_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x18e)
+#define MT6389_MISC_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x190)
+#define MT6389_MISC_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x192)
+#define MT6389_MISC_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x194)
+#define MT6389_MISC_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x196)
+#define MT6389_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x198)
+#define MT6389_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x19a)
+#define MT6389_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x19c)
+#define MT6389_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x19e)
+#define MT6389_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x1a0)
+#define MT6389_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x1a2)
+#define MT6389_TOP_DCXO_CKEN_SW (MT6389_PMIC_REG_BASE+0x1a4)
+#define MT6389_PMRC_CON0 (MT6389_PMIC_REG_BASE+0x1a6)
+#define MT6389_PMRC_CON0_SET (MT6389_PMIC_REG_BASE+0x1a8)
+#define MT6389_PMRC_CON0_CLR (MT6389_PMIC_REG_BASE+0x1aa)
+#define MT6389_PMRC_CON1 (MT6389_PMIC_REG_BASE+0x1ac)
+#define MT6389_PMRC_CON1_SET (MT6389_PMIC_REG_BASE+0x1ae)
+#define MT6389_PMRC_CON1_CLR (MT6389_PMIC_REG_BASE+0x1b0)
+#define MT6389_PMRC_CON2 (MT6389_PMIC_REG_BASE+0x1b2)
+#define MT6389_PLT0_ID (MT6389_PMIC_REG_BASE+0x380)
+#define MT6389_PLT0_REV0 (MT6389_PMIC_REG_BASE+0x382)
+#define MT6389_PLT0_REV1 (MT6389_PMIC_REG_BASE+0x384)
+#define MT6389_PLT0_DSN_DXI (MT6389_PMIC_REG_BASE+0x386)
+#define MT6389_TOP_CLK_TRIM (MT6389_PMIC_REG_BASE+0x388)
+#define MT6389_OTP_CON0 (MT6389_PMIC_REG_BASE+0x38a)
+#define MT6389_OTP_CON1 (MT6389_PMIC_REG_BASE+0x38c)
+#define MT6389_OTP_CON2 (MT6389_PMIC_REG_BASE+0x38e)
+#define MT6389_OTP_CON3 (MT6389_PMIC_REG_BASE+0x390)
+#define MT6389_OTP_CON4 (MT6389_PMIC_REG_BASE+0x392)
+#define MT6389_OTP_CON5 (MT6389_PMIC_REG_BASE+0x394)
+#define MT6389_OTP_CON6 (MT6389_PMIC_REG_BASE+0x396)
+#define MT6389_OTP_CON7 (MT6389_PMIC_REG_BASE+0x398)
+#define MT6389_OTP_CON8 (MT6389_PMIC_REG_BASE+0x39a)
+#define MT6389_OTP_CON9 (MT6389_PMIC_REG_BASE+0x39c)
+#define MT6389_OTP_CON10 (MT6389_PMIC_REG_BASE+0x39e)
+#define MT6389_OTP_CON11 (MT6389_PMIC_REG_BASE+0x3a0)
+#define MT6389_OTP_CON12 (MT6389_PMIC_REG_BASE+0x3a2)
+#define MT6389_OTP_CON13 (MT6389_PMIC_REG_BASE+0x3a4)
+#define MT6389_OTP_CON14 (MT6389_PMIC_REG_BASE+0x3a6)
+#define MT6389_OTP_CON15 (MT6389_PMIC_REG_BASE+0x3a8)
+#define MT6389_OTP_CON16 (MT6389_PMIC_REG_BASE+0x3aa)
+#define MT6389_OTP_CON17 (MT6389_PMIC_REG_BASE+0x3ac)
+#define MT6389_OTP_CON18 (MT6389_PMIC_REG_BASE+0x3ae)
+#define MT6389_OTP_CON19 (MT6389_PMIC_REG_BASE+0x3b0)
+#define MT6389_OTP_CON20 (MT6389_PMIC_REG_BASE+0x3b2)
+#define MT6389_OTP_CON21 (MT6389_PMIC_REG_BASE+0x3b4)
+#define MT6389_OTP_CON22 (MT6389_PMIC_REG_BASE+0x3b6)
+#define MT6389_TOP_TMA_KEY (MT6389_PMIC_REG_BASE+0x3b8)
+#define MT6389_TOP_MDB_CONF0 (MT6389_PMIC_REG_BASE+0x3ba)
+#define MT6389_TOP_MDB_CONF1 (MT6389_PMIC_REG_BASE+0x3bc)
+#define MT6389_TOP_MDB_CONF2 (MT6389_PMIC_REG_BASE+0x3be)
+#define MT6389_TOP_MDB_CONF3 (MT6389_PMIC_REG_BASE+0x3c0)
+#define MT6389_PLT0_ELR_NUM (MT6389_PMIC_REG_BASE+0x3c2)
+#define MT6389_PLT0_ELR0 (MT6389_PMIC_REG_BASE+0x3c4)
+#define MT6389_SPISLV_ID (MT6389_PMIC_REG_BASE+0x400)
+#define MT6389_SPISLV_REV0 (MT6389_PMIC_REG_BASE+0x402)
+#define MT6389_SPISLV_REV1 (MT6389_PMIC_REG_BASE+0x404)
+#define MT6389_SPISLV_DSN_DXI (MT6389_PMIC_REG_BASE+0x406)
+#define MT6389_RG_SPI_CON0 (MT6389_PMIC_REG_BASE+0x408)
+#define MT6389_RG_SPI_RECORD0 (MT6389_PMIC_REG_BASE+0x40a)
+#define MT6389_DEW_DIO_EN (MT6389_PMIC_REG_BASE+0x40c)
+#define MT6389_DEW_READ_TEST (MT6389_PMIC_REG_BASE+0x40e)
+#define MT6389_DEW_WRITE_TEST (MT6389_PMIC_REG_BASE+0x410)
+#define MT6389_DEW_CRC_SWRST (MT6389_PMIC_REG_BASE+0x412)
+#define MT6389_DEW_CRC_EN (MT6389_PMIC_REG_BASE+0x414)
+#define MT6389_DEW_CRC_VAL (MT6389_PMIC_REG_BASE+0x416)
+#define MT6389_DEW_CIPHER_KEY_SEL (MT6389_PMIC_REG_BASE+0x418)
+#define MT6389_DEW_CIPHER_IV_SEL (MT6389_PMIC_REG_BASE+0x41a)
+#define MT6389_DEW_CIPHER_EN (MT6389_PMIC_REG_BASE+0x41c)
+#define MT6389_DEW_CIPHER_RDY (MT6389_PMIC_REG_BASE+0x41e)
+#define MT6389_DEW_CIPHER_MODE (MT6389_PMIC_REG_BASE+0x420)
+#define MT6389_DEW_CIPHER_SWRST (MT6389_PMIC_REG_BASE+0x422)
+#define MT6389_DEW_RDDMY_NO (MT6389_PMIC_REG_BASE+0x424)
+#define MT6389_RG_SPI_CON2 (MT6389_PMIC_REG_BASE+0x426)
+#define MT6389_RECORD_CMD0 (MT6389_PMIC_REG_BASE+0x428)
+#define MT6389_RECORD_CMD1 (MT6389_PMIC_REG_BASE+0x42a)
+#define MT6389_RECORD_CMD2 (MT6389_PMIC_REG_BASE+0x42c)
+#define MT6389_RECORD_CMD3 (MT6389_PMIC_REG_BASE+0x42e)
+#define MT6389_RECORD_CMD4 (MT6389_PMIC_REG_BASE+0x430)
+#define MT6389_RECORD_CMD5 (MT6389_PMIC_REG_BASE+0x432)
+#define MT6389_RECORD_WDATA0 (MT6389_PMIC_REG_BASE+0x434)
+#define MT6389_RECORD_WDATA1 (MT6389_PMIC_REG_BASE+0x436)
+#define MT6389_RECORD_WDATA2 (MT6389_PMIC_REG_BASE+0x438)
+#define MT6389_RECORD_WDATA3 (MT6389_PMIC_REG_BASE+0x43a)
+#define MT6389_RECORD_WDATA4 (MT6389_PMIC_REG_BASE+0x43c)
+#define MT6389_RECORD_WDATA5 (MT6389_PMIC_REG_BASE+0x43e)
+#define MT6389_RG_SPI_CON9 (MT6389_PMIC_REG_BASE+0x440)
+#define MT6389_RG_SPI_CON10 (MT6389_PMIC_REG_BASE+0x442)
+#define MT6389_RG_SPI_CON11 (MT6389_PMIC_REG_BASE+0x444)
+#define MT6389_RG_SPI_CON12 (MT6389_PMIC_REG_BASE+0x446)
+#define MT6389_RG_SPI_CON13 (MT6389_PMIC_REG_BASE+0x448)
+#define MT6389_SPISLV_KEY (MT6389_PMIC_REG_BASE+0x44a)
+#define MT6389_INT_TYPE_CON0 (MT6389_PMIC_REG_BASE+0x44c)
+#define MT6389_INT_TYPE_CON0_SET (MT6389_PMIC_REG_BASE+0x44e)
+#define MT6389_INT_TYPE_CON0_CLR (MT6389_PMIC_REG_BASE+0x450)
+#define MT6389_INT_STA (MT6389_PMIC_REG_BASE+0x452)
+#define MT6389_RG_SPI_CON1 (MT6389_PMIC_REG_BASE+0x454)
+#define MT6389_TOP_SPI_CON0 (MT6389_PMIC_REG_BASE+0x456)
+#define MT6389_TOP_SPI_CON1 (MT6389_PMIC_REG_BASE+0x458)
+#define MT6389_SCK_TOP_DSN_ID (MT6389_PMIC_REG_BASE+0x500)
+#define MT6389_SCK_TOP_DSN_REV0 (MT6389_PMIC_REG_BASE+0x502)
+#define MT6389_SCK_TOP_DBI (MT6389_PMIC_REG_BASE+0x504)
+#define MT6389_SCK_TOP_DXI (MT6389_PMIC_REG_BASE+0x506)
+#define MT6389_SCK_TOP_TPM0 (MT6389_PMIC_REG_BASE+0x508)
+#define MT6389_SCK_TOP_TPM1 (MT6389_PMIC_REG_BASE+0x50a)
+#define MT6389_SCK_TOP_CON0 (MT6389_PMIC_REG_BASE+0x50c)
+#define MT6389_SCK_TOP_CON1 (MT6389_PMIC_REG_BASE+0x50e)
+#define MT6389_SCK_TOP_TEST_OUT (MT6389_PMIC_REG_BASE+0x510)
+#define MT6389_SCK_TOP_TEST_CON0 (MT6389_PMIC_REG_BASE+0x512)
+#define MT6389_SCK_TOP_CKPDN_CON0 (MT6389_PMIC_REG_BASE+0x514)
+#define MT6389_SCK_TOP_CKPDN_CON0_SET (MT6389_PMIC_REG_BASE+0x516)
+#define MT6389_SCK_TOP_CKPDN_CON0_CLR (MT6389_PMIC_REG_BASE+0x518)
+#define MT6389_SCK_TOP_CKHWEN_CON0 (MT6389_PMIC_REG_BASE+0x51a)
+#define MT6389_SCK_TOP_CKHWEN_CON0_SET (MT6389_PMIC_REG_BASE+0x51c)
+#define MT6389_SCK_TOP_CKHWEN_CON0_CLR (MT6389_PMIC_REG_BASE+0x51e)
+#define MT6389_SCK_TOP_CKTST_CON (MT6389_PMIC_REG_BASE+0x520)
+#define MT6389_SCK_TOP_RST_CON0 (MT6389_PMIC_REG_BASE+0x522)
+#define MT6389_SCK_TOP_RST_CON0_SET (MT6389_PMIC_REG_BASE+0x524)
+#define MT6389_SCK_TOP_RST_CON0_CLR (MT6389_PMIC_REG_BASE+0x526)
+#define MT6389_SCK_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x528)
+#define MT6389_SCK_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x52a)
+#define MT6389_SCK_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x52c)
+#define MT6389_SCK_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x52e)
+#define MT6389_SCK_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x530)
+#define MT6389_SCK_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x532)
+#define MT6389_SCK_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x534)
+#define MT6389_SCK_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x536)
+#define MT6389_SCK_TOP_INT_MISC_CON (MT6389_PMIC_REG_BASE+0x538)
+#define MT6389_EOSC_CALI_CON0 (MT6389_PMIC_REG_BASE+0x53a)
+#define MT6389_EOSC_CALI_CON1 (MT6389_PMIC_REG_BASE+0x53c)
+#define MT6389_RTC_MIX_CON0 (MT6389_PMIC_REG_BASE+0x53e)
+#define MT6389_RTC_MIX_CON1 (MT6389_PMIC_REG_BASE+0x540)
+#define MT6389_RTC_MIX_CON2 (MT6389_PMIC_REG_BASE+0x542)
+#define MT6389_RTC_DIG_CON0 (MT6389_PMIC_REG_BASE+0x544)
+#define MT6389_FQMTR_CON0 (MT6389_PMIC_REG_BASE+0x546)
+#define MT6389_FQMTR_CON1 (MT6389_PMIC_REG_BASE+0x548)
+#define MT6389_FQMTR_CON2 (MT6389_PMIC_REG_BASE+0x54a)
+#define MT6389_XO_BUF_CTL0 (MT6389_PMIC_REG_BASE+0x54c)
+#define MT6389_XO_BUF_CTL1 (MT6389_PMIC_REG_BASE+0x54e)
+#define MT6389_XO_BUF_CTL2 (MT6389_PMIC_REG_BASE+0x550)
+#define MT6389_XO_BUF_CTL3 (MT6389_PMIC_REG_BASE+0x552)
+#define MT6389_XO_BUF_CTL4 (MT6389_PMIC_REG_BASE+0x554)
+#define MT6389_XO_CONN_BT0 (MT6389_PMIC_REG_BASE+0x556)
+#define MT6389_RTC_DSN_ID (MT6389_PMIC_REG_BASE+0x580)
+#define MT6389_RTC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x582)
+#define MT6389_RTC_DBI (MT6389_PMIC_REG_BASE+0x584)
+#define MT6389_RTC_DXI (MT6389_PMIC_REG_BASE+0x586)
+#define MT6389_RTC_BBPU (MT6389_PMIC_REG_BASE+0x588)
+#define MT6389_RTC_IRQ_STA (MT6389_PMIC_REG_BASE+0x58a)
+#define MT6389_RTC_IRQ_EN (MT6389_PMIC_REG_BASE+0x58c)
+#define MT6389_RTC_CII_EN (MT6389_PMIC_REG_BASE+0x58e)
+#define MT6389_RTC_AL_MASK (MT6389_PMIC_REG_BASE+0x590)
+#define MT6389_RTC_TC_SEC (MT6389_PMIC_REG_BASE+0x592)
+#define MT6389_RTC_TC_MIN (MT6389_PMIC_REG_BASE+0x594)
+#define MT6389_RTC_TC_HOU (MT6389_PMIC_REG_BASE+0x596)
+#define MT6389_RTC_TC_DOM (MT6389_PMIC_REG_BASE+0x598)
+#define MT6389_RTC_TC_DOW (MT6389_PMIC_REG_BASE+0x59a)
+#define MT6389_RTC_TC_MTH (MT6389_PMIC_REG_BASE+0x59c)
+#define MT6389_RTC_TC_YEA (MT6389_PMIC_REG_BASE+0x59e)
+#define MT6389_RTC_AL_SEC (MT6389_PMIC_REG_BASE+0x5a0)
+#define MT6389_RTC_AL_MIN (MT6389_PMIC_REG_BASE+0x5a2)
+#define MT6389_RTC_AL_HOU (MT6389_PMIC_REG_BASE+0x5a4)
+#define MT6389_RTC_AL_DOM (MT6389_PMIC_REG_BASE+0x5a6)
+#define MT6389_RTC_AL_DOW (MT6389_PMIC_REG_BASE+0x5a8)
+#define MT6389_RTC_AL_MTH (MT6389_PMIC_REG_BASE+0x5aa)
+#define MT6389_RTC_AL_YEA (MT6389_PMIC_REG_BASE+0x5ac)
+#define MT6389_RTC_OSC32CON (MT6389_PMIC_REG_BASE+0x5ae)
+#define MT6389_RTC_POWERKEY1 (MT6389_PMIC_REG_BASE+0x5b0)
+#define MT6389_RTC_POWERKEY2 (MT6389_PMIC_REG_BASE+0x5b2)
+#define MT6389_RTC_PDN1 (MT6389_PMIC_REG_BASE+0x5b4)
+#define MT6389_RTC_PDN2 (MT6389_PMIC_REG_BASE+0x5b6)
+#define MT6389_RTC_SPAR0 (MT6389_PMIC_REG_BASE+0x5b8)
+#define MT6389_RTC_SPAR1 (MT6389_PMIC_REG_BASE+0x5ba)
+#define MT6389_RTC_PROT (MT6389_PMIC_REG_BASE+0x5bc)
+#define MT6389_RTC_DIFF (MT6389_PMIC_REG_BASE+0x5be)
+#define MT6389_RTC_CALI (MT6389_PMIC_REG_BASE+0x5c0)
+#define MT6389_RTC_WRTGR (MT6389_PMIC_REG_BASE+0x5c2)
+#define MT6389_RTC_CON (MT6389_PMIC_REG_BASE+0x5c4)
+#define MT6389_RTC_SEC_CTRL (MT6389_PMIC_REG_BASE+0x5c6)
+#define MT6389_RTC_INT_CNT (MT6389_PMIC_REG_BASE+0x5c8)
+#define MT6389_RTC_SEC_DAT0 (MT6389_PMIC_REG_BASE+0x5ca)
+#define MT6389_RTC_SEC_DAT1 (MT6389_PMIC_REG_BASE+0x5cc)
+#define MT6389_RTC_SEC_DAT2 (MT6389_PMIC_REG_BASE+0x5ce)
+#define MT6389_RTC_SEC_DSN_ID (MT6389_PMIC_REG_BASE+0x600)
+#define MT6389_RTC_SEC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x602)
+#define MT6389_RTC_SEC_DBI (MT6389_PMIC_REG_BASE+0x604)
+#define MT6389_RTC_SEC_DXI (MT6389_PMIC_REG_BASE+0x606)
+#define MT6389_RTC_TC_SEC_SEC (MT6389_PMIC_REG_BASE+0x608)
+#define MT6389_RTC_TC_MIN_SEC (MT6389_PMIC_REG_BASE+0x60a)
+#define MT6389_RTC_TC_HOU_SEC (MT6389_PMIC_REG_BASE+0x60c)
+#define MT6389_RTC_TC_DOM_SEC (MT6389_PMIC_REG_BASE+0x60e)
+#define MT6389_RTC_TC_DOW_SEC (MT6389_PMIC_REG_BASE+0x610)
+#define MT6389_RTC_TC_MTH_SEC (MT6389_PMIC_REG_BASE+0x612)
+#define MT6389_RTC_TC_YEA_SEC (MT6389_PMIC_REG_BASE+0x614)
+#define MT6389_RTC_SEC_CK_PDN (MT6389_PMIC_REG_BASE+0x616)
+#define MT6389_RTC_SEC_WRTGR (MT6389_PMIC_REG_BASE+0x618)
+#define MT6389_DCXO_DSN_ID (MT6389_PMIC_REG_BASE+0x780)
+#define MT6389_DCXO_DSN_REV0 (MT6389_PMIC_REG_BASE+0x782)
+#define MT6389_DCXO_DSN_DBI (MT6389_PMIC_REG_BASE+0x784)
+#define MT6389_DCXO_DSN_DXI (MT6389_PMIC_REG_BASE+0x786)
+#define MT6389_DCXO_CW00 (MT6389_PMIC_REG_BASE+0x788)
+#define MT6389_DCXO_CW00_SET (MT6389_PMIC_REG_BASE+0x78a)
+#define MT6389_DCXO_CW00_CLR (MT6389_PMIC_REG_BASE+0x78c)
+#define MT6389_DCXO_CW01 (MT6389_PMIC_REG_BASE+0x78e)
+#define MT6389_DCXO_CW02 (MT6389_PMIC_REG_BASE+0x790)
+#define MT6389_DCXO_CW03 (MT6389_PMIC_REG_BASE+0x792)
+#define MT6389_DCXO_CW04 (MT6389_PMIC_REG_BASE+0x794)
+#define MT6389_DCXO_CW05 (MT6389_PMIC_REG_BASE+0x796)
+#define MT6389_DCXO_CW06 (MT6389_PMIC_REG_BASE+0x798)
+#define MT6389_DCXO_CW07 (MT6389_PMIC_REG_BASE+0x79a)
+#define MT6389_DCXO_CW08 (MT6389_PMIC_REG_BASE+0x79c)
+#define MT6389_DCXO_CW09 (MT6389_PMIC_REG_BASE+0x79e)
+#define MT6389_DCXO_CW09_SET (MT6389_PMIC_REG_BASE+0x7a0)
+#define MT6389_DCXO_CW09_CLR (MT6389_PMIC_REG_BASE+0x7a2)
+#define MT6389_DCXO_CW10 (MT6389_PMIC_REG_BASE+0x7a4)
+#define MT6389_DCXO_CW11 (MT6389_PMIC_REG_BASE+0x7a6)
+#define MT6389_DCXO_CW12 (MT6389_PMIC_REG_BASE+0x7a8)
+#define MT6389_DCXO_CW13 (MT6389_PMIC_REG_BASE+0x7aa)
+#define MT6389_DCXO_CW14 (MT6389_PMIC_REG_BASE+0x7ac)
+#define MT6389_DCXO_CW15 (MT6389_PMIC_REG_BASE+0x7ae)
+#define MT6389_DCXO_CW16 (MT6389_PMIC_REG_BASE+0x7b0)
+#define MT6389_DCXO_CW17 (MT6389_PMIC_REG_BASE+0x7b2)
+#define MT6389_DCXO_CW18 (MT6389_PMIC_REG_BASE+0x7b4)
+#define MT6389_DCXO_CW19 (MT6389_PMIC_REG_BASE+0x7b6)
+#define MT6389_DCXO_ELR_NUM (MT6389_PMIC_REG_BASE+0x7b8)
+#define MT6389_DCXO_ELR0 (MT6389_PMIC_REG_BASE+0x7ba)
+#define MT6389_PSC_TOP_ID (MT6389_PMIC_REG_BASE+0x900)
+#define MT6389_PSC_TOP_REV0 (MT6389_PMIC_REG_BASE+0x902)
+#define MT6389_PSC_TOP_DBI (MT6389_PMIC_REG_BASE+0x904)
+#define MT6389_PSC_TOP_DXI (MT6389_PMIC_REG_BASE+0x906)
+#define MT6389_PSC_TPM0 (MT6389_PMIC_REG_BASE+0x908)
+#define MT6389_PSC_TPM1 (MT6389_PMIC_REG_BASE+0x90a)
+#define MT6389_PSC_TOP_CLKCTL_0 (MT6389_PMIC_REG_BASE+0x90c)
+#define MT6389_PSC_TOP_RSTCTL_0 (MT6389_PMIC_REG_BASE+0x90e)
+#define MT6389_PSC_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x910)
+#define MT6389_PSC_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x912)
+#define MT6389_PSC_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x914)
+#define MT6389_PSC_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x916)
+#define MT6389_PSC_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x918)
+#define MT6389_PSC_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x91a)
+#define MT6389_PSC_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x91c)
+#define MT6389_PSC_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x91e)
+#define MT6389_PSC_TOP_INT_MISC_CON (MT6389_PMIC_REG_BASE+0x920)
+#define MT6389_PSC_TOP_INT_MISC_CON_SET (MT6389_PMIC_REG_BASE+0x922)
+#define MT6389_PSC_TOP_INT_MISC_CON_CLR (MT6389_PMIC_REG_BASE+0x924)
+#define MT6389_PSC_TOP_MON_CTL (MT6389_PMIC_REG_BASE+0x926)
+#define MT6389_PSC_KEY_CTL (MT6389_PMIC_REG_BASE+0x928)
+#define MT6389_STRUP_ID (MT6389_PMIC_REG_BASE+0x980)
+#define MT6389_STRUP_REV0 (MT6389_PMIC_REG_BASE+0x982)
+#define MT6389_STRUP_DBI (MT6389_PMIC_REG_BASE+0x984)
+#define MT6389_STRUP_DSN_FPI (MT6389_PMIC_REG_BASE+0x986)
+#define MT6389_STRUP_ANA_CON0 (MT6389_PMIC_REG_BASE+0x988)
+#define MT6389_STRUP_ANA_CON1 (MT6389_PMIC_REG_BASE+0x98a)
+#define MT6389_STRUP_ANA_CON2 (MT6389_PMIC_REG_BASE+0x98c)
+#define MT6389_STRUP_ANA_CON3 (MT6389_PMIC_REG_BASE+0x98e)
+#define MT6389_STRUP_ANA_CON4 (MT6389_PMIC_REG_BASE+0x990)
+#define MT6389_STRUP_ELR_NUM (MT6389_PMIC_REG_BASE+0x992)
+#define MT6389_STRUP_ELR_0 (MT6389_PMIC_REG_BASE+0x994)
+#define MT6389_STRUP_ELR_1 (MT6389_PMIC_REG_BASE+0x996)
+#define MT6389_STRUP_ELR_2 (MT6389_PMIC_REG_BASE+0x998)
+#define MT6389_STRUP_ELR_3 (MT6389_PMIC_REG_BASE+0x99a)
+#define MT6389_STRUP_ELR_4 (MT6389_PMIC_REG_BASE+0x99c)
+#define MT6389_PSEQ_ID (MT6389_PMIC_REG_BASE+0xa00)
+#define MT6389_PSEQ_REV0 (MT6389_PMIC_REG_BASE+0xa02)
+#define MT6389_PSEQ_DBI (MT6389_PMIC_REG_BASE+0xa04)
+#define MT6389_PSEQ_DXI (MT6389_PMIC_REG_BASE+0xa06)
+#define MT6389_PPCCTL0 (MT6389_PMIC_REG_BASE+0xa08)
+#define MT6389_PPCCTL1 (MT6389_PMIC_REG_BASE+0xa0a)
+#define MT6389_PPCCFG0 (MT6389_PMIC_REG_BASE+0xa0c)
+#define MT6389_STRUP_CON9 (MT6389_PMIC_REG_BASE+0xa0e)
+#define MT6389_STRUP_CON11 (MT6389_PMIC_REG_BASE+0xa10)
+#define MT6389_STRUP_CON12 (MT6389_PMIC_REG_BASE+0xa12)
+#define MT6389_PORFLAG (MT6389_PMIC_REG_BASE+0xa14)
+#define MT6389_STRUP_CON4 (MT6389_PMIC_REG_BASE+0xa16)
+#define MT6389_STRUP_CON1 (MT6389_PMIC_REG_BASE+0xa18)
+#define MT6389_STRUP_CON2 (MT6389_PMIC_REG_BASE+0xa1a)
+#define MT6389_STRUP_CON5 (MT6389_PMIC_REG_BASE+0xa1c)
+#define MT6389_STRUP_CON19 (MT6389_PMIC_REG_BASE+0xa1e)
+#define MT6389_STRUP_PGDEB0 (MT6389_PMIC_REG_BASE+0xa20)
+#define MT6389_STRUP_PGDEB1 (MT6389_PMIC_REG_BASE+0xa22)
+#define MT6389_STRUP_PGENB0 (MT6389_PMIC_REG_BASE+0xa24)
+#define MT6389_STRUP_PGENB1 (MT6389_PMIC_REG_BASE+0xa26)
+#define MT6389_STRUP_OCENB0 (MT6389_PMIC_REG_BASE+0xa28)
+#define MT6389_STRUP_OCENB1 (MT6389_PMIC_REG_BASE+0xa2a)
+#define MT6389_PPCTST0 (MT6389_PMIC_REG_BASE+0xa2c)
+#define MT6389_PPCCTL2 (MT6389_PMIC_REG_BASE+0xa2e)
+#define MT6389_STRUP_CON10 (MT6389_PMIC_REG_BASE+0xa30)
+#define MT6389_STRUP_CON3 (MT6389_PMIC_REG_BASE+0xa32)
+#define MT6389_STRUP_CON6 (MT6389_PMIC_REG_BASE+0xa34)
+#define MT6389_TPO_CON0 (MT6389_PMIC_REG_BASE+0xa36)
+#define MT6389_TPO_CON1 (MT6389_PMIC_REG_BASE+0xa38)
+#define MT6389_TPO_CON2 (MT6389_PMIC_REG_BASE+0xa3a)
+#define MT6389_CPSWKEY (MT6389_PMIC_REG_BASE+0xa3c)
+#define MT6389_CPSCFG0 (MT6389_PMIC_REG_BASE+0xa3e)
+#define MT6389_CPSDSA0 (MT6389_PMIC_REG_BASE+0xa40)
+#define MT6389_CPSDSA1 (MT6389_PMIC_REG_BASE+0xa42)
+#define MT6389_CPSDSA2 (MT6389_PMIC_REG_BASE+0xa44)
+#define MT6389_CPSDSA3 (MT6389_PMIC_REG_BASE+0xa46)
+#define MT6389_CPSDSA4 (MT6389_PMIC_REG_BASE+0xa48)
+#define MT6389_CPSDSA5 (MT6389_PMIC_REG_BASE+0xa4a)
+#define MT6389_CPSDSA6 (MT6389_PMIC_REG_BASE+0xa4c)
+#define MT6389_PSEQ_ELR_NUM (MT6389_PMIC_REG_BASE+0xa4e)
+#define MT6389_PSEQ_ELR0 (MT6389_PMIC_REG_BASE+0xa50)
+#define MT6389_PSEQ_ELR1 (MT6389_PMIC_REG_BASE+0xa52)
+#define MT6389_PSEQ_ELR2 (MT6389_PMIC_REG_BASE+0xa54)
+#define MT6389_PSEQ_ELR3 (MT6389_PMIC_REG_BASE+0xa56)
+#define MT6389_CPSUSA_ELR0 (MT6389_PMIC_REG_BASE+0xa58)
+#define MT6389_CPSUSA_ELR1 (MT6389_PMIC_REG_BASE+0xa5a)
+#define MT6389_CPSUSA_ELR2 (MT6389_PMIC_REG_BASE+0xa5c)
+#define MT6389_CPSUSA_ELR3 (MT6389_PMIC_REG_BASE+0xa5e)
+#define MT6389_CPSUSA_ELR4 (MT6389_PMIC_REG_BASE+0xa60)
+#define MT6389_CPSUSA_ELR5 (MT6389_PMIC_REG_BASE+0xa62)
+#define MT6389_CPSUSA_ELR6 (MT6389_PMIC_REG_BASE+0xa64)
+#define MT6389_CHRDET_ID (MT6389_PMIC_REG_BASE+0xa80)
+#define MT6389_CHRDET_REV0 (MT6389_PMIC_REG_BASE+0xa82)
+#define MT6389_CHRDET_DBI (MT6389_PMIC_REG_BASE+0xa84)
+#define MT6389_CHRDET_DXI (MT6389_PMIC_REG_BASE+0xa86)
+#define MT6389_PCHR_VREF_ANA_CON0 (MT6389_PMIC_REG_BASE+0xa88)
+#define MT6389_PCHR_VREF_ANA_CON1 (MT6389_PMIC_REG_BASE+0xa8a)
+#define MT6389_PCHR_VREF_ANA_CON2 (MT6389_PMIC_REG_BASE+0xa8c)
+#define MT6389_PCHR_VREF_ANA_CON3 (MT6389_PMIC_REG_BASE+0xa8e)
+#define MT6389_PCHR_VREF_ELR_NUM (MT6389_PMIC_REG_BASE+0xa90)
+#define MT6389_PCHR_VREF_ELR_0 (MT6389_PMIC_REG_BASE+0xa92)
+#define MT6389_PCHR_VREF_ELR_1 (MT6389_PMIC_REG_BASE+0xa94)
+#define MT6389_HK_TOP_ID (MT6389_PMIC_REG_BASE+0xf80)
+#define MT6389_HK_TOP_REV0 (MT6389_PMIC_REG_BASE+0xf82)
+#define MT6389_HK_TOP_DBI (MT6389_PMIC_REG_BASE+0xf84)
+#define MT6389_HK_TOP_DXI (MT6389_PMIC_REG_BASE+0xf86)
+#define MT6389_HK_TPM0 (MT6389_PMIC_REG_BASE+0xf88)
+#define MT6389_HK_TPM1 (MT6389_PMIC_REG_BASE+0xf8a)
+#define MT6389_HK_TOP_CLK_CON0 (MT6389_PMIC_REG_BASE+0xf8c)
+#define MT6389_HK_TOP_CLK_CON1 (MT6389_PMIC_REG_BASE+0xf8e)
+#define MT6389_HK_TOP_RST_CON0 (MT6389_PMIC_REG_BASE+0xf90)
+#define MT6389_HK_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0xf92)
+#define MT6389_HK_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0xf94)
+#define MT6389_HK_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0xf96)
+#define MT6389_HK_TOP_INT_CON1 (MT6389_PMIC_REG_BASE+0xf98)
+#define MT6389_HK_TOP_INT_CON1_SET (MT6389_PMIC_REG_BASE+0xf9a)
+#define MT6389_HK_TOP_INT_CON1_CLR (MT6389_PMIC_REG_BASE+0xf9c)
+#define MT6389_HK_TOP_INT_CON2 (MT6389_PMIC_REG_BASE+0xf9e)
+#define MT6389_HK_TOP_INT_CON2_SET (MT6389_PMIC_REG_BASE+0xfa0)
+#define MT6389_HK_TOP_INT_CON2_CLR (MT6389_PMIC_REG_BASE+0xfa2)
+#define MT6389_HK_TOP_INT_CON3 (MT6389_PMIC_REG_BASE+0xfa4)
+#define MT6389_HK_TOP_INT_CON3_SET (MT6389_PMIC_REG_BASE+0xfa6)
+#define MT6389_HK_TOP_INT_CON3_CLR (MT6389_PMIC_REG_BASE+0xfa8)
+#define MT6389_HK_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0xfaa)
+#define MT6389_HK_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0xfac)
+#define MT6389_HK_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0xfae)
+#define MT6389_HK_TOP_INT_MASK_CON1 (MT6389_PMIC_REG_BASE+0xfb0)
+#define MT6389_HK_TOP_INT_MASK_CON1_SET (MT6389_PMIC_REG_BASE+0xfb2)
+#define MT6389_HK_TOP_INT_MASK_CON1_CLR (MT6389_PMIC_REG_BASE+0xfb4)
+#define MT6389_HK_TOP_INT_MASK_CON2 (MT6389_PMIC_REG_BASE+0xfb6)
+#define MT6389_HK_TOP_INT_MASK_CON2_SET (MT6389_PMIC_REG_BASE+0xfb8)
+#define MT6389_HK_TOP_INT_MASK_CON2_CLR (MT6389_PMIC_REG_BASE+0xfba)
+#define MT6389_HK_TOP_INT_MASK_CON3 (MT6389_PMIC_REG_BASE+0xfbc)
+#define MT6389_HK_TOP_INT_MASK_CON3_SET (MT6389_PMIC_REG_BASE+0xfbe)
+#define MT6389_HK_TOP_INT_MASK_CON3_CLR (MT6389_PMIC_REG_BASE+0xfc0)
+#define MT6389_HK_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0xfc2)
+#define MT6389_HK_TOP_INT_STATUS1 (MT6389_PMIC_REG_BASE+0xfc4)
+#define MT6389_HK_TOP_INT_STATUS2 (MT6389_PMIC_REG_BASE+0xfc6)
+#define MT6389_HK_TOP_INT_STATUS3 (MT6389_PMIC_REG_BASE+0xfc8)
+#define MT6389_HK_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0xfca)
+#define MT6389_HK_TOP_INT_RAW_STATUS1 (MT6389_PMIC_REG_BASE+0xfcc)
+#define MT6389_HK_TOP_INT_RAW_STATUS2 (MT6389_PMIC_REG_BASE+0xfce)
+#define MT6389_HK_TOP_INT_RAW_STATUS3 (MT6389_PMIC_REG_BASE+0xfd0)
+#define MT6389_HK_TOP_MON_CON0 (MT6389_PMIC_REG_BASE+0xfd2)
+#define MT6389_HK_TOP_MON_CON1 (MT6389_PMIC_REG_BASE+0xfd4)
+#define MT6389_HK_TOP_MON_CON2 (MT6389_PMIC_REG_BASE+0xfd6)
+#define MT6389_HK_TOP_CHR_CON (MT6389_PMIC_REG_BASE+0xfd8)
+#define MT6389_HK_TOP_ANA_CON (MT6389_PMIC_REG_BASE+0xfda)
+#define MT6389_HK_TOP_AUXADC_ANA (MT6389_PMIC_REG_BASE+0xfdc)
+#define MT6389_HK_TOP_STRUP (MT6389_PMIC_REG_BASE+0xfde)
+#define MT6389_HK_TOP_LDO_CON (MT6389_PMIC_REG_BASE+0xfe0)
+#define MT6389_HK_TOP_LDO_STATUS (MT6389_PMIC_REG_BASE+0xfe2)
+#define MT6389_HK_TOP_WKEY (MT6389_PMIC_REG_BASE+0xfe4)
+#define MT6389_AUXADC_DSN_ID (MT6389_PMIC_REG_BASE+0x1000)
+#define MT6389_AUXADC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1002)
+#define MT6389_AUXADC_DSN_DBI (MT6389_PMIC_REG_BASE+0x1004)
+#define MT6389_AUXADC_DSN_FPI (MT6389_PMIC_REG_BASE+0x1006)
+#define MT6389_AUXADC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1008)
+#define MT6389_AUXADC_ANA_CON1 (MT6389_PMIC_REG_BASE+0x100a)
+#define MT6389_AUXADC_DIG_1_DSN_ID (MT6389_PMIC_REG_BASE+0x1080)
+#define MT6389_AUXADC_DIG_1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1082)
+#define MT6389_AUXADC_DIG_1_DSN_DBI (MT6389_PMIC_REG_BASE+0x1084)
+#define MT6389_AUXADC_DIG_1_DSN_DXI (MT6389_PMIC_REG_BASE+0x1086)
+#define MT6389_AUXADC_ADC0 (MT6389_PMIC_REG_BASE+0x1088)
+#define MT6389_AUXADC_ADC1 (MT6389_PMIC_REG_BASE+0x108a)
+#define MT6389_AUXADC_ADC2 (MT6389_PMIC_REG_BASE+0x108c)
+#define MT6389_AUXADC_ADC3 (MT6389_PMIC_REG_BASE+0x108e)
+#define MT6389_AUXADC_ADC4 (MT6389_PMIC_REG_BASE+0x1090)
+#define MT6389_AUXADC_ADC5 (MT6389_PMIC_REG_BASE+0x1092)
+#define MT6389_AUXADC_ADC6 (MT6389_PMIC_REG_BASE+0x1094)
+#define MT6389_AUXADC_ADC7 (MT6389_PMIC_REG_BASE+0x1096)
+#define MT6389_AUXADC_ADC8 (MT6389_PMIC_REG_BASE+0x1098)
+#define MT6389_AUXADC_ADC9 (MT6389_PMIC_REG_BASE+0x109a)
+#define MT6389_AUXADC_ADC10 (MT6389_PMIC_REG_BASE+0x109c)
+#define MT6389_AUXADC_ADC11 (MT6389_PMIC_REG_BASE+0x109e)
+#define MT6389_AUXADC_ADC14 (MT6389_PMIC_REG_BASE+0x10a0)
+#define MT6389_AUXADC_ADC15 (MT6389_PMIC_REG_BASE+0x10a2)
+#define MT6389_AUXADC_ADC16 (MT6389_PMIC_REG_BASE+0x10a4)
+#define MT6389_AUXADC_ADC17 (MT6389_PMIC_REG_BASE+0x10a6)
+#define MT6389_AUXADC_ADC18 (MT6389_PMIC_REG_BASE+0x10a8)
+#define MT6389_AUXADC_ADC19 (MT6389_PMIC_REG_BASE+0x10aa)
+#define MT6389_AUXADC_ADC20 (MT6389_PMIC_REG_BASE+0x10ac)
+#define MT6389_AUXADC_ADC21 (MT6389_PMIC_REG_BASE+0x10ae)
+#define MT6389_AUXADC_ADC22 (MT6389_PMIC_REG_BASE+0x10b0)
+#define MT6389_AUXADC_ADC23 (MT6389_PMIC_REG_BASE+0x10b2)
+#define MT6389_AUXADC_ADC24 (MT6389_PMIC_REG_BASE+0x10b4)
+#define MT6389_AUXADC_ADC26 (MT6389_PMIC_REG_BASE+0x10b6)
+#define MT6389_AUXADC_ADC27 (MT6389_PMIC_REG_BASE+0x10b8)
+#define MT6389_AUXADC_ADC30 (MT6389_PMIC_REG_BASE+0x10ba)
+#define MT6389_AUXADC_ADC32 (MT6389_PMIC_REG_BASE+0x10bc)
+#define MT6389_AUXADC_ADC33 (MT6389_PMIC_REG_BASE+0x10be)
+#define MT6389_AUXADC_ADC34 (MT6389_PMIC_REG_BASE+0x10c0)
+#define MT6389_AUXADC_ADC37 (MT6389_PMIC_REG_BASE+0x10c2)
+#define MT6389_AUXADC_ADC38 (MT6389_PMIC_REG_BASE+0x10c4)
+#define MT6389_AUXADC_ADC39 (MT6389_PMIC_REG_BASE+0x10c6)
+#define MT6389_AUXADC_ADC40 (MT6389_PMIC_REG_BASE+0x10c8)
+#define MT6389_AUXADC_ADC41 (MT6389_PMIC_REG_BASE+0x10ca)
+#define MT6389_AUXADC_ADC42 (MT6389_PMIC_REG_BASE+0x10cc)
+#define MT6389_AUXADC_ADC43 (MT6389_PMIC_REG_BASE+0x10ce)
+#define MT6389_AUXADC_ADC44 (MT6389_PMIC_REG_BASE+0x10d0)
+#define MT6389_AUXADC_STA0 (MT6389_PMIC_REG_BASE+0x10d2)
+#define MT6389_AUXADC_STA1 (MT6389_PMIC_REG_BASE+0x10d4)
+#define MT6389_AUXADC_STA2 (MT6389_PMIC_REG_BASE+0x10d6)
+#define MT6389_AUXADC_SPL_LIST_0 (MT6389_PMIC_REG_BASE+0x10d8)
+#define MT6389_AUXADC_SPL_LIST_1 (MT6389_PMIC_REG_BASE+0x10da)
+#define MT6389_AUXADC_SPL_LIST_2 (MT6389_PMIC_REG_BASE+0x10dc)
+#define MT6389_AUXADC_SPL_LIST_3 (MT6389_PMIC_REG_BASE+0x10de)
+#define MT6389_AUXADC_SPL_LIST_4 (MT6389_PMIC_REG_BASE+0x10e0)
+#define MT6389_AUXADC_DIG_2_DSN_ID (MT6389_PMIC_REG_BASE+0x1100)
+#define MT6389_AUXADC_DIG_2_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1102)
+#define MT6389_AUXADC_DIG_2_DSN_DBI (MT6389_PMIC_REG_BASE+0x1104)
+#define MT6389_AUXADC_DIG_2_DSN_DXI (MT6389_PMIC_REG_BASE+0x1106)
+#define MT6389_AUXADC_RQST0 (MT6389_PMIC_REG_BASE+0x1108)
+#define MT6389_AUXADC_RQST1 (MT6389_PMIC_REG_BASE+0x110a)
+#define MT6389_AUXADC_RQST2 (MT6389_PMIC_REG_BASE+0x110c)
+#define MT6389_AUXADC_RQST3 (MT6389_PMIC_REG_BASE+0x110e)
+#define MT6389_AUXADC_RQST4 (MT6389_PMIC_REG_BASE+0x1110)
+#define MT6389_AUXADC_DIG_3_DSN_ID (MT6389_PMIC_REG_BASE+0x1180)
+#define MT6389_AUXADC_DIG_3_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1182)
+#define MT6389_AUXADC_DIG_3_DSN_DBI (MT6389_PMIC_REG_BASE+0x1184)
+#define MT6389_AUXADC_DIG_3_DSN_DXI (MT6389_PMIC_REG_BASE+0x1186)
+#define MT6389_AUXADC_CON0 (MT6389_PMIC_REG_BASE+0x1188)
+#define MT6389_AUXADC_CON0_SET (MT6389_PMIC_REG_BASE+0x118a)
+#define MT6389_AUXADC_CON0_CLR (MT6389_PMIC_REG_BASE+0x118c)
+#define MT6389_AUXADC_CON1 (MT6389_PMIC_REG_BASE+0x118e)
+#define MT6389_AUXADC_CON2 (MT6389_PMIC_REG_BASE+0x1190)
+#define MT6389_AUXADC_CON3 (MT6389_PMIC_REG_BASE+0x1192)
+#define MT6389_AUXADC_CON4 (MT6389_PMIC_REG_BASE+0x1194)
+#define MT6389_AUXADC_CON5 (MT6389_PMIC_REG_BASE+0x1196)
+#define MT6389_AUXADC_CON6 (MT6389_PMIC_REG_BASE+0x1198)
+#define MT6389_AUXADC_CON7 (MT6389_PMIC_REG_BASE+0x119a)
+#define MT6389_AUXADC_CON8 (MT6389_PMIC_REG_BASE+0x119c)
+#define MT6389_AUXADC_CON9 (MT6389_PMIC_REG_BASE+0x119e)
+#define MT6389_AUXADC_CON10 (MT6389_PMIC_REG_BASE+0x11a0)
+#define MT6389_AUXADC_CON11 (MT6389_PMIC_REG_BASE+0x11a2)
+#define MT6389_AUXADC_CON12 (MT6389_PMIC_REG_BASE+0x11a4)
+#define MT6389_AUXADC_AVG_NUM0 (MT6389_PMIC_REG_BASE+0x11a6)
+#define MT6389_AUXADC_AVG_NUM1 (MT6389_PMIC_REG_BASE+0x11a8)
+#define MT6389_AUXADC_AVG_NUM2 (MT6389_PMIC_REG_BASE+0x11aa)
+#define MT6389_AUXADC_TRIM_SEL0 (MT6389_PMIC_REG_BASE+0x11ac)
+#define MT6389_AUXADC_TRIM_SEL1 (MT6389_PMIC_REG_BASE+0x11ae)
+#define MT6389_AUXADC_TRIM_SEL2 (MT6389_PMIC_REG_BASE+0x11b0)
+#define MT6389_AUXADC_TRIM_SEL3 (MT6389_PMIC_REG_BASE+0x11b2)
+#define MT6389_AUXADC_CON13 (MT6389_PMIC_REG_BASE+0x11b4)
+#define MT6389_AUXADC_CON14 (MT6389_PMIC_REG_BASE+0x11b6)
+#define MT6389_AUXADC_CON15 (MT6389_PMIC_REG_BASE+0x11b8)
+#define MT6389_AUXADC_CON16 (MT6389_PMIC_REG_BASE+0x11ba)
+#define MT6389_AUXADC_CON18 (MT6389_PMIC_REG_BASE+0x11bc)
+#define MT6389_AUXADC_CON19 (MT6389_PMIC_REG_BASE+0x11be)
+#define MT6389_AUXADC_CON20 (MT6389_PMIC_REG_BASE+0x11c0)
+#define MT6389_AUXADC_AUTORPT0 (MT6389_PMIC_REG_BASE+0x11c2)
+#define MT6389_AUXADC_ACCDET (MT6389_PMIC_REG_BASE+0x11c4)
+#define MT6389_AUXADC_DBG0 (MT6389_PMIC_REG_BASE+0x11c6)
+#define MT6389_AUXADC_DIG_3_ELR_NUM (MT6389_PMIC_REG_BASE+0x11c8)
+#define MT6389_AUXADC_DIG_3_ELR0 (MT6389_PMIC_REG_BASE+0x11ca)
+#define MT6389_AUXADC_DIG_3_ELR1 (MT6389_PMIC_REG_BASE+0x11cc)
+#define MT6389_AUXADC_DIG_3_ELR2 (MT6389_PMIC_REG_BASE+0x11ce)
+#define MT6389_AUXADC_DIG_3_ELR3 (MT6389_PMIC_REG_BASE+0x11d0)
+#define MT6389_AUXADC_DIG_3_ELR4 (MT6389_PMIC_REG_BASE+0x11d2)
+#define MT6389_AUXADC_DIG_3_ELR5 (MT6389_PMIC_REG_BASE+0x11d4)
+#define MT6389_AUXADC_DIG_3_ELR6 (MT6389_PMIC_REG_BASE+0x11d6)
+#define MT6389_AUXADC_DIG_3_ELR7 (MT6389_PMIC_REG_BASE+0x11d8)
+#define MT6389_AUXADC_DIG_3_ELR8 (MT6389_PMIC_REG_BASE+0x11da)
+#define MT6389_AUXADC_DIG_3_ELR9 (MT6389_PMIC_REG_BASE+0x11dc)
+#define MT6389_AUXADC_DIG_3_ELR10 (MT6389_PMIC_REG_BASE+0x11de)
+#define MT6389_AUXADC_DIG_3_ELR11 (MT6389_PMIC_REG_BASE+0x11e0)
+#define MT6389_AUXADC_DIG_3_ELR12 (MT6389_PMIC_REG_BASE+0x11e2)
+#define MT6389_AUXADC_DIG_3_ELR13 (MT6389_PMIC_REG_BASE+0x11e4)
+#define MT6389_AUXADC_DIG_3_ELR14 (MT6389_PMIC_REG_BASE+0x11e6)
+#define MT6389_AUXADC_DIG_3_ELR15 (MT6389_PMIC_REG_BASE+0x11e8)
+#define MT6389_AUXADC_DIG_3_ELR16 (MT6389_PMIC_REG_BASE+0x11ea)
+#define MT6389_AUXADC_DIG_3_ELR17 (MT6389_PMIC_REG_BASE+0x11ec)
+#define MT6389_AUXADC_DIG_3_ELR18 (MT6389_PMIC_REG_BASE+0x11ee)
+#define MT6389_AUXADC_DIG_3_ELR19 (MT6389_PMIC_REG_BASE+0x11f0)
+#define MT6389_AUXADC_DIG_3_ELR20 (MT6389_PMIC_REG_BASE+0x11f2)
+#define MT6389_AUXADC_DIG_3_ELR21 (MT6389_PMIC_REG_BASE+0x11f4)
+#define MT6389_AUXADC_DIG_3_ELR22 (MT6389_PMIC_REG_BASE+0x11f6)
+#define MT6389_AUXADC_DIG_3_ELR23 (MT6389_PMIC_REG_BASE+0x11f8)
+#define MT6389_AUXADC_DIG_3_ELR24 (MT6389_PMIC_REG_BASE+0x11fa)
+#define MT6389_AUXADC_DIG_3_ELR25 (MT6389_PMIC_REG_BASE+0x11fc)
+#define MT6389_AUXADC_DIG_3_ELR26 (MT6389_PMIC_REG_BASE+0x11fe)
+#define MT6389_AUXADC_DIG_4_DSN_ID (MT6389_PMIC_REG_BASE+0x1200)
+#define MT6389_AUXADC_DIG_4_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1202)
+#define MT6389_AUXADC_DIG_4_DSN_DBI (MT6389_PMIC_REG_BASE+0x1204)
+#define MT6389_AUXADC_DIG_4_DSN_DXI (MT6389_PMIC_REG_BASE+0x1206)
+#define MT6389_AUXADC_IMP0 (MT6389_PMIC_REG_BASE+0x1208)
+#define MT6389_AUXADC_IMP1 (MT6389_PMIC_REG_BASE+0x120a)
+#define MT6389_AUXADC_IMP2 (MT6389_PMIC_REG_BASE+0x120c)
+#define MT6389_AUXADC_IMP3 (MT6389_PMIC_REG_BASE+0x120e)
+#define MT6389_AUXADC_IMP4 (MT6389_PMIC_REG_BASE+0x1210)
+#define MT6389_AUXADC_IMP5 (MT6389_PMIC_REG_BASE+0x1212)
+#define MT6389_AUXADC_LBAT0 (MT6389_PMIC_REG_BASE+0x1214)
+#define MT6389_AUXADC_LBAT1 (MT6389_PMIC_REG_BASE+0x1216)
+#define MT6389_AUXADC_LBAT2 (MT6389_PMIC_REG_BASE+0x1218)
+#define MT6389_AUXADC_LBAT3 (MT6389_PMIC_REG_BASE+0x121a)
+#define MT6389_AUXADC_LBAT4 (MT6389_PMIC_REG_BASE+0x121c)
+#define MT6389_AUXADC_LBAT5 (MT6389_PMIC_REG_BASE+0x121e)
+#define MT6389_AUXADC_LBAT6 (MT6389_PMIC_REG_BASE+0x1220)
+#define MT6389_AUXADC_LBAT7 (MT6389_PMIC_REG_BASE+0x1222)
+#define MT6389_AUXADC_LBAT8 (MT6389_PMIC_REG_BASE+0x1224)
+#define MT6389_AUXADC_BAT_TEMP_0 (MT6389_PMIC_REG_BASE+0x1226)
+#define MT6389_AUXADC_BAT_TEMP_1 (MT6389_PMIC_REG_BASE+0x1228)
+#define MT6389_AUXADC_BAT_TEMP_2 (MT6389_PMIC_REG_BASE+0x122a)
+#define MT6389_AUXADC_BAT_TEMP_3 (MT6389_PMIC_REG_BASE+0x122c)
+#define MT6389_AUXADC_BAT_TEMP_4 (MT6389_PMIC_REG_BASE+0x122e)
+#define MT6389_AUXADC_BAT_TEMP_5 (MT6389_PMIC_REG_BASE+0x1230)
+#define MT6389_AUXADC_BAT_TEMP_6 (MT6389_PMIC_REG_BASE+0x1232)
+#define MT6389_AUXADC_BAT_TEMP_7 (MT6389_PMIC_REG_BASE+0x1234)
+#define MT6389_AUXADC_BAT_TEMP_8 (MT6389_PMIC_REG_BASE+0x1236)
+#define MT6389_AUXADC_BAT_TEMP_9 (MT6389_PMIC_REG_BASE+0x1238)
+#define MT6389_AUXADC_LBAT2_0 (MT6389_PMIC_REG_BASE+0x123a)
+#define MT6389_AUXADC_LBAT2_1 (MT6389_PMIC_REG_BASE+0x123c)
+#define MT6389_AUXADC_LBAT2_2 (MT6389_PMIC_REG_BASE+0x123e)
+#define MT6389_AUXADC_LBAT2_3 (MT6389_PMIC_REG_BASE+0x1240)
+#define MT6389_AUXADC_LBAT2_4 (MT6389_PMIC_REG_BASE+0x1242)
+#define MT6389_AUXADC_LBAT2_5 (MT6389_PMIC_REG_BASE+0x1244)
+#define MT6389_AUXADC_LBAT2_6 (MT6389_PMIC_REG_BASE+0x1246)
+#define MT6389_AUXADC_LBAT2_7 (MT6389_PMIC_REG_BASE+0x1248)
+#define MT6389_AUXADC_LBAT2_8 (MT6389_PMIC_REG_BASE+0x124a)
+#define MT6389_AUXADC_THR0 (MT6389_PMIC_REG_BASE+0x124c)
+#define MT6389_AUXADC_THR1 (MT6389_PMIC_REG_BASE+0x124e)
+#define MT6389_AUXADC_THR2 (MT6389_PMIC_REG_BASE+0x1250)
+#define MT6389_AUXADC_THR3 (MT6389_PMIC_REG_BASE+0x1252)
+#define MT6389_AUXADC_THR4 (MT6389_PMIC_REG_BASE+0x1254)
+#define MT6389_AUXADC_THR5 (MT6389_PMIC_REG_BASE+0x1256)
+#define MT6389_AUXADC_THR6 (MT6389_PMIC_REG_BASE+0x1258)
+#define MT6389_AUXADC_THR7 (MT6389_PMIC_REG_BASE+0x125a)
+#define MT6389_AUXADC_THR8 (MT6389_PMIC_REG_BASE+0x125c)
+#define MT6389_AUXADC_MDRT_0 (MT6389_PMIC_REG_BASE+0x125e)
+#define MT6389_AUXADC_MDRT_1 (MT6389_PMIC_REG_BASE+0x1260)
+#define MT6389_AUXADC_MDRT_2 (MT6389_PMIC_REG_BASE+0x1262)
+#define MT6389_AUXADC_MDRT_3 (MT6389_PMIC_REG_BASE+0x1264)
+#define MT6389_AUXADC_MDRT_4 (MT6389_PMIC_REG_BASE+0x1266)
+#define MT6389_AUXADC_MDRT_5 (MT6389_PMIC_REG_BASE+0x1268)
+#define MT6389_AUXADC_DCXO_MDRT_0 (MT6389_PMIC_REG_BASE+0x126a)
+#define MT6389_AUXADC_DCXO_MDRT_1 (MT6389_PMIC_REG_BASE+0x126c)
+#define MT6389_AUXADC_DCXO_MDRT_2 (MT6389_PMIC_REG_BASE+0x126e)
+#define MT6389_AUXADC_DCXO_MDRT_3 (MT6389_PMIC_REG_BASE+0x1270)
+#define MT6389_AUXADC_DCXO_MDRT_4 (MT6389_PMIC_REG_BASE+0x1272)
+#define MT6389_AUXADC_DCXO_MDRT_5 (MT6389_PMIC_REG_BASE+0x1274)
+#define MT6389_AUXADC_RSV_1 (MT6389_PMIC_REG_BASE+0x1276)
+#define MT6389_AUXADC_PRI_NEW (MT6389_PMIC_REG_BASE+0x1278)
+#define MT6389_AUXADC_DIG_5_DSN_ID (MT6389_PMIC_REG_BASE+0x1280)
+#define MT6389_AUXADC_DIG_5_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1282)
+#define MT6389_AUXADC_DIG_5_DSN_DBI (MT6389_PMIC_REG_BASE+0x1284)
+#define MT6389_AUXADC_DIG_5_DSN_DXI (MT6389_PMIC_REG_BASE+0x1286)
+#define MT6389_AUXADC_ADC_INTER1_DIV (MT6389_PMIC_REG_BASE+0x1288)
+#define MT6389_AUXADC_ADC_INTER2_DIV (MT6389_PMIC_REG_BASE+0x128a)
+#define MT6389_AUXADC_ADC_INTER3_DIV (MT6389_PMIC_REG_BASE+0x128c)
+#define MT6389_AUXADC_ADC_INTER4_DIV (MT6389_PMIC_REG_BASE+0x128e)
+#define MT6389_AUXADC_ADC_INTER5_DIV (MT6389_PMIC_REG_BASE+0x1290)
+#define MT6389_AUXADC_ADC_INTER6_DIV (MT6389_PMIC_REG_BASE+0x1292)
+#define MT6389_AUXADC_ADC_INTER7_DIV (MT6389_PMIC_REG_BASE+0x1294)
+#define MT6389_AUXADC_ADC_INTER8_DIV (MT6389_PMIC_REG_BASE+0x1296)
+#define MT6389_AUXADC_ADC_INTER9_DIV (MT6389_PMIC_REG_BASE+0x1298)
+#define MT6389_AUXADC_ADC_INTER10_DIV (MT6389_PMIC_REG_BASE+0x129a)
+#define MT6389_AUXADC_ADC_INTER11_DIV (MT6389_PMIC_REG_BASE+0x129c)
+#define MT6389_AUXADC_ADC_INTER12_DIV (MT6389_PMIC_REG_BASE+0x129e)
+#define MT6389_AUXADC_ADC_INTER13_DIV (MT6389_PMIC_REG_BASE+0x12a0)
+#define MT6389_AUXADC_ADC_INTER14_DIV (MT6389_PMIC_REG_BASE+0x12a2)
+#define MT6389_AUXADC_ADC_INTER1 (MT6389_PMIC_REG_BASE+0x12a4)
+#define MT6389_AUXADC_ADC_INTER2 (MT6389_PMIC_REG_BASE+0x12a6)
+#define MT6389_AUXADC_ADC_INTER3 (MT6389_PMIC_REG_BASE+0x12a8)
+#define MT6389_AUXADC_ADC_INTER4 (MT6389_PMIC_REG_BASE+0x12aa)
+#define MT6389_AUXADC_ADC_INTER5 (MT6389_PMIC_REG_BASE+0x12ac)
+#define MT6389_AUXADC_ADC_INTER6 (MT6389_PMIC_REG_BASE+0x12ae)
+#define MT6389_AUXADC_ADC_INTER7 (MT6389_PMIC_REG_BASE+0x12b0)
+#define MT6389_AUXADC_ADC_INTER8 (MT6389_PMIC_REG_BASE+0x12b2)
+#define MT6389_AUXADC_ADC_INTER9 (MT6389_PMIC_REG_BASE+0x12b4)
+#define MT6389_AUXADC_ADC_TREF (MT6389_PMIC_REG_BASE+0x12b6)
+#define MT6389_AUXADC_ADC_EXT1 (MT6389_PMIC_REG_BASE+0x12b8)
+#define MT6389_AUXADC_ADC_EXT2 (MT6389_PMIC_REG_BASE+0x12ba)
+#define MT6389_AUXADC_ADC_EXT3 (MT6389_PMIC_REG_BASE+0x12bc)
+#define MT6389_AUXADC_ADC_EXT4 (MT6389_PMIC_REG_BASE+0x12be)
+#define MT6389_AUXADC_ADC_EXT5 (MT6389_PMIC_REG_BASE+0x12c0)
+#define MT6389_AUXADC_ADC_EXT6 (MT6389_PMIC_REG_BASE+0x12c2)
+#define MT6389_AUXADC_ADC_EXT7 (MT6389_PMIC_REG_BASE+0x12c4)
+#define MT6389_AUXADC_ADC_EXT8 (MT6389_PMIC_REG_BASE+0x12c6)
+#define MT6389_AUXADC_STA_INTER_DIV (MT6389_PMIC_REG_BASE+0x12c8)
+#define MT6389_AUXADC_STA_INTER (MT6389_PMIC_REG_BASE+0x12ca)
+#define MT6389_AUXADC_STA_EXT (MT6389_PMIC_REG_BASE+0x12cc)
+#define MT6389_AUXADC_INTER_DIV_EN (MT6389_PMIC_REG_BASE+0x12ce)
+#define MT6389_AUXADC_INTER_EN (MT6389_PMIC_REG_BASE+0x12d0)
+#define MT6389_AUXADC_EXT_EN (MT6389_PMIC_REG_BASE+0x12d2)
+#define MT6389_AUXADC_DIG_6_DSN_ID (MT6389_PMIC_REG_BASE+0x1300)
+#define MT6389_AUXADC_DIG_6_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1302)
+#define MT6389_AUXADC_DIG_6_DSN_DBI (MT6389_PMIC_REG_BASE+0x1304)
+#define MT6389_AUXADC_DIG_6_DSN_DXI (MT6389_PMIC_REG_BASE+0x1306)
+#define MT6389_AUXADC_NAG_0 (MT6389_PMIC_REG_BASE+0x1308)
+#define MT6389_AUXADC_NAG_1 (MT6389_PMIC_REG_BASE+0x130a)
+#define MT6389_AUXADC_NAG_2 (MT6389_PMIC_REG_BASE+0x130c)
+#define MT6389_AUXADC_NAG_3 (MT6389_PMIC_REG_BASE+0x130e)
+#define MT6389_AUXADC_NAG_4 (MT6389_PMIC_REG_BASE+0x1310)
+#define MT6389_AUXADC_NAG_5 (MT6389_PMIC_REG_BASE+0x1312)
+#define MT6389_AUXADC_NAG_6 (MT6389_PMIC_REG_BASE+0x1314)
+#define MT6389_AUXADC_NAG_7 (MT6389_PMIC_REG_BASE+0x1316)
+#define MT6389_AUXADC_NAG_8 (MT6389_PMIC_REG_BASE+0x1318)
+#define MT6389_AUXADC_NAG_9 (MT6389_PMIC_REG_BASE+0x131a)
+#define MT6389_AUXADC_NAG_10 (MT6389_PMIC_REG_BASE+0x131c)
+#define MT6389_AUXADC_NAG_11 (MT6389_PMIC_REG_BASE+0x131e)
+#define MT6389_AUXADC_INTER1_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1320)
+#define MT6389_AUXADC_INTER1_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x1322)
+#define MT6389_AUXADC_INTER1_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x1324)
+#define MT6389_AUXADC_INTER1_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x1326)
+#define MT6389_AUXADC_INTER1_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1328)
+#define MT6389_AUXADC_INTER1_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x132a)
+#define MT6389_AUXADC_INTER1_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x132c)
+#define MT6389_AUXADC_INTER1_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x132e)
+#define MT6389_AUXADC_INTER1_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1330)
+#define MT6389_AUXADC_INTER2_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1332)
+#define MT6389_AUXADC_INTER2_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x1334)
+#define MT6389_AUXADC_INTER2_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x1336)
+#define MT6389_AUXADC_INTER2_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x1338)
+#define MT6389_AUXADC_INTER2_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x133a)
+#define MT6389_AUXADC_INTER2_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x133c)
+#define MT6389_AUXADC_INTER2_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x133e)
+#define MT6389_AUXADC_INTER2_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1340)
+#define MT6389_AUXADC_INTER2_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1342)
+#define MT6389_AUXADC_INTER3_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1344)
+#define MT6389_AUXADC_INTER3_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x1346)
+#define MT6389_AUXADC_INTER3_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x1348)
+#define MT6389_AUXADC_INTER3_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x134a)
+#define MT6389_AUXADC_INTER3_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x134c)
+#define MT6389_AUXADC_INTER3_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x134e)
+#define MT6389_AUXADC_INTER3_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1350)
+#define MT6389_AUXADC_INTER3_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1352)
+#define MT6389_AUXADC_INTER3_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1354)
+#define MT6389_AUXADC_INTER4_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1356)
+#define MT6389_AUXADC_INTER4_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x1358)
+#define MT6389_AUXADC_INTER4_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x135a)
+#define MT6389_AUXADC_INTER4_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x135c)
+#define MT6389_AUXADC_INTER4_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x135e)
+#define MT6389_AUXADC_INTER4_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1360)
+#define MT6389_AUXADC_INTER4_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1362)
+#define MT6389_AUXADC_INTER4_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1364)
+#define MT6389_AUXADC_INTER4_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1366)
+#define MT6389_AUXADC_INTER5_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1368)
+#define MT6389_AUXADC_INTER5_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x136a)
+#define MT6389_AUXADC_INTER5_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x136c)
+#define MT6389_AUXADC_INTER5_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x136e)
+#define MT6389_AUXADC_INTER5_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1370)
+#define MT6389_AUXADC_INTER5_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1372)
+#define MT6389_AUXADC_INTER5_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1374)
+#define MT6389_AUXADC_INTER5_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1376)
+#define MT6389_AUXADC_INTER5_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1378)
+#define MT6389_AUXADC_DIG_7_DSN_ID (MT6389_PMIC_REG_BASE+0x1380)
+#define MT6389_AUXADC_DIG_7_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1382)
+#define MT6389_AUXADC_DIG_7_DSN_DBI (MT6389_PMIC_REG_BASE+0x1384)
+#define MT6389_AUXADC_DIG_7_DSN_DXI (MT6389_PMIC_REG_BASE+0x1386)
+#define MT6389_AUXADC_INTER6_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1388)
+#define MT6389_AUXADC_INTER6_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x138a)
+#define MT6389_AUXADC_INTER6_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x138c)
+#define MT6389_AUXADC_INTER6_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x138e)
+#define MT6389_AUXADC_INTER6_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1390)
+#define MT6389_AUXADC_INTER6_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1392)
+#define MT6389_AUXADC_INTER6_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1394)
+#define MT6389_AUXADC_INTER6_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1396)
+#define MT6389_AUXADC_INTER6_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1398)
+#define MT6389_AUXADC_INTER7_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x139a)
+#define MT6389_AUXADC_INTER7_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x139c)
+#define MT6389_AUXADC_INTER7_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x139e)
+#define MT6389_AUXADC_INTER7_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x13a0)
+#define MT6389_AUXADC_INTER7_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x13a2)
+#define MT6389_AUXADC_INTER7_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x13a4)
+#define MT6389_AUXADC_INTER7_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x13a6)
+#define MT6389_AUXADC_INTER7_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x13a8)
+#define MT6389_AUXADC_INTER7_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x13aa)
+#define MT6389_AUXADC_INTER8_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x13ac)
+#define MT6389_AUXADC_INTER8_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x13ae)
+#define MT6389_AUXADC_INTER8_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x13b0)
+#define MT6389_AUXADC_INTER8_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x13b2)
+#define MT6389_AUXADC_INTER8_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x13b4)
+#define MT6389_AUXADC_INTER8_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x13b6)
+#define MT6389_AUXADC_INTER8_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x13b8)
+#define MT6389_AUXADC_INTER8_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x13ba)
+#define MT6389_AUXADC_INTER8_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x13bc)
+#define MT6389_AUXADC_INTER9_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x13be)
+#define MT6389_AUXADC_INTER9_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x13c0)
+#define MT6389_AUXADC_INTER9_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x13c2)
+#define MT6389_AUXADC_INTER9_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x13c4)
+#define MT6389_AUXADC_INTER9_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x13c6)
+#define MT6389_AUXADC_INTER9_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x13c8)
+#define MT6389_AUXADC_INTER9_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x13ca)
+#define MT6389_AUXADC_INTER9_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x13cc)
+#define MT6389_AUXADC_INTER9_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x13ce)
+#define MT6389_AUXADC_INTER10_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x13d0)
+#define MT6389_AUXADC_INTER10_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x13d2)
+#define MT6389_AUXADC_INTER10_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x13d4)
+#define MT6389_AUXADC_INTER10_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x13d6)
+#define MT6389_AUXADC_INTER10_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x13d8)
+#define MT6389_AUXADC_INTER10_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x13da)
+#define MT6389_AUXADC_INTER10_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x13dc)
+#define MT6389_AUXADC_INTER10_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x13de)
+#define MT6389_AUXADC_INTER10_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x13e0)
+#define MT6389_AUXADC_INTER11_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x13e2)
+#define MT6389_AUXADC_INTER11_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x13e4)
+#define MT6389_AUXADC_INTER11_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x13e6)
+#define MT6389_AUXADC_INTER11_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x13e8)
+#define MT6389_AUXADC_INTER11_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x13ea)
+#define MT6389_AUXADC_INTER11_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x13ec)
+#define MT6389_AUXADC_INTER11_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x13ee)
+#define MT6389_AUXADC_INTER11_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x13f0)
+#define MT6389_AUXADC_INTER11_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x13f2)
+#define MT6389_AUXADC_DIG_8_DSN_ID (MT6389_PMIC_REG_BASE+0x1400)
+#define MT6389_AUXADC_DIG_8_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1402)
+#define MT6389_AUXADC_DIG_8_DSN_DBI (MT6389_PMIC_REG_BASE+0x1404)
+#define MT6389_AUXADC_DIG_8_DSN_DXI (MT6389_PMIC_REG_BASE+0x1406)
+#define MT6389_AUXADC_INTER12_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x1408)
+#define MT6389_AUXADC_INTER12_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x140a)
+#define MT6389_AUXADC_INTER12_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x140c)
+#define MT6389_AUXADC_INTER12_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x140e)
+#define MT6389_AUXADC_INTER12_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1410)
+#define MT6389_AUXADC_INTER12_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1412)
+#define MT6389_AUXADC_INTER12_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1414)
+#define MT6389_AUXADC_INTER12_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1416)
+#define MT6389_AUXADC_INTER12_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x1418)
+#define MT6389_AUXADC_INTER13_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x141a)
+#define MT6389_AUXADC_INTER13_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x141c)
+#define MT6389_AUXADC_INTER13_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x141e)
+#define MT6389_AUXADC_INTER13_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x1420)
+#define MT6389_AUXADC_INTER13_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1422)
+#define MT6389_AUXADC_INTER13_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1424)
+#define MT6389_AUXADC_INTER13_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1426)
+#define MT6389_AUXADC_INTER13_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x1428)
+#define MT6389_AUXADC_INTER13_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x142a)
+#define MT6389_AUXADC_INTER14_DET_DIV_0 (MT6389_PMIC_REG_BASE+0x142c)
+#define MT6389_AUXADC_INTER14_DET_DIV_1 (MT6389_PMIC_REG_BASE+0x142e)
+#define MT6389_AUXADC_INTER14_DET_DIV_2 (MT6389_PMIC_REG_BASE+0x1430)
+#define MT6389_AUXADC_INTER14_DET_DIV_3 (MT6389_PMIC_REG_BASE+0x1432)
+#define MT6389_AUXADC_INTER14_DET_DIV_4 (MT6389_PMIC_REG_BASE+0x1434)
+#define MT6389_AUXADC_INTER14_DET_DIV_5 (MT6389_PMIC_REG_BASE+0x1436)
+#define MT6389_AUXADC_INTER14_DET_DIV_6 (MT6389_PMIC_REG_BASE+0x1438)
+#define MT6389_AUXADC_INTER14_DET_DIV_7 (MT6389_PMIC_REG_BASE+0x143a)
+#define MT6389_AUXADC_INTER14_DET_DIV_8 (MT6389_PMIC_REG_BASE+0x143c)
+#define MT6389_AUXADC_INTER1_DET_0 (MT6389_PMIC_REG_BASE+0x143e)
+#define MT6389_AUXADC_INTER1_DET_1 (MT6389_PMIC_REG_BASE+0x1440)
+#define MT6389_AUXADC_INTER1_DET_2 (MT6389_PMIC_REG_BASE+0x1442)
+#define MT6389_AUXADC_INTER1_DET_3 (MT6389_PMIC_REG_BASE+0x1444)
+#define MT6389_AUXADC_INTER1_DET_4 (MT6389_PMIC_REG_BASE+0x1446)
+#define MT6389_AUXADC_INTER1_DET_5 (MT6389_PMIC_REG_BASE+0x1448)
+#define MT6389_AUXADC_INTER1_DET_6 (MT6389_PMIC_REG_BASE+0x144a)
+#define MT6389_AUXADC_INTER1_DET_7 (MT6389_PMIC_REG_BASE+0x144c)
+#define MT6389_AUXADC_INTER1_DET_8 (MT6389_PMIC_REG_BASE+0x144e)
+#define MT6389_AUXADC_INTER2_DET_0 (MT6389_PMIC_REG_BASE+0x1450)
+#define MT6389_AUXADC_INTER2_DET_1 (MT6389_PMIC_REG_BASE+0x1452)
+#define MT6389_AUXADC_INTER2_DET_2 (MT6389_PMIC_REG_BASE+0x1454)
+#define MT6389_AUXADC_INTER2_DET_3 (MT6389_PMIC_REG_BASE+0x1456)
+#define MT6389_AUXADC_INTER2_DET_4 (MT6389_PMIC_REG_BASE+0x1458)
+#define MT6389_AUXADC_INTER2_DET_5 (MT6389_PMIC_REG_BASE+0x145a)
+#define MT6389_AUXADC_INTER2_DET_6 (MT6389_PMIC_REG_BASE+0x145c)
+#define MT6389_AUXADC_INTER2_DET_7 (MT6389_PMIC_REG_BASE+0x145e)
+#define MT6389_AUXADC_INTER2_DET_8 (MT6389_PMIC_REG_BASE+0x1460)
+#define MT6389_AUXADC_INTER3_DET_0 (MT6389_PMIC_REG_BASE+0x1462)
+#define MT6389_AUXADC_INTER3_DET_1 (MT6389_PMIC_REG_BASE+0x1464)
+#define MT6389_AUXADC_INTER3_DET_2 (MT6389_PMIC_REG_BASE+0x1466)
+#define MT6389_AUXADC_INTER3_DET_3 (MT6389_PMIC_REG_BASE+0x1468)
+#define MT6389_AUXADC_INTER3_DET_4 (MT6389_PMIC_REG_BASE+0x146a)
+#define MT6389_AUXADC_INTER3_DET_5 (MT6389_PMIC_REG_BASE+0x146c)
+#define MT6389_AUXADC_INTER3_DET_6 (MT6389_PMIC_REG_BASE+0x146e)
+#define MT6389_AUXADC_INTER3_DET_7 (MT6389_PMIC_REG_BASE+0x1470)
+#define MT6389_AUXADC_INTER3_DET_8 (MT6389_PMIC_REG_BASE+0x1472)
+#define MT6389_AUXADC_DIG_9_DSN_ID (MT6389_PMIC_REG_BASE+0x1480)
+#define MT6389_AUXADC_DIG_9_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1482)
+#define MT6389_AUXADC_DIG_9_DSN_DBI (MT6389_PMIC_REG_BASE+0x1484)
+#define MT6389_AUXADC_DIG_9_DSN_DXI (MT6389_PMIC_REG_BASE+0x1486)
+#define MT6389_AUXADC_INTER4_DET_0 (MT6389_PMIC_REG_BASE+0x1488)
+#define MT6389_AUXADC_INTER4_DET_1 (MT6389_PMIC_REG_BASE+0x148a)
+#define MT6389_AUXADC_INTER4_DET_2 (MT6389_PMIC_REG_BASE+0x148c)
+#define MT6389_AUXADC_INTER4_DET_3 (MT6389_PMIC_REG_BASE+0x148e)
+#define MT6389_AUXADC_INTER4_DET_4 (MT6389_PMIC_REG_BASE+0x1490)
+#define MT6389_AUXADC_INTER4_DET_5 (MT6389_PMIC_REG_BASE+0x1492)
+#define MT6389_AUXADC_INTER4_DET_6 (MT6389_PMIC_REG_BASE+0x1494)
+#define MT6389_AUXADC_INTER4_DET_7 (MT6389_PMIC_REG_BASE+0x1496)
+#define MT6389_AUXADC_INTER4_DET_8 (MT6389_PMIC_REG_BASE+0x1498)
+#define MT6389_AUXADC_INTER5_DET_0 (MT6389_PMIC_REG_BASE+0x149a)
+#define MT6389_AUXADC_INTER5_DET_1 (MT6389_PMIC_REG_BASE+0x149c)
+#define MT6389_AUXADC_INTER5_DET_2 (MT6389_PMIC_REG_BASE+0x149e)
+#define MT6389_AUXADC_INTER5_DET_3 (MT6389_PMIC_REG_BASE+0x14a0)
+#define MT6389_AUXADC_INTER5_DET_4 (MT6389_PMIC_REG_BASE+0x14a2)
+#define MT6389_AUXADC_INTER5_DET_5 (MT6389_PMIC_REG_BASE+0x14a4)
+#define MT6389_AUXADC_INTER5_DET_6 (MT6389_PMIC_REG_BASE+0x14a6)
+#define MT6389_AUXADC_INTER5_DET_7 (MT6389_PMIC_REG_BASE+0x14a8)
+#define MT6389_AUXADC_INTER5_DET_8 (MT6389_PMIC_REG_BASE+0x14aa)
+#define MT6389_AUXADC_INTER6_DET_0 (MT6389_PMIC_REG_BASE+0x14ac)
+#define MT6389_AUXADC_INTER6_DET_1 (MT6389_PMIC_REG_BASE+0x14ae)
+#define MT6389_AUXADC_INTER6_DET_2 (MT6389_PMIC_REG_BASE+0x14b0)
+#define MT6389_AUXADC_INTER6_DET_3 (MT6389_PMIC_REG_BASE+0x14b2)
+#define MT6389_AUXADC_INTER6_DET_4 (MT6389_PMIC_REG_BASE+0x14b4)
+#define MT6389_AUXADC_INTER6_DET_5 (MT6389_PMIC_REG_BASE+0x14b6)
+#define MT6389_AUXADC_INTER6_DET_6 (MT6389_PMIC_REG_BASE+0x14b8)
+#define MT6389_AUXADC_INTER6_DET_7 (MT6389_PMIC_REG_BASE+0x14ba)
+#define MT6389_AUXADC_INTER6_DET_8 (MT6389_PMIC_REG_BASE+0x14bc)
+#define MT6389_AUXADC_INTER7_DET_0 (MT6389_PMIC_REG_BASE+0x14be)
+#define MT6389_AUXADC_INTER7_DET_1 (MT6389_PMIC_REG_BASE+0x14c0)
+#define MT6389_AUXADC_INTER7_DET_2 (MT6389_PMIC_REG_BASE+0x14c2)
+#define MT6389_AUXADC_INTER7_DET_3 (MT6389_PMIC_REG_BASE+0x14c4)
+#define MT6389_AUXADC_INTER7_DET_4 (MT6389_PMIC_REG_BASE+0x14c6)
+#define MT6389_AUXADC_INTER7_DET_5 (MT6389_PMIC_REG_BASE+0x14c8)
+#define MT6389_AUXADC_INTER7_DET_6 (MT6389_PMIC_REG_BASE+0x14ca)
+#define MT6389_AUXADC_INTER7_DET_7 (MT6389_PMIC_REG_BASE+0x14cc)
+#define MT6389_AUXADC_INTER7_DET_8 (MT6389_PMIC_REG_BASE+0x14ce)
+#define MT6389_AUXADC_INTER8_DET_0 (MT6389_PMIC_REG_BASE+0x14d0)
+#define MT6389_AUXADC_INTER8_DET_1 (MT6389_PMIC_REG_BASE+0x14d2)
+#define MT6389_AUXADC_INTER8_DET_2 (MT6389_PMIC_REG_BASE+0x14d4)
+#define MT6389_AUXADC_INTER8_DET_3 (MT6389_PMIC_REG_BASE+0x14d6)
+#define MT6389_AUXADC_INTER8_DET_4 (MT6389_PMIC_REG_BASE+0x14d8)
+#define MT6389_AUXADC_INTER8_DET_5 (MT6389_PMIC_REG_BASE+0x14da)
+#define MT6389_AUXADC_INTER8_DET_6 (MT6389_PMIC_REG_BASE+0x14dc)
+#define MT6389_AUXADC_INTER8_DET_7 (MT6389_PMIC_REG_BASE+0x14de)
+#define MT6389_AUXADC_INTER8_DET_8 (MT6389_PMIC_REG_BASE+0x14e0)
+#define MT6389_AUXADC_INTER9_DET_0 (MT6389_PMIC_REG_BASE+0x14e2)
+#define MT6389_AUXADC_INTER9_DET_1 (MT6389_PMIC_REG_BASE+0x14e4)
+#define MT6389_AUXADC_INTER9_DET_2 (MT6389_PMIC_REG_BASE+0x14e6)
+#define MT6389_AUXADC_INTER9_DET_3 (MT6389_PMIC_REG_BASE+0x14e8)
+#define MT6389_AUXADC_INTER9_DET_4 (MT6389_PMIC_REG_BASE+0x14ea)
+#define MT6389_AUXADC_INTER9_DET_5 (MT6389_PMIC_REG_BASE+0x14ec)
+#define MT6389_AUXADC_INTER9_DET_6 (MT6389_PMIC_REG_BASE+0x14ee)
+#define MT6389_AUXADC_INTER9_DET_7 (MT6389_PMIC_REG_BASE+0x14f0)
+#define MT6389_AUXADC_INTER9_DET_8 (MT6389_PMIC_REG_BASE+0x14f2)
+#define MT6389_BUCK_TOP_DSN_ID (MT6389_PMIC_REG_BASE+0x1580)
+#define MT6389_BUCK_TOP_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1582)
+#define MT6389_BUCK_TOP_DBI (MT6389_PMIC_REG_BASE+0x1584)
+#define MT6389_BUCK_TOP_DXI (MT6389_PMIC_REG_BASE+0x1586)
+#define MT6389_BUCK_TOP_PAM0 (MT6389_PMIC_REG_BASE+0x1588)
+#define MT6389_BUCK_TOP_PAM1 (MT6389_PMIC_REG_BASE+0x158a)
+#define MT6389_BUCK_TOP_CLK_CON0 (MT6389_PMIC_REG_BASE+0x158c)
+#define MT6389_BUCK_TOP_CLK_CON0_SET (MT6389_PMIC_REG_BASE+0x158e)
+#define MT6389_BUCK_TOP_CLK_CON0_CLR (MT6389_PMIC_REG_BASE+0x1590)
+#define MT6389_BUCK_TOP_CLK_HWEN_CON0 (MT6389_PMIC_REG_BASE+0x1592)
+#define MT6389_BUCK_TOP_CLK_HWEN_CON0_SET (MT6389_PMIC_REG_BASE+0x1594)
+#define MT6389_BUCK_TOP_CLK_HWEN_CON0_CLR (MT6389_PMIC_REG_BASE+0x1596)
+#define MT6389_BUCK_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x1598)
+#define MT6389_BUCK_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x159a)
+#define MT6389_BUCK_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x159c)
+#define MT6389_BUCK_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x159e)
+#define MT6389_BUCK_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x15a0)
+#define MT6389_BUCK_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x15a2)
+#define MT6389_BUCK_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x15a4)
+#define MT6389_BUCK_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x15a6)
+#define MT6389_BUCK_TOP_VOW_CON (MT6389_PMIC_REG_BASE+0x15a8)
+#define MT6389_BUCK_TOP_STB_CON (MT6389_PMIC_REG_BASE+0x15aa)
+#define MT6389_BUCK_TOP_VGP2_MINFREQ_CON (MT6389_PMIC_REG_BASE+0x15ac)
+#define MT6389_BUCK_TOP_VPA_MINFREQ_CON (MT6389_PMIC_REG_BASE+0x15ae)
+#define MT6389_BUCK_TOP_OC_CON0 (MT6389_PMIC_REG_BASE+0x15b0)
+#define MT6389_BUCK_TOP_KEY_PROT (MT6389_PMIC_REG_BASE+0x15b2)
+#define MT6389_BUCK_TOP_SSC_CON (MT6389_PMIC_REG_BASE+0x15b4)
+#define MT6389_BUCK_TOP_K_CON0 (MT6389_PMIC_REG_BASE+0x15b6)
+#define MT6389_BUCK_TOP_K_CON1 (MT6389_PMIC_REG_BASE+0x15b8)
+#define MT6389_BUCK_TOP_K_CON2 (MT6389_PMIC_REG_BASE+0x15ba)
+#define MT6389_BUCK_TOP_WDTDBG0 (MT6389_PMIC_REG_BASE+0x15bc)
+#define MT6389_BUCK_TOP_WDTDBG1 (MT6389_PMIC_REG_BASE+0x15be)
+#define MT6389_BUCK_TOP_WDTDBG2 (MT6389_PMIC_REG_BASE+0x15c0)
+#define MT6389_BUCK_TOP_WDTDBG3 (MT6389_PMIC_REG_BASE+0x15c2)
+#define MT6389_BUCK_TOP_ELR_NUM (MT6389_PMIC_REG_BASE+0x15c4)
+#define MT6389_BUCK_TOP_ELR0 (MT6389_PMIC_REG_BASE+0x15c6)
+#define MT6389_BUCK_TOP_ELR1 (MT6389_PMIC_REG_BASE+0x15c8)
+#define MT6389_BUCK_TOP_ELR2 (MT6389_PMIC_REG_BASE+0x15ca)
+#define MT6389_BUCK_VPROC_DSN_ID (MT6389_PMIC_REG_BASE+0x1600)
+#define MT6389_BUCK_VPROC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1602)
+#define MT6389_BUCK_VPROC_DSN_DBI (MT6389_PMIC_REG_BASE+0x1604)
+#define MT6389_BUCK_VPROC_DSN_DXI (MT6389_PMIC_REG_BASE+0x1606)
+#define MT6389_BUCK_VPROC_CON0 (MT6389_PMIC_REG_BASE+0x1608)
+#define MT6389_BUCK_VPROC_CON0_SET (MT6389_PMIC_REG_BASE+0x160a)
+#define MT6389_BUCK_VPROC_CON0_CLR (MT6389_PMIC_REG_BASE+0x160c)
+#define MT6389_BUCK_VPROC_CON1 (MT6389_PMIC_REG_BASE+0x160e)
+#define MT6389_BUCK_VPROC_SLP_CON (MT6389_PMIC_REG_BASE+0x1610)
+#define MT6389_BUCK_VPROC_CFG0 (MT6389_PMIC_REG_BASE+0x1612)
+#define MT6389_BUCK_VPROC_OP_EN (MT6389_PMIC_REG_BASE+0x1614)
+#define MT6389_BUCK_VPROC_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1616)
+#define MT6389_BUCK_VPROC_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1618)
+#define MT6389_BUCK_VPROC_OP_CFG (MT6389_PMIC_REG_BASE+0x161a)
+#define MT6389_BUCK_VPROC_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x161c)
+#define MT6389_BUCK_VPROC_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x161e)
+#define MT6389_BUCK_VPROC_OP_MODE (MT6389_PMIC_REG_BASE+0x1620)
+#define MT6389_BUCK_VPROC_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x1622)
+#define MT6389_BUCK_VPROC_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x1624)
+#define MT6389_BUCK_VPROC_DBG0 (MT6389_PMIC_REG_BASE+0x1626)
+#define MT6389_BUCK_VPROC_DBG1 (MT6389_PMIC_REG_BASE+0x1628)
+#define MT6389_BUCK_VPROC_STALL_TRACK0 (MT6389_PMIC_REG_BASE+0x162a)
+#define MT6389_BUCK_VPROC_ELR_NUM (MT6389_PMIC_REG_BASE+0x162c)
+#define MT6389_BUCK_VPROC_ELR0 (MT6389_PMIC_REG_BASE+0x162e)
+#define MT6389_BUCK_VCORE_DSN_ID (MT6389_PMIC_REG_BASE+0x1680)
+#define MT6389_BUCK_VCORE_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1682)
+#define MT6389_BUCK_VCORE_DSN_DBI (MT6389_PMIC_REG_BASE+0x1684)
+#define MT6389_BUCK_VCORE_DSN_DXI (MT6389_PMIC_REG_BASE+0x1686)
+#define MT6389_BUCK_VCORE_CON0 (MT6389_PMIC_REG_BASE+0x1688)
+#define MT6389_BUCK_VCORE_CON0_SET (MT6389_PMIC_REG_BASE+0x168a)
+#define MT6389_BUCK_VCORE_CON0_CLR (MT6389_PMIC_REG_BASE+0x168c)
+#define MT6389_BUCK_VCORE_CON1 (MT6389_PMIC_REG_BASE+0x168e)
+#define MT6389_BUCK_VCORE_SLP_CON (MT6389_PMIC_REG_BASE+0x1690)
+#define MT6389_BUCK_VCORE_CFG0 (MT6389_PMIC_REG_BASE+0x1692)
+#define MT6389_BUCK_VCORE_OP_EN (MT6389_PMIC_REG_BASE+0x1694)
+#define MT6389_BUCK_VCORE_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1696)
+#define MT6389_BUCK_VCORE_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1698)
+#define MT6389_BUCK_VCORE_OP_CFG (MT6389_PMIC_REG_BASE+0x169a)
+#define MT6389_BUCK_VCORE_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x169c)
+#define MT6389_BUCK_VCORE_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x169e)
+#define MT6389_BUCK_VCORE_OP_MODE (MT6389_PMIC_REG_BASE+0x16a0)
+#define MT6389_BUCK_VCORE_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x16a2)
+#define MT6389_BUCK_VCORE_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x16a4)
+#define MT6389_BUCK_VCORE_DBG0 (MT6389_PMIC_REG_BASE+0x16a6)
+#define MT6389_BUCK_VCORE_DBG1 (MT6389_PMIC_REG_BASE+0x16a8)
+#define MT6389_BUCK_VCORE_ELR_NUM (MT6389_PMIC_REG_BASE+0x16aa)
+#define MT6389_BUCK_VCORE_ELR0 (MT6389_PMIC_REG_BASE+0x16ac)
+#define MT6389_BUCK_VSRAM_OTHERS_DSN_ID (MT6389_PMIC_REG_BASE+0x1700)
+#define MT6389_BUCK_VSRAM_OTHERS_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1702)
+#define MT6389_BUCK_VSRAM_OTHERS_DSN_DBI (MT6389_PMIC_REG_BASE+0x1704)
+#define MT6389_BUCK_VSRAM_OTHERS_DSN_DXI (MT6389_PMIC_REG_BASE+0x1706)
+#define MT6389_BUCK_VSRAM_OTHERS_CON0 (MT6389_PMIC_REG_BASE+0x1708)
+#define MT6389_BUCK_VSRAM_OTHERS_CON0_SET (MT6389_PMIC_REG_BASE+0x170a)
+#define MT6389_BUCK_VSRAM_OTHERS_CON0_CLR (MT6389_PMIC_REG_BASE+0x170c)
+#define MT6389_BUCK_VSRAM_OTHERS_CON1 (MT6389_PMIC_REG_BASE+0x170e)
+#define MT6389_BUCK_VSRAM_OTHERS_SLP_CON (MT6389_PMIC_REG_BASE+0x1710)
+#define MT6389_BUCK_VSRAM_OTHERS_CFG0 (MT6389_PMIC_REG_BASE+0x1712)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_EN (MT6389_PMIC_REG_BASE+0x1714)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1716)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1718)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_CFG (MT6389_PMIC_REG_BASE+0x171a)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x171c)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x171e)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_MODE (MT6389_PMIC_REG_BASE+0x1720)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x1722)
+#define MT6389_BUCK_VSRAM_OTHERS_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x1724)
+#define MT6389_BUCK_VSRAM_OTHERS_DBG0 (MT6389_PMIC_REG_BASE+0x1726)
+#define MT6389_BUCK_VSRAM_OTHERS_DBG1 (MT6389_PMIC_REG_BASE+0x1728)
+#define MT6389_BUCK_VSRAM_OTHERS_ELR_NUM (MT6389_PMIC_REG_BASE+0x172a)
+#define MT6389_BUCK_VSRAM_OTHERS_ELR0 (MT6389_PMIC_REG_BASE+0x172c)
+#define MT6389_BUCK_VMODEM_DSN_ID (MT6389_PMIC_REG_BASE+0x1780)
+#define MT6389_BUCK_VMODEM_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1782)
+#define MT6389_BUCK_VMODEM_DSN_DBI (MT6389_PMIC_REG_BASE+0x1784)
+#define MT6389_BUCK_VMODEM_DSN_DXI (MT6389_PMIC_REG_BASE+0x1786)
+#define MT6389_BUCK_VMODEM_CON0 (MT6389_PMIC_REG_BASE+0x1788)
+#define MT6389_BUCK_VMODEM_CON0_SET (MT6389_PMIC_REG_BASE+0x178a)
+#define MT6389_BUCK_VMODEM_CON0_CLR (MT6389_PMIC_REG_BASE+0x178c)
+#define MT6389_BUCK_VMODEM_CON1 (MT6389_PMIC_REG_BASE+0x178e)
+#define MT6389_BUCK_VMODEM_SLP_CON (MT6389_PMIC_REG_BASE+0x1790)
+#define MT6389_BUCK_VMODEM_CFG0 (MT6389_PMIC_REG_BASE+0x1792)
+#define MT6389_BUCK_VMODEM_OP_EN (MT6389_PMIC_REG_BASE+0x1794)
+#define MT6389_BUCK_VMODEM_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1796)
+#define MT6389_BUCK_VMODEM_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1798)
+#define MT6389_BUCK_VMODEM_OP_CFG (MT6389_PMIC_REG_BASE+0x179a)
+#define MT6389_BUCK_VMODEM_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x179c)
+#define MT6389_BUCK_VMODEM_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x179e)
+#define MT6389_BUCK_VMODEM_OP_MODE (MT6389_PMIC_REG_BASE+0x17a0)
+#define MT6389_BUCK_VMODEM_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x17a2)
+#define MT6389_BUCK_VMODEM_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x17a4)
+#define MT6389_BUCK_VMODEM_DBG0 (MT6389_PMIC_REG_BASE+0x17a6)
+#define MT6389_BUCK_VMODEM_DBG1 (MT6389_PMIC_REG_BASE+0x17a8)
+#define MT6389_BUCK_VMODEM_ELR_NUM (MT6389_PMIC_REG_BASE+0x17aa)
+#define MT6389_BUCK_VMODEM_ELR0 (MT6389_PMIC_REG_BASE+0x17ac)
+#define MT6389_BUCK_VDRAM1_DSN_ID (MT6389_PMIC_REG_BASE+0x1800)
+#define MT6389_BUCK_VDRAM1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1802)
+#define MT6389_BUCK_VDRAM1_DSN_DBI (MT6389_PMIC_REG_BASE+0x1804)
+#define MT6389_BUCK_VDRAM1_DSN_DXI (MT6389_PMIC_REG_BASE+0x1806)
+#define MT6389_BUCK_VDRAM1_CON0 (MT6389_PMIC_REG_BASE+0x1808)
+#define MT6389_BUCK_VDRAM1_CON0_SET (MT6389_PMIC_REG_BASE+0x180a)
+#define MT6389_BUCK_VDRAM1_CON0_CLR (MT6389_PMIC_REG_BASE+0x180c)
+#define MT6389_BUCK_VDRAM1_CON1 (MT6389_PMIC_REG_BASE+0x180e)
+#define MT6389_BUCK_VDRAM1_SLP_CON (MT6389_PMIC_REG_BASE+0x1810)
+#define MT6389_BUCK_VDRAM1_CFG0 (MT6389_PMIC_REG_BASE+0x1812)
+#define MT6389_BUCK_VDRAM1_OP_EN (MT6389_PMIC_REG_BASE+0x1814)
+#define MT6389_BUCK_VDRAM1_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1816)
+#define MT6389_BUCK_VDRAM1_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1818)
+#define MT6389_BUCK_VDRAM1_OP_CFG (MT6389_PMIC_REG_BASE+0x181a)
+#define MT6389_BUCK_VDRAM1_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x181c)
+#define MT6389_BUCK_VDRAM1_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x181e)
+#define MT6389_BUCK_VDRAM1_OP_MODE (MT6389_PMIC_REG_BASE+0x1820)
+#define MT6389_BUCK_VDRAM1_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x1822)
+#define MT6389_BUCK_VDRAM1_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x1824)
+#define MT6389_BUCK_VDRAM1_DBG0 (MT6389_PMIC_REG_BASE+0x1826)
+#define MT6389_BUCK_VDRAM1_DBG1 (MT6389_PMIC_REG_BASE+0x1828)
+#define MT6389_BUCK_VDRAM1_ELR_NUM (MT6389_PMIC_REG_BASE+0x182a)
+#define MT6389_BUCK_VDRAM1_ELR0 (MT6389_PMIC_REG_BASE+0x182c)
+#define MT6389_BUCK_VS1_DSN_ID (MT6389_PMIC_REG_BASE+0x1880)
+#define MT6389_BUCK_VS1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1882)
+#define MT6389_BUCK_VS1_DSN_DBI (MT6389_PMIC_REG_BASE+0x1884)
+#define MT6389_BUCK_VS1_DSN_DXI (MT6389_PMIC_REG_BASE+0x1886)
+#define MT6389_BUCK_VS1_CON0 (MT6389_PMIC_REG_BASE+0x1888)
+#define MT6389_BUCK_VS1_CON0_SET (MT6389_PMIC_REG_BASE+0x188a)
+#define MT6389_BUCK_VS1_CON0_CLR (MT6389_PMIC_REG_BASE+0x188c)
+#define MT6389_BUCK_VS1_CON1 (MT6389_PMIC_REG_BASE+0x188e)
+#define MT6389_BUCK_VS1_SLP_CON (MT6389_PMIC_REG_BASE+0x1890)
+#define MT6389_BUCK_VS1_CFG0 (MT6389_PMIC_REG_BASE+0x1892)
+#define MT6389_BUCK_VS1_OP_EN (MT6389_PMIC_REG_BASE+0x1894)
+#define MT6389_BUCK_VS1_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1896)
+#define MT6389_BUCK_VS1_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1898)
+#define MT6389_BUCK_VS1_OP_CFG (MT6389_PMIC_REG_BASE+0x189a)
+#define MT6389_BUCK_VS1_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x189c)
+#define MT6389_BUCK_VS1_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x189e)
+#define MT6389_BUCK_VS1_OP_MODE (MT6389_PMIC_REG_BASE+0x18a0)
+#define MT6389_BUCK_VS1_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x18a2)
+#define MT6389_BUCK_VS1_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x18a4)
+#define MT6389_BUCK_VS1_DBG0 (MT6389_PMIC_REG_BASE+0x18a6)
+#define MT6389_BUCK_VS1_DBG1 (MT6389_PMIC_REG_BASE+0x18a8)
+#define MT6389_BUCK_VS1_VOTER (MT6389_PMIC_REG_BASE+0x18aa)
+#define MT6389_BUCK_VS1_VOTER_SET (MT6389_PMIC_REG_BASE+0x18ac)
+#define MT6389_BUCK_VS1_VOTER_CLR (MT6389_PMIC_REG_BASE+0x18ae)
+#define MT6389_BUCK_VS1_VOTER_CFG (MT6389_PMIC_REG_BASE+0x18b0)
+#define MT6389_BUCK_VS1_ELR_NUM (MT6389_PMIC_REG_BASE+0x18b2)
+#define MT6389_BUCK_VS1_ELR0 (MT6389_PMIC_REG_BASE+0x18b4)
+#define MT6389_BUCK_VS2_DSN_ID (MT6389_PMIC_REG_BASE+0x1900)
+#define MT6389_BUCK_VS2_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1902)
+#define MT6389_BUCK_VS2_DSN_DBI (MT6389_PMIC_REG_BASE+0x1904)
+#define MT6389_BUCK_VS2_DSN_DXI (MT6389_PMIC_REG_BASE+0x1906)
+#define MT6389_BUCK_VS2_CON0 (MT6389_PMIC_REG_BASE+0x1908)
+#define MT6389_BUCK_VS2_CON0_SET (MT6389_PMIC_REG_BASE+0x190a)
+#define MT6389_BUCK_VS2_CON0_CLR (MT6389_PMIC_REG_BASE+0x190c)
+#define MT6389_BUCK_VS2_CON1 (MT6389_PMIC_REG_BASE+0x190e)
+#define MT6389_BUCK_VS2_SLP_CON (MT6389_PMIC_REG_BASE+0x1910)
+#define MT6389_BUCK_VS2_CFG0 (MT6389_PMIC_REG_BASE+0x1912)
+#define MT6389_BUCK_VS2_OP_EN (MT6389_PMIC_REG_BASE+0x1914)
+#define MT6389_BUCK_VS2_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1916)
+#define MT6389_BUCK_VS2_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1918)
+#define MT6389_BUCK_VS2_OP_CFG (MT6389_PMIC_REG_BASE+0x191a)
+#define MT6389_BUCK_VS2_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x191c)
+#define MT6389_BUCK_VS2_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x191e)
+#define MT6389_BUCK_VS2_OP_MODE (MT6389_PMIC_REG_BASE+0x1920)
+#define MT6389_BUCK_VS2_OP_MODE_SET (MT6389_PMIC_REG_BASE+0x1922)
+#define MT6389_BUCK_VS2_OP_MODE_CLR (MT6389_PMIC_REG_BASE+0x1924)
+#define MT6389_BUCK_VS2_DBG0 (MT6389_PMIC_REG_BASE+0x1926)
+#define MT6389_BUCK_VS2_DBG1 (MT6389_PMIC_REG_BASE+0x1928)
+#define MT6389_BUCK_VS2_VOTER (MT6389_PMIC_REG_BASE+0x192a)
+#define MT6389_BUCK_VS2_VOTER_SET (MT6389_PMIC_REG_BASE+0x192c)
+#define MT6389_BUCK_VS2_VOTER_CLR (MT6389_PMIC_REG_BASE+0x192e)
+#define MT6389_BUCK_VS2_VOTER_CFG (MT6389_PMIC_REG_BASE+0x1930)
+#define MT6389_BUCK_VS2_ELR_NUM (MT6389_PMIC_REG_BASE+0x1932)
+#define MT6389_BUCK_VS2_ELR0 (MT6389_PMIC_REG_BASE+0x1934)
+#define MT6389_BUCK_VPA_DSN_ID (MT6389_PMIC_REG_BASE+0x1980)
+#define MT6389_BUCK_VPA_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1982)
+#define MT6389_BUCK_VPA_DSN_DBI (MT6389_PMIC_REG_BASE+0x1984)
+#define MT6389_BUCK_VPA_DSN_DXI (MT6389_PMIC_REG_BASE+0x1986)
+#define MT6389_BUCK_VPA_CON0 (MT6389_PMIC_REG_BASE+0x1988)
+#define MT6389_BUCK_VPA_CON0_SET (MT6389_PMIC_REG_BASE+0x198a)
+#define MT6389_BUCK_VPA_CON0_CLR (MT6389_PMIC_REG_BASE+0x198c)
+#define MT6389_BUCK_VPA_CON1 (MT6389_PMIC_REG_BASE+0x198e)
+#define MT6389_BUCK_VPA_CFG0 (MT6389_PMIC_REG_BASE+0x1990)
+#define MT6389_BUCK_VPA_DBG0 (MT6389_PMIC_REG_BASE+0x1992)
+#define MT6389_BUCK_VPA_DBG1 (MT6389_PMIC_REG_BASE+0x1994)
+#define MT6389_BUCK_VPA_DLC_CON0 (MT6389_PMIC_REG_BASE+0x1996)
+#define MT6389_BUCK_VPA_DLC_CON1 (MT6389_PMIC_REG_BASE+0x1998)
+#define MT6389_BUCK_VPA_DLC_CON2 (MT6389_PMIC_REG_BASE+0x199a)
+#define MT6389_BUCK_VPA_MSFG_CON0 (MT6389_PMIC_REG_BASE+0x199c)
+#define MT6389_BUCK_VPA_MSFG_CON1 (MT6389_PMIC_REG_BASE+0x199e)
+#define MT6389_BUCK_VPA_MSFG_RRATE0 (MT6389_PMIC_REG_BASE+0x19a0)
+#define MT6389_BUCK_VPA_MSFG_RRATE1 (MT6389_PMIC_REG_BASE+0x19a2)
+#define MT6389_BUCK_VPA_MSFG_RRATE2 (MT6389_PMIC_REG_BASE+0x19a4)
+#define MT6389_BUCK_VPA_MSFG_RTHD0 (MT6389_PMIC_REG_BASE+0x19a6)
+#define MT6389_BUCK_VPA_MSFG_RTHD1 (MT6389_PMIC_REG_BASE+0x19a8)
+#define MT6389_BUCK_VPA_MSFG_RTHD2 (MT6389_PMIC_REG_BASE+0x19aa)
+#define MT6389_BUCK_VPA_MSFG_FRATE0 (MT6389_PMIC_REG_BASE+0x19ac)
+#define MT6389_BUCK_VPA_MSFG_FRATE1 (MT6389_PMIC_REG_BASE+0x19ae)
+#define MT6389_BUCK_VPA_MSFG_FRATE2 (MT6389_PMIC_REG_BASE+0x19b0)
+#define MT6389_BUCK_VPA_MSFG_FTHD0 (MT6389_PMIC_REG_BASE+0x19b2)
+#define MT6389_BUCK_VPA_MSFG_FTHD1 (MT6389_PMIC_REG_BASE+0x19b4)
+#define MT6389_BUCK_VPA_MSFG_FTHD2 (MT6389_PMIC_REG_BASE+0x19b6)
+#define MT6389_BUCK_ANA0_DSN_ID (MT6389_PMIC_REG_BASE+0x1a00)
+#define MT6389_BUCK_ANA0_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1a02)
+#define MT6389_BUCK_ANA0_DSN_DBI (MT6389_PMIC_REG_BASE+0x1a04)
+#define MT6389_BUCK_ANA0_DSN_FPI (MT6389_PMIC_REG_BASE+0x1a06)
+#define MT6389_SMPS_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a08)
+#define MT6389_VPROC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a0a)
+#define MT6389_VPROC_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1a0c)
+#define MT6389_VPROC_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1a0e)
+#define MT6389_VPROC_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1a10)
+#define MT6389_VPROC_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1a12)
+#define MT6389_VPROC_ANA_CON5 (MT6389_PMIC_REG_BASE+0x1a14)
+#define MT6389_VCORE_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a16)
+#define MT6389_VCORE_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1a18)
+#define MT6389_VCORE_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1a1a)
+#define MT6389_VCORE_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1a1c)
+#define MT6389_VCORE_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1a1e)
+#define MT6389_VCORE_ANA_CON5 (MT6389_PMIC_REG_BASE+0x1a20)
+#define MT6389_BUCK_ANA0_ELR_NUM (MT6389_PMIC_REG_BASE+0x1a22)
+#define MT6389_SMPS_ELR_0 (MT6389_PMIC_REG_BASE+0x1a24)
+#define MT6389_SMPS_ELR_1 (MT6389_PMIC_REG_BASE+0x1a26)
+#define MT6389_SMPS_ELR_2 (MT6389_PMIC_REG_BASE+0x1a28)
+#define MT6389_SMPS_ELR_3 (MT6389_PMIC_REG_BASE+0x1a2a)
+#define MT6389_SMPS_ELR_4 (MT6389_PMIC_REG_BASE+0x1a2c)
+#define MT6389_SMPS_ELR_5 (MT6389_PMIC_REG_BASE+0x1a2e)
+#define MT6389_SMPS_ELR_6 (MT6389_PMIC_REG_BASE+0x1a30)
+#define MT6389_SMPS_ELR_7 (MT6389_PMIC_REG_BASE+0x1a32)
+#define MT6389_SMPS_ELR_8 (MT6389_PMIC_REG_BASE+0x1a34)
+#define MT6389_SMPS_ELR_9 (MT6389_PMIC_REG_BASE+0x1a36)
+#define MT6389_SMPS_ELR_10 (MT6389_PMIC_REG_BASE+0x1a38)
+#define MT6389_BUCK_ANA1_DSN_ID (MT6389_PMIC_REG_BASE+0x1a80)
+#define MT6389_BUCK_ANA1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1a82)
+#define MT6389_BUCK_ANA1_DSN_DBI (MT6389_PMIC_REG_BASE+0x1a84)
+#define MT6389_BUCK_ANA1_DSN_FPI (MT6389_PMIC_REG_BASE+0x1a86)
+#define MT6389_VMODEM_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a88)
+#define MT6389_VMODEM_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1a8a)
+#define MT6389_VMODEM_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1a8c)
+#define MT6389_VMODEM_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1a8e)
+#define MT6389_VMODEM_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1a90)
+#define MT6389_VMODEM_ANA_CON5 (MT6389_PMIC_REG_BASE+0x1a92)
+#define MT6389_VS1_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a94)
+#define MT6389_VS1_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1a96)
+#define MT6389_VS1_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1a98)
+#define MT6389_VS1_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1a9a)
+#define MT6389_VS1_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1a9c)
+#define MT6389_VS2_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1a9e)
+#define MT6389_VS2_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1aa0)
+#define MT6389_VS2_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1aa2)
+#define MT6389_VS2_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1aa4)
+#define MT6389_VS2_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1aa6)
+#define MT6389_VPA_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1aa8)
+#define MT6389_VPA_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1aaa)
+#define MT6389_VPA_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1aac)
+#define MT6389_VPA_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1aae)
+#define MT6389_VPA_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1ab0)
+#define MT6389_VPA_ANA_CON5 (MT6389_PMIC_REG_BASE+0x1ab2)
+#define MT6389_VPA_ANA_CON6 (MT6389_PMIC_REG_BASE+0x1ab4)
+#define MT6389_VDRAM1_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1ab6)
+#define MT6389_VDRAM1_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1ab8)
+#define MT6389_VDRAM1_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1aba)
+#define MT6389_VDRAM1_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1abc)
+#define MT6389_VDRAM1_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1abe)
+#define MT6389_VSRAM_OTHERS_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1ac0)
+#define MT6389_VSRAM_OTHERS_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1ac2)
+#define MT6389_VSRAM_OTHERS_ANA_CON2 (MT6389_PMIC_REG_BASE+0x1ac4)
+#define MT6389_VSRAM_OTHERS_ANA_CON3 (MT6389_PMIC_REG_BASE+0x1ac6)
+#define MT6389_VSRAM_OTHERS_ANA_CON4 (MT6389_PMIC_REG_BASE+0x1ac8)
+#define MT6389_VSRAM_OTHERS_ANA_CON5 (MT6389_PMIC_REG_BASE+0x1aca)
+#define MT6389_BUCK_ANA1_ELR_NUM (MT6389_PMIC_REG_BASE+0x1acc)
+#define MT6389_VMODEM_ELR_0 (MT6389_PMIC_REG_BASE+0x1ace)
+#define MT6389_VMODEM_ELR_1 (MT6389_PMIC_REG_BASE+0x1ad0)
+#define MT6389_VMODEM_ELR_2 (MT6389_PMIC_REG_BASE+0x1ad2)
+#define MT6389_VMODEM_ELR_3 (MT6389_PMIC_REG_BASE+0x1ad4)
+#define MT6389_VMODEM_ELR_4 (MT6389_PMIC_REG_BASE+0x1ad6)
+#define MT6389_VMODEM_ELR_5 (MT6389_PMIC_REG_BASE+0x1ad8)
+#define MT6389_VMODEM_ELR_6 (MT6389_PMIC_REG_BASE+0x1ada)
+#define MT6389_VMODEM_ELR_7 (MT6389_PMIC_REG_BASE+0x1adc)
+#define MT6389_VMODEM_ELR_8 (MT6389_PMIC_REG_BASE+0x1ade)
+#define MT6389_VMODEM_ELR_9 (MT6389_PMIC_REG_BASE+0x1ae0)
+#define MT6389_VMODEM_ELR_10 (MT6389_PMIC_REG_BASE+0x1ae2)
+#define MT6389_VMODEM_ELR_11 (MT6389_PMIC_REG_BASE+0x1ae4)
+#define MT6389_VMODEM_ELR_12 (MT6389_PMIC_REG_BASE+0x1ae6)
+#define MT6389_VMODEM_ELR_13 (MT6389_PMIC_REG_BASE+0x1ae8)
+#define MT6389_VMODEM_ELR_14 (MT6389_PMIC_REG_BASE+0x1aea)
+#define MT6389_VMODEM_ELR_15 (MT6389_PMIC_REG_BASE+0x1aec)
+#define MT6389_VMODEM_ELR_16 (MT6389_PMIC_REG_BASE+0x1aee)
+#define MT6389_VMODEM_ELR_17 (MT6389_PMIC_REG_BASE+0x1af0)
+#define MT6389_VMODEM_ELR_18 (MT6389_PMIC_REG_BASE+0x1af2)
+#define MT6389_LDO_TOP_ID (MT6389_PMIC_REG_BASE+0x1c80)
+#define MT6389_LDO_TOP_REV0 (MT6389_PMIC_REG_BASE+0x1c82)
+#define MT6389_LDO_TOP_DBI (MT6389_PMIC_REG_BASE+0x1c84)
+#define MT6389_LDO_TOP_DXI (MT6389_PMIC_REG_BASE+0x1c86)
+#define MT6389_LDO_TPM0 (MT6389_PMIC_REG_BASE+0x1c88)
+#define MT6389_LDO_TPM1 (MT6389_PMIC_REG_BASE+0x1c8a)
+#define MT6389_LDO_TOP_CKPDN_CON0 (MT6389_PMIC_REG_BASE+0x1c8c)
+#define MT6389_TOP_TOP_CKHWEN_CON0 (MT6389_PMIC_REG_BASE+0x1c8e)
+#define MT6389_LDO_TOP_CLK_DCM_CON0 (MT6389_PMIC_REG_BASE+0x1c90)
+#define MT6389_LDO_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x1c92)
+#define MT6389_LDO_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x1c94)
+#define MT6389_LDO_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x1c96)
+#define MT6389_LDO_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x1c98)
+#define MT6389_LDO_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x1c9a)
+#define MT6389_LDO_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x1c9c)
+#define MT6389_LDO_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x1c9e)
+#define MT6389_LDO_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x1ca0)
+#define MT6389_LDO_TOP_INT_MASK_CON1 (MT6389_PMIC_REG_BASE+0x1ca2)
+#define MT6389_LDO_TOP_INT_MASK_CON1_SET (MT6389_PMIC_REG_BASE+0x1ca4)
+#define MT6389_LDO_TOP_INT_MASK_CON1_CLR (MT6389_PMIC_REG_BASE+0x1ca6)
+#define MT6389_LDO_TOP_INT_CON1 (MT6389_PMIC_REG_BASE+0x1ca8)
+#define MT6389_LDO_TOP_INT_CON1_SET (MT6389_PMIC_REG_BASE+0x1caa)
+#define MT6389_LDO_TOP_INT_CON1_CLR (MT6389_PMIC_REG_BASE+0x1cac)
+#define MT6389_LDO_TOP_INT_STATUS1 (MT6389_PMIC_REG_BASE+0x1cae)
+#define MT6389_LDO_TOP_INT_RAW_STATUS1 (MT6389_PMIC_REG_BASE+0x1cb0)
+#define MT6389_LDO_TEST_CON0 (MT6389_PMIC_REG_BASE+0x1cb2)
+#define MT6389_LDO_TOP_CON0 (MT6389_PMIC_REG_BASE+0x1cb4)
+#define MT6389_LDO_TOP_CON1 (MT6389_PMIC_REG_BASE+0x1cb6)
+#define MT6389_VRTC28_CON (MT6389_PMIC_REG_BASE+0x1cb8)
+#define MT6389_VAUX18_ACK (MT6389_PMIC_REG_BASE+0x1cba)
+#define MT6389_TREF_CON (MT6389_PMIC_REG_BASE+0x1cbc)
+#define MT6389_VOW_DVS_CON (MT6389_PMIC_REG_BASE+0x1cbe)
+#define MT6389_VDRAM2_MON (MT6389_PMIC_REG_BASE+0x1cc0)
+#define MT6389_LDO_TOP_ELR_NUM (MT6389_PMIC_REG_BASE+0x1cc2)
+#define MT6389_LDO_TOP_ELR (MT6389_PMIC_REG_BASE+0x1cc4)
+#define MT6389_LDO_VDRAM2_ELR_0 (MT6389_PMIC_REG_BASE+0x1cc6)
+#define MT6389_LDO_VDRAM2_ELR_1 (MT6389_PMIC_REG_BASE+0x1cc8)
+#define MT6389_LDO_GNR0_DSN_ID (MT6389_PMIC_REG_BASE+0x1d00)
+#define MT6389_LDO_GNR0_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1d02)
+#define MT6389_LDO_GNR0_DSN_DBI (MT6389_PMIC_REG_BASE+0x1d04)
+#define MT6389_LDO_GNR0_DSN_DXI (MT6389_PMIC_REG_BASE+0x1d06)
+#define MT6389_LDO_VFE28_CON0 (MT6389_PMIC_REG_BASE+0x1d08)
+#define MT6389_LDO_VFE28_CON1 (MT6389_PMIC_REG_BASE+0x1d0a)
+#define MT6389_LDO_VFE28_MON (MT6389_PMIC_REG_BASE+0x1d0c)
+#define MT6389_LDO_VFE28_OP_EN (MT6389_PMIC_REG_BASE+0x1d0e)
+#define MT6389_LDO_VFE28_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d10)
+#define MT6389_LDO_VFE28_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d12)
+#define MT6389_LDO_VFE28_OP_CFG (MT6389_PMIC_REG_BASE+0x1d14)
+#define MT6389_LDO_VFE28_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d16)
+#define MT6389_LDO_VFE28_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d18)
+#define MT6389_LDO_VRF18_CON0 (MT6389_PMIC_REG_BASE+0x1d1a)
+#define MT6389_LDO_VRF18_CON1 (MT6389_PMIC_REG_BASE+0x1d1c)
+#define MT6389_LDO_VRF18_MON (MT6389_PMIC_REG_BASE+0x1d1e)
+#define MT6389_LDO_VRF18_OP_EN (MT6389_PMIC_REG_BASE+0x1d20)
+#define MT6389_LDO_VRF18_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d22)
+#define MT6389_LDO_VRF18_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d24)
+#define MT6389_LDO_VRF18_OP_CFG (MT6389_PMIC_REG_BASE+0x1d26)
+#define MT6389_LDO_VRF18_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d28)
+#define MT6389_LDO_VRF18_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d2a)
+#define MT6389_LDO_VRF12_CON0 (MT6389_PMIC_REG_BASE+0x1d2c)
+#define MT6389_LDO_VRF12_CON1 (MT6389_PMIC_REG_BASE+0x1d2e)
+#define MT6389_LDO_VRF12_MON (MT6389_PMIC_REG_BASE+0x1d30)
+#define MT6389_LDO_VRF12_OP_EN (MT6389_PMIC_REG_BASE+0x1d32)
+#define MT6389_LDO_VRF12_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d34)
+#define MT6389_LDO_VRF12_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d36)
+#define MT6389_LDO_VRF12_OP_CFG (MT6389_PMIC_REG_BASE+0x1d38)
+#define MT6389_LDO_VRF12_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d3a)
+#define MT6389_LDO_VRF12_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d3c)
+#define MT6389_LDO_VGP3_CON0 (MT6389_PMIC_REG_BASE+0x1d3e)
+#define MT6389_LDO_VGP3_CON1 (MT6389_PMIC_REG_BASE+0x1d40)
+#define MT6389_LDO_VGP3_MON (MT6389_PMIC_REG_BASE+0x1d42)
+#define MT6389_LDO_VGP3_OP_EN (MT6389_PMIC_REG_BASE+0x1d44)
+#define MT6389_LDO_VGP3_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d46)
+#define MT6389_LDO_VGP3_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d48)
+#define MT6389_LDO_VGP3_OP_CFG (MT6389_PMIC_REG_BASE+0x1d4a)
+#define MT6389_LDO_VGP3_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d4c)
+#define MT6389_LDO_VGP3_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d4e)
+#define MT6389_LDO_VCN33_CON0 (MT6389_PMIC_REG_BASE+0x1d50)
+#define MT6389_LDO_VCN33_CON1 (MT6389_PMIC_REG_BASE+0x1d52)
+#define MT6389_LDO_VCN33_MON (MT6389_PMIC_REG_BASE+0x1d54)
+#define MT6389_LDO_VCN33_OP_EN (MT6389_PMIC_REG_BASE+0x1d56)
+#define MT6389_LDO_VCN33_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d58)
+#define MT6389_LDO_VCN33_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d5a)
+#define MT6389_LDO_VCN33_OP_CFG (MT6389_PMIC_REG_BASE+0x1d5c)
+#define MT6389_LDO_VCN33_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d5e)
+#define MT6389_LDO_VCN33_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d60)
+#define MT6389_LDO_VCN33_MULTI_SW (MT6389_PMIC_REG_BASE+0x1d62)
+#define MT6389_LDO_VCN18_CON0 (MT6389_PMIC_REG_BASE+0x1d64)
+#define MT6389_LDO_VCN18_CON1 (MT6389_PMIC_REG_BASE+0x1d66)
+#define MT6389_LDO_VCN18_MON (MT6389_PMIC_REG_BASE+0x1d68)
+#define MT6389_LDO_VCN18_OP_EN (MT6389_PMIC_REG_BASE+0x1d6a)
+#define MT6389_LDO_VCN18_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d6c)
+#define MT6389_LDO_VCN18_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d6e)
+#define MT6389_LDO_VCN18_OP_CFG (MT6389_PMIC_REG_BASE+0x1d70)
+#define MT6389_LDO_VCN18_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d72)
+#define MT6389_LDO_VCN18_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d74)
+#define MT6389_LDO_GNR1_DSN_ID (MT6389_PMIC_REG_BASE+0x1d80)
+#define MT6389_LDO_GNR1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1d82)
+#define MT6389_LDO_GNR1_DSN_DBI (MT6389_PMIC_REG_BASE+0x1d84)
+#define MT6389_LDO_GNR1_DSN_DXI (MT6389_PMIC_REG_BASE+0x1d86)
+#define MT6389_LDO_VA12_CON0 (MT6389_PMIC_REG_BASE+0x1d88)
+#define MT6389_LDO_VA12_CON1 (MT6389_PMIC_REG_BASE+0x1d8a)
+#define MT6389_LDO_VA12_MON (MT6389_PMIC_REG_BASE+0x1d8c)
+#define MT6389_LDO_VA12_OP_EN (MT6389_PMIC_REG_BASE+0x1d8e)
+#define MT6389_LDO_VA12_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1d90)
+#define MT6389_LDO_VA12_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1d92)
+#define MT6389_LDO_VA12_OP_CFG (MT6389_PMIC_REG_BASE+0x1d94)
+#define MT6389_LDO_VA12_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1d96)
+#define MT6389_LDO_VA12_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1d98)
+#define MT6389_LDO_VA09_CON0 (MT6389_PMIC_REG_BASE+0x1d9a)
+#define MT6389_LDO_VA09_CON1 (MT6389_PMIC_REG_BASE+0x1d9c)
+#define MT6389_LDO_VA09_MON (MT6389_PMIC_REG_BASE+0x1d9e)
+#define MT6389_LDO_VA09_OP_EN (MT6389_PMIC_REG_BASE+0x1da0)
+#define MT6389_LDO_VA09_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1da2)
+#define MT6389_LDO_VA09_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1da4)
+#define MT6389_LDO_VA09_OP_CFG (MT6389_PMIC_REG_BASE+0x1da6)
+#define MT6389_LDO_VA09_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1da8)
+#define MT6389_LDO_VA09_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1daa)
+#define MT6389_LDO_VAUX18_CON0 (MT6389_PMIC_REG_BASE+0x1dac)
+#define MT6389_LDO_VAUX18_CON1 (MT6389_PMIC_REG_BASE+0x1dae)
+#define MT6389_LDO_VAUX18_MON (MT6389_PMIC_REG_BASE+0x1db0)
+#define MT6389_LDO_VAUX18_OP_EN (MT6389_PMIC_REG_BASE+0x1db2)
+#define MT6389_LDO_VAUX18_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1db4)
+#define MT6389_LDO_VAUX18_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1db6)
+#define MT6389_LDO_VAUX18_OP_CFG (MT6389_PMIC_REG_BASE+0x1db8)
+#define MT6389_LDO_VAUX18_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1dba)
+#define MT6389_LDO_VAUX18_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1dbc)
+#define MT6389_LDO_VAUD28_CON0 (MT6389_PMIC_REG_BASE+0x1dbe)
+#define MT6389_LDO_VAUD28_CON1 (MT6389_PMIC_REG_BASE+0x1dc0)
+#define MT6389_LDO_VAUD28_MON (MT6389_PMIC_REG_BASE+0x1dc2)
+#define MT6389_LDO_VAUD28_OP_EN (MT6389_PMIC_REG_BASE+0x1dc4)
+#define MT6389_LDO_VAUD28_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1dc6)
+#define MT6389_LDO_VAUD28_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1dc8)
+#define MT6389_LDO_VAUD28_OP_CFG (MT6389_PMIC_REG_BASE+0x1dca)
+#define MT6389_LDO_VAUD28_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1dcc)
+#define MT6389_LDO_VAUD28_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1dce)
+#define MT6389_LDO_VIO18_CON0 (MT6389_PMIC_REG_BASE+0x1dd0)
+#define MT6389_LDO_VIO18_CON1 (MT6389_PMIC_REG_BASE+0x1dd2)
+#define MT6389_LDO_VIO18_MON (MT6389_PMIC_REG_BASE+0x1dd4)
+#define MT6389_LDO_VIO18_OP_EN (MT6389_PMIC_REG_BASE+0x1dd6)
+#define MT6389_LDO_VIO18_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1dd8)
+#define MT6389_LDO_VIO18_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1dda)
+#define MT6389_LDO_VIO18_OP_CFG (MT6389_PMIC_REG_BASE+0x1ddc)
+#define MT6389_LDO_VIO18_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1dde)
+#define MT6389_LDO_VIO18_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1de0)
+#define MT6389_LDO_VIO33_CON0 (MT6389_PMIC_REG_BASE+0x1de2)
+#define MT6389_LDO_VIO33_CON1 (MT6389_PMIC_REG_BASE+0x1de4)
+#define MT6389_LDO_VIO33_MON (MT6389_PMIC_REG_BASE+0x1de6)
+#define MT6389_LDO_VIO33_OP_EN (MT6389_PMIC_REG_BASE+0x1de8)
+#define MT6389_LDO_VIO33_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1dea)
+#define MT6389_LDO_VIO33_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1dec)
+#define MT6389_LDO_VIO33_OP_CFG (MT6389_PMIC_REG_BASE+0x1dee)
+#define MT6389_LDO_VIO33_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1df0)
+#define MT6389_LDO_VIO33_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1df2)
+#define MT6389_LDO_GNR2_DSN_ID (MT6389_PMIC_REG_BASE+0x1e00)
+#define MT6389_LDO_GNR2_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1e02)
+#define MT6389_LDO_GNR2_DSN_DBI (MT6389_PMIC_REG_BASE+0x1e04)
+#define MT6389_LDO_GNR2_DSN_DXI (MT6389_PMIC_REG_BASE+0x1e06)
+#define MT6389_LDO_VGP1_CON0 (MT6389_PMIC_REG_BASE+0x1e08)
+#define MT6389_LDO_VGP1_CON1 (MT6389_PMIC_REG_BASE+0x1e0a)
+#define MT6389_LDO_VGP1_MON (MT6389_PMIC_REG_BASE+0x1e0c)
+#define MT6389_LDO_VGP1_OP_EN (MT6389_PMIC_REG_BASE+0x1e0e)
+#define MT6389_LDO_VGP1_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e10)
+#define MT6389_LDO_VGP1_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e12)
+#define MT6389_LDO_VGP1_OP_CFG (MT6389_PMIC_REG_BASE+0x1e14)
+#define MT6389_LDO_VGP1_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e16)
+#define MT6389_LDO_VGP1_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e18)
+#define MT6389_LDO_VGP2_CON0 (MT6389_PMIC_REG_BASE+0x1e1a)
+#define MT6389_LDO_VGP2_CON1 (MT6389_PMIC_REG_BASE+0x1e1c)
+#define MT6389_LDO_VGP2_MON (MT6389_PMIC_REG_BASE+0x1e1e)
+#define MT6389_LDO_VGP2_OP_EN (MT6389_PMIC_REG_BASE+0x1e20)
+#define MT6389_LDO_VGP2_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e22)
+#define MT6389_LDO_VGP2_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e24)
+#define MT6389_LDO_VGP2_OP_CFG (MT6389_PMIC_REG_BASE+0x1e26)
+#define MT6389_LDO_VGP2_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e28)
+#define MT6389_LDO_VGP2_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e2a)
+#define MT6389_LDO_VDRAM2_CON0 (MT6389_PMIC_REG_BASE+0x1e2c)
+#define MT6389_LDO_VDRAM2_CON1 (MT6389_PMIC_REG_BASE+0x1e2e)
+#define MT6389_LDO_VDRAM2_MON (MT6389_PMIC_REG_BASE+0x1e30)
+#define MT6389_LDO_VDRAM2_OP_EN (MT6389_PMIC_REG_BASE+0x1e32)
+#define MT6389_LDO_VDRAM2_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e34)
+#define MT6389_LDO_VDRAM2_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e36)
+#define MT6389_LDO_VDRAM2_OP_CFG (MT6389_PMIC_REG_BASE+0x1e38)
+#define MT6389_LDO_VDRAM2_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e3a)
+#define MT6389_LDO_VDRAM2_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e3c)
+#define MT6389_LDO_VMCH_CON0 (MT6389_PMIC_REG_BASE+0x1e3e)
+#define MT6389_LDO_VMCH_CON1 (MT6389_PMIC_REG_BASE+0x1e40)
+#define MT6389_LDO_VMCH_MON (MT6389_PMIC_REG_BASE+0x1e42)
+#define MT6389_LDO_VMCH_OP_EN (MT6389_PMIC_REG_BASE+0x1e44)
+#define MT6389_LDO_VMCH_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e46)
+#define MT6389_LDO_VMCH_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e48)
+#define MT6389_LDO_VMCH_OP_CFG (MT6389_PMIC_REG_BASE+0x1e4a)
+#define MT6389_LDO_VMCH_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e4c)
+#define MT6389_LDO_VMCH_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e4e)
+#define MT6389_LDO_VMCH_EINT (MT6389_PMIC_REG_BASE+0x1e50)
+#define MT6389_LDO_VEMC_CON0 (MT6389_PMIC_REG_BASE+0x1e52)
+#define MT6389_LDO_VEMC_CON1 (MT6389_PMIC_REG_BASE+0x1e54)
+#define MT6389_LDO_VEMC_MON (MT6389_PMIC_REG_BASE+0x1e56)
+#define MT6389_LDO_VEMC_OP_EN (MT6389_PMIC_REG_BASE+0x1e58)
+#define MT6389_LDO_VEMC_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e5a)
+#define MT6389_LDO_VEMC_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e5c)
+#define MT6389_LDO_VEMC_OP_CFG (MT6389_PMIC_REG_BASE+0x1e5e)
+#define MT6389_LDO_VEMC_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e60)
+#define MT6389_LDO_VEMC_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e62)
+#define MT6389_LDO_VSIM1_CON0 (MT6389_PMIC_REG_BASE+0x1e64)
+#define MT6389_LDO_VSIM1_CON1 (MT6389_PMIC_REG_BASE+0x1e66)
+#define MT6389_LDO_VSIM1_MON (MT6389_PMIC_REG_BASE+0x1e68)
+#define MT6389_LDO_VSIM1_OP_EN (MT6389_PMIC_REG_BASE+0x1e6a)
+#define MT6389_LDO_VSIM1_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e6c)
+#define MT6389_LDO_VSIM1_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e6e)
+#define MT6389_LDO_VSIM1_OP_CFG (MT6389_PMIC_REG_BASE+0x1e70)
+#define MT6389_LDO_VSIM1_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e72)
+#define MT6389_LDO_VSIM1_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e74)
+#define MT6389_LDO_VSIM1_EINT (MT6389_PMIC_REG_BASE+0x1e76)
+#define MT6389_LDO_GNR3_DSN_ID (MT6389_PMIC_REG_BASE+0x1e80)
+#define MT6389_LDO_GNR3_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1e82)
+#define MT6389_LDO_GNR3_DSN_DBI (MT6389_PMIC_REG_BASE+0x1e84)
+#define MT6389_LDO_GNR3_DSN_DXI (MT6389_PMIC_REG_BASE+0x1e86)
+#define MT6389_LDO_VSIM2_CON0 (MT6389_PMIC_REG_BASE+0x1e88)
+#define MT6389_LDO_VSIM2_CON1 (MT6389_PMIC_REG_BASE+0x1e8a)
+#define MT6389_LDO_VSIM2_MON (MT6389_PMIC_REG_BASE+0x1e8c)
+#define MT6389_LDO_VSIM2_OP_EN (MT6389_PMIC_REG_BASE+0x1e8e)
+#define MT6389_LDO_VSIM2_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1e90)
+#define MT6389_LDO_VSIM2_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1e92)
+#define MT6389_LDO_VSIM2_OP_CFG (MT6389_PMIC_REG_BASE+0x1e94)
+#define MT6389_LDO_VSIM2_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1e96)
+#define MT6389_LDO_VSIM2_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1e98)
+#define MT6389_LDO_VSIM2_EINT (MT6389_PMIC_REG_BASE+0x1e9a)
+#define MT6389_LDO_VUSB_CON0 (MT6389_PMIC_REG_BASE+0x1e9c)
+#define MT6389_LDO_VUSB_CON1 (MT6389_PMIC_REG_BASE+0x1e9e)
+#define MT6389_LDO_VUSB_MON (MT6389_PMIC_REG_BASE+0x1ea0)
+#define MT6389_LDO_VUSB_OP_EN (MT6389_PMIC_REG_BASE+0x1ea2)
+#define MT6389_LDO_VUSB_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1ea4)
+#define MT6389_LDO_VUSB_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1ea6)
+#define MT6389_LDO_VUSB_OP_CFG (MT6389_PMIC_REG_BASE+0x1ea8)
+#define MT6389_LDO_VUSB_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1eaa)
+#define MT6389_LDO_VUSB_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1eac)
+#define MT6389_LDO_VXO22_CON0 (MT6389_PMIC_REG_BASE+0x1eae)
+#define MT6389_LDO_VXO22_CON1 (MT6389_PMIC_REG_BASE+0x1eb0)
+#define MT6389_LDO_VXO22_MON (MT6389_PMIC_REG_BASE+0x1eb2)
+#define MT6389_LDO_VXO22_OP_EN (MT6389_PMIC_REG_BASE+0x1eb4)
+#define MT6389_LDO_VXO22_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1eb6)
+#define MT6389_LDO_VXO22_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1eb8)
+#define MT6389_LDO_VXO22_OP_CFG (MT6389_PMIC_REG_BASE+0x1eba)
+#define MT6389_LDO_VXO22_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1ebc)
+#define MT6389_LDO_VXO22_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1ebe)
+#define MT6389_LDO_VRFCK_CON0 (MT6389_PMIC_REG_BASE+0x1ec0)
+#define MT6389_LDO_VRFCK_CON1 (MT6389_PMIC_REG_BASE+0x1ec2)
+#define MT6389_LDO_VRFCK_MON (MT6389_PMIC_REG_BASE+0x1ec4)
+#define MT6389_LDO_VRFCK_OP_EN (MT6389_PMIC_REG_BASE+0x1ec6)
+#define MT6389_LDO_VRFCK_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1ec8)
+#define MT6389_LDO_VRFCK_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1eca)
+#define MT6389_LDO_VRFCK_OP_CFG (MT6389_PMIC_REG_BASE+0x1ecc)
+#define MT6389_LDO_VRFCK_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1ece)
+#define MT6389_LDO_VRFCK_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1ed0)
+#define MT6389_LDO_VBBCK_CON0 (MT6389_PMIC_REG_BASE+0x1ed2)
+#define MT6389_LDO_VBBCK_CON1 (MT6389_PMIC_REG_BASE+0x1ed4)
+#define MT6389_LDO_VBBCK_MON (MT6389_PMIC_REG_BASE+0x1ed6)
+#define MT6389_LDO_VBBCK_OP_EN (MT6389_PMIC_REG_BASE+0x1ed8)
+#define MT6389_LDO_VBBCK_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1eda)
+#define MT6389_LDO_VBBCK_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1edc)
+#define MT6389_LDO_VBBCK_OP_CFG (MT6389_PMIC_REG_BASE+0x1ede)
+#define MT6389_LDO_VBBCK_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1ee0)
+#define MT6389_LDO_VBBCK_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1ee2)
+#define MT6389_LDO_VSRAM0_DSN_ID (MT6389_PMIC_REG_BASE+0x1f00)
+#define MT6389_LDO_VSRAM0_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1f02)
+#define MT6389_LDO_VSRAM0_DSN_DBI (MT6389_PMIC_REG_BASE+0x1f04)
+#define MT6389_LDO_VSRAM0_DSN_DXI (MT6389_PMIC_REG_BASE+0x1f06)
+#define MT6389_LDO_VSRAM_PROC_CON0 (MT6389_PMIC_REG_BASE+0x1f08)
+#define MT6389_LDO_VSRAM_PROC_CON1 (MT6389_PMIC_REG_BASE+0x1f0a)
+#define MT6389_LDO_VSRAM_PROC_MON (MT6389_PMIC_REG_BASE+0x1f0c)
+#define MT6389_LDO_VSRAM_PROC_VOSEL0 (MT6389_PMIC_REG_BASE+0x1f0e)
+#define MT6389_LDO_VSRAM_PROC_VOSEL1 (MT6389_PMIC_REG_BASE+0x1f10)
+#define MT6389_LDO_VSRAM_PROC_SFCHG (MT6389_PMIC_REG_BASE+0x1f12)
+#define MT6389_LDO_VSRAM_PROC_DVS (MT6389_PMIC_REG_BASE+0x1f14)
+#define MT6389_LDO_VSRAM_PROC_OP_EN (MT6389_PMIC_REG_BASE+0x1f16)
+#define MT6389_LDO_VSRAM_PROC_OP_EN_SET (MT6389_PMIC_REG_BASE+0x1f18)
+#define MT6389_LDO_VSRAM_PROC_OP_EN_CLR (MT6389_PMIC_REG_BASE+0x1f1a)
+#define MT6389_LDO_VSRAM_PROC_OP_CFG (MT6389_PMIC_REG_BASE+0x1f1c)
+#define MT6389_LDO_VSRAM_PROC_OP_CFG_SET (MT6389_PMIC_REG_BASE+0x1f1e)
+#define MT6389_LDO_VSRAM_PROC_OP_CFG_CLR (MT6389_PMIC_REG_BASE+0x1f20)
+#define MT6389_LDO_VSRAM_PROC_TRACK0 (MT6389_PMIC_REG_BASE+0x1f22)
+#define MT6389_LDO_VSRAM_PROC_TRACK1 (MT6389_PMIC_REG_BASE+0x1f24)
+#define MT6389_LDO_VSRAM_PROC_TRACK2 (MT6389_PMIC_REG_BASE+0x1f26)
+#define MT6389_LDO_VSRAM0_ELR_NUM (MT6389_PMIC_REG_BASE+0x1f28)
+#define MT6389_LDO_VSRAM_PROC_ELR_0 (MT6389_PMIC_REG_BASE+0x1f2a)
+#define MT6389_LDO_VSRAM_PROC_ELR_1 (MT6389_PMIC_REG_BASE+0x1f2c)
+#define MT6389_LDO_ANA0_DSN_ID (MT6389_PMIC_REG_BASE+0x1f80)
+#define MT6389_LDO_ANA0_DSN_REV0 (MT6389_PMIC_REG_BASE+0x1f82)
+#define MT6389_LDO_ANA0_DSN_DBI (MT6389_PMIC_REG_BASE+0x1f84)
+#define MT6389_LDO_ANA0_DSN_FPI (MT6389_PMIC_REG_BASE+0x1f86)
+#define MT6389_VFE28_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f88)
+#define MT6389_VFE28_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f8a)
+#define MT6389_VAUX18_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f8c)
+#define MT6389_VAUX18_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f8e)
+#define MT6389_VAUD28_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f90)
+#define MT6389_VAUD28_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f92)
+#define MT6389_VUSB_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f94)
+#define MT6389_VUSB_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f96)
+#define MT6389_VCN33_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f98)
+#define MT6389_VCN33_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f9a)
+#define MT6389_VEMC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1f9c)
+#define MT6389_VEMC_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1f9e)
+#define MT6389_VSIM1_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fa0)
+#define MT6389_VSIM1_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1fa2)
+#define MT6389_VSIM2_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fa4)
+#define MT6389_VSIM2_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1fa6)
+#define MT6389_VMCH_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fa8)
+#define MT6389_VMCH_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1faa)
+#define MT6389_VIO33_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fac)
+#define MT6389_VIO33_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1fae)
+#define MT6389_VGP1_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fb0)
+#define MT6389_VGP1_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1fb2)
+#define MT6389_VGP2_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fb4)
+#define MT6389_VGP2_ANA_CON1 (MT6389_PMIC_REG_BASE+0x1fb6)
+#define MT6389_ADLDO_ANA_CON0 (MT6389_PMIC_REG_BASE+0x1fb8)
+#define MT6389_LDO_ANA0_ELR_NUM (MT6389_PMIC_REG_BASE+0x1fba)
+#define MT6389_VFE28_ELR_0 (MT6389_PMIC_REG_BASE+0x1fbc)
+#define MT6389_VFE28_ELR_1 (MT6389_PMIC_REG_BASE+0x1fbe)
+#define MT6389_VFE28_ELR_2 (MT6389_PMIC_REG_BASE+0x1fc0)
+#define MT6389_VFE28_ELR_3 (MT6389_PMIC_REG_BASE+0x1fc2)
+#define MT6389_VFE28_ELR_4 (MT6389_PMIC_REG_BASE+0x1fc4)
+#define MT6389_VFE28_ELR_5 (MT6389_PMIC_REG_BASE+0x1fc6)
+#define MT6389_LDO_ANA1_DSN_ID (MT6389_PMIC_REG_BASE+0x2000)
+#define MT6389_LDO_ANA1_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2002)
+#define MT6389_LDO_ANA1_DSN_DBI (MT6389_PMIC_REG_BASE+0x2004)
+#define MT6389_LDO_ANA1_DSN_FPI (MT6389_PMIC_REG_BASE+0x2006)
+#define MT6389_VRF18_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2008)
+#define MT6389_VRF18_ANA_CON1 (MT6389_PMIC_REG_BASE+0x200a)
+#define MT6389_VGP3_ANA_CON0 (MT6389_PMIC_REG_BASE+0x200c)
+#define MT6389_VGP3_ANA_CON1 (MT6389_PMIC_REG_BASE+0x200e)
+#define MT6389_VCN18_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2010)
+#define MT6389_VCN18_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2012)
+#define MT6389_VIO18_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2014)
+#define MT6389_VIO18_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2016)
+#define MT6389_SLDO20_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2018)
+#define MT6389_VRF12_ANA_CON0 (MT6389_PMIC_REG_BASE+0x201a)
+#define MT6389_VRF12_ANA_CON1 (MT6389_PMIC_REG_BASE+0x201c)
+#define MT6389_VA09_ANA_CON0 (MT6389_PMIC_REG_BASE+0x201e)
+#define MT6389_VA09_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2020)
+#define MT6389_VA12_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2022)
+#define MT6389_VA12_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2024)
+#define MT6389_VSRAM_PROC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2026)
+#define MT6389_VDRAM2_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2028)
+#define MT6389_SLDO14_ANA_CON0 (MT6389_PMIC_REG_BASE+0x202a)
+#define MT6389_LDO_ANA1_ELR_NUM (MT6389_PMIC_REG_BASE+0x202c)
+#define MT6389_VRF18_ELR_0 (MT6389_PMIC_REG_BASE+0x202e)
+#define MT6389_VRF18_ELR_1 (MT6389_PMIC_REG_BASE+0x2030)
+#define MT6389_VRF18_ELR_2 (MT6389_PMIC_REG_BASE+0x2032)
+#define MT6389_VRF18_ELR_3 (MT6389_PMIC_REG_BASE+0x2034)
+#define MT6389_VRF18_ELR_4 (MT6389_PMIC_REG_BASE+0x2036)
+#define MT6389_LDO_ANA2_DSN_ID (MT6389_PMIC_REG_BASE+0x2080)
+#define MT6389_LDO_ANA2_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2082)
+#define MT6389_LDO_ANA2_DSN_DBI (MT6389_PMIC_REG_BASE+0x2084)
+#define MT6389_LDO_ANA2_DSN_FPI (MT6389_PMIC_REG_BASE+0x2086)
+#define MT6389_VXO22_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2088)
+#define MT6389_VXO22_ANA_CON1 (MT6389_PMIC_REG_BASE+0x208a)
+#define MT6389_VRFCK_ANA_CON0 (MT6389_PMIC_REG_BASE+0x208c)
+#define MT6389_VRFCK_ANA_CON1 (MT6389_PMIC_REG_BASE+0x208e)
+#define MT6389_VRFCK_1_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2090)
+#define MT6389_VRFCK_1_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2092)
+#define MT6389_VBBCK_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2094)
+#define MT6389_VBBCK_ANA_CON1 (MT6389_PMIC_REG_BASE+0x2096)
+#define MT6389_LDO_ANA2_ELR_NUM (MT6389_PMIC_REG_BASE+0x2098)
+#define MT6389_DCXO_ADLDO_BIAS_ELR_0 (MT6389_PMIC_REG_BASE+0x209a)
+#define MT6389_DCXO_ADLDO_BIAS_ELR_1 (MT6389_PMIC_REG_BASE+0x209c)
+#define MT6389_AUD_TOP_ID (MT6389_PMIC_REG_BASE+0x2480)
+#define MT6389_AUD_TOP_REV0 (MT6389_PMIC_REG_BASE+0x2482)
+#define MT6389_AUD_TOP_DBI (MT6389_PMIC_REG_BASE+0x2484)
+#define MT6389_AUD_TOP_DXI (MT6389_PMIC_REG_BASE+0x2486)
+#define MT6389_AUD_TOP_CKPDN_TPM0 (MT6389_PMIC_REG_BASE+0x2488)
+#define MT6389_AUD_TOP_CKPDN_TPM1 (MT6389_PMIC_REG_BASE+0x248a)
+#define MT6389_AUD_TOP_CKPDN_CON0 (MT6389_PMIC_REG_BASE+0x248c)
+#define MT6389_AUD_TOP_CKPDN_CON0_SET (MT6389_PMIC_REG_BASE+0x248e)
+#define MT6389_AUD_TOP_CKPDN_CON0_CLR (MT6389_PMIC_REG_BASE+0x2490)
+#define MT6389_AUD_TOP_CKSEL_CON0 (MT6389_PMIC_REG_BASE+0x2492)
+#define MT6389_AUD_TOP_CKSEL_CON0_SET (MT6389_PMIC_REG_BASE+0x2494)
+#define MT6389_AUD_TOP_CKSEL_CON0_CLR (MT6389_PMIC_REG_BASE+0x2496)
+#define MT6389_AUD_TOP_CKTST_CON0 (MT6389_PMIC_REG_BASE+0x2498)
+#define MT6389_AUD_TOP_CLK_HWEN_CON0 (MT6389_PMIC_REG_BASE+0x249a)
+#define MT6389_AUD_TOP_CLK_HWEN_CON0_SET (MT6389_PMIC_REG_BASE+0x249c)
+#define MT6389_AUD_TOP_CLK_HWEN_CON0_CLR (MT6389_PMIC_REG_BASE+0x249e)
+#define MT6389_AUD_TOP_RST_CON0 (MT6389_PMIC_REG_BASE+0x24a0)
+#define MT6389_AUD_TOP_RST_CON0_SET (MT6389_PMIC_REG_BASE+0x24a2)
+#define MT6389_AUD_TOP_RST_CON0_CLR (MT6389_PMIC_REG_BASE+0x24a4)
+#define MT6389_AUD_TOP_RST_BANK_CON0 (MT6389_PMIC_REG_BASE+0x24a6)
+#define MT6389_AUD_TOP_INT_CON0 (MT6389_PMIC_REG_BASE+0x24a8)
+#define MT6389_AUD_TOP_INT_CON0_SET (MT6389_PMIC_REG_BASE+0x24aa)
+#define MT6389_AUD_TOP_INT_CON0_CLR (MT6389_PMIC_REG_BASE+0x24ac)
+#define MT6389_AUD_TOP_INT_MASK_CON0 (MT6389_PMIC_REG_BASE+0x24ae)
+#define MT6389_AUD_TOP_INT_MASK_CON0_SET (MT6389_PMIC_REG_BASE+0x24b0)
+#define MT6389_AUD_TOP_INT_MASK_CON0_CLR (MT6389_PMIC_REG_BASE+0x24b2)
+#define MT6389_AUD_TOP_INT_STATUS0 (MT6389_PMIC_REG_BASE+0x24b4)
+#define MT6389_AUD_TOP_INT_RAW_STATUS0 (MT6389_PMIC_REG_BASE+0x24b6)
+#define MT6389_AUD_TOP_INT_MISC_CON0 (MT6389_PMIC_REG_BASE+0x24b8)
+#define MT6389_AUDNCP_CLKDIV_CON0 (MT6389_PMIC_REG_BASE+0x24ba)
+#define MT6389_AUDNCP_CLKDIV_CON1 (MT6389_PMIC_REG_BASE+0x24bc)
+#define MT6389_AUDNCP_CLKDIV_CON2 (MT6389_PMIC_REG_BASE+0x24be)
+#define MT6389_AUDNCP_CLKDIV_CON3 (MT6389_PMIC_REG_BASE+0x24c0)
+#define MT6389_AUDNCP_CLKDIV_CON4 (MT6389_PMIC_REG_BASE+0x24c2)
+#define MT6389_AUD_TOP_MON_CON0 (MT6389_PMIC_REG_BASE+0x24c4)
+#define MT6389_AUDIO_DIG_DSN_ID (MT6389_PMIC_REG_BASE+0x2500)
+#define MT6389_AUDIO_DIG_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2502)
+#define MT6389_AUDIO_DIG_DSN_DBI (MT6389_PMIC_REG_BASE+0x2504)
+#define MT6389_AUDIO_DIG_DSN_DXI (MT6389_PMIC_REG_BASE+0x2506)
+#define MT6389_AFE_UL_DL_CON0 (MT6389_PMIC_REG_BASE+0x2508)
+#define MT6389_AFE_DL_SRC2_CON0_L (MT6389_PMIC_REG_BASE+0x250a)
+#define MT6389_AFE_UL_SRC_CON0_H (MT6389_PMIC_REG_BASE+0x250c)
+#define MT6389_AFE_UL_SRC_CON0_L (MT6389_PMIC_REG_BASE+0x250e)
+#define MT6389_AFE_TOP_CON0 (MT6389_PMIC_REG_BASE+0x2510)
+#define MT6389_AUDIO_TOP_CON0 (MT6389_PMIC_REG_BASE+0x2512)
+#define MT6389_AFE_MON_DEBUG0 (MT6389_PMIC_REG_BASE+0x2514)
+#define MT6389_AFUNC_AUD_CON0 (MT6389_PMIC_REG_BASE+0x2516)
+#define MT6389_AFUNC_AUD_CON1 (MT6389_PMIC_REG_BASE+0x2518)
+#define MT6389_AFUNC_AUD_CON2 (MT6389_PMIC_REG_BASE+0x251a)
+#define MT6389_AFUNC_AUD_CON3 (MT6389_PMIC_REG_BASE+0x251c)
+#define MT6389_AFUNC_AUD_CON4 (MT6389_PMIC_REG_BASE+0x251e)
+#define MT6389_AFUNC_AUD_CON5 (MT6389_PMIC_REG_BASE+0x2520)
+#define MT6389_AFUNC_AUD_CON6 (MT6389_PMIC_REG_BASE+0x2522)
+#define MT6389_AFUNC_AUD_MON0 (MT6389_PMIC_REG_BASE+0x2524)
+#define MT6389_AUDRC_TUNE_MON0 (MT6389_PMIC_REG_BASE+0x2526)
+#define MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0 (MT6389_PMIC_REG_BASE+0x2528)
+#define MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 (MT6389_PMIC_REG_BASE+0x252a)
+#define MT6389_AFE_ADDA_MTKAIF_MON0 (MT6389_PMIC_REG_BASE+0x252c)
+#define MT6389_AFE_ADDA_MTKAIF_MON1 (MT6389_PMIC_REG_BASE+0x252e)
+#define MT6389_AFE_ADDA_MTKAIF_MON2 (MT6389_PMIC_REG_BASE+0x2530)
+#define MT6389_AFE_ADDA_MTKAIF_MON3 (MT6389_PMIC_REG_BASE+0x2532)
+#define MT6389_AFE_ADDA_MTKAIF_CFG0 (MT6389_PMIC_REG_BASE+0x2534)
+#define MT6389_AFE_ADDA_MTKAIF_RX_CFG0 (MT6389_PMIC_REG_BASE+0x2536)
+#define MT6389_AFE_ADDA_MTKAIF_RX_CFG1 (MT6389_PMIC_REG_BASE+0x2538)
+#define MT6389_AFE_ADDA_MTKAIF_RX_CFG2 (MT6389_PMIC_REG_BASE+0x253a)
+#define MT6389_AFE_ADDA_MTKAIF_RX_CFG3 (MT6389_PMIC_REG_BASE+0x253c)
+#define MT6389_AFE_ADDA_MTKAIF_TX_CFG1 (MT6389_PMIC_REG_BASE+0x253e)
+#define MT6389_AFE_SGEN_CFG0 (MT6389_PMIC_REG_BASE+0x2540)
+#define MT6389_AFE_SGEN_CFG1 (MT6389_PMIC_REG_BASE+0x2542)
+#define MT6389_AFE_ADC_ASYNC_FIFO_CFG (MT6389_PMIC_REG_BASE+0x2544)
+#define MT6389_AFE_DCCLK_CFG0 (MT6389_PMIC_REG_BASE+0x2546)
+#define MT6389_AFE_DCCLK_CFG1 (MT6389_PMIC_REG_BASE+0x2548)
+#define MT6389_AUDIO_DIG_CFG (MT6389_PMIC_REG_BASE+0x254a)
+#define MT6389_AFE_AUD_PAD_TOP (MT6389_PMIC_REG_BASE+0x254c)
+#define MT6389_AFE_AUD_PAD_TOP_MON (MT6389_PMIC_REG_BASE+0x254e)
+#define MT6389_AFE_AUD_PAD_TOP_MON1 (MT6389_PMIC_REG_BASE+0x2550)
+#define MT6389_AFE_CG_EN_MON (MT6389_PMIC_REG_BASE+0x2552)
+#define MT6389_AUDENC_DSN_ID (MT6389_PMIC_REG_BASE+0x2580)
+#define MT6389_AUDENC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2582)
+#define MT6389_AUDENC_DSN_DBI (MT6389_PMIC_REG_BASE+0x2584)
+#define MT6389_AUDENC_DSN_FPI (MT6389_PMIC_REG_BASE+0x2586)
+#define MT6389_AUDENC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2588)
+#define MT6389_AUDENC_ANA_CON1 (MT6389_PMIC_REG_BASE+0x258a)
+#define MT6389_AUDENC_ANA_CON2 (MT6389_PMIC_REG_BASE+0x258c)
+#define MT6389_AUDENC_ANA_CON3 (MT6389_PMIC_REG_BASE+0x258e)
+#define MT6389_AUDENC_ANA_CON4 (MT6389_PMIC_REG_BASE+0x2590)
+#define MT6389_AUDENC_ANA_CON5 (MT6389_PMIC_REG_BASE+0x2592)
+#define MT6389_AUDENC_ANA_CON6 (MT6389_PMIC_REG_BASE+0x2594)
+#define MT6389_AUDENC_ANA_CON7 (MT6389_PMIC_REG_BASE+0x2596)
+#define MT6389_AUDENC_ANA_CON8 (MT6389_PMIC_REG_BASE+0x2598)
+#define MT6389_AUDENC_ANA_CON9 (MT6389_PMIC_REG_BASE+0x259a)
+#define MT6389_AUDENC_ANA_CON10 (MT6389_PMIC_REG_BASE+0x259c)
+#define MT6389_AUDENC_ANA_CON11 (MT6389_PMIC_REG_BASE+0x259e)
+#define MT6389_AUDENC_ANA_CON12 (MT6389_PMIC_REG_BASE+0x25a0)
+#define MT6389_AUDDEC_DSN_ID (MT6389_PMIC_REG_BASE+0x2600)
+#define MT6389_AUDDEC_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2602)
+#define MT6389_AUDDEC_DSN_DBI (MT6389_PMIC_REG_BASE+0x2604)
+#define MT6389_AUDDEC_DSN_FPI (MT6389_PMIC_REG_BASE+0x2606)
+#define MT6389_AUDDEC_ANA_CON0 (MT6389_PMIC_REG_BASE+0x2608)
+#define MT6389_AUDDEC_ANA_CON1 (MT6389_PMIC_REG_BASE+0x260a)
+#define MT6389_AUDDEC_ANA_CON2 (MT6389_PMIC_REG_BASE+0x260c)
+#define MT6389_AUDDEC_ANA_CON3 (MT6389_PMIC_REG_BASE+0x260e)
+#define MT6389_AUDDEC_ANA_CON4 (MT6389_PMIC_REG_BASE+0x2610)
+#define MT6389_AUDDEC_ANA_CON5 (MT6389_PMIC_REG_BASE+0x2612)
+#define MT6389_AUDDEC_ANA_CON6 (MT6389_PMIC_REG_BASE+0x2614)
+#define MT6389_AUDDEC_ANA_CON7 (MT6389_PMIC_REG_BASE+0x2616)
+#define MT6389_AUDDEC_ANA_CON8 (MT6389_PMIC_REG_BASE+0x2618)
+#define MT6389_AUDDEC_ANA_CON9 (MT6389_PMIC_REG_BASE+0x261a)
+#define MT6389_AUDDEC_ANA_CON10 (MT6389_PMIC_REG_BASE+0x261c)
+#define MT6389_AUDDEC_ANA_CON11 (MT6389_PMIC_REG_BASE+0x261e)
+#define MT6389_AUDDEC_ANA_CON12 (MT6389_PMIC_REG_BASE+0x2620)
+#define MT6389_AUDDEC_ANA_CON13 (MT6389_PMIC_REG_BASE+0x2622)
+#define MT6389_AUDDEC_ELR_NUM (MT6389_PMIC_REG_BASE+0x2624)
+#define MT6389_AUDDEC_ELR_0 (MT6389_PMIC_REG_BASE+0x2626)
+#define MT6389_AUDZCD_DSN_ID (MT6389_PMIC_REG_BASE+0x2680)
+#define MT6389_AUDZCD_DSN_REV0 (MT6389_PMIC_REG_BASE+0x2682)
+#define MT6389_AUDZCD_DSN_DBI (MT6389_PMIC_REG_BASE+0x2684)
+#define MT6389_AUDZCD_DSN_FPI (MT6389_PMIC_REG_BASE+0x2686)
+#define MT6389_ZCD_CON0 (MT6389_PMIC_REG_BASE+0x2688)
+#define MT6389_ZCD_CON1 (MT6389_PMIC_REG_BASE+0x268a)
+#define MT6389_ZCD_CON2 (MT6389_PMIC_REG_BASE+0x268c)
+#define MT6389_ZCD_CON3 (MT6389_PMIC_REG_BASE+0x268e)
+#define MT6389_ZCD_CON4 (MT6389_PMIC_REG_BASE+0x2690)
+#define MT6389_ZCD_CON5 (MT6389_PMIC_REG_BASE+0x2692)
+//mask is HEX; shift is Integer
+#define PMIC_TOP0_ANA_ID_ADDR \
+ MT6389_TOP0_ID
+#define PMIC_TOP0_ANA_ID_MASK 0xFF
+#define PMIC_TOP0_ANA_ID_SHIFT 0
+#define PMIC_TOP0_DIG_ID_ADDR \
+ MT6389_TOP0_ID
+#define PMIC_TOP0_DIG_ID_MASK 0xFF
+#define PMIC_TOP0_DIG_ID_SHIFT 8
+#define PMIC_TOP0_ANA_MINOR_REV_ADDR \
+ MT6389_TOP0_REV0
+#define PMIC_TOP0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_TOP0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_TOP0_ANA_MAJOR_REV_ADDR \
+ MT6389_TOP0_REV0
+#define PMIC_TOP0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_TOP0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_TOP0_DIG_MINOR_REV_ADDR \
+ MT6389_TOP0_REV0
+#define PMIC_TOP0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_TOP0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_TOP0_DIG_MAJOR_REV_ADDR \
+ MT6389_TOP0_REV0
+#define PMIC_TOP0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_TOP0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_TOP0_DSN_CBS_ADDR \
+ MT6389_TOP0_DSN_DBI
+#define PMIC_TOP0_DSN_CBS_MASK 0x3
+#define PMIC_TOP0_DSN_CBS_SHIFT 0
+#define PMIC_TOP0_DSN_BIX_ADDR \
+ MT6389_TOP0_DSN_DBI
+#define PMIC_TOP0_DSN_BIX_MASK 0x3
+#define PMIC_TOP0_DSN_BIX_SHIFT 2
+#define PMIC_TOP0_DSN_ESP_ADDR \
+ MT6389_TOP0_DSN_DBI
+#define PMIC_TOP0_DSN_ESP_MASK 0xFF
+#define PMIC_TOP0_DSN_ESP_SHIFT 8
+#define PMIC_TOP0_DSN_FPI_ADDR \
+ MT6389_TOP0_DSN_DXI
+#define PMIC_TOP0_DSN_FPI_MASK 0xFF
+#define PMIC_TOP0_DSN_FPI_SHIFT 0
+#define PMIC_HWCID_ADDR \
+ MT6389_HWCID
+#define PMIC_HWCID_MASK 0xFFFF
+#define PMIC_HWCID_SHIFT 0
+#define PMIC_SWCID_ADDR \
+ MT6389_SWCID
+#define PMIC_SWCID_MASK 0xFFFF
+#define PMIC_SWCID_SHIFT 0
+#define PMIC_STS_ENB_ADDR \
+ MT6389_PONSTS
+#define PMIC_STS_ENB_MASK 0x1
+#define PMIC_STS_ENB_SHIFT 0
+#define PMIC_STS_RBOOT_ADDR \
+ MT6389_PONSTS
+#define PMIC_STS_RBOOT_MASK 0x1
+#define PMIC_STS_RBOOT_SHIFT 4
+#define PMIC_STS_UVLO_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_UVLO_MASK 0x1
+#define PMIC_STS_UVLO_SHIFT 0
+#define PMIC_STS_PGFAIL_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_PGFAIL_MASK 0x1
+#define PMIC_STS_PGFAIL_SHIFT 1
+#define PMIC_STS_PSOC_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_PSOC_MASK 0x1
+#define PMIC_STS_PSOC_SHIFT 2
+#define PMIC_STS_THRDN_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_THRDN_MASK 0x1
+#define PMIC_STS_THRDN_SHIFT 3
+#define PMIC_STS_WRST_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_WRST_MASK 0x1
+#define PMIC_STS_WRST_SHIFT 4
+#define PMIC_STS_CRST_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_CRST_MASK 0x1
+#define PMIC_STS_CRST_SHIFT 5
+#define PMIC_STS_RESET_B_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_RESET_B_MASK 0x1
+#define PMIC_STS_RESET_B_SHIFT 6
+#define PMIC_STS_PROTECT_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_PROTECT_MASK 0x1
+#define PMIC_STS_PROTECT_SHIFT 7
+#define PMIC_STS_BWDT_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_BWDT_MASK 0x1
+#define PMIC_STS_BWDT_SHIFT 8
+#define PMIC_STS_DDLO_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_DDLO_MASK 0x1
+#define PMIC_STS_DDLO_SHIFT 9
+#define PMIC_STS_WDT_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_WDT_MASK 0x1
+#define PMIC_STS_WDT_SHIFT 10
+#define PMIC_STS_KEYPWR_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_KEYPWR_MASK 0x1
+#define PMIC_STS_KEYPWR_SHIFT 12
+#define PMIC_STS_OVLO_ADDR \
+ MT6389_POFFSTS
+#define PMIC_STS_OVLO_MASK 0x1
+#define PMIC_STS_OVLO_SHIFT 13
+#define PMIC_RG_POFFSTS_CLR_ADDR \
+ MT6389_PSTSCTL
+#define PMIC_RG_POFFSTS_CLR_MASK 0x1
+#define PMIC_RG_POFFSTS_CLR_SHIFT 0
+#define PMIC_RG_PONSTS_CLR_ADDR \
+ MT6389_PSTSCTL
+#define PMIC_RG_PONSTS_CLR_MASK 0x1
+#define PMIC_RG_PONSTS_CLR_SHIFT 8
+#define PMIC_VEMC_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VEMC_PG_DEB_MASK 0x1
+#define PMIC_VEMC_PG_DEB_SHIFT 0
+#define PMIC_VIO18_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VIO18_PG_DEB_MASK 0x1
+#define PMIC_VIO18_PG_DEB_SHIFT 1
+#define PMIC_VSRAM_PROC_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VSRAM_PROC_PG_DEB_MASK 0x1
+#define PMIC_VSRAM_PROC_PG_DEB_SHIFT 2
+#define PMIC_VPROC_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VPROC_PG_DEB_MASK 0x1
+#define PMIC_VPROC_PG_DEB_SHIFT 3
+#define PMIC_VA12_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VA12_PG_DEB_MASK 0x1
+#define PMIC_VA12_PG_DEB_SHIFT 4
+#define PMIC_VA09_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VA09_PG_DEB_MASK 0x1
+#define PMIC_VA09_PG_DEB_SHIFT 5
+#define PMIC_VSRAM_OTHERS_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VSRAM_OTHERS_PG_DEB_MASK 0x1
+#define PMIC_VSRAM_OTHERS_PG_DEB_SHIFT 6
+#define PMIC_VBBCK_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VBBCK_PG_DEB_MASK 0x1
+#define PMIC_VBBCK_PG_DEB_SHIFT 7
+#define PMIC_VRFCK_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VRFCK_PG_DEB_MASK 0x1
+#define PMIC_VRFCK_PG_DEB_SHIFT 8
+#define PMIC_VS1_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VS1_PG_DEB_MASK 0x1
+#define PMIC_VS1_PG_DEB_SHIFT 9
+#define PMIC_VMODEM_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VMODEM_PG_DEB_MASK 0x1
+#define PMIC_VMODEM_PG_DEB_SHIFT 10
+#define PMIC_VCORE_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VCORE_PG_DEB_MASK 0x1
+#define PMIC_VCORE_PG_DEB_SHIFT 11
+#define PMIC_VS2_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VS2_PG_DEB_MASK 0x1
+#define PMIC_VS2_PG_DEB_SHIFT 12
+#define PMIC_VRTC_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VRTC_PG_DEB_MASK 0x1
+#define PMIC_VRTC_PG_DEB_SHIFT 13
+#define PMIC_VAUX18_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VAUX18_PG_DEB_MASK 0x1
+#define PMIC_VAUX18_PG_DEB_SHIFT 14
+#define PMIC_VXO22_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS0
+#define PMIC_VXO22_PG_DEB_MASK 0x1
+#define PMIC_VXO22_PG_DEB_SHIFT 15
+#define PMIC_VAUD28_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS1
+#define PMIC_VAUD28_PG_DEB_MASK 0x1
+#define PMIC_VAUD28_PG_DEB_SHIFT 11
+#define PMIC_VUSB_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS1
+#define PMIC_VUSB_PG_DEB_MASK 0x1
+#define PMIC_VUSB_PG_DEB_SHIFT 12
+#define PMIC_VDRAM2_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS1
+#define PMIC_VDRAM2_PG_DEB_MASK 0x1
+#define PMIC_VDRAM2_PG_DEB_SHIFT 13
+#define PMIC_VDRAM1_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS1
+#define PMIC_VDRAM1_PG_DEB_MASK 0x1
+#define PMIC_VDRAM1_PG_DEB_SHIFT 14
+#define PMIC_VIO33_PG_DEB_ADDR \
+ MT6389_PG_DEB_STS1
+#define PMIC_VIO33_PG_DEB_MASK 0x1
+#define PMIC_VIO33_PG_DEB_SHIFT 15
+#define PMIC_STRUP_VEMC_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VEMC_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VEMC_PG_STATUS_SHIFT 0
+#define PMIC_STRUP_VIO18_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VIO18_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VIO18_PG_STATUS_SHIFT 1
+#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_SHIFT 2
+#define PMIC_STRUP_VPROC_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VPROC_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VPROC_PG_STATUS_SHIFT 3
+#define PMIC_STRUP_VA12_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VA12_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VA12_PG_STATUS_SHIFT 4
+#define PMIC_STRUP_VA09_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VA09_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VA09_PG_STATUS_SHIFT 5
+#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_SHIFT 6
+#define PMIC_STRUP_VBBCK_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VBBCK_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VBBCK_PG_STATUS_SHIFT 7
+#define PMIC_STRUP_VRFCK_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VRFCK_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VRFCK_PG_STATUS_SHIFT 8
+#define PMIC_STRUP_VS1_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VS1_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VS1_PG_STATUS_SHIFT 9
+#define PMIC_STRUP_VMODEM_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VMODEM_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VMODEM_PG_STATUS_SHIFT 10
+#define PMIC_STRUP_VCORE_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VCORE_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VCORE_PG_STATUS_SHIFT 11
+#define PMIC_STRUP_VS2_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VS2_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VS2_PG_STATUS_SHIFT 12
+#define PMIC_STRUP_VRTC_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VRTC_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VRTC_PG_STATUS_SHIFT 13
+#define PMIC_STRUP_VAUX18_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VAUX18_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VAUX18_PG_STATUS_SHIFT 14
+#define PMIC_STRUP_VXO22_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS0
+#define PMIC_STRUP_VXO22_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VXO22_PG_STATUS_SHIFT 15
+#define PMIC_STRUP_VAUD28_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS1
+#define PMIC_STRUP_VAUD28_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VAUD28_PG_STATUS_SHIFT 11
+#define PMIC_STRUP_VUSB_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS1
+#define PMIC_STRUP_VUSB_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VUSB_PG_STATUS_SHIFT 12
+#define PMIC_STRUP_VDRAM2_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS1
+#define PMIC_STRUP_VDRAM2_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VDRAM2_PG_STATUS_SHIFT 13
+#define PMIC_STRUP_VDRAM1_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS1
+#define PMIC_STRUP_VDRAM1_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VDRAM1_PG_STATUS_SHIFT 14
+#define PMIC_STRUP_VIO33_PG_STATUS_ADDR \
+ MT6389_PG_SDN_STS1
+#define PMIC_STRUP_VIO33_PG_STATUS_MASK 0x1
+#define PMIC_STRUP_VIO33_PG_STATUS_SHIFT 15
+#define PMIC_STRUP_VEMC_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VEMC_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VEMC_OC_STATUS_SHIFT 0
+#define PMIC_STRUP_VIO18_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VIO18_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VIO18_OC_STATUS_SHIFT 1
+#define PMIC_STRUP_VSRAM_PROC_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VSRAM_PROC_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VSRAM_PROC_OC_STATUS_SHIFT 2
+#define PMIC_STRUP_VPROC_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VPROC_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VPROC_OC_STATUS_SHIFT 3
+#define PMIC_STRUP_VA12_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VA12_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VA12_OC_STATUS_SHIFT 4
+#define PMIC_STRUP_VA09_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VA09_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VA09_OC_STATUS_SHIFT 5
+#define PMIC_STRUP_VSRAM_OTHERS_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VSRAM_OTHERS_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VSRAM_OTHERS_OC_STATUS_SHIFT 6
+#define PMIC_STRUP_VBBCK_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VBBCK_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VBBCK_OC_STATUS_SHIFT 7
+#define PMIC_STRUP_VRFCK_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VRFCK_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VRFCK_OC_STATUS_SHIFT 8
+#define PMIC_STRUP_VS1_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VS1_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VS1_OC_STATUS_SHIFT 9
+#define PMIC_STRUP_VMODEM_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VMODEM_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VMODEM_OC_STATUS_SHIFT 10
+#define PMIC_STRUP_VCORE_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VCORE_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VCORE_OC_STATUS_SHIFT 11
+#define PMIC_STRUP_VS2_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VS2_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VS2_OC_STATUS_SHIFT 12
+#define PMIC_STRUP_VRTC_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VRTC_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VRTC_OC_STATUS_SHIFT 13
+#define PMIC_STRUP_VAUX18_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VAUX18_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VAUX18_OC_STATUS_SHIFT 14
+#define PMIC_STRUP_VXO22_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS0
+#define PMIC_STRUP_VXO22_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VXO22_OC_STATUS_SHIFT 15
+#define PMIC_STRUP_VAUD28_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS1
+#define PMIC_STRUP_VAUD28_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VAUD28_OC_STATUS_SHIFT 11
+#define PMIC_STRUP_VUSB_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS1
+#define PMIC_STRUP_VUSB_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VUSB_OC_STATUS_SHIFT 12
+#define PMIC_STRUP_VDRAM2_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS1
+#define PMIC_STRUP_VDRAM2_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VDRAM2_OC_STATUS_SHIFT 13
+#define PMIC_STRUP_VDRAM1_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS1
+#define PMIC_STRUP_VDRAM1_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VDRAM1_OC_STATUS_SHIFT 14
+#define PMIC_STRUP_VIO33_OC_STATUS_ADDR \
+ MT6389_OC_SDN_STS1
+#define PMIC_STRUP_VIO33_OC_STATUS_MASK 0x1
+#define PMIC_STRUP_VIO33_OC_STATUS_SHIFT 15
+#define PMIC_PMU_THERMAL_DEB_ADDR \
+ MT6389_THERMALSTATUS
+#define PMIC_PMU_THERMAL_DEB_MASK 0x1
+#define PMIC_PMU_THERMAL_DEB_SHIFT 14
+#define PMIC_STRUP_THERMAL_STATUS_ADDR \
+ MT6389_THERMALSTATUS
+#define PMIC_STRUP_THERMAL_STATUS_MASK 0x1
+#define PMIC_STRUP_THERMAL_STATUS_SHIFT 15
+#define PMIC_RG_SRCLKEN_IN0_EN_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_SRCLKEN_IN0_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN0_EN_SHIFT 0
+#define PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT 1
+#define PMIC_RG_SRCLKEN_IN1_EN_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_SRCLKEN_IN1_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN1_EN_SHIFT 2
+#define PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT 3
+#define PMIC_RG_SRCLKEN_IN_SYNC_EN_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_SRCLKEN_IN_SYNC_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN_SYNC_EN_SHIFT 8
+#define PMIC_RG_OSC_EN_AUTO_OFF_ADDR \
+ MT6389_TOP_CON
+#define PMIC_RG_OSC_EN_AUTO_OFF_MASK 0x1
+#define PMIC_RG_OSC_EN_AUTO_OFF_SHIFT 9
+#define PMIC_TEST_OUT_ADDR \
+ MT6389_TEST_OUT
+#define PMIC_TEST_OUT_MASK 0x7FF
+#define PMIC_TEST_OUT_SHIFT 0
+#define PMIC_RG_MON_FLAG_SEL_ADDR \
+ MT6389_TEST_CON0
+#define PMIC_RG_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_MON_FLAG_SEL_SHIFT 0
+#define PMIC_RG_MON_GRP_SEL_ADDR \
+ MT6389_TEST_CON0
+#define PMIC_RG_MON_GRP_SEL_MASK 0x1F
+#define PMIC_RG_MON_GRP_SEL_SHIFT 8
+#define PMIC_RG_NANDTREE_MODE_ADDR \
+ MT6389_TEST_CON1
+#define PMIC_RG_NANDTREE_MODE_MASK 0x1
+#define PMIC_RG_NANDTREE_MODE_SHIFT 0
+#define PMIC_RG_TEST_AUXADC_ADDR \
+ MT6389_TEST_CON1
+#define PMIC_RG_TEST_AUXADC_MASK 0x1
+#define PMIC_RG_TEST_AUXADC_SHIFT 1
+#define PMIC_RG_EFUSE_MODE_ADDR \
+ MT6389_TEST_CON1
+#define PMIC_RG_EFUSE_MODE_MASK 0x1
+#define PMIC_RG_EFUSE_MODE_SHIFT 2
+#define PMIC_RG_TEST_STRUP_ADDR \
+ MT6389_TEST_CON1
+#define PMIC_RG_TEST_STRUP_MASK 0x1
+#define PMIC_RG_TEST_STRUP_SHIFT 3
+#define PMIC_TESTMODE_SW_ADDR \
+ MT6389_TESTMODE_SW
+#define PMIC_TESTMODE_SW_MASK 0x1
+#define PMIC_TESTMODE_SW_SHIFT 0
+#define PMIC_PMU_TEST_MODE_SCAN_ADDR \
+ MT6389_TOPSTATUS
+#define PMIC_PMU_TEST_MODE_SCAN_MASK 0x1
+#define PMIC_PMU_TEST_MODE_SCAN_SHIFT 0
+#define PMIC_PWRKEY_DEB_ADDR \
+ MT6389_TOPSTATUS
+#define PMIC_PWRKEY_DEB_MASK 0x1
+#define PMIC_PWRKEY_DEB_SHIFT 1
+#define PMIC_CHRDET_DEB_ADDR \
+ MT6389_TOPSTATUS
+#define PMIC_CHRDET_DEB_MASK 0x1
+#define PMIC_CHRDET_DEB_SHIFT 2
+#define PMIC_HOMEKEY_DEB_ADDR \
+ MT6389_TOPSTATUS
+#define PMIC_HOMEKEY_DEB_MASK 0x1
+#define PMIC_HOMEKEY_DEB_SHIFT 3
+#define PMIC_RG_PMU_TDSEL_ADDR \
+ MT6389_TDSEL_CON
+#define PMIC_RG_PMU_TDSEL_MASK 0x1
+#define PMIC_RG_PMU_TDSEL_SHIFT 0
+#define PMIC_RG_SPI_TDSEL_ADDR \
+ MT6389_TDSEL_CON
+#define PMIC_RG_SPI_TDSEL_MASK 0x1
+#define PMIC_RG_SPI_TDSEL_SHIFT 1
+#define PMIC_RG_AUD_TDSEL_ADDR \
+ MT6389_TDSEL_CON
+#define PMIC_RG_AUD_TDSEL_MASK 0x1
+#define PMIC_RG_AUD_TDSEL_SHIFT 2
+#define PMIC_RG_E32CAL_TDSEL_ADDR \
+ MT6389_TDSEL_CON
+#define PMIC_RG_E32CAL_TDSEL_MASK 0x1
+#define PMIC_RG_E32CAL_TDSEL_SHIFT 3
+#define PMIC_RG_PMU_RDSEL_ADDR \
+ MT6389_RDSEL_CON
+#define PMIC_RG_PMU_RDSEL_MASK 0x1
+#define PMIC_RG_PMU_RDSEL_SHIFT 0
+#define PMIC_RG_SPI_RDSEL_ADDR \
+ MT6389_RDSEL_CON
+#define PMIC_RG_SPI_RDSEL_MASK 0x1
+#define PMIC_RG_SPI_RDSEL_SHIFT 1
+#define PMIC_RG_AUD_RDSEL_ADDR \
+ MT6389_RDSEL_CON
+#define PMIC_RG_AUD_RDSEL_MASK 0x1
+#define PMIC_RG_AUD_RDSEL_SHIFT 2
+#define PMIC_RG_E32CAL_RDSEL_ADDR \
+ MT6389_RDSEL_CON
+#define PMIC_RG_E32CAL_RDSEL_MASK 0x1
+#define PMIC_RG_E32CAL_RDSEL_SHIFT 3
+#define PMIC_RG_SMT_WDTRSTB_IN_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_WDTRSTB_IN_MASK 0x1
+#define PMIC_RG_SMT_WDTRSTB_IN_SHIFT 0
+#define PMIC_RG_SMT_SRCLKEN_IN0_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_SRCLKEN_IN0_MASK 0x1
+#define PMIC_RG_SMT_SRCLKEN_IN0_SHIFT 1
+#define PMIC_RG_SMT_SRCLKEN_IN1_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_SRCLKEN_IN1_MASK 0x1
+#define PMIC_RG_SMT_SRCLKEN_IN1_SHIFT 2
+#define PMIC_RG_SMT_RTC_32K1V8_0_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_RTC_32K1V8_0_MASK 0x1
+#define PMIC_RG_SMT_RTC_32K1V8_0_SHIFT 3
+#define PMIC_RG_SMT_RTC_32K1V8_1_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_RTC_32K1V8_1_MASK 0x1
+#define PMIC_RG_SMT_RTC_32K1V8_1_SHIFT 4
+#define PMIC_RG_SMT_RTC_32K1V8_2_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_RTC_32K1V8_2_MASK 0x1
+#define PMIC_RG_SMT_RTC_32K1V8_2_SHIFT 5
+#define PMIC_RG_SMT_SD_CARD_DET_N_ADDR \
+ MT6389_SMT_CON0
+#define PMIC_RG_SMT_SD_CARD_DET_N_MASK 0x1
+#define PMIC_RG_SMT_SD_CARD_DET_N_SHIFT 6
+#define PMIC_RG_SMT_SPI_CLK_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_SPI_CLK_MASK 0x1
+#define PMIC_RG_SMT_SPI_CLK_SHIFT 0
+#define PMIC_RG_SMT_SPI_CSN_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_SPI_CSN_MASK 0x1
+#define PMIC_RG_SMT_SPI_CSN_SHIFT 1
+#define PMIC_RG_SMT_SPI_MOSI_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_SPI_MOSI_MASK 0x1
+#define PMIC_RG_SMT_SPI_MOSI_SHIFT 2
+#define PMIC_RG_SMT_SPI_MISO_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_SPI_MISO_MASK 0x1
+#define PMIC_RG_SMT_SPI_MISO_SHIFT 3
+#define PMIC_RG_SMT_AUD_CLK_MOSI_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_CLK_MOSI_MASK 0x1
+#define PMIC_RG_SMT_AUD_CLK_MOSI_SHIFT 4
+#define PMIC_RG_SMT_AUD_DAT_MOSI0_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_DAT_MOSI0_MASK 0x1
+#define PMIC_RG_SMT_AUD_DAT_MOSI0_SHIFT 5
+#define PMIC_RG_SMT_AUD_SYNC_MOSI_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_SYNC_MOSI_MASK 0x1
+#define PMIC_RG_SMT_AUD_SYNC_MOSI_SHIFT 6
+#define PMIC_RG_SMT_AUD_CLK_MISO_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_CLK_MISO_MASK 0x1
+#define PMIC_RG_SMT_AUD_CLK_MISO_SHIFT 7
+#define PMIC_RG_SMT_AUD_DAT_MISO0_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_DAT_MISO0_MASK 0x1
+#define PMIC_RG_SMT_AUD_DAT_MISO0_SHIFT 8
+#define PMIC_RG_SMT_AUD_DAT_MISO1_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_DAT_MISO1_MASK 0x1
+#define PMIC_RG_SMT_AUD_DAT_MISO1_SHIFT 9
+#define PMIC_RG_SMT_AUD_SYNC_MISO_ADDR \
+ MT6389_SMT_CON1
+#define PMIC_RG_SMT_AUD_SYNC_MISO_MASK 0x1
+#define PMIC_RG_SMT_AUD_SYNC_MISO_SHIFT 10
+#define PMIC_RG_TOP_RSV0_ADDR \
+ MT6389_TOP_RSV0
+#define PMIC_RG_TOP_RSV0_MASK 0x1
+#define PMIC_RG_TOP_RSV0_SHIFT 0
+#define PMIC_RG_TOP_RSV1_ADDR \
+ MT6389_TOP_RSV1
+#define PMIC_RG_TOP_RSV1_MASK 0x1
+#define PMIC_RG_TOP_RSV1_SHIFT 0
+#define PMIC_RG_OCTL_SRCLKEN_IN0_ADDR \
+ MT6389_DRV_CON0
+#define PMIC_RG_OCTL_SRCLKEN_IN0_MASK 0xF
+#define PMIC_RG_OCTL_SRCLKEN_IN0_SHIFT 0
+#define PMIC_RG_OCTL_SRCLKEN_IN1_ADDR \
+ MT6389_DRV_CON0
+#define PMIC_RG_OCTL_SRCLKEN_IN1_MASK 0xF
+#define PMIC_RG_OCTL_SRCLKEN_IN1_SHIFT 4
+#define PMIC_RG_OCTL_RTC_32K1V8_0_ADDR \
+ MT6389_DRV_CON0
+#define PMIC_RG_OCTL_RTC_32K1V8_0_MASK 0xF
+#define PMIC_RG_OCTL_RTC_32K1V8_0_SHIFT 8
+#define PMIC_RG_OCTL_RTC_32K1V8_1_ADDR \
+ MT6389_DRV_CON0
+#define PMIC_RG_OCTL_RTC_32K1V8_1_MASK 0xF
+#define PMIC_RG_OCTL_RTC_32K1V8_1_SHIFT 12
+#define PMIC_RG_OCTL_SPI_CLK_ADDR \
+ MT6389_DRV_CON1
+#define PMIC_RG_OCTL_SPI_CLK_MASK 0xF
+#define PMIC_RG_OCTL_SPI_CLK_SHIFT 0
+#define PMIC_RG_OCTL_SPI_CSN_ADDR \
+ MT6389_DRV_CON1
+#define PMIC_RG_OCTL_SPI_CSN_MASK 0xF
+#define PMIC_RG_OCTL_SPI_CSN_SHIFT 4
+#define PMIC_RG_OCTL_SPI_MOSI_ADDR \
+ MT6389_DRV_CON1
+#define PMIC_RG_OCTL_SPI_MOSI_MASK 0xF
+#define PMIC_RG_OCTL_SPI_MOSI_SHIFT 8
+#define PMIC_RG_OCTL_SPI_MISO_ADDR \
+ MT6389_DRV_CON1
+#define PMIC_RG_OCTL_SPI_MISO_MASK 0xF
+#define PMIC_RG_OCTL_SPI_MISO_SHIFT 12
+#define PMIC_RG_OCTL_AUD_CLK_MOSI_ADDR \
+ MT6389_DRV_CON2
+#define PMIC_RG_OCTL_AUD_CLK_MOSI_MASK 0xF
+#define PMIC_RG_OCTL_AUD_CLK_MOSI_SHIFT 0
+#define PMIC_RG_OCTL_AUD_DAT_MOSI0_ADDR \
+ MT6389_DRV_CON2
+#define PMIC_RG_OCTL_AUD_DAT_MOSI0_MASK 0xF
+#define PMIC_RG_OCTL_AUD_DAT_MOSI0_SHIFT 4
+#define PMIC_RG_OCTL_AUD_SYNC_MOSI_ADDR \
+ MT6389_DRV_CON2
+#define PMIC_RG_OCTL_AUD_SYNC_MOSI_MASK 0xF
+#define PMIC_RG_OCTL_AUD_SYNC_MOSI_SHIFT 8
+#define PMIC_RG_OCTL_AUD_CLK_MISO_ADDR \
+ MT6389_DRV_CON2
+#define PMIC_RG_OCTL_AUD_CLK_MISO_MASK 0xF
+#define PMIC_RG_OCTL_AUD_CLK_MISO_SHIFT 12
+#define PMIC_RG_OCTL_AUD_DAT_MISO0_ADDR \
+ MT6389_DRV_CON3
+#define PMIC_RG_OCTL_AUD_DAT_MISO0_MASK 0xF
+#define PMIC_RG_OCTL_AUD_DAT_MISO0_SHIFT 0
+#define PMIC_RG_OCTL_AUD_DAT_MISO1_ADDR \
+ MT6389_DRV_CON3
+#define PMIC_RG_OCTL_AUD_DAT_MISO1_MASK 0xF
+#define PMIC_RG_OCTL_AUD_DAT_MISO1_SHIFT 4
+#define PMIC_RG_OCTL_AUD_SYNC_MISO_ADDR \
+ MT6389_DRV_CON3
+#define PMIC_RG_OCTL_AUD_SYNC_MISO_MASK 0xF
+#define PMIC_RG_OCTL_AUD_SYNC_MISO_SHIFT 8
+#define PMIC_RG_OCTL_RTC_32K1V8_2_ADDR \
+ MT6389_DRV_CON4
+#define PMIC_RG_OCTL_RTC_32K1V8_2_MASK 0xF
+#define PMIC_RG_OCTL_RTC_32K1V8_2_SHIFT 0
+#define PMIC_RG_OCTL_SD_CARD_DET_N_ADDR \
+ MT6389_DRV_CON4
+#define PMIC_RG_OCTL_SD_CARD_DET_N_MASK 0xF
+#define PMIC_RG_OCTL_SD_CARD_DET_N_SHIFT 4
+#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_SHIFT 0
+#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_SHIFT 1
+#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_SHIFT 2
+#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_SHIFT 3
+#define PMIC_RG_SPI_CLK_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SPI_CLK_FILTER_EN_MASK 0x1
+#define PMIC_RG_SPI_CLK_FILTER_EN_SHIFT 4
+#define PMIC_RG_SPI_CSN_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SPI_CSN_FILTER_EN_MASK 0x1
+#define PMIC_RG_SPI_CSN_FILTER_EN_SHIFT 5
+#define PMIC_RG_SPI_MOSI_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SPI_MOSI_FILTER_EN_MASK 0x1
+#define PMIC_RG_SPI_MOSI_FILTER_EN_SHIFT 6
+#define PMIC_RG_SPI_MISO_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_SPI_MISO_FILTER_EN_MASK 0x1
+#define PMIC_RG_SPI_MISO_FILTER_EN_SHIFT 7
+#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_SHIFT 8
+#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_SHIFT 9
+#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_SHIFT 10
+#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_SHIFT 11
+#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_SHIFT 12
+#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_SHIFT 13
+#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_MASK 0x1
+#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_SHIFT 14
+#define PMIC_RG_RTC32K_1V8_2_FILTER_EN_ADDR \
+ MT6389_FILTER_CON0
+#define PMIC_RG_RTC32K_1V8_2_FILTER_EN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_2_FILTER_EN_SHIFT 15
+#define PMIC_RG_WDTRSTB_IN_FILTER_EN_ADDR \
+ MT6389_FILTER_CON1
+#define PMIC_RG_WDTRSTB_IN_FILTER_EN_MASK 0x1
+#define PMIC_RG_WDTRSTB_IN_FILTER_EN_SHIFT 0
+#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_ADDR \
+ MT6389_FILTER_CON1
+#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_MASK 0x1
+#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_SHIFT 1
+#define PMIC_RG_SRCLKEN_IN0_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SRCLKEN_IN0_RCSEL_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN0_RCSEL_SHIFT 0
+#define PMIC_RG_SRCLKEN_IN1_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SRCLKEN_IN1_RCSEL_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN1_RCSEL_SHIFT 1
+#define PMIC_RG_RTC32K_1V8_0_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_RTC32K_1V8_0_RCSEL_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_0_RCSEL_SHIFT 2
+#define PMIC_RG_RTC32K_1V8_1_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_RTC32K_1V8_1_RCSEL_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_1_RCSEL_SHIFT 3
+#define PMIC_RG_SPI_CLK_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SPI_CLK_RCSEL_MASK 0x1
+#define PMIC_RG_SPI_CLK_RCSEL_SHIFT 4
+#define PMIC_RG_SPI_CSN_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SPI_CSN_RCSEL_MASK 0x1
+#define PMIC_RG_SPI_CSN_RCSEL_SHIFT 5
+#define PMIC_RG_SPI_MOSI_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SPI_MOSI_RCSEL_MASK 0x1
+#define PMIC_RG_SPI_MOSI_RCSEL_SHIFT 6
+#define PMIC_RG_SPI_MISO_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_SPI_MISO_RCSEL_MASK 0x1
+#define PMIC_RG_SPI_MISO_RCSEL_SHIFT 7
+#define PMIC_RG_AUD_CLK_MOSI_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_CLK_MOSI_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_CLK_MOSI_RCSEL_SHIFT 8
+#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_SHIFT 9
+#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_SHIFT 10
+#define PMIC_RG_AUD_CLK_MISO_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_CLK_MISO_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_CLK_MISO_RCSEL_SHIFT 11
+#define PMIC_RG_AUD_DAT_MISO0_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_DAT_MISO0_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_DAT_MISO0_RCSEL_SHIFT 12
+#define PMIC_RG_AUD_DAT_MISO1_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_DAT_MISO1_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_DAT_MISO1_RCSEL_SHIFT 13
+#define PMIC_RG_AUD_SYNC_MISO_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_AUD_SYNC_MISO_RCSEL_MASK 0x1
+#define PMIC_RG_AUD_SYNC_MISO_RCSEL_SHIFT 14
+#define PMIC_RG_RTC32K_1V8_2_RCSEL_ADDR \
+ MT6389_FILTER_CON2
+#define PMIC_RG_RTC32K_1V8_2_RCSEL_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_2_RCSEL_SHIFT 15
+#define PMIC_RG_WDTRSTB_IN_RCSEL_ADDR \
+ MT6389_FILTER_CON3
+#define PMIC_RG_WDTRSTB_IN_RCSEL_MASK 0x1
+#define PMIC_RG_WDTRSTB_IN_RCSEL_SHIFT 0
+#define PMIC_RG_SD_CARD_DET_N_RCSEL_ADDR \
+ MT6389_FILTER_CON3
+#define PMIC_RG_SD_CARD_DET_N_RCSEL_MASK 0x1
+#define PMIC_RG_SD_CARD_DET_N_RCSEL_SHIFT 1
+#define PMIC_TOP_STATUS_ADDR \
+ MT6389_TOP_STATUS
+#define PMIC_TOP_STATUS_MASK 0xF
+#define PMIC_TOP_STATUS_SHIFT 0
+#define PMIC_TOP_STATUS_SET_ADDR \
+ MT6389_TOP_STATUS_SET
+#define PMIC_TOP_STATUS_SET_MASK 0x3
+#define PMIC_TOP_STATUS_SET_SHIFT 0
+#define PMIC_TOP_STATUS_CLR_ADDR \
+ MT6389_TOP_STATUS_CLR
+#define PMIC_TOP_STATUS_CLR_MASK 0x3
+#define PMIC_TOP_STATUS_CLR_SHIFT 0
+#define PMIC_VM_MODE_ADDR \
+ MT6389_TOP_TRAP
+#define PMIC_VM_MODE_MASK 0x3
+#define PMIC_VM_MODE_SHIFT 0
+#define PMIC_TOP1_ANA_ID_ADDR \
+ MT6389_TOP1_ID
+#define PMIC_TOP1_ANA_ID_MASK 0xFF
+#define PMIC_TOP1_ANA_ID_SHIFT 0
+#define PMIC_TOP1_DIG_ID_ADDR \
+ MT6389_TOP1_ID
+#define PMIC_TOP1_DIG_ID_MASK 0xFF
+#define PMIC_TOP1_DIG_ID_SHIFT 8
+#define PMIC_TOP1_ANA_MINOR_REV_ADDR \
+ MT6389_TOP1_REV0
+#define PMIC_TOP1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_TOP1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_TOP1_ANA_MAJOR_REV_ADDR \
+ MT6389_TOP1_REV0
+#define PMIC_TOP1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_TOP1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_TOP1_DIG_MINOR_REV_ADDR \
+ MT6389_TOP1_REV0
+#define PMIC_TOP1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_TOP1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_TOP1_DIG_MAJOR_REV_ADDR \
+ MT6389_TOP1_REV0
+#define PMIC_TOP1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_TOP1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_TOP1_DSN_CBS_ADDR \
+ MT6389_TOP1_DSN_DBI
+#define PMIC_TOP1_DSN_CBS_MASK 0x3
+#define PMIC_TOP1_DSN_CBS_SHIFT 0
+#define PMIC_TOP1_DSN_BIX_ADDR \
+ MT6389_TOP1_DSN_DBI
+#define PMIC_TOP1_DSN_BIX_MASK 0x3
+#define PMIC_TOP1_DSN_BIX_SHIFT 2
+#define PMIC_TOP1_DSN_ESP_ADDR \
+ MT6389_TOP1_DSN_DBI
+#define PMIC_TOP1_DSN_ESP_MASK 0xFF
+#define PMIC_TOP1_DSN_ESP_SHIFT 8
+#define PMIC_TOP1_DSN_FPI_ADDR \
+ MT6389_TOP1_DSN_DXI
+#define PMIC_TOP1_DSN_FPI_MASK 0xFF
+#define PMIC_TOP1_DSN_FPI_SHIFT 0
+#define PMIC_GPIO_DIR0_ADDR \
+ MT6389_GPIO_DIR0
+#define PMIC_GPIO_DIR0_MASK 0xFFFF
+#define PMIC_GPIO_DIR0_SHIFT 0
+#define PMIC_GPIO_DIR0_SET_ADDR \
+ MT6389_GPIO_DIR0_SET
+#define PMIC_GPIO_DIR0_SET_MASK 0xFFFF
+#define PMIC_GPIO_DIR0_SET_SHIFT 0
+#define PMIC_GPIO_DIR0_CLR_ADDR \
+ MT6389_GPIO_DIR0_CLR
+#define PMIC_GPIO_DIR0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DIR0_CLR_SHIFT 0
+#define PMIC_GPIO_DIR1_ADDR \
+ MT6389_GPIO_DIR1
+#define PMIC_GPIO_DIR1_MASK 0x1
+#define PMIC_GPIO_DIR1_SHIFT 0
+#define PMIC_GPIO_DIR1_SET_ADDR \
+ MT6389_GPIO_DIR1_SET
+#define PMIC_GPIO_DIR1_SET_MASK 0xFFFF
+#define PMIC_GPIO_DIR1_SET_SHIFT 0
+#define PMIC_GPIO_DIR1_CLR_ADDR \
+ MT6389_GPIO_DIR1_CLR
+#define PMIC_GPIO_DIR1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DIR1_CLR_SHIFT 0
+#define PMIC_GPIO_PULLEN0_ADDR \
+ MT6389_GPIO_PULLEN0
+#define PMIC_GPIO_PULLEN0_MASK 0xFFFF
+#define PMIC_GPIO_PULLEN0_SHIFT 0
+#define PMIC_GPIO_PULLEN0_SET_ADDR \
+ MT6389_GPIO_PULLEN0_SET
+#define PMIC_GPIO_PULLEN0_SET_MASK 0xFFFF
+#define PMIC_GPIO_PULLEN0_SET_SHIFT 0
+#define PMIC_GPIO_PULLEN0_CLR_ADDR \
+ MT6389_GPIO_PULLEN0_CLR
+#define PMIC_GPIO_PULLEN0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_PULLEN0_CLR_SHIFT 0
+#define PMIC_GPIO_PULLEN1_ADDR \
+ MT6389_GPIO_PULLEN1
+#define PMIC_GPIO_PULLEN1_MASK 0x1
+#define PMIC_GPIO_PULLEN1_SHIFT 0
+#define PMIC_GPIO_PULLEN1_SET_ADDR \
+ MT6389_GPIO_PULLEN1_SET
+#define PMIC_GPIO_PULLEN1_SET_MASK 0xFFFF
+#define PMIC_GPIO_PULLEN1_SET_SHIFT 0
+#define PMIC_GPIO_PULLEN1_CLR_ADDR \
+ MT6389_GPIO_PULLEN1_CLR
+#define PMIC_GPIO_PULLEN1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_PULLEN1_CLR_SHIFT 0
+#define PMIC_GPIO_PULLSEL0_ADDR \
+ MT6389_GPIO_PULLSEL0
+#define PMIC_GPIO_PULLSEL0_MASK 0xFFFF
+#define PMIC_GPIO_PULLSEL0_SHIFT 0
+#define PMIC_GPIO_PULLSEL0_SET_ADDR \
+ MT6389_GPIO_PULLSEL0_SET
+#define PMIC_GPIO_PULLSEL0_SET_MASK 0xFFFF
+#define PMIC_GPIO_PULLSEL0_SET_SHIFT 0
+#define PMIC_GPIO_PULLSEL0_CLR_ADDR \
+ MT6389_GPIO_PULLSEL0_CLR
+#define PMIC_GPIO_PULLSEL0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_PULLSEL0_CLR_SHIFT 0
+#define PMIC_GPIO_PULLSEL1_ADDR \
+ MT6389_GPIO_PULLSEL1
+#define PMIC_GPIO_PULLSEL1_MASK 0x1
+#define PMIC_GPIO_PULLSEL1_SHIFT 0
+#define PMIC_GPIO_PULLSEL1_SET_ADDR \
+ MT6389_GPIO_PULLSEL1_SET
+#define PMIC_GPIO_PULLSEL1_SET_MASK 0xFFFF
+#define PMIC_GPIO_PULLSEL1_SET_SHIFT 0
+#define PMIC_GPIO_PULLSEL1_CLR_ADDR \
+ MT6389_GPIO_PULLSEL1_CLR
+#define PMIC_GPIO_PULLSEL1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_PULLSEL1_CLR_SHIFT 0
+#define PMIC_GPIO_DINV0_ADDR \
+ MT6389_GPIO_DINV0
+#define PMIC_GPIO_DINV0_MASK 0xFFFF
+#define PMIC_GPIO_DINV0_SHIFT 0
+#define PMIC_GPIO_DINV0_SET_ADDR \
+ MT6389_GPIO_DINV0_SET
+#define PMIC_GPIO_DINV0_SET_MASK 0xFFFF
+#define PMIC_GPIO_DINV0_SET_SHIFT 0
+#define PMIC_GPIO_DINV0_CLR_ADDR \
+ MT6389_GPIO_DINV0_CLR
+#define PMIC_GPIO_DINV0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DINV0_CLR_SHIFT 0
+#define PMIC_GPIO_DINV1_ADDR \
+ MT6389_GPIO_DINV1
+#define PMIC_GPIO_DINV1_MASK 0x1
+#define PMIC_GPIO_DINV1_SHIFT 0
+#define PMIC_GPIO_DINV1_SET_ADDR \
+ MT6389_GPIO_DINV1_SET
+#define PMIC_GPIO_DINV1_SET_MASK 0xFFFF
+#define PMIC_GPIO_DINV1_SET_SHIFT 0
+#define PMIC_GPIO_DINV1_CLR_ADDR \
+ MT6389_GPIO_DINV1_CLR
+#define PMIC_GPIO_DINV1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DINV1_CLR_SHIFT 0
+#define PMIC_GPIO_DOUT0_ADDR \
+ MT6389_GPIO_DOUT0
+#define PMIC_GPIO_DOUT0_MASK 0xFFFF
+#define PMIC_GPIO_DOUT0_SHIFT 0
+#define PMIC_GPIO_DOUT0_SET_ADDR \
+ MT6389_GPIO_DOUT0_SET
+#define PMIC_GPIO_DOUT0_SET_MASK 0xFFFF
+#define PMIC_GPIO_DOUT0_SET_SHIFT 0
+#define PMIC_GPIO_DOUT0_CLR_ADDR \
+ MT6389_GPIO_DOUT0_CLR
+#define PMIC_GPIO_DOUT0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DOUT0_CLR_SHIFT 0
+#define PMIC_GPIO_DOUT1_ADDR \
+ MT6389_GPIO_DOUT1
+#define PMIC_GPIO_DOUT1_MASK 0x1
+#define PMIC_GPIO_DOUT1_SHIFT 0
+#define PMIC_GPIO_DOUT1_SET_ADDR \
+ MT6389_GPIO_DOUT1_SET
+#define PMIC_GPIO_DOUT1_SET_MASK 0xFFFF
+#define PMIC_GPIO_DOUT1_SET_SHIFT 0
+#define PMIC_GPIO_DOUT1_CLR_ADDR \
+ MT6389_GPIO_DOUT1_CLR
+#define PMIC_GPIO_DOUT1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_DOUT1_CLR_SHIFT 0
+#define PMIC_GPIO_PI0_ADDR \
+ MT6389_GPIO_PI0
+#define PMIC_GPIO_PI0_MASK 0xFFFF
+#define PMIC_GPIO_PI0_SHIFT 0
+#define PMIC_GPIO_PI1_ADDR \
+ MT6389_GPIO_PI1
+#define PMIC_GPIO_PI1_MASK 0x1
+#define PMIC_GPIO_PI1_SHIFT 0
+#define PMIC_GPIO_POE0_ADDR \
+ MT6389_GPIO_POE0
+#define PMIC_GPIO_POE0_MASK 0xFFFF
+#define PMIC_GPIO_POE0_SHIFT 0
+#define PMIC_GPIO_POE1_ADDR \
+ MT6389_GPIO_POE1
+#define PMIC_GPIO_POE1_MASK 0x1
+#define PMIC_GPIO_POE1_SHIFT 0
+#define PMIC_GPIO0_MODE_ADDR \
+ MT6389_GPIO_MODE0
+#define PMIC_GPIO0_MODE_MASK 0x7
+#define PMIC_GPIO0_MODE_SHIFT 0
+#define PMIC_GPIO1_MODE_ADDR \
+ MT6389_GPIO_MODE0
+#define PMIC_GPIO1_MODE_MASK 0x7
+#define PMIC_GPIO1_MODE_SHIFT 3
+#define PMIC_GPIO2_MODE_ADDR \
+ MT6389_GPIO_MODE0
+#define PMIC_GPIO2_MODE_MASK 0x7
+#define PMIC_GPIO2_MODE_SHIFT 6
+#define PMIC_GPIO3_MODE_ADDR \
+ MT6389_GPIO_MODE0
+#define PMIC_GPIO3_MODE_MASK 0x7
+#define PMIC_GPIO3_MODE_SHIFT 9
+#define PMIC_GPIO_MODE0_SET_ADDR \
+ MT6389_GPIO_MODE0_SET
+#define PMIC_GPIO_MODE0_SET_MASK 0xFFFF
+#define PMIC_GPIO_MODE0_SET_SHIFT 0
+#define PMIC_GPIO_MODE0_CLR_ADDR \
+ MT6389_GPIO_MODE0_CLR
+#define PMIC_GPIO_MODE0_CLR_MASK 0xFFFF
+#define PMIC_GPIO_MODE0_CLR_SHIFT 0
+#define PMIC_GPIO4_MODE_ADDR \
+ MT6389_GPIO_MODE1
+#define PMIC_GPIO4_MODE_MASK 0x7
+#define PMIC_GPIO4_MODE_SHIFT 0
+#define PMIC_GPIO5_MODE_ADDR \
+ MT6389_GPIO_MODE1
+#define PMIC_GPIO5_MODE_MASK 0x7
+#define PMIC_GPIO5_MODE_SHIFT 3
+#define PMIC_GPIO6_MODE_ADDR \
+ MT6389_GPIO_MODE1
+#define PMIC_GPIO6_MODE_MASK 0x7
+#define PMIC_GPIO6_MODE_SHIFT 6
+#define PMIC_GPIO7_MODE_ADDR \
+ MT6389_GPIO_MODE1
+#define PMIC_GPIO7_MODE_MASK 0x7
+#define PMIC_GPIO7_MODE_SHIFT 9
+#define PMIC_GPIO_MODE1_SET_ADDR \
+ MT6389_GPIO_MODE1_SET
+#define PMIC_GPIO_MODE1_SET_MASK 0xFFFF
+#define PMIC_GPIO_MODE1_SET_SHIFT 0
+#define PMIC_GPIO_MODE1_CLR_ADDR \
+ MT6389_GPIO_MODE1_CLR
+#define PMIC_GPIO_MODE1_CLR_MASK 0xFFFF
+#define PMIC_GPIO_MODE1_CLR_SHIFT 0
+#define PMIC_GPIO8_MODE_ADDR \
+ MT6389_GPIO_MODE2
+#define PMIC_GPIO8_MODE_MASK 0x7
+#define PMIC_GPIO8_MODE_SHIFT 0
+#define PMIC_GPIO9_MODE_ADDR \
+ MT6389_GPIO_MODE2
+#define PMIC_GPIO9_MODE_MASK 0x7
+#define PMIC_GPIO9_MODE_SHIFT 3
+#define PMIC_GPIO10_MODE_ADDR \
+ MT6389_GPIO_MODE2
+#define PMIC_GPIO10_MODE_MASK 0x7
+#define PMIC_GPIO10_MODE_SHIFT 6
+#define PMIC_GPIO11_MODE_ADDR \
+ MT6389_GPIO_MODE2
+#define PMIC_GPIO11_MODE_MASK 0x7
+#define PMIC_GPIO11_MODE_SHIFT 9
+#define PMIC_GPIO_MODE2_SET_ADDR \
+ MT6389_GPIO_MODE2_SET
+#define PMIC_GPIO_MODE2_SET_MASK 0xFFFF
+#define PMIC_GPIO_MODE2_SET_SHIFT 0
+#define PMIC_GPIO_MODE2_CLR_ADDR \
+ MT6389_GPIO_MODE2_CLR
+#define PMIC_GPIO_MODE2_CLR_MASK 0xFFFF
+#define PMIC_GPIO_MODE2_CLR_SHIFT 0
+#define PMIC_GPIO12_MODE_ADDR \
+ MT6389_GPIO_MODE3
+#define PMIC_GPIO12_MODE_MASK 0x7
+#define PMIC_GPIO12_MODE_SHIFT 0
+#define PMIC_GPIO13_MODE_ADDR \
+ MT6389_GPIO_MODE3
+#define PMIC_GPIO13_MODE_MASK 0x7
+#define PMIC_GPIO13_MODE_SHIFT 3
+#define PMIC_GPIO14_MODE_ADDR \
+ MT6389_GPIO_MODE3
+#define PMIC_GPIO14_MODE_MASK 0x7
+#define PMIC_GPIO14_MODE_SHIFT 6
+#define PMIC_GPIO15_MODE_ADDR \
+ MT6389_GPIO_MODE3
+#define PMIC_GPIO15_MODE_MASK 0x7
+#define PMIC_GPIO15_MODE_SHIFT 9
+#define PMIC_GPIO_MODE3_SET_ADDR \
+ MT6389_GPIO_MODE3_SET
+#define PMIC_GPIO_MODE3_SET_MASK 0xFFFF
+#define PMIC_GPIO_MODE3_SET_SHIFT 0
+#define PMIC_GPIO_MODE3_CLR_ADDR \
+ MT6389_GPIO_MODE3_CLR
+#define PMIC_GPIO_MODE3_CLR_MASK 0xFFFF
+#define PMIC_GPIO_MODE3_CLR_SHIFT 0
+#define PMIC_GPIO16_MODE_ADDR \
+ MT6389_GPIO_MODE4
+#define PMIC_GPIO16_MODE_MASK 0x7
+#define PMIC_GPIO16_MODE_SHIFT 0
+#define PMIC_GPIO_MODE4_SET_ADDR \
+ MT6389_GPIO_MODE4_SET
+#define PMIC_GPIO_MODE4_SET_MASK 0xFFFF
+#define PMIC_GPIO_MODE4_SET_SHIFT 0
+#define PMIC_GPIO_MODE4_CLR_ADDR \
+ MT6389_GPIO_MODE4_CLR
+#define PMIC_GPIO_MODE4_CLR_MASK 0xFFFF
+#define PMIC_GPIO_MODE4_CLR_SHIFT 0
+#define PMIC_GPIO_RSV_ADDR \
+ MT6389_GPIO_RSV
+#define PMIC_GPIO_RSV_MASK 0x1
+#define PMIC_GPIO_RSV_SHIFT 0
+#define PMIC_TOP2_ANA_ID_ADDR \
+ MT6389_TOP2_ID
+#define PMIC_TOP2_ANA_ID_MASK 0xFF
+#define PMIC_TOP2_ANA_ID_SHIFT 0
+#define PMIC_TOP2_DIG_ID_ADDR \
+ MT6389_TOP2_ID
+#define PMIC_TOP2_DIG_ID_MASK 0xFF
+#define PMIC_TOP2_DIG_ID_SHIFT 8
+#define PMIC_TOP2_ANA_MINOR_REV_ADDR \
+ MT6389_TOP2_REV0
+#define PMIC_TOP2_ANA_MINOR_REV_MASK 0xF
+#define PMIC_TOP2_ANA_MINOR_REV_SHIFT 0
+#define PMIC_TOP2_ANA_MAJOR_REV_ADDR \
+ MT6389_TOP2_REV0
+#define PMIC_TOP2_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_TOP2_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_TOP2_DIG_MINOR_REV_ADDR \
+ MT6389_TOP2_REV0
+#define PMIC_TOP2_DIG_MINOR_REV_MASK 0xF
+#define PMIC_TOP2_DIG_MINOR_REV_SHIFT 8
+#define PMIC_TOP2_DIG_MAJOR_REV_ADDR \
+ MT6389_TOP2_REV0
+#define PMIC_TOP2_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_TOP2_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_TOP2_DSN_CBS_ADDR \
+ MT6389_TOP2_DSN_DBI
+#define PMIC_TOP2_DSN_CBS_MASK 0x3
+#define PMIC_TOP2_DSN_CBS_SHIFT 0
+#define PMIC_TOP2_DSN_BIX_ADDR \
+ MT6389_TOP2_DSN_DBI
+#define PMIC_TOP2_DSN_BIX_MASK 0x3
+#define PMIC_TOP2_DSN_BIX_SHIFT 2
+#define PMIC_TOP2_DSN_ESP_ADDR \
+ MT6389_TOP2_DSN_DBI
+#define PMIC_TOP2_DSN_ESP_MASK 0xFF
+#define PMIC_TOP2_DSN_ESP_SHIFT 8
+#define PMIC_TOP2_DSN_FPI_ADDR \
+ MT6389_TOP2_DSN_DXI
+#define PMIC_TOP2_DSN_FPI_MASK 0xFF
+#define PMIC_TOP2_DSN_FPI_SHIFT 0
+#define PMIC_TOP_CLK_OFFSET_ADDR \
+ MT6389_TOP_PAM0
+#define PMIC_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_TOP_RST_OFFSET_ADDR \
+ MT6389_TOP_PAM0
+#define PMIC_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_TOP_INT_OFFSET_ADDR \
+ MT6389_TOP_PAM1
+#define PMIC_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_TOP_INT_LEN_ADDR \
+ MT6389_TOP_PAM1
+#define PMIC_TOP_INT_LEN_MASK 0xFF
+#define PMIC_TOP_INT_LEN_SHIFT 8
+#define PMIC_RG_SCK32K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_SCK32K_CK_PDN_MASK 0x1
+#define PMIC_RG_SCK32K_CK_PDN_SHIFT 0
+#define PMIC_RG_INTRP_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_INTRP_CK_PDN_MASK 0x1
+#define PMIC_RG_INTRP_CK_PDN_SHIFT 2
+#define PMIC_RG_EFUSE_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_EFUSE_CK_PDN_MASK 0x1
+#define PMIC_RG_EFUSE_CK_PDN_SHIFT 4
+#define PMIC_RG_CK_PDN_RSV0_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_CK_PDN_RSV0_MASK 0x1
+#define PMIC_RG_CK_PDN_RSV0_SHIFT 5
+#define PMIC_RG_CK_PDN_RSV1_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_CK_PDN_RSV1_MASK 0x1
+#define PMIC_RG_CK_PDN_RSV1_SHIFT 6
+#define PMIC_RG_SPI_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_SPI_CK_PDN_MASK 0x1
+#define PMIC_RG_SPI_CK_PDN_SHIFT 7
+#define PMIC_RG_CK_PDN_RSV2_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_CK_PDN_RSV2_MASK 0x1
+#define PMIC_RG_CK_PDN_RSV2_SHIFT 8
+#define PMIC_RG_PMU32K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_PMU32K_CK_PDN_MASK 0x1
+#define PMIC_RG_PMU32K_CK_PDN_SHIFT 9
+#define PMIC_RG_FQMTR_32K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_FQMTR_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_FQMTR_32K_CK_PDN_SHIFT 10
+#define PMIC_RG_FQMTR_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_FQMTR_CK_PDN_MASK 0x1
+#define PMIC_RG_FQMTR_CK_PDN_SHIFT 11
+#define PMIC_RG_PMU128K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_PMU128K_CK_PDN_MASK 0x1
+#define PMIC_RG_PMU128K_CK_PDN_SHIFT 13
+#define PMIC_RG_RTC26M_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_RTC26M_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC26M_CK_PDN_SHIFT 14
+#define PMIC_RG_RTC32K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON0
+#define PMIC_RG_RTC32K_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC32K_CK_PDN_SHIFT 15
+#define PMIC_TOP_CKPDN_CON0_SET_ADDR \
+ MT6389_TOP_CKPDN_CON0_SET
+#define PMIC_TOP_CKPDN_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_CKPDN_CON0_SET_SHIFT 0
+#define PMIC_TOP_CKPDN_CON0_CLR_ADDR \
+ MT6389_TOP_CKPDN_CON0_CLR
+#define PMIC_TOP_CKPDN_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKPDN_CON0_CLR_SHIFT 0
+#define PMIC_RG_RTC32K_1V8_0_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_RTC32K_1V8_0_PDN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_0_PDN_SHIFT 0
+#define PMIC_RG_RTC32K_1V8_1_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_RTC32K_1V8_1_PDN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_1_PDN_SHIFT 1
+#define PMIC_RG_TRIM_128K_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_TRIM_128K_CK_PDN_MASK 0x1
+#define PMIC_RG_TRIM_128K_CK_PDN_SHIFT 2
+#define PMIC_RG_BGR_TEST_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_BGR_TEST_CK_PDN_MASK 0x1
+#define PMIC_RG_BGR_TEST_CK_PDN_SHIFT 3
+#define PMIC_RG_PCHR_TEST_CK_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_PCHR_TEST_CK_PDN_MASK 0x1
+#define PMIC_RG_PCHR_TEST_CK_PDN_SHIFT 4
+#define PMIC_RG_RTC32K_1V8_2_PDN_ADDR \
+ MT6389_TOP_CKPDN_CON1
+#define PMIC_RG_RTC32K_1V8_2_PDN_MASK 0x1
+#define PMIC_RG_RTC32K_1V8_2_PDN_SHIFT 5
+#define PMIC_TOP_CKPDN_CON1_SET_ADDR \
+ MT6389_TOP_CKPDN_CON1_SET
+#define PMIC_TOP_CKPDN_CON1_SET_MASK 0xFFFF
+#define PMIC_TOP_CKPDN_CON1_SET_SHIFT 0
+#define PMIC_TOP_CKPDN_CON1_CLR_ADDR \
+ MT6389_TOP_CKPDN_CON1_CLR
+#define PMIC_TOP_CKPDN_CON1_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKPDN_CON1_CLR_SHIFT 0
+#define PMIC_RG_FQMTR_CK_CKSEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_FQMTR_CK_CKSEL_MASK 0x7
+#define PMIC_RG_FQMTR_CK_CKSEL_SHIFT 0
+#define PMIC_RG_RTC_32K1V8_SEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_RTC_32K1V8_SEL_MASK 0x1
+#define PMIC_RG_RTC_32K1V8_SEL_SHIFT 3
+#define PMIC_RG_BGR_TEST_CK_SEL_CKSEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_BGR_TEST_CK_SEL_CKSEL_MASK 0x1
+#define PMIC_RG_BGR_TEST_CK_SEL_CKSEL_SHIFT 4
+#define PMIC_RG_PCHR_TEST_CK_CKSEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PCHR_TEST_CK_CKSEL_MASK 0x1
+#define PMIC_RG_PCHR_TEST_CK_CKSEL_SHIFT 5
+#define PMIC_RG_PMU_26M_CK_SEL_HWEN_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PMU_26M_CK_SEL_HWEN_MASK 0x1
+#define PMIC_RG_PMU_26M_CK_SEL_HWEN_SHIFT 6
+#define PMIC_RG_PMU_26M_CK_SEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PMU_26M_CK_SEL_MASK 0x1
+#define PMIC_RG_PMU_26M_CK_SEL_SHIFT 7
+#define PMIC_RG_PMU_1M_CK_SEL_HWEN_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PMU_1M_CK_SEL_HWEN_MASK 0x1
+#define PMIC_RG_PMU_1M_CK_SEL_HWEN_SHIFT 8
+#define PMIC_RG_PMU_1M_CK_SEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PMU_1M_CK_SEL_MASK 0x1
+#define PMIC_RG_PMU_1M_CK_SEL_SHIFT 9
+#define PMIC_RG_PMU32K_CK_CKSEL_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_PMU32K_CK_CKSEL_MASK 0x1
+#define PMIC_RG_PMU32K_CK_CKSEL_SHIFT 10
+#define PMIC_RG_TOP_CKSEL_CON0_RSV_ADDR \
+ MT6389_TOP_CKSEL_CON0
+#define PMIC_RG_TOP_CKSEL_CON0_RSV_MASK 0x1F
+#define PMIC_RG_TOP_CKSEL_CON0_RSV_SHIFT 11
+#define PMIC_TOP_CKSEL_CON0_SET_ADDR \
+ MT6389_TOP_CKSEL_CON0_SET
+#define PMIC_TOP_CKSEL_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_CKSEL_CON0_SET_SHIFT 0
+#define PMIC_TOP_CKSEL_CON0_CLR_ADDR \
+ MT6389_TOP_CKSEL_CON0_CLR
+#define PMIC_TOP_CKSEL_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKSEL_CON0_CLR_SHIFT 0
+#define PMIC_RG_SRCVOLTEN_SW_ADDR \
+ MT6389_TOP_CKSEL_CON1
+#define PMIC_RG_SRCVOLTEN_SW_MASK 0x1
+#define PMIC_RG_SRCVOLTEN_SW_SHIFT 0
+#define PMIC_RG_VOWEN_SW_ADDR \
+ MT6389_TOP_CKSEL_CON1
+#define PMIC_RG_VOWEN_SW_MASK 0x1
+#define PMIC_RG_VOWEN_SW_SHIFT 1
+#define PMIC_RG_SRCVOLTEN_MODE_ADDR \
+ MT6389_TOP_CKSEL_CON1
+#define PMIC_RG_SRCVOLTEN_MODE_MASK 0x1
+#define PMIC_RG_SRCVOLTEN_MODE_SHIFT 8
+#define PMIC_RG_VOWEN_MODE_ADDR \
+ MT6389_TOP_CKSEL_CON1
+#define PMIC_RG_VOWEN_MODE_MASK 0x1
+#define PMIC_RG_VOWEN_MODE_SHIFT 9
+#define PMIC_RG_TOP_CKSEL_CON2_RSV_ADDR \
+ MT6389_TOP_CKSEL_CON1
+#define PMIC_RG_TOP_CKSEL_CON2_RSV_MASK 0xF
+#define PMIC_RG_TOP_CKSEL_CON2_RSV_SHIFT 12
+#define PMIC_TOP_CKSEL_CON1_SET_ADDR \
+ MT6389_TOP_CKSEL_CON1_SET
+#define PMIC_TOP_CKSEL_CON1_SET_MASK 0xFFFF
+#define PMIC_TOP_CKSEL_CON1_SET_SHIFT 0
+#define PMIC_TOP_CKSEL_CON1_CLR_ADDR \
+ MT6389_TOP_CKSEL_CON1_CLR
+#define PMIC_TOP_CKSEL_CON1_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKSEL_CON1_CLR_SHIFT 0
+#define PMIC_RG_REG_CK_DIVSEL_ADDR \
+ MT6389_TOP_CKDIVSEL_CON0
+#define PMIC_RG_REG_CK_DIVSEL_MASK 0x3
+#define PMIC_RG_REG_CK_DIVSEL_SHIFT 0
+#define PMIC_TOP_CKDIVSEL_CON0_RSV_ADDR \
+ MT6389_TOP_CKDIVSEL_CON0
+#define PMIC_TOP_CKDIVSEL_CON0_RSV_MASK 0x3F
+#define PMIC_TOP_CKDIVSEL_CON0_RSV_SHIFT 10
+#define PMIC_TOP_CKDIVSEL_CON0_SET_ADDR \
+ MT6389_TOP_CKDIVSEL_CON0_SET
+#define PMIC_TOP_CKDIVSEL_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_CKDIVSEL_CON0_SET_SHIFT 0
+#define PMIC_TOP_CKDIVSEL_CON0_CLR_ADDR \
+ MT6389_TOP_CKDIVSEL_CON0_CLR
+#define PMIC_TOP_CKDIVSEL_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKDIVSEL_CON0_CLR_SHIFT 0
+#define PMIC_RG_EFUSE_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_CKHWEN_CON0
+#define PMIC_RG_EFUSE_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT 2
+#define PMIC_RG_EINT_32K_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_CKHWEN_CON0
+#define PMIC_RG_EINT_32K_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_EINT_32K_CK_PDN_HWEN_SHIFT 3
+#define PMIC_RG_RTC26M_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC26M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC26M_CK_PDN_HWEN_SHIFT 5
+#define PMIC_TOP_CKHWEN_CON0_RSV_ADDR \
+ MT6389_TOP_CKHWEN_CON0
+#define PMIC_TOP_CKHWEN_CON0_RSV_MASK 0x3
+#define PMIC_TOP_CKHWEN_CON0_RSV_SHIFT 14
+#define PMIC_TOP_CKHWEN_CON0_SET_ADDR \
+ MT6389_TOP_CKHWEN_CON0_SET
+#define PMIC_TOP_CKHWEN_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_CKHWEN_CON0_SET_SHIFT 0
+#define PMIC_TOP_CKHWEN_CON0_CLR_ADDR \
+ MT6389_TOP_CKHWEN_CON0_CLR
+#define PMIC_TOP_CKHWEN_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_CKHWEN_CON0_CLR_SHIFT 0
+#define PMIC_RG_PMU128K_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_PMU128K_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_PMU128K_CK_TST_DIS_SHIFT 0
+#define PMIC_RG_DCXO_1M_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_DCXO_1M_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_DCXO_1M_CK_TST_DIS_SHIFT 1
+#define PMIC_RG_DCXO_26M_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_DCXO_26M_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_DCXO_26M_CK_TST_DIS_SHIFT 2
+#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_MASK 0x1
+#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_SHIFT 3
+#define PMIC_RG_RTC_26M_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_RTC_26M_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_RTC_26M_CK_TST_DIS_SHIFT 4
+#define PMIC_RG_RTC_32K_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_RTC_32K_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_RTC_32K_CK_TST_DIS_SHIFT 5
+#define PMIC_RG_SCK_32K_CK_TST_DIS_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_RG_SCK_32K_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_SCK_32K_CK_TST_DIS_SHIFT 6
+#define PMIC_TOP_CKTST_CON0_RSV_ADDR \
+ MT6389_TOP_CKTST_CON0
+#define PMIC_TOP_CKTST_CON0_RSV_MASK 0xFF
+#define PMIC_TOP_CKTST_CON0_RSV_SHIFT 8
+#define PMIC_RG_PMU128K_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_PMU128K_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_PMU128K_CK_TSTSEL_SHIFT 0
+#define PMIC_RG_DCXO_1M_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_DCXO_1M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_DCXO_1M_CK_TSTSEL_SHIFT 1
+#define PMIC_RG_DCXO_26M_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_DCXO_26M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_DCXO_26M_CK_TSTSEL_SHIFT 2
+#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_MASK 0x1
+#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_SHIFT 3
+#define PMIC_RG_RTC_26M_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_RTC_26M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_RTC_26M_CK_TSTSEL_SHIFT 4
+#define PMIC_RG_RTC_32K_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_RTC_32K_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_RTC_32K_CK_TSTSEL_SHIFT 5
+#define PMIC_RG_SCK_32K_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_SCK_32K_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_SCK_32K_CK_TSTSEL_SHIFT 6
+#define PMIC_RG_EFUSE_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_EFUSE_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_EFUSE_CK_TSTSEL_SHIFT 7
+#define PMIC_RG_BGR_TEST_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_BGR_TEST_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_BGR_TEST_CK_TSTSEL_SHIFT 8
+#define PMIC_RG_PCHR_TEST_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_PCHR_TEST_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_PCHR_TEST_CK_TSTSEL_SHIFT 9
+#define PMIC_RG_FQMTR_CK_TSTSEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_FQMTR_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_FQMTR_CK_TSTSEL_SHIFT 10
+#define PMIC_RG_DCXO1M_TSTCK_SEL_ADDR \
+ MT6389_TOP_CKTST_CON1
+#define PMIC_RG_DCXO1M_TSTCK_SEL_MASK 0x1
+#define PMIC_RG_DCXO1M_TSTCK_SEL_SHIFT 11
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_SEL_SHIFT 0
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_BUCK_SW_SHIFT 1
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_SEL_SHIFT 2
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_BM_SW_SHIFT 3
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_SEL_SHIFT 4
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_HK_SW_SHIFT 5
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_SEL_SHIFT 6
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_LDO_SW_SHIFT 7
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_SEL_SHIFT 8
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_SCK_SW_SHIFT 9
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_SEL_SHIFT 10
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_ADDR \
+ MT6389_TOP_CLK_CON0
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_MDB_SW_SHIFT 11
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_SEL_SHIFT 0
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_BUCK_SW_SHIFT 1
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_SEL_SHIFT 2
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_LDO_SW_SHIFT 3
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_SEL_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_SEL_SHIFT 4
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_ADDR \
+ MT6389_TOP_CLK_CON1
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_HK_SW_SHIFT 5
+#define PMIC_RG_TOP_MDB_DCM_SW_MODE_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_TOP_MDB_DCM_SW_MODE_MASK 0x1
+#define PMIC_RG_TOP_MDB_DCM_SW_MODE_SHIFT 0
+#define PMIC_RG_TOP_MDB_DCM_SW_EN_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_TOP_MDB_DCM_SW_EN_MASK 0x1
+#define PMIC_RG_TOP_MDB_DCM_SW_EN_SHIFT 1
+#define PMIC_RG_SCK_MDB_DCM_SW_MODE_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_SCK_MDB_DCM_SW_MODE_MASK 0x1
+#define PMIC_RG_SCK_MDB_DCM_SW_MODE_SHIFT 2
+#define PMIC_RG_SCK_MDB_DCM_SW_EN_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_SCK_MDB_DCM_SW_EN_MASK 0x1
+#define PMIC_RG_SCK_MDB_DCM_SW_EN_SHIFT 3
+#define PMIC_RG_LDO_MDB_DCM_SW_MODE_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_LDO_MDB_DCM_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_MDB_DCM_SW_MODE_SHIFT 4
+#define PMIC_RG_LDO_MDB_DCM_SW_EN_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_LDO_MDB_DCM_SW_EN_MASK 0x1
+#define PMIC_RG_LDO_MDB_DCM_SW_EN_SHIFT 5
+#define PMIC_RG_BUCK_MDB_DCM_SW_MODE_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_BUCK_MDB_DCM_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_MDB_DCM_SW_MODE_SHIFT 6
+#define PMIC_RG_BUCK_MDB_DCM_SW_EN_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_BUCK_MDB_DCM_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_MDB_DCM_SW_EN_SHIFT 7
+#define PMIC_RG_MDB_DCXO26M_DCM_LP_EN_ADDR \
+ MT6389_TOP_CLK_DCM0
+#define PMIC_RG_MDB_DCXO26M_DCM_LP_EN_MASK 0x1
+#define PMIC_RG_MDB_DCXO26M_DCM_LP_EN_SHIFT 12
+#define PMIC_RG_EFUSE_MAN_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_EFUSE_MAN_RST_MASK 0x1
+#define PMIC_RG_EFUSE_MAN_RST_SHIFT 0
+#define PMIC_RG_DRIVER_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_DRIVER_RST_MASK 0x1
+#define PMIC_RG_DRIVER_RST_SHIFT 6
+#define PMIC_RG_FQMTR_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_FQMTR_RST_MASK 0x1
+#define PMIC_RG_FQMTR_RST_SHIFT 8
+#define PMIC_RG_RTC_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_RTC_RST_MASK 0x1
+#define PMIC_RG_RTC_RST_SHIFT 9
+#define PMIC_RG_TYPE_C_CC_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_TYPE_C_CC_RST_MASK 0x1
+#define PMIC_RG_TYPE_C_CC_RST_SHIFT 10
+#define PMIC_RG_CLK_TRIM_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_CLK_TRIM_RST_MASK 0x1
+#define PMIC_RG_CLK_TRIM_RST_SHIFT 14
+#define PMIC_RG_BUCK_SRCLKEN_RST_ADDR \
+ MT6389_TOP_RST_CON0
+#define PMIC_RG_BUCK_SRCLKEN_RST_MASK 0x1
+#define PMIC_RG_BUCK_SRCLKEN_RST_SHIFT 15
+#define PMIC_TOP_RST_CON0_SET_ADDR \
+ MT6389_TOP_RST_CON0_SET
+#define PMIC_TOP_RST_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_RST_CON0_SET_SHIFT 0
+#define PMIC_TOP_RST_CON0_CLR_ADDR \
+ MT6389_TOP_RST_CON0_CLR
+#define PMIC_TOP_RST_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_RST_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_PROT_PMPP_RST_ADDR \
+ MT6389_TOP_RST_CON1
+#define PMIC_RG_BUCK_PROT_PMPP_RST_MASK 0x1
+#define PMIC_RG_BUCK_PROT_PMPP_RST_SHIFT 1
+#define PMIC_RG_SPK_RST_ADDR \
+ MT6389_TOP_RST_CON1
+#define PMIC_RG_SPK_RST_MASK 0x1
+#define PMIC_RG_SPK_RST_SHIFT 2
+#define PMIC_RG_FT_VR_SYSRSTB_ADDR \
+ MT6389_TOP_RST_CON1
+#define PMIC_RG_FT_VR_SYSRSTB_MASK 0x1
+#define PMIC_RG_FT_VR_SYSRSTB_SHIFT 4
+#define PMIC_RG_LDO_CALI_RST_ADDR \
+ MT6389_TOP_RST_CON1
+#define PMIC_RG_LDO_CALI_RST_MASK 0x1
+#define PMIC_RG_LDO_CALI_RST_SHIFT 7
+#define PMIC_TOP_RST_CON1_RSV_ADDR \
+ MT6389_TOP_RST_CON1
+#define PMIC_TOP_RST_CON1_RSV_MASK 0x1
+#define PMIC_TOP_RST_CON1_RSV_SHIFT 8
+#define PMIC_TOP_RST_CON1_SET_ADDR \
+ MT6389_TOP_RST_CON1_SET
+#define PMIC_TOP_RST_CON1_SET_MASK 0xFFFF
+#define PMIC_TOP_RST_CON1_SET_SHIFT 0
+#define PMIC_TOP_RST_CON1_CLR_ADDR \
+ MT6389_TOP_RST_CON1_CLR
+#define PMIC_TOP_RST_CON1_CLR_MASK 0xFFFF
+#define PMIC_TOP_RST_CON1_CLR_SHIFT 0
+#define PMIC_RG_CHR_LDO_DET_MODE_ADDR \
+ MT6389_TOP_RST_CON2
+#define PMIC_RG_CHR_LDO_DET_MODE_MASK 0x1
+#define PMIC_RG_CHR_LDO_DET_MODE_SHIFT 0
+#define PMIC_RG_CHR_LDO_DET_SW_ADDR \
+ MT6389_TOP_RST_CON2
+#define PMIC_RG_CHR_LDO_DET_SW_MASK 0x1
+#define PMIC_RG_CHR_LDO_DET_SW_SHIFT 1
+#define PMIC_RG_CHRWDT_FLAG_MODE_ADDR \
+ MT6389_TOP_RST_CON2
+#define PMIC_RG_CHRWDT_FLAG_MODE_MASK 0x1
+#define PMIC_RG_CHRWDT_FLAG_MODE_SHIFT 2
+#define PMIC_RG_CHRWDT_FLAG_SW_ADDR \
+ MT6389_TOP_RST_CON2
+#define PMIC_RG_CHRWDT_FLAG_SW_MASK 0x1
+#define PMIC_RG_CHRWDT_FLAG_SW_SHIFT 3
+#define PMIC_TOP_RST_CON2_RSV_ADDR \
+ MT6389_TOP_RST_CON2
+#define PMIC_TOP_RST_CON2_RSV_MASK 0xF
+#define PMIC_TOP_RST_CON2_RSV_SHIFT 4
+#define PMIC_RG_GPIO_RST_SEL_ADDR \
+ MT6389_TOP_RST_CON3
+#define PMIC_RG_GPIO_RST_SEL_MASK 0x1
+#define PMIC_RG_GPIO_RST_SEL_SHIFT 0
+#define PMIC_RG_WDTRSTB_EN_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_WDTRSTB_EN_MASK 0x1
+#define PMIC_RG_WDTRSTB_EN_SHIFT 0
+#define PMIC_RG_WDTRSTB_MODE_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_WDTRSTB_MODE_MASK 0x1
+#define PMIC_RG_WDTRSTB_MODE_SHIFT 1
+#define PMIC_WDTRSTB_STATUS_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_WDTRSTB_STATUS_MASK 0x1
+#define PMIC_WDTRSTB_STATUS_SHIFT 2
+#define PMIC_WDTRSTB_STATUS_CLR_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_WDTRSTB_STATUS_CLR_MASK 0x1
+#define PMIC_WDTRSTB_STATUS_CLR_SHIFT 3
+#define PMIC_RG_WDTRSTB_FB_EN_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_WDTRSTB_FB_EN_MASK 0x1
+#define PMIC_RG_WDTRSTB_FB_EN_SHIFT 4
+#define PMIC_RG_WDTRSTB_DEB_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_WDTRSTB_DEB_MASK 0x1
+#define PMIC_RG_WDTRSTB_DEB_SHIFT 5
+#define PMIC_RG_PWRKEY_KEY_MODE_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_PWRKEY_KEY_MODE_MASK 0x1
+#define PMIC_RG_PWRKEY_KEY_MODE_SHIFT 8
+#define PMIC_RG_PWRKEY_RST_EN_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_PWRKEY_RST_EN_MASK 0x1
+#define PMIC_RG_PWRKEY_RST_EN_SHIFT 9
+#define PMIC_RG_PWRRST_TMR_DIS_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_PWRRST_TMR_DIS_MASK 0x1
+#define PMIC_RG_PWRRST_TMR_DIS_SHIFT 10
+#define PMIC_RG_PWRKEY_RST_TD_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_RG_PWRKEY_RST_TD_MASK 0x3
+#define PMIC_RG_PWRKEY_RST_TD_SHIFT 12
+#define PMIC_TOP_RST_MISC_RSV_ADDR \
+ MT6389_TOP_RST_MISC
+#define PMIC_TOP_RST_MISC_RSV_MASK 0x3
+#define PMIC_TOP_RST_MISC_RSV_SHIFT 14
+#define PMIC_TOP_RST_MISC_SET_ADDR \
+ MT6389_TOP_RST_MISC_SET
+#define PMIC_TOP_RST_MISC_SET_MASK 0xFFFF
+#define PMIC_TOP_RST_MISC_SET_SHIFT 0
+#define PMIC_TOP_RST_MISC_CLR_ADDR \
+ MT6389_TOP_RST_MISC_CLR
+#define PMIC_TOP_RST_MISC_CLR_MASK 0xFFFF
+#define PMIC_TOP_RST_MISC_CLR_SHIFT 0
+#define PMIC_VPWRIN_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_VPWRIN_RSTB_STATUS_MASK 0x1
+#define PMIC_VPWRIN_RSTB_STATUS_SHIFT 0
+#define PMIC_DDLO_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_DDLO_RSTB_STATUS_MASK 0x1
+#define PMIC_DDLO_RSTB_STATUS_SHIFT 1
+#define PMIC_UVLO_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_UVLO_RSTB_STATUS_MASK 0x1
+#define PMIC_UVLO_RSTB_STATUS_SHIFT 2
+#define PMIC_RTC_DDLO_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_RTC_DDLO_RSTB_STATUS_MASK 0x1
+#define PMIC_RTC_DDLO_RSTB_STATUS_SHIFT 3
+#define PMIC_CHRWDT_REG_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_CHRWDT_REG_RSTB_STATUS_MASK 0x1
+#define PMIC_CHRWDT_REG_RSTB_STATUS_SHIFT 4
+#define PMIC_CHRDET_REG_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_CHRDET_REG_RSTB_STATUS_MASK 0x1
+#define PMIC_CHRDET_REG_RSTB_STATUS_SHIFT 5
+#define PMIC_BWDT_DDLO_RSTB_STATUS_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_BWDT_DDLO_RSTB_STATUS_MASK 0x1
+#define PMIC_BWDT_DDLO_RSTB_STATUS_SHIFT 6
+#define PMIC_TOP_RST_STATUS_RSV_ADDR \
+ MT6389_TOP_RST_STATUS
+#define PMIC_TOP_RST_STATUS_RSV_MASK 0x1
+#define PMIC_TOP_RST_STATUS_RSV_SHIFT 7
+#define PMIC_TOP_RST_STATUS_SET_ADDR \
+ MT6389_TOP_RST_STATUS_SET
+#define PMIC_TOP_RST_STATUS_SET_MASK 0xFFFF
+#define PMIC_TOP_RST_STATUS_SET_SHIFT 0
+#define PMIC_TOP_RST_STATUS_CLR_ADDR \
+ MT6389_TOP_RST_STATUS_CLR
+#define PMIC_TOP_RST_STATUS_CLR_MASK 0xFFFF
+#define PMIC_TOP_RST_STATUS_CLR_SHIFT 0
+#define PMIC_TOP2_ELR_LEN_ADDR \
+ MT6389_TOP2_ELR_NUM
+#define PMIC_TOP2_ELR_LEN_MASK 0xFF
+#define PMIC_TOP2_ELR_LEN_SHIFT 0
+#define PMIC_RG_TOP2_RSV0_ADDR \
+ MT6389_TOP2_ELR0
+#define PMIC_RG_TOP2_RSV0_MASK 0xFFFF
+#define PMIC_RG_TOP2_RSV0_SHIFT 0
+#define PMIC_RG_TOP2_RSV1_ADDR \
+ MT6389_TOP2_ELR1
+#define PMIC_RG_TOP2_RSV1_MASK 0xFFFF
+#define PMIC_RG_TOP2_RSV1_SHIFT 0
+#define PMIC_TOP3_ANA_ID_ADDR \
+ MT6389_TOP3_ID
+#define PMIC_TOP3_ANA_ID_MASK 0xFF
+#define PMIC_TOP3_ANA_ID_SHIFT 0
+#define PMIC_TOP3_DIG_ID_ADDR \
+ MT6389_TOP3_ID
+#define PMIC_TOP3_DIG_ID_MASK 0xFF
+#define PMIC_TOP3_DIG_ID_SHIFT 8
+#define PMIC_TOP3_ANA_MINOR_REV_ADDR \
+ MT6389_TOP3_REV0
+#define PMIC_TOP3_ANA_MINOR_REV_MASK 0xF
+#define PMIC_TOP3_ANA_MINOR_REV_SHIFT 0
+#define PMIC_TOP3_ANA_MAJOR_REV_ADDR \
+ MT6389_TOP3_REV0
+#define PMIC_TOP3_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_TOP3_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_TOP3_DIG_MINOR_REV_ADDR \
+ MT6389_TOP3_REV0
+#define PMIC_TOP3_DIG_MINOR_REV_MASK 0xF
+#define PMIC_TOP3_DIG_MINOR_REV_SHIFT 8
+#define PMIC_TOP3_DIG_MAJOR_REV_ADDR \
+ MT6389_TOP3_REV0
+#define PMIC_TOP3_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_TOP3_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_TOP3_DSN_CBS_ADDR \
+ MT6389_TOP3_DSN_DBI
+#define PMIC_TOP3_DSN_CBS_MASK 0x3
+#define PMIC_TOP3_DSN_CBS_SHIFT 0
+#define PMIC_TOP3_DSN_BIX_ADDR \
+ MT6389_TOP3_DSN_DBI
+#define PMIC_TOP3_DSN_BIX_MASK 0x3
+#define PMIC_TOP3_DSN_BIX_SHIFT 2
+#define PMIC_TOP3_DSN_ESP_ADDR \
+ MT6389_TOP3_DSN_DBI
+#define PMIC_TOP3_DSN_ESP_MASK 0xFF
+#define PMIC_TOP3_DSN_ESP_SHIFT 8
+#define PMIC_TOP3_DSN_FPI_ADDR \
+ MT6389_TOP3_DSN_DXI
+#define PMIC_TOP3_DSN_FPI_MASK 0xFF
+#define PMIC_TOP3_DSN_FPI_SHIFT 0
+#define PMIC_RG_INT_EN_SPI_CMD_ALERT_ADDR \
+ MT6389_MISC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_SPI_CMD_ALERT_MASK 0x1
+#define PMIC_RG_INT_EN_SPI_CMD_ALERT_SHIFT 0
+#define PMIC_MISC_TOP_INT_CON0_SET_ADDR \
+ MT6389_MISC_TOP_INT_CON0_SET
+#define PMIC_MISC_TOP_INT_CON0_SET_MASK 0xFFFF
+#define PMIC_MISC_TOP_INT_CON0_SET_SHIFT 0
+#define PMIC_MISC_TOP_INT_CON0_CLR_ADDR \
+ MT6389_MISC_TOP_INT_CON0_CLR
+#define PMIC_MISC_TOP_INT_CON0_CLR_MASK 0xFFFF
+#define PMIC_MISC_TOP_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_ADDR \
+ MT6389_MISC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_MASK 0x1
+#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_SHIFT 0
+#define PMIC_MISC_TOP_INT_MASK_CON0_SET_ADDR \
+ MT6389_MISC_TOP_INT_MASK_CON0_SET
+#define PMIC_MISC_TOP_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_MISC_TOP_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_ADDR \
+ MT6389_MISC_TOP_INT_MASK_CON0_CLR
+#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_ADDR \
+ MT6389_MISC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_MASK 0x1
+#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_ADDR \
+ MT6389_MISC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_SHIFT 0
+#define PMIC_RG_INT_MASK_BUCK_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BUCK_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_BUCK_TOP_SHIFT 0
+#define PMIC_RG_INT_MASK_LDO_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_LDO_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_LDO_TOP_SHIFT 1
+#define PMIC_RG_INT_MASK_PSC_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_PSC_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_PSC_TOP_SHIFT 2
+#define PMIC_RG_INT_MASK_SCK_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_SCK_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_SCK_TOP_SHIFT 3
+#define PMIC_RG_INT_MASK_BM_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BM_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_BM_TOP_SHIFT 4
+#define PMIC_RG_INT_MASK_HK_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_HK_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_HK_TOP_SHIFT 5
+#define PMIC_RG_INT_MASK_XPP_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_XPP_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_XPP_TOP_SHIFT 6
+#define PMIC_RG_INT_MASK_AUD_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_AUD_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_AUD_TOP_SHIFT 7
+#define PMIC_RG_INT_MASK_MISC_TOP_ADDR \
+ MT6389_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_MISC_TOP_MASK 0x1
+#define PMIC_RG_INT_MASK_MISC_TOP_SHIFT 8
+#define PMIC_TOP_INT_MASK_CON0_SET_ADDR \
+ MT6389_TOP_INT_MASK_CON0_SET
+#define PMIC_TOP_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_TOP_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_TOP_INT_MASK_CON0_CLR_ADDR \
+ MT6389_TOP_INT_MASK_CON0_CLR
+#define PMIC_TOP_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_TOP_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_INT_STATUS_BUCK_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_BUCK_TOP_MASK 0x1
+#define PMIC_INT_STATUS_BUCK_TOP_SHIFT 0
+#define PMIC_INT_STATUS_LDO_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_LDO_TOP_MASK 0x1
+#define PMIC_INT_STATUS_LDO_TOP_SHIFT 1
+#define PMIC_INT_STATUS_PSC_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_PSC_TOP_MASK 0x1
+#define PMIC_INT_STATUS_PSC_TOP_SHIFT 2
+#define PMIC_INT_STATUS_SCK_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_SCK_TOP_MASK 0x1
+#define PMIC_INT_STATUS_SCK_TOP_SHIFT 3
+#define PMIC_INT_STATUS_BM_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_BM_TOP_MASK 0x1
+#define PMIC_INT_STATUS_BM_TOP_SHIFT 4
+#define PMIC_INT_STATUS_HK_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_HK_TOP_MASK 0x1
+#define PMIC_INT_STATUS_HK_TOP_SHIFT 5
+#define PMIC_INT_STATUS_XPP_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_XPP_TOP_MASK 0x1
+#define PMIC_INT_STATUS_XPP_TOP_SHIFT 6
+#define PMIC_INT_STATUS_AUD_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_AUD_TOP_MASK 0x1
+#define PMIC_INT_STATUS_AUD_TOP_SHIFT 7
+#define PMIC_INT_STATUS_MISC_TOP_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_MISC_TOP_MASK 0x1
+#define PMIC_INT_STATUS_MISC_TOP_SHIFT 8
+#define PMIC_INT_STATUS_TOP_RSV_ADDR \
+ MT6389_TOP_INT_STATUS0
+#define PMIC_INT_STATUS_TOP_RSV_MASK 0x7F
+#define PMIC_INT_STATUS_TOP_RSV_SHIFT 9
+#define PMIC_INT_RAW_STATUS_BUCK_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_BUCK_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_BUCK_TOP_SHIFT 0
+#define PMIC_INT_RAW_STATUS_LDO_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_LDO_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_LDO_TOP_SHIFT 1
+#define PMIC_INT_RAW_STATUS_PSC_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_PSC_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_PSC_TOP_SHIFT 2
+#define PMIC_INT_RAW_STATUS_SCK_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_SCK_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_SCK_TOP_SHIFT 3
+#define PMIC_INT_RAW_STATUS_BM_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_BM_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_BM_TOP_SHIFT 4
+#define PMIC_INT_RAW_STATUS_HK_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_HK_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_HK_TOP_SHIFT 5
+#define PMIC_INT_RAW_STATUS_XPP_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_XPP_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_XPP_TOP_SHIFT 6
+#define PMIC_INT_RAW_STATUS_AUD_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_AUD_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_AUD_TOP_SHIFT 7
+#define PMIC_INT_RAW_STATUS_MISC_TOP_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_MISC_TOP_MASK 0x1
+#define PMIC_INT_RAW_STATUS_MISC_TOP_SHIFT 8
+#define PMIC_INT_RAW_STATUS_TOP_RSV_ADDR \
+ MT6389_TOP_INT_RAW_STATUS0
+#define PMIC_INT_RAW_STATUS_TOP_RSV_MASK 0x7F
+#define PMIC_INT_RAW_STATUS_TOP_RSV_SHIFT 9
+#define PMIC_RG_INT_POLARITY_ADDR \
+ MT6389_TOP_INT_CON0
+#define PMIC_RG_INT_POLARITY_MASK 0x1
+#define PMIC_RG_INT_POLARITY_SHIFT 0
+#define PMIC_RG_DCXO26M_CKEN_SW_SEL_ADDR \
+ MT6389_TOP_DCXO_CKEN_SW
+#define PMIC_RG_DCXO26M_CKEN_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_SW_SEL_SHIFT 0
+#define PMIC_RG_DCXO26M_CKEN_SW_ADDR \
+ MT6389_TOP_DCXO_CKEN_SW
+#define PMIC_RG_DCXO26M_CKEN_SW_MASK 0x1
+#define PMIC_RG_DCXO26M_CKEN_SW_SHIFT 1
+#define PMIC_RG_DCXO1M_CKEN_SW_SEL_ADDR \
+ MT6389_TOP_DCXO_CKEN_SW
+#define PMIC_RG_DCXO1M_CKEN_SW_SEL_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_SW_SEL_SHIFT 2
+#define PMIC_RG_DCXO1M_CKEN_SW_ADDR \
+ MT6389_TOP_DCXO_CKEN_SW
+#define PMIC_RG_DCXO1M_CKEN_SW_MASK 0x1
+#define PMIC_RG_DCXO1M_CKEN_SW_SHIFT 3
+#define PMIC_PMRC_EN_ADDR \
+ MT6389_PMRC_CON0
+#define PMIC_PMRC_EN_MASK 0xFFFF
+#define PMIC_PMRC_EN_SHIFT 0
+#define PMIC_PMRC_EN_SET_ADDR \
+ MT6389_PMRC_CON0_SET
+#define PMIC_PMRC_EN_SET_MASK 0xFFFF
+#define PMIC_PMRC_EN_SET_SHIFT 0
+#define PMIC_PMRC_EN_CLR_ADDR \
+ MT6389_PMRC_CON0_CLR
+#define PMIC_PMRC_EN_CLR_MASK 0xFFFF
+#define PMIC_PMRC_EN_CLR_SHIFT 0
+#define PMIC_RG_VR_SPM_MODE_ADDR \
+ MT6389_PMRC_CON1
+#define PMIC_RG_VR_SPM_MODE_MASK 0x1
+#define PMIC_RG_VR_SPM_MODE_SHIFT 0
+#define PMIC_RG_VR_MD_MODE_ADDR \
+ MT6389_PMRC_CON1
+#define PMIC_RG_VR_MD_MODE_MASK 0x1
+#define PMIC_RG_VR_MD_MODE_SHIFT 1
+#define PMIC_RG_VR_SSHUB_MODE_ADDR \
+ MT6389_PMRC_CON1
+#define PMIC_RG_VR_SSHUB_MODE_MASK 0x1
+#define PMIC_RG_VR_SSHUB_MODE_SHIFT 2
+#define PMIC_PMRC_CON1_SET_ADDR \
+ MT6389_PMRC_CON1_SET
+#define PMIC_PMRC_CON1_SET_MASK 0xFFFF
+#define PMIC_PMRC_CON1_SET_SHIFT 0
+#define PMIC_PMRC_CON1_CLR_ADDR \
+ MT6389_PMRC_CON1_CLR
+#define PMIC_PMRC_CON1_CLR_MASK 0xFFFF
+#define PMIC_PMRC_CON1_CLR_SHIFT 0
+#define PMIC_RG_SRCLKEN2_MODE_ADDR \
+ MT6389_PMRC_CON2
+#define PMIC_RG_SRCLKEN2_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN2_MODE_SHIFT 0
+#define PMIC_RG_SRCLKEN3_MODE_ADDR \
+ MT6389_PMRC_CON2
+#define PMIC_RG_SRCLKEN3_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN3_MODE_SHIFT 1
+#define PMIC_PLT0_ANA_ID_ADDR \
+ MT6389_PLT0_ID
+#define PMIC_PLT0_ANA_ID_MASK 0xFF
+#define PMIC_PLT0_ANA_ID_SHIFT 0
+#define PMIC_PLT0_DIG_ID_ADDR \
+ MT6389_PLT0_ID
+#define PMIC_PLT0_DIG_ID_MASK 0xFF
+#define PMIC_PLT0_DIG_ID_SHIFT 8
+#define PMIC_PLT0_ANA_MINOR_REV_ADDR \
+ MT6389_PLT0_REV0
+#define PMIC_PLT0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_PLT0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_PLT0_ANA_MAJOR_REV_ADDR \
+ MT6389_PLT0_REV0
+#define PMIC_PLT0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_PLT0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_PLT0_DIG_MINOR_REV_ADDR \
+ MT6389_PLT0_REV0
+#define PMIC_PLT0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_PLT0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_PLT0_DIG_MAJOR_REV_ADDR \
+ MT6389_PLT0_REV0
+#define PMIC_PLT0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_PLT0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_PLT0_DSN_CBS_ADDR \
+ MT6389_PLT0_REV1
+#define PMIC_PLT0_DSN_CBS_MASK 0x3
+#define PMIC_PLT0_DSN_CBS_SHIFT 0
+#define PMIC_PLT0_DSN_BIX_ADDR \
+ MT6389_PLT0_REV1
+#define PMIC_PLT0_DSN_BIX_MASK 0x3
+#define PMIC_PLT0_DSN_BIX_SHIFT 2
+#define PMIC_PLT0_DSN_ESP_ADDR \
+ MT6389_PLT0_REV1
+#define PMIC_PLT0_DSN_ESP_MASK 0xFF
+#define PMIC_PLT0_DSN_ESP_SHIFT 8
+#define PMIC_PLT0_DSN_FPI_ADDR \
+ MT6389_PLT0_DSN_DXI
+#define PMIC_PLT0_DSN_FPI_MASK 0xFF
+#define PMIC_PLT0_DSN_FPI_SHIFT 0
+#define PMIC_RG_OSC_128K_TRIM_EN_ADDR \
+ MT6389_TOP_CLK_TRIM
+#define PMIC_RG_OSC_128K_TRIM_EN_MASK 0x1
+#define PMIC_RG_OSC_128K_TRIM_EN_SHIFT 6
+#define PMIC_RG_OSC_128K_TRIM_RATE_ADDR \
+ MT6389_TOP_CLK_TRIM
+#define PMIC_RG_OSC_128K_TRIM_RATE_MASK 0x3
+#define PMIC_RG_OSC_128K_TRIM_RATE_SHIFT 7
+#define PMIC_DA_OSC_128K_TRIM_ADDR \
+ MT6389_TOP_CLK_TRIM
+#define PMIC_DA_OSC_128K_TRIM_MASK 0x3F
+#define PMIC_DA_OSC_128K_TRIM_SHIFT 9
+#define PMIC_RG_OTP_PA_ADDR \
+ MT6389_OTP_CON0
+#define PMIC_RG_OTP_PA_MASK 0xFF
+#define PMIC_RG_OTP_PA_SHIFT 0
+#define PMIC_RG_OTP_PDIN_ADDR \
+ MT6389_OTP_CON1
+#define PMIC_RG_OTP_PDIN_MASK 0xFF
+#define PMIC_RG_OTP_PDIN_SHIFT 0
+#define PMIC_RG_OTP_PTM_ADDR \
+ MT6389_OTP_CON2
+#define PMIC_RG_OTP_PTM_MASK 0x3
+#define PMIC_RG_OTP_PTM_SHIFT 0
+#define PMIC_RG_OTP_PWE_ADDR \
+ MT6389_OTP_CON3
+#define PMIC_RG_OTP_PWE_MASK 0x7
+#define PMIC_RG_OTP_PWE_SHIFT 0
+#define PMIC_RG_OTP_PPROG_ADDR \
+ MT6389_OTP_CON4
+#define PMIC_RG_OTP_PPROG_MASK 0x1
+#define PMIC_RG_OTP_PPROG_SHIFT 0
+#define PMIC_RG_OTP_PWE_SRC_ADDR \
+ MT6389_OTP_CON5
+#define PMIC_RG_OTP_PWE_SRC_MASK 0x1
+#define PMIC_RG_OTP_PWE_SRC_SHIFT 0
+#define PMIC_RG_OTP_PROG_PKEY_ADDR \
+ MT6389_OTP_CON6
+#define PMIC_RG_OTP_PROG_PKEY_MASK 0xFFFF
+#define PMIC_RG_OTP_PROG_PKEY_SHIFT 0
+#define PMIC_RG_OTP_RD_PKEY_ADDR \
+ MT6389_OTP_CON7
+#define PMIC_RG_OTP_RD_PKEY_MASK 0xFFFF
+#define PMIC_RG_OTP_RD_PKEY_SHIFT 0
+#define PMIC_RG_OTP_RD_TRIG_ADDR \
+ MT6389_OTP_CON8
+#define PMIC_RG_OTP_RD_TRIG_MASK 0x1
+#define PMIC_RG_OTP_RD_TRIG_SHIFT 0
+#define PMIC_RG_RD_RDY_BYPASS_ADDR \
+ MT6389_OTP_CON9
+#define PMIC_RG_RD_RDY_BYPASS_MASK 0x1
+#define PMIC_RG_RD_RDY_BYPASS_SHIFT 0
+#define PMIC_RG_SKIP_OTP_OUT_ADDR \
+ MT6389_OTP_CON10
+#define PMIC_RG_SKIP_OTP_OUT_MASK 0x1
+#define PMIC_RG_SKIP_OTP_OUT_SHIFT 0
+#define PMIC_RG_OTP_RD_SW_ADDR \
+ MT6389_OTP_CON11
+#define PMIC_RG_OTP_RD_SW_MASK 0x1
+#define PMIC_RG_OTP_RD_SW_SHIFT 0
+#define PMIC_RG_OTP_DOUT_SW_ADDR \
+ MT6389_OTP_CON12
+#define PMIC_RG_OTP_DOUT_SW_MASK 0xFFFF
+#define PMIC_RG_OTP_DOUT_SW_SHIFT 0
+#define PMIC_RG_OTP_RD_BUSY_ADDR \
+ MT6389_OTP_CON13
+#define PMIC_RG_OTP_RD_BUSY_MASK 0x1
+#define PMIC_RG_OTP_RD_BUSY_SHIFT 0
+#define PMIC_RG_OTP_RD_ACK_ADDR \
+ MT6389_OTP_CON13
+#define PMIC_RG_OTP_RD_ACK_MASK 0x1
+#define PMIC_RG_OTP_RD_ACK_SHIFT 2
+#define PMIC_RG_OTP_PA_SW_ADDR \
+ MT6389_OTP_CON14
+#define PMIC_RG_OTP_PA_SW_MASK 0x7F
+#define PMIC_RG_OTP_PA_SW_SHIFT 0
+#define PMIC_OTP_DOUT_0_ADDR \
+ MT6389_OTP_CON15
+#define PMIC_OTP_DOUT_0_MASK 0xFFFF
+#define PMIC_OTP_DOUT_0_SHIFT 0
+#define PMIC_OTP_DOUT_1_ADDR \
+ MT6389_OTP_CON16
+#define PMIC_OTP_DOUT_1_MASK 0xFFFF
+#define PMIC_OTP_DOUT_1_SHIFT 0
+#define PMIC_OTP_DOUT_2_ADDR \
+ MT6389_OTP_CON17
+#define PMIC_OTP_DOUT_2_MASK 0xFFFF
+#define PMIC_OTP_DOUT_2_SHIFT 0
+#define PMIC_OTP_DOUT_HW_ADDR \
+ MT6389_OTP_CON18
+#define PMIC_OTP_DOUT_HW_MASK 0xFFFF
+#define PMIC_OTP_DOUT_HW_SHIFT 0
+#define PMIC_RG_OTP_PROG_MACRO_SEL_ADDR \
+ MT6389_OTP_CON19
+#define PMIC_RG_OTP_PROG_MACRO_SEL_MASK 0x3
+#define PMIC_RG_OTP_PROG_MACRO_SEL_SHIFT 0
+#define PMIC_RG_OTP_MISMATCH_PA_CLR_ADDR \
+ MT6389_OTP_CON20
+#define PMIC_RG_OTP_MISMATCH_PA_CLR_MASK 0x1
+#define PMIC_RG_OTP_MISMATCH_PA_CLR_SHIFT 0
+#define PMIC_RG_OTP_MISMATCH_PA_0_ADDR \
+ MT6389_OTP_CON21
+#define PMIC_RG_OTP_MISMATCH_PA_0_MASK 0x1FF
+#define PMIC_RG_OTP_MISMATCH_PA_0_SHIFT 0
+#define PMIC_RG_OTP_MISMATCH_PA_1_ADDR \
+ MT6389_OTP_CON22
+#define PMIC_RG_OTP_MISMATCH_PA_1_MASK 0x1FF
+#define PMIC_RG_OTP_MISMATCH_PA_1_SHIFT 0
+#define PMIC_TMA_KEY_ADDR \
+ MT6389_TOP_TMA_KEY
+#define PMIC_TMA_KEY_MASK 0xFFFF
+#define PMIC_TMA_KEY_SHIFT 0
+#define PMIC_TOP_MDB_RSV0_ADDR \
+ MT6389_TOP_MDB_CONF0
+#define PMIC_TOP_MDB_RSV0_MASK 0xFFFF
+#define PMIC_TOP_MDB_RSV0_SHIFT 0
+#define PMIC_TOP_MDB_RSV1_ADDR \
+ MT6389_TOP_MDB_CONF1
+#define PMIC_TOP_MDB_RSV1_MASK 0xFFFF
+#define PMIC_TOP_MDB_RSV1_SHIFT 0
+#define PMIC_RG_MDB_DM1_DS_EN_ADDR \
+ MT6389_TOP_MDB_CONF2
+#define PMIC_RG_MDB_DM1_DS_EN_MASK 0x1
+#define PMIC_RG_MDB_DM1_DS_EN_SHIFT 0
+#define PMIC_RG_AUTO_LOAD_FORCE_ADDR \
+ MT6389_TOP_MDB_CONF2
+#define PMIC_RG_AUTO_LOAD_FORCE_MASK 0x1
+#define PMIC_RG_AUTO_LOAD_FORCE_SHIFT 1
+#define PMIC_RG_OTP_WRITE_SEL_ADDR \
+ MT6389_TOP_MDB_CONF2
+#define PMIC_RG_OTP_WRITE_SEL_MASK 0x1
+#define PMIC_RG_OTP_WRITE_SEL_SHIFT 2
+#define PMIC_RG_TOP_MDB_BRIDGE_BYPASS_EN_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_TOP_MDB_BRIDGE_BYPASS_EN_MASK 0x1
+#define PMIC_RG_TOP_MDB_BRIDGE_BYPASS_EN_SHIFT 0
+#define PMIC_RG_SCK_MDB_BRIDGE_BYPASS_EN_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_SCK_MDB_BRIDGE_BYPASS_EN_MASK 0x1
+#define PMIC_RG_SCK_MDB_BRIDGE_BYPASS_EN_SHIFT 1
+#define PMIC_RG_LDO_MDB_BRIDGE_BYPASS_EN_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_LDO_MDB_BRIDGE_BYPASS_EN_MASK 0x1
+#define PMIC_RG_LDO_MDB_BRIDGE_BYPASS_EN_SHIFT 2
+#define PMIC_RG_BUCK_MDB_BRIDGE_BYPASS_EN_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_BUCK_MDB_BRIDGE_BYPASS_EN_MASK 0x1
+#define PMIC_RG_BUCK_MDB_BRIDGE_BYPASS_EN_SHIFT 3
+#define PMIC_RG_MDB_BRDG_ACS_SUSPEND_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_MDB_BRDG_ACS_SUSPEND_MASK 0x1
+#define PMIC_RG_MDB_BRDG_ACS_SUSPEND_SHIFT 8
+#define PMIC_RG_MDB_BRDG_ACS_DEEPIDLE_ADDR \
+ MT6389_TOP_MDB_CONF3
+#define PMIC_RG_MDB_BRDG_ACS_DEEPIDLE_MASK 0x1
+#define PMIC_RG_MDB_BRDG_ACS_DEEPIDLE_SHIFT 9
+#define PMIC_PLT0_ELR_LEN_ADDR \
+ MT6389_PLT0_ELR_NUM
+#define PMIC_PLT0_ELR_LEN_MASK 0xFF
+#define PMIC_PLT0_ELR_LEN_SHIFT 0
+#define PMIC_RG_OSC_128K_TRIM_ADDR \
+ MT6389_PLT0_ELR0
+#define PMIC_RG_OSC_128K_TRIM_MASK 0x3F
+#define PMIC_RG_OSC_128K_TRIM_SHIFT 0
+#define PMIC_SPISLV_ANA_ID_ADDR \
+ MT6389_SPISLV_ID
+#define PMIC_SPISLV_ANA_ID_MASK 0xFF
+#define PMIC_SPISLV_ANA_ID_SHIFT 0
+#define PMIC_SPISLV_DIG_ID_ADDR \
+ MT6389_SPISLV_ID
+#define PMIC_SPISLV_DIG_ID_MASK 0xFF
+#define PMIC_SPISLV_DIG_ID_SHIFT 8
+#define PMIC_SPISLV_ANA_MINOR_REV_ADDR \
+ MT6389_SPISLV_REV0
+#define PMIC_SPISLV_ANA_MINOR_REV_MASK 0xF
+#define PMIC_SPISLV_ANA_MINOR_REV_SHIFT 0
+#define PMIC_SPISLV_ANA_MAJOR_REV_ADDR \
+ MT6389_SPISLV_REV0
+#define PMIC_SPISLV_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_SPISLV_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_SPISLV_DIG_MINOR_REV_ADDR \
+ MT6389_SPISLV_REV0
+#define PMIC_SPISLV_DIG_MINOR_REV_MASK 0xF
+#define PMIC_SPISLV_DIG_MINOR_REV_SHIFT 8
+#define PMIC_SPISLV_DIG_MAJOR_REV_ADDR \
+ MT6389_SPISLV_REV0
+#define PMIC_SPISLV_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_SPISLV_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_SPISLV_DSN_CBS_ADDR \
+ MT6389_SPISLV_REV1
+#define PMIC_SPISLV_DSN_CBS_MASK 0x3
+#define PMIC_SPISLV_DSN_CBS_SHIFT 0
+#define PMIC_SPISLV_DSN_BIX_ADDR \
+ MT6389_SPISLV_REV1
+#define PMIC_SPISLV_DSN_BIX_MASK 0x3
+#define PMIC_SPISLV_DSN_BIX_SHIFT 2
+#define PMIC_SPISLV_DSN_ESP_ADDR \
+ MT6389_SPISLV_REV1
+#define PMIC_SPISLV_DSN_ESP_MASK 0xFF
+#define PMIC_SPISLV_DSN_ESP_SHIFT 8
+#define PMIC_SPISLV_DSN_FPI_ADDR \
+ MT6389_SPISLV_DSN_DXI
+#define PMIC_SPISLV_DSN_FPI_MASK 0xFF
+#define PMIC_SPISLV_DSN_FPI_SHIFT 0
+#define PMIC_RG_SPI_MISO_MODE_SEL_ADDR \
+ MT6389_RG_SPI_CON0
+#define PMIC_RG_SPI_MISO_MODE_SEL_MASK 0x3
+#define PMIC_RG_SPI_MISO_MODE_SEL_SHIFT 0
+#define PMIC_RG_EN_RECORD_ADDR \
+ MT6389_RG_SPI_RECORD0
+#define PMIC_RG_EN_RECORD_MASK 0x1
+#define PMIC_RG_EN_RECORD_SHIFT 0
+#define PMIC_RG_RD_RECORD_EN_ADDR \
+ MT6389_RG_SPI_RECORD0
+#define PMIC_RG_RD_RECORD_EN_MASK 0x1
+#define PMIC_RG_RD_RECORD_EN_SHIFT 1
+#define PMIC_RG_SPI_RSV_ADDR \
+ MT6389_RG_SPI_RECORD0
+#define PMIC_RG_SPI_RSV_MASK 0x3FFF
+#define PMIC_RG_SPI_RSV_SHIFT 2
+#define PMIC_DEW_DIO_EN_ADDR \
+ MT6389_DEW_DIO_EN
+#define PMIC_DEW_DIO_EN_MASK 0x1
+#define PMIC_DEW_DIO_EN_SHIFT 0
+#define PMIC_DEW_READ_TEST_ADDR \
+ MT6389_DEW_READ_TEST
+#define PMIC_DEW_READ_TEST_MASK 0xFFFF
+#define PMIC_DEW_READ_TEST_SHIFT 0
+#define PMIC_DEW_WRITE_TEST_ADDR \
+ MT6389_DEW_WRITE_TEST
+#define PMIC_DEW_WRITE_TEST_MASK 0xFFFF
+#define PMIC_DEW_WRITE_TEST_SHIFT 0
+#define PMIC_DEW_CRC_SWRST_ADDR \
+ MT6389_DEW_CRC_SWRST
+#define PMIC_DEW_CRC_SWRST_MASK 0x1
+#define PMIC_DEW_CRC_SWRST_SHIFT 0
+#define PMIC_DEW_CRC_EN_ADDR \
+ MT6389_DEW_CRC_EN
+#define PMIC_DEW_CRC_EN_MASK 0x1
+#define PMIC_DEW_CRC_EN_SHIFT 0
+#define PMIC_DEW_CRC_VAL_ADDR \
+ MT6389_DEW_CRC_VAL
+#define PMIC_DEW_CRC_VAL_MASK 0xFF
+#define PMIC_DEW_CRC_VAL_SHIFT 0
+#define PMIC_DEW_CIPHER_KEY_SEL_ADDR \
+ MT6389_DEW_CIPHER_KEY_SEL
+#define PMIC_DEW_CIPHER_KEY_SEL_MASK 0x3
+#define PMIC_DEW_CIPHER_KEY_SEL_SHIFT 0
+#define PMIC_DEW_CIPHER_IV_SEL_ADDR \
+ MT6389_DEW_CIPHER_IV_SEL
+#define PMIC_DEW_CIPHER_IV_SEL_MASK 0x3
+#define PMIC_DEW_CIPHER_IV_SEL_SHIFT 0
+#define PMIC_DEW_CIPHER_EN_ADDR \
+ MT6389_DEW_CIPHER_EN
+#define PMIC_DEW_CIPHER_EN_MASK 0x1
+#define PMIC_DEW_CIPHER_EN_SHIFT 0
+#define PMIC_DEW_CIPHER_RDY_ADDR \
+ MT6389_DEW_CIPHER_RDY
+#define PMIC_DEW_CIPHER_RDY_MASK 0x1
+#define PMIC_DEW_CIPHER_RDY_SHIFT 0
+#define PMIC_DEW_CIPHER_MODE_ADDR \
+ MT6389_DEW_CIPHER_MODE
+#define PMIC_DEW_CIPHER_MODE_MASK 0x1
+#define PMIC_DEW_CIPHER_MODE_SHIFT 0
+#define PMIC_DEW_CIPHER_SWRST_ADDR \
+ MT6389_DEW_CIPHER_SWRST
+#define PMIC_DEW_CIPHER_SWRST_MASK 0x1
+#define PMIC_DEW_CIPHER_SWRST_SHIFT 0
+#define PMIC_DEW_RDDMY_NO_ADDR \
+ MT6389_DEW_RDDMY_NO
+#define PMIC_DEW_RDDMY_NO_MASK 0xF
+#define PMIC_DEW_RDDMY_NO_SHIFT 0
+#define PMIC_RG_SPI_DLY_SEL_ADDR \
+ MT6389_RG_SPI_CON2
+#define PMIC_RG_SPI_DLY_SEL_MASK 0xF
+#define PMIC_RG_SPI_DLY_SEL_SHIFT 0
+#define PMIC_RECORD_CMD0_ADDR \
+ MT6389_RECORD_CMD0
+#define PMIC_RECORD_CMD0_MASK 0xFFFF
+#define PMIC_RECORD_CMD0_SHIFT 0
+#define PMIC_RECORD_CMD1_ADDR \
+ MT6389_RECORD_CMD1
+#define PMIC_RECORD_CMD1_MASK 0xFFFF
+#define PMIC_RECORD_CMD1_SHIFT 0
+#define PMIC_RECORD_CMD2_ADDR \
+ MT6389_RECORD_CMD2
+#define PMIC_RECORD_CMD2_MASK 0xFFFF
+#define PMIC_RECORD_CMD2_SHIFT 0
+#define PMIC_RECORD_CMD3_ADDR \
+ MT6389_RECORD_CMD3
+#define PMIC_RECORD_CMD3_MASK 0xFFFF
+#define PMIC_RECORD_CMD3_SHIFT 0
+#define PMIC_RECORD_CMD4_ADDR \
+ MT6389_RECORD_CMD4
+#define PMIC_RECORD_CMD4_MASK 0xFFFF
+#define PMIC_RECORD_CMD4_SHIFT 0
+#define PMIC_RECORD_CMD5_ADDR \
+ MT6389_RECORD_CMD5
+#define PMIC_RECORD_CMD5_MASK 0xFFFF
+#define PMIC_RECORD_CMD5_SHIFT 0
+#define PMIC_RECORD_WDATA0_ADDR \
+ MT6389_RECORD_WDATA0
+#define PMIC_RECORD_WDATA0_MASK 0xFFFF
+#define PMIC_RECORD_WDATA0_SHIFT 0
+#define PMIC_RECORD_WDATA1_ADDR \
+ MT6389_RECORD_WDATA1
+#define PMIC_RECORD_WDATA1_MASK 0xFFFF
+#define PMIC_RECORD_WDATA1_SHIFT 0
+#define PMIC_RECORD_WDATA2_ADDR \
+ MT6389_RECORD_WDATA2
+#define PMIC_RECORD_WDATA2_MASK 0xFFFF
+#define PMIC_RECORD_WDATA2_SHIFT 0
+#define PMIC_RECORD_WDATA3_ADDR \
+ MT6389_RECORD_WDATA3
+#define PMIC_RECORD_WDATA3_MASK 0xFFFF
+#define PMIC_RECORD_WDATA3_SHIFT 0
+#define PMIC_RECORD_WDATA4_ADDR \
+ MT6389_RECORD_WDATA4
+#define PMIC_RECORD_WDATA4_MASK 0xFFFF
+#define PMIC_RECORD_WDATA4_SHIFT 0
+#define PMIC_RECORD_WDATA5_ADDR \
+ MT6389_RECORD_WDATA5
+#define PMIC_RECORD_WDATA5_MASK 0xFFFF
+#define PMIC_RECORD_WDATA5_SHIFT 0
+#define PMIC_RG_ADDR_TARGET_ADDR \
+ MT6389_RG_SPI_CON9
+#define PMIC_RG_ADDR_TARGET_MASK 0xFFFF
+#define PMIC_RG_ADDR_TARGET_SHIFT 0
+#define PMIC_RG_ADDR_MASK_ADDR \
+ MT6389_RG_SPI_CON10
+#define PMIC_RG_ADDR_MASK_MASK 0xFFFF
+#define PMIC_RG_ADDR_MASK_SHIFT 0
+#define PMIC_RG_WDATA_TARGET_ADDR \
+ MT6389_RG_SPI_CON11
+#define PMIC_RG_WDATA_TARGET_MASK 0xFFFF
+#define PMIC_RG_WDATA_TARGET_SHIFT 0
+#define PMIC_RG_WDATA_MASK_ADDR \
+ MT6389_RG_SPI_CON12
+#define PMIC_RG_WDATA_MASK_MASK 0xFFFF
+#define PMIC_RG_WDATA_MASK_SHIFT 0
+#define PMIC_RG_SPI_RECORD_CLR_ADDR \
+ MT6389_RG_SPI_CON13
+#define PMIC_RG_SPI_RECORD_CLR_MASK 0x1
+#define PMIC_RG_SPI_RECORD_CLR_SHIFT 0
+#define PMIC_RG_CMD_ALERT_CLR_ADDR \
+ MT6389_RG_SPI_CON13
+#define PMIC_RG_CMD_ALERT_CLR_MASK 0x1
+#define PMIC_RG_CMD_ALERT_CLR_SHIFT 15
+#define PMIC_SPISLV_KEY_ADDR \
+ MT6389_SPISLV_KEY
+#define PMIC_SPISLV_KEY_MASK 0xFFFF
+#define PMIC_SPISLV_KEY_SHIFT 0
+#define PMIC_INT_TYPE_CON0_ADDR \
+ MT6389_INT_TYPE_CON0
+#define PMIC_INT_TYPE_CON0_MASK 0xFFFF
+#define PMIC_INT_TYPE_CON0_SHIFT 0
+#define PMIC_INT_TYPE_CON0_SET_ADDR \
+ MT6389_INT_TYPE_CON0_SET
+#define PMIC_INT_TYPE_CON0_SET_MASK 0xFFFF
+#define PMIC_INT_TYPE_CON0_SET_SHIFT 0
+#define PMIC_INT_TYPE_CON0_CLR_ADDR \
+ MT6389_INT_TYPE_CON0_CLR
+#define PMIC_INT_TYPE_CON0_CLR_MASK 0xFFFF
+#define PMIC_INT_TYPE_CON0_CLR_SHIFT 0
+#define PMIC_CPU_INT_STA_ADDR \
+ MT6389_INT_STA
+#define PMIC_CPU_INT_STA_MASK 0x1
+#define PMIC_CPU_INT_STA_SHIFT 0
+#define PMIC_MD32_INT_STA_ADDR \
+ MT6389_INT_STA
+#define PMIC_MD32_INT_STA_MASK 0x1
+#define PMIC_MD32_INT_STA_SHIFT 1
+#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_ADDR \
+ MT6389_RG_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_SHIFT 0
+#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_ADDR \
+ MT6389_RG_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_SHIFT 1
+#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_ADDR \
+ MT6389_RG_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_SHIFT 2
+#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_ADDR \
+ MT6389_RG_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_SHIFT 3
+#define PMIC_RG_SRCLKEN_IN2_EN_ADDR \
+ MT6389_TOP_SPI_CON0
+#define PMIC_RG_SRCLKEN_IN2_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN2_EN_SHIFT 0
+#define PMIC_RG_SRCLKEN_IN3_EN_ADDR \
+ MT6389_TOP_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN3_EN_MASK 0x1
+#define PMIC_RG_SRCLKEN_IN3_EN_SHIFT 0
+#define PMIC_SCK_TOP_ANA_ID_ADDR \
+ MT6389_SCK_TOP_DSN_ID
+#define PMIC_SCK_TOP_ANA_ID_MASK 0xFF
+#define PMIC_SCK_TOP_ANA_ID_SHIFT 0
+#define PMIC_SCK_TOP_DIG_ID_ADDR \
+ MT6389_SCK_TOP_DSN_ID
+#define PMIC_SCK_TOP_DIG_ID_MASK 0xFF
+#define PMIC_SCK_TOP_DIG_ID_SHIFT 8
+#define PMIC_SCK_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_SCK_TOP_DSN_REV0
+#define PMIC_SCK_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_SCK_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_SCK_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_SCK_TOP_DSN_REV0
+#define PMIC_SCK_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_SCK_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_SCK_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_SCK_TOP_DSN_REV0
+#define PMIC_SCK_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_SCK_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_SCK_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_SCK_TOP_DSN_REV0
+#define PMIC_SCK_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_SCK_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_SCK_TOP_CBS_ADDR \
+ MT6389_SCK_TOP_DBI
+#define PMIC_SCK_TOP_CBS_MASK 0x3
+#define PMIC_SCK_TOP_CBS_SHIFT 0
+#define PMIC_SCK_TOP_BIX_ADDR \
+ MT6389_SCK_TOP_DBI
+#define PMIC_SCK_TOP_BIX_MASK 0x3
+#define PMIC_SCK_TOP_BIX_SHIFT 2
+#define PMIC_SCK_TOP_ESP_ADDR \
+ MT6389_SCK_TOP_DBI
+#define PMIC_SCK_TOP_ESP_MASK 0xFF
+#define PMIC_SCK_TOP_ESP_SHIFT 8
+#define PMIC_SCK_TOP_FPI_ADDR \
+ MT6389_SCK_TOP_DXI
+#define PMIC_SCK_TOP_FPI_MASK 0xFF
+#define PMIC_SCK_TOP_FPI_SHIFT 0
+#define PMIC_SCK_TOP_CLK_OFFSET_ADDR \
+ MT6389_SCK_TOP_TPM0
+#define PMIC_SCK_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_SCK_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_SCK_TOP_RST_OFFSET_ADDR \
+ MT6389_SCK_TOP_TPM0
+#define PMIC_SCK_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_SCK_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_SCK_TOP_INT_OFFSET_ADDR \
+ MT6389_SCK_TOP_TPM1
+#define PMIC_SCK_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_SCK_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_SCK_TOP_INT_LEN_ADDR \
+ MT6389_SCK_TOP_TPM1
+#define PMIC_SCK_TOP_INT_LEN_MASK 0xFF
+#define PMIC_SCK_TOP_INT_LEN_SHIFT 8
+#define PMIC_SCK_TOP_XTAL_SEL_ADDR \
+ MT6389_SCK_TOP_CON0
+#define PMIC_SCK_TOP_XTAL_SEL_MASK 0x1
+#define PMIC_SCK_TOP_XTAL_SEL_SHIFT 0
+#define PMIC_SCK_TOP_RESERVED_ADDR \
+ MT6389_SCK_TOP_CON0
+#define PMIC_SCK_TOP_RESERVED_MASK 0x7FFF
+#define PMIC_SCK_TOP_RESERVED_SHIFT 1
+#define PMIC_XOSC32_ENB_DET_ADDR \
+ MT6389_SCK_TOP_CON1
+#define PMIC_XOSC32_ENB_DET_MASK 0x1
+#define PMIC_XOSC32_ENB_DET_SHIFT 0
+#define PMIC_SCK_TOP_TEST_OUT_ADDR \
+ MT6389_SCK_TOP_TEST_OUT
+#define PMIC_SCK_TOP_TEST_OUT_MASK 0xFF
+#define PMIC_SCK_TOP_TEST_OUT_SHIFT 0
+#define PMIC_SCK_TOP_MON_FLAG_SEL_ADDR \
+ MT6389_SCK_TOP_TEST_CON0
+#define PMIC_SCK_TOP_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_SCK_TOP_MON_FLAG_SEL_SHIFT 0
+#define PMIC_SCK_TOP_MON_GRP_SEL_ADDR \
+ MT6389_SCK_TOP_TEST_CON0
+#define PMIC_SCK_TOP_MON_GRP_SEL_MASK 0x3
+#define PMIC_SCK_TOP_MON_GRP_SEL_SHIFT 8
+#define PMIC_RG_RTC_SEC_MCLK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_SEC_MCLK_PDN_MASK 0x1
+#define PMIC_RG_RTC_SEC_MCLK_PDN_SHIFT 0
+#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_MASK 0x1
+#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_SHIFT 1
+#define PMIC_RG_RTC_EOSC32_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_EOSC32_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT 2
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_SHIFT 3
+#define PMIC_RG_RTC_MCLK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_MCLK_PDN_MASK 0x1
+#define PMIC_RG_RTC_MCLK_PDN_SHIFT 4
+#define PMIC_RG_RTC_32K_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC_32K_CK_PDN_SHIFT 5
+#define PMIC_RG_RTC_26M_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_26M_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC_26M_CK_PDN_SHIFT 6
+#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_MASK 0x1
+#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_SHIFT 7
+#define PMIC_RG_RTC_INTRP_CK_PDN_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0
+#define PMIC_RG_RTC_INTRP_CK_PDN_MASK 0x1
+#define PMIC_RG_RTC_INTRP_CK_PDN_SHIFT 8
+#define PMIC_SCK_TOP_CKPDN_CON0_SET_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0_SET
+#define PMIC_SCK_TOP_CKPDN_CON0_SET_MASK 0xFF
+#define PMIC_SCK_TOP_CKPDN_CON0_SET_SHIFT 0
+#define PMIC_SCK_TOP_CKPDN_CON0_CLR_ADDR \
+ MT6389_SCK_TOP_CKPDN_CON0_CLR
+#define PMIC_SCK_TOP_CKPDN_CON0_CLR_MASK 0xFF
+#define PMIC_SCK_TOP_CKPDN_CON0_CLR_SHIFT 0
+#define PMIC_RG_RTC_26M_CK_PDN_HWEN_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_26M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC_26M_CK_PDN_HWEN_SHIFT 0
+#define PMIC_RG_RTC_MCLK_PDN_HWEN_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_MCLK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC_MCLK_PDN_HWEN_SHIFT 1
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_SHIFT 2
+#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_SHIFT 3
+#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_SHIFT 4
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_MASK 0x1F
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_SHIFT 5
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_MASK 0x3F
+#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_SHIFT 10
+#define PMIC_SCK_TOP_CKHWEN_CON_SET_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0_SET
+#define PMIC_SCK_TOP_CKHWEN_CON_SET_MASK 0xFFFF
+#define PMIC_SCK_TOP_CKHWEN_CON_SET_SHIFT 0
+#define PMIC_SCK_TOP_CKHWEN_CON_CLR_ADDR \
+ MT6389_SCK_TOP_CKHWEN_CON0_CLR
+#define PMIC_SCK_TOP_CKHWEN_CON_CLR_MASK 0xFFFF
+#define PMIC_SCK_TOP_CKHWEN_CON_CLR_SHIFT 0
+#define PMIC_RG_RTC_CK_TSTSEL_RSV_ADDR \
+ MT6389_SCK_TOP_CKTST_CON
+#define PMIC_RG_RTC_CK_TSTSEL_RSV_MASK 0xF
+#define PMIC_RG_RTC_CK_TSTSEL_RSV_SHIFT 0
+#define PMIC_RG_RTCDET_CK_TSTSEL_ADDR \
+ MT6389_SCK_TOP_CKTST_CON
+#define PMIC_RG_RTCDET_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_RTCDET_CK_TSTSEL_SHIFT 4
+#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_ADDR \
+ MT6389_SCK_TOP_CKTST_CON
+#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT 5
+#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_ADDR \
+ MT6389_SCK_TOP_CKTST_CON
+#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_SHIFT 6
+#define PMIC_RG_RTC_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_RTC_SWRST_MASK 0x1
+#define PMIC_RG_RTC_SWRST_SHIFT 0
+#define PMIC_RG_RTC_SEC_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_RTC_SEC_SWRST_MASK 0x1
+#define PMIC_RG_RTC_SEC_SWRST_SHIFT 1
+#define PMIC_RG_BANK_RTC_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_BANK_RTC_SWRST_MASK 0x1
+#define PMIC_RG_BANK_RTC_SWRST_SHIFT 2
+#define PMIC_RG_BANK_RTC_SEC_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_BANK_RTC_SEC_SWRST_MASK 0x1
+#define PMIC_RG_BANK_RTC_SEC_SWRST_SHIFT 3
+#define PMIC_RG_BANK_EOSC_CALI_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_BANK_EOSC_CALI_SWRST_MASK 0x1
+#define PMIC_RG_BANK_EOSC_CALI_SWRST_SHIFT 4
+#define PMIC_RG_BANK_SCK_TOP_SWRST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_BANK_SCK_TOP_SWRST_MASK 0x1
+#define PMIC_RG_BANK_SCK_TOP_SWRST_SHIFT 5
+#define PMIC_RG_BANK_FQMTR_RST_ADDR \
+ MT6389_SCK_TOP_RST_CON0
+#define PMIC_RG_BANK_FQMTR_RST_MASK 0x1
+#define PMIC_RG_BANK_FQMTR_RST_SHIFT 6
+#define PMIC_SCK_TOP_RST_CON0_SET_ADDR \
+ MT6389_SCK_TOP_RST_CON0_SET
+#define PMIC_SCK_TOP_RST_CON0_SET_MASK 0x3F
+#define PMIC_SCK_TOP_RST_CON0_SET_SHIFT 0
+#define PMIC_SCK_TOP_RST_CON0_CLR_ADDR \
+ MT6389_SCK_TOP_RST_CON0_CLR
+#define PMIC_SCK_TOP_RST_CON0_CLR_MASK 0x3F
+#define PMIC_SCK_TOP_RST_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_EN_RTC_ADDR \
+ MT6389_SCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_RTC_MASK 0x1
+#define PMIC_RG_INT_EN_RTC_SHIFT 0
+#define PMIC_SCK_TOP_INT_CON0_SET_ADDR \
+ MT6389_SCK_TOP_INT_CON0_SET
+#define PMIC_SCK_TOP_INT_CON0_SET_MASK 0x1
+#define PMIC_SCK_TOP_INT_CON0_SET_SHIFT 0
+#define PMIC_SCK_TOP_INT_CON0_CLR_ADDR \
+ MT6389_SCK_TOP_INT_CON0_CLR
+#define PMIC_SCK_TOP_INT_CON0_CLR_MASK 0x1
+#define PMIC_SCK_TOP_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_RTC_ADDR \
+ MT6389_SCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_RTC_MASK 0x1
+#define PMIC_RG_INT_MASK_RTC_SHIFT 0
+#define PMIC_SCK_TOP_INT_MASK_CON0_SET_ADDR \
+ MT6389_SCK_TOP_INT_MASK_CON0_SET
+#define PMIC_SCK_TOP_INT_MASK_CON0_SET_MASK 0x1
+#define PMIC_SCK_TOP_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_ADDR \
+ MT6389_SCK_TOP_INT_MASK_CON0_CLR
+#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_MASK 0x1
+#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_RTC_ADDR \
+ MT6389_SCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_RTC_MASK 0x1
+#define PMIC_RG_INT_STATUS_RTC_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_RTC_ADDR \
+ MT6389_SCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_RTC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_RTC_SHIFT 0
+#define PMIC_SCK_TOP_POLARITY_ADDR \
+ MT6389_SCK_TOP_INT_MISC_CON
+#define PMIC_SCK_TOP_POLARITY_MASK 0x1
+#define PMIC_SCK_TOP_POLARITY_SHIFT 0
+#define PMIC_EOSC_CALI_START_ADDR \
+ MT6389_EOSC_CALI_CON0
+#define PMIC_EOSC_CALI_START_MASK 0x1
+#define PMIC_EOSC_CALI_START_SHIFT 0
+#define PMIC_EOSC_CALI_TD_ADDR \
+ MT6389_EOSC_CALI_CON0
+#define PMIC_EOSC_CALI_TD_MASK 0x7
+#define PMIC_EOSC_CALI_TD_SHIFT 5
+#define PMIC_EOSC_CALI_TEST_ADDR \
+ MT6389_EOSC_CALI_CON0
+#define PMIC_EOSC_CALI_TEST_MASK 0xF
+#define PMIC_EOSC_CALI_TEST_SHIFT 9
+#define PMIC_EOSC_CALI_DCXO_RDY_TD_ADDR \
+ MT6389_EOSC_CALI_CON1
+#define PMIC_EOSC_CALI_DCXO_RDY_TD_MASK 0x7
+#define PMIC_EOSC_CALI_DCXO_RDY_TD_SHIFT 0
+#define PMIC_FRC_VTCXO0_ON_ADDR \
+ MT6389_EOSC_CALI_CON1
+#define PMIC_FRC_VTCXO0_ON_MASK 0x1
+#define PMIC_FRC_VTCXO0_ON_SHIFT 8
+#define PMIC_EOSC_CALI_RSV_ADDR \
+ MT6389_EOSC_CALI_CON1
+#define PMIC_EOSC_CALI_RSV_MASK 0xF
+#define PMIC_EOSC_CALI_RSV_SHIFT 11
+#define PMIC_MIX_EOSC32_STP_LPDTB_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_EOSC32_STP_LPDTB_MASK 0x1
+#define PMIC_MIX_EOSC32_STP_LPDTB_SHIFT 1
+#define PMIC_MIX_EOSC32_STP_LPDEN_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_EOSC32_STP_LPDEN_MASK 0x1
+#define PMIC_MIX_EOSC32_STP_LPDEN_SHIFT 2
+#define PMIC_MIX_XOSC32_STP_PWDB_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_XOSC32_STP_PWDB_MASK 0x1
+#define PMIC_MIX_XOSC32_STP_PWDB_SHIFT 3
+#define PMIC_MIX_XOSC32_STP_LPDTB_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_XOSC32_STP_LPDTB_MASK 0x1
+#define PMIC_MIX_XOSC32_STP_LPDTB_SHIFT 4
+#define PMIC_MIX_XOSC32_STP_LPDEN_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_XOSC32_STP_LPDEN_MASK 0x1
+#define PMIC_MIX_XOSC32_STP_LPDEN_SHIFT 5
+#define PMIC_MIX_XOSC32_STP_LPDRST_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_XOSC32_STP_LPDRST_MASK 0x1
+#define PMIC_MIX_XOSC32_STP_LPDRST_SHIFT 6
+#define PMIC_MIX_XOSC32_STP_CALI_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_MIX_XOSC32_STP_CALI_MASK 0x1F
+#define PMIC_MIX_XOSC32_STP_CALI_SHIFT 7
+#define PMIC_STMP_MODE_ADDR \
+ MT6389_RTC_MIX_CON0
+#define PMIC_STMP_MODE_MASK 0x1
+#define PMIC_STMP_MODE_SHIFT 12
+#define PMIC_MIX_EOSC32_STP_CHOP_EN_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_EOSC32_STP_CHOP_EN_MASK 0x1
+#define PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT 0
+#define PMIC_MIX_DCXO_STP_LVSH_EN_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_DCXO_STP_LVSH_EN_MASK 0x1
+#define PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT 1
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT 2
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1
+#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
+#define PMIC_MIX_RTC_STP_XOSC32_ENB_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_RTC_STP_XOSC32_ENB_MASK 0x1
+#define PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT 4
+#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
+#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5
+#define PMIC_MIX_EOSC32_STP_RSV_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_EOSC32_STP_RSV_MASK 0x3
+#define PMIC_MIX_EOSC32_STP_RSV_SHIFT 6
+#define PMIC_MIX_EOSC32_VCT_EN_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_EOSC32_VCT_EN_MASK 0x1
+#define PMIC_MIX_EOSC32_VCT_EN_SHIFT 8
+#define PMIC_MIX_EOSC32_OPT_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_EOSC32_OPT_MASK 0x3
+#define PMIC_MIX_EOSC32_OPT_SHIFT 9
+#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_MASK 0x1
+#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_SHIFT 11
+#define PMIC_MIX_RTC_GPIO_COREDETB_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_RTC_GPIO_COREDETB_MASK 0x1
+#define PMIC_MIX_RTC_GPIO_COREDETB_SHIFT 12
+#define PMIC_MIX_RTC_GPIO_F32KOB_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_RTC_GPIO_F32KOB_MASK 0x1
+#define PMIC_MIX_RTC_GPIO_F32KOB_SHIFT 13
+#define PMIC_MIX_RTC_GPIO_GPO_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_RTC_GPIO_GPO_MASK 0x1
+#define PMIC_MIX_RTC_GPIO_GPO_SHIFT 14
+#define PMIC_MIX_RTC_GPIO_OE_ADDR \
+ MT6389_RTC_MIX_CON1
+#define PMIC_MIX_RTC_GPIO_OE_MASK 0x1
+#define PMIC_MIX_RTC_GPIO_OE_SHIFT 15
+#define PMIC_MIX_RTC_STP_DEBUG_OUT_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_RTC_STP_DEBUG_OUT_MASK 0x3
+#define PMIC_MIX_RTC_STP_DEBUG_OUT_SHIFT 0
+#define PMIC_MIX_RTC_STP_DEBUG_SEL_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_RTC_STP_DEBUG_SEL_MASK 0x3
+#define PMIC_MIX_RTC_STP_DEBUG_SEL_SHIFT 4
+#define PMIC_MIX_RTC_STP_K_EOSC32_EN_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_RTC_STP_K_EOSC32_EN_MASK 0x1
+#define PMIC_MIX_RTC_STP_K_EOSC32_EN_SHIFT 7
+#define PMIC_MIX_RTC_STP_EMBCK_SEL_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_RTC_STP_EMBCK_SEL_MASK 0x1
+#define PMIC_MIX_RTC_STP_EMBCK_SEL_SHIFT 8
+#define PMIC_MIX_STP_BBWAKEUP_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_STP_BBWAKEUP_MASK 0x1
+#define PMIC_MIX_STP_BBWAKEUP_SHIFT 9
+#define PMIC_MIX_STP_RTC_DDLO_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_STP_RTC_DDLO_MASK 0x1
+#define PMIC_MIX_STP_RTC_DDLO_SHIFT 10
+#define PMIC_MIX_RTC_XOSC32_ENB_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_RTC_XOSC32_ENB_MASK 0x1
+#define PMIC_MIX_RTC_XOSC32_ENB_SHIFT 11
+#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_ADDR \
+ MT6389_RTC_MIX_CON2
+#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK 0x1
+#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12
+#define PMIC_RG_RTC_TEST_OUT_ADDR \
+ MT6389_RTC_DIG_CON0
+#define PMIC_RG_RTC_TEST_OUT_MASK 0x3
+#define PMIC_RG_RTC_TEST_OUT_SHIFT 0
+#define PMIC_RG_RTC_DIG_TEST_IN_ADDR \
+ MT6389_RTC_DIG_CON0
+#define PMIC_RG_RTC_DIG_TEST_IN_MASK 0x1
+#define PMIC_RG_RTC_DIG_TEST_IN_SHIFT 3
+#define PMIC_RG_RTC_DIG_TEST_MODE_ADDR \
+ MT6389_RTC_DIG_CON0
+#define PMIC_RG_RTC_DIG_TEST_MODE_MASK 0x1
+#define PMIC_RG_RTC_DIG_TEST_MODE_SHIFT 15
+#define PMIC_FQMTR_TCKSEL_ADDR \
+ MT6389_FQMTR_CON0
+#define PMIC_FQMTR_TCKSEL_MASK 0x7
+#define PMIC_FQMTR_TCKSEL_SHIFT 0
+#define PMIC_FQMTR_BUSY_ADDR \
+ MT6389_FQMTR_CON0
+#define PMIC_FQMTR_BUSY_MASK 0x1
+#define PMIC_FQMTR_BUSY_SHIFT 3
+#define PMIC_FQMTR_DCXO26M_EN_ADDR \
+ MT6389_FQMTR_CON0
+#define PMIC_FQMTR_DCXO26M_EN_MASK 0x1
+#define PMIC_FQMTR_DCXO26M_EN_SHIFT 4
+#define PMIC_FQMTR_EN_ADDR \
+ MT6389_FQMTR_CON0
+#define PMIC_FQMTR_EN_MASK 0x1
+#define PMIC_FQMTR_EN_SHIFT 15
+#define PMIC_FQMTR_WINSET_ADDR \
+ MT6389_FQMTR_CON1
+#define PMIC_FQMTR_WINSET_MASK 0xFFFF
+#define PMIC_FQMTR_WINSET_SHIFT 0
+#define PMIC_FQMTR_DATA_ADDR \
+ MT6389_FQMTR_CON2
+#define PMIC_FQMTR_DATA_MASK 0xFFFF
+#define PMIC_FQMTR_DATA_SHIFT 0
+#define PMIC_XO_SOC_VOTE_ADDR \
+ MT6389_XO_BUF_CTL0
+#define PMIC_XO_SOC_VOTE_MASK 0x7FF
+#define PMIC_XO_SOC_VOTE_SHIFT 0
+#define PMIC_XO_WCN_VOTE_ADDR \
+ MT6389_XO_BUF_CTL1
+#define PMIC_XO_WCN_VOTE_MASK 0x7FF
+#define PMIC_XO_WCN_VOTE_SHIFT 0
+#define PMIC_XO_NFC_VOTE_ADDR \
+ MT6389_XO_BUF_CTL2
+#define PMIC_XO_NFC_VOTE_MASK 0x7FF
+#define PMIC_XO_NFC_VOTE_SHIFT 0
+#define PMIC_XO_CEL_VOTE_ADDR \
+ MT6389_XO_BUF_CTL3
+#define PMIC_XO_CEL_VOTE_MASK 0x7FF
+#define PMIC_XO_CEL_VOTE_SHIFT 0
+#define PMIC_XO_EXT_VOTE_ADDR \
+ MT6389_XO_BUF_CTL4
+#define PMIC_XO_EXT_VOTE_MASK 0x7FF
+#define PMIC_XO_EXT_VOTE_SHIFT 0
+#define PMIC_XO_MODE_CONN_BT_MASK_ADDR \
+ MT6389_XO_CONN_BT0
+#define PMIC_XO_MODE_CONN_BT_MASK_MASK 0x1
+#define PMIC_XO_MODE_CONN_BT_MASK_SHIFT 0
+#define PMIC_XO_BUF_CONN_BT_MASK_ADDR \
+ MT6389_XO_CONN_BT0
+#define PMIC_XO_BUF_CONN_BT_MASK_MASK 0x1
+#define PMIC_XO_BUF_CONN_BT_MASK_SHIFT 1
+#define PMIC_RTC_ANA_ID_ADDR \
+ MT6389_RTC_DSN_ID
+#define PMIC_RTC_ANA_ID_MASK 0xFF
+#define PMIC_RTC_ANA_ID_SHIFT 0
+#define PMIC_RTC_DIG_ID_ADDR \
+ MT6389_RTC_DSN_ID
+#define PMIC_RTC_DIG_ID_MASK 0xFF
+#define PMIC_RTC_DIG_ID_SHIFT 8
+#define PMIC_RTC_ANA_MINOR_REV_ADDR \
+ MT6389_RTC_DSN_REV0
+#define PMIC_RTC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_RTC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_RTC_ANA_MAJOR_REV_ADDR \
+ MT6389_RTC_DSN_REV0
+#define PMIC_RTC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_RTC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_RTC_DIG_MINOR_REV_ADDR \
+ MT6389_RTC_DSN_REV0
+#define PMIC_RTC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_RTC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_RTC_DIG_MAJOR_REV_ADDR \
+ MT6389_RTC_DSN_REV0
+#define PMIC_RTC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_RTC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_RTC_DSN_CBS_ADDR \
+ MT6389_RTC_DBI
+#define PMIC_RTC_DSN_CBS_MASK 0x3
+#define PMIC_RTC_DSN_CBS_SHIFT 0
+#define PMIC_RTC_DSN_BIX_ADDR \
+ MT6389_RTC_DBI
+#define PMIC_RTC_DSN_BIX_MASK 0x3
+#define PMIC_RTC_DSN_BIX_SHIFT 2
+#define PMIC_RTC_DSN_ESP_ADDR \
+ MT6389_RTC_DBI
+#define PMIC_RTC_DSN_ESP_MASK 0xFF
+#define PMIC_RTC_DSN_ESP_SHIFT 8
+#define PMIC_RTC_DSN_FPI_ADDR \
+ MT6389_RTC_DXI
+#define PMIC_RTC_DSN_FPI_MASK 0xFF
+#define PMIC_RTC_DSN_FPI_SHIFT 0
+#define PMIC_BBPU_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_BBPU_MASK 0xF
+#define PMIC_BBPU_SHIFT 0
+#define PMIC_CLRPKY_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_CLRPKY_MASK 0x1
+#define PMIC_CLRPKY_SHIFT 4
+#define PMIC_RELOAD_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_RELOAD_MASK 0x1
+#define PMIC_RELOAD_SHIFT 5
+#define PMIC_CBUSY_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_CBUSY_MASK 0x1
+#define PMIC_CBUSY_SHIFT 6
+#define PMIC_ALARM_STATUS_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_ALARM_STATUS_MASK 0x1
+#define PMIC_ALARM_STATUS_SHIFT 7
+#define PMIC_KEY_BBPU_ADDR \
+ MT6389_RTC_BBPU
+#define PMIC_KEY_BBPU_MASK 0xFF
+#define PMIC_KEY_BBPU_SHIFT 8
+#define PMIC_ALSTA_ADDR \
+ MT6389_RTC_IRQ_STA
+#define PMIC_ALSTA_MASK 0x1
+#define PMIC_ALSTA_SHIFT 0
+#define PMIC_TCSTA_ADDR \
+ MT6389_RTC_IRQ_STA
+#define PMIC_TCSTA_MASK 0x1
+#define PMIC_TCSTA_SHIFT 1
+#define PMIC_LPSTA_ADDR \
+ MT6389_RTC_IRQ_STA
+#define PMIC_LPSTA_MASK 0x1
+#define PMIC_LPSTA_SHIFT 3
+#define PMIC_AL_EN_ADDR \
+ MT6389_RTC_IRQ_EN
+#define PMIC_AL_EN_MASK 0x1
+#define PMIC_AL_EN_SHIFT 0
+#define PMIC_TC_EN_ADDR \
+ MT6389_RTC_IRQ_EN
+#define PMIC_TC_EN_MASK 0x1
+#define PMIC_TC_EN_SHIFT 1
+#define PMIC_ONESHOT_ADDR \
+ MT6389_RTC_IRQ_EN
+#define PMIC_ONESHOT_MASK 0x1
+#define PMIC_ONESHOT_SHIFT 2
+#define PMIC_LP_EN_ADDR \
+ MT6389_RTC_IRQ_EN
+#define PMIC_LP_EN_MASK 0x1
+#define PMIC_LP_EN_SHIFT 3
+#define PMIC_SECCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_SECCII_MASK 0x1
+#define PMIC_SECCII_SHIFT 0
+#define PMIC_MINCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_MINCII_MASK 0x1
+#define PMIC_MINCII_SHIFT 1
+#define PMIC_HOUCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_HOUCII_MASK 0x1
+#define PMIC_HOUCII_SHIFT 2
+#define PMIC_DOMCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_DOMCII_MASK 0x1
+#define PMIC_DOMCII_SHIFT 3
+#define PMIC_DOWCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_DOWCII_MASK 0x1
+#define PMIC_DOWCII_SHIFT 4
+#define PMIC_MTHCII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_MTHCII_MASK 0x1
+#define PMIC_MTHCII_SHIFT 5
+#define PMIC_YEACII_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_YEACII_MASK 0x1
+#define PMIC_YEACII_SHIFT 6
+#define PMIC_SECCII_1_2_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_SECCII_1_2_MASK 0x1
+#define PMIC_SECCII_1_2_SHIFT 7
+#define PMIC_SECCII_1_4_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_SECCII_1_4_MASK 0x1
+#define PMIC_SECCII_1_4_SHIFT 8
+#define PMIC_SECCII_1_8_ADDR \
+ MT6389_RTC_CII_EN
+#define PMIC_SECCII_1_8_MASK 0x1
+#define PMIC_SECCII_1_8_SHIFT 9
+#define PMIC_SEC_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_SEC_MSK_MASK 0x1
+#define PMIC_SEC_MSK_SHIFT 0
+#define PMIC_MIN_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_MIN_MSK_MASK 0x1
+#define PMIC_MIN_MSK_SHIFT 1
+#define PMIC_HOU_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_HOU_MSK_MASK 0x1
+#define PMIC_HOU_MSK_SHIFT 2
+#define PMIC_DOM_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_DOM_MSK_MASK 0x1
+#define PMIC_DOM_MSK_SHIFT 3
+#define PMIC_DOW_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_DOW_MSK_MASK 0x1
+#define PMIC_DOW_MSK_SHIFT 4
+#define PMIC_MTH_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_MTH_MSK_MASK 0x1
+#define PMIC_MTH_MSK_SHIFT 5
+#define PMIC_YEA_MSK_ADDR \
+ MT6389_RTC_AL_MASK
+#define PMIC_YEA_MSK_MASK 0x1
+#define PMIC_YEA_MSK_SHIFT 6
+#define PMIC_TC_SECOND_ADDR \
+ MT6389_RTC_TC_SEC
+#define PMIC_TC_SECOND_MASK 0x3F
+#define PMIC_TC_SECOND_SHIFT 0
+#define PMIC_TC_MINUTE_ADDR \
+ MT6389_RTC_TC_MIN
+#define PMIC_TC_MINUTE_MASK 0x3F
+#define PMIC_TC_MINUTE_SHIFT 0
+#define PMIC_TC_HOUR_ADDR \
+ MT6389_RTC_TC_HOU
+#define PMIC_TC_HOUR_MASK 0x1F
+#define PMIC_TC_HOUR_SHIFT 0
+#define PMIC_TC_DOM_ADDR \
+ MT6389_RTC_TC_DOM
+#define PMIC_TC_DOM_MASK 0x1F
+#define PMIC_TC_DOM_SHIFT 0
+#define PMIC_TC_DOW_ADDR \
+ MT6389_RTC_TC_DOW
+#define PMIC_TC_DOW_MASK 0x7
+#define PMIC_TC_DOW_SHIFT 0
+#define PMIC_TC_MONTH_ADDR \
+ MT6389_RTC_TC_MTH
+#define PMIC_TC_MONTH_MASK 0xF
+#define PMIC_TC_MONTH_SHIFT 0
+#define PMIC_RTC_MACRO_ID_ADDR \
+ MT6389_RTC_TC_MTH
+#define PMIC_RTC_MACRO_ID_MASK 0xFFF
+#define PMIC_RTC_MACRO_ID_SHIFT 4
+#define PMIC_TC_YEAR_ADDR \
+ MT6389_RTC_TC_YEA
+#define PMIC_TC_YEAR_MASK 0x7F
+#define PMIC_TC_YEAR_SHIFT 0
+#define PMIC_AL_SECOND_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_AL_SECOND_MASK 0x3F
+#define PMIC_AL_SECOND_SHIFT 0
+#define PMIC_BBPU_AUTO_PDN_SEL_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_AUTO_PDN_SEL_MASK 0x1
+#define PMIC_BBPU_AUTO_PDN_SEL_SHIFT 6
+#define PMIC_BBPU_2SEC_CK_SEL_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_2SEC_CK_SEL_MASK 0x1
+#define PMIC_BBPU_2SEC_CK_SEL_SHIFT 7
+#define PMIC_BBPU_2SEC_EN_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_2SEC_EN_MASK 0x1
+#define PMIC_BBPU_2SEC_EN_SHIFT 8
+#define PMIC_BBPU_2SEC_MODE_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_2SEC_MODE_MASK 0x3
+#define PMIC_BBPU_2SEC_MODE_SHIFT 9
+#define PMIC_BBPU_2SEC_STAT_CLEAR_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_2SEC_STAT_CLEAR_MASK 0x1
+#define PMIC_BBPU_2SEC_STAT_CLEAR_SHIFT 11
+#define PMIC_BBPU_2SEC_STAT_STA_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_BBPU_2SEC_STAT_STA_MASK 0x1
+#define PMIC_BBPU_2SEC_STAT_STA_SHIFT 12
+#define PMIC_RTC_LPD_OPT_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_RTC_LPD_OPT_MASK 0x3
+#define PMIC_RTC_LPD_OPT_SHIFT 13
+#define PMIC_K_EOSC32_VTCXO_ON_SEL_ADDR \
+ MT6389_RTC_AL_SEC
+#define PMIC_K_EOSC32_VTCXO_ON_SEL_MASK 0x1
+#define PMIC_K_EOSC32_VTCXO_ON_SEL_SHIFT 15
+#define PMIC_AL_MINUTE_ADDR \
+ MT6389_RTC_AL_MIN
+#define PMIC_AL_MINUTE_MASK 0x3F
+#define PMIC_AL_MINUTE_SHIFT 0
+#define PMIC_AL_HOUR_ADDR \
+ MT6389_RTC_AL_HOU
+#define PMIC_AL_HOUR_MASK 0x1F
+#define PMIC_AL_HOUR_SHIFT 0
+#define PMIC_NEW_SPARE0_ADDR \
+ MT6389_RTC_AL_HOU
+#define PMIC_NEW_SPARE0_MASK 0xFF
+#define PMIC_NEW_SPARE0_SHIFT 8
+#define PMIC_AL_DOM_ADDR \
+ MT6389_RTC_AL_DOM
+#define PMIC_AL_DOM_MASK 0x1F
+#define PMIC_AL_DOM_SHIFT 0
+#define PMIC_NEW_SPARE1_ADDR \
+ MT6389_RTC_AL_DOM
+#define PMIC_NEW_SPARE1_MASK 0xFF
+#define PMIC_NEW_SPARE1_SHIFT 8
+#define PMIC_AL_DOW_ADDR \
+ MT6389_RTC_AL_DOW
+#define PMIC_AL_DOW_MASK 0x7
+#define PMIC_AL_DOW_SHIFT 0
+#define PMIC_RG_EOSC_CALI_TD_ADDR \
+ MT6389_RTC_AL_DOW
+#define PMIC_RG_EOSC_CALI_TD_MASK 0x7
+#define PMIC_RG_EOSC_CALI_TD_SHIFT 5
+#define PMIC_NEW_SPARE2_ADDR \
+ MT6389_RTC_AL_DOW
+#define PMIC_NEW_SPARE2_MASK 0xFF
+#define PMIC_NEW_SPARE2_SHIFT 8
+#define PMIC_AL_MONTH_ADDR \
+ MT6389_RTC_AL_MTH
+#define PMIC_AL_MONTH_MASK 0xF
+#define PMIC_AL_MONTH_SHIFT 0
+#define PMIC_NEW_SPARE3_ADDR \
+ MT6389_RTC_AL_MTH
+#define PMIC_NEW_SPARE3_MASK 0xFF
+#define PMIC_NEW_SPARE3_SHIFT 8
+#define PMIC_AL_YEAR_ADDR \
+ MT6389_RTC_AL_YEA
+#define PMIC_AL_YEAR_MASK 0x7F
+#define PMIC_AL_YEAR_SHIFT 0
+#define PMIC_RTC_K_EOSC_RSV_ADDR \
+ MT6389_RTC_AL_YEA
+#define PMIC_RTC_K_EOSC_RSV_MASK 0xFF
+#define PMIC_RTC_K_EOSC_RSV_SHIFT 8
+#define PMIC_XOSCCALI_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_XOSCCALI_MASK 0x1F
+#define PMIC_XOSCCALI_SHIFT 0
+#define PMIC_RTC_XOSC32_ENB_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_XOSC32_ENB_MASK 0x1
+#define PMIC_RTC_XOSC32_ENB_SHIFT 5
+#define PMIC_RTC_EMBCK_SEL_MODE_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_EMBCK_SEL_MODE_MASK 0x3
+#define PMIC_RTC_EMBCK_SEL_MODE_SHIFT 6
+#define PMIC_RTC_EMBCK_SRC_SEL_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_EMBCK_SRC_SEL_MASK 0x1
+#define PMIC_RTC_EMBCK_SRC_SEL_SHIFT 8
+#define PMIC_RTC_EMBCK_SEL_OPTION_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_EMBCK_SEL_OPTION_MASK 0x1
+#define PMIC_RTC_EMBCK_SEL_OPTION_SHIFT 9
+#define PMIC_RTC_GPS_CKOUT_EN_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_GPS_CKOUT_EN_MASK 0x1
+#define PMIC_RTC_GPS_CKOUT_EN_SHIFT 10
+#define PMIC_RTC_EOSC32_VCT_EN_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_EOSC32_VCT_EN_MASK 0x1
+#define PMIC_RTC_EOSC32_VCT_EN_SHIFT 11
+#define PMIC_RTC_EOSC32_CHOP_EN_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_EOSC32_CHOP_EN_MASK 0x1
+#define PMIC_RTC_EOSC32_CHOP_EN_SHIFT 12
+#define PMIC_RTC_GP_OSC32_CON_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_GP_OSC32_CON_MASK 0x3
+#define PMIC_RTC_GP_OSC32_CON_SHIFT 13
+#define PMIC_RTC_REG_XOSC32_ENB_ADDR \
+ MT6389_RTC_OSC32CON
+#define PMIC_RTC_REG_XOSC32_ENB_MASK 0x1
+#define PMIC_RTC_REG_XOSC32_ENB_SHIFT 15
+#define PMIC_RTC_POWERKEY1_ADDR \
+ MT6389_RTC_POWERKEY1
+#define PMIC_RTC_POWERKEY1_MASK 0xFFFF
+#define PMIC_RTC_POWERKEY1_SHIFT 0
+#define PMIC_RTC_POWERKEY2_ADDR \
+ MT6389_RTC_POWERKEY2
+#define PMIC_RTC_POWERKEY2_MASK 0xFFFF
+#define PMIC_RTC_POWERKEY2_SHIFT 0
+#define PMIC_RTC_PDN1_ADDR \
+ MT6389_RTC_PDN1
+#define PMIC_RTC_PDN1_MASK 0xFFFF
+#define PMIC_RTC_PDN1_SHIFT 0
+#define PMIC_RTC_PDN2_ADDR \
+ MT6389_RTC_PDN2
+#define PMIC_RTC_PDN2_MASK 0xFFFF
+#define PMIC_RTC_PDN2_SHIFT 0
+#define PMIC_RTC_SPAR0_ADDR \
+ MT6389_RTC_SPAR0
+#define PMIC_RTC_SPAR0_MASK 0xFFFF
+#define PMIC_RTC_SPAR0_SHIFT 0
+#define PMIC_RTC_SPAR1_ADDR \
+ MT6389_RTC_SPAR1
+#define PMIC_RTC_SPAR1_MASK 0xFFFF
+#define PMIC_RTC_SPAR1_SHIFT 0
+#define PMIC_RTC_PROT_ADDR \
+ MT6389_RTC_PROT
+#define PMIC_RTC_PROT_MASK 0xFFFF
+#define PMIC_RTC_PROT_SHIFT 0
+#define PMIC_RTC_DIFF_ADDR \
+ MT6389_RTC_DIFF
+#define PMIC_RTC_DIFF_MASK 0xFFF
+#define PMIC_RTC_DIFF_SHIFT 0
+#define PMIC_POWER_DETECTED_ADDR \
+ MT6389_RTC_DIFF
+#define PMIC_POWER_DETECTED_MASK 0x1
+#define PMIC_POWER_DETECTED_SHIFT 12
+#define PMIC_K_EOSC32_RSV_ADDR \
+ MT6389_RTC_DIFF
+#define PMIC_K_EOSC32_RSV_MASK 0x1
+#define PMIC_K_EOSC32_RSV_SHIFT 14
+#define PMIC_CALI_RD_SEL_ADDR \
+ MT6389_RTC_DIFF
+#define PMIC_CALI_RD_SEL_MASK 0x1
+#define PMIC_CALI_RD_SEL_SHIFT 15
+#define PMIC_RTC_CALI_ADDR \
+ MT6389_RTC_CALI
+#define PMIC_RTC_CALI_MASK 0x3FFF
+#define PMIC_RTC_CALI_SHIFT 0
+#define PMIC_CALI_WR_SEL_ADDR \
+ MT6389_RTC_CALI
+#define PMIC_CALI_WR_SEL_MASK 0x1
+#define PMIC_CALI_WR_SEL_SHIFT 14
+#define PMIC_K_EOSC32_OVERFLOW_ADDR \
+ MT6389_RTC_CALI
+#define PMIC_K_EOSC32_OVERFLOW_MASK 0x1
+#define PMIC_K_EOSC32_OVERFLOW_SHIFT 15
+#define PMIC_WRTGR_ADDR \
+ MT6389_RTC_WRTGR
+#define PMIC_WRTGR_MASK 0x1
+#define PMIC_WRTGR_SHIFT 0
+#define PMIC_VBAT_LPSTA_RAW_ADDR \
+ MT6389_RTC_CON
+#define PMIC_VBAT_LPSTA_RAW_MASK 0x1
+#define PMIC_VBAT_LPSTA_RAW_SHIFT 0
+#define PMIC_EOSC32_LPEN_ADDR \
+ MT6389_RTC_CON
+#define PMIC_EOSC32_LPEN_MASK 0x1
+#define PMIC_EOSC32_LPEN_SHIFT 1
+#define PMIC_XOSC32_LPEN_ADDR \
+ MT6389_RTC_CON
+#define PMIC_XOSC32_LPEN_MASK 0x1
+#define PMIC_XOSC32_LPEN_SHIFT 2
+#define PMIC_LPRST_ADDR \
+ MT6389_RTC_CON
+#define PMIC_LPRST_MASK 0x1
+#define PMIC_LPRST_SHIFT 3
+#define PMIC_CDBO_ADDR \
+ MT6389_RTC_CON
+#define PMIC_CDBO_MASK 0x1
+#define PMIC_CDBO_SHIFT 4
+#define PMIC_F32KOB_ADDR \
+ MT6389_RTC_CON
+#define PMIC_F32KOB_MASK 0x1
+#define PMIC_F32KOB_SHIFT 5
+#define PMIC_GPO_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GPO_MASK 0x1
+#define PMIC_GPO_SHIFT 6
+#define PMIC_GOE_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GOE_MASK 0x1
+#define PMIC_GOE_SHIFT 7
+#define PMIC_GSR_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GSR_MASK 0x1
+#define PMIC_GSR_SHIFT 8
+#define PMIC_GSMT_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GSMT_MASK 0x1
+#define PMIC_GSMT_SHIFT 9
+#define PMIC_GPEN_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GPEN_MASK 0x1
+#define PMIC_GPEN_SHIFT 10
+#define PMIC_GPU_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GPU_MASK 0x1
+#define PMIC_GPU_SHIFT 11
+#define PMIC_GE4_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GE4_MASK 0x1
+#define PMIC_GE4_SHIFT 12
+#define PMIC_GE8_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GE8_MASK 0x1
+#define PMIC_GE8_SHIFT 13
+#define PMIC_GPI_ADDR \
+ MT6389_RTC_CON
+#define PMIC_GPI_MASK 0x1
+#define PMIC_GPI_SHIFT 14
+#define PMIC_LPSTA_RAW_ADDR \
+ MT6389_RTC_CON
+#define PMIC_LPSTA_RAW_MASK 0x1
+#define PMIC_LPSTA_RAW_SHIFT 15
+#define PMIC_DAT0_LOCK_ADDR \
+ MT6389_RTC_SEC_CTRL
+#define PMIC_DAT0_LOCK_MASK 0x1
+#define PMIC_DAT0_LOCK_SHIFT 0
+#define PMIC_DAT1_LOCK_ADDR \
+ MT6389_RTC_SEC_CTRL
+#define PMIC_DAT1_LOCK_MASK 0x1
+#define PMIC_DAT1_LOCK_SHIFT 1
+#define PMIC_DAT2_LOCK_ADDR \
+ MT6389_RTC_SEC_CTRL
+#define PMIC_DAT2_LOCK_MASK 0x1
+#define PMIC_DAT2_LOCK_SHIFT 2
+#define PMIC_RTC_INT_CNT_ADDR \
+ MT6389_RTC_INT_CNT
+#define PMIC_RTC_INT_CNT_MASK 0x7FFF
+#define PMIC_RTC_INT_CNT_SHIFT 0
+#define PMIC_RTC_SEC_DAT0_ADDR \
+ MT6389_RTC_SEC_DAT0
+#define PMIC_RTC_SEC_DAT0_MASK 0xFFFF
+#define PMIC_RTC_SEC_DAT0_SHIFT 0
+#define PMIC_RTC_SEC_DAT1_ADDR \
+ MT6389_RTC_SEC_DAT1
+#define PMIC_RTC_SEC_DAT1_MASK 0xFFFF
+#define PMIC_RTC_SEC_DAT1_SHIFT 0
+#define PMIC_RTC_SEC_DAT2_ADDR \
+ MT6389_RTC_SEC_DAT2
+#define PMIC_RTC_SEC_DAT2_MASK 0xFFFF
+#define PMIC_RTC_SEC_DAT2_SHIFT 0
+#define PMIC_RTC_SEC_ANA_ID_ADDR \
+ MT6389_RTC_SEC_DSN_ID
+#define PMIC_RTC_SEC_ANA_ID_MASK 0xFF
+#define PMIC_RTC_SEC_ANA_ID_SHIFT 0
+#define PMIC_RTC_SEC_DIG_ID_ADDR \
+ MT6389_RTC_SEC_DSN_ID
+#define PMIC_RTC_SEC_DIG_ID_MASK 0xFF
+#define PMIC_RTC_SEC_DIG_ID_SHIFT 8
+#define PMIC_RTC_SEC_ANA_MINOR_REV_ADDR \
+ MT6389_RTC_SEC_DSN_REV0
+#define PMIC_RTC_SEC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_RTC_SEC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_RTC_SEC_ANA_MAJOR_REV_ADDR \
+ MT6389_RTC_SEC_DSN_REV0
+#define PMIC_RTC_SEC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_RTC_SEC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_RTC_SEC_DIG_MINOR_REV_ADDR \
+ MT6389_RTC_SEC_DSN_REV0
+#define PMIC_RTC_SEC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_RTC_SEC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_RTC_SEC_DIG_MAJOR_REV_ADDR \
+ MT6389_RTC_SEC_DSN_REV0
+#define PMIC_RTC_SEC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_RTC_SEC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_RTC_SEC_DSN_CBS_ADDR \
+ MT6389_RTC_SEC_DBI
+#define PMIC_RTC_SEC_DSN_CBS_MASK 0x3
+#define PMIC_RTC_SEC_DSN_CBS_SHIFT 0
+#define PMIC_RTC_SEC_DSN_BIX_ADDR \
+ MT6389_RTC_SEC_DBI
+#define PMIC_RTC_SEC_DSN_BIX_MASK 0x3
+#define PMIC_RTC_SEC_DSN_BIX_SHIFT 2
+#define PMIC_RTC_SEC_DSN_ESP_ADDR \
+ MT6389_RTC_SEC_DBI
+#define PMIC_RTC_SEC_DSN_ESP_MASK 0xFF
+#define PMIC_RTC_SEC_DSN_ESP_SHIFT 8
+#define PMIC_RTC_SEC_DSN_FPI_ADDR \
+ MT6389_RTC_SEC_DXI
+#define PMIC_RTC_SEC_DSN_FPI_MASK 0xFF
+#define PMIC_RTC_SEC_DSN_FPI_SHIFT 0
+#define PMIC_TC_SECOND_SEC_ADDR \
+ MT6389_RTC_TC_SEC_SEC
+#define PMIC_TC_SECOND_SEC_MASK 0x3F
+#define PMIC_TC_SECOND_SEC_SHIFT 0
+#define PMIC_TC_MINUTE_SEC_ADDR \
+ MT6389_RTC_TC_MIN_SEC
+#define PMIC_TC_MINUTE_SEC_MASK 0x3F
+#define PMIC_TC_MINUTE_SEC_SHIFT 0
+#define PMIC_TC_HOUR_SEC_ADDR \
+ MT6389_RTC_TC_HOU_SEC
+#define PMIC_TC_HOUR_SEC_MASK 0x1F
+#define PMIC_TC_HOUR_SEC_SHIFT 0
+#define PMIC_TC_DOM_SEC_ADDR \
+ MT6389_RTC_TC_DOM_SEC
+#define PMIC_TC_DOM_SEC_MASK 0x1F
+#define PMIC_TC_DOM_SEC_SHIFT 0
+#define PMIC_TC_DOW_SEC_ADDR \
+ MT6389_RTC_TC_DOW_SEC
+#define PMIC_TC_DOW_SEC_MASK 0x7
+#define PMIC_TC_DOW_SEC_SHIFT 0
+#define PMIC_TC_MONTH_SEC_ADDR \
+ MT6389_RTC_TC_MTH_SEC
+#define PMIC_TC_MONTH_SEC_MASK 0xF
+#define PMIC_TC_MONTH_SEC_SHIFT 0
+#define PMIC_TC_YEAR_SEC_ADDR \
+ MT6389_RTC_TC_YEA_SEC
+#define PMIC_TC_YEAR_SEC_MASK 0x7F
+#define PMIC_TC_YEAR_SEC_SHIFT 0
+#define PMIC_RTC_SEC_CK_PDN_ADDR \
+ MT6389_RTC_SEC_CK_PDN
+#define PMIC_RTC_SEC_CK_PDN_MASK 0x1
+#define PMIC_RTC_SEC_CK_PDN_SHIFT 0
+#define PMIC_RTC_SEC_WRTGR_ADDR \
+ MT6389_RTC_SEC_WRTGR
+#define PMIC_RTC_SEC_WRTGR_MASK 0x1
+#define PMIC_RTC_SEC_WRTGR_SHIFT 0
+#define PMIC_DCXO_ANA_ID_ADDR \
+ MT6389_DCXO_DSN_ID
+#define PMIC_DCXO_ANA_ID_MASK 0xFF
+#define PMIC_DCXO_ANA_ID_SHIFT 0
+#define PMIC_DCXO_DIG_ID_ADDR \
+ MT6389_DCXO_DSN_ID
+#define PMIC_DCXO_DIG_ID_MASK 0xFF
+#define PMIC_DCXO_DIG_ID_SHIFT 8
+#define PMIC_DCXO_ANA_MINOR_REV_ADDR \
+ MT6389_DCXO_DSN_REV0
+#define PMIC_DCXO_ANA_MINOR_REV_MASK 0xF
+#define PMIC_DCXO_ANA_MINOR_REV_SHIFT 0
+#define PMIC_DCXO_ANA_MAJOR_REV_ADDR \
+ MT6389_DCXO_DSN_REV0
+#define PMIC_DCXO_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_DCXO_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_DCXO_DIG_MINOR_REV_ADDR \
+ MT6389_DCXO_DSN_REV0
+#define PMIC_DCXO_DIG_MINOR_REV_MASK 0xF
+#define PMIC_DCXO_DIG_MINOR_REV_SHIFT 8
+#define PMIC_DCXO_DIG_MAJOR_REV_ADDR \
+ MT6389_DCXO_DSN_REV0
+#define PMIC_DCXO_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_DCXO_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_DCXO_DSN_CBS_ADDR \
+ MT6389_DCXO_DSN_DBI
+#define PMIC_DCXO_DSN_CBS_MASK 0x3
+#define PMIC_DCXO_DSN_CBS_SHIFT 0
+#define PMIC_DCXO_DSN_BIX_ADDR \
+ MT6389_DCXO_DSN_DBI
+#define PMIC_DCXO_DSN_BIX_MASK 0x3
+#define PMIC_DCXO_DSN_BIX_SHIFT 2
+#define PMIC_DCXO_DSN_ESP_ADDR \
+ MT6389_DCXO_DSN_DBI
+#define PMIC_DCXO_DSN_ESP_MASK 0xFF
+#define PMIC_DCXO_DSN_ESP_SHIFT 8
+#define PMIC_DCXO_DSN_FPI_ADDR \
+ MT6389_DCXO_DSN_DXI
+#define PMIC_DCXO_DSN_FPI_MASK 0xFF
+#define PMIC_DCXO_DSN_FPI_SHIFT 0
+#define PMIC_XO_EXTBUF1_MODE_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF1_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF1_MODE_SHIFT 0
+#define PMIC_XO_EXTBUF1_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF1_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF1_EN_M_SHIFT 2
+#define PMIC_XO_EXTBUF2_MODE_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF2_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF2_MODE_SHIFT 3
+#define PMIC_XO_EXTBUF2_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF2_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF2_EN_M_SHIFT 5
+#define PMIC_XO_EXTBUF3_MODE_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF3_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF3_MODE_SHIFT 6
+#define PMIC_XO_EXTBUF3_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF3_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF3_EN_M_SHIFT 8
+#define PMIC_XO_EXTBUF4_MODE_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF4_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF4_MODE_SHIFT 9
+#define PMIC_XO_EXTBUF4_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_EXTBUF4_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF4_EN_M_SHIFT 11
+#define PMIC_XO_BB_LPM_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_BB_LPM_EN_M_MASK 0x1
+#define PMIC_XO_BB_LPM_EN_M_SHIFT 12
+#define PMIC_XO_ENBB_MAN_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_ENBB_MAN_MASK 0x1
+#define PMIC_XO_ENBB_MAN_SHIFT 13
+#define PMIC_XO_ENBB_EN_M_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_ENBB_EN_M_MASK 0x1
+#define PMIC_XO_ENBB_EN_M_SHIFT 14
+#define PMIC_XO_CLKSEL_MAN_ADDR \
+ MT6389_DCXO_CW00
+#define PMIC_XO_CLKSEL_MAN_MASK 0x1
+#define PMIC_XO_CLKSEL_MAN_SHIFT 15
+#define PMIC_DCXO_CW00_SET_ADDR \
+ MT6389_DCXO_CW00_SET
+#define PMIC_DCXO_CW00_SET_MASK 0xFFFF
+#define PMIC_DCXO_CW00_SET_SHIFT 0
+#define PMIC_DCXO_CW00_CLR_ADDR \
+ MT6389_DCXO_CW00_CLR
+#define PMIC_DCXO_CW00_CLR_MASK 0xFFFF
+#define PMIC_DCXO_CW00_CLR_SHIFT 0
+#define PMIC_XO_CLKSEL_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_CLKSEL_EN_M_MASK 0x1
+#define PMIC_XO_CLKSEL_EN_M_SHIFT 0
+#define PMIC_XO_EXTBUF1_CKG_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF1_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF1_CKG_MAN_SHIFT 1
+#define PMIC_XO_EXTBUF1_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF1_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF1_CKG_EN_M_SHIFT 2
+#define PMIC_XO_EXTBUF2_CKG_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF2_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF2_CKG_MAN_SHIFT 3
+#define PMIC_XO_EXTBUF2_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF2_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF2_CKG_EN_M_SHIFT 4
+#define PMIC_XO_EXTBUF3_CKG_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF3_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF3_CKG_MAN_SHIFT 5
+#define PMIC_XO_EXTBUF3_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF3_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF3_CKG_EN_M_SHIFT 6
+#define PMIC_XO_EXTBUF4_CKG_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF4_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF4_CKG_MAN_SHIFT 7
+#define PMIC_XO_EXTBUF4_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_EXTBUF4_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF4_CKG_EN_M_SHIFT 8
+#define PMIC_XO_HV_PBUF_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_HV_PBUF_MAN_MASK 0x1
+#define PMIC_XO_HV_PBUF_MAN_SHIFT 9
+#define PMIC_XO_HV_PBUF_EN_SYNC_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_HV_PBUF_EN_SYNC_M_MASK 0x1
+#define PMIC_XO_HV_PBUF_EN_SYNC_M_SHIFT 10
+#define PMIC_XO_HV_PBUFBIAS_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_HV_PBUFBIAS_EN_M_MASK 0x1
+#define PMIC_XO_HV_PBUFBIAS_EN_M_SHIFT 11
+#define PMIC_XO_LV_PBUF_MAN_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_LV_PBUF_MAN_MASK 0x1
+#define PMIC_XO_LV_PBUF_MAN_SHIFT 12
+#define PMIC_XO_LV_PBUFBIAS_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_LV_PBUFBIAS_EN_M_MASK 0x1
+#define PMIC_XO_LV_PBUFBIAS_EN_M_SHIFT 13
+#define PMIC_XO_LV_PBUF_EN_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_LV_PBUF_EN_M_MASK 0x1
+#define PMIC_XO_LV_PBUF_EN_M_SHIFT 14
+#define PMIC_XO_BBLPM_CKSEL_M_ADDR \
+ MT6389_DCXO_CW01
+#define PMIC_XO_BBLPM_CKSEL_M_MASK 0x1
+#define PMIC_XO_BBLPM_CKSEL_M_SHIFT 15
+#define PMIC_XO_EN32K_MAN_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_EN32K_MAN_MASK 0x1
+#define PMIC_XO_EN32K_MAN_SHIFT 0
+#define PMIC_XO_EN32K_M_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_EN32K_M_MASK 0x1
+#define PMIC_XO_EN32K_M_SHIFT 1
+#define PMIC_RG_XO_CBANK_POL_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_RG_XO_CBANK_POL_MASK 0x1
+#define PMIC_RG_XO_CBANK_POL_SHIFT 2
+#define PMIC_XO_XMODE_M_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_XMODE_M_MASK 0x1
+#define PMIC_XO_XMODE_M_SHIFT 3
+#define PMIC_XO_STRUP_MODE_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_STRUP_MODE_MASK 0x1
+#define PMIC_XO_STRUP_MODE_SHIFT 4
+#define PMIC_RG_XO_PCTAT_CCOMP_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_RG_XO_PCTAT_CCOMP_MASK 0x3
+#define PMIC_RG_XO_PCTAT_CCOMP_SHIFT 5
+#define PMIC_RG_XO_VTEST_SEL_MUX_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_RG_XO_VTEST_SEL_MUX_MASK 0x1F
+#define PMIC_RG_XO_VTEST_SEL_MUX_SHIFT 7
+#define PMIC_XO_SWRST_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_SWRST_MASK 0x1
+#define PMIC_XO_SWRST_SHIFT 12
+#define PMIC_XO_CBANK_SYNC_DYN_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_CBANK_SYNC_DYN_MASK 0x1
+#define PMIC_XO_CBANK_SYNC_DYN_SHIFT 13
+#define PMIC_XO_PCTAT_EN_MAN_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_PCTAT_EN_MAN_MASK 0x1
+#define PMIC_XO_PCTAT_EN_MAN_SHIFT 14
+#define PMIC_XO_PCTAT_EN_M_ADDR \
+ MT6389_DCXO_CW02
+#define PMIC_XO_PCTAT_EN_M_MASK 0x1
+#define PMIC_XO_PCTAT_EN_M_SHIFT 15
+#define PMIC_XO_PMU_CKEN_M_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_PMU_CKEN_M_MASK 0x1
+#define PMIC_XO_PMU_CKEN_M_SHIFT 0
+#define PMIC_XO_PMU_CKEN_MAN_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_PMU_CKEN_MAN_MASK 0x1
+#define PMIC_XO_PMU_CKEN_MAN_SHIFT 1
+#define PMIC_XO_EXTBUF6_CKG_MAN_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_EXTBUF6_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF6_CKG_MAN_SHIFT 2
+#define PMIC_XO_EXTBUF6_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_EXTBUF6_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF6_CKG_EN_M_SHIFT 3
+#define PMIC_XO_EXTBUF7_CKG_MAN_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_EXTBUF7_CKG_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF7_CKG_MAN_SHIFT 4
+#define PMIC_XO_EXTBUF7_CKG_EN_M_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_EXTBUF7_CKG_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF7_CKG_EN_M_SHIFT 5
+#define PMIC_RG_XO_CORE_LPM_ISEL_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_RG_XO_CORE_LPM_ISEL_MASK 0x1F
+#define PMIC_RG_XO_CORE_LPM_ISEL_SHIFT 6
+#define PMIC_XO_FPM_ISEL_M_ADDR \
+ MT6389_DCXO_CW03
+#define PMIC_XO_FPM_ISEL_M_MASK 0x1F
+#define PMIC_XO_FPM_ISEL_M_SHIFT 11
+#define PMIC_XO_CDAC_FPM_ADDR \
+ MT6389_DCXO_CW04
+#define PMIC_XO_CDAC_FPM_MASK 0xFF
+#define PMIC_XO_CDAC_FPM_SHIFT 0
+#define PMIC_XO_CDAC_LPM_ADDR \
+ MT6389_DCXO_CW04
+#define PMIC_XO_CDAC_LPM_MASK 0xFF
+#define PMIC_XO_CDAC_LPM_SHIFT 8
+#define PMIC_XO_32KDIV_NFRAC_FPM_ADDR \
+ MT6389_DCXO_CW05
+#define PMIC_XO_32KDIV_NFRAC_FPM_MASK 0x3FFF
+#define PMIC_XO_32KDIV_NFRAC_FPM_SHIFT 0
+#define PMIC_XO_COFST_FPM_ADDR \
+ MT6389_DCXO_CW05
+#define PMIC_XO_COFST_FPM_MASK 0x3
+#define PMIC_XO_COFST_FPM_SHIFT 14
+#define PMIC_XO_32KDIV_NFRAC_LPM_ADDR \
+ MT6389_DCXO_CW06
+#define PMIC_XO_32KDIV_NFRAC_LPM_MASK 0x3FFF
+#define PMIC_XO_32KDIV_NFRAC_LPM_SHIFT 0
+#define PMIC_XO_COFST_LPM_ADDR \
+ MT6389_DCXO_CW06
+#define PMIC_XO_COFST_LPM_MASK 0x3
+#define PMIC_XO_COFST_LPM_SHIFT 14
+#define PMIC_XO_CORE_MAN_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_MAN_MASK 0x1
+#define PMIC_XO_CORE_MAN_SHIFT 0
+#define PMIC_XO_CORE_EN_M_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_EN_M_MASK 0x1
+#define PMIC_XO_CORE_EN_M_SHIFT 1
+#define PMIC_XO_CORE_TURBO_EN_SYNC_M_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_TURBO_EN_SYNC_M_MASK 0x1
+#define PMIC_XO_CORE_TURBO_EN_SYNC_M_SHIFT 2
+#define PMIC_RG_XO_PCTAT_IS_EN_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_RG_XO_PCTAT_IS_EN_MASK 0x1
+#define PMIC_RG_XO_PCTAT_IS_EN_SHIFT 3
+#define PMIC_XO_STARTUP_EN_M_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_STARTUP_EN_M_MASK 0x1
+#define PMIC_XO_STARTUP_EN_M_SHIFT 4
+#define PMIC_RG_XO_CMP_GSEL_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_RG_XO_CMP_GSEL_MASK 0x3
+#define PMIC_RG_XO_CMP_GSEL_SHIFT 5
+#define PMIC_XO_CORE_VBSEL_SYNC_M_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_VBSEL_SYNC_M_MASK 0x1
+#define PMIC_XO_CORE_VBSEL_SYNC_M_SHIFT 7
+#define PMIC_XO_CORE_FPMBIAS_EN_M_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_FPMBIAS_EN_M_MASK 0x1
+#define PMIC_XO_CORE_FPMBIAS_EN_M_SHIFT 8
+#define PMIC_XO_CORE_LPMCF_SYNC_FPM_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_LPMCF_SYNC_FPM_MASK 0x1
+#define PMIC_XO_CORE_LPMCF_SYNC_FPM_SHIFT 9
+#define PMIC_XO_CORE_LPMCF_SYNC_LPM_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_XO_CORE_LPMCF_SYNC_LPM_MASK 0x1
+#define PMIC_XO_CORE_LPMCF_SYNC_LPM_SHIFT 10
+#define PMIC_RG_XO_CORE_LPM_ISEL_MAN_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_RG_XO_CORE_LPM_ISEL_MAN_MASK 0x1
+#define PMIC_RG_XO_CORE_LPM_ISEL_MAN_SHIFT 11
+#define PMIC_RG_XO_CORE_LPM_IDAC_ADDR \
+ MT6389_DCXO_CW07
+#define PMIC_RG_XO_CORE_LPM_IDAC_MASK 0xF
+#define PMIC_RG_XO_CORE_LPM_IDAC_SHIFT 12
+#define PMIC_XO_AAC_CMP_MAN_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_CMP_MAN_MASK 0x1
+#define PMIC_XO_AAC_CMP_MAN_SHIFT 0
+#define PMIC_XO_AAC_EN_M_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_EN_M_MASK 0x1
+#define PMIC_XO_AAC_EN_M_SHIFT 1
+#define PMIC_XO_PMIC_TOP_DIG_SW_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_PMIC_TOP_DIG_SW_MASK 0x1
+#define PMIC_XO_PMIC_TOP_DIG_SW_SHIFT 2
+#define PMIC_XO_CMP_EN_M_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_CMP_EN_M_MASK 0x1
+#define PMIC_XO_CMP_EN_M_SHIFT 3
+#define PMIC_XO_AAC_VSEL_M_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_VSEL_M_MASK 0xF
+#define PMIC_XO_AAC_VSEL_M_SHIFT 4
+#define PMIC_RG_XO_AAC_X1EN_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_RG_XO_AAC_X1EN_MASK 0x1
+#define PMIC_RG_XO_AAC_X1EN_SHIFT 8
+#define PMIC_RG_XO_LVBUF_CKSEL_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_RG_XO_LVBUF_CKSEL_MASK 0x1
+#define PMIC_RG_XO_LVBUF_CKSEL_SHIFT 9
+#define PMIC_RG_XO_RFCK_EXTBUF_LP_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_RG_XO_RFCK_EXTBUF_LP_MASK 0x1
+#define PMIC_RG_XO_RFCK_EXTBUF_LP_SHIFT 10
+#define PMIC_RG_XO_BBCK_EXTBUF_LP_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_RG_XO_BBCK_EXTBUF_LP_MASK 0x1
+#define PMIC_RG_XO_BBCK_EXTBUF_LP_SHIFT 11
+#define PMIC_XO_AAC_FPM_TIME_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_FPM_TIME_MASK 0x3
+#define PMIC_XO_AAC_FPM_TIME_SHIFT 12
+#define PMIC_XO_AAC_ISEL_MAN_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_ISEL_MAN_MASK 0x1
+#define PMIC_XO_AAC_ISEL_MAN_SHIFT 14
+#define PMIC_XO_AAC_FPM_SWEN_ADDR \
+ MT6389_DCXO_CW08
+#define PMIC_XO_AAC_FPM_SWEN_MASK 0x1
+#define PMIC_XO_AAC_FPM_SWEN_SHIFT 15
+#define PMIC_XO_32KDIV_SWRST_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_32KDIV_SWRST_MASK 0x1
+#define PMIC_XO_32KDIV_SWRST_SHIFT 0
+#define PMIC_XO_32KDIV_RATIO_MAN_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_32KDIV_RATIO_MAN_MASK 0x1
+#define PMIC_XO_32KDIV_RATIO_MAN_SHIFT 1
+#define PMIC_XO_32KDIV_TEST_EN_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_32KDIV_TEST_EN_MASK 0x1
+#define PMIC_XO_32KDIV_TEST_EN_SHIFT 2
+#define PMIC_XO_CTL_SYNC_BUF_MAN_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_CTL_SYNC_BUF_MAN_MASK 0x1
+#define PMIC_XO_CTL_SYNC_BUF_MAN_SHIFT 3
+#define PMIC_XO_CTL_SYNC_BUF_EN_M_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_CTL_SYNC_BUF_EN_M_MASK 0x1
+#define PMIC_XO_CTL_SYNC_BUF_EN_M_SHIFT 4
+#define PMIC_RG_XO_HV_PBUF_VSET_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_RG_XO_HV_PBUF_VSET_MASK 0xF
+#define PMIC_RG_XO_HV_PBUF_VSET_SHIFT 5
+#define PMIC_XO_EXTBUF6_MODE_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_EXTBUF6_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF6_MODE_SHIFT 9
+#define PMIC_XO_EXTBUF6_EN_M_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_EXTBUF6_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF6_EN_M_SHIFT 11
+#define PMIC_XO_EXTBUF7_MODE_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_EXTBUF7_MODE_MASK 0x3
+#define PMIC_XO_EXTBUF7_MODE_SHIFT 12
+#define PMIC_XO_EXTBUF7_EN_M_ADDR \
+ MT6389_DCXO_CW09
+#define PMIC_XO_EXTBUF7_EN_M_MASK 0x1
+#define PMIC_XO_EXTBUF7_EN_M_SHIFT 14
+#define PMIC_DCXO_CW09_SET_ADDR \
+ MT6389_DCXO_CW09_SET
+#define PMIC_DCXO_CW09_SET_MASK 0xFFFF
+#define PMIC_DCXO_CW09_SET_SHIFT 0
+#define PMIC_DCXO_CW09_CLR_ADDR \
+ MT6389_DCXO_CW09_CLR
+#define PMIC_DCXO_CW09_CLR_MASK 0xFFFF
+#define PMIC_DCXO_CW09_CLR_SHIFT 0
+#define PMIC_XO_MDB_TBO_EN_SEL_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_MDB_TBO_EN_SEL_MASK 0x1
+#define PMIC_XO_MDB_TBO_EN_SEL_SHIFT 0
+#define PMIC_XO_EXTBUF4_CLKSEL_MAN_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_EXTBUF4_CLKSEL_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF4_CLKSEL_MAN_SHIFT 1
+#define PMIC_XO_VIO18PG_BUFEN_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_VIO18PG_BUFEN_MASK 0x1
+#define PMIC_XO_VIO18PG_BUFEN_SHIFT 2
+#define PMIC_XO_CAL_EN_MAN_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_CAL_EN_MAN_MASK 0x1
+#define PMIC_XO_CAL_EN_MAN_SHIFT 3
+#define PMIC_XO_CAL_EN_M_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_CAL_EN_M_MASK 0x1
+#define PMIC_XO_CAL_EN_M_SHIFT 4
+#define PMIC_RG_XO_CORE_OSCTD_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_CORE_OSCTD_MASK 0x3
+#define PMIC_RG_XO_CORE_OSCTD_SHIFT 5
+#define PMIC_XO_THADC_EN_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_XO_THADC_EN_MASK 0x1
+#define PMIC_XO_THADC_EN_SHIFT 7
+#define PMIC_RG_XO_SYNC_CKPOL_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_SYNC_CKPOL_MASK 0x1
+#define PMIC_RG_XO_SYNC_CKPOL_SHIFT 8
+#define PMIC_RG_XO_CORE_FPM_IDAC_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_CORE_FPM_IDAC_MASK 0x3
+#define PMIC_RG_XO_CORE_FPM_IDAC_SHIFT 9
+#define PMIC_RG_XO_CTL_POL_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_CTL_POL_MASK 0x1
+#define PMIC_RG_XO_CTL_POL_SHIFT 11
+#define PMIC_RG_XO_CTL_SYNC_BYP_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_CTL_SYNC_BYP_MASK 0x1
+#define PMIC_RG_XO_CTL_SYNC_BYP_SHIFT 12
+#define PMIC_RG_XO_VXO22PG_MAN_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_VXO22PG_MAN_MASK 0x1
+#define PMIC_RG_XO_VXO22PG_MAN_SHIFT 13
+#define PMIC_RG_XO_HV_PBUF_BYP_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_HV_PBUF_BYP_MASK 0x1
+#define PMIC_RG_XO_HV_PBUF_BYP_SHIFT 14
+#define PMIC_RG_XO_HV_PBUF_ENCL_ADDR \
+ MT6389_DCXO_CW10
+#define PMIC_RG_XO_HV_PBUF_ENCL_MASK 0x1
+#define PMIC_RG_XO_HV_PBUF_ENCL_SHIFT 15
+#define PMIC_RG_XO_CORE_VGBIAS_VSET_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_CORE_VGBIAS_VSET_MASK 0x7
+#define PMIC_RG_XO_CORE_VGBIAS_VSET_SHIFT 0
+#define PMIC_XO_CORE_TURBO_EN_SYNC_MAN_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_XO_CORE_TURBO_EN_SYNC_MAN_MASK 0x1
+#define PMIC_XO_CORE_TURBO_EN_SYNC_MAN_SHIFT 3
+#define PMIC_RG_XO_HV_PBUF_ISET_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_HV_PBUF_ISET_MASK 0x3
+#define PMIC_RG_XO_HV_PBUF_ISET_SHIFT 4
+#define PMIC_RG_XO_HEATER_SEL_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_HEATER_SEL_MASK 0x3
+#define PMIC_RG_XO_HEATER_SEL_SHIFT 6
+#define PMIC_RG_XO_RESERVED6_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_RESERVED6_MASK 0x1
+#define PMIC_RG_XO_RESERVED6_SHIFT 8
+#define PMIC_RG_XO_VOW_EN_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_VOW_EN_MASK 0x1
+#define PMIC_RG_XO_VOW_EN_SHIFT 9
+#define PMIC_RG_XO_LV_PBUF_ISET_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_LV_PBUF_ISET_MASK 0x7
+#define PMIC_RG_XO_LV_PBUF_ISET_SHIFT 10
+#define PMIC_RG_XO_LV_PBUF_FPMISET_ADDR \
+ MT6389_DCXO_CW11
+#define PMIC_RG_XO_LV_PBUF_FPMISET_MASK 0x7
+#define PMIC_RG_XO_LV_PBUF_FPMISET_SHIFT 13
+#define PMIC_XO_BB_LPM_EN_SEL_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_BB_LPM_EN_SEL_MASK 0x1
+#define PMIC_XO_BB_LPM_EN_SEL_SHIFT 0
+#define PMIC_XO_EXTBUF1_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF1_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF1_BBLPM_EN_MASK_SHIFT 1
+#define PMIC_XO_EXTBUF2_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF2_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF2_BBLPM_EN_MASK_SHIFT 2
+#define PMIC_XO_EXTBUF3_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF3_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF3_BBLPM_EN_MASK_SHIFT 3
+#define PMIC_XO_EXTBUF4_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF4_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF4_BBLPM_EN_MASK_SHIFT 4
+#define PMIC_XO_EXTBUF6_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF6_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF6_BBLPM_EN_MASK_SHIFT 5
+#define PMIC_XO_EXTBUF7_BBLPM_EN_MASK_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF7_BBLPM_EN_MASK_MASK 0x1
+#define PMIC_XO_EXTBUF7_BBLPM_EN_MASK_SHIFT 6
+#define PMIC_RG_XO_DIG26M_DIV4_32KDIV_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_DIG26M_DIV4_32KDIV_MASK 0x1
+#define PMIC_RG_XO_DIG26M_DIV4_32KDIV_SHIFT 7
+#define PMIC_RG_XO_BBLPM_FREQ_FPM_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_BBLPM_FREQ_FPM_MASK 0x1
+#define PMIC_RG_XO_BBLPM_FREQ_FPM_SHIFT 8
+#define PMIC_RG_XO_EXTBUF2_INV_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_EXTBUF2_INV_MASK 0x1
+#define PMIC_RG_XO_EXTBUF2_INV_SHIFT 9
+#define PMIC_RG_XO_EXTBUF3_INV_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_EXTBUF3_INV_MASK 0x1
+#define PMIC_RG_XO_EXTBUF3_INV_SHIFT 10
+#define PMIC_XO_THADC_EN_MAN_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_THADC_EN_MAN_MASK 0x1
+#define PMIC_XO_THADC_EN_MAN_SHIFT 11
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK 0x1
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT 12
+#define PMIC_RG_XO_AUDIO_EN_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_AUDIO_EN_MASK 0x1
+#define PMIC_RG_XO_AUDIO_EN_SHIFT 13
+#define PMIC_RG_XO_AUDIO_ATTEN_ADDR \
+ MT6389_DCXO_CW12
+#define PMIC_RG_XO_AUDIO_ATTEN_MASK 0x3
+#define PMIC_RG_XO_AUDIO_ATTEN_SHIFT 14
+#define PMIC_RG_XO_EXTBUF2_SRSEL_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF2_SRSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF2_SRSEL_SHIFT 0
+#define PMIC_RG_XO_DIG26M_DEGLITCH_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_DIG26M_DEGLITCH_MASK 0x1
+#define PMIC_RG_XO_DIG26M_DEGLITCH_SHIFT 3
+#define PMIC_RG_XO_EXTBUF4_SRSEL_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF4_SRSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF4_SRSEL_SHIFT 4
+#define PMIC_RG_XO_DIG26M_DIV2_SW_MAN_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_DIG26M_DIV2_SW_MAN_MASK 0x1
+#define PMIC_RG_XO_DIG26M_DIV2_SW_MAN_SHIFT 7
+#define PMIC_RG_XO_EXTBUF1_HD_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF1_HD_MASK 0x3
+#define PMIC_RG_XO_EXTBUF1_HD_SHIFT 8
+#define PMIC_RG_XO_EXTBUF3_HD_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF3_HD_MASK 0x3
+#define PMIC_RG_XO_EXTBUF3_HD_SHIFT 10
+#define PMIC_RG_XO_EXTBUF6_HD_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF6_HD_MASK 0x3
+#define PMIC_RG_XO_EXTBUF6_HD_SHIFT 12
+#define PMIC_RG_XO_EXTBUF7_HD_ADDR \
+ MT6389_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF7_HD_MASK 0x3
+#define PMIC_RG_XO_EXTBUF7_HD_SHIFT 14
+#define PMIC_XO_STA_CTL_MAN_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_STA_CTL_MAN_MASK 0x1
+#define PMIC_XO_STA_CTL_MAN_SHIFT 0
+#define PMIC_XO_STA_CTL_M_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_STA_CTL_M_MASK 0x7
+#define PMIC_XO_STA_CTL_M_SHIFT 1
+#define PMIC_XO_VBBCK_EN_MAN_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_VBBCK_EN_MAN_MASK 0x1
+#define PMIC_XO_VBBCK_EN_MAN_SHIFT 4
+#define PMIC_XO_VBBCK_EN_M_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_VBBCK_EN_M_MASK 0x1
+#define PMIC_XO_VBBCK_EN_M_SHIFT 5
+#define PMIC_XO_VRFCK_EN_MAN_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_VRFCK_EN_MAN_MASK 0x1
+#define PMIC_XO_VRFCK_EN_MAN_SHIFT 6
+#define PMIC_XO_VRFCK_EN_M_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_VRFCK_EN_M_MASK 0x1
+#define PMIC_XO_VRFCK_EN_M_SHIFT 7
+#define PMIC_XO_RESERVED2_ADDR \
+ MT6389_DCXO_CW14
+#define PMIC_XO_RESERVED2_MASK 0xFF
+#define PMIC_XO_RESERVED2_SHIFT 8
+#define PMIC_RG_XO_RESERVED1_ADDR \
+ MT6389_DCXO_CW15
+#define PMIC_RG_XO_RESERVED1_MASK 0xFF
+#define PMIC_RG_XO_RESERVED1_SHIFT 0
+#define PMIC_RG_XO_RESERVED2_ADDR \
+ MT6389_DCXO_CW15
+#define PMIC_RG_XO_RESERVED2_MASK 0xFF
+#define PMIC_RG_XO_RESERVED2_SHIFT 8
+#define PMIC_XO_STATIC_AUXOUT_SEL_ADDR \
+ MT6389_DCXO_CW16
+#define PMIC_XO_STATIC_AUXOUT_SEL_MASK 0x3F
+#define PMIC_XO_STATIC_AUXOUT_SEL_SHIFT 0
+#define PMIC_XO_AUXOUT_SEL_ADDR \
+ MT6389_DCXO_CW16
+#define PMIC_XO_AUXOUT_SEL_MASK 0x3FF
+#define PMIC_XO_AUXOUT_SEL_SHIFT 6
+#define PMIC_XO_STATIC_AUXOUT_ADDR \
+ MT6389_DCXO_CW17
+#define PMIC_XO_STATIC_AUXOUT_MASK 0xFFFF
+#define PMIC_XO_STATIC_AUXOUT_SHIFT 0
+#define PMIC_RG_XO_PCTAT_BG_EN_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_BG_EN_MASK 0x1
+#define PMIC_RG_XO_PCTAT_BG_EN_SHIFT 0
+#define PMIC_RG_XO_PCTAT_RPTAT_SEL_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_RPTAT_SEL_MASK 0x7
+#define PMIC_RG_XO_PCTAT_RPTAT_SEL_SHIFT 1
+#define PMIC_RG_XO_PCTAT_IPTAT_SEL_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_IPTAT_SEL_MASK 0x3
+#define PMIC_RG_XO_PCTAT_IPTAT_SEL_SHIFT 4
+#define PMIC_RG_XO_PCTAT_RCTAT_SEL_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_RCTAT_SEL_MASK 0x7
+#define PMIC_RG_XO_PCTAT_RCTAT_SEL_SHIFT 6
+#define PMIC_RG_XO_PCTAT_ICTAT_SEL_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_ICTAT_SEL_MASK 0x3
+#define PMIC_RG_XO_PCTAT_ICTAT_SEL_SHIFT 9
+#define PMIC_RG_XO_CBANK_SYNC_BYP_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_CBANK_SYNC_BYP_MASK 0x1
+#define PMIC_RG_XO_CBANK_SYNC_BYP_SHIFT 11
+#define PMIC_RG_XO_PCTAT_VCTAT_SEL_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_VCTAT_SEL_MASK 0x1
+#define PMIC_RG_XO_PCTAT_VCTAT_SEL_SHIFT 12
+#define PMIC_RG_XO_PCTAT_VTEMP_ADDR \
+ MT6389_DCXO_CW18
+#define PMIC_RG_XO_PCTAT_VTEMP_MASK 0x7
+#define PMIC_RG_XO_PCTAT_VTEMP_SHIFT 13
+#define PMIC_RG_XO_CORE_LPM_PMICBIAS_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_CORE_LPM_PMICBIAS_MASK 0x1
+#define PMIC_RG_XO_CORE_LPM_PMICBIAS_SHIFT 0
+#define PMIC_RG_XO_EXTBUF1_RSEL_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF1_RSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF1_RSEL_SHIFT 1
+#define PMIC_RG_XO_EXTBUF2_RSEL_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF2_RSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF2_RSEL_SHIFT 4
+#define PMIC_RG_XO_EXTBUF3_RSEL_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF3_RSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF3_RSEL_SHIFT 7
+#define PMIC_RG_XO_EXTBUF4_RSEL_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF4_RSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF4_RSEL_SHIFT 10
+#define PMIC_RG_XO_EXTBUF7_RSEL_ADDR \
+ MT6389_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF7_RSEL_MASK 0x7
+#define PMIC_RG_XO_EXTBUF7_RSEL_SHIFT 13
+#define PMIC_DCXO_ELR_LEN_ADDR \
+ MT6389_DCXO_ELR_NUM
+#define PMIC_DCXO_ELR_LEN_MASK 0xFF
+#define PMIC_DCXO_ELR_LEN_SHIFT 0
+#define PMIC_RG_XO_DIG26M_DIV2_ADDR \
+ MT6389_DCXO_ELR0
+#define PMIC_RG_XO_DIG26M_DIV2_MASK 0x1
+#define PMIC_RG_XO_DIG26M_DIV2_SHIFT 0
+#define PMIC_XO_PWRKEY_RSTB_SEL_ADDR \
+ MT6389_DCXO_ELR0
+#define PMIC_XO_PWRKEY_RSTB_SEL_MASK 0x1
+#define PMIC_XO_PWRKEY_RSTB_SEL_SHIFT 1
+#define PMIC_XO_ELR_RESERVED_ADDR \
+ MT6389_DCXO_ELR0
+#define PMIC_XO_ELR_RESERVED_MASK 0x3F
+#define PMIC_XO_ELR_RESERVED_SHIFT 2
+#define PMIC_PSC_TOP_ANA_ID_ADDR \
+ MT6389_PSC_TOP_ID
+#define PMIC_PSC_TOP_ANA_ID_MASK 0xFF
+#define PMIC_PSC_TOP_ANA_ID_SHIFT 0
+#define PMIC_PSC_TOP_DIG_ID_ADDR \
+ MT6389_PSC_TOP_ID
+#define PMIC_PSC_TOP_DIG_ID_MASK 0xFF
+#define PMIC_PSC_TOP_DIG_ID_SHIFT 8
+#define PMIC_PSC_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_PSC_TOP_REV0
+#define PMIC_PSC_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_PSC_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_PSC_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_PSC_TOP_REV0
+#define PMIC_PSC_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_PSC_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_PSC_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_PSC_TOP_REV0
+#define PMIC_PSC_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_PSC_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_PSC_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_PSC_TOP_REV0
+#define PMIC_PSC_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_PSC_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_PSC_TOP_CBS_ADDR \
+ MT6389_PSC_TOP_DBI
+#define PMIC_PSC_TOP_CBS_MASK 0x3
+#define PMIC_PSC_TOP_CBS_SHIFT 0
+#define PMIC_PSC_TOP_BIX_ADDR \
+ MT6389_PSC_TOP_DBI
+#define PMIC_PSC_TOP_BIX_MASK 0x3
+#define PMIC_PSC_TOP_BIX_SHIFT 2
+#define PMIC_PSC_TOP_ESP_ADDR \
+ MT6389_PSC_TOP_DBI
+#define PMIC_PSC_TOP_ESP_MASK 0xFF
+#define PMIC_PSC_TOP_ESP_SHIFT 8
+#define PMIC_PSC_TOP_FPI_ADDR \
+ MT6389_PSC_TOP_DXI
+#define PMIC_PSC_TOP_FPI_MASK 0xFF
+#define PMIC_PSC_TOP_FPI_SHIFT 0
+#define PMIC_PSC_TOP_CLK_OFFSET_ADDR \
+ MT6389_PSC_TPM0
+#define PMIC_PSC_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_PSC_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_PSC_TOP_RST_OFFSET_ADDR \
+ MT6389_PSC_TPM0
+#define PMIC_PSC_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_PSC_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_PSC_TOP_INT_OFFSET_ADDR \
+ MT6389_PSC_TPM1
+#define PMIC_PSC_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_PSC_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_PSC_TOP_INT_LEN_ADDR \
+ MT6389_PSC_TPM1
+#define PMIC_PSC_TOP_INT_LEN_MASK 0xFF
+#define PMIC_PSC_TOP_INT_LEN_SHIFT 8
+#define PMIC_RG_CHRDET_32K_CK_PDN_ADDR \
+ MT6389_PSC_TOP_CLKCTL_0
+#define PMIC_RG_CHRDET_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_CHRDET_32K_CK_PDN_SHIFT 0
+#define PMIC_RG_STRUP_LONG_PRESS_RST_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_RG_STRUP_LONG_PRESS_RST_MASK 0x1
+#define PMIC_RG_STRUP_LONG_PRESS_RST_SHIFT 0
+#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_MASK 0x1
+#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_SHIFT 4
+#define PMIC_BANK_STRUP_SWRST_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_BANK_STRUP_SWRST_MASK 0x1
+#define PMIC_BANK_STRUP_SWRST_SHIFT 8
+#define PMIC_BANK_PSEQ_SWRST_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_BANK_PSEQ_SWRST_MASK 0x1
+#define PMIC_BANK_PSEQ_SWRST_SHIFT 9
+#define PMIC_BANK_CHRDET_SWRST_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_BANK_CHRDET_SWRST_MASK 0x1
+#define PMIC_BANK_CHRDET_SWRST_SHIFT 12
+#define PMIC_RG_CHRDET_RST_ADDR \
+ MT6389_PSC_TOP_RSTCTL_0
+#define PMIC_RG_CHRDET_RST_MASK 0x1
+#define PMIC_RG_CHRDET_RST_SHIFT 13
+#define PMIC_RG_INT_EN_ENB_R_ADDR \
+ MT6389_PSC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_ENB_R_MASK 0x1
+#define PMIC_RG_INT_EN_ENB_R_SHIFT 0
+#define PMIC_RG_INT_EN_PMIC_RESET_B_H2L_ADDR \
+ MT6389_PSC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_PMIC_RESET_B_H2L_MASK 0x1
+#define PMIC_RG_INT_EN_PMIC_RESET_B_H2L_SHIFT 1
+#define PMIC_RG_INT_EN_NI_LBAT_INT_ADDR \
+ MT6389_PSC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_NI_LBAT_INT_MASK 0x1
+#define PMIC_RG_INT_EN_NI_LBAT_INT_SHIFT 2
+#define PMIC_RG_INT_EN_CHRDET_ADDR \
+ MT6389_PSC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_CHRDET_MASK 0x1
+#define PMIC_RG_INT_EN_CHRDET_SHIFT 3
+#define PMIC_RG_INT_EN_CHRDET_EDGE_ADDR \
+ MT6389_PSC_TOP_INT_CON0
+#define PMIC_RG_INT_EN_CHRDET_EDGE_MASK 0x1
+#define PMIC_RG_INT_EN_CHRDET_EDGE_SHIFT 4
+#define PMIC_PSC_INT_CON0_SET_ADDR \
+ MT6389_PSC_TOP_INT_CON0_SET
+#define PMIC_PSC_INT_CON0_SET_MASK 0xFFFF
+#define PMIC_PSC_INT_CON0_SET_SHIFT 0
+#define PMIC_PSC_INT_CON0_CLR_ADDR \
+ MT6389_PSC_TOP_INT_CON0_CLR
+#define PMIC_PSC_INT_CON0_CLR_MASK 0xFFFF
+#define PMIC_PSC_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_ENB_R_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_ENB_R_MASK 0x1
+#define PMIC_RG_INT_MASK_ENB_R_SHIFT 0
+#define PMIC_RG_INT_MASK_PMIC_RESET_B_H2L_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_PMIC_RESET_B_H2L_MASK 0x1
+#define PMIC_RG_INT_MASK_PMIC_RESET_B_H2L_SHIFT 1
+#define PMIC_RG_INT_MASK_NI_LBAT_INT_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_NI_LBAT_INT_MASK 0x1
+#define PMIC_RG_INT_MASK_NI_LBAT_INT_SHIFT 2
+#define PMIC_RG_INT_MASK_CHRDET_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_CHRDET_MASK 0x1
+#define PMIC_RG_INT_MASK_CHRDET_SHIFT 3
+#define PMIC_RG_INT_MASK_CHRDET_EDGE_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_CHRDET_EDGE_MASK 0x1
+#define PMIC_RG_INT_MASK_CHRDET_EDGE_SHIFT 4
+#define PMIC_PSC_INT_MASK_CON0_SET_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0_SET
+#define PMIC_PSC_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_PSC_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_PSC_INT_MASK_CON0_CLR_ADDR \
+ MT6389_PSC_TOP_INT_MASK_CON0_CLR
+#define PMIC_PSC_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_PSC_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_ENB_R_ADDR \
+ MT6389_PSC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_ENB_R_MASK 0x1
+#define PMIC_RG_INT_STATUS_ENB_R_SHIFT 0
+#define PMIC_RG_INT_STATUS_PMIC_RESET_B_H2L_ADDR \
+ MT6389_PSC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_PMIC_RESET_B_H2L_MASK 0x1
+#define PMIC_RG_INT_STATUS_PMIC_RESET_B_H2L_SHIFT 1
+#define PMIC_RG_INT_STATUS_NI_LBAT_INT_ADDR \
+ MT6389_PSC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_NI_LBAT_INT_MASK 0x1
+#define PMIC_RG_INT_STATUS_NI_LBAT_INT_SHIFT 2
+#define PMIC_RG_INT_STATUS_CHRDET_ADDR \
+ MT6389_PSC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_CHRDET_MASK 0x1
+#define PMIC_RG_INT_STATUS_CHRDET_SHIFT 3
+#define PMIC_RG_INT_STATUS_CHRDET_EDGE_ADDR \
+ MT6389_PSC_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_CHRDET_EDGE_MASK 0x1
+#define PMIC_RG_INT_STATUS_CHRDET_EDGE_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_ENB_R_ADDR \
+ MT6389_PSC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_ENB_R_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_ENB_R_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_PMIC_RESET_B_H2L_ADDR \
+ MT6389_PSC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_PMIC_RESET_B_H2L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_PMIC_RESET_B_H2L_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_ADDR \
+ MT6389_PSC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_ADDR \
+ MT6389_PSC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_ADDR \
+ MT6389_PSC_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_SHIFT 4
+#define PMIC_RG_PSC_INT_POLARITY_ADDR \
+ MT6389_PSC_TOP_INT_MISC_CON
+#define PMIC_RG_PSC_INT_POLARITY_MASK 0x1
+#define PMIC_RG_PSC_INT_POLARITY_SHIFT 0
+#define PMIC_INT_MISC_CON_SET_ADDR \
+ MT6389_PSC_TOP_INT_MISC_CON_SET
+#define PMIC_INT_MISC_CON_SET_MASK 0xFFFF
+#define PMIC_INT_MISC_CON_SET_SHIFT 0
+#define PMIC_INT_MISC_CON_CLR_ADDR \
+ MT6389_PSC_TOP_INT_MISC_CON_CLR
+#define PMIC_INT_MISC_CON_CLR_MASK 0xFFFF
+#define PMIC_INT_MISC_CON_CLR_SHIFT 0
+#define PMIC_RG_PSC_MON_GRP_SEL_ADDR \
+ MT6389_PSC_TOP_MON_CTL
+#define PMIC_RG_PSC_MON_GRP_SEL_MASK 0x7
+#define PMIC_RG_PSC_MON_GRP_SEL_SHIFT 0
+#define PMIC_RG_MBS_PSC_KEY_ADDR \
+ MT6389_PSC_KEY_CTL
+#define PMIC_RG_MBS_PSC_KEY_MASK 0xFFFF
+#define PMIC_RG_MBS_PSC_KEY_SHIFT 0
+#define PMIC_STRUP_ANA_ID_ADDR \
+ MT6389_STRUP_ID
+#define PMIC_STRUP_ANA_ID_MASK 0xFF
+#define PMIC_STRUP_ANA_ID_SHIFT 0
+#define PMIC_STRUP_DIG_ID_ADDR \
+ MT6389_STRUP_ID
+#define PMIC_STRUP_DIG_ID_MASK 0xFF
+#define PMIC_STRUP_DIG_ID_SHIFT 8
+#define PMIC_STRUP_ANA_MINOR_REV_ADDR \
+ MT6389_STRUP_REV0
+#define PMIC_STRUP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_STRUP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_STRUP_ANA_MAJOR_REV_ADDR \
+ MT6389_STRUP_REV0
+#define PMIC_STRUP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_STRUP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_STRUP_DIG_MINOR_REV_ADDR \
+ MT6389_STRUP_REV0
+#define PMIC_STRUP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_STRUP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_STRUP_DIG_MAJOR_REV_ADDR \
+ MT6389_STRUP_REV0
+#define PMIC_STRUP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_STRUP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_STRUP_CBS_ADDR \
+ MT6389_STRUP_DBI
+#define PMIC_STRUP_CBS_MASK 0x3
+#define PMIC_STRUP_CBS_SHIFT 0
+#define PMIC_STRUP_BIX_ADDR \
+ MT6389_STRUP_DBI
+#define PMIC_STRUP_BIX_MASK 0x3
+#define PMIC_STRUP_BIX_SHIFT 2
+#define PMIC_STRUP_DSN_ESP_ADDR \
+ MT6389_STRUP_DBI
+#define PMIC_STRUP_DSN_ESP_MASK 0xFF
+#define PMIC_STRUP_DSN_ESP_SHIFT 8
+#define PMIC_STRUP_DSN_FPI_ADDR \
+ MT6389_STRUP_DSN_FPI
+#define PMIC_STRUP_DSN_FPI_MASK 0xFF
+#define PMIC_STRUP_DSN_FPI_SHIFT 0
+#define PMIC_RG_TM_OUT_ADDR \
+ MT6389_STRUP_ANA_CON0
+#define PMIC_RG_TM_OUT_MASK 0xF
+#define PMIC_RG_TM_OUT_SHIFT 0
+#define PMIC_RG_THR_TMODE_ADDR \
+ MT6389_STRUP_ANA_CON0
+#define PMIC_RG_THR_TMODE_MASK 0x1
+#define PMIC_RG_THR_TMODE_SHIFT 4
+#define PMIC_RG_THRDET_SEL_ADDR \
+ MT6389_STRUP_ANA_CON1
+#define PMIC_RG_THRDET_SEL_MASK 0x1
+#define PMIC_RG_THRDET_SEL_SHIFT 0
+#define PMIC_RG_STRUP_THR_SEL_ADDR \
+ MT6389_STRUP_ANA_CON1
+#define PMIC_RG_STRUP_THR_SEL_MASK 0x3
+#define PMIC_RG_STRUP_THR_SEL_SHIFT 1
+#define PMIC_RG_VREF_BG_ADDR \
+ MT6389_STRUP_ANA_CON1
+#define PMIC_RG_VREF_BG_MASK 0x7
+#define PMIC_RG_VREF_BG_SHIFT 3
+#define PMIC_RG_RST_DRVSEL_ADDR \
+ MT6389_STRUP_ANA_CON1
+#define PMIC_RG_RST_DRVSEL_MASK 0x1
+#define PMIC_RG_RST_DRVSEL_SHIFT 6
+#define PMIC_RG_PMU_RSV_ADDR \
+ MT6389_STRUP_ANA_CON1
+#define PMIC_RG_PMU_RSV_MASK 0xF
+#define PMIC_RG_PMU_RSV_SHIFT 8
+#define PMIC_RG_PMU_RSV1_ADDR \
+ MT6389_STRUP_ANA_CON2
+#define PMIC_RG_PMU_RSV1_MASK 0xF
+#define PMIC_RG_PMU_RSV1_SHIFT 0
+#define PMIC_RG_PMU_RSV2_ADDR \
+ MT6389_STRUP_ANA_CON2
+#define PMIC_RG_PMU_RSV2_MASK 0xF
+#define PMIC_RG_PMU_RSV2_SHIFT 4
+#define PMIC_RGS_ANA_CHIP_ID_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_ANA_CHIP_ID_MASK 0x7
+#define PMIC_RGS_ANA_CHIP_ID_SHIFT 0
+#define PMIC_RGS_VUSB_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VUSB_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VUSB_PG_STATUS_SHIFT 3
+#define PMIC_RGS_VAUX18_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VAUX18_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VAUX18_PG_STATUS_SHIFT 4
+#define PMIC_RGS_VAUD28_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VAUD28_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VAUD28_PG_STATUS_SHIFT 5
+#define PMIC_RGS_VXO22_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VXO22_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VXO22_PG_STATUS_SHIFT 6
+#define PMIC_RGS_VEMC_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VEMC_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VEMC_PG_STATUS_SHIFT 7
+#define PMIC_RGS_VIO18_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VIO18_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VIO18_PG_STATUS_SHIFT 8
+#define PMIC_RGS_VIO33_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VIO33_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VIO33_PG_STATUS_SHIFT 9
+#define PMIC_RGS_VSRAM_PROC_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VSRAM_PROC_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VSRAM_PROC_PG_STATUS_SHIFT 10
+#define PMIC_RGS_VA12_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VA12_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VA12_PG_STATUS_SHIFT 11
+#define PMIC_RGS_VA09_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VA09_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VA09_PG_STATUS_SHIFT 12
+#define PMIC_RGS_VRFCK_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VRFCK_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VRFCK_PG_STATUS_SHIFT 13
+#define PMIC_RGS_VRFCK_1_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VRFCK_1_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VRFCK_1_PG_STATUS_SHIFT 14
+#define PMIC_RGS_VBBCK_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON3
+#define PMIC_RGS_VBBCK_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VBBCK_PG_STATUS_SHIFT 15
+#define PMIC_RGS_VRTC28_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VRTC28_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VRTC28_PG_STATUS_SHIFT 0
+#define PMIC_RGS_VS1_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VS1_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VS1_PG_STATUS_SHIFT 1
+#define PMIC_RGS_VMODEM_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VMODEM_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VMODEM_PG_STATUS_SHIFT 2
+#define PMIC_RGS_VPROC_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VPROC_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VPROC_PG_STATUS_SHIFT 3
+#define PMIC_RGS_VCORE_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VCORE_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VCORE_PG_STATUS_SHIFT 4
+#define PMIC_RGS_VSRAM_OTHERS_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VSRAM_OTHERS_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VSRAM_OTHERS_PG_STATUS_SHIFT 5
+#define PMIC_RGS_VDRAM1_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VDRAM1_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VDRAM1_PG_STATUS_SHIFT 6
+#define PMIC_RGS_VDRAM2_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VDRAM2_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VDRAM2_PG_STATUS_SHIFT 7
+#define PMIC_RGS_VS2_PG_STATUS_ADDR \
+ MT6389_STRUP_ANA_CON4
+#define PMIC_RGS_VS2_PG_STATUS_MASK 0x1
+#define PMIC_RGS_VS2_PG_STATUS_SHIFT 8
+#define PMIC_STRUP_ELR_LEN_ADDR \
+ MT6389_STRUP_ELR_NUM
+#define PMIC_STRUP_ELR_LEN_MASK 0xFF
+#define PMIC_STRUP_ELR_LEN_SHIFT 0
+#define PMIC_RG_STRUP_IREF_TRIM_ADDR \
+ MT6389_STRUP_ELR_0
+#define PMIC_RG_STRUP_IREF_TRIM_MASK 0x3F
+#define PMIC_RG_STRUP_IREF_TRIM_SHIFT 0
+#define PMIC_RG_THR_LOC_SEL_ADDR \
+ MT6389_STRUP_ELR_0
+#define PMIC_RG_THR_LOC_SEL_MASK 0xF
+#define PMIC_RG_THR_LOC_SEL_SHIFT 8
+#define PMIC_RG_THR1_140_TRIM_ADDR \
+ MT6389_STRUP_ELR_1
+#define PMIC_RG_THR1_140_TRIM_MASK 0x1F
+#define PMIC_RG_THR1_140_TRIM_SHIFT 0
+#define PMIC_RG_THR1_RSV0_ADDR \
+ MT6389_STRUP_ELR_1
+#define PMIC_RG_THR1_RSV0_MASK 0x7
+#define PMIC_RG_THR1_RSV0_SHIFT 5
+#define PMIC_RG_THR1_110_TRIM_ADDR \
+ MT6389_STRUP_ELR_1
+#define PMIC_RG_THR1_110_TRIM_MASK 0x1F
+#define PMIC_RG_THR1_110_TRIM_SHIFT 8
+#define PMIC_RG_THR1_RSV1_ADDR \
+ MT6389_STRUP_ELR_1
+#define PMIC_RG_THR1_RSV1_MASK 0x7
+#define PMIC_RG_THR1_RSV1_SHIFT 13
+#define PMIC_RG_THR2_140_TRIM_ADDR \
+ MT6389_STRUP_ELR_2
+#define PMIC_RG_THR2_140_TRIM_MASK 0x1F
+#define PMIC_RG_THR2_140_TRIM_SHIFT 0
+#define PMIC_RG_THR2_RSV0_ADDR \
+ MT6389_STRUP_ELR_2
+#define PMIC_RG_THR2_RSV0_MASK 0x7
+#define PMIC_RG_THR2_RSV0_SHIFT 5
+#define PMIC_RG_THR2_110_TRIM_ADDR \
+ MT6389_STRUP_ELR_2
+#define PMIC_RG_THR2_110_TRIM_MASK 0x1F
+#define PMIC_RG_THR2_110_TRIM_SHIFT 8
+#define PMIC_RG_THR2_RSV1_ADDR \
+ MT6389_STRUP_ELR_2
+#define PMIC_RG_THR2_RSV1_MASK 0x7
+#define PMIC_RG_THR2_RSV1_SHIFT 13
+#define PMIC_RG_THR3_140_TRIM_ADDR \
+ MT6389_STRUP_ELR_3
+#define PMIC_RG_THR3_140_TRIM_MASK 0x1F
+#define PMIC_RG_THR3_140_TRIM_SHIFT 0
+#define PMIC_RG_THR3_RSV0_ADDR \
+ MT6389_STRUP_ELR_3
+#define PMIC_RG_THR3_RSV0_MASK 0x7
+#define PMIC_RG_THR3_RSV0_SHIFT 5
+#define PMIC_RG_THR3_110_TRIM_ADDR \
+ MT6389_STRUP_ELR_3
+#define PMIC_RG_THR3_110_TRIM_MASK 0x1F
+#define PMIC_RG_THR3_110_TRIM_SHIFT 8
+#define PMIC_RG_THR3_RSV1_ADDR \
+ MT6389_STRUP_ELR_3
+#define PMIC_RG_THR3_RSV1_MASK 0x7
+#define PMIC_RG_THR3_RSV1_SHIFT 13
+#define PMIC_RG_THR4_140_TRIM_ADDR \
+ MT6389_STRUP_ELR_4
+#define PMIC_RG_THR4_140_TRIM_MASK 0x1F
+#define PMIC_RG_THR4_140_TRIM_SHIFT 0
+#define PMIC_RG_THR4_RSV0_ADDR \
+ MT6389_STRUP_ELR_4
+#define PMIC_RG_THR4_RSV0_MASK 0x7
+#define PMIC_RG_THR4_RSV0_SHIFT 5
+#define PMIC_RG_THR4_110_TRIM_ADDR \
+ MT6389_STRUP_ELR_4
+#define PMIC_RG_THR4_110_TRIM_MASK 0x1F
+#define PMIC_RG_THR4_110_TRIM_SHIFT 8
+#define PMIC_RG_THR4_RSV1_ADDR \
+ MT6389_STRUP_ELR_4
+#define PMIC_RG_THR4_RSV1_MASK 0x7
+#define PMIC_RG_THR4_RSV1_SHIFT 13
+#define PMIC_PSEQ_ANA_ID_ADDR \
+ MT6389_PSEQ_ID
+#define PMIC_PSEQ_ANA_ID_MASK 0xFF
+#define PMIC_PSEQ_ANA_ID_SHIFT 0
+#define PMIC_PSEQ_DIG_ID_ADDR \
+ MT6389_PSEQ_ID
+#define PMIC_PSEQ_DIG_ID_MASK 0xFF
+#define PMIC_PSEQ_DIG_ID_SHIFT 8
+#define PMIC_PSEQ_ANA_MINOR_REV_ADDR \
+ MT6389_PSEQ_REV0
+#define PMIC_PSEQ_ANA_MINOR_REV_MASK 0xF
+#define PMIC_PSEQ_ANA_MINOR_REV_SHIFT 0
+#define PMIC_PSEQ_ANA_MAJOR_REV_ADDR \
+ MT6389_PSEQ_REV0
+#define PMIC_PSEQ_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_PSEQ_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_PSEQ_DIG_MINOR_REV_ADDR \
+ MT6389_PSEQ_REV0
+#define PMIC_PSEQ_DIG_MINOR_REV_MASK 0xF
+#define PMIC_PSEQ_DIG_MINOR_REV_SHIFT 8
+#define PMIC_PSEQ_DIG_MAJOR_REV_ADDR \
+ MT6389_PSEQ_REV0
+#define PMIC_PSEQ_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_PSEQ_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_PSEQ_CBS_ADDR \
+ MT6389_PSEQ_DBI
+#define PMIC_PSEQ_CBS_MASK 0x3
+#define PMIC_PSEQ_CBS_SHIFT 0
+#define PMIC_PSEQ_BIX_ADDR \
+ MT6389_PSEQ_DBI
+#define PMIC_PSEQ_BIX_MASK 0x3
+#define PMIC_PSEQ_BIX_SHIFT 2
+#define PMIC_PSEQ_ESP_ADDR \
+ MT6389_PSEQ_DBI
+#define PMIC_PSEQ_ESP_MASK 0xFF
+#define PMIC_PSEQ_ESP_SHIFT 8
+#define PMIC_PSEQ_FPI_ADDR \
+ MT6389_PSEQ_DXI
+#define PMIC_PSEQ_FPI_MASK 0xFF
+#define PMIC_PSEQ_FPI_SHIFT 0
+#define PMIC_RG_USBDL_MODE_ADDR \
+ MT6389_PPCCTL0
+#define PMIC_RG_USBDL_MODE_MASK 0x1
+#define PMIC_RG_USBDL_MODE_SHIFT 4
+#define PMIC_RG_WDTRST_ACT_ADDR \
+ MT6389_PPCCTL0
+#define PMIC_RG_WDTRST_ACT_MASK 0x3
+#define PMIC_RG_WDTRST_ACT_SHIFT 5
+#define PMIC_RG_CRST_ADDR \
+ MT6389_PPCCTL1
+#define PMIC_RG_CRST_MASK 0x1
+#define PMIC_RG_CRST_SHIFT 0
+#define PMIC_RG_WRST_ADDR \
+ MT6389_PPCCTL1
+#define PMIC_RG_WRST_MASK 0x1
+#define PMIC_RG_WRST_SHIFT 1
+#define PMIC_RG_CRST_INTV_ADDR \
+ MT6389_PPCCTL1
+#define PMIC_RG_CRST_INTV_MASK 0x3
+#define PMIC_RG_CRST_INTV_SHIFT 8
+#define PMIC_RG_WRST_INTV_ADDR \
+ MT6389_PPCCTL1
+#define PMIC_RG_WRST_INTV_MASK 0x3
+#define PMIC_RG_WRST_INTV_SHIFT 10
+#define PMIC_RG_WDTRST_EN_ADDR \
+ MT6389_PPCCFG0
+#define PMIC_RG_WDTRST_EN_MASK 0x1
+#define PMIC_RG_WDTRST_EN_SHIFT 0
+#define PMIC_RG_KEYPWR_VCORE_OPT_ADDR \
+ MT6389_PPCCFG0
+#define PMIC_RG_KEYPWR_VCORE_OPT_MASK 0x1
+#define PMIC_RG_KEYPWR_VCORE_OPT_SHIFT 8
+#define PMIC_RG_KEYPWR_VXO22_OPT_ADDR \
+ MT6389_PPCCFG0
+#define PMIC_RG_KEYPWR_VXO22_OPT_MASK 0x1
+#define PMIC_RG_KEYPWR_VXO22_OPT_SHIFT 9
+#define PMIC_RG_KEYPWR_VIO18_OPT_ADDR \
+ MT6389_PPCCFG0
+#define PMIC_RG_KEYPWR_VIO18_OPT_MASK 0x1
+#define PMIC_RG_KEYPWR_VIO18_OPT_SHIFT 10
+#define PMIC_RG_RSV_SWREG_ADDR \
+ MT6389_STRUP_CON9
+#define PMIC_RG_RSV_SWREG_MASK 0xFFFF
+#define PMIC_RG_RSV_SWREG_SHIFT 0
+#define PMIC_RG_STRUP_THR_CLR_ADDR \
+ MT6389_STRUP_CON11
+#define PMIC_RG_STRUP_THR_CLR_MASK 0x1
+#define PMIC_RG_STRUP_THR_CLR_SHIFT 0
+#define PMIC_RG_UVLO_DEC_EN_ADDR \
+ MT6389_STRUP_CON12
+#define PMIC_RG_UVLO_DEC_EN_MASK 0x1
+#define PMIC_RG_UVLO_DEC_EN_SHIFT 14
+#define PMIC_RG_POR_FLAG_ADDR \
+ MT6389_PORFLAG
+#define PMIC_RG_POR_FLAG_MASK 0x1
+#define PMIC_RG_POR_FLAG_SHIFT 0
+#define PMIC_RGS_CHRDET_ADDR \
+ MT6389_STRUP_CON4
+#define PMIC_RGS_CHRDET_MASK 0x1
+#define PMIC_RGS_CHRDET_SHIFT 0
+#define PMIC_USBDL_ADDR \
+ MT6389_STRUP_CON4
+#define PMIC_USBDL_MASK 0x1
+#define PMIC_USBDL_SHIFT 15
+#define PMIC_RG_STRUP_THER_DEB_RTD_ADDR \
+ MT6389_STRUP_CON1
+#define PMIC_RG_STRUP_THER_DEB_RTD_MASK 0x3
+#define PMIC_RG_STRUP_THER_DEB_RTD_SHIFT 0
+#define PMIC_RG_STRUP_THER_DEB_FTD_ADDR \
+ MT6389_STRUP_CON2
+#define PMIC_RG_STRUP_THER_DEB_FTD_MASK 0x3
+#define PMIC_RG_STRUP_THER_DEB_FTD_SHIFT 0
+#define PMIC_RG_STRUP_EXT_PMIC_EN_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_RG_STRUP_EXT_PMIC_EN_MASK 0x3
+#define PMIC_RG_STRUP_EXT_PMIC_EN_SHIFT 0
+#define PMIC_RG_STRUP_EXT_PMIC_SEL_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_RG_STRUP_EXT_PMIC_SEL_MASK 0x3
+#define PMIC_RG_STRUP_EXT_PMIC_SEL_SHIFT 4
+#define PMIC_RGS_EXT_PMIC_PG_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_RGS_EXT_PMIC_PG_MASK 0x1
+#define PMIC_RGS_EXT_PMIC_PG_SHIFT 6
+#define PMIC_DA_EXT_PMIC_EN1_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_DA_EXT_PMIC_EN1_MASK 0x1
+#define PMIC_DA_EXT_PMIC_EN1_SHIFT 8
+#define PMIC_DA_EXT_PMIC_EN2_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_DA_EXT_PMIC_EN2_MASK 0x1
+#define PMIC_DA_EXT_PMIC_EN2_SHIFT 9
+#define PMIC_RG_EXT_PMIC_PG_DEBTD_ADDR \
+ MT6389_STRUP_CON5
+#define PMIC_RG_EXT_PMIC_PG_DEBTD_MASK 0x1
+#define PMIC_RG_EXT_PMIC_PG_DEBTD_SHIFT 10
+#define PMIC_RG_RTC_SPAR_DEB_EN_ADDR \
+ MT6389_STRUP_CON19
+#define PMIC_RG_RTC_SPAR_DEB_EN_MASK 0x1
+#define PMIC_RG_RTC_SPAR_DEB_EN_SHIFT 8
+#define PMIC_RG_RTC_ALARM_DEB_EN_ADDR \
+ MT6389_STRUP_CON19
+#define PMIC_RG_RTC_ALARM_DEB_EN_MASK 0x1
+#define PMIC_RG_RTC_ALARM_DEB_EN_SHIFT 9
+#define PMIC_RG_STRUP_VIO33_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VIO33_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VIO33_PG_H2L_EN_SHIFT 0
+#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_SHIFT 1
+#define PMIC_RG_STRUP_VIO18_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VIO18_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VIO18_PG_H2L_EN_SHIFT 2
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_SHIFT 3
+#define PMIC_RG_STRUP_VPROC_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VPROC_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VPROC_PG_H2L_EN_SHIFT 4
+#define PMIC_RG_STRUP_VA12_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VA12_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VA12_PG_H2L_EN_SHIFT 5
+#define PMIC_RG_STRUP_VA09_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VA09_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VA09_PG_H2L_EN_SHIFT 6
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_SHIFT 7
+#define PMIC_RG_STRUP_VBBCK_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VBBCK_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VBBCK_PG_H2L_EN_SHIFT 8
+#define PMIC_RG_STRUP_VRFCK_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VRFCK_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VRFCK_PG_H2L_EN_SHIFT 9
+#define PMIC_RG_STRUP_VS1_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VS1_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VS1_PG_H2L_EN_SHIFT 10
+#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_SHIFT 11
+#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_SHIFT 12
+#define PMIC_RG_STRUP_VS2_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VS2_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VS2_PG_H2L_EN_SHIFT 13
+#define PMIC_RG_STRUP_VRTC_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VRTC_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VRTC_PG_H2L_EN_SHIFT 14
+#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB0
+#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_SHIFT 15
+#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB1
+#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_SHIFT 12
+#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB1
+#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_SHIFT 13
+#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB1
+#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_SHIFT 14
+#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_ADDR \
+ MT6389_STRUP_PGDEB1
+#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_SHIFT 15
+#define PMIC_RG_STRUP_RSV0_00_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_00_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_00_ENB_SHIFT 0
+#define PMIC_RG_STRUP_RSV0_01_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_01_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_01_ENB_SHIFT 1
+#define PMIC_RG_STRUP_RSV0_02_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_02_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_02_ENB_SHIFT 2
+#define PMIC_RG_STRUP_RSV0_03_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_03_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_03_ENB_SHIFT 3
+#define PMIC_RG_STRUP_RSV0_04_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_04_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_04_ENB_SHIFT 4
+#define PMIC_RG_STRUP_RSV0_05_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_05_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_05_ENB_SHIFT 5
+#define PMIC_RG_STRUP_RSV0_06_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_06_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_06_ENB_SHIFT 6
+#define PMIC_RG_STRUP_RSV0_07_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_07_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_07_ENB_SHIFT 7
+#define PMIC_RG_STRUP_RSV0_08_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_08_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_08_ENB_SHIFT 8
+#define PMIC_RG_STRUP_RSV0_09_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_09_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_09_ENB_SHIFT 9
+#define PMIC_RG_STRUP_RSV0_10_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_10_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_10_ENB_SHIFT 10
+#define PMIC_RG_STRUP_RSV0_11_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_11_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_11_ENB_SHIFT 11
+#define PMIC_RG_STRUP_RSV0_12_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_12_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_12_ENB_SHIFT 12
+#define PMIC_RG_STRUP_RSV0_13_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_13_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_13_ENB_SHIFT 13
+#define PMIC_RG_STRUP_RSV0_14_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_14_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_14_ENB_SHIFT 14
+#define PMIC_RG_STRUP_RSV0_15_ENB_ADDR \
+ MT6389_STRUP_PGENB0
+#define PMIC_RG_STRUP_RSV0_15_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_15_ENB_SHIFT 15
+#define PMIC_RG_STRUP_RSV0_20_ENB_ADDR \
+ MT6389_STRUP_PGENB1
+#define PMIC_RG_STRUP_RSV0_20_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_20_ENB_SHIFT 11
+#define PMIC_RG_STRUP_RSV0_19_ENB_ADDR \
+ MT6389_STRUP_PGENB1
+#define PMIC_RG_STRUP_RSV0_19_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_19_ENB_SHIFT 12
+#define PMIC_RG_STRUP_RSV0_18_ENB_ADDR \
+ MT6389_STRUP_PGENB1
+#define PMIC_RG_STRUP_RSV0_18_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_18_ENB_SHIFT 13
+#define PMIC_RG_STRUP_RSV0_17_ENB_ADDR \
+ MT6389_STRUP_PGENB1
+#define PMIC_RG_STRUP_RSV0_17_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_17_ENB_SHIFT 14
+#define PMIC_RG_STRUP_RSV0_16_ENB_ADDR \
+ MT6389_STRUP_PGENB1
+#define PMIC_RG_STRUP_RSV0_16_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV0_16_ENB_SHIFT 15
+#define PMIC_RG_STRUP_RSV1_00_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_00_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_00_ENB_SHIFT 0
+#define PMIC_RG_STRUP_RSV1_01_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_01_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_01_ENB_SHIFT 1
+#define PMIC_RG_STRUP_RSV1_02_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_02_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_02_ENB_SHIFT 2
+#define PMIC_RG_STRUP_VPROC_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VPROC_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VPROC_OC_ENB_SHIFT 3
+#define PMIC_RG_STRUP_RSV1_04_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_04_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_04_ENB_SHIFT 4
+#define PMIC_RG_STRUP_RSV1_05_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_05_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_05_ENB_SHIFT 5
+#define PMIC_RG_STRUP_VSRAM_OTHERS_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VSRAM_OTHERS_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_OTHERS_OC_ENB_SHIFT 6
+#define PMIC_RG_STRUP_RSV1_07_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_07_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_07_ENB_SHIFT 7
+#define PMIC_RG_STRUP_RSV1_08_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_08_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_08_ENB_SHIFT 8
+#define PMIC_RG_STRUP_VS1_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VS1_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VS1_OC_ENB_SHIFT 9
+#define PMIC_RG_STRUP_VMODEM_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VMODEM_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VMODEM_OC_ENB_SHIFT 10
+#define PMIC_RG_STRUP_VCORE_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VCORE_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VCORE_OC_ENB_SHIFT 11
+#define PMIC_RG_STRUP_VS2_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VS2_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VS2_OC_ENB_SHIFT 12
+#define PMIC_RG_STRUP_VRTC_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_VRTC_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VRTC_OC_ENB_SHIFT 13
+#define PMIC_RG_STRUP_RSV1_14_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_14_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_14_ENB_SHIFT 14
+#define PMIC_RG_STRUP_RSV1_15_ENB_ADDR \
+ MT6389_STRUP_OCENB0
+#define PMIC_RG_STRUP_RSV1_15_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_15_ENB_SHIFT 15
+#define PMIC_RG_STRUP_RSV1_19_ENB_ADDR \
+ MT6389_STRUP_OCENB1
+#define PMIC_RG_STRUP_RSV1_19_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_19_ENB_SHIFT 11
+#define PMIC_RG_STRUP_RSV1_18_ENB_ADDR \
+ MT6389_STRUP_OCENB1
+#define PMIC_RG_STRUP_RSV1_18_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_18_ENB_SHIFT 12
+#define PMIC_RG_STRUP_RSV1_17_ENB_ADDR \
+ MT6389_STRUP_OCENB1
+#define PMIC_RG_STRUP_RSV1_17_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_17_ENB_SHIFT 13
+#define PMIC_RG_STRUP_VDRAM1_OC_ENB_ADDR \
+ MT6389_STRUP_OCENB1
+#define PMIC_RG_STRUP_VDRAM1_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM1_OC_ENB_SHIFT 14
+#define PMIC_RG_STRUP_RSV1_16_ENB_ADDR \
+ MT6389_STRUP_OCENB1
+#define PMIC_RG_STRUP_RSV1_16_ENB_MASK 0x1
+#define PMIC_RG_STRUP_RSV1_16_ENB_SHIFT 15
+#define PMIC_RG_PSEQ_FORCE_ON_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_FORCE_ON_MASK 0x1
+#define PMIC_RG_PSEQ_FORCE_ON_SHIFT 0
+#define PMIC_RG_PSEQ_FORCE_TEST_EN_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_FORCE_TEST_EN_MASK 0x1
+#define PMIC_RG_PSEQ_FORCE_TEST_EN_SHIFT 1
+#define PMIC_RG_PSEQ_BYPASS_DEB_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_BYPASS_DEB_MASK 0x1
+#define PMIC_RG_PSEQ_BYPASS_DEB_SHIFT 4
+#define PMIC_RG_PSEQ_BYPASS_SEQ_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_BYPASS_SEQ_MASK 0x1
+#define PMIC_RG_PSEQ_BYPASS_SEQ_SHIFT 5
+#define PMIC_RG_PSEQ_LPBWDT_ACC_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_LPBWDT_ACC_MASK 0x1
+#define PMIC_RG_PSEQ_LPBWDT_ACC_SHIFT 6
+#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_ADDR \
+ MT6389_PPCTST0
+#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_MASK 0x1
+#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_SHIFT 8
+#define PMIC_RG_PSEQ_PG_CK_SEL_ADDR \
+ MT6389_PPCCTL2
+#define PMIC_RG_PSEQ_PG_CK_SEL_MASK 0x1
+#define PMIC_RG_PSEQ_PG_CK_SEL_SHIFT 0
+#define PMIC_RG_THM_SHDN_EN_ADDR \
+ MT6389_PPCCTL2
+#define PMIC_RG_THM_SHDN_EN_MASK 0x1
+#define PMIC_RG_THM_SHDN_EN_SHIFT 8
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_ADDR \
+ MT6389_STRUP_CON10
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_MASK 0x1
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SHIFT 0
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_ADDR \
+ MT6389_STRUP_CON10
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK 0x1
+#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT 1
+#define PMIC_RG_THR_TEST_ADDR \
+ MT6389_STRUP_CON10
+#define PMIC_RG_THR_TEST_MASK 0x3
+#define PMIC_RG_THR_TEST_SHIFT 12
+#define PMIC_RG_STRUP_ENVTEM_ADDR \
+ MT6389_STRUP_CON10
+#define PMIC_RG_STRUP_ENVTEM_MASK 0x1
+#define PMIC_RG_STRUP_ENVTEM_SHIFT 14
+#define PMIC_RG_STRUP_ENVTEM_CTRL_ADDR \
+ MT6389_STRUP_CON10
+#define PMIC_RG_STRUP_ENVTEM_CTRL_MASK 0x1
+#define PMIC_RG_STRUP_ENVTEM_CTRL_SHIFT 15
+#define PMIC_DDUVLO_DEB_EN_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_DDUVLO_DEB_EN_MASK 0x1
+#define PMIC_DDUVLO_DEB_EN_SHIFT 4
+#define PMIC_RG_STRUP_FT_CTRL_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_STRUP_FT_CTRL_MASK 0x3
+#define PMIC_RG_STRUP_FT_CTRL_SHIFT 5
+#define PMIC_RG_BIASGEN_FORCE_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_BIASGEN_FORCE_MASK 0x1
+#define PMIC_RG_BIASGEN_FORCE_SHIFT 8
+#define PMIC_RG_STRUP_PWRON_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_STRUP_PWRON_MASK 0x1
+#define PMIC_RG_STRUP_PWRON_SHIFT 9
+#define PMIC_RG_STRUP_PWRON_SEL_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_STRUP_PWRON_SEL_MASK 0x1
+#define PMIC_RG_STRUP_PWRON_SEL_SHIFT 10
+#define PMIC_RG_BIASGEN_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_BIASGEN_MASK 0x1
+#define PMIC_RG_BIASGEN_SHIFT 11
+#define PMIC_RG_BIASGEN_SEL_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_BIASGEN_SEL_MASK 0x1
+#define PMIC_RG_BIASGEN_SEL_SHIFT 12
+#define PMIC_RG_DCXO_PMU_CKEN_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_DCXO_PMU_CKEN_MASK 0x1
+#define PMIC_RG_DCXO_PMU_CKEN_SHIFT 13
+#define PMIC_RG_DCXO_PMU_CKEN_SEL_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_RG_DCXO_PMU_CKEN_SEL_MASK 0x1
+#define PMIC_RG_DCXO_PMU_CKEN_SEL_SHIFT 14
+#define PMIC_STRUP_DIG_IO_PG_FORCE_ADDR \
+ MT6389_STRUP_CON3
+#define PMIC_STRUP_DIG_IO_PG_FORCE_MASK 0x1
+#define PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT 15
+#define PMIC_RG_ATST_PG_CHK_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_ATST_PG_CHK_MASK 0x1
+#define PMIC_RG_ATST_PG_CHK_SHIFT 0
+#define PMIC_RG_STRUP_PG_DEB_MODE_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_STRUP_PG_DEB_MODE_MASK 0x1
+#define PMIC_RG_STRUP_PG_DEB_MODE_SHIFT 1
+#define PMIC_RG_OVLO_FCMPL_SW_SEL_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_OVLO_FCMPL_SW_SEL_MASK 0x1
+#define PMIC_RG_OVLO_FCMPL_SW_SEL_SHIFT 2
+#define PMIC_RG_OVLO_FCMPL_SW_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_OVLO_FCMPL_SW_MASK 0x1
+#define PMIC_RG_OVLO_FCMPL_SW_SHIFT 3
+#define PMIC_RG_UVLO_VSYS_VTH_SW_SEL_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_UVLO_VSYS_VTH_SW_SEL_MASK 0x1
+#define PMIC_RG_UVLO_VSYS_VTH_SW_SEL_SHIFT 4
+#define PMIC_RG_UVLO_VSYS_VTH_SW_ADDR \
+ MT6389_STRUP_CON6
+#define PMIC_RG_UVLO_VSYS_VTH_SW_MASK 0x1
+#define PMIC_RG_UVLO_VSYS_VTH_SW_SHIFT 5
+#define PMIC_RG_STATUS_B_ADDR \
+ MT6389_TPO_CON0
+#define PMIC_RG_STATUS_B_MASK 0x1
+#define PMIC_RG_STATUS_B_SHIFT 0
+#define PMIC_RG_TPO_REF_ENB_ADDR \
+ MT6389_TPO_CON1
+#define PMIC_RG_TPO_REF_ENB_MASK 0x1
+#define PMIC_RG_TPO_REF_ENB_SHIFT 0
+#define PMIC_RG_TPO_REF_ENB_SW_MODE_ADDR \
+ MT6389_TPO_CON1
+#define PMIC_RG_TPO_REF_ENB_SW_MODE_MASK 0x1
+#define PMIC_RG_TPO_REF_ENB_SW_MODE_SHIFT 1
+#define PMIC_RG_BYPASS_CLROC_ADDR \
+ MT6389_TPO_CON1
+#define PMIC_RG_BYPASS_CLROC_MASK 0x1
+#define PMIC_RG_BYPASS_CLROC_SHIFT 2
+#define PMIC_RG_PMIC_ENB_DEB_SEL_ADDR \
+ MT6389_TPO_CON2
+#define PMIC_RG_PMIC_ENB_DEB_SEL_MASK 0x3
+#define PMIC_RG_PMIC_ENB_DEB_SEL_SHIFT 0
+#define PMIC_RG_PMIC_ENB_DLY_SEL_ADDR \
+ MT6389_TPO_CON2
+#define PMIC_RG_PMIC_ENB_DLY_SEL_MASK 0x3
+#define PMIC_RG_PMIC_ENB_DLY_SEL_SHIFT 2
+#define PMIC_RG_PMIC_RESET_B_DEB_SEL_ADDR \
+ MT6389_TPO_CON2
+#define PMIC_RG_PMIC_RESET_B_DEB_SEL_MASK 0x3
+#define PMIC_RG_PMIC_RESET_B_DEB_SEL_SHIFT 4
+#define PMIC_RG_PMIC_RESET_B_DLY_SEL_ADDR \
+ MT6389_TPO_CON2
+#define PMIC_RG_PMIC_RESET_B_DLY_SEL_MASK 0x3
+#define PMIC_RG_PMIC_RESET_B_DLY_SEL_SHIFT 6
+#define PMIC_RG_CPS_W_KEY_ADDR \
+ MT6389_CPSWKEY
+#define PMIC_RG_CPS_W_KEY_MASK 0xFFFF
+#define PMIC_RG_CPS_W_KEY_SHIFT 0
+#define PMIC_RG_SLOT_INTV_DOWN_ADDR \
+ MT6389_CPSCFG0
+#define PMIC_RG_SLOT_INTV_DOWN_MASK 0x3
+#define PMIC_RG_SLOT_INTV_DOWN_SHIFT 0
+#define PMIC_RG_DSEQ_LEN_ADDR \
+ MT6389_CPSCFG0
+#define PMIC_RG_DSEQ_LEN_MASK 0x1F
+#define PMIC_RG_DSEQ_LEN_SHIFT 8
+#define PMIC_RG_VXO22_DSA_ADDR \
+ MT6389_CPSDSA0
+#define PMIC_RG_VXO22_DSA_MASK 0x1F
+#define PMIC_RG_VXO22_DSA_SHIFT 0
+#define PMIC_RG_VAUX18_DSA_ADDR \
+ MT6389_CPSDSA0
+#define PMIC_RG_VAUX18_DSA_MASK 0x1F
+#define PMIC_RG_VAUX18_DSA_SHIFT 5
+#define PMIC_RG_VRTC_DSA_ADDR \
+ MT6389_CPSDSA0
+#define PMIC_RG_VRTC_DSA_MASK 0x1F
+#define PMIC_RG_VRTC_DSA_SHIFT 10
+#define PMIC_RG_VS2_DSA_ADDR \
+ MT6389_CPSDSA1
+#define PMIC_RG_VS2_DSA_MASK 0x1F
+#define PMIC_RG_VS2_DSA_SHIFT 0
+#define PMIC_RG_VCORE_DSA_ADDR \
+ MT6389_CPSDSA1
+#define PMIC_RG_VCORE_DSA_MASK 0x1F
+#define PMIC_RG_VCORE_DSA_SHIFT 5
+#define PMIC_RG_VMODEM_DSA_ADDR \
+ MT6389_CPSDSA1
+#define PMIC_RG_VMODEM_DSA_MASK 0x1F
+#define PMIC_RG_VMODEM_DSA_SHIFT 10
+#define PMIC_RG_VS1_DSA_ADDR \
+ MT6389_CPSDSA2
+#define PMIC_RG_VS1_DSA_MASK 0x1F
+#define PMIC_RG_VS1_DSA_SHIFT 0
+#define PMIC_RG_VRFCK_DSA_ADDR \
+ MT6389_CPSDSA2
+#define PMIC_RG_VRFCK_DSA_MASK 0x1F
+#define PMIC_RG_VRFCK_DSA_SHIFT 5
+#define PMIC_RG_VBBCK_DSA_ADDR \
+ MT6389_CPSDSA2
+#define PMIC_RG_VBBCK_DSA_MASK 0x1F
+#define PMIC_RG_VBBCK_DSA_SHIFT 10
+#define PMIC_RG_VSRAM_OTHERS_DSA_ADDR \
+ MT6389_CPSDSA3
+#define PMIC_RG_VSRAM_OTHERS_DSA_MASK 0x1F
+#define PMIC_RG_VSRAM_OTHERS_DSA_SHIFT 0
+#define PMIC_RG_VA09_DSA_ADDR \
+ MT6389_CPSDSA3
+#define PMIC_RG_VA09_DSA_MASK 0x1F
+#define PMIC_RG_VA09_DSA_SHIFT 5
+#define PMIC_RG_VA12_DSA_ADDR \
+ MT6389_CPSDSA3
+#define PMIC_RG_VA12_DSA_MASK 0x1F
+#define PMIC_RG_VA12_DSA_SHIFT 10
+#define PMIC_RG_VPROC_DSA_ADDR \
+ MT6389_CPSDSA4
+#define PMIC_RG_VPROC_DSA_MASK 0x1F
+#define PMIC_RG_VPROC_DSA_SHIFT 0
+#define PMIC_RG_VSRAM_PROC_DSA_ADDR \
+ MT6389_CPSDSA4
+#define PMIC_RG_VSRAM_PROC_DSA_MASK 0x1F
+#define PMIC_RG_VSRAM_PROC_DSA_SHIFT 5
+#define PMIC_RG_VIO18_DSA_ADDR \
+ MT6389_CPSDSA4
+#define PMIC_RG_VIO18_DSA_MASK 0x1F
+#define PMIC_RG_VIO18_DSA_SHIFT 10
+#define PMIC_RG_VEMC_DSA_ADDR \
+ MT6389_CPSDSA5
+#define PMIC_RG_VEMC_DSA_MASK 0x1F
+#define PMIC_RG_VEMC_DSA_SHIFT 0
+#define PMIC_RG_VIO33_DSA_ADDR \
+ MT6389_CPSDSA5
+#define PMIC_RG_VIO33_DSA_MASK 0x1F
+#define PMIC_RG_VIO33_DSA_SHIFT 5
+#define PMIC_RG_VDRAM1_DSA_ADDR \
+ MT6389_CPSDSA5
+#define PMIC_RG_VDRAM1_DSA_MASK 0x1F
+#define PMIC_RG_VDRAM1_DSA_SHIFT 10
+#define PMIC_RG_VDRAM2_DSA_ADDR \
+ MT6389_CPSDSA6
+#define PMIC_RG_VDRAM2_DSA_MASK 0x1F
+#define PMIC_RG_VDRAM2_DSA_SHIFT 0
+#define PMIC_RG_VUSB_DSA_ADDR \
+ MT6389_CPSDSA6
+#define PMIC_RG_VUSB_DSA_MASK 0x1F
+#define PMIC_RG_VUSB_DSA_SHIFT 5
+#define PMIC_RG_VAUD28_DSA_ADDR \
+ MT6389_CPSDSA6
+#define PMIC_RG_VAUD28_DSA_MASK 0x1F
+#define PMIC_RG_VAUD28_DSA_SHIFT 10
+#define PMIC_PSEQ_ELR_LEN_ADDR \
+ MT6389_PSEQ_ELR_NUM
+#define PMIC_PSEQ_ELR_LEN_MASK 0xFF
+#define PMIC_PSEQ_ELR_LEN_SHIFT 0
+#define PMIC_RG_BWDT_EN_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_BWDT_EN_MASK 0x1
+#define PMIC_RG_BWDT_EN_SHIFT 0
+#define PMIC_RG_BWDT_TSEL_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_BWDT_TSEL_MASK 0x1
+#define PMIC_RG_BWDT_TSEL_SHIFT 1
+#define PMIC_RG_PSEQ_ELR_RSV1_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_PSEQ_ELR_RSV1_MASK 0x1
+#define PMIC_RG_PSEQ_ELR_RSV1_SHIFT 2
+#define PMIC_RG_BWDT_TD_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_BWDT_TD_MASK 0x3
+#define PMIC_RG_BWDT_TD_SHIFT 3
+#define PMIC_RG_BWDT_CHRTD_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_BWDT_CHRTD_MASK 0x1
+#define PMIC_RG_BWDT_CHRTD_SHIFT 5
+#define PMIC_RG_BWDT_DDLO_TD_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_BWDT_DDLO_TD_MASK 0x3
+#define PMIC_RG_BWDT_DDLO_TD_SHIFT 6
+#define PMIC_RG_SLOT_INTV_UP_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_SLOT_INTV_UP_MASK 0x3
+#define PMIC_RG_SLOT_INTV_UP_SHIFT 8
+#define PMIC_RG_SEQ_LEN_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_SEQ_LEN_MASK 0x1F
+#define PMIC_RG_SEQ_LEN_SHIFT 10
+#define PMIC_RG_PSEQ_ELR_RSV0_ADDR \
+ MT6389_PSEQ_ELR0
+#define PMIC_RG_PSEQ_ELR_RSV0_MASK 0x1
+#define PMIC_RG_PSEQ_ELR_RSV0_SHIFT 15
+#define PMIC_RG_PSPG_SHDN_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_PSPG_SHDN_ENB_MASK 0x3
+#define PMIC_RG_PSPG_SHDN_ENB_SHIFT 0
+#define PMIC_RG_PSEQ_F32K_FORCE_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_PSEQ_F32K_FORCE_MASK 0x1
+#define PMIC_RG_PSEQ_F32K_FORCE_SHIFT 2
+#define PMIC_RG_STRUP_VDRAM1_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_STRUP_VDRAM1_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM1_PG_ENB_SHIFT 3
+#define PMIC_RG_SMPS_IVGEN_SEL_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_SMPS_IVGEN_SEL_MASK 0x1
+#define PMIC_RG_SMPS_IVGEN_SEL_SHIFT 4
+#define PMIC_RG_CPS_S0EXT_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_CPS_S0EXT_ENB_MASK 0x1
+#define PMIC_RG_CPS_S0EXT_ENB_SHIFT 6
+#define PMIC_RG_CPS_S0EXT_TD_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_CPS_S0EXT_TD_MASK 0x1
+#define PMIC_RG_CPS_S0EXT_TD_SHIFT 7
+#define PMIC_RG_SDN_DLY_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_SDN_DLY_ENB_MASK 0x1
+#define PMIC_RG_SDN_DLY_ENB_SHIFT 8
+#define PMIC_RG_STRUP_VDRAM2_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_STRUP_VDRAM2_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM2_PG_ENB_SHIFT 9
+#define PMIC_RG_LDO_PG_STB_MODE_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_LDO_PG_STB_MODE_MASK 0x1
+#define PMIC_RG_LDO_PG_STB_MODE_SHIFT 12
+#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_SHIFT 13
+#define PMIC_RG_PROTECT_DIS_ADDR \
+ MT6389_PSEQ_ELR1
+#define PMIC_RG_PROTECT_DIS_MASK 0x1
+#define PMIC_RG_PROTECT_DIS_SHIFT 14
+#define PMIC_RG_STRUP_VEMC_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VEMC_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VEMC_PG_ENB_SHIFT 0
+#define PMIC_RG_STRUP_VIO18_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VIO18_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VIO18_PG_ENB_SHIFT 1
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_SHIFT 2
+#define PMIC_RG_STRUP_VPROC_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VPROC_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VPROC_PG_ENB_SHIFT 3
+#define PMIC_RG_STRUP_VA12_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VA12_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VA12_PG_ENB_SHIFT 4
+#define PMIC_RG_STRUP_VA09_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VA09_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VA09_PG_ENB_SHIFT 5
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_SHIFT 6
+#define PMIC_RG_STRUP_VBBCK_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VBBCK_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VBBCK_PG_ENB_SHIFT 7
+#define PMIC_RG_STRUP_VRFCK_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VRFCK_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VRFCK_PG_ENB_SHIFT 8
+#define PMIC_RG_STRUP_VS1_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VS1_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VS1_PG_ENB_SHIFT 9
+#define PMIC_RG_STRUP_VMODEM_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VMODEM_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VMODEM_PG_ENB_SHIFT 10
+#define PMIC_RG_STRUP_VCORE_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VCORE_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VCORE_PG_ENB_SHIFT 11
+#define PMIC_RG_STRUP_VS2_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VS2_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VS2_PG_ENB_SHIFT 12
+#define PMIC_RG_STRUP_VRTC_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VRTC_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VRTC_PG_ENB_SHIFT 13
+#define PMIC_RG_STRUP_VAUX18_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VAUX18_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VAUX18_PG_ENB_SHIFT 14
+#define PMIC_RG_STRUP_VXO22_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR2
+#define PMIC_RG_STRUP_VXO22_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VXO22_PG_ENB_SHIFT 15
+#define PMIC_RG_STRUP_VEMC_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VEMC_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VEMC_OC_ENB_SHIFT 0
+#define PMIC_RG_STRUP_VIO18_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VIO18_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VIO18_OC_ENB_SHIFT 1
+#define PMIC_RG_STRUP_VSRAM_PROC_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VSRAM_PROC_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VSRAM_PROC_OC_ENB_SHIFT 2
+#define PMIC_RG_STRUP_VAUX18_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VAUX18_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VAUX18_OC_ENB_SHIFT 3
+#define PMIC_RG_STRUP_VA12_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VA12_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VA12_OC_ENB_SHIFT 4
+#define PMIC_RG_STRUP_VA09_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VA09_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VA09_OC_ENB_SHIFT 5
+#define PMIC_RG_STRUP_VXO22_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VXO22_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VXO22_OC_ENB_SHIFT 6
+#define PMIC_RG_STRUP_VBBCK_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VBBCK_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VBBCK_OC_ENB_SHIFT 7
+#define PMIC_RG_STRUP_VRFCK_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VRFCK_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VRFCK_OC_ENB_SHIFT 8
+#define PMIC_RG_STRUP_VAUD28_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VAUD28_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VAUD28_OC_ENB_SHIFT 9
+#define PMIC_RG_STRUP_VUSB_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VUSB_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VUSB_OC_ENB_SHIFT 10
+#define PMIC_RG_STRUP_VDRAM2_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VDRAM2_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VDRAM2_OC_ENB_SHIFT 11
+#define PMIC_RG_STRUP_VIO33_OC_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VIO33_OC_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VIO33_OC_ENB_SHIFT 12
+#define PMIC_RG_STRUP_VUSB_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VUSB_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VUSB_PG_ENB_SHIFT 13
+#define PMIC_RG_STRUP_VIO33_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VIO33_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VIO33_PG_ENB_SHIFT 14
+#define PMIC_RG_STRUP_VAUD28_PG_ENB_ADDR \
+ MT6389_PSEQ_ELR3
+#define PMIC_RG_STRUP_VAUD28_PG_ENB_MASK 0x1
+#define PMIC_RG_STRUP_VAUD28_PG_ENB_SHIFT 15
+#define PMIC_RG_VXO22_USA_ADDR \
+ MT6389_CPSUSA_ELR0
+#define PMIC_RG_VXO22_USA_MASK 0x1F
+#define PMIC_RG_VXO22_USA_SHIFT 0
+#define PMIC_RG_VAUX18_USA_ADDR \
+ MT6389_CPSUSA_ELR0
+#define PMIC_RG_VAUX18_USA_MASK 0x1F
+#define PMIC_RG_VAUX18_USA_SHIFT 5
+#define PMIC_RG_VRTC_USA_ADDR \
+ MT6389_CPSUSA_ELR0
+#define PMIC_RG_VRTC_USA_MASK 0x1F
+#define PMIC_RG_VRTC_USA_SHIFT 10
+#define PMIC_RG_VS2_USA_ADDR \
+ MT6389_CPSUSA_ELR1
+#define PMIC_RG_VS2_USA_MASK 0x1F
+#define PMIC_RG_VS2_USA_SHIFT 0
+#define PMIC_RG_VCORE_USA_ADDR \
+ MT6389_CPSUSA_ELR1
+#define PMIC_RG_VCORE_USA_MASK 0x1F
+#define PMIC_RG_VCORE_USA_SHIFT 5
+#define PMIC_RG_VMODEM_USA_ADDR \
+ MT6389_CPSUSA_ELR1
+#define PMIC_RG_VMODEM_USA_MASK 0x1F
+#define PMIC_RG_VMODEM_USA_SHIFT 10
+#define PMIC_RG_VS1_USA_ADDR \
+ MT6389_CPSUSA_ELR2
+#define PMIC_RG_VS1_USA_MASK 0x1F
+#define PMIC_RG_VS1_USA_SHIFT 0
+#define PMIC_RG_VRFCK_USA_ADDR \
+ MT6389_CPSUSA_ELR2
+#define PMIC_RG_VRFCK_USA_MASK 0x1F
+#define PMIC_RG_VRFCK_USA_SHIFT 5
+#define PMIC_RG_VBBCK_USA_ADDR \
+ MT6389_CPSUSA_ELR2
+#define PMIC_RG_VBBCK_USA_MASK 0x1F
+#define PMIC_RG_VBBCK_USA_SHIFT 10
+#define PMIC_RG_VSRAM_OTHERS_USA_ADDR \
+ MT6389_CPSUSA_ELR3
+#define PMIC_RG_VSRAM_OTHERS_USA_MASK 0x1F
+#define PMIC_RG_VSRAM_OTHERS_USA_SHIFT 0
+#define PMIC_RG_VA09_USA_ADDR \
+ MT6389_CPSUSA_ELR3
+#define PMIC_RG_VA09_USA_MASK 0x1F
+#define PMIC_RG_VA09_USA_SHIFT 5
+#define PMIC_RG_VA12_USA_ADDR \
+ MT6389_CPSUSA_ELR3
+#define PMIC_RG_VA12_USA_MASK 0x1F
+#define PMIC_RG_VA12_USA_SHIFT 10
+#define PMIC_RG_VPROC_USA_ADDR \
+ MT6389_CPSUSA_ELR4
+#define PMIC_RG_VPROC_USA_MASK 0x1F
+#define PMIC_RG_VPROC_USA_SHIFT 0
+#define PMIC_RG_VSRAM_PROC_USA_ADDR \
+ MT6389_CPSUSA_ELR4
+#define PMIC_RG_VSRAM_PROC_USA_MASK 0x1F
+#define PMIC_RG_VSRAM_PROC_USA_SHIFT 5
+#define PMIC_RG_VIO18_USA_ADDR \
+ MT6389_CPSUSA_ELR4
+#define PMIC_RG_VIO18_USA_MASK 0x1F
+#define PMIC_RG_VIO18_USA_SHIFT 10
+#define PMIC_RG_VEMC_USA_ADDR \
+ MT6389_CPSUSA_ELR5
+#define PMIC_RG_VEMC_USA_MASK 0x1F
+#define PMIC_RG_VEMC_USA_SHIFT 0
+#define PMIC_RG_VIO33_USA_ADDR \
+ MT6389_CPSUSA_ELR5
+#define PMIC_RG_VIO33_USA_MASK 0x1F
+#define PMIC_RG_VIO33_USA_SHIFT 5
+#define PMIC_RG_VDRAM1_USA_ADDR \
+ MT6389_CPSUSA_ELR5
+#define PMIC_RG_VDRAM1_USA_MASK 0x1F
+#define PMIC_RG_VDRAM1_USA_SHIFT 10
+#define PMIC_RG_VDRAM2_USA_ADDR \
+ MT6389_CPSUSA_ELR6
+#define PMIC_RG_VDRAM2_USA_MASK 0x1F
+#define PMIC_RG_VDRAM2_USA_SHIFT 0
+#define PMIC_RG_VUSB_USA_ADDR \
+ MT6389_CPSUSA_ELR6
+#define PMIC_RG_VUSB_USA_MASK 0x1F
+#define PMIC_RG_VUSB_USA_SHIFT 5
+#define PMIC_RG_VAUD28_USA_ADDR \
+ MT6389_CPSUSA_ELR6
+#define PMIC_RG_VAUD28_USA_MASK 0x1F
+#define PMIC_RG_VAUD28_USA_SHIFT 10
+#define PMIC_CHRDET_ANA_ID_ADDR \
+ MT6389_CHRDET_ID
+#define PMIC_CHRDET_ANA_ID_MASK 0xFF
+#define PMIC_CHRDET_ANA_ID_SHIFT 0
+#define PMIC_CHRDET_DIG_ID_ADDR \
+ MT6389_CHRDET_ID
+#define PMIC_CHRDET_DIG_ID_MASK 0xFF
+#define PMIC_CHRDET_DIG_ID_SHIFT 8
+#define PMIC_CHRDET_ANA_MINOR_REV_ADDR \
+ MT6389_CHRDET_REV0
+#define PMIC_CHRDET_ANA_MINOR_REV_MASK 0xF
+#define PMIC_CHRDET_ANA_MINOR_REV_SHIFT 0
+#define PMIC_CHRDET_ANA_MAJOR_REV_ADDR \
+ MT6389_CHRDET_REV0
+#define PMIC_CHRDET_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_CHRDET_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_CHRDET_DIG_MINOR_REV_ADDR \
+ MT6389_CHRDET_REV0
+#define PMIC_CHRDET_DIG_MINOR_REV_MASK 0xF
+#define PMIC_CHRDET_DIG_MINOR_REV_SHIFT 8
+#define PMIC_CHRDET_DIG_MAJOR_REV_ADDR \
+ MT6389_CHRDET_REV0
+#define PMIC_CHRDET_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_CHRDET_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_CHRDET_CBS_ADDR \
+ MT6389_CHRDET_DBI
+#define PMIC_CHRDET_CBS_MASK 0x3
+#define PMIC_CHRDET_CBS_SHIFT 0
+#define PMIC_CHRDET_BIX_ADDR \
+ MT6389_CHRDET_DBI
+#define PMIC_CHRDET_BIX_MASK 0x3
+#define PMIC_CHRDET_BIX_SHIFT 2
+#define PMIC_CHRDET_ESP_ADDR \
+ MT6389_CHRDET_DBI
+#define PMIC_CHRDET_ESP_MASK 0xFF
+#define PMIC_CHRDET_ESP_SHIFT 8
+#define PMIC_CHRDET_FPI_ADDR \
+ MT6389_CHRDET_DXI
+#define PMIC_CHRDET_FPI_MASK 0xFF
+#define PMIC_CHRDET_FPI_SHIFT 0
+#define PMIC_RG_BGR_TEST_RSTB_ADDR \
+ MT6389_PCHR_VREF_ANA_CON0
+#define PMIC_RG_BGR_TEST_RSTB_MASK 0x1
+#define PMIC_RG_BGR_TEST_RSTB_SHIFT 1
+#define PMIC_RG_BGR_TEST_EN_ADDR \
+ MT6389_PCHR_VREF_ANA_CON0
+#define PMIC_RG_BGR_TEST_EN_MASK 0x1
+#define PMIC_RG_BGR_TEST_EN_SHIFT 2
+#define PMIC_RG_BGR_UNCHOP_ADDR \
+ MT6389_PCHR_VREF_ANA_CON1
+#define PMIC_RG_BGR_UNCHOP_MASK 0x1
+#define PMIC_RG_BGR_UNCHOP_SHIFT 0
+#define PMIC_RG_BGR_UNCHOP_PH_ADDR \
+ MT6389_PCHR_VREF_ANA_CON1
+#define PMIC_RG_BGR_UNCHOP_PH_MASK 0x1
+#define PMIC_RG_BGR_UNCHOP_PH_SHIFT 1
+#define PMIC_RG_UVLO_VTHL_ADDR \
+ MT6389_PCHR_VREF_ANA_CON1
+#define PMIC_RG_UVLO_VTHL_MASK 0x1F
+#define PMIC_RG_UVLO_VTHL_SHIFT 2
+#define PMIC_RG_OVLO_VTH_SEL_ADDR \
+ MT6389_PCHR_VREF_ANA_CON1
+#define PMIC_RG_OVLO_VTH_SEL_MASK 0x7
+#define PMIC_RG_OVLO_VTH_SEL_SHIFT 8
+#define PMIC_RG_LBAT_INT_VTH_ADDR \
+ MT6389_PCHR_VREF_ANA_CON2
+#define PMIC_RG_LBAT_INT_VTH_MASK 0x1F
+#define PMIC_RG_LBAT_INT_VTH_SHIFT 0
+#define PMIC_RG_PCHR_RV_ADDR \
+ MT6389_PCHR_VREF_ANA_CON3
+#define PMIC_RG_PCHR_RV_MASK 0xF
+#define PMIC_RG_PCHR_RV_SHIFT 0
+#define PMIC_RG_VCDT_EN_ADDR \
+ MT6389_PCHR_VREF_ANA_CON3
+#define PMIC_RG_VCDT_EN_MASK 0x1
+#define PMIC_RG_VCDT_EN_SHIFT 4
+#define PMIC_CHRDET_ELR_LEN_ADDR \
+ MT6389_PCHR_VREF_ELR_NUM
+#define PMIC_CHRDET_ELR_LEN_MASK 0xFF
+#define PMIC_CHRDET_ELR_LEN_SHIFT 0
+#define PMIC_RG_BGR_TRIM_ADDR \
+ MT6389_PCHR_VREF_ELR_0
+#define PMIC_RG_BGR_TRIM_MASK 0x3F
+#define PMIC_RG_BGR_TRIM_SHIFT 0
+#define PMIC_RG_BGR_TRIM_EN_ADDR \
+ MT6389_PCHR_VREF_ELR_0
+#define PMIC_RG_BGR_TRIM_EN_MASK 0x1
+#define PMIC_RG_BGR_TRIM_EN_SHIFT 8
+#define PMIC_RG_BGR_RSEL_ADDR \
+ MT6389_PCHR_VREF_ELR_0
+#define PMIC_RG_BGR_RSEL_MASK 0x1F
+#define PMIC_RG_BGR_RSEL_SHIFT 9
+#define PMIC_RG_OVLO_EN_ADDR \
+ MT6389_PCHR_VREF_ELR_1
+#define PMIC_RG_OVLO_EN_MASK 0x1
+#define PMIC_RG_OVLO_EN_SHIFT 0
+#define PMIC_RG_VCDT_VTH_TRIM_ADDR \
+ MT6389_PCHR_VREF_ELR_1
+#define PMIC_RG_VCDT_VTH_TRIM_MASK 0xFF
+#define PMIC_RG_VCDT_VTH_TRIM_SHIFT 8
+#define PMIC_HK_TOP_ANA_ID_ADDR \
+ MT6389_HK_TOP_ID
+#define PMIC_HK_TOP_ANA_ID_MASK 0xFF
+#define PMIC_HK_TOP_ANA_ID_SHIFT 0
+#define PMIC_HK_TOP_DIG_ID_ADDR \
+ MT6389_HK_TOP_ID
+#define PMIC_HK_TOP_DIG_ID_MASK 0xFF
+#define PMIC_HK_TOP_DIG_ID_SHIFT 8
+#define PMIC_HK_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_HK_TOP_REV0
+#define PMIC_HK_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_HK_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_HK_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_HK_TOP_REV0
+#define PMIC_HK_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_HK_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_HK_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_HK_TOP_REV0
+#define PMIC_HK_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_HK_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_HK_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_HK_TOP_REV0
+#define PMIC_HK_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_HK_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_HK_TOP_CBS_ADDR \
+ MT6389_HK_TOP_DBI
+#define PMIC_HK_TOP_CBS_MASK 0x3
+#define PMIC_HK_TOP_CBS_SHIFT 0
+#define PMIC_HK_TOP_BIX_ADDR \
+ MT6389_HK_TOP_DBI
+#define PMIC_HK_TOP_BIX_MASK 0x3
+#define PMIC_HK_TOP_BIX_SHIFT 2
+#define PMIC_HK_TOP_ESP_ADDR \
+ MT6389_HK_TOP_DBI
+#define PMIC_HK_TOP_ESP_MASK 0xFF
+#define PMIC_HK_TOP_ESP_SHIFT 8
+#define PMIC_HK_TOP_FPI_ADDR \
+ MT6389_HK_TOP_DXI
+#define PMIC_HK_TOP_FPI_MASK 0xFF
+#define PMIC_HK_TOP_FPI_SHIFT 0
+#define PMIC_HK_CLK_OFFSET_ADDR \
+ MT6389_HK_TPM0
+#define PMIC_HK_CLK_OFFSET_MASK 0xFF
+#define PMIC_HK_CLK_OFFSET_SHIFT 0
+#define PMIC_HK_RST_OFFSET_ADDR \
+ MT6389_HK_TPM0
+#define PMIC_HK_RST_OFFSET_MASK 0xFF
+#define PMIC_HK_RST_OFFSET_SHIFT 8
+#define PMIC_HK_INT_OFFSET_ADDR \
+ MT6389_HK_TPM1
+#define PMIC_HK_INT_OFFSET_MASK 0xFF
+#define PMIC_HK_INT_OFFSET_SHIFT 0
+#define PMIC_HK_INT_LEN_ADDR \
+ MT6389_HK_TPM1
+#define PMIC_HK_INT_LEN_MASK 0xFF
+#define PMIC_HK_INT_LEN_SHIFT 8
+#define PMIC_RG_AUXADC_26M_CK_PDN_HWEN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_26M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_AUXADC_26M_CK_PDN_HWEN_SHIFT 0
+#define PMIC_RG_AUXADC_26M_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_26M_CK_PDN_MASK 0x1
+#define PMIC_RG_AUXADC_26M_CK_PDN_SHIFT 1
+#define PMIC_RG_AUXADC_CK_PDN_HWEN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_AUXADC_CK_PDN_HWEN_SHIFT 2
+#define PMIC_RG_AUXADC_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_CK_PDN_MASK 0x1
+#define PMIC_RG_AUXADC_CK_PDN_SHIFT 3
+#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_SHIFT 4
+#define PMIC_RG_AUXADC_RNG_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_RNG_CK_PDN_MASK 0x1
+#define PMIC_RG_AUXADC_RNG_CK_PDN_SHIFT 5
+#define PMIC_RG_AUXADC_1M_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_1M_CK_PDN_MASK 0x1
+#define PMIC_RG_AUXADC_1M_CK_PDN_SHIFT 6
+#define PMIC_RG_AUXADC_32K_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_AUXADC_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_AUXADC_32K_CK_PDN_SHIFT 7
+#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_SHIFT 8
+#define PMIC_RG_HK_INTRP_CK_PDN_ADDR \
+ MT6389_HK_TOP_CLK_CON0
+#define PMIC_RG_HK_INTRP_CK_PDN_MASK 0x1
+#define PMIC_RG_HK_INTRP_CK_PDN_SHIFT 9
+#define PMIC_RG_AUXADC_26M_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_AUXADC_26M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUXADC_26M_CK_TSTSEL_SHIFT 0
+#define PMIC_RG_AUXADC_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_AUXADC_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUXADC_CK_TSTSEL_SHIFT 1
+#define PMIC_RG_AUXADC_RNG_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_AUXADC_RNG_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUXADC_RNG_CK_TSTSEL_SHIFT 2
+#define PMIC_RG_AUXADC_1M_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_AUXADC_1M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUXADC_1M_CK_TSTSEL_SHIFT 3
+#define PMIC_RG_AUXADC_32K_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_AUXADC_32K_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUXADC_32K_CK_TSTSEL_SHIFT 4
+#define PMIC_RG_HK_INTRP_CK_TSTSEL_ADDR \
+ MT6389_HK_TOP_CLK_CON1
+#define PMIC_RG_HK_INTRP_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_HK_INTRP_CK_TSTSEL_SHIFT 5
+#define PMIC_RG_AUXADC_RST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_RG_AUXADC_RST_MASK 0x1
+#define PMIC_RG_AUXADC_RST_SHIFT 0
+#define PMIC_RG_AUXADC_REG_RST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_RG_AUXADC_REG_RST_MASK 0x1
+#define PMIC_RG_AUXADC_REG_RST_SHIFT 1
+#define PMIC_BANK_HK_TOP_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_HK_TOP_SWRST_MASK 0x1
+#define PMIC_BANK_HK_TOP_SWRST_SHIFT 2
+#define PMIC_BANK_AUXADC_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_SWRST_SHIFT 3
+#define PMIC_BANK_AUXADC_DIG_1_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_1_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_1_SWRST_SHIFT 4
+#define PMIC_BANK_AUXADC_DIG_2_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_2_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_2_SWRST_SHIFT 5
+#define PMIC_BANK_AUXADC_DIG_3_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_3_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_3_SWRST_SHIFT 6
+#define PMIC_BANK_AUXADC_DIG_4_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_4_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_4_SWRST_SHIFT 7
+#define PMIC_BANK_AUXADC_DIG_5_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_5_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_5_SWRST_SHIFT 8
+#define PMIC_BANK_AUXADC_DIG_6_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_6_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_6_SWRST_SHIFT 9
+#define PMIC_BANK_AUXADC_DIG_7_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_7_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_7_SWRST_SHIFT 10
+#define PMIC_BANK_AUXADC_DIG_8_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_8_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_8_SWRST_SHIFT 11
+#define PMIC_BANK_AUXADC_DIG_9_SWRST_ADDR \
+ MT6389_HK_TOP_RST_CON0
+#define PMIC_BANK_AUXADC_DIG_9_SWRST_MASK 0x1
+#define PMIC_BANK_AUXADC_DIG_9_SWRST_SHIFT 12
+#define PMIC_RG_INT_EN_BAT_H_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT_H_MASK 0x1
+#define PMIC_RG_INT_EN_BAT_H_SHIFT 0
+#define PMIC_RG_INT_EN_BAT_L_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT_L_MASK 0x1
+#define PMIC_RG_INT_EN_BAT_L_SHIFT 1
+#define PMIC_RG_INT_EN_BAT2_H_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT2_H_MASK 0x1
+#define PMIC_RG_INT_EN_BAT2_H_SHIFT 2
+#define PMIC_RG_INT_EN_BAT2_L_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT2_L_MASK 0x1
+#define PMIC_RG_INT_EN_BAT2_L_SHIFT 3
+#define PMIC_RG_INT_EN_BAT_TEMP_H_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT_TEMP_H_MASK 0x1
+#define PMIC_RG_INT_EN_BAT_TEMP_H_SHIFT 4
+#define PMIC_RG_INT_EN_BAT_TEMP_L_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_BAT_TEMP_L_MASK 0x1
+#define PMIC_RG_INT_EN_BAT_TEMP_L_SHIFT 5
+#define PMIC_RG_INT_EN_THR_H_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_THR_H_MASK 0x1
+#define PMIC_RG_INT_EN_THR_H_SHIFT 6
+#define PMIC_RG_INT_EN_THR_L_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_THR_L_MASK 0x1
+#define PMIC_RG_INT_EN_THR_L_SHIFT 7
+#define PMIC_RG_INT_EN_AUXADC_IMP_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_AUXADC_IMP_MASK 0x1
+#define PMIC_RG_INT_EN_AUXADC_IMP_SHIFT 8
+#define PMIC_RG_INT_EN_NAG_C_DLTV_ADDR \
+ MT6389_HK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_NAG_C_DLTV_MASK 0x1
+#define PMIC_RG_INT_EN_NAG_C_DLTV_SHIFT 9
+#define PMIC_HK_INT_CON0_SET_ADDR \
+ MT6389_HK_TOP_INT_CON0_SET
+#define PMIC_HK_INT_CON0_SET_MASK 0xFFFF
+#define PMIC_HK_INT_CON0_SET_SHIFT 0
+#define PMIC_HK_INT_CON0_CLR_ADDR \
+ MT6389_HK_TOP_INT_CON0_CLR
+#define PMIC_HK_INT_CON0_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER1_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER2_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER3_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER4_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER5_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER6_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_H_SHIFT 12
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER7_DET_DIV_L_SHIFT 13
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_H_SHIFT 14
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON1
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER8_DET_DIV_L_SHIFT 15
+#define PMIC_HK_INT_CON1_SET_ADDR \
+ MT6389_HK_TOP_INT_CON1_SET
+#define PMIC_HK_INT_CON1_SET_MASK 0xFFFF
+#define PMIC_HK_INT_CON1_SET_SHIFT 0
+#define PMIC_HK_INT_CON1_CLR_ADDR \
+ MT6389_HK_TOP_INT_CON1_CLR
+#define PMIC_HK_INT_CON1_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_CON1_CLR_SHIFT 0
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER9_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER10_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER11_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER12_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER13_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER14_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_EN_INTER1_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER1_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER1_DET_H_SHIFT 12
+#define PMIC_RG_INT_EN_INTER1_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON2
+#define PMIC_RG_INT_EN_INTER1_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER1_DET_L_SHIFT 13
+#define PMIC_HK_INT_CON2_SET_ADDR \
+ MT6389_HK_TOP_INT_CON2_SET
+#define PMIC_HK_INT_CON2_SET_MASK 0xFFFF
+#define PMIC_HK_INT_CON2_SET_SHIFT 0
+#define PMIC_HK_INT_CON2_CLR_ADDR \
+ MT6389_HK_TOP_INT_CON2_CLR
+#define PMIC_HK_INT_CON2_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_CON2_CLR_SHIFT 0
+#define PMIC_RG_INT_EN_INTER2_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER2_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER2_DET_H_SHIFT 0
+#define PMIC_RG_INT_EN_INTER2_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER2_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER2_DET_L_SHIFT 1
+#define PMIC_RG_INT_EN_INTER3_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER3_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER3_DET_H_SHIFT 2
+#define PMIC_RG_INT_EN_INTER3_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER3_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER3_DET_L_SHIFT 3
+#define PMIC_RG_INT_EN_INTER4_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER4_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER4_DET_H_SHIFT 4
+#define PMIC_RG_INT_EN_INTER4_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER4_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER4_DET_L_SHIFT 5
+#define PMIC_RG_INT_EN_INTER5_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER5_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER5_DET_H_SHIFT 6
+#define PMIC_RG_INT_EN_INTER5_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER5_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER5_DET_L_SHIFT 7
+#define PMIC_RG_INT_EN_INTER6_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER6_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER6_DET_H_SHIFT 8
+#define PMIC_RG_INT_EN_INTER6_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER6_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER6_DET_L_SHIFT 9
+#define PMIC_RG_INT_EN_INTER7_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER7_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER7_DET_H_SHIFT 10
+#define PMIC_RG_INT_EN_INTER7_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER7_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER7_DET_L_SHIFT 11
+#define PMIC_RG_INT_EN_INTER8_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER8_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER8_DET_H_SHIFT 12
+#define PMIC_RG_INT_EN_INTER8_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER8_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER8_DET_L_SHIFT 13
+#define PMIC_RG_INT_EN_INTER9_DET_H_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER9_DET_H_MASK 0x1
+#define PMIC_RG_INT_EN_INTER9_DET_H_SHIFT 14
+#define PMIC_RG_INT_EN_INTER9_DET_L_ADDR \
+ MT6389_HK_TOP_INT_CON3
+#define PMIC_RG_INT_EN_INTER9_DET_L_MASK 0x1
+#define PMIC_RG_INT_EN_INTER9_DET_L_SHIFT 15
+#define PMIC_HK_INT_CON3_SET_ADDR \
+ MT6389_HK_TOP_INT_CON3_SET
+#define PMIC_HK_INT_CON3_SET_MASK 0xFFFF
+#define PMIC_HK_INT_CON3_SET_SHIFT 0
+#define PMIC_HK_INT_CON3_CLR_ADDR \
+ MT6389_HK_TOP_INT_CON3_CLR
+#define PMIC_HK_INT_CON3_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_CON3_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_BAT_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT_H_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT_H_SHIFT 0
+#define PMIC_RG_INT_MASK_BAT_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT_L_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT_L_SHIFT 1
+#define PMIC_RG_INT_MASK_BAT2_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT2_H_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT2_H_SHIFT 2
+#define PMIC_RG_INT_MASK_BAT2_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT2_L_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT2_L_SHIFT 3
+#define PMIC_RG_INT_MASK_BAT_TEMP_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT_TEMP_H_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT_TEMP_H_SHIFT 4
+#define PMIC_RG_INT_MASK_BAT_TEMP_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_BAT_TEMP_L_MASK 0x1
+#define PMIC_RG_INT_MASK_BAT_TEMP_L_SHIFT 5
+#define PMIC_RG_INT_MASK_THR_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_THR_H_MASK 0x1
+#define PMIC_RG_INT_MASK_THR_H_SHIFT 6
+#define PMIC_RG_INT_MASK_THR_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_THR_L_MASK 0x1
+#define PMIC_RG_INT_MASK_THR_L_SHIFT 7
+#define PMIC_RG_INT_MASK_AUXADC_IMP_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_AUXADC_IMP_MASK 0x1
+#define PMIC_RG_INT_MASK_AUXADC_IMP_SHIFT 8
+#define PMIC_RG_INT_MASK_NAG_C_DLTV_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_NAG_C_DLTV_MASK 0x1
+#define PMIC_RG_INT_MASK_NAG_C_DLTV_SHIFT 9
+#define PMIC_HK_INT_MASK_CON0_SET_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0_SET
+#define PMIC_HK_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_HK_INT_MASK_CON0_CLR_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON0_CLR
+#define PMIC_HK_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER1_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER2_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER3_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER4_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER5_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER6_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_H_SHIFT 12
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER7_DET_DIV_L_SHIFT 13
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_H_SHIFT 14
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER8_DET_DIV_L_SHIFT 15
+#define PMIC_HK_INT_MASK_CON1_SET_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1_SET
+#define PMIC_HK_INT_MASK_CON1_SET_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON1_SET_SHIFT 0
+#define PMIC_HK_INT_MASK_CON1_CLR_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON1_CLR
+#define PMIC_HK_INT_MASK_CON1_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON1_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER9_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER10_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER11_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER12_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER13_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER14_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_MASK_INTER1_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER1_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER1_DET_H_SHIFT 12
+#define PMIC_RG_INT_MASK_INTER1_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2
+#define PMIC_RG_INT_MASK_INTER1_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER1_DET_L_SHIFT 13
+#define PMIC_HK_INT_MASK_CON2_SET_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2_SET
+#define PMIC_HK_INT_MASK_CON2_SET_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON2_SET_SHIFT 0
+#define PMIC_HK_INT_MASK_CON2_CLR_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON2_CLR
+#define PMIC_HK_INT_MASK_CON2_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON2_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER2_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER2_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER2_DET_H_SHIFT 0
+#define PMIC_RG_INT_MASK_INTER2_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER2_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER2_DET_L_SHIFT 1
+#define PMIC_RG_INT_MASK_INTER3_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER3_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER3_DET_H_SHIFT 2
+#define PMIC_RG_INT_MASK_INTER3_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER3_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER3_DET_L_SHIFT 3
+#define PMIC_RG_INT_MASK_INTER4_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER4_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER4_DET_H_SHIFT 4
+#define PMIC_RG_INT_MASK_INTER4_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER4_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER4_DET_L_SHIFT 5
+#define PMIC_RG_INT_MASK_INTER5_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER5_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER5_DET_H_SHIFT 6
+#define PMIC_RG_INT_MASK_INTER5_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER5_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER5_DET_L_SHIFT 7
+#define PMIC_RG_INT_MASK_INTER6_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER6_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER6_DET_H_SHIFT 8
+#define PMIC_RG_INT_MASK_INTER6_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER6_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER6_DET_L_SHIFT 9
+#define PMIC_RG_INT_MASK_INTER7_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER7_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER7_DET_H_SHIFT 10
+#define PMIC_RG_INT_MASK_INTER7_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER7_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER7_DET_L_SHIFT 11
+#define PMIC_RG_INT_MASK_INTER8_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER8_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER8_DET_H_SHIFT 12
+#define PMIC_RG_INT_MASK_INTER8_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER8_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER8_DET_L_SHIFT 13
+#define PMIC_RG_INT_MASK_INTER9_DET_H_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER9_DET_H_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER9_DET_H_SHIFT 14
+#define PMIC_RG_INT_MASK_INTER9_DET_L_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3
+#define PMIC_RG_INT_MASK_INTER9_DET_L_MASK 0x1
+#define PMIC_RG_INT_MASK_INTER9_DET_L_SHIFT 15
+#define PMIC_HK_INT_MASK_CON3_SET_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3_SET
+#define PMIC_HK_INT_MASK_CON3_SET_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON3_SET_SHIFT 0
+#define PMIC_HK_INT_MASK_CON3_CLR_ADDR \
+ MT6389_HK_TOP_INT_MASK_CON3_CLR
+#define PMIC_HK_INT_MASK_CON3_CLR_MASK 0xFFFF
+#define PMIC_HK_INT_MASK_CON3_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_BAT_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT_H_SHIFT 0
+#define PMIC_RG_INT_STATUS_BAT_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT_L_SHIFT 1
+#define PMIC_RG_INT_STATUS_BAT2_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT2_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT2_H_SHIFT 2
+#define PMIC_RG_INT_STATUS_BAT2_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT2_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT2_L_SHIFT 3
+#define PMIC_RG_INT_STATUS_BAT_TEMP_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT_TEMP_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT_TEMP_H_SHIFT 4
+#define PMIC_RG_INT_STATUS_BAT_TEMP_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_BAT_TEMP_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_BAT_TEMP_L_SHIFT 5
+#define PMIC_RG_INT_STATUS_THR_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_THR_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_THR_H_SHIFT 6
+#define PMIC_RG_INT_STATUS_THR_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_THR_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_THR_L_SHIFT 7
+#define PMIC_RG_INT_STATUS_AUXADC_IMP_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_AUXADC_IMP_MASK 0x1
+#define PMIC_RG_INT_STATUS_AUXADC_IMP_SHIFT 8
+#define PMIC_RG_INT_STATUS_NAG_C_DLTV_ADDR \
+ MT6389_HK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_NAG_C_DLTV_MASK 0x1
+#define PMIC_RG_INT_STATUS_NAG_C_DLTV_SHIFT 9
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER1_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER2_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER3_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER4_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER5_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER6_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_H_SHIFT 12
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER7_DET_DIV_L_SHIFT 13
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_H_SHIFT 14
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER8_DET_DIV_L_SHIFT 15
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER9_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER10_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER11_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER12_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER13_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER14_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_STATUS_INTER1_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER1_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER1_DET_H_SHIFT 12
+#define PMIC_RG_INT_STATUS_INTER1_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS2
+#define PMIC_RG_INT_STATUS_INTER1_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER1_DET_L_SHIFT 13
+#define PMIC_RG_INT_STATUS_INTER2_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER2_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER2_DET_H_SHIFT 0
+#define PMIC_RG_INT_STATUS_INTER2_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER2_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER2_DET_L_SHIFT 1
+#define PMIC_RG_INT_STATUS_INTER3_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER3_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER3_DET_H_SHIFT 2
+#define PMIC_RG_INT_STATUS_INTER3_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER3_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER3_DET_L_SHIFT 3
+#define PMIC_RG_INT_STATUS_INTER4_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER4_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER4_DET_H_SHIFT 4
+#define PMIC_RG_INT_STATUS_INTER4_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER4_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER4_DET_L_SHIFT 5
+#define PMIC_RG_INT_STATUS_INTER5_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER5_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER5_DET_H_SHIFT 6
+#define PMIC_RG_INT_STATUS_INTER5_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER5_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER5_DET_L_SHIFT 7
+#define PMIC_RG_INT_STATUS_INTER6_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER6_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER6_DET_H_SHIFT 8
+#define PMIC_RG_INT_STATUS_INTER6_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER6_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER6_DET_L_SHIFT 9
+#define PMIC_RG_INT_STATUS_INTER7_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER7_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER7_DET_H_SHIFT 10
+#define PMIC_RG_INT_STATUS_INTER7_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER7_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER7_DET_L_SHIFT 11
+#define PMIC_RG_INT_STATUS_INTER8_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER8_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER8_DET_H_SHIFT 12
+#define PMIC_RG_INT_STATUS_INTER8_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER8_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER8_DET_L_SHIFT 13
+#define PMIC_RG_INT_STATUS_INTER9_DET_H_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER9_DET_H_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER9_DET_H_SHIFT 14
+#define PMIC_RG_INT_STATUS_INTER9_DET_L_ADDR \
+ MT6389_HK_TOP_INT_STATUS3
+#define PMIC_RG_INT_STATUS_INTER9_DET_L_MASK 0x1
+#define PMIC_RG_INT_STATUS_INTER9_DET_L_SHIFT 15
+#define PMIC_RG_INT_RAW_STATUS_BAT_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT_H_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_BAT_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT_L_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_BAT2_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT2_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT2_H_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_BAT2_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT2_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT2_L_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_THR_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_THR_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_THR_H_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_THR_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_THR_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_THR_L_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_SHIFT 8
+#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_SHIFT 9
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_H_SHIFT 12
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_L_SHIFT 13
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_H_SHIFT 14
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_L_SHIFT 15
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_H_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_L_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_H_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_L_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_H_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_L_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_H_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_L_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_H_SHIFT 8
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_L_SHIFT 9
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_H_SHIFT 10
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_L_SHIFT 11
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_H_SHIFT 12
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS2
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER1_DET_L_SHIFT 13
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_H_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER2_DET_L_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_H_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER3_DET_L_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_H_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER4_DET_L_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_H_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER5_DET_L_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_H_SHIFT 8
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER6_DET_L_SHIFT 9
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_H_SHIFT 10
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER7_DET_L_SHIFT 11
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_H_SHIFT 12
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER8_DET_L_SHIFT 13
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_H_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_H_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_H_SHIFT 14
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_L_ADDR \
+ MT6389_HK_TOP_INT_RAW_STATUS3
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_L_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_INTER9_DET_L_SHIFT 15
+#define PMIC_RG_CLK_MON_FLAG_EN_ADDR \
+ MT6389_HK_TOP_MON_CON0
+#define PMIC_RG_CLK_MON_FLAG_EN_MASK 0x1
+#define PMIC_RG_CLK_MON_FLAG_EN_SHIFT 0
+#define PMIC_RG_CLK_MON_FLAG_SEL_ADDR \
+ MT6389_HK_TOP_MON_CON0
+#define PMIC_RG_CLK_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_CLK_MON_FLAG_SEL_SHIFT 1
+#define PMIC_RG_INT_MON_FLAG_EN_ADDR \
+ MT6389_HK_TOP_MON_CON1
+#define PMIC_RG_INT_MON_FLAG_EN_MASK 0x1
+#define PMIC_RG_INT_MON_FLAG_EN_SHIFT 0
+#define PMIC_RG_INT_MON_FLAG_SEL_ADDR \
+ MT6389_HK_TOP_MON_CON1
+#define PMIC_RG_INT_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_INT_MON_FLAG_SEL_SHIFT 1
+#define PMIC_RG_HK_MON_FLAG_SEL_ADDR \
+ MT6389_HK_TOP_MON_CON2
+#define PMIC_RG_HK_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_HK_MON_FLAG_SEL_SHIFT 0
+#define PMIC_RG_MON_FLAG_SEL_AUXADC_ADDR \
+ MT6389_HK_TOP_MON_CON2
+#define PMIC_RG_MON_FLAG_SEL_AUXADC_MASK 0x1
+#define PMIC_RG_MON_FLAG_SEL_AUXADC_SHIFT 8
+#define PMIC_RG_ADCIN_VSEN_MUX_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT 0
+#define PMIC_RG_BATON_TDET_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_BATON_TDET_EN_MASK 0x1
+#define PMIC_RG_BATON_TDET_EN_SHIFT 1
+#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
+#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 2
+#define PMIC_RG_ADCIN_VBAT_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_ADCIN_VBAT_EN_MASK 0x1
+#define PMIC_RG_ADCIN_VBAT_EN_SHIFT 3
+#define PMIC_RG_ADCIN_VSEN_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_ADCIN_VSEN_EN_MASK 0x1
+#define PMIC_RG_ADCIN_VSEN_EN_SHIFT 4
+#define PMIC_RG_ADCIN_CHR_EN_ADDR \
+ MT6389_HK_TOP_CHR_CON
+#define PMIC_RG_ADCIN_CHR_EN_MASK 0x1
+#define PMIC_RG_ADCIN_CHR_EN_SHIFT 5
+#define PMIC_RG_AUXADC_DIFFBUF_SWEN_ADDR \
+ MT6389_HK_TOP_ANA_CON
+#define PMIC_RG_AUXADC_DIFFBUF_SWEN_MASK 0x1
+#define PMIC_RG_AUXADC_DIFFBUF_SWEN_SHIFT 0
+#define PMIC_RG_AUXADC_DIFFBUF_EN_ADDR \
+ MT6389_HK_TOP_ANA_CON
+#define PMIC_RG_AUXADC_DIFFBUF_EN_MASK 0x1
+#define PMIC_RG_AUXADC_DIFFBUF_EN_SHIFT 1
+#define PMIC_DA_ADCIN_VBAT_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_ADCIN_VBAT_EN_MASK 0x1
+#define PMIC_DA_ADCIN_VBAT_EN_SHIFT 0
+#define PMIC_DA_AUXADC_VBAT_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_AUXADC_VBAT_EN_MASK 0x1
+#define PMIC_DA_AUXADC_VBAT_EN_SHIFT 1
+#define PMIC_DA_ADCIN_VSEN_MUX_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define PMIC_DA_ADCIN_VSEN_MUX_EN_SHIFT 2
+#define PMIC_DA_ADCIN_VSEN_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_ADCIN_VSEN_EN_MASK 0x1
+#define PMIC_DA_ADCIN_VSEN_EN_SHIFT 3
+#define PMIC_DA_ADCIN_CHR_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_ADCIN_CHR_EN_MASK 0x1
+#define PMIC_DA_ADCIN_CHR_EN_SHIFT 4
+#define PMIC_DA_BATON_TDET_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_BATON_TDET_EN_MASK 0x1
+#define PMIC_DA_BATON_TDET_EN_SHIFT 5
+#define PMIC_DA_ADCIN_BATID_SW_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_ADCIN_BATID_SW_EN_MASK 0x1
+#define PMIC_DA_ADCIN_BATID_SW_EN_SHIFT 6
+#define PMIC_DA_AUXADC_DIFFBUF_EN_ADDR \
+ MT6389_HK_TOP_AUXADC_ANA
+#define PMIC_DA_AUXADC_DIFFBUF_EN_MASK 0x1
+#define PMIC_DA_AUXADC_DIFFBUF_EN_SHIFT 7
+#define PMIC_RG_HK_STRUP_AUXADC_START_SW_ADDR \
+ MT6389_HK_TOP_STRUP
+#define PMIC_RG_HK_STRUP_AUXADC_START_SW_MASK 0x1
+#define PMIC_RG_HK_STRUP_AUXADC_START_SW_SHIFT 0
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SW_ADDR \
+ MT6389_HK_TOP_STRUP
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SW_MASK 0x1
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SW_SHIFT 1
+#define PMIC_RG_HK_STRUP_AUXADC_START_SEL_ADDR \
+ MT6389_HK_TOP_STRUP
+#define PMIC_RG_HK_STRUP_AUXADC_START_SEL_MASK 0x1
+#define PMIC_RG_HK_STRUP_AUXADC_START_SEL_SHIFT 2
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SEL_ADDR \
+ MT6389_HK_TOP_STRUP
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SEL_MASK 0x1
+#define PMIC_RG_HK_STRUP_AUXADC_RSTB_SEL_SHIFT 3
+#define PMIC_RG_HK_STRUP_AUXADC_RPCNT_MAX_ADDR \
+ MT6389_HK_TOP_STRUP
+#define PMIC_RG_HK_STRUP_AUXADC_RPCNT_MAX_MASK 0x7F
+#define PMIC_RG_HK_STRUP_AUXADC_RPCNT_MAX_SHIFT 4
+#define PMIC_RG_VAUX18_AUXADC_STB_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VAUX18_AUXADC_STB_SWEN_MASK 0x1
+#define PMIC_RG_VAUX18_AUXADC_STB_SWEN_SHIFT 0
+#define PMIC_RG_VAUX18_AUXADC_STB_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VAUX18_AUXADC_STB_EN_MASK 0x1
+#define PMIC_RG_VAUX18_AUXADC_STB_EN_SHIFT 1
+#define PMIC_RG_VAUX18_AUXADC_ACK_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VAUX18_AUXADC_ACK_SWEN_MASK 0x1
+#define PMIC_RG_VAUX18_AUXADC_ACK_SWEN_SHIFT 2
+#define PMIC_RG_VAUX18_AUXADC_ACK_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VAUX18_AUXADC_ACK_EN_MASK 0x1
+#define PMIC_RG_VAUX18_AUXADC_ACK_EN_SHIFT 3
+#define PMIC_RG_VBIF28_AUXADC_STB_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VBIF28_AUXADC_STB_SWEN_MASK 0x1
+#define PMIC_RG_VBIF28_AUXADC_STB_SWEN_SHIFT 4
+#define PMIC_RG_VBIF28_AUXADC_STB_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VBIF28_AUXADC_STB_EN_MASK 0x1
+#define PMIC_RG_VBIF28_AUXADC_STB_EN_SHIFT 5
+#define PMIC_RG_VBIF28_AUXADC_ACK_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VBIF28_AUXADC_ACK_SWEN_MASK 0x1
+#define PMIC_RG_VBIF28_AUXADC_ACK_SWEN_SHIFT 6
+#define PMIC_RG_VBIF28_AUXADC_ACK_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VBIF28_AUXADC_ACK_EN_MASK 0x1
+#define PMIC_RG_VBIF28_AUXADC_ACK_EN_SHIFT 7
+#define PMIC_RG_VTREF_AUXADC_STB_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_STB_SWEN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_STB_SWEN_SHIFT 8
+#define PMIC_RG_VTREF_AUXADC_STB_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_STB_EN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_STB_EN_SHIFT 9
+#define PMIC_RG_VTREF_AUXADC_ACK_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_ACK_SWEN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_ACK_SWEN_SHIFT 10
+#define PMIC_RG_VTREF_AUXADC_ACK_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_ACK_EN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_ACK_EN_SHIFT 11
+#define PMIC_RG_VTREF_AUXADC_PWDB_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_PWDB_SWEN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_PWDB_SWEN_SHIFT 12
+#define PMIC_RG_VTREF_AUXADC_PWDB_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_PWDB_EN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_PWDB_EN_SHIFT 13
+#define PMIC_RG_VTREF_AUXADC_REQ_SWEN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_REQ_SWEN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_REQ_SWEN_SHIFT 14
+#define PMIC_RG_VTREF_AUXADC_REQ_EN_ADDR \
+ MT6389_HK_TOP_LDO_CON
+#define PMIC_RG_VTREF_AUXADC_REQ_EN_MASK 0x1
+#define PMIC_RG_VTREF_AUXADC_REQ_EN_SHIFT 15
+#define PMIC_DD_AUXADC_VAUX18_REQ_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VAUX18_REQ_MASK 0x1
+#define PMIC_DD_AUXADC_VAUX18_REQ_SHIFT 0
+#define PMIC_DD_VAUX18_AUXADC_STB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VAUX18_AUXADC_STB_MASK 0x1
+#define PMIC_DD_VAUX18_AUXADC_STB_SHIFT 1
+#define PMIC_DD_AUXADC_VAUX18_PWDB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VAUX18_PWDB_MASK 0x1
+#define PMIC_DD_AUXADC_VAUX18_PWDB_SHIFT 2
+#define PMIC_DD_VAUX18_AUXADC_ACK_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VAUX18_AUXADC_ACK_MASK 0x1
+#define PMIC_DD_VAUX18_AUXADC_ACK_SHIFT 3
+#define PMIC_DD_AUXADC_VBIF28_REQ_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VBIF28_REQ_MASK 0x1
+#define PMIC_DD_AUXADC_VBIF28_REQ_SHIFT 4
+#define PMIC_DD_VBIF28_AUXADC_STB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VBIF28_AUXADC_STB_MASK 0x1
+#define PMIC_DD_VBIF28_AUXADC_STB_SHIFT 5
+#define PMIC_DD_AUXADC_VBIF28_PWDB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VBIF28_PWDB_MASK 0x1
+#define PMIC_DD_AUXADC_VBIF28_PWDB_SHIFT 6
+#define PMIC_DD_VBIF28_AUXADC_ACK_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VBIF28_AUXADC_ACK_MASK 0x1
+#define PMIC_DD_VBIF28_AUXADC_ACK_SHIFT 7
+#define PMIC_DD_AUXADC_VTREF_REQ_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VTREF_REQ_MASK 0x1
+#define PMIC_DD_AUXADC_VTREF_REQ_SHIFT 8
+#define PMIC_DD_VTREF_AUXADC_STB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VTREF_AUXADC_STB_MASK 0x1
+#define PMIC_DD_VTREF_AUXADC_STB_SHIFT 9
+#define PMIC_DD_AUXADC_VTREF_PWDB_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_AUXADC_VTREF_PWDB_MASK 0x1
+#define PMIC_DD_AUXADC_VTREF_PWDB_SHIFT 10
+#define PMIC_DD_VTREF_AUXADC_ACK_ADDR \
+ MT6389_HK_TOP_LDO_STATUS
+#define PMIC_DD_VTREF_AUXADC_ACK_MASK 0x1
+#define PMIC_DD_VTREF_AUXADC_ACK_SHIFT 11
+#define PMIC_HK_AUXADC_KEY_ADDR \
+ MT6389_HK_TOP_WKEY
+#define PMIC_HK_AUXADC_KEY_MASK 0xFFFF
+#define PMIC_HK_AUXADC_KEY_SHIFT 0
+#define PMIC_AUXADC_ANA_ID_ADDR \
+ MT6389_AUXADC_DSN_ID
+#define PMIC_AUXADC_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_ID_ADDR \
+ MT6389_AUXADC_DSN_ID
+#define PMIC_AUXADC_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DSN_REV0
+#define PMIC_AUXADC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DSN_REV0
+#define PMIC_AUXADC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DSN_REV0
+#define PMIC_AUXADC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DSN_REV0
+#define PMIC_AUXADC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DSN_CBS_ADDR \
+ MT6389_AUXADC_DSN_DBI
+#define PMIC_AUXADC_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DSN_BIX_ADDR \
+ MT6389_AUXADC_DSN_DBI
+#define PMIC_AUXADC_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DSN_ESP_ADDR \
+ MT6389_AUXADC_DSN_DBI
+#define PMIC_AUXADC_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DSN_FPI_ADDR \
+ MT6389_AUXADC_DSN_FPI
+#define PMIC_AUXADC_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DSN_FPI_SHIFT 0
+#define PMIC_RG_AUX_RSV_ADDR \
+ MT6389_AUXADC_ANA_CON0
+#define PMIC_RG_AUX_RSV_MASK 0xFFFF
+#define PMIC_RG_AUX_RSV_SHIFT 0
+#define PMIC_RG_AUXADC_CALI_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_AUXADC_CALI_MASK 0xF
+#define PMIC_RG_AUXADC_CALI_SHIFT 0
+#define PMIC_RG_VBUF_BYP_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_VBUF_BYP_MASK 0x1
+#define PMIC_RG_VBUF_BYP_SHIFT 4
+#define PMIC_RG_VBUF_CALEN_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_VBUF_CALEN_MASK 0x1
+#define PMIC_RG_VBUF_CALEN_SHIFT 5
+#define PMIC_RG_VBUF_EXTEN_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_VBUF_EXTEN_MASK 0x1
+#define PMIC_RG_VBUF_EXTEN_SHIFT 6
+#define PMIC_RG_AUXADC_RNG_EN_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_AUXADC_RNG_EN_MASK 0x1
+#define PMIC_RG_AUXADC_RNG_EN_SHIFT 7
+#define PMIC_RG_AUXADC_NOISE_RES_ADDR \
+ MT6389_AUXADC_ANA_CON1
+#define PMIC_RG_AUXADC_NOISE_RES_MASK 0x3
+#define PMIC_RG_AUXADC_NOISE_RES_SHIFT 8
+#define PMIC_AUXADC_DIG_1_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_ID
+#define PMIC_AUXADC_DIG_1_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_1_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_1_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_ID
+#define PMIC_AUXADC_DIG_1_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_1_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_REV0
+#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_REV0
+#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_REV0
+#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_REV0
+#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_1_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_DBI
+#define PMIC_AUXADC_DIG_1_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_1_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_1_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_DBI
+#define PMIC_AUXADC_DIG_1_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_1_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_1_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_DBI
+#define PMIC_AUXADC_DIG_1_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_1_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_1_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_1_DSN_DXI
+#define PMIC_AUXADC_DIG_1_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_1_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_ADC_OUT_CH0_ADDR \
+ MT6389_AUXADC_ADC0
+#define PMIC_AUXADC_ADC_OUT_CH0_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH0_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH0_ADDR \
+ MT6389_AUXADC_ADC0
+#define PMIC_AUXADC_ADC_RDY_CH0_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH0_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH1_ADDR \
+ MT6389_AUXADC_ADC1
+#define PMIC_AUXADC_ADC_OUT_CH1_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH1_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH1_ADDR \
+ MT6389_AUXADC_ADC1
+#define PMIC_AUXADC_ADC_RDY_CH1_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH1_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH2_ADDR \
+ MT6389_AUXADC_ADC2
+#define PMIC_AUXADC_ADC_OUT_CH2_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH2_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH2_ADDR \
+ MT6389_AUXADC_ADC2
+#define PMIC_AUXADC_ADC_RDY_CH2_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH2_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH3_ADDR \
+ MT6389_AUXADC_ADC3
+#define PMIC_AUXADC_ADC_OUT_CH3_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH3_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH3_ADDR \
+ MT6389_AUXADC_ADC3
+#define PMIC_AUXADC_ADC_RDY_CH3_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH3_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH4_ADDR \
+ MT6389_AUXADC_ADC4
+#define PMIC_AUXADC_ADC_OUT_CH4_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH4_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH4_ADDR \
+ MT6389_AUXADC_ADC4
+#define PMIC_AUXADC_ADC_RDY_CH4_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH4_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH5_ADDR \
+ MT6389_AUXADC_ADC5
+#define PMIC_AUXADC_ADC_OUT_CH5_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH5_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH5_ADDR \
+ MT6389_AUXADC_ADC5
+#define PMIC_AUXADC_ADC_RDY_CH5_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH5_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH6_ADDR \
+ MT6389_AUXADC_ADC6
+#define PMIC_AUXADC_ADC_OUT_CH6_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH6_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH6_ADDR \
+ MT6389_AUXADC_ADC6
+#define PMIC_AUXADC_ADC_RDY_CH6_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH6_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH7_ADDR \
+ MT6389_AUXADC_ADC7
+#define PMIC_AUXADC_ADC_OUT_CH7_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH7_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH7_ADDR \
+ MT6389_AUXADC_ADC7
+#define PMIC_AUXADC_ADC_RDY_CH7_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH7_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH8_ADDR \
+ MT6389_AUXADC_ADC8
+#define PMIC_AUXADC_ADC_OUT_CH8_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH8_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH8_ADDR \
+ MT6389_AUXADC_ADC8
+#define PMIC_AUXADC_ADC_RDY_CH8_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH8_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH9_ADDR \
+ MT6389_AUXADC_ADC9
+#define PMIC_AUXADC_ADC_OUT_CH9_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH9_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH9_ADDR \
+ MT6389_AUXADC_ADC9
+#define PMIC_AUXADC_ADC_RDY_CH9_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH9_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH10_ADDR \
+ MT6389_AUXADC_ADC10
+#define PMIC_AUXADC_ADC_OUT_CH10_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH10_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH10_ADDR \
+ MT6389_AUXADC_ADC10
+#define PMIC_AUXADC_ADC_RDY_CH10_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH10_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH11_ADDR \
+ MT6389_AUXADC_ADC11
+#define PMIC_AUXADC_ADC_OUT_CH11_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH11_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH11_ADDR \
+ MT6389_AUXADC_ADC11
+#define PMIC_AUXADC_ADC_RDY_CH11_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH11_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH14_15_ADDR \
+ MT6389_AUXADC_ADC14
+#define PMIC_AUXADC_ADC_OUT_CH14_15_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH14_15_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH14_15_ADDR \
+ MT6389_AUXADC_ADC14
+#define PMIC_AUXADC_ADC_RDY_CH14_15_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH14_15_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_ADDR \
+ MT6389_AUXADC_ADC15
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_ADDR \
+ MT6389_AUXADC_ADC15
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_ADDR \
+ MT6389_AUXADC_ADC16
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_ADDR \
+ MT6389_AUXADC_ADC16
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_ADDR \
+ MT6389_AUXADC_ADC17
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_ADDR \
+ MT6389_AUXADC_ADC17
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_ADDR \
+ MT6389_AUXADC_ADC18
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_ADDR \
+ MT6389_AUXADC_ADC18
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_ADDR \
+ MT6389_AUXADC_ADC19
+#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_ADDR \
+ MT6389_AUXADC_ADC19
+#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_ADDR \
+ MT6389_AUXADC_ADC20
+#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_ADDR \
+ MT6389_AUXADC_ADC20
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_ADDR \
+ MT6389_AUXADC_ADC21
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_ADDR \
+ MT6389_AUXADC_ADC21
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_ADDR \
+ MT6389_AUXADC_ADC22
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_ADDR \
+ MT6389_AUXADC_ADC22
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_ADDR \
+ MT6389_AUXADC_ADC23
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_ADDR \
+ MT6389_AUXADC_ADC23
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_ADDR \
+ MT6389_AUXADC_ADC24
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_ADDR \
+ MT6389_AUXADC_ADC24
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_ADDR \
+ MT6389_AUXADC_ADC26
+#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_ADDR \
+ MT6389_AUXADC_ADC26
+#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_ADDR \
+ MT6389_AUXADC_ADC27
+#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_ADDR \
+ MT6389_AUXADC_ADC27
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_RAW_ADDR \
+ MT6389_AUXADC_ADC30
+#define PMIC_AUXADC_ADC_OUT_RAW_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_RAW_SHIFT 0
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_ADDR \
+ MT6389_AUXADC_ADC32
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_ADDR \
+ MT6389_AUXADC_ADC32
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_ADDR \
+ MT6389_AUXADC_ADC33
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_ADDR \
+ MT6389_AUXADC_ADC33
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_ADDR \
+ MT6389_AUXADC_ADC34
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_ADDR \
+ MT6389_AUXADC_ADC34
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_BATID_ADDR \
+ MT6389_AUXADC_ADC37
+#define PMIC_AUXADC_ADC_OUT_BATID_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_BATID_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_BATID_ADDR \
+ MT6389_AUXADC_ADC37
+#define PMIC_AUXADC_ADC_RDY_BATID_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_BATID_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_ADDR \
+ MT6389_AUXADC_ADC38
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_ADDR \
+ MT6389_AUXADC_ADC38
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_ADDR \
+ MT6389_AUXADC_ADC39
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_ADDR \
+ MT6389_AUXADC_ADC39
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_ADDR \
+ MT6389_AUXADC_ADC40
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_ADDR \
+ MT6389_AUXADC_ADC40
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_ADC41
+#define PMIC_AUXADC_ADC_OUT_MDRT_WAKEUP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_MDRT_WAKEUP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_ADC41
+#define PMIC_AUXADC_ADC_RDY_MDRT_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_MDRT_WAKEUP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_ADC42
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_WAKEUP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_WAKEUP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_ADC42
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_WAKEUP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_MDRT_MERGE_ADDR \
+ MT6389_AUXADC_ADC43
+#define PMIC_AUXADC_ADC_OUT_MDRT_MERGE_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_MDRT_MERGE_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_MDRT_MERGE_ADDR \
+ MT6389_AUXADC_ADC43
+#define PMIC_AUXADC_ADC_RDY_MDRT_MERGE_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_MDRT_MERGE_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MERGE_ADDR \
+ MT6389_AUXADC_ADC44
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MERGE_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MERGE_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_ADDR \
+ MT6389_AUXADC_ADC44
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE_SHIFT 15
+#define PMIC_AUXADC_ADC_BUSY_IN_ADDR \
+ MT6389_AUXADC_STA0
+#define PMIC_AUXADC_ADC_BUSY_IN_MASK 0xFFF
+#define PMIC_AUXADC_ADC_BUSY_IN_SHIFT 0
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_STA0
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_WAKEUP_SHIFT 12
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_WAKEUP_ADDR \
+ MT6389_AUXADC_STA0
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_WAKEUP_SHIFT 13
+#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_ADDR \
+ MT6389_AUXADC_STA0
+#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_SHIFT 15
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_SHIFT 2
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_SHIFT 3
+#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_SHIFT 7
+#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_SHIFT 9
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_SHIFT 11
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_SHIFT 12
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_GPS_SHIFT 13
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_ADDR \
+ MT6389_AUXADC_STA1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_SHIFT 15
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_SHIFT 0
+#define PMIC_AUXADC_ADC_BUSY_IN_BATID_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_BATID_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_BATID_SHIFT 2
+#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_SHIFT 3
+#define PMIC_AUXADC_ADC_BUSY_IN_THR1_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_THR1_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR1_SHIFT 11
+#define PMIC_AUXADC_ADC_BUSY_IN_THR2_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_THR2_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR2_SHIFT 12
+#define PMIC_AUXADC_ADC_BUSY_IN_THR3_ADDR \
+ MT6389_AUXADC_STA2
+#define PMIC_AUXADC_ADC_BUSY_IN_THR3_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR3_SHIFT 13
+#define PMIC_AUXADC_SAMPLE_LIST_15_0_ADDR \
+ MT6389_AUXADC_SPL_LIST_0
+#define PMIC_AUXADC_SAMPLE_LIST_15_0_MASK 0xFFFF
+#define PMIC_AUXADC_SAMPLE_LIST_15_0_SHIFT 0
+#define PMIC_AUXADC_SAMPLE_LIST_31_16_ADDR \
+ MT6389_AUXADC_SPL_LIST_1
+#define PMIC_AUXADC_SAMPLE_LIST_31_16_MASK 0xFFFF
+#define PMIC_AUXADC_SAMPLE_LIST_31_16_SHIFT 0
+#define PMIC_AUXADC_SAMPLE_LIST_47_32_ADDR \
+ MT6389_AUXADC_SPL_LIST_2
+#define PMIC_AUXADC_SAMPLE_LIST_47_32_MASK 0xFFFF
+#define PMIC_AUXADC_SAMPLE_LIST_47_32_SHIFT 0
+#define PMIC_AUXADC_SAMPLE_LIST_63_48_ADDR \
+ MT6389_AUXADC_SPL_LIST_3
+#define PMIC_AUXADC_SAMPLE_LIST_63_48_MASK 0xFFFF
+#define PMIC_AUXADC_SAMPLE_LIST_63_48_SHIFT 0
+#define PMIC_AUXADC_SAMPLE_LIST_79_64_ADDR \
+ MT6389_AUXADC_SPL_LIST_4
+#define PMIC_AUXADC_SAMPLE_LIST_79_64_MASK 0xFFFF
+#define PMIC_AUXADC_SAMPLE_LIST_79_64_SHIFT 0
+#define PMIC_AUXADC_DIG_2_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_ID
+#define PMIC_AUXADC_DIG_2_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_2_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_2_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_ID
+#define PMIC_AUXADC_DIG_2_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_2_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_REV0
+#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_REV0
+#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_REV0
+#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_REV0
+#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_2_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_DBI
+#define PMIC_AUXADC_DIG_2_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_2_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_2_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_DBI
+#define PMIC_AUXADC_DIG_2_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_2_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_2_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_DBI
+#define PMIC_AUXADC_DIG_2_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_2_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_2_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_2_DSN_DXI
+#define PMIC_AUXADC_DIG_2_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_2_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_RQST_CH0_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH0_MASK 0x1
+#define PMIC_AUXADC_RQST_CH0_SHIFT 0
+#define PMIC_AUXADC_RQST_CH1_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH1_MASK 0x1
+#define PMIC_AUXADC_RQST_CH1_SHIFT 1
+#define PMIC_AUXADC_RQST_CH2_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH2_MASK 0x1
+#define PMIC_AUXADC_RQST_CH2_SHIFT 2
+#define PMIC_AUXADC_RQST_CH3_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH3_MASK 0x1
+#define PMIC_AUXADC_RQST_CH3_SHIFT 3
+#define PMIC_AUXADC_RQST_CH4_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH4_MASK 0x1
+#define PMIC_AUXADC_RQST_CH4_SHIFT 4
+#define PMIC_AUXADC_RQST_CH5_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH5_MASK 0x1
+#define PMIC_AUXADC_RQST_CH5_SHIFT 5
+#define PMIC_AUXADC_RQST_CH6_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH6_MASK 0x1
+#define PMIC_AUXADC_RQST_CH6_SHIFT 6
+#define PMIC_AUXADC_RQST_CH7_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH7_MASK 0x1
+#define PMIC_AUXADC_RQST_CH7_SHIFT 7
+#define PMIC_AUXADC_RQST_CH8_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH8_MASK 0x1
+#define PMIC_AUXADC_RQST_CH8_SHIFT 8
+#define PMIC_AUXADC_RQST_CH9_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH9_MASK 0x1
+#define PMIC_AUXADC_RQST_CH9_SHIFT 9
+#define PMIC_AUXADC_RQST_CH10_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH10_MASK 0x1
+#define PMIC_AUXADC_RQST_CH10_SHIFT 10
+#define PMIC_AUXADC_RQST_CH11_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH11_MASK 0x1
+#define PMIC_AUXADC_RQST_CH11_SHIFT 11
+#define PMIC_AUXADC_RQST_CH12_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH12_MASK 0x1
+#define PMIC_AUXADC_RQST_CH12_SHIFT 12
+#define PMIC_AUXADC_RQST_CH13_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH13_MASK 0x1
+#define PMIC_AUXADC_RQST_CH13_SHIFT 13
+#define PMIC_AUXADC_RQST_CH14_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH14_MASK 0x1
+#define PMIC_AUXADC_RQST_CH14_SHIFT 14
+#define PMIC_AUXADC_RQST_CH15_ADDR \
+ MT6389_AUXADC_RQST0
+#define PMIC_AUXADC_RQST_CH15_MASK 0x1
+#define PMIC_AUXADC_RQST_CH15_SHIFT 15
+#define PMIC_AUXADC_RQST_CH0_BY_MD_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH0_BY_MD_MASK 0x1
+#define PMIC_AUXADC_RQST_CH0_BY_MD_SHIFT 0
+#define PMIC_AUXADC_RQST_CH1_BY_MD_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH1_BY_MD_MASK 0x1
+#define PMIC_AUXADC_RQST_CH1_BY_MD_SHIFT 1
+#define PMIC_AUXADC_RQST_CH4_BY_MD_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH4_BY_MD_MASK 0x1
+#define PMIC_AUXADC_RQST_CH4_BY_MD_SHIFT 2
+#define PMIC_AUXADC_RQST_CH7_BY_MD_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH7_BY_MD_MASK 0x1
+#define PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT 3
+#define PMIC_AUXADC_RQST_CH7_BY_GPS_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH7_BY_GPS_MASK 0x1
+#define PMIC_AUXADC_RQST_CH7_BY_GPS_SHIFT 4
+#define PMIC_AUXADC_RQST_DCXO_BY_MD_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_DCXO_BY_MD_MASK 0x1
+#define PMIC_AUXADC_RQST_DCXO_BY_MD_SHIFT 5
+#define PMIC_AUXADC_RQST_DCXO_BY_GPS_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_DCXO_BY_GPS_MASK 0x1
+#define PMIC_AUXADC_RQST_DCXO_BY_GPS_SHIFT 6
+#define PMIC_AUXADC_RQST_BATID_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_BATID_MASK 0x1
+#define PMIC_AUXADC_RQST_BATID_SHIFT 7
+#define PMIC_AUXADC_RQST_CH4_BY_THR1_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH4_BY_THR1_MASK 0x1
+#define PMIC_AUXADC_RQST_CH4_BY_THR1_SHIFT 8
+#define PMIC_AUXADC_RQST_CH4_BY_THR2_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH4_BY_THR2_MASK 0x1
+#define PMIC_AUXADC_RQST_CH4_BY_THR2_SHIFT 9
+#define PMIC_AUXADC_RQST_CH4_BY_THR3_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_CH4_BY_THR3_MASK 0x1
+#define PMIC_AUXADC_RQST_CH4_BY_THR3_SHIFT 10
+#define PMIC_AUXADC_RQST_RSV1_ADDR \
+ MT6389_AUXADC_RQST1
+#define PMIC_AUXADC_RQST_RSV1_MASK 0x1
+#define PMIC_AUXADC_RQST_RSV1_SHIFT 11
+#define PMIC_AUXADC_RQST_INTER1_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER1_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER1_DIV_SHIFT 0
+#define PMIC_AUXADC_RQST_INTER2_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER2_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER2_DIV_SHIFT 1
+#define PMIC_AUXADC_RQST_INTER3_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER3_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER3_DIV_SHIFT 2
+#define PMIC_AUXADC_RQST_INTER4_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER4_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER4_DIV_SHIFT 3
+#define PMIC_AUXADC_RQST_INTER5_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER5_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER5_DIV_SHIFT 4
+#define PMIC_AUXADC_RQST_INTER6_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER6_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER6_DIV_SHIFT 5
+#define PMIC_AUXADC_RQST_INTER7_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER7_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER7_DIV_SHIFT 6
+#define PMIC_AUXADC_RQST_INTER8_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER8_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER8_DIV_SHIFT 7
+#define PMIC_AUXADC_RQST_INTER9_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER9_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER9_DIV_SHIFT 8
+#define PMIC_AUXADC_RQST_INTER10_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER10_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER10_DIV_SHIFT 9
+#define PMIC_AUXADC_RQST_INTER11_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER11_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER11_DIV_SHIFT 10
+#define PMIC_AUXADC_RQST_INTER12_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER12_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER12_DIV_SHIFT 11
+#define PMIC_AUXADC_RQST_INTER13_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER13_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER13_DIV_SHIFT 12
+#define PMIC_AUXADC_RQST_INTER14_DIV_ADDR \
+ MT6389_AUXADC_RQST2
+#define PMIC_AUXADC_RQST_INTER14_DIV_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER14_DIV_SHIFT 13
+#define PMIC_AUXADC_RQST_INTER1_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER1_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER1_SHIFT 0
+#define PMIC_AUXADC_RQST_INTER2_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER2_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER2_SHIFT 1
+#define PMIC_AUXADC_RQST_INTER3_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER3_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER3_SHIFT 2
+#define PMIC_AUXADC_RQST_INTER4_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER4_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER4_SHIFT 3
+#define PMIC_AUXADC_RQST_INTER5_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER5_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER5_SHIFT 4
+#define PMIC_AUXADC_RQST_INTER6_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER6_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER6_SHIFT 5
+#define PMIC_AUXADC_RQST_INTER7_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER7_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER7_SHIFT 6
+#define PMIC_AUXADC_RQST_INTER8_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER8_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER8_SHIFT 7
+#define PMIC_AUXADC_RQST_INTER9_ADDR \
+ MT6389_AUXADC_RQST3
+#define PMIC_AUXADC_RQST_INTER9_MASK 0x1
+#define PMIC_AUXADC_RQST_INTER9_SHIFT 8
+#define PMIC_AUXADC_RQST_TREF_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_TREF_MASK 0x1
+#define PMIC_AUXADC_RQST_TREF_SHIFT 0
+#define PMIC_AUXADC_RQST_EXT1_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT1_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT1_SHIFT 1
+#define PMIC_AUXADC_RQST_EXT2_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT2_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT2_SHIFT 2
+#define PMIC_AUXADC_RQST_EXT3_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT3_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT3_SHIFT 3
+#define PMIC_AUXADC_RQST_EXT4_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT4_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT4_SHIFT 4
+#define PMIC_AUXADC_RQST_EXT5_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT5_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT5_SHIFT 5
+#define PMIC_AUXADC_RQST_EXT6_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT6_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT6_SHIFT 6
+#define PMIC_AUXADC_RQST_EXT7_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT7_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT7_SHIFT 7
+#define PMIC_AUXADC_RQST_EXT8_ADDR \
+ MT6389_AUXADC_RQST4
+#define PMIC_AUXADC_RQST_EXT8_MASK 0x1
+#define PMIC_AUXADC_RQST_EXT8_SHIFT 8
+#define PMIC_AUXADC_DIG_3_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_ID
+#define PMIC_AUXADC_DIG_3_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_3_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_3_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_ID
+#define PMIC_AUXADC_DIG_3_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_3_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_REV0
+#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_REV0
+#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_REV0
+#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_REV0
+#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_3_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_DBI
+#define PMIC_AUXADC_DIG_3_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_3_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_3_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_DBI
+#define PMIC_AUXADC_DIG_3_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_3_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_3_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_DBI
+#define PMIC_AUXADC_DIG_3_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_3_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_3_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_3_DSN_DXI
+#define PMIC_AUXADC_DIG_3_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_3_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_CK_ON_EXTD_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_CK_ON_EXTD_MASK 0x3F
+#define PMIC_AUXADC_CK_ON_EXTD_SHIFT 0
+#define PMIC_AUXADC_SRCLKEN_SRC_SEL_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_SRCLKEN_SRC_SEL_MASK 0x3
+#define PMIC_AUXADC_SRCLKEN_SRC_SEL_SHIFT 6
+#define PMIC_AUXADC_ADC_PWDB_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_ADC_PWDB_MASK 0x1
+#define PMIC_AUXADC_ADC_PWDB_SHIFT 8
+#define PMIC_AUXADC_ADC_PWDB_SWCTRL_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_ADC_PWDB_SWCTRL_MASK 0x1
+#define PMIC_AUXADC_ADC_PWDB_SWCTRL_SHIFT 9
+#define PMIC_AUXADC_STRUP_CK_ON_ENB_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_STRUP_CK_ON_ENB_MASK 0x1
+#define PMIC_AUXADC_STRUP_CK_ON_ENB_SHIFT 10
+#define PMIC_AUXADC_SRCLKEN_CK_EN_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_SRCLKEN_CK_EN_MASK 0x1
+#define PMIC_AUXADC_SRCLKEN_CK_EN_SHIFT 12
+#define PMIC_AUXADC_CK_AON_GPS_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_CK_AON_GPS_MASK 0x1
+#define PMIC_AUXADC_CK_AON_GPS_SHIFT 13
+#define PMIC_AUXADC_CK_AON_MD_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_CK_AON_MD_MASK 0x1
+#define PMIC_AUXADC_CK_AON_MD_SHIFT 14
+#define PMIC_AUXADC_CK_AON_ADDR \
+ MT6389_AUXADC_CON0
+#define PMIC_AUXADC_CK_AON_MASK 0x1
+#define PMIC_AUXADC_CK_AON_SHIFT 15
+#define PMIC_AUXADC_CON0_SET_ADDR \
+ MT6389_AUXADC_CON0_SET
+#define PMIC_AUXADC_CON0_SET_MASK 0xFFFF
+#define PMIC_AUXADC_CON0_SET_SHIFT 0
+#define PMIC_AUXADC_CON0_CLR_ADDR \
+ MT6389_AUXADC_CON0_CLR
+#define PMIC_AUXADC_CON0_CLR_MASK 0xFFFF
+#define PMIC_AUXADC_CON0_CLR_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_SMALL_ADDR \
+ MT6389_AUXADC_CON1
+#define PMIC_AUXADC_AVG_NUM_SMALL_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_SMALL_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_LARGE_ADDR \
+ MT6389_AUXADC_CON1
+#define PMIC_AUXADC_AVG_NUM_LARGE_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_LARGE_SHIFT 3
+#define PMIC_AUXADC_SPL_NUM_SMALL_ADDR \
+ MT6389_AUXADC_CON1
+#define PMIC_AUXADC_SPL_NUM_SMALL_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_SMALL_SHIFT 6
+#define PMIC_AUXADC_AVG_NUM_SEL_ADDR \
+ MT6389_AUXADC_CON2
+#define PMIC_AUXADC_AVG_NUM_SEL_MASK 0xFFF
+#define PMIC_AUXADC_AVG_NUM_SEL_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_ADDR \
+ MT6389_AUXADC_CON2
+#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_MASK 0x1
+#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_SHIFT 12
+#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_ADDR \
+ MT6389_AUXADC_CON2
+#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_MASK 0x1
+#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_SHIFT 13
+#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_ADDR \
+ MT6389_AUXADC_CON2
+#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_MASK 0x1
+#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_SHIFT 14
+#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_ADDR \
+ MT6389_AUXADC_CON2
+#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_SHIFT 15
+#define PMIC_AUXADC_SPL_NUM_LARGE_ADDR \
+ MT6389_AUXADC_CON3
+#define PMIC_AUXADC_SPL_NUM_LARGE_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_LARGE_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_SLEEP_ADDR \
+ MT6389_AUXADC_CON4
+#define PMIC_AUXADC_SPL_NUM_SLEEP_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_SLEEP_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_ADDR \
+ MT6389_AUXADC_CON4
+#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_MASK 0x1
+#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_SHIFT 15
+#define PMIC_AUXADC_SPL_NUM_SEL_ADDR \
+ MT6389_AUXADC_CON5
+#define PMIC_AUXADC_SPL_NUM_SEL_MASK 0xFFF
+#define PMIC_AUXADC_SPL_NUM_SEL_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_ADDR \
+ MT6389_AUXADC_CON5
+#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_MASK 0x1
+#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_SHIFT 12
+#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_ADDR \
+ MT6389_AUXADC_CON5
+#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_MASK 0x1
+#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_SHIFT 13
+#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_ADDR \
+ MT6389_AUXADC_CON5
+#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_MASK 0x1
+#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_SHIFT 14
+#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_ADDR \
+ MT6389_AUXADC_CON5
+#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_MASK 0x1
+#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_SHIFT 15
+#define PMIC_AUXADC_SPL_NUM_CH0_ADDR \
+ MT6389_AUXADC_CON6
+#define PMIC_AUXADC_SPL_NUM_CH0_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH0_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH3_ADDR \
+ MT6389_AUXADC_CON7
+#define PMIC_AUXADC_SPL_NUM_CH3_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH3_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH7_ADDR \
+ MT6389_AUXADC_CON8
+#define PMIC_AUXADC_SPL_NUM_CH7_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH7_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH6_ADDR \
+ MT6389_AUXADC_CON9
+#define PMIC_AUXADC_SPL_NUM_CH6_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH6_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH8_ADDR \
+ MT6389_AUXADC_CON10
+#define PMIC_AUXADC_SPL_NUM_CH8_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH8_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH12_ADDR \
+ MT6389_AUXADC_CON11
+#define PMIC_AUXADC_SPL_NUM_CH12_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH12_SHIFT 0
+#define PMIC_AUXADC_SPL_NUM_CH13_ADDR \
+ MT6389_AUXADC_CON12
+#define PMIC_AUXADC_SPL_NUM_CH13_MASK 0x3FF
+#define PMIC_AUXADC_SPL_NUM_CH13_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_CH12_ADDR \
+ MT6389_AUXADC_AVG_NUM0
+#define PMIC_AUXADC_AVG_NUM_CH12_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH12_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_LBAT_ADDR \
+ MT6389_AUXADC_AVG_NUM0
+#define PMIC_AUXADC_AVG_NUM_LBAT_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_LBAT_SHIFT 4
+#define PMIC_AUXADC_AVG_NUM_CH7_ADDR \
+ MT6389_AUXADC_AVG_NUM0
+#define PMIC_AUXADC_AVG_NUM_CH7_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH7_SHIFT 7
+#define PMIC_AUXADC_AVG_NUM_CH3_ADDR \
+ MT6389_AUXADC_AVG_NUM0
+#define PMIC_AUXADC_AVG_NUM_CH3_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH3_SHIFT 10
+#define PMIC_AUXADC_AVG_NUM_CH0_ADDR \
+ MT6389_AUXADC_AVG_NUM0
+#define PMIC_AUXADC_AVG_NUM_CH0_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH0_SHIFT 13
+#define PMIC_AUXADC_AVG_NUM_CH13_ADDR \
+ MT6389_AUXADC_AVG_NUM1
+#define PMIC_AUXADC_AVG_NUM_CH13_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH13_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_HPC_ADDR \
+ MT6389_AUXADC_AVG_NUM1
+#define PMIC_AUXADC_AVG_NUM_HPC_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_HPC_SHIFT 4
+#define PMIC_AUXADC_AVG_NUM_DCXO_ADDR \
+ MT6389_AUXADC_AVG_NUM1
+#define PMIC_AUXADC_AVG_NUM_DCXO_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_DCXO_SHIFT 7
+#define PMIC_AUXADC_AVG_NUM_CH7_WAKEUP_ADDR \
+ MT6389_AUXADC_AVG_NUM1
+#define PMIC_AUXADC_AVG_NUM_CH7_WAKEUP_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH7_WAKEUP_SHIFT 10
+#define PMIC_AUXADC_AVG_NUM_BTMP_ADDR \
+ MT6389_AUXADC_AVG_NUM1
+#define PMIC_AUXADC_AVG_NUM_BTMP_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_BTMP_SHIFT 13
+#define PMIC_AUXADC_AVG_NUM_NAG_ADDR \
+ MT6389_AUXADC_AVG_NUM2
+#define PMIC_AUXADC_AVG_NUM_NAG_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_NAG_SHIFT 0
+#define PMIC_AUXADC_AVG_NUM_DCXO_WAKEUP_ADDR \
+ MT6389_AUXADC_AVG_NUM2
+#define PMIC_AUXADC_AVG_NUM_DCXO_WAKEUP_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_DCXO_WAKEUP_SHIFT 4
+#define PMIC_AUXADC_AVG_NUM_CH8_ADDR \
+ MT6389_AUXADC_AVG_NUM2
+#define PMIC_AUXADC_AVG_NUM_CH8_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH8_SHIFT 7
+#define PMIC_AUXADC_AVG_NUM_CH6_ADDR \
+ MT6389_AUXADC_AVG_NUM2
+#define PMIC_AUXADC_AVG_NUM_CH6_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_CH6_SHIFT 10
+#define PMIC_AUXADC_AVG_NUM_ZCV_ADDR \
+ MT6389_AUXADC_AVG_NUM2
+#define PMIC_AUXADC_AVG_NUM_ZCV_MASK 0x7
+#define PMIC_AUXADC_AVG_NUM_ZCV_SHIFT 13
+#define PMIC_AUXADC_TRIM_CH0_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL0
+#define PMIC_AUXADC_TRIM_CH0_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH0_SEL_SHIFT 0
+#define PMIC_AUXADC_TRIM_CH1_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL0
+#define PMIC_AUXADC_TRIM_CH1_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH1_SEL_SHIFT 4
+#define PMIC_AUXADC_TRIM_CH2_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL0
+#define PMIC_AUXADC_TRIM_CH2_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH2_SEL_SHIFT 8
+#define PMIC_AUXADC_TRIM_CH3_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL0
+#define PMIC_AUXADC_TRIM_CH3_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH3_SEL_SHIFT 12
+#define PMIC_AUXADC_TRIM_CH4_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL1
+#define PMIC_AUXADC_TRIM_CH4_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH4_SEL_SHIFT 0
+#define PMIC_AUXADC_TRIM_CH5_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL1
+#define PMIC_AUXADC_TRIM_CH5_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH5_SEL_SHIFT 4
+#define PMIC_AUXADC_TRIM_CH6_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL1
+#define PMIC_AUXADC_TRIM_CH6_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH6_SEL_SHIFT 8
+#define PMIC_AUXADC_TRIM_CH7_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL1
+#define PMIC_AUXADC_TRIM_CH7_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH7_SEL_SHIFT 12
+#define PMIC_AUXADC_TRIM_CH8_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL2
+#define PMIC_AUXADC_TRIM_CH8_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH8_SEL_SHIFT 0
+#define PMIC_AUXADC_TRIM_CH9_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL2
+#define PMIC_AUXADC_TRIM_CH9_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH9_SEL_SHIFT 4
+#define PMIC_AUXADC_TRIM_CH10_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL2
+#define PMIC_AUXADC_TRIM_CH10_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH10_SEL_SHIFT 8
+#define PMIC_AUXADC_TRIM_CH11_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL2
+#define PMIC_AUXADC_TRIM_CH11_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH11_SEL_SHIFT 12
+#define PMIC_AUXADC_TRIM_CH12_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL3
+#define PMIC_AUXADC_TRIM_CH12_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH12_SEL_SHIFT 0
+#define PMIC_AUXADC_TRIM_CH13_SEL_ADDR \
+ MT6389_AUXADC_TRIM_SEL3
+#define PMIC_AUXADC_TRIM_CH13_SEL_MASK 0x7
+#define PMIC_AUXADC_TRIM_CH13_SEL_SHIFT 4
+#define PMIC_AUXADC_ADC_2S_COMP_ENB_ADDR \
+ MT6389_AUXADC_TRIM_SEL3
+#define PMIC_AUXADC_ADC_2S_COMP_ENB_MASK 0x1
+#define PMIC_AUXADC_ADC_2S_COMP_ENB_SHIFT 14
+#define PMIC_AUXADC_ADC_TRIM_COMP_ADDR \
+ MT6389_AUXADC_TRIM_SEL3
+#define PMIC_AUXADC_ADC_TRIM_COMP_MASK 0x1
+#define PMIC_AUXADC_ADC_TRIM_COMP_SHIFT 15
+#define PMIC_AUXADC_RNG_EN_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_RNG_EN_MASK 0x1
+#define PMIC_AUXADC_RNG_EN_SHIFT 0
+#define PMIC_AUXADC_TEST_MODE_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_TEST_MODE_MASK 0x1
+#define PMIC_AUXADC_TEST_MODE_SHIFT 3
+#define PMIC_AUXADC_BIT_SEL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_BIT_SEL_MASK 0x1
+#define PMIC_AUXADC_BIT_SEL_SHIFT 4
+#define PMIC_AUXADC_START_SW_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_START_SW_MASK 0x1
+#define PMIC_AUXADC_START_SW_SHIFT 5
+#define PMIC_AUXADC_START_SWCTRL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_START_SWCTRL_MASK 0x1
+#define PMIC_AUXADC_START_SWCTRL_SHIFT 6
+#define PMIC_AUXADC_TS_VBE_SEL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_TS_VBE_SEL_MASK 0x7
+#define PMIC_AUXADC_TS_VBE_SEL_SHIFT 7
+#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_MASK 0x1
+#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_SHIFT 10
+#define PMIC_AUXADC_VBUF_EN_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_VBUF_EN_MASK 0x1
+#define PMIC_AUXADC_VBUF_EN_SHIFT 11
+#define PMIC_AUXADC_VBUF_EN_SWCTRL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_VBUF_EN_SWCTRL_MASK 0x1
+#define PMIC_AUXADC_VBUF_EN_SWCTRL_SHIFT 12
+#define PMIC_AUXADC_OUT_SEL_ADDR \
+ MT6389_AUXADC_CON13
+#define PMIC_AUXADC_OUT_SEL_MASK 0x1
+#define PMIC_AUXADC_OUT_SEL_SHIFT 13
+#define PMIC_AUXADC_DA_DAC_ADDR \
+ MT6389_AUXADC_CON14
+#define PMIC_AUXADC_DA_DAC_MASK 0xFFF
+#define PMIC_AUXADC_DA_DAC_SHIFT 0
+#define PMIC_AUXADC_DA_DAC_SWCTRL_ADDR \
+ MT6389_AUXADC_CON14
+#define PMIC_AUXADC_DA_DAC_SWCTRL_MASK 0x1
+#define PMIC_AUXADC_DA_DAC_SWCTRL_SHIFT 12
+#define PMIC_AD_AUXADC_COMP_ADDR \
+ MT6389_AUXADC_CON14
+#define PMIC_AD_AUXADC_COMP_MASK 0x1
+#define PMIC_AD_AUXADC_COMP_SHIFT 15
+#define PMIC_AUXADC_ADCIN_VSEN_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_VSEN_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_VSEN_EN_SHIFT 0
+#define PMIC_AUXADC_ADCIN_VBAT_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_VBAT_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_VBAT_EN_SHIFT 1
+#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT 2
+#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_SHIFT 3
+#define PMIC_AUXADC_ADCIN_CHR_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_CHR_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_CHR_EN_SHIFT 4
+#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_SHIFT 5
+#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
+#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_SHIFT 6
+#define PMIC_AUXADC_XO_THADC_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_XO_THADC_EN_MASK 0x1
+#define PMIC_AUXADC_XO_THADC_EN_SHIFT 7
+#define PMIC_AUXADC_ADCIN_BATID_SW_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_ADCIN_BATID_SW_EN_MASK 0x1
+#define PMIC_AUXADC_ADCIN_BATID_SW_EN_SHIFT 8
+#define PMIC_AUXADC_VXO22_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_VXO22_EN_MASK 0x1
+#define PMIC_AUXADC_VXO22_EN_SHIFT 9
+#define PMIC_AUXADC_DIG0_RSV0_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_DIG0_RSV0_MASK 0x1
+#define PMIC_AUXADC_DIG0_RSV0_SHIFT 10
+#define PMIC_AUXADC_CHSEL_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_CHSEL_MASK 0xF
+#define PMIC_AUXADC_CHSEL_SHIFT 11
+#define PMIC_AUXADC_SWCTRL_EN_ADDR \
+ MT6389_AUXADC_CON15
+#define PMIC_AUXADC_SWCTRL_EN_MASK 0x1
+#define PMIC_AUXADC_SWCTRL_EN_SHIFT 15
+#define PMIC_AUXADC_SOURCE_LBAT_SEL_ADDR \
+ MT6389_AUXADC_CON16
+#define PMIC_AUXADC_SOURCE_LBAT_SEL_MASK 0x1
+#define PMIC_AUXADC_SOURCE_LBAT_SEL_SHIFT 0
+#define PMIC_AUXADC_SOURCE_LBAT2_SEL_ADDR \
+ MT6389_AUXADC_CON16
+#define PMIC_AUXADC_SOURCE_LBAT2_SEL_MASK 0x1
+#define PMIC_AUXADC_SOURCE_LBAT2_SEL_SHIFT 1
+#define PMIC_AUXADC_START_EXTD_ADDR \
+ MT6389_AUXADC_CON16
+#define PMIC_AUXADC_START_EXTD_MASK 0x7F
+#define PMIC_AUXADC_START_EXTD_SHIFT 2
+#define PMIC_AUXADC_DAC_EXTD_ADDR \
+ MT6389_AUXADC_CON16
+#define PMIC_AUXADC_DAC_EXTD_MASK 0xF
+#define PMIC_AUXADC_DAC_EXTD_SHIFT 11
+#define PMIC_AUXADC_DAC_EXTD_EN_ADDR \
+ MT6389_AUXADC_CON16
+#define PMIC_AUXADC_DAC_EXTD_EN_MASK 0x1
+#define PMIC_AUXADC_DAC_EXTD_EN_SHIFT 15
+#define PMIC_AUXADC_START_SHADE_NUM_ADDR \
+ MT6389_AUXADC_CON18
+#define PMIC_AUXADC_START_SHADE_NUM_MASK 0x3FF
+#define PMIC_AUXADC_START_SHADE_NUM_SHIFT 0
+#define PMIC_AUXADC_START_SHADE_EN_ADDR \
+ MT6389_AUXADC_CON18
+#define PMIC_AUXADC_START_SHADE_EN_MASK 0x1
+#define PMIC_AUXADC_START_SHADE_EN_SHIFT 14
+#define PMIC_AUXADC_START_SHADE_SEL_ADDR \
+ MT6389_AUXADC_CON18
+#define PMIC_AUXADC_START_SHADE_SEL_MASK 0x1
+#define PMIC_AUXADC_START_SHADE_SEL_SHIFT 15
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_SHIFT 1
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_SHIFT 2
+#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_SHIFT 3
+#define PMIC_AUXADC_DIG0_RSV1_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_DIG0_RSV1_MASK 0x7
+#define PMIC_AUXADC_DIG0_RSV1_SHIFT 8
+#define PMIC_AUXADC_STATE_CS_S_ADDR \
+ MT6389_AUXADC_CON19
+#define PMIC_AUXADC_STATE_CS_S_MASK 0xF
+#define PMIC_AUXADC_STATE_CS_S_SHIFT 12
+#define PMIC_AUXADC_DATA_REUSE_SEL_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_DATA_REUSE_SEL_MASK 0x3
+#define PMIC_AUXADC_DATA_REUSE_SEL_SHIFT 0
+#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_MASK 0x3
+#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_SHIFT 2
+#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_MASK 0x3
+#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_SHIFT 4
+#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_MASK 0x3
+#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_SHIFT 6
+#define PMIC_AUXADC_DATA_REUSE_EN_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_DATA_REUSE_EN_MASK 0x1
+#define PMIC_AUXADC_DATA_REUSE_EN_SHIFT 8
+#define PMIC_AUXADC_CH0_DATA_REUSE_EN_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_CH0_DATA_REUSE_EN_MASK 0x1
+#define PMIC_AUXADC_CH0_DATA_REUSE_EN_SHIFT 9
+#define PMIC_AUXADC_CH1_DATA_REUSE_EN_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_CH1_DATA_REUSE_EN_MASK 0x1
+#define PMIC_AUXADC_CH1_DATA_REUSE_EN_SHIFT 10
+#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_ADDR \
+ MT6389_AUXADC_CON20
+#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_MASK 0x1
+#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_SHIFT 11
+#define PMIC_AUXADC_AUTORPT_PRD_ADDR \
+ MT6389_AUXADC_AUTORPT0
+#define PMIC_AUXADC_AUTORPT_PRD_MASK 0x3FF
+#define PMIC_AUXADC_AUTORPT_PRD_SHIFT 0
+#define PMIC_AUXADC_AUTORPT_EN_ADDR \
+ MT6389_AUXADC_AUTORPT0
+#define PMIC_AUXADC_AUTORPT_EN_MASK 0x1
+#define PMIC_AUXADC_AUTORPT_EN_SHIFT 15
+#define PMIC_AUXADC_ACCDET_AUTO_SPL_ADDR \
+ MT6389_AUXADC_ACCDET
+#define PMIC_AUXADC_ACCDET_AUTO_SPL_MASK 0x1
+#define PMIC_AUXADC_ACCDET_AUTO_SPL_SHIFT 0
+#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \
+ MT6389_AUXADC_ACCDET
+#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
+#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT 1
+#define PMIC_AUXADC_ACCDET_DIG1_RSV0_ADDR \
+ MT6389_AUXADC_ACCDET
+#define PMIC_AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F
+#define PMIC_AUXADC_ACCDET_DIG1_RSV0_SHIFT 2
+#define PMIC_AUXADC_ACCDET_DIG0_RSV0_ADDR \
+ MT6389_AUXADC_ACCDET
+#define PMIC_AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF
+#define PMIC_AUXADC_ACCDET_DIG0_RSV0_SHIFT 8
+#define PMIC_AUXADC_FGADC_START_SW_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_FGADC_START_SW_MASK 0x1
+#define PMIC_AUXADC_FGADC_START_SW_SHIFT 0
+#define PMIC_AUXADC_FGADC_START_SEL_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_FGADC_START_SEL_MASK 0x1
+#define PMIC_AUXADC_FGADC_START_SEL_SHIFT 1
+#define PMIC_AUXADC_IMP_FGADC_R_SW_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_IMP_FGADC_R_SW_MASK 0x1
+#define PMIC_AUXADC_IMP_FGADC_R_SW_SHIFT 2
+#define PMIC_AUXADC_IMP_FGADC_R_SEL_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_IMP_FGADC_R_SEL_MASK 0x1
+#define PMIC_AUXADC_IMP_FGADC_R_SEL_SHIFT 3
+#define PMIC_AUXADC_BAT_PLUGIN_START_SW_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_BAT_PLUGIN_START_SW_MASK 0x1
+#define PMIC_AUXADC_BAT_PLUGIN_START_SW_SHIFT 4
+#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_MASK 0x1
+#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_SHIFT 5
+#define PMIC_AUXADC_DBG_DIG0_RSV2_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_DBG_DIG0_RSV2_MASK 0xF
+#define PMIC_AUXADC_DBG_DIG0_RSV2_SHIFT 6
+#define PMIC_AUXADC_DBG_DIG1_RSV2_ADDR \
+ MT6389_AUXADC_DBG0
+#define PMIC_AUXADC_DBG_DIG1_RSV2_MASK 0x3F
+#define PMIC_AUXADC_DBG_DIG1_RSV2_SHIFT 10
+#define PMIC_AUXADC_DIG_3_ELR_LEN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR_NUM
+#define PMIC_AUXADC_DIG_3_ELR_LEN_MASK 0xFF
+#define PMIC_AUXADC_DIG_3_ELR_LEN_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH7_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR0
+#define PMIC_EFUSE_GAIN_CH7_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH7_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR1
+#define PMIC_EFUSE_OFFSET_CH7_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH4_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR2
+#define PMIC_EFUSE_GAIN_CH4_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH4_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR3
+#define PMIC_EFUSE_OFFSET_CH4_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH0_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR4
+#define PMIC_EFUSE_GAIN_CH0_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH0_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR5
+#define PMIC_EFUSE_OFFSET_CH0_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT 0
+#define PMIC_AUXADC_SW_GAIN_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR6
+#define PMIC_AUXADC_SW_GAIN_TRIM_MASK 0x7FFF
+#define PMIC_AUXADC_SW_GAIN_TRIM_SHIFT 0
+#define PMIC_AUXADC_SW_OFFSET_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR7
+#define PMIC_AUXADC_SW_OFFSET_TRIM_MASK 0x7FFF
+#define PMIC_AUXADC_SW_OFFSET_TRIM_SHIFT 0
+#define PMIC_AUXADC_EFUSE_ID_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_ID_MASK 0x1
+#define PMIC_AUXADC_EFUSE_ID_SHIFT 0
+#define PMIC_AUXADC_EFUSE_O_SLOPE_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_O_SLOPE_MASK 0x3F
+#define PMIC_AUXADC_EFUSE_O_SLOPE_SHIFT 1
+#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_MASK 0x1
+#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_SHIFT 7
+#define PMIC_AUXADC_EFUSE_DEGC_CALI_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_DEGC_CALI_MASK 0x3F
+#define PMIC_AUXADC_EFUSE_DEGC_CALI_SHIFT 8
+#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_MASK 0x1
+#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_SHIFT 14
+#define PMIC_AUXADC_EFUSE_RSV0_ADDR \
+ MT6389_AUXADC_DIG_3_ELR8
+#define PMIC_AUXADC_EFUSE_RSV0_MASK 0x1
+#define PMIC_AUXADC_EFUSE_RSV0_SHIFT 15
+#define PMIC_AUXADC_EFUSE_O_VTS_ADDR \
+ MT6389_AUXADC_DIG_3_ELR9
+#define PMIC_AUXADC_EFUSE_O_VTS_MASK 0x1FFF
+#define PMIC_AUXADC_EFUSE_O_VTS_SHIFT 0
+#define PMIC_AUXADC_EFUSE_RSV1_ADDR \
+ MT6389_AUXADC_DIG_3_ELR9
+#define PMIC_AUXADC_EFUSE_RSV1_MASK 0x7
+#define PMIC_AUXADC_EFUSE_RSV1_SHIFT 13
+#define PMIC_AUXADC_EFUSE_O_VTS_2_ADDR \
+ MT6389_AUXADC_DIG_3_ELR10
+#define PMIC_AUXADC_EFUSE_O_VTS_2_MASK 0x1FFF
+#define PMIC_AUXADC_EFUSE_O_VTS_2_SHIFT 0
+#define PMIC_AUXADC_EFUSE_RSV2_ADDR \
+ MT6389_AUXADC_DIG_3_ELR10
+#define PMIC_AUXADC_EFUSE_RSV2_MASK 0x7
+#define PMIC_AUXADC_EFUSE_RSV2_SHIFT 13
+#define PMIC_AUXADC_EFUSE_O_VTS_3_ADDR \
+ MT6389_AUXADC_DIG_3_ELR11
+#define PMIC_AUXADC_EFUSE_O_VTS_3_MASK 0x1FFF
+#define PMIC_AUXADC_EFUSE_O_VTS_3_SHIFT 0
+#define PMIC_AUXADC_EFUSE_RSV3_ADDR \
+ MT6389_AUXADC_DIG_3_ELR11
+#define PMIC_AUXADC_EFUSE_RSV3_MASK 0x7
+#define PMIC_AUXADC_EFUSE_RSV3_SHIFT 13
+#define PMIC_AUXADC_EFUSE_O_VTS_4_ADDR \
+ MT6389_AUXADC_DIG_3_ELR12
+#define PMIC_AUXADC_EFUSE_O_VTS_4_MASK 0x1FFF
+#define PMIC_AUXADC_EFUSE_O_VTS_4_SHIFT 0
+#define PMIC_AUXADC_EFUSE_RSV4_ADDR \
+ MT6389_AUXADC_DIG_3_ELR12
+#define PMIC_AUXADC_EFUSE_RSV4_MASK 0x7
+#define PMIC_AUXADC_EFUSE_RSV4_SHIFT 13
+#define PMIC_AUXADC_EFUSE_GAIN_AUX_ADDR \
+ MT6389_AUXADC_DIG_3_ELR13
+#define PMIC_AUXADC_EFUSE_GAIN_AUX_MASK 0xFF
+#define PMIC_AUXADC_EFUSE_GAIN_AUX_SHIFT 0
+#define PMIC_AUXADC_EFUSE_RSV5_ADDR \
+ MT6389_AUXADC_DIG_3_ELR13
+#define PMIC_AUXADC_EFUSE_RSV5_MASK 0xFF
+#define PMIC_AUXADC_EFUSE_RSV5_SHIFT 8
+#define PMIC_AUXADC_EFUSE_GAIN_BGRL_ADDR \
+ MT6389_AUXADC_DIG_3_ELR14
+#define PMIC_AUXADC_EFUSE_GAIN_BGRL_MASK 0x7F
+#define PMIC_AUXADC_EFUSE_GAIN_BGRL_SHIFT 0
+#define PMIC_AUXADC_EFUSE_GAIN_BGRH_ADDR \
+ MT6389_AUXADC_DIG_3_ELR14
+#define PMIC_AUXADC_EFUSE_GAIN_BGRH_MASK 0x7F
+#define PMIC_AUXADC_EFUSE_GAIN_BGRH_SHIFT 7
+#define PMIC_AUXADC_EFUSE_RSV6_ADDR \
+ MT6389_AUXADC_DIG_3_ELR14
+#define PMIC_AUXADC_EFUSE_RSV6_MASK 0x3
+#define PMIC_AUXADC_EFUSE_RSV6_SHIFT 14
+#define PMIC_AUXADC_EFUSE_CALI_FROM_EFUSE_EN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_CALI_FROM_EFUSE_EN_MASK 0x1
+#define PMIC_AUXADC_EFUSE_CALI_FROM_EFUSE_EN_SHIFT 0
+#define PMIC_AUXADC_EFUSE_ADC_BGRCALI_EN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_ADC_BGRCALI_EN_MASK 0x1
+#define PMIC_AUXADC_EFUSE_ADC_BGRCALI_EN_SHIFT 1
+#define PMIC_AUXADC_EFUSE_ADC_AUXCALI_EN_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_ADC_AUXCALI_EN_MASK 0x1
+#define PMIC_AUXADC_EFUSE_ADC_AUXCALI_EN_SHIFT 2
+#define PMIC_AUXADC_EFUSE_TRMPL_CALI_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_TRMPL_CALI_MASK 0x7
+#define PMIC_AUXADC_EFUSE_TRMPL_CALI_SHIFT 3
+#define PMIC_AUXADC_EFUSE_TRMPH_CALI_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_TRMPH_CALI_MASK 0x7
+#define PMIC_AUXADC_EFUSE_TRMPH_CALI_SHIFT 6
+#define PMIC_AUXADC_EFUSE_SIGN_BGRL_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_SIGN_BGRL_MASK 0x1
+#define PMIC_AUXADC_EFUSE_SIGN_BGRL_SHIFT 9
+#define PMIC_AUXADC_EFUSE_SIGN_BGRH_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_SIGN_BGRH_MASK 0x1
+#define PMIC_AUXADC_EFUSE_SIGN_BGRH_SHIFT 10
+#define PMIC_AUXADC_EFUSE_SIGN_AUX_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_SIGN_AUX_MASK 0x1
+#define PMIC_AUXADC_EFUSE_SIGN_AUX_SHIFT 11
+#define PMIC_AUXADC_EFUSE_RSV7_ADDR \
+ MT6389_AUXADC_DIG_3_ELR15
+#define PMIC_AUXADC_EFUSE_RSV7_MASK 0xF
+#define PMIC_AUXADC_EFUSE_RSV7_SHIFT 12
+#define PMIC_AUXADC_EFUSE_VBG12_ADDR \
+ MT6389_AUXADC_DIG_3_ELR16
+#define PMIC_AUXADC_EFUSE_VBG12_MASK 0x7F
+#define PMIC_AUXADC_EFUSE_VBG12_SHIFT 0
+#define PMIC_AUXADC_EFUSE_VAUX18_ADDR \
+ MT6389_AUXADC_DIG_3_ELR16
+#define PMIC_AUXADC_EFUSE_VAUX18_MASK 0x7F
+#define PMIC_AUXADC_EFUSE_VAUX18_SHIFT 7
+#define PMIC_EFUSE_GAIN_CH13_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR17
+#define PMIC_EFUSE_GAIN_CH13_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH13_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH13_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR18
+#define PMIC_EFUSE_OFFSET_CH13_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH13_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH12_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR19
+#define PMIC_EFUSE_GAIN_CH12_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH12_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH12_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR20
+#define PMIC_EFUSE_OFFSET_CH12_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH12_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH8_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR21
+#define PMIC_EFUSE_GAIN_CH8_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH8_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH8_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR22
+#define PMIC_EFUSE_OFFSET_CH8_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH8_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH6_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR23
+#define PMIC_EFUSE_GAIN_CH6_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH6_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH6_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR24
+#define PMIC_EFUSE_OFFSET_CH6_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH6_TRIM_SHIFT 0
+#define PMIC_EFUSE_GAIN_CH2_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR25
+#define PMIC_EFUSE_GAIN_CH2_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_GAIN_CH2_TRIM_SHIFT 0
+#define PMIC_EFUSE_OFFSET_CH2_TRIM_ADDR \
+ MT6389_AUXADC_DIG_3_ELR26
+#define PMIC_EFUSE_OFFSET_CH2_TRIM_MASK 0x7FFF
+#define PMIC_EFUSE_OFFSET_CH2_TRIM_SHIFT 0
+#define PMIC_AUXADC_DIG_4_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_ID
+#define PMIC_AUXADC_DIG_4_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_4_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_4_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_ID
+#define PMIC_AUXADC_DIG_4_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_4_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_REV0
+#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_REV0
+#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_REV0
+#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_REV0
+#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_4_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_DBI
+#define PMIC_AUXADC_DIG_4_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_4_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_4_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_DBI
+#define PMIC_AUXADC_DIG_4_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_4_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_4_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_DBI
+#define PMIC_AUXADC_DIG_4_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_4_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_4_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_4_DSN_DXI
+#define PMIC_AUXADC_DIG_4_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_4_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_IMP_EN_ADDR \
+ MT6389_AUXADC_IMP0
+#define PMIC_AUXADC_IMP_EN_MASK 0x1
+#define PMIC_AUXADC_IMP_EN_SHIFT 0
+#define PMIC_AUXADC_IMP_PRD_SEL_ADDR \
+ MT6389_AUXADC_IMP1
+#define PMIC_AUXADC_IMP_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_IMP_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_IMP_CNT_SEL_ADDR \
+ MT6389_AUXADC_IMP1
+#define PMIC_AUXADC_IMP_CNT_SEL_MASK 0x3
+#define PMIC_AUXADC_IMP_CNT_SEL_SHIFT 2
+#define PMIC_AUXADC_IMPEDANCE_CHSEL_ADDR \
+ MT6389_AUXADC_IMP1
+#define PMIC_AUXADC_IMPEDANCE_CHSEL_MASK 0x1
+#define PMIC_AUXADC_IMPEDANCE_CHSEL_SHIFT 4
+#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_ADDR \
+ MT6389_AUXADC_IMP1
+#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_MASK 0x1
+#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT 15
+#define PMIC_AUXADC_IMP_START_ADDR \
+ MT6389_AUXADC_IMP2
+#define PMIC_AUXADC_IMP_START_MASK 0x1
+#define PMIC_AUXADC_IMP_START_SHIFT 0
+#define PMIC_AUXADC_IMP_STATE_ADDR \
+ MT6389_AUXADC_IMP2
+#define PMIC_AUXADC_IMP_STATE_MASK 0xF
+#define PMIC_AUXADC_IMP_STATE_SHIFT 1
+#define PMIC_AUXADC_IMP_COUNT_ADDR \
+ MT6389_AUXADC_IMP2
+#define PMIC_AUXADC_IMP_COUNT_MASK 0xF
+#define PMIC_AUXADC_IMP_COUNT_SHIFT 5
+#define PMIC_AUXADC_IMP_FGADC_R_S_ADDR \
+ MT6389_AUXADC_IMP2
+#define PMIC_AUXADC_IMP_FGADC_R_S_MASK 0x1
+#define PMIC_AUXADC_IMP_FGADC_R_S_SHIFT 9
+#define PMIC_FGADC_AUXADC_IMP_R_DONE_S_ADDR \
+ MT6389_AUXADC_IMP2
+#define PMIC_FGADC_AUXADC_IMP_R_DONE_S_MASK 0x1
+#define PMIC_FGADC_AUXADC_IMP_R_DONE_S_SHIFT 10
+#define PMIC_AUXADC_ADC_OUT_IMP_ADDR \
+ MT6389_AUXADC_IMP3
+#define PMIC_AUXADC_ADC_OUT_IMP_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_IMP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_IMP_ADDR \
+ MT6389_AUXADC_IMP3
+#define PMIC_AUXADC_ADC_RDY_IMP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_IMP_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_IMP_AVG_ADDR \
+ MT6389_AUXADC_IMP4
+#define PMIC_AUXADC_ADC_OUT_IMP_AVG_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_IMP_AVG_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_IMP_AVG_ADDR \
+ MT6389_AUXADC_IMP4
+#define PMIC_AUXADC_ADC_RDY_IMP_AVG_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_IMP_AVG_SHIFT 15
+#define PMIC_AUXADC_IMP_CK_SW_EN_ADDR \
+ MT6389_AUXADC_IMP5
+#define PMIC_AUXADC_IMP_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_IMP_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_IMP_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_IMP5
+#define PMIC_AUXADC_IMP_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_IMP_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_IMP_ADDR \
+ MT6389_AUXADC_IMP5
+#define PMIC_AUXADC_ADC_BUSY_IN_IMP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_IMP_SHIFT 15
+#define PMIC_AUXADC_LBAT_EN_ADDR \
+ MT6389_AUXADC_LBAT0
+#define PMIC_AUXADC_LBAT_EN_MASK 0x1
+#define PMIC_AUXADC_LBAT_EN_SHIFT 0
+#define PMIC_AUXADC_LBAT_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_LBAT1
+#define PMIC_AUXADC_LBAT_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_LBAT_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_LBAT1
+#define PMIC_AUXADC_LBAT_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_LBAT_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_LBAT1
+#define PMIC_AUXADC_LBAT_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_LBAT_VOLT_MAX_ADDR \
+ MT6389_AUXADC_LBAT2
+#define PMIC_AUXADC_LBAT_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_LBAT_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_LBAT2
+#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_LBAT_DET_MAX_ADDR \
+ MT6389_AUXADC_LBAT2
+#define PMIC_AUXADC_LBAT_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_LBAT_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_LBAT_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_LBAT2
+#define PMIC_AUXADC_LBAT_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_LBAT_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_LBAT_VOLT_MIN_ADDR \
+ MT6389_AUXADC_LBAT3
+#define PMIC_AUXADC_LBAT_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_LBAT_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_LBAT3
+#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_LBAT_DET_MIN_ADDR \
+ MT6389_AUXADC_LBAT3
+#define PMIC_AUXADC_LBAT_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_LBAT_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_LBAT_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_LBAT3
+#define PMIC_AUXADC_LBAT_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_LBAT_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_LBAT4
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_LBAT5
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_LBAT_STATE_ADDR \
+ MT6389_AUXADC_LBAT6
+#define PMIC_AUXADC_LBAT_STATE_MASK 0x7
+#define PMIC_AUXADC_LBAT_STATE_SHIFT 12
+#define PMIC_AUXADC_LBAT_AUXADC_START_ADDR \
+ MT6389_AUXADC_LBAT6
+#define PMIC_AUXADC_LBAT_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_LBAT_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_LBAT_ADDR \
+ MT6389_AUXADC_LBAT7
+#define PMIC_AUXADC_ADC_OUT_LBAT_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_LBAT_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_LBAT_ADDR \
+ MT6389_AUXADC_LBAT7
+#define PMIC_AUXADC_ADC_RDY_LBAT_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_LBAT_SHIFT 15
+#define PMIC_AUXADC_LBAT_CK_SW_EN_ADDR \
+ MT6389_AUXADC_LBAT8
+#define PMIC_AUXADC_LBAT_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_LBAT_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_LBAT_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_LBAT8
+#define PMIC_AUXADC_LBAT_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_LBAT_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_ADDR \
+ MT6389_AUXADC_LBAT8
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_SHIFT 15
+#define PMIC_AUXADC_BAT_TEMP_EN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_0
+#define PMIC_AUXADC_BAT_TEMP_EN_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_EN_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_1
+#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_BAT_TEMP_2
+#define PMIC_AUXADC_BAT_TEMP_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_BAT_TEMP_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_BAT_TEMP_2
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_BAT_TEMP_2
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_ADDR \
+ MT6389_AUXADC_BAT_TEMP_3
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_BAT_TEMP_3
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_BAT_TEMP_DET_MAX_ADDR \
+ MT6389_AUXADC_BAT_TEMP_3
+#define PMIC_AUXADC_BAT_TEMP_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_BAT_TEMP_3
+#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_4
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_4
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_BAT_TEMP_DET_MIN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_4
+#define PMIC_AUXADC_BAT_TEMP_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_BAT_TEMP_4
+#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_BAT_TEMP_5
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_6
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_STATE_ADDR \
+ MT6389_AUXADC_BAT_TEMP_7
+#define PMIC_AUXADC_BAT_TEMP_STATE_MASK 0x7
+#define PMIC_AUXADC_BAT_TEMP_STATE_SHIFT 12
+#define PMIC_AUXADC_BAT_TEMP_AUXADC_START_ADDR \
+ MT6389_AUXADC_BAT_TEMP_7
+#define PMIC_AUXADC_BAT_TEMP_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_ADDR \
+ MT6389_AUXADC_BAT_TEMP_8
+#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_ADDR \
+ MT6389_AUXADC_BAT_TEMP_8
+#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_SHIFT 15
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_ADDR \
+ MT6389_AUXADC_BAT_TEMP_9
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_BAT_TEMP_9
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_ADDR \
+ MT6389_AUXADC_BAT_TEMP_9
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_SHIFT 15
+#define PMIC_AUXADC_LBAT2_EN_ADDR \
+ MT6389_AUXADC_LBAT2_0
+#define PMIC_AUXADC_LBAT2_EN_MASK 0x1
+#define PMIC_AUXADC_LBAT2_EN_SHIFT 0
+#define PMIC_AUXADC_LBAT2_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_LBAT2_1
+#define PMIC_AUXADC_LBAT2_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT2_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_LBAT2_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_LBAT2_1
+#define PMIC_AUXADC_LBAT2_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT2_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_LBAT2_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_LBAT2_1
+#define PMIC_AUXADC_LBAT2_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_LBAT2_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_LBAT2_VOLT_MAX_ADDR \
+ MT6389_AUXADC_LBAT2_2
+#define PMIC_AUXADC_LBAT2_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_LBAT2_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_LBAT2_2
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_LBAT2_DET_MAX_ADDR \
+ MT6389_AUXADC_LBAT2_2
+#define PMIC_AUXADC_LBAT2_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_LBAT2_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_LBAT2_2
+#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_LBAT2_VOLT_MIN_ADDR \
+ MT6389_AUXADC_LBAT2_3
+#define PMIC_AUXADC_LBAT2_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_LBAT2_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_LBAT2_3
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_LBAT2_DET_MIN_ADDR \
+ MT6389_AUXADC_LBAT2_3
+#define PMIC_AUXADC_LBAT2_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_LBAT2_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_LBAT2_3
+#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_LBAT2_4
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_LBAT2_5
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_LBAT2_STATE_ADDR \
+ MT6389_AUXADC_LBAT2_6
+#define PMIC_AUXADC_LBAT2_STATE_MASK 0x7
+#define PMIC_AUXADC_LBAT2_STATE_SHIFT 12
+#define PMIC_AUXADC_LBAT2_AUXADC_START_ADDR \
+ MT6389_AUXADC_LBAT2_6
+#define PMIC_AUXADC_LBAT2_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_LBAT2_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_LBAT2_ADDR \
+ MT6389_AUXADC_LBAT2_7
+#define PMIC_AUXADC_ADC_OUT_LBAT2_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_LBAT2_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_LBAT2_ADDR \
+ MT6389_AUXADC_LBAT2_7
+#define PMIC_AUXADC_ADC_RDY_LBAT2_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_LBAT2_SHIFT 15
+#define PMIC_AUXADC_LBAT2_CK_SW_EN_ADDR \
+ MT6389_AUXADC_LBAT2_8
+#define PMIC_AUXADC_LBAT2_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_LBAT2_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_LBAT2_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_LBAT2_8
+#define PMIC_AUXADC_LBAT2_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_LBAT2_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_ADDR \
+ MT6389_AUXADC_LBAT2_8
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT 15
+#define PMIC_AUXADC_THR_EN_ADDR \
+ MT6389_AUXADC_THR0
+#define PMIC_AUXADC_THR_EN_MASK 0x1
+#define PMIC_AUXADC_THR_EN_SHIFT 0
+#define PMIC_AUXADC_THR_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_THR1
+#define PMIC_AUXADC_THR_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_THR_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_THR_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_THR1
+#define PMIC_AUXADC_THR_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_THR_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_THR_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_THR1
+#define PMIC_AUXADC_THR_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_THR_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_THR_VOLT_MAX_ADDR \
+ MT6389_AUXADC_THR2
+#define PMIC_AUXADC_THR_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_THR_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_THR_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_THR2
+#define PMIC_AUXADC_THR_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_THR_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_THR_DET_MAX_ADDR \
+ MT6389_AUXADC_THR2
+#define PMIC_AUXADC_THR_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_THR_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_THR_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_THR2
+#define PMIC_AUXADC_THR_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_THR_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_THR_VOLT_MIN_ADDR \
+ MT6389_AUXADC_THR3
+#define PMIC_AUXADC_THR_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_THR_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_THR_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_THR3
+#define PMIC_AUXADC_THR_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_THR_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_THR_DET_MIN_ADDR \
+ MT6389_AUXADC_THR3
+#define PMIC_AUXADC_THR_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_THR_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_THR_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_THR3
+#define PMIC_AUXADC_THR_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_THR_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_THR4
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_THR5
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_THR_STATE_ADDR \
+ MT6389_AUXADC_THR6
+#define PMIC_AUXADC_THR_STATE_MASK 0x7
+#define PMIC_AUXADC_THR_STATE_SHIFT 12
+#define PMIC_AUXADC_THR_AUXADC_START_ADDR \
+ MT6389_AUXADC_THR6
+#define PMIC_AUXADC_THR_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_THR_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_THR_HW_ADDR \
+ MT6389_AUXADC_THR7
+#define PMIC_AUXADC_ADC_OUT_THR_HW_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_THR_HW_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_THR_HW_ADDR \
+ MT6389_AUXADC_THR7
+#define PMIC_AUXADC_ADC_RDY_THR_HW_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_THR_HW_SHIFT 15
+#define PMIC_AUXADC_THR_CK_SW_EN_ADDR \
+ MT6389_AUXADC_THR8
+#define PMIC_AUXADC_THR_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_THR_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_THR_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_THR8
+#define PMIC_AUXADC_THR_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_THR_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_ADDR \
+ MT6389_AUXADC_THR8
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_SHIFT 15
+#define PMIC_AUXADC_MDRT_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_MDRT_0
+#define PMIC_AUXADC_MDRT_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_MDRT_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_MDRT_DET_EN_ADDR \
+ MT6389_AUXADC_MDRT_0
+#define PMIC_AUXADC_MDRT_DET_EN_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_EN_SHIFT 15
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_ADDR \
+ MT6389_AUXADC_MDRT_1
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_MASK 0xFFF
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_SHIFT 0
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_ADDR \
+ MT6389_AUXADC_MDRT_1
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_SHIFT 15
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_ADDR \
+ MT6389_AUXADC_MDRT_2
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_SHIFT 0
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_ADDR \
+ MT6389_AUXADC_MDRT_2
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_SHIFT 1
+#define PMIC_AUXADC_MDRT_DET_WKUP_EN_ADDR \
+ MT6389_AUXADC_MDRT_2
+#define PMIC_AUXADC_MDRT_DET_WKUP_EN_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_WKUP_EN_SHIFT 2
+#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_ADDR \
+ MT6389_AUXADC_MDRT_2
+#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_MASK 0x1
+#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_SHIFT 3
+#define PMIC_AUXADC_MDRT_STATE_ADDR \
+ MT6389_AUXADC_MDRT_3
+#define PMIC_AUXADC_MDRT_STATE_MASK 0x3
+#define PMIC_AUXADC_MDRT_STATE_SHIFT 0
+#define PMIC_AUXADC_MDRT_START_ADDR \
+ MT6389_AUXADC_MDRT_3
+#define PMIC_AUXADC_MDRT_START_MASK 0x1
+#define PMIC_AUXADC_MDRT_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_MDRT_ADDR \
+ MT6389_AUXADC_MDRT_4
+#define PMIC_AUXADC_ADC_OUT_MDRT_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_MDRT_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_MDRT_ADDR \
+ MT6389_AUXADC_MDRT_4
+#define PMIC_AUXADC_ADC_RDY_MDRT_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_MDRT_SHIFT 15
+#define PMIC_AUXADC_MDRT_CK_SW_EN_ADDR \
+ MT6389_AUXADC_MDRT_5
+#define PMIC_AUXADC_MDRT_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_MDRT_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_MDRT_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_MDRT_5
+#define PMIC_AUXADC_MDRT_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_MDRT_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_ADDR \
+ MT6389_AUXADC_MDRT_5
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_SHIFT 15
+#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_0
+#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_DCXO_MDRT_DET_EN_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_0
+#define PMIC_AUXADC_DCXO_MDRT_DET_EN_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_EN_SHIFT 15
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_MASK 0xFFF
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_SHIFT 0
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_SHIFT 15
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_2
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SHIFT 0
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_2
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_SHIFT 1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_2
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_SHIFT 2
+#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_2
+#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_SHIFT 3
+#define PMIC_AUXADC_DCXO_MDRT_STATE_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_3
+#define PMIC_AUXADC_DCXO_MDRT_STATE_MASK 0x3
+#define PMIC_AUXADC_DCXO_MDRT_STATE_SHIFT 0
+#define PMIC_AUXADC_DCXO_MDRT_START_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_3
+#define PMIC_AUXADC_DCXO_MDRT_START_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_4
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_4
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_SHIFT 15
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_EN_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_5
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_5
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_DCXO_MDRT_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_ADDR \
+ MT6389_AUXADC_DCXO_MDRT_5
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_SHIFT 15
+#define PMIC_AUXADC_RSV_1RSV0_ADDR \
+ MT6389_AUXADC_RSV_1
+#define PMIC_AUXADC_RSV_1RSV0_MASK 0xFFFF
+#define PMIC_AUXADC_RSV_1RSV0_SHIFT 0
+#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_ADDR \
+ MT6389_AUXADC_PRI_NEW
+#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_MASK 0x1
+#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_SHIFT 0
+#define PMIC_AUXADC_DIG_5_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_ID
+#define PMIC_AUXADC_DIG_5_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_5_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_5_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_ID
+#define PMIC_AUXADC_DIG_5_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_5_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_5_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_REV0
+#define PMIC_AUXADC_DIG_5_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_5_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_5_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_REV0
+#define PMIC_AUXADC_DIG_5_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_5_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_5_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_REV0
+#define PMIC_AUXADC_DIG_5_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_5_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_5_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_REV0
+#define PMIC_AUXADC_DIG_5_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_5_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_5_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_DBI
+#define PMIC_AUXADC_DIG_5_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_5_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_5_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_DBI
+#define PMIC_AUXADC_DIG_5_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_5_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_5_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_DBI
+#define PMIC_AUXADC_DIG_5_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_5_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_5_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_5_DSN_DXI
+#define PMIC_AUXADC_DIG_5_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_5_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_ADC_OUT_INTER1_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER1_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER1_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER1_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER1_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER1_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER1_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER1_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER2_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER2_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER2_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER2_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER2_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER2_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER2_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER2_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER3_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER3_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER3_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER3_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER3_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER3_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER3_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER3_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER4_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER4_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER4_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER4_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER4_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER4_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER4_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER4_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER5_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER5_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER5_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER5_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER5_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER5_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER5_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER5_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER6_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER6_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER6_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER6_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER6_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER6_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER6_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER6_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER7_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER7_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER7_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER7_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER7_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER7_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER7_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER7_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER8_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER8_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER8_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER8_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER8_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER8_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER8_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER8_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER9_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER9_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER9_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER9_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER9_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER9_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER9_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER9_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER10_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER10_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER10_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER10_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER10_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER10_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER10_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER10_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER11_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER11_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER11_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER11_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER11_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER11_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER11_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER11_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER12_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER12_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER12_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER12_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER12_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER12_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER12_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER12_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER13_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER13_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER13_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER13_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER13_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER13_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER13_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER13_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER14_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER14_DIV
+#define PMIC_AUXADC_ADC_OUT_INTER14_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER14_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER14_DIV_ADDR \
+ MT6389_AUXADC_ADC_INTER14_DIV
+#define PMIC_AUXADC_ADC_RDY_INTER14_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER14_DIV_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER1_ADDR \
+ MT6389_AUXADC_ADC_INTER1
+#define PMIC_AUXADC_ADC_OUT_INTER1_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER1_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER1_ADDR \
+ MT6389_AUXADC_ADC_INTER1
+#define PMIC_AUXADC_ADC_RDY_INTER1_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER1_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER2_ADDR \
+ MT6389_AUXADC_ADC_INTER2
+#define PMIC_AUXADC_ADC_OUT_INTER2_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER2_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER2_ADDR \
+ MT6389_AUXADC_ADC_INTER2
+#define PMIC_AUXADC_ADC_RDY_INTER2_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER2_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER3_ADDR \
+ MT6389_AUXADC_ADC_INTER3
+#define PMIC_AUXADC_ADC_OUT_INTER3_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER3_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER3_ADDR \
+ MT6389_AUXADC_ADC_INTER3
+#define PMIC_AUXADC_ADC_RDY_INTER3_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER3_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER4_ADDR \
+ MT6389_AUXADC_ADC_INTER4
+#define PMIC_AUXADC_ADC_OUT_INTER4_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER4_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER4_ADDR \
+ MT6389_AUXADC_ADC_INTER4
+#define PMIC_AUXADC_ADC_RDY_INTER4_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER4_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER5_ADDR \
+ MT6389_AUXADC_ADC_INTER5
+#define PMIC_AUXADC_ADC_OUT_INTER5_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER5_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER5_ADDR \
+ MT6389_AUXADC_ADC_INTER5
+#define PMIC_AUXADC_ADC_RDY_INTER5_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER5_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER6_ADDR \
+ MT6389_AUXADC_ADC_INTER6
+#define PMIC_AUXADC_ADC_OUT_INTER6_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER6_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER6_ADDR \
+ MT6389_AUXADC_ADC_INTER6
+#define PMIC_AUXADC_ADC_RDY_INTER6_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER6_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER7_ADDR \
+ MT6389_AUXADC_ADC_INTER7
+#define PMIC_AUXADC_ADC_OUT_INTER7_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER7_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER7_ADDR \
+ MT6389_AUXADC_ADC_INTER7
+#define PMIC_AUXADC_ADC_RDY_INTER7_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER7_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER8_ADDR \
+ MT6389_AUXADC_ADC_INTER8
+#define PMIC_AUXADC_ADC_OUT_INTER8_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER8_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER8_ADDR \
+ MT6389_AUXADC_ADC_INTER8
+#define PMIC_AUXADC_ADC_RDY_INTER8_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER8_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER9_ADDR \
+ MT6389_AUXADC_ADC_INTER9
+#define PMIC_AUXADC_ADC_OUT_INTER9_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER9_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER9_ADDR \
+ MT6389_AUXADC_ADC_INTER9
+#define PMIC_AUXADC_ADC_RDY_INTER9_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER9_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_TREF_ADDR \
+ MT6389_AUXADC_ADC_TREF
+#define PMIC_AUXADC_ADC_OUT_TREF_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_TREF_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_TREF_ADDR \
+ MT6389_AUXADC_ADC_TREF
+#define PMIC_AUXADC_ADC_RDY_TREF_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_TREF_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT1_ADDR \
+ MT6389_AUXADC_ADC_EXT1
+#define PMIC_AUXADC_ADC_OUT_EXT1_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT1_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT1_ADDR \
+ MT6389_AUXADC_ADC_EXT1
+#define PMIC_AUXADC_ADC_RDY_EXT1_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT1_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT2_ADDR \
+ MT6389_AUXADC_ADC_EXT2
+#define PMIC_AUXADC_ADC_OUT_EXT2_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT2_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT2_ADDR \
+ MT6389_AUXADC_ADC_EXT2
+#define PMIC_AUXADC_ADC_RDY_EXT2_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT2_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT3_ADDR \
+ MT6389_AUXADC_ADC_EXT3
+#define PMIC_AUXADC_ADC_OUT_EXT3_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT3_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT3_ADDR \
+ MT6389_AUXADC_ADC_EXT3
+#define PMIC_AUXADC_ADC_RDY_EXT3_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT3_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT4_ADDR \
+ MT6389_AUXADC_ADC_EXT4
+#define PMIC_AUXADC_ADC_OUT_EXT4_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT4_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT4_ADDR \
+ MT6389_AUXADC_ADC_EXT4
+#define PMIC_AUXADC_ADC_RDY_EXT4_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT4_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT5_ADDR \
+ MT6389_AUXADC_ADC_EXT5
+#define PMIC_AUXADC_ADC_OUT_EXT5_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT5_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT5_ADDR \
+ MT6389_AUXADC_ADC_EXT5
+#define PMIC_AUXADC_ADC_RDY_EXT5_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT5_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT6_ADDR \
+ MT6389_AUXADC_ADC_EXT6
+#define PMIC_AUXADC_ADC_OUT_EXT6_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT6_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT6_ADDR \
+ MT6389_AUXADC_ADC_EXT6
+#define PMIC_AUXADC_ADC_RDY_EXT6_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT6_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT7_ADDR \
+ MT6389_AUXADC_ADC_EXT7
+#define PMIC_AUXADC_ADC_OUT_EXT7_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT7_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT7_ADDR \
+ MT6389_AUXADC_ADC_EXT7
+#define PMIC_AUXADC_ADC_RDY_EXT7_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT7_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_EXT8_ADDR \
+ MT6389_AUXADC_ADC_EXT8
+#define PMIC_AUXADC_ADC_OUT_EXT8_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_EXT8_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_EXT8_ADDR \
+ MT6389_AUXADC_ADC_EXT8
+#define PMIC_AUXADC_ADC_RDY_EXT8_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_EXT8_SHIFT 15
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DIV_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DIV_SHIFT 2
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DIV_SHIFT 3
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DIV_SHIFT 4
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DIV_SHIFT 5
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DIV_SHIFT 6
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DIV_SHIFT 7
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DIV_SHIFT 8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DIV_SHIFT 9
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DIV_SHIFT 10
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DIV_SHIFT 11
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DIV_SHIFT 12
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DIV_SHIFT 13
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DIV_ADDR \
+ MT6389_AUXADC_STA_INTER_DIV
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DIV_SHIFT 14
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_SHIFT 2
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_SHIFT 3
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_SHIFT 4
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_SHIFT 5
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_SHIFT 6
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_SHIFT 7
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_SHIFT 8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_ADDR \
+ MT6389_AUXADC_STA_INTER
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_SHIFT 9
+#define PMIC_AUXADC_ADC_BUSY_IN_TREF_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_TREF_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_TREF_SHIFT 0
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT1_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT1_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT1_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT2_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT2_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT2_SHIFT 2
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT3_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT3_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT3_SHIFT 3
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT4_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT4_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT4_SHIFT 4
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT5_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT5_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT5_SHIFT 5
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT6_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT6_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT6_SHIFT 6
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT7_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT7_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT7_SHIFT 7
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT8_ADDR \
+ MT6389_AUXADC_STA_EXT
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT8_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_EXT8_SHIFT 8
+#define PMIC_AUXADC_INTER1_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER1_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DIV_EN_SHIFT 1
+#define PMIC_AUXADC_INTER2_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER2_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DIV_EN_SHIFT 2
+#define PMIC_AUXADC_INTER3_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER3_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DIV_EN_SHIFT 3
+#define PMIC_AUXADC_INTER4_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER4_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DIV_EN_SHIFT 4
+#define PMIC_AUXADC_INTER5_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER5_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DIV_EN_SHIFT 5
+#define PMIC_AUXADC_INTER6_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER6_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DIV_EN_SHIFT 6
+#define PMIC_AUXADC_INTER7_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER7_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DIV_EN_SHIFT 7
+#define PMIC_AUXADC_INTER8_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER8_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DIV_EN_SHIFT 8
+#define PMIC_AUXADC_INTER9_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER9_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DIV_EN_SHIFT 9
+#define PMIC_AUXADC_INTER10_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER10_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER10_DIV_EN_SHIFT 10
+#define PMIC_AUXADC_INTER11_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER11_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER11_DIV_EN_SHIFT 11
+#define PMIC_AUXADC_INTER12_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER12_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER12_DIV_EN_SHIFT 12
+#define PMIC_AUXADC_INTER13_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER13_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER13_DIV_EN_SHIFT 13
+#define PMIC_AUXADC_INTER14_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER_DIV_EN
+#define PMIC_AUXADC_INTER14_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER14_DIV_EN_SHIFT 14
+#define PMIC_AUXADC_INTER1_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER1_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_EN_SHIFT 1
+#define PMIC_AUXADC_INTER2_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER2_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_EN_SHIFT 2
+#define PMIC_AUXADC_INTER3_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER3_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_EN_SHIFT 3
+#define PMIC_AUXADC_INTER4_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER4_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_EN_SHIFT 4
+#define PMIC_AUXADC_INTER5_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER5_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_EN_SHIFT 5
+#define PMIC_AUXADC_INTER6_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER6_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_EN_SHIFT 6
+#define PMIC_AUXADC_INTER7_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER7_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_EN_SHIFT 7
+#define PMIC_AUXADC_INTER8_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER8_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_EN_SHIFT 8
+#define PMIC_AUXADC_INTER9_EN_ADDR \
+ MT6389_AUXADC_INTER_EN
+#define PMIC_AUXADC_INTER9_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_EN_SHIFT 9
+#define PMIC_AUXADC_EXT1_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT1_EN_MASK 0x1
+#define PMIC_AUXADC_EXT1_EN_SHIFT 1
+#define PMIC_AUXADC_EXT2_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT2_EN_MASK 0x1
+#define PMIC_AUXADC_EXT2_EN_SHIFT 2
+#define PMIC_AUXADC_EXT3_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT3_EN_MASK 0x1
+#define PMIC_AUXADC_EXT3_EN_SHIFT 3
+#define PMIC_AUXADC_EXT4_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT4_EN_MASK 0x1
+#define PMIC_AUXADC_EXT4_EN_SHIFT 4
+#define PMIC_AUXADC_EXT5_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT5_EN_MASK 0x1
+#define PMIC_AUXADC_EXT5_EN_SHIFT 5
+#define PMIC_AUXADC_EXT6_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT6_EN_MASK 0x1
+#define PMIC_AUXADC_EXT6_EN_SHIFT 6
+#define PMIC_AUXADC_EXT7_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT7_EN_MASK 0x1
+#define PMIC_AUXADC_EXT7_EN_SHIFT 7
+#define PMIC_AUXADC_EXT8_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_EXT8_EN_MASK 0x1
+#define PMIC_AUXADC_EXT8_EN_SHIFT 8
+#define PMIC_RG_AUXADC_TREF_SW_MODE_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_RG_AUXADC_TREF_SW_MODE_MASK 0x1
+#define PMIC_RG_AUXADC_TREF_SW_MODE_SHIFT 13
+#define PMIC_AUXADC_TREF_SW_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_TREF_SW_EN_MASK 0x1
+#define PMIC_AUXADC_TREF_SW_EN_SHIFT 14
+#define PMIC_AUXADC_TREF_EN_ADDR \
+ MT6389_AUXADC_EXT_EN
+#define PMIC_AUXADC_TREF_EN_MASK 0x1
+#define PMIC_AUXADC_TREF_EN_SHIFT 15
+#define PMIC_AUXADC_DIG_6_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_ID
+#define PMIC_AUXADC_DIG_6_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_6_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_6_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_ID
+#define PMIC_AUXADC_DIG_6_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_6_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_6_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_REV0
+#define PMIC_AUXADC_DIG_6_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_6_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_6_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_REV0
+#define PMIC_AUXADC_DIG_6_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_6_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_6_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_REV0
+#define PMIC_AUXADC_DIG_6_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_6_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_6_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_REV0
+#define PMIC_AUXADC_DIG_6_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_6_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_6_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_DBI
+#define PMIC_AUXADC_DIG_6_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_6_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_6_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_DBI
+#define PMIC_AUXADC_DIG_6_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_6_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_6_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_DBI
+#define PMIC_AUXADC_DIG_6_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_6_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_6_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_6_DSN_DXI
+#define PMIC_AUXADC_DIG_6_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_6_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_NAG_EN_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_EN_MASK 0x1
+#define PMIC_AUXADC_NAG_EN_SHIFT 0
+#define PMIC_AUXADC_NAG_CLR_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_CLR_MASK 0x1
+#define PMIC_AUXADC_NAG_CLR_SHIFT 1
+#define PMIC_AUXADC_NAG_VBAT1_SEL_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_VBAT1_SEL_MASK 0x1
+#define PMIC_AUXADC_NAG_VBAT1_SEL_SHIFT 2
+#define PMIC_AUXADC_NAG_PRD_SEL_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_NAG_PRD_SEL_SHIFT 3
+#define PMIC_AUXADC_NAG_IRQ_EN_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_IRQ_EN_MASK 0x1
+#define PMIC_AUXADC_NAG_IRQ_EN_SHIFT 10
+#define PMIC_AUXADC_NAG_C_DLTV_IRQ_ADDR \
+ MT6389_AUXADC_NAG_0
+#define PMIC_AUXADC_NAG_C_DLTV_IRQ_MASK 0x1
+#define PMIC_AUXADC_NAG_C_DLTV_IRQ_SHIFT 15
+#define PMIC_AUXADC_NAG_ZCV_ADDR \
+ MT6389_AUXADC_NAG_1
+#define PMIC_AUXADC_NAG_ZCV_MASK 0x7FFF
+#define PMIC_AUXADC_NAG_ZCV_SHIFT 0
+#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_ADDR \
+ MT6389_AUXADC_NAG_2
+#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_MASK 0xFFFF
+#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_SHIFT 0
+#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_ADDR \
+ MT6389_AUXADC_NAG_3
+#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_MASK 0x7FF
+#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_SHIFT 0
+#define PMIC_AUXADC_NAG_CNT_15_0_ADDR \
+ MT6389_AUXADC_NAG_4
+#define PMIC_AUXADC_NAG_CNT_15_0_MASK 0xFFFF
+#define PMIC_AUXADC_NAG_CNT_15_0_SHIFT 0
+#define PMIC_AUXADC_NAG_CNT_25_16_ADDR \
+ MT6389_AUXADC_NAG_5
+#define PMIC_AUXADC_NAG_CNT_25_16_MASK 0x3FF
+#define PMIC_AUXADC_NAG_CNT_25_16_SHIFT 0
+#define PMIC_AUXADC_NAG_DLTV_ADDR \
+ MT6389_AUXADC_NAG_6
+#define PMIC_AUXADC_NAG_DLTV_MASK 0xFFFF
+#define PMIC_AUXADC_NAG_DLTV_SHIFT 0
+#define PMIC_AUXADC_NAG_C_DLTV_15_0_ADDR \
+ MT6389_AUXADC_NAG_7
+#define PMIC_AUXADC_NAG_C_DLTV_15_0_MASK 0xFFFF
+#define PMIC_AUXADC_NAG_C_DLTV_15_0_SHIFT 0
+#define PMIC_AUXADC_NAG_C_DLTV_26_16_ADDR \
+ MT6389_AUXADC_NAG_8
+#define PMIC_AUXADC_NAG_C_DLTV_26_16_MASK 0x7FF
+#define PMIC_AUXADC_NAG_C_DLTV_26_16_SHIFT 0
+#define PMIC_AUXADC_NAG_AUXADC_START_ADDR \
+ MT6389_AUXADC_NAG_9
+#define PMIC_AUXADC_NAG_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_NAG_AUXADC_START_SHIFT 0
+#define PMIC_AUXADC_NAG_STATE_ADDR \
+ MT6389_AUXADC_NAG_9
+#define PMIC_AUXADC_NAG_STATE_MASK 0x7
+#define PMIC_AUXADC_NAG_STATE_SHIFT 1
+#define PMIC_AUXADC_ADC_OUT_NAG_ADDR \
+ MT6389_AUXADC_NAG_10
+#define PMIC_AUXADC_ADC_OUT_NAG_MASK 0x7FFF
+#define PMIC_AUXADC_ADC_OUT_NAG_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_NAG_ADDR \
+ MT6389_AUXADC_NAG_10
+#define PMIC_AUXADC_ADC_RDY_NAG_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_NAG_SHIFT 15
+#define PMIC_AUXADC_NAG_CK_SW_EN_ADDR \
+ MT6389_AUXADC_NAG_11
+#define PMIC_AUXADC_NAG_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_NAG_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_NAG_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_NAG_11
+#define PMIC_AUXADC_NAG_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_NAG_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_NAG_ADDR \
+ MT6389_AUXADC_NAG_11
+#define PMIC_AUXADC_ADC_BUSY_IN_NAG_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_NAG_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_0
+#define PMIC_AUXADC_INTER1_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_1
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_1
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_1
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_2
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_2
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_2
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER1_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_2
+#define PMIC_AUXADC_INTER1_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_3
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER1_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_3
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_3
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER1_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_3
+#define PMIC_AUXADC_INTER1_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_4
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_5
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_6
+#define PMIC_AUXADC_INTER1_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER1_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_6
+#define PMIC_AUXADC_INTER1_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_8
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_8
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER1_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_0
+#define PMIC_AUXADC_INTER2_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_1
+#define PMIC_AUXADC_INTER2_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_1
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_1
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_2
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_2
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_2
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_2
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_3
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER2_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_3
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_3
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_3
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_4
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_5
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_6
+#define PMIC_AUXADC_INTER2_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER2_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_6
+#define PMIC_AUXADC_INTER2_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_8
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_8
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER2_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_0
+#define PMIC_AUXADC_INTER3_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_1
+#define PMIC_AUXADC_INTER3_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_1
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_1
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_2
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_2
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_2
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_2
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_3
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER3_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_3
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_3
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_3
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_4
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_5
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_6
+#define PMIC_AUXADC_INTER3_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER3_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_6
+#define PMIC_AUXADC_INTER3_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_8
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_8
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER3_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_0
+#define PMIC_AUXADC_INTER4_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_1
+#define PMIC_AUXADC_INTER4_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_1
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_1
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_2
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_2
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_2
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_2
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_3
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER4_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_3
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_3
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_3
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_4
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_5
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_6
+#define PMIC_AUXADC_INTER4_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER4_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_6
+#define PMIC_AUXADC_INTER4_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_8
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_8
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER4_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_0
+#define PMIC_AUXADC_INTER5_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_1
+#define PMIC_AUXADC_INTER5_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_1
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_1
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_2
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_2
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_2
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_2
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_3
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER5_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_3
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_3
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_3
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_4
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_5
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_6
+#define PMIC_AUXADC_INTER5_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER5_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_6
+#define PMIC_AUXADC_INTER5_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_8
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_8
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER5_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_DIG_7_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_ID
+#define PMIC_AUXADC_DIG_7_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_7_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_7_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_ID
+#define PMIC_AUXADC_DIG_7_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_7_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_7_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_REV0
+#define PMIC_AUXADC_DIG_7_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_7_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_7_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_REV0
+#define PMIC_AUXADC_DIG_7_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_7_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_7_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_REV0
+#define PMIC_AUXADC_DIG_7_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_7_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_7_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_REV0
+#define PMIC_AUXADC_DIG_7_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_7_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_7_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_DBI
+#define PMIC_AUXADC_DIG_7_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_7_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_7_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_DBI
+#define PMIC_AUXADC_DIG_7_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_7_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_7_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_DBI
+#define PMIC_AUXADC_DIG_7_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_7_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_7_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_7_DSN_DXI
+#define PMIC_AUXADC_DIG_7_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_7_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_0
+#define PMIC_AUXADC_INTER6_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_1
+#define PMIC_AUXADC_INTER6_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_1
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_1
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_2
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_2
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_2
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_2
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_3
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER6_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_3
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_3
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_3
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_4
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_5
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_6
+#define PMIC_AUXADC_INTER6_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER6_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_6
+#define PMIC_AUXADC_INTER6_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_8
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_8
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER6_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_0
+#define PMIC_AUXADC_INTER7_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_1
+#define PMIC_AUXADC_INTER7_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_1
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_1
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_2
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_2
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_2
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_2
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_3
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER7_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_3
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_3
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_3
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_4
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_5
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_6
+#define PMIC_AUXADC_INTER7_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER7_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_6
+#define PMIC_AUXADC_INTER7_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_8
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_8
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER7_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_0
+#define PMIC_AUXADC_INTER8_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_1
+#define PMIC_AUXADC_INTER8_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_1
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_1
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_2
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_2
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_2
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_2
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_3
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER8_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_3
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_3
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_3
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_4
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_5
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_6
+#define PMIC_AUXADC_INTER8_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER8_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_6
+#define PMIC_AUXADC_INTER8_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_8
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_8
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER8_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_0
+#define PMIC_AUXADC_INTER9_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_1
+#define PMIC_AUXADC_INTER9_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_1
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_1
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_2
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_2
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_2
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_2
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_3
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER9_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_3
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_3
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_3
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_4
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_5
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_6
+#define PMIC_AUXADC_INTER9_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER9_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_6
+#define PMIC_AUXADC_INTER9_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_8
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_8
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER9_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER10_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_0
+#define PMIC_AUXADC_INTER10_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_1
+#define PMIC_AUXADC_INTER10_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER10_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_1
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_1
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_2
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_2
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_2
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_2
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_3
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER10_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_3
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_3
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_3
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_4
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_5
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_6
+#define PMIC_AUXADC_INTER10_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER10_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER10_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_6
+#define PMIC_AUXADC_INTER10_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER10_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER10_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER10_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER10_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER10_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER10_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_8
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_8
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER10_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER10_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER10_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER11_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_0
+#define PMIC_AUXADC_INTER11_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_1
+#define PMIC_AUXADC_INTER11_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER11_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_1
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_1
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_2
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_2
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_2
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_2
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_3
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER11_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_3
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_3
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_3
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_4
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_5
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_6
+#define PMIC_AUXADC_INTER11_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER11_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER11_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_6
+#define PMIC_AUXADC_INTER11_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER11_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER11_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER11_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER11_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER11_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER11_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_8
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_8
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER11_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER11_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER11_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_DIG_8_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_ID
+#define PMIC_AUXADC_DIG_8_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_8_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_8_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_ID
+#define PMIC_AUXADC_DIG_8_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_8_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_8_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_REV0
+#define PMIC_AUXADC_DIG_8_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_8_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_8_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_REV0
+#define PMIC_AUXADC_DIG_8_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_8_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_8_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_REV0
+#define PMIC_AUXADC_DIG_8_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_8_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_8_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_REV0
+#define PMIC_AUXADC_DIG_8_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_8_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_8_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_DBI
+#define PMIC_AUXADC_DIG_8_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_8_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_8_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_DBI
+#define PMIC_AUXADC_DIG_8_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_8_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_8_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_DBI
+#define PMIC_AUXADC_DIG_8_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_8_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_8_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_8_DSN_DXI
+#define PMIC_AUXADC_DIG_8_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_8_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_0
+#define PMIC_AUXADC_INTER12_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_1
+#define PMIC_AUXADC_INTER12_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER12_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_1
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_1
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_2
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_2
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_2
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_2
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_3
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER12_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_3
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_3
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_3
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_4
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_5
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_6
+#define PMIC_AUXADC_INTER12_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER12_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER12_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_6
+#define PMIC_AUXADC_INTER12_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER12_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER12_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER12_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER12_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER12_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER12_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_8
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_8
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER12_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER12_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER12_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER13_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_0
+#define PMIC_AUXADC_INTER13_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_1
+#define PMIC_AUXADC_INTER13_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER13_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_1
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_1
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_2
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_2
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_2
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_2
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_3
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER13_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_3
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_3
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_3
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_4
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_5
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_6
+#define PMIC_AUXADC_INTER13_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER13_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER13_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_6
+#define PMIC_AUXADC_INTER13_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER13_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER13_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER13_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER13_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER13_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER13_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_8
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_8
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER13_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER13_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER13_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER14_DET_DIV_EN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_0
+#define PMIC_AUXADC_INTER14_DET_DIV_EN_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_EN_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_1
+#define PMIC_AUXADC_INTER14_DET_DIV_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER14_DET_DIV_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_1
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_1
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_2
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_2
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_2
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_2
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_3
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER14_DET_DIV_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_3
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_3
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_3
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_4
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_5
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_STATE_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_6
+#define PMIC_AUXADC_INTER14_DET_DIV_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER14_DET_DIV_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER14_DET_DIV_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_6
+#define PMIC_AUXADC_INTER14_DET_DIV_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER14_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_7
+#define PMIC_AUXADC_ADC_OUT_INTER14_DET_DIV_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER14_DET_DIV_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER14_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_7
+#define PMIC_AUXADC_ADC_RDY_INTER14_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER14_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_8
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_8
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER14_DET_DIV_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DET_DIV_ADDR \
+ MT6389_AUXADC_INTER14_DET_DIV_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DET_DIV_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER14_DET_DIV_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_EN_ADDR \
+ MT6389_AUXADC_INTER1_DET_0
+#define PMIC_AUXADC_INTER1_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_1
+#define PMIC_AUXADC_INTER1_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_1
+#define PMIC_AUXADC_INTER1_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER1_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER1_DET_1
+#define PMIC_AUXADC_INTER1_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER1_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER1_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_2
+#define PMIC_AUXADC_INTER1_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER1_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_2
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_2
+#define PMIC_AUXADC_INTER1_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER1_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER1_DET_2
+#define PMIC_AUXADC_INTER1_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_3
+#define PMIC_AUXADC_INTER1_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER1_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_3
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_3
+#define PMIC_AUXADC_INTER1_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER1_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER1_DET_3
+#define PMIC_AUXADC_INTER1_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER1_DET_4
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER1_DET_5
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER1_DET_6
+#define PMIC_AUXADC_INTER1_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER1_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER1_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER1_DET_6
+#define PMIC_AUXADC_INTER1_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_ADDR \
+ MT6389_AUXADC_INTER1_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER1_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_ADDR \
+ MT6389_AUXADC_INTER1_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER1_DET_SHIFT 15
+#define PMIC_AUXADC_INTER1_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER1_DET_8
+#define PMIC_AUXADC_INTER1_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER1_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER1_DET_8
+#define PMIC_AUXADC_INTER1_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER1_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_ADDR \
+ MT6389_AUXADC_INTER1_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_EN_ADDR \
+ MT6389_AUXADC_INTER2_DET_0
+#define PMIC_AUXADC_INTER2_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_1
+#define PMIC_AUXADC_INTER2_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_1
+#define PMIC_AUXADC_INTER2_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER2_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER2_DET_1
+#define PMIC_AUXADC_INTER2_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER2_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER2_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_2
+#define PMIC_AUXADC_INTER2_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER2_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_2
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_2
+#define PMIC_AUXADC_INTER2_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER2_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER2_DET_2
+#define PMIC_AUXADC_INTER2_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_3
+#define PMIC_AUXADC_INTER2_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER2_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_3
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_3
+#define PMIC_AUXADC_INTER2_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER2_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER2_DET_3
+#define PMIC_AUXADC_INTER2_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER2_DET_4
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER2_DET_5
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER2_DET_6
+#define PMIC_AUXADC_INTER2_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER2_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER2_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER2_DET_6
+#define PMIC_AUXADC_INTER2_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_ADDR \
+ MT6389_AUXADC_INTER2_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER2_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_ADDR \
+ MT6389_AUXADC_INTER2_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER2_DET_SHIFT 15
+#define PMIC_AUXADC_INTER2_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER2_DET_8
+#define PMIC_AUXADC_INTER2_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER2_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER2_DET_8
+#define PMIC_AUXADC_INTER2_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER2_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_ADDR \
+ MT6389_AUXADC_INTER2_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_EN_ADDR \
+ MT6389_AUXADC_INTER3_DET_0
+#define PMIC_AUXADC_INTER3_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_1
+#define PMIC_AUXADC_INTER3_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_1
+#define PMIC_AUXADC_INTER3_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER3_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER3_DET_1
+#define PMIC_AUXADC_INTER3_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER3_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER3_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_2
+#define PMIC_AUXADC_INTER3_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER3_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_2
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_2
+#define PMIC_AUXADC_INTER3_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER3_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER3_DET_2
+#define PMIC_AUXADC_INTER3_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_3
+#define PMIC_AUXADC_INTER3_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER3_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_3
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_3
+#define PMIC_AUXADC_INTER3_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER3_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER3_DET_3
+#define PMIC_AUXADC_INTER3_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER3_DET_4
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER3_DET_5
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER3_DET_6
+#define PMIC_AUXADC_INTER3_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER3_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER3_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER3_DET_6
+#define PMIC_AUXADC_INTER3_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_ADDR \
+ MT6389_AUXADC_INTER3_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER3_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_ADDR \
+ MT6389_AUXADC_INTER3_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER3_DET_SHIFT 15
+#define PMIC_AUXADC_INTER3_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER3_DET_8
+#define PMIC_AUXADC_INTER3_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER3_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER3_DET_8
+#define PMIC_AUXADC_INTER3_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER3_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_ADDR \
+ MT6389_AUXADC_INTER3_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_SHIFT 15
+#define PMIC_AUXADC_DIG_9_ANA_ID_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_ID
+#define PMIC_AUXADC_DIG_9_ANA_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_9_ANA_ID_SHIFT 0
+#define PMIC_AUXADC_DIG_9_DIG_ID_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_ID
+#define PMIC_AUXADC_DIG_9_DIG_ID_MASK 0xFF
+#define PMIC_AUXADC_DIG_9_DIG_ID_SHIFT 8
+#define PMIC_AUXADC_DIG_9_ANA_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_REV0
+#define PMIC_AUXADC_DIG_9_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_9_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUXADC_DIG_9_ANA_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_REV0
+#define PMIC_AUXADC_DIG_9_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_9_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUXADC_DIG_9_DIG_MINOR_REV_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_REV0
+#define PMIC_AUXADC_DIG_9_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_9_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUXADC_DIG_9_DIG_MAJOR_REV_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_REV0
+#define PMIC_AUXADC_DIG_9_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUXADC_DIG_9_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUXADC_DIG_9_DSN_CBS_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_DBI
+#define PMIC_AUXADC_DIG_9_DSN_CBS_MASK 0x3
+#define PMIC_AUXADC_DIG_9_DSN_CBS_SHIFT 0
+#define PMIC_AUXADC_DIG_9_DSN_BIX_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_DBI
+#define PMIC_AUXADC_DIG_9_DSN_BIX_MASK 0x3
+#define PMIC_AUXADC_DIG_9_DSN_BIX_SHIFT 2
+#define PMIC_AUXADC_DIG_9_DSN_ESP_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_DBI
+#define PMIC_AUXADC_DIG_9_DSN_ESP_MASK 0xFF
+#define PMIC_AUXADC_DIG_9_DSN_ESP_SHIFT 8
+#define PMIC_AUXADC_DIG_9_DSN_FPI_ADDR \
+ MT6389_AUXADC_DIG_9_DSN_DXI
+#define PMIC_AUXADC_DIG_9_DSN_FPI_MASK 0xFF
+#define PMIC_AUXADC_DIG_9_DSN_FPI_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_EN_ADDR \
+ MT6389_AUXADC_INTER4_DET_0
+#define PMIC_AUXADC_INTER4_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_1
+#define PMIC_AUXADC_INTER4_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_1
+#define PMIC_AUXADC_INTER4_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER4_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER4_DET_1
+#define PMIC_AUXADC_INTER4_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER4_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER4_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_2
+#define PMIC_AUXADC_INTER4_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER4_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_2
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_2
+#define PMIC_AUXADC_INTER4_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER4_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER4_DET_2
+#define PMIC_AUXADC_INTER4_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_3
+#define PMIC_AUXADC_INTER4_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER4_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_3
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_3
+#define PMIC_AUXADC_INTER4_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER4_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER4_DET_3
+#define PMIC_AUXADC_INTER4_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER4_DET_4
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER4_DET_5
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER4_DET_6
+#define PMIC_AUXADC_INTER4_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER4_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER4_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER4_DET_6
+#define PMIC_AUXADC_INTER4_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_ADDR \
+ MT6389_AUXADC_INTER4_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER4_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_ADDR \
+ MT6389_AUXADC_INTER4_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER4_DET_SHIFT 15
+#define PMIC_AUXADC_INTER4_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER4_DET_8
+#define PMIC_AUXADC_INTER4_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER4_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER4_DET_8
+#define PMIC_AUXADC_INTER4_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER4_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_ADDR \
+ MT6389_AUXADC_INTER4_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_EN_ADDR \
+ MT6389_AUXADC_INTER5_DET_0
+#define PMIC_AUXADC_INTER5_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_1
+#define PMIC_AUXADC_INTER5_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_1
+#define PMIC_AUXADC_INTER5_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER5_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER5_DET_1
+#define PMIC_AUXADC_INTER5_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER5_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER5_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_2
+#define PMIC_AUXADC_INTER5_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER5_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_2
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_2
+#define PMIC_AUXADC_INTER5_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER5_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER5_DET_2
+#define PMIC_AUXADC_INTER5_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_3
+#define PMIC_AUXADC_INTER5_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER5_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_3
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_3
+#define PMIC_AUXADC_INTER5_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER5_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER5_DET_3
+#define PMIC_AUXADC_INTER5_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER5_DET_4
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER5_DET_5
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER5_DET_6
+#define PMIC_AUXADC_INTER5_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER5_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER5_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER5_DET_6
+#define PMIC_AUXADC_INTER5_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_ADDR \
+ MT6389_AUXADC_INTER5_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER5_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_ADDR \
+ MT6389_AUXADC_INTER5_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER5_DET_SHIFT 15
+#define PMIC_AUXADC_INTER5_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER5_DET_8
+#define PMIC_AUXADC_INTER5_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER5_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER5_DET_8
+#define PMIC_AUXADC_INTER5_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER5_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_ADDR \
+ MT6389_AUXADC_INTER5_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_EN_ADDR \
+ MT6389_AUXADC_INTER6_DET_0
+#define PMIC_AUXADC_INTER6_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_1
+#define PMIC_AUXADC_INTER6_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_1
+#define PMIC_AUXADC_INTER6_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER6_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER6_DET_1
+#define PMIC_AUXADC_INTER6_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER6_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER6_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_2
+#define PMIC_AUXADC_INTER6_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER6_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_2
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_2
+#define PMIC_AUXADC_INTER6_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER6_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER6_DET_2
+#define PMIC_AUXADC_INTER6_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_3
+#define PMIC_AUXADC_INTER6_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER6_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_3
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_3
+#define PMIC_AUXADC_INTER6_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER6_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER6_DET_3
+#define PMIC_AUXADC_INTER6_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER6_DET_4
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER6_DET_5
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER6_DET_6
+#define PMIC_AUXADC_INTER6_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER6_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER6_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER6_DET_6
+#define PMIC_AUXADC_INTER6_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_ADDR \
+ MT6389_AUXADC_INTER6_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER6_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_ADDR \
+ MT6389_AUXADC_INTER6_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER6_DET_SHIFT 15
+#define PMIC_AUXADC_INTER6_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER6_DET_8
+#define PMIC_AUXADC_INTER6_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER6_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER6_DET_8
+#define PMIC_AUXADC_INTER6_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER6_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_ADDR \
+ MT6389_AUXADC_INTER6_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_EN_ADDR \
+ MT6389_AUXADC_INTER7_DET_0
+#define PMIC_AUXADC_INTER7_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_1
+#define PMIC_AUXADC_INTER7_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_1
+#define PMIC_AUXADC_INTER7_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER7_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER7_DET_1
+#define PMIC_AUXADC_INTER7_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER7_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER7_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_2
+#define PMIC_AUXADC_INTER7_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER7_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_2
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_2
+#define PMIC_AUXADC_INTER7_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER7_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER7_DET_2
+#define PMIC_AUXADC_INTER7_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_3
+#define PMIC_AUXADC_INTER7_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER7_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_3
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_3
+#define PMIC_AUXADC_INTER7_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER7_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER7_DET_3
+#define PMIC_AUXADC_INTER7_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER7_DET_4
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER7_DET_5
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER7_DET_6
+#define PMIC_AUXADC_INTER7_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER7_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER7_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER7_DET_6
+#define PMIC_AUXADC_INTER7_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_ADDR \
+ MT6389_AUXADC_INTER7_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER7_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_ADDR \
+ MT6389_AUXADC_INTER7_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER7_DET_SHIFT 15
+#define PMIC_AUXADC_INTER7_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER7_DET_8
+#define PMIC_AUXADC_INTER7_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER7_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER7_DET_8
+#define PMIC_AUXADC_INTER7_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER7_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_ADDR \
+ MT6389_AUXADC_INTER7_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_EN_ADDR \
+ MT6389_AUXADC_INTER8_DET_0
+#define PMIC_AUXADC_INTER8_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_1
+#define PMIC_AUXADC_INTER8_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_1
+#define PMIC_AUXADC_INTER8_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER8_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER8_DET_1
+#define PMIC_AUXADC_INTER8_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER8_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER8_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_2
+#define PMIC_AUXADC_INTER8_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER8_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_2
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_2
+#define PMIC_AUXADC_INTER8_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER8_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER8_DET_2
+#define PMIC_AUXADC_INTER8_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_3
+#define PMIC_AUXADC_INTER8_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER8_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_3
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_3
+#define PMIC_AUXADC_INTER8_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER8_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER8_DET_3
+#define PMIC_AUXADC_INTER8_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER8_DET_4
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER8_DET_5
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER8_DET_6
+#define PMIC_AUXADC_INTER8_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER8_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER8_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER8_DET_6
+#define PMIC_AUXADC_INTER8_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_ADDR \
+ MT6389_AUXADC_INTER8_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER8_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_ADDR \
+ MT6389_AUXADC_INTER8_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER8_DET_SHIFT 15
+#define PMIC_AUXADC_INTER8_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER8_DET_8
+#define PMIC_AUXADC_INTER8_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER8_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER8_DET_8
+#define PMIC_AUXADC_INTER8_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER8_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_ADDR \
+ MT6389_AUXADC_INTER8_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_EN_ADDR \
+ MT6389_AUXADC_INTER9_DET_0
+#define PMIC_AUXADC_INTER9_DET_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_EN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_PRD_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_1
+#define PMIC_AUXADC_INTER9_DET_PRD_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_PRD_SEL_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DEBT_MAX_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_1
+#define PMIC_AUXADC_INTER9_DET_DEBT_MAX_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_DEBT_MAX_SEL_SHIFT 2
+#define PMIC_AUXADC_INTER9_DET_DEBT_MIN_SEL_ADDR \
+ MT6389_AUXADC_INTER9_DET_1
+#define PMIC_AUXADC_INTER9_DET_DEBT_MIN_SEL_MASK 0x3
+#define PMIC_AUXADC_INTER9_DET_DEBT_MIN_SEL_SHIFT 4
+#define PMIC_AUXADC_INTER9_DET_VOLT_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_2
+#define PMIC_AUXADC_INTER9_DET_VOLT_MAX_MASK 0xFFF
+#define PMIC_AUXADC_INTER9_DET_VOLT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_2
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MAX_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_2
+#define PMIC_AUXADC_INTER9_DET_MAX_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_MAX_SHIFT 13
+#define PMIC_AUXADC_INTER9_DET_MAX_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER9_DET_2
+#define PMIC_AUXADC_INTER9_DET_MAX_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_MAX_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_VOLT_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_3
+#define PMIC_AUXADC_INTER9_DET_VOLT_MIN_MASK 0xFFF
+#define PMIC_AUXADC_INTER9_DET_VOLT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_3
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_IRQ_EN_MIN_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_3
+#define PMIC_AUXADC_INTER9_DET_MIN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_MIN_SHIFT 13
+#define PMIC_AUXADC_INTER9_DET_MIN_IRQ_B_ADDR \
+ MT6389_AUXADC_INTER9_DET_3
+#define PMIC_AUXADC_INTER9_DET_MIN_IRQ_B_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_MIN_IRQ_B_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MAX_ADDR \
+ MT6389_AUXADC_INTER9_DET_4
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MAX_MASK 0xF
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MIN_ADDR \
+ MT6389_AUXADC_INTER9_DET_5
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MIN_MASK 0xF
+#define PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_STATE_ADDR \
+ MT6389_AUXADC_INTER9_DET_6
+#define PMIC_AUXADC_INTER9_DET_STATE_MASK 0x7
+#define PMIC_AUXADC_INTER9_DET_STATE_SHIFT 12
+#define PMIC_AUXADC_INTER9_DET_AUXADC_START_ADDR \
+ MT6389_AUXADC_INTER9_DET_6
+#define PMIC_AUXADC_INTER9_DET_AUXADC_START_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_AUXADC_START_SHIFT 15
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_ADDR \
+ MT6389_AUXADC_INTER9_DET_7
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_MASK 0xFFF
+#define PMIC_AUXADC_ADC_OUT_INTER9_DET_SHIFT 0
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_ADDR \
+ MT6389_AUXADC_INTER9_DET_7
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_RDY_INTER9_DET_SHIFT 15
+#define PMIC_AUXADC_INTER9_DET_CK_SW_EN_ADDR \
+ MT6389_AUXADC_INTER9_DET_8
+#define PMIC_AUXADC_INTER9_DET_CK_SW_EN_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_CK_SW_EN_SHIFT 0
+#define PMIC_AUXADC_INTER9_DET_CK_SW_MODE_ADDR \
+ MT6389_AUXADC_INTER9_DET_8
+#define PMIC_AUXADC_INTER9_DET_CK_SW_MODE_MASK 0x1
+#define PMIC_AUXADC_INTER9_DET_CK_SW_MODE_SHIFT 1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_ADDR \
+ MT6389_AUXADC_INTER9_DET_8
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_MASK 0x1
+#define PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_SHIFT 15
+#define PMIC_BUCK_TOP_ANA_ID_ADDR \
+ MT6389_BUCK_TOP_DSN_ID
+#define PMIC_BUCK_TOP_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_TOP_ANA_ID_SHIFT 0
+#define PMIC_BUCK_TOP_DIG_ID_ADDR \
+ MT6389_BUCK_TOP_DSN_ID
+#define PMIC_BUCK_TOP_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_TOP_DIG_ID_SHIFT 8
+#define PMIC_BUCK_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_TOP_DSN_REV0
+#define PMIC_BUCK_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_TOP_DSN_REV0
+#define PMIC_BUCK_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_TOP_DSN_REV0
+#define PMIC_BUCK_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_TOP_DSN_REV0
+#define PMIC_BUCK_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_TOP_CBS_ADDR \
+ MT6389_BUCK_TOP_DBI
+#define PMIC_BUCK_TOP_CBS_MASK 0x3
+#define PMIC_BUCK_TOP_CBS_SHIFT 0
+#define PMIC_BUCK_TOP_BIX_ADDR \
+ MT6389_BUCK_TOP_DBI
+#define PMIC_BUCK_TOP_BIX_MASK 0x3
+#define PMIC_BUCK_TOP_BIX_SHIFT 2
+#define PMIC_BUCK_TOP_ESP_ADDR \
+ MT6389_BUCK_TOP_DBI
+#define PMIC_BUCK_TOP_ESP_MASK 0xFF
+#define PMIC_BUCK_TOP_ESP_SHIFT 8
+#define PMIC_BUCK_TOP_FPI_ADDR \
+ MT6389_BUCK_TOP_DXI
+#define PMIC_BUCK_TOP_FPI_MASK 0xFF
+#define PMIC_BUCK_TOP_FPI_SHIFT 0
+#define PMIC_BUCK_TOP_CLK_OFFSET_ADDR \
+ MT6389_BUCK_TOP_PAM0
+#define PMIC_BUCK_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_BUCK_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_BUCK_TOP_RST_OFFSET_ADDR \
+ MT6389_BUCK_TOP_PAM0
+#define PMIC_BUCK_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_BUCK_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_BUCK_TOP_INT_OFFSET_ADDR \
+ MT6389_BUCK_TOP_PAM1
+#define PMIC_BUCK_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_BUCK_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_BUCK_TOP_INT_LEN_ADDR \
+ MT6389_BUCK_TOP_PAM1
+#define PMIC_BUCK_TOP_INT_LEN_MASK 0xFF
+#define PMIC_BUCK_TOP_INT_LEN_SHIFT 8
+#define PMIC_RG_BUCK32K_CK_PDN_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_BUCK32K_CK_PDN_MASK 0x1
+#define PMIC_RG_BUCK32K_CK_PDN_SHIFT 0
+#define PMIC_RG_BUCK1M_CK_PDN_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_BUCK1M_CK_PDN_MASK 0x1
+#define PMIC_RG_BUCK1M_CK_PDN_SHIFT 1
+#define PMIC_RG_BUCK26M_CK_PDN_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_BUCK26M_CK_PDN_MASK 0x1
+#define PMIC_RG_BUCK26M_CK_PDN_SHIFT 2
+#define PMIC_RG_BUCK_ANA_CK_PDN_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_BUCK_ANA_CK_PDN_MASK 0x1
+#define PMIC_RG_BUCK_ANA_CK_PDN_SHIFT 3
+#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_MASK 0x1
+#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT 4
+#define PMIC_RG_SMPS_26M_CK_TST_DIS_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_SMPS_26M_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_SMPS_26M_CK_TST_DIS_SHIFT 5
+#define PMIC_RG_SMPS_26M_CK_TSTSEL_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0
+#define PMIC_RG_SMPS_26M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_SMPS_26M_CK_TSTSEL_SHIFT 6
+#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0_SET
+#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_ADDR \
+ MT6389_BUCK_TOP_CLK_CON0_CLR
+#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK32K_CK_PDN_HWEN_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK32K_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_BUCK32K_CK_PDN_HWEN_SHIFT 0
+#define PMIC_RG_BUCK1M_CK_PDN_HWEN_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK1M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_BUCK1M_CK_PDN_HWEN_SHIFT 1
+#define PMIC_RG_BUCK26M_CK_PDN_HWEN_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK26M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_BUCK26M_CK_PDN_HWEN_SHIFT 2
+#define PMIC_RG_BUCK_SLEEP_CTRL_MODE_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK_SLEEP_CTRL_MODE_MASK 0x1
+#define PMIC_RG_BUCK_SLEEP_CTRL_MODE_SHIFT 3
+#define PMIC_RG_BUCK_OSC_EN_MODE_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK_OSC_EN_MODE_MASK 0x1
+#define PMIC_RG_BUCK_OSC_EN_MODE_SHIFT 4
+#define PMIC_RG_BUCK_OSC_EN_SW_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0
+#define PMIC_RG_BUCK_OSC_EN_SW_MASK 0x1
+#define PMIC_RG_BUCK_OSC_EN_SW_SHIFT 5
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0_SET
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_ADDR \
+ MT6389_BUCK_TOP_CLK_HWEN_CON0_CLR
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_EN_VPROC_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VPROC_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VPROC_OC_SHIFT 0
+#define PMIC_RG_INT_EN_VCORE_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VCORE_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VCORE_OC_SHIFT 1
+#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_SHIFT 2
+#define PMIC_RG_INT_EN_VMODEM_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VMODEM_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VMODEM_OC_SHIFT 3
+#define PMIC_RG_INT_EN_VDRAM1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VDRAM1_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VDRAM1_OC_SHIFT 4
+#define PMIC_RG_INT_EN_VS1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VS1_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VS1_OC_SHIFT 5
+#define PMIC_RG_INT_EN_VS2_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VS2_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VS2_OC_SHIFT 6
+#define PMIC_RG_INT_EN_VPA_OC_ADDR \
+ MT6389_BUCK_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VPA_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VPA_OC_SHIFT 7
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_ADDR \
+ MT6389_BUCK_TOP_INT_CON0_SET
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_ADDR \
+ MT6389_BUCK_TOP_INT_CON0_CLR
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_VPROC_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VPROC_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VPROC_OC_SHIFT 0
+#define PMIC_RG_INT_MASK_VCORE_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VCORE_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VCORE_OC_SHIFT 1
+#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_SHIFT 2
+#define PMIC_RG_INT_MASK_VMODEM_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VMODEM_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VMODEM_OC_SHIFT 3
+#define PMIC_RG_INT_MASK_VDRAM1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VDRAM1_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VDRAM1_OC_SHIFT 4
+#define PMIC_RG_INT_MASK_VS1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VS1_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VS1_OC_SHIFT 5
+#define PMIC_RG_INT_MASK_VS2_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VS2_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VS2_OC_SHIFT 6
+#define PMIC_RG_INT_MASK_VPA_OC_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VPA_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VPA_OC_SHIFT 7
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0_SET
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_ADDR \
+ MT6389_BUCK_TOP_INT_MASK_CON0_CLR
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_VPROC_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VPROC_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VPROC_OC_SHIFT 0
+#define PMIC_RG_INT_STATUS_VCORE_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VCORE_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VCORE_OC_SHIFT 1
+#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_SHIFT 2
+#define PMIC_RG_INT_STATUS_VMODEM_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VMODEM_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VMODEM_OC_SHIFT 3
+#define PMIC_RG_INT_STATUS_VDRAM1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VDRAM1_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VDRAM1_OC_SHIFT 4
+#define PMIC_RG_INT_STATUS_VS1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VS1_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VS1_OC_SHIFT 5
+#define PMIC_RG_INT_STATUS_VS2_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VS2_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VS2_OC_SHIFT 6
+#define PMIC_RG_INT_STATUS_VPA_OC_ADDR \
+ MT6389_BUCK_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VPA_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VPA_OC_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_VPROC_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VPROC_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VPROC_OC_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_VS1_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VS1_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VS1_OC_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_VS2_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VS2_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VS2_OC_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_VPA_OC_ADDR \
+ MT6389_BUCK_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VPA_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VPA_OC_SHIFT 7
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_ADDR \
+ MT6389_BUCK_TOP_VOW_CON
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_MASK 0x1
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_SHIFT 0
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_ADDR \
+ MT6389_BUCK_TOP_VOW_CON
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_MASK 0x1
+#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_SHIFT 1
+#define PMIC_RG_BUCK_STB_MAX_ADDR \
+ MT6389_BUCK_TOP_STB_CON
+#define PMIC_RG_BUCK_STB_MAX_MASK 0x1FF
+#define PMIC_RG_BUCK_STB_MAX_SHIFT 0
+#define PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_ADDR \
+ MT6389_BUCK_TOP_VGP2_MINFREQ_CON
+#define PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_MASK 0xFF
+#define PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_SHIFT 0
+#define PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_ADDR \
+ MT6389_BUCK_TOP_VGP2_MINFREQ_CON
+#define PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_MASK 0x7
+#define PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MINFREQ_LATENCY_MAX_ADDR \
+ MT6389_BUCK_TOP_VPA_MINFREQ_CON
+#define PMIC_RG_BUCK_VPA_MINFREQ_LATENCY_MAX_MASK 0xFF
+#define PMIC_RG_BUCK_VPA_MINFREQ_LATENCY_MAX_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MINFREQ_DURATION_MAX_ADDR \
+ MT6389_BUCK_TOP_VPA_MINFREQ_CON
+#define PMIC_RG_BUCK_VPA_MINFREQ_DURATION_MAX_MASK 0xF
+#define PMIC_RG_BUCK_VPA_MINFREQ_DURATION_MAX_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VPROC_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_OC_SDN_STATUS_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_STATUS_SHIFT 2
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_SHIFT 3
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_SHIFT 4
+#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_SHIFT 5
+#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_SHIFT 6
+#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_ADDR \
+ MT6389_BUCK_TOP_OC_CON0
+#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK 0x1
+#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT 7
+#define PMIC_BUCK_TOP_WRITE_KEY_ADDR \
+ MT6389_BUCK_TOP_KEY_PROT
+#define PMIC_BUCK_TOP_WRITE_KEY_MASK 0xFFFF
+#define PMIC_BUCK_TOP_WRITE_KEY_SHIFT 0
+#define PMIC_DA_BUCK_SSC_FREQ_ADDR \
+ MT6389_BUCK_TOP_SSC_CON
+#define PMIC_DA_BUCK_SSC_FREQ_MASK 0x3
+#define PMIC_DA_BUCK_SSC_FREQ_SHIFT 0
+#define PMIC_RG_BUCK_K_RST_DONE_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_RST_DONE_MASK 0x1
+#define PMIC_RG_BUCK_K_RST_DONE_SHIFT 0
+#define PMIC_RG_BUCK_K_MAP_SEL_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_MAP_SEL_MASK 0x1
+#define PMIC_RG_BUCK_K_MAP_SEL_SHIFT 1
+#define PMIC_RG_BUCK_K_ONCE_EN_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_ONCE_EN_MASK 0x1
+#define PMIC_RG_BUCK_K_ONCE_EN_SHIFT 2
+#define PMIC_RG_BUCK_K_ONCE_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_ONCE_MASK 0x1
+#define PMIC_RG_BUCK_K_ONCE_SHIFT 3
+#define PMIC_RG_BUCK_K_START_MANUAL_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_START_MANUAL_MASK 0x1
+#define PMIC_RG_BUCK_K_START_MANUAL_SHIFT 4
+#define PMIC_RG_BUCK_K_SRC_SEL_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_SRC_SEL_MASK 0x1
+#define PMIC_RG_BUCK_K_SRC_SEL_SHIFT 5
+#define PMIC_RG_BUCK_K_AUTO_EN_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_AUTO_EN_MASK 0x1
+#define PMIC_RG_BUCK_K_AUTO_EN_SHIFT 6
+#define PMIC_RG_BUCK_K_INV_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_INV_MASK 0x1
+#define PMIC_RG_BUCK_K_INV_SHIFT 7
+#define PMIC_RG_BUCK_K_CK_EN_ADDR \
+ MT6389_BUCK_TOP_K_CON0
+#define PMIC_RG_BUCK_K_CK_EN_MASK 0x1
+#define PMIC_RG_BUCK_K_CK_EN_SHIFT 8
+#define PMIC_BUCK_K_RESULT_ADDR \
+ MT6389_BUCK_TOP_K_CON1
+#define PMIC_BUCK_K_RESULT_MASK 0x1
+#define PMIC_BUCK_K_RESULT_SHIFT 0
+#define PMIC_BUCK_K_DONE_ADDR \
+ MT6389_BUCK_TOP_K_CON1
+#define PMIC_BUCK_K_DONE_MASK 0x1
+#define PMIC_BUCK_K_DONE_SHIFT 1
+#define PMIC_BUCK_K_CONTROL_ADDR \
+ MT6389_BUCK_TOP_K_CON1
+#define PMIC_BUCK_K_CONTROL_MASK 0x3F
+#define PMIC_BUCK_K_CONTROL_SHIFT 2
+#define PMIC_DA_SMPS_OSC_CAL_ADDR \
+ MT6389_BUCK_TOP_K_CON1
+#define PMIC_DA_SMPS_OSC_CAL_MASK 0x3F
+#define PMIC_DA_SMPS_OSC_CAL_SHIFT 8
+#define PMIC_RG_BUCK_K_BUCK_CK_CNT_ADDR \
+ MT6389_BUCK_TOP_K_CON2
+#define PMIC_RG_BUCK_K_BUCK_CK_CNT_MASK 0x3FF
+#define PMIC_RG_BUCK_K_BUCK_CK_CNT_SHIFT 0
+#define PMIC_BUCK_VPROC_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG0
+#define PMIC_BUCK_VPROC_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VPROC_WDTDBG_VOSEL_SHIFT 0
+#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG0
+#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_SHIFT 8
+#define PMIC_BUCK_VSRAM_OTHERS_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG1
+#define PMIC_BUCK_VSRAM_OTHERS_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VSRAM_OTHERS_WDTDBG_VOSEL_SHIFT 0
+#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG1
+#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_SHIFT 8
+#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG2
+#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_SHIFT 0
+#define PMIC_BUCK_VS1_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG2
+#define PMIC_BUCK_VS1_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VS1_WDTDBG_VOSEL_SHIFT 8
+#define PMIC_BUCK_VS2_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG3
+#define PMIC_BUCK_VS2_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VS2_WDTDBG_VOSEL_SHIFT 0
+#define PMIC_BUCK_VPA_WDTDBG_VOSEL_ADDR \
+ MT6389_BUCK_TOP_WDTDBG3
+#define PMIC_BUCK_VPA_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_BUCK_VPA_WDTDBG_VOSEL_SHIFT 8
+#define PMIC_BUCK_TOP_ELR_LEN_ADDR \
+ MT6389_BUCK_TOP_ELR_NUM
+#define PMIC_BUCK_TOP_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_TOP_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VPROC_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_OC_SDN_EN_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_EN_SHIFT 2
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_SHIFT 3
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_SHIFT 4
+#define PMIC_RG_BUCK_VS1_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VS1_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_OC_SDN_EN_SHIFT 5
+#define PMIC_RG_BUCK_VS2_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VS2_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_OC_SDN_EN_SHIFT 6
+#define PMIC_RG_BUCK_VPA_OC_SDN_EN_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT 7
+#define PMIC_RG_BUCK_DCM_MODE_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_DCM_MODE_MASK 0x1
+#define PMIC_RG_BUCK_DCM_MODE_SHIFT 8
+#define PMIC_RG_BUCK_K_CONTROL_SMPS_ADDR \
+ MT6389_BUCK_TOP_ELR0
+#define PMIC_RG_BUCK_K_CONTROL_SMPS_MASK 0x3F
+#define PMIC_RG_BUCK_K_CONTROL_SMPS_SHIFT 10
+#define PMIC_RG_BUCK_VPROC_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VPROC_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VPROC_VOSEL_LIMIT_SEL_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_SHIFT 2
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_LIMIT_SEL_SHIFT 4
+#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT 6
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_SHIFT 8
+#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_SHIFT 10
+#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_SHIFT 12
+#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_BUCK_TOP_ELR1
+#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT 14
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP2_ADDR \
+ MT6389_BUCK_TOP_ELR2
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP2_MASK 0x7F
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP2_SHIFT 0
+#define PMIC_BUCK_VPROC_ANA_ID_ADDR \
+ MT6389_BUCK_VPROC_DSN_ID
+#define PMIC_BUCK_VPROC_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VPROC_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VPROC_DIG_ID_ADDR \
+ MT6389_BUCK_VPROC_DSN_ID
+#define PMIC_BUCK_VPROC_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VPROC_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VPROC_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VPROC_DSN_REV0
+#define PMIC_BUCK_VPROC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VPROC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VPROC_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VPROC_DSN_REV0
+#define PMIC_BUCK_VPROC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VPROC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VPROC_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VPROC_DSN_REV0
+#define PMIC_BUCK_VPROC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VPROC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VPROC_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VPROC_DSN_REV0
+#define PMIC_BUCK_VPROC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VPROC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VPROC_DSN_CBS_ADDR \
+ MT6389_BUCK_VPROC_DSN_DBI
+#define PMIC_BUCK_VPROC_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VPROC_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VPROC_DSN_BIX_ADDR \
+ MT6389_BUCK_VPROC_DSN_DBI
+#define PMIC_BUCK_VPROC_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VPROC_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VPROC_DSN_ESP_ADDR \
+ MT6389_BUCK_VPROC_DSN_DBI
+#define PMIC_BUCK_VPROC_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VPROC_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VPROC_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VPROC_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VPROC_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VPROC_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VPROC_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VPROC_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VPROC_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VPROC_DSN_DXI
+#define PMIC_BUCK_VPROC_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VPROC_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VPROC_EN_ADDR \
+ MT6389_BUCK_VPROC_CON0
+#define PMIC_RG_BUCK_VPROC_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_EN_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_LP_ADDR \
+ MT6389_BUCK_VPROC_CON0
+#define PMIC_RG_BUCK_VPROC_LP_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_LP_SHIFT 1
+#define PMIC_RG_BUCK_VPROC_CON0_SET_ADDR \
+ MT6389_BUCK_VPROC_CON0_SET
+#define PMIC_RG_BUCK_VPROC_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_CON0_CLR_ADDR \
+ MT6389_BUCK_VPROC_CON0_CLR
+#define PMIC_RG_BUCK_VPROC_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VPROC_CON1
+#define PMIC_RG_BUCK_VPROC_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VPROC_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VPROC_SLP_CON
+#define PMIC_RG_BUCK_VPROC_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VPROC_CFG0
+#define PMIC_RG_BUCK_VPROC_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VPROC_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VPROC_CFG0
+#define PMIC_RG_BUCK_VPROC_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VPROC_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VPROC_CFG0
+#define PMIC_RG_BUCK_VPROC_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VPROC_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_SFCHG_REN_ADDR \
+ MT6389_BUCK_VPROC_CFG0
+#define PMIC_RG_BUCK_VPROC_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VPROC_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VPROC_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VPROC_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VPROC_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VPROC_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VPROC_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VPROC_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VPROC_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VPROC_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VPROC_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VPROC_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VPROC_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VPROC_SW_OP_EN_ADDR \
+ MT6389_BUCK_VPROC_OP_EN
+#define PMIC_RG_BUCK_VPROC_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VPROC_OP_EN_SET_ADDR \
+ MT6389_BUCK_VPROC_OP_EN_SET
+#define PMIC_RG_BUCK_VPROC_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VPROC_OP_EN_CLR
+#define PMIC_RG_BUCK_VPROC_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VPROC_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VPROC_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VPROC_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VPROC_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VPROC_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VPROC_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VPROC_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VPROC_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VPROC_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VPROC_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VPROC_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG
+#define PMIC_RG_BUCK_VPROC_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VPROC_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG_SET
+#define PMIC_RG_BUCK_VPROC_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VPROC_OP_CFG_CLR
+#define PMIC_RG_BUCK_VPROC_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VPROC_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VPROC_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VPROC_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VPROC_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VPROC_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VPROC_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VPROC_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VPROC_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VPROC_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VPROC_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VPROC_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE
+#define PMIC_RG_BUCK_VPROC_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VPROC_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE_SET
+#define PMIC_RG_BUCK_VPROC_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VPROC_OP_MODE_CLR
+#define PMIC_RG_BUCK_VPROC_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPROC_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VPROC_VOSEL_ADDR \
+ MT6389_BUCK_VPROC_DBG0
+#define PMIC_DA_VPROC_VOSEL_MASK 0x7F
+#define PMIC_DA_VPROC_VOSEL_SHIFT 0
+#define PMIC_DA_VPROC_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VPROC_DBG0
+#define PMIC_DA_VPROC_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VPROC_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VPROC_EN_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_EN_MASK 0x1
+#define PMIC_DA_VPROC_EN_SHIFT 0
+#define PMIC_DA_VPROC_STB_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_STB_MASK 0x1
+#define PMIC_DA_VPROC_STB_SHIFT 1
+#define PMIC_DA_VPROC_LOOP_SEL_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VPROC_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VPROC_R2R_PDN_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_R2R_PDN_MASK 0x1
+#define PMIC_DA_VPROC_R2R_PDN_SHIFT 3
+#define PMIC_DA_VPROC_DVS_EN_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_DVS_EN_MASK 0x1
+#define PMIC_DA_VPROC_DVS_EN_SHIFT 4
+#define PMIC_DA_VPROC_DVS_DOWN_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VPROC_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VPROC_SSH_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_SSH_MASK 0x1
+#define PMIC_DA_VPROC_SSH_SHIFT 6
+#define PMIC_DA_VPROC_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_DA_VPROC_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VPROC_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VPROC_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_RG_BUCK_VPROC_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VPROC_CK_SW_EN_ADDR \
+ MT6389_BUCK_VPROC_DBG1
+#define PMIC_RG_BUCK_VPROC_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_CK_SW_EN_SHIFT 13
+#define PMIC_RG_BUCK_VPROC_TRACK_STALL_BYPASS_ADDR \
+ MT6389_BUCK_VPROC_STALL_TRACK0
+#define PMIC_RG_BUCK_VPROC_TRACK_STALL_BYPASS_MASK 0x1
+#define PMIC_RG_BUCK_VPROC_TRACK_STALL_BYPASS_SHIFT 0
+#define PMIC_BUCK_VPROC_ELR_LEN_ADDR \
+ MT6389_BUCK_VPROC_ELR_NUM
+#define PMIC_BUCK_VPROC_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VPROC_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VPROC_VOSEL_ADDR \
+ MT6389_BUCK_VPROC_ELR0
+#define PMIC_RG_BUCK_VPROC_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VPROC_VOSEL_SHIFT 0
+#define PMIC_BUCK_VCORE_ANA_ID_ADDR \
+ MT6389_BUCK_VCORE_DSN_ID
+#define PMIC_BUCK_VCORE_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VCORE_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VCORE_DIG_ID_ADDR \
+ MT6389_BUCK_VCORE_DSN_ID
+#define PMIC_BUCK_VCORE_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VCORE_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VCORE_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VCORE_DSN_REV0
+#define PMIC_BUCK_VCORE_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VCORE_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VCORE_DSN_REV0
+#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VCORE_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VCORE_DSN_REV0
+#define PMIC_BUCK_VCORE_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VCORE_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VCORE_DSN_REV0
+#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VCORE_DSN_CBS_ADDR \
+ MT6389_BUCK_VCORE_DSN_DBI
+#define PMIC_BUCK_VCORE_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VCORE_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VCORE_DSN_BIX_ADDR \
+ MT6389_BUCK_VCORE_DSN_DBI
+#define PMIC_BUCK_VCORE_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VCORE_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VCORE_DSN_ESP_ADDR \
+ MT6389_BUCK_VCORE_DSN_DBI
+#define PMIC_BUCK_VCORE_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VCORE_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VCORE_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VCORE_DSN_DXI
+#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VCORE_EN_ADDR \
+ MT6389_BUCK_VCORE_CON0
+#define PMIC_RG_BUCK_VCORE_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_EN_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_LP_ADDR \
+ MT6389_BUCK_VCORE_CON0
+#define PMIC_RG_BUCK_VCORE_LP_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_LP_SHIFT 1
+#define PMIC_RG_BUCK_VCORE_CON0_SET_ADDR \
+ MT6389_BUCK_VCORE_CON0_SET
+#define PMIC_RG_BUCK_VCORE_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_CON0_CLR_ADDR \
+ MT6389_BUCK_VCORE_CON0_CLR
+#define PMIC_RG_BUCK_VCORE_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VCORE_CON1
+#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VCORE_SLP_CON
+#define PMIC_RG_BUCK_VCORE_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VCORE_CFG0
+#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VCORE_CFG0
+#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VCORE_CFG0
+#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VCORE_SFCHG_REN_ADDR \
+ MT6389_BUCK_VCORE_CFG0
+#define PMIC_RG_BUCK_VCORE_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VCORE_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VCORE_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VCORE_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VCORE_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VCORE_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VCORE_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VCORE_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VCORE_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VCORE_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VCORE_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VCORE_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VCORE_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VCORE_SW_OP_EN_ADDR \
+ MT6389_BUCK_VCORE_OP_EN
+#define PMIC_RG_BUCK_VCORE_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VCORE_OP_EN_SET_ADDR \
+ MT6389_BUCK_VCORE_OP_EN_SET
+#define PMIC_RG_BUCK_VCORE_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VCORE_OP_EN_CLR
+#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VCORE_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VCORE_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VCORE_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VCORE_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VCORE_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VCORE_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VCORE_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VCORE_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VCORE_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VCORE_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VCORE_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VCORE_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG
+#define PMIC_RG_BUCK_VCORE_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG_SET
+#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VCORE_OP_CFG_CLR
+#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VCORE_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VCORE_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VCORE_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VCORE_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VCORE_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VCORE_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VCORE_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VCORE_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VCORE_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VCORE_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VCORE_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VCORE_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE
+#define PMIC_RG_BUCK_VCORE_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VCORE_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE_SET
+#define PMIC_RG_BUCK_VCORE_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VCORE_OP_MODE_CLR
+#define PMIC_RG_BUCK_VCORE_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VCORE_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VCORE_VOSEL_ADDR \
+ MT6389_BUCK_VCORE_DBG0
+#define PMIC_DA_VCORE_VOSEL_MASK 0x7F
+#define PMIC_DA_VCORE_VOSEL_SHIFT 0
+#define PMIC_DA_VCORE_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VCORE_DBG0
+#define PMIC_DA_VCORE_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VCORE_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VCORE_EN_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_EN_MASK 0x1
+#define PMIC_DA_VCORE_EN_SHIFT 0
+#define PMIC_DA_VCORE_STB_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_STB_MASK 0x1
+#define PMIC_DA_VCORE_STB_SHIFT 1
+#define PMIC_DA_VCORE_LOOP_SEL_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VCORE_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VCORE_R2R_PDN_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_R2R_PDN_MASK 0x1
+#define PMIC_DA_VCORE_R2R_PDN_SHIFT 3
+#define PMIC_DA_VCORE_DVS_EN_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_DVS_EN_MASK 0x1
+#define PMIC_DA_VCORE_DVS_EN_SHIFT 4
+#define PMIC_DA_VCORE_DVS_DOWN_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VCORE_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VCORE_SSH_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_SSH_MASK 0x1
+#define PMIC_DA_VCORE_SSH_SHIFT 6
+#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VCORE_CK_SW_EN_ADDR \
+ MT6389_BUCK_VCORE_DBG1
+#define PMIC_RG_BUCK_VCORE_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VCORE_CK_SW_EN_SHIFT 13
+#define PMIC_BUCK_VCORE_ELR_LEN_ADDR \
+ MT6389_BUCK_VCORE_ELR_NUM
+#define PMIC_BUCK_VCORE_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VCORE_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VCORE_VOSEL_ADDR \
+ MT6389_BUCK_VCORE_ELR0
+#define PMIC_RG_BUCK_VCORE_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VCORE_VOSEL_SHIFT 0
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_ID_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_ID
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_ID_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_ID
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_REV0
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_REV0
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VSRAM_OTHERS_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_REV0
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_REV0
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VSRAM_OTHERS_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_CBS_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DBI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_BIX_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DBI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_ESP_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DBI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DSN_DXI
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VSRAM_OTHERS_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CON0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_EN_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_LP_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CON0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_LP_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_LP_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_SET_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CON0_SET
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_CLR_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CON0_CLR
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CON1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_SLP_CON
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CFG0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CFG0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CFG0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_REN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_CFG0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SW_OP_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_SET_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN_SET
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_EN_CLR
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG_SET
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_CFG_CLR
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE_SET
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_OP_MODE_CLR
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG0
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT 0
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG0
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VSRAM_OTHERS_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_EN_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_EN_SHIFT 0
+#define PMIC_DA_VSRAM_OTHERS_STB_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_STB_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_STB_SHIFT 1
+#define PMIC_DA_VSRAM_OTHERS_LOOP_SEL_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_SHIFT 3
+#define PMIC_DA_VSRAM_OTHERS_DVS_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_DVS_EN_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_DVS_EN_SHIFT 4
+#define PMIC_DA_VSRAM_OTHERS_DVS_DOWN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VSRAM_OTHERS_SSH_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_SSH_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_SSH_SHIFT 6
+#define PMIC_DA_VSRAM_OTHERS_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_DA_VSRAM_OTHERS_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VSRAM_OTHERS_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_EN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_DBG1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_EN_SHIFT 13
+#define PMIC_BUCK_VSRAM_OTHERS_ELR_LEN_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_ELR_NUM
+#define PMIC_BUCK_VSRAM_OTHERS_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VSRAM_OTHERS_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_ADDR \
+ MT6389_BUCK_VSRAM_OTHERS_ELR0
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SHIFT 0
+#define PMIC_BUCK_VMODEM_ANA_ID_ADDR \
+ MT6389_BUCK_VMODEM_DSN_ID
+#define PMIC_BUCK_VMODEM_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VMODEM_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VMODEM_DIG_ID_ADDR \
+ MT6389_BUCK_VMODEM_DSN_ID
+#define PMIC_BUCK_VMODEM_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VMODEM_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VMODEM_DSN_REV0
+#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VMODEM_DSN_REV0
+#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VMODEM_DSN_REV0
+#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VMODEM_DSN_REV0
+#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VMODEM_DSN_CBS_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DBI
+#define PMIC_BUCK_VMODEM_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VMODEM_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VMODEM_DSN_BIX_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DBI
+#define PMIC_BUCK_VMODEM_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VMODEM_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VMODEM_DSN_ESP_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DBI
+#define PMIC_BUCK_VMODEM_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VMODEM_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VMODEM_DSN_DXI
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VMODEM_EN_ADDR \
+ MT6389_BUCK_VMODEM_CON0
+#define PMIC_RG_BUCK_VMODEM_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_EN_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_LP_ADDR \
+ MT6389_BUCK_VMODEM_CON0
+#define PMIC_RG_BUCK_VMODEM_LP_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_LP_SHIFT 1
+#define PMIC_RG_BUCK_VMODEM_CON0_SET_ADDR \
+ MT6389_BUCK_VMODEM_CON0_SET
+#define PMIC_RG_BUCK_VMODEM_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_CON0_CLR_ADDR \
+ MT6389_BUCK_VMODEM_CON0_CLR
+#define PMIC_RG_BUCK_VMODEM_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VMODEM_CON1
+#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VMODEM_SLP_CON
+#define PMIC_RG_BUCK_VMODEM_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VMODEM_CFG0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VMODEM_CFG0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VMODEM_CFG0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_ADDR \
+ MT6389_BUCK_VMODEM_CFG0
+#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN
+#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN_SET
+#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VMODEM_OP_EN_CLR
+#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG_SET
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VMODEM_OP_CFG_CLR
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE_SET
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VMODEM_OP_MODE_CLR
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VMODEM_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VMODEM_VOSEL_ADDR \
+ MT6389_BUCK_VMODEM_DBG0
+#define PMIC_DA_VMODEM_VOSEL_MASK 0x7F
+#define PMIC_DA_VMODEM_VOSEL_SHIFT 0
+#define PMIC_DA_VMODEM_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VMODEM_DBG0
+#define PMIC_DA_VMODEM_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VMODEM_EN_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_EN_MASK 0x1
+#define PMIC_DA_VMODEM_EN_SHIFT 0
+#define PMIC_DA_VMODEM_STB_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_STB_MASK 0x1
+#define PMIC_DA_VMODEM_STB_SHIFT 1
+#define PMIC_DA_VMODEM_LOOP_SEL_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VMODEM_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VMODEM_R2R_PDN_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_R2R_PDN_MASK 0x1
+#define PMIC_DA_VMODEM_R2R_PDN_SHIFT 3
+#define PMIC_DA_VMODEM_DVS_EN_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_DVS_EN_MASK 0x1
+#define PMIC_DA_VMODEM_DVS_EN_SHIFT 4
+#define PMIC_DA_VMODEM_DVS_DOWN_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VMODEM_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VMODEM_SSH_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_SSH_MASK 0x1
+#define PMIC_DA_VMODEM_SSH_SHIFT 6
+#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_ADDR \
+ MT6389_BUCK_VMODEM_DBG1
+#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_SHIFT 13
+#define PMIC_BUCK_VMODEM_ELR_LEN_ADDR \
+ MT6389_BUCK_VMODEM_ELR_NUM
+#define PMIC_BUCK_VMODEM_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VMODEM_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VMODEM_VOSEL_ADDR \
+ MT6389_BUCK_VMODEM_ELR0
+#define PMIC_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT 0
+#define PMIC_BUCK_VDRAM1_ANA_ID_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_ID
+#define PMIC_BUCK_VDRAM1_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VDRAM1_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VDRAM1_DIG_ID_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_ID
+#define PMIC_BUCK_VDRAM1_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VDRAM1_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_REV0
+#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_REV0
+#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_REV0
+#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_REV0
+#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VDRAM1_DSN_CBS_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DBI
+#define PMIC_BUCK_VDRAM1_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VDRAM1_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VDRAM1_DSN_BIX_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DBI
+#define PMIC_BUCK_VDRAM1_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VDRAM1_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VDRAM1_DSN_ESP_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DBI
+#define PMIC_BUCK_VDRAM1_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VDRAM1_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VDRAM1_DSN_DXI
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VDRAM1_EN_ADDR \
+ MT6389_BUCK_VDRAM1_CON0
+#define PMIC_RG_BUCK_VDRAM1_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_EN_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_LP_ADDR \
+ MT6389_BUCK_VDRAM1_CON0
+#define PMIC_RG_BUCK_VDRAM1_LP_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_LP_SHIFT 1
+#define PMIC_RG_BUCK_VDRAM1_CON0_SET_ADDR \
+ MT6389_BUCK_VDRAM1_CON0_SET
+#define PMIC_RG_BUCK_VDRAM1_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_CON0_CLR_ADDR \
+ MT6389_BUCK_VDRAM1_CON0_CLR
+#define PMIC_RG_BUCK_VDRAM1_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VDRAM1_CON1
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VDRAM1_SLP_CON
+#define PMIC_RG_BUCK_VDRAM1_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VDRAM1_CFG0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VDRAM1_CFG0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VDRAM1_CFG0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_ADDR \
+ MT6389_BUCK_VDRAM1_CFG0
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN
+#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN_SET
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VDRAM1_OP_EN_CLR
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG_SET
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VDRAM1_OP_CFG_CLR
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE_SET
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VDRAM1_OP_MODE_CLR
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VDRAM1_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VDRAM1_VOSEL_ADDR \
+ MT6389_BUCK_VDRAM1_DBG0
+#define PMIC_DA_VDRAM1_VOSEL_MASK 0x7F
+#define PMIC_DA_VDRAM1_VOSEL_SHIFT 0
+#define PMIC_DA_VDRAM1_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VDRAM1_DBG0
+#define PMIC_DA_VDRAM1_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VDRAM1_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VDRAM1_EN_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_EN_MASK 0x1
+#define PMIC_DA_VDRAM1_EN_SHIFT 0
+#define PMIC_DA_VDRAM1_STB_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_STB_MASK 0x1
+#define PMIC_DA_VDRAM1_STB_SHIFT 1
+#define PMIC_DA_VDRAM1_LOOP_SEL_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VDRAM1_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VDRAM1_R2R_PDN_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_R2R_PDN_MASK 0x1
+#define PMIC_DA_VDRAM1_R2R_PDN_SHIFT 3
+#define PMIC_DA_VDRAM1_DVS_EN_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_DVS_EN_MASK 0x1
+#define PMIC_DA_VDRAM1_DVS_EN_SHIFT 4
+#define PMIC_DA_VDRAM1_DVS_DOWN_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VDRAM1_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VDRAM1_SSH_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_SSH_MASK 0x1
+#define PMIC_DA_VDRAM1_SSH_SHIFT 6
+#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_ADDR \
+ MT6389_BUCK_VDRAM1_DBG1
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_SHIFT 13
+#define PMIC_BUCK_VDRAM1_ELR_LEN_ADDR \
+ MT6389_BUCK_VDRAM1_ELR_NUM
+#define PMIC_BUCK_VDRAM1_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VDRAM1_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_ADDR \
+ MT6389_BUCK_VDRAM1_ELR0
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VDRAM1_VOSEL_SHIFT 0
+#define PMIC_BUCK_VS1_ANA_ID_ADDR \
+ MT6389_BUCK_VS1_DSN_ID
+#define PMIC_BUCK_VS1_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VS1_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VS1_DIG_ID_ADDR \
+ MT6389_BUCK_VS1_DSN_ID
+#define PMIC_BUCK_VS1_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VS1_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VS1_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VS1_DSN_REV0
+#define PMIC_BUCK_VS1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VS1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VS1_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VS1_DSN_REV0
+#define PMIC_BUCK_VS1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VS1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VS1_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VS1_DSN_REV0
+#define PMIC_BUCK_VS1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VS1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VS1_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VS1_DSN_REV0
+#define PMIC_BUCK_VS1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VS1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VS1_DSN_CBS_ADDR \
+ MT6389_BUCK_VS1_DSN_DBI
+#define PMIC_BUCK_VS1_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VS1_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VS1_DSN_BIX_ADDR \
+ MT6389_BUCK_VS1_DSN_DBI
+#define PMIC_BUCK_VS1_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VS1_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VS1_DSN_ESP_ADDR \
+ MT6389_BUCK_VS1_DSN_DBI
+#define PMIC_BUCK_VS1_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VS1_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VS1_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VS1_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VS1_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VS1_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VS1_DSN_DXI
+#define PMIC_BUCK_VS1_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VS1_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VS1_EN_ADDR \
+ MT6389_BUCK_VS1_CON0
+#define PMIC_RG_BUCK_VS1_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS1_LP_ADDR \
+ MT6389_BUCK_VS1_CON0
+#define PMIC_RG_BUCK_VS1_LP_MASK 0x1
+#define PMIC_RG_BUCK_VS1_LP_SHIFT 1
+#define PMIC_RG_BUCK_VS1_CON0_SET_ADDR \
+ MT6389_BUCK_VS1_CON0_SET
+#define PMIC_RG_BUCK_VS1_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS1_CON0_CLR_ADDR \
+ MT6389_BUCK_VS1_CON0_CLR
+#define PMIC_RG_BUCK_VS1_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VS1_CON1
+#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VS1_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VS1_SLP_CON
+#define PMIC_RG_BUCK_VS1_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VS1_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VS1_CFG0
+#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VS1_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VS1_CFG0
+#define PMIC_RG_BUCK_VS1_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VS1_CFG0
+#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VS1_SFCHG_REN_ADDR \
+ MT6389_BUCK_VS1_CFG0
+#define PMIC_RG_BUCK_VS1_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VS1_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS1_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VS1_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VS1_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VS1_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VS1_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VS1_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VS1_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VS1_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VS1_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VS1_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VS1_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VS1_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VS1_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VS1_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VS1_SW_OP_EN_ADDR \
+ MT6389_BUCK_VS1_OP_EN
+#define PMIC_RG_BUCK_VS1_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VS1_OP_EN_SET_ADDR \
+ MT6389_BUCK_VS1_OP_EN_SET
+#define PMIC_RG_BUCK_VS1_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS1_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VS1_OP_EN_CLR
+#define PMIC_RG_BUCK_VS1_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VS1_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VS1_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VS1_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VS1_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VS1_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VS1_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VS1_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VS1_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VS1_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VS1_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VS1_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VS1_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VS1_OP_CFG
+#define PMIC_RG_BUCK_VS1_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VS1_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VS1_OP_CFG_SET
+#define PMIC_RG_BUCK_VS1_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VS1_OP_CFG_CLR
+#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS1_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VS1_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VS1_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VS1_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VS1_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VS1_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VS1_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VS1_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VS1_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VS1_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VS1_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VS1_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VS1_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VS1_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VS1_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VS1_OP_MODE
+#define PMIC_RG_BUCK_VS1_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VS1_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VS1_OP_MODE_SET
+#define PMIC_RG_BUCK_VS1_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS1_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VS1_OP_MODE_CLR
+#define PMIC_RG_BUCK_VS1_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS1_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VS1_VOSEL_ADDR \
+ MT6389_BUCK_VS1_DBG0
+#define PMIC_DA_VS1_VOSEL_MASK 0x7F
+#define PMIC_DA_VS1_VOSEL_SHIFT 0
+#define PMIC_DA_VS1_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VS1_DBG0
+#define PMIC_DA_VS1_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VS1_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VS1_EN_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_EN_MASK 0x1
+#define PMIC_DA_VS1_EN_SHIFT 0
+#define PMIC_DA_VS1_STB_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_STB_MASK 0x1
+#define PMIC_DA_VS1_STB_SHIFT 1
+#define PMIC_DA_VS1_LOOP_SEL_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VS1_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VS1_R2R_PDN_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_R2R_PDN_MASK 0x1
+#define PMIC_DA_VS1_R2R_PDN_SHIFT 3
+#define PMIC_DA_VS1_DVS_EN_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_DVS_EN_MASK 0x1
+#define PMIC_DA_VS1_DVS_EN_SHIFT 4
+#define PMIC_DA_VS1_DVS_DOWN_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VS1_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VS1_SSH_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_SSH_MASK 0x1
+#define PMIC_DA_VS1_SSH_SHIFT 6
+#define PMIC_DA_VS1_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_DA_VS1_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VS1_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VS1_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_RG_BUCK_VS1_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS1_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VS1_CK_SW_EN_ADDR \
+ MT6389_BUCK_VS1_DBG1
+#define PMIC_RG_BUCK_VS1_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS1_CK_SW_EN_SHIFT 13
+#define PMIC_RG_BUCK_VS1_VOTER_EN_ADDR \
+ MT6389_BUCK_VS1_VOTER
+#define PMIC_RG_BUCK_VS1_VOTER_EN_MASK 0xFFF
+#define PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_ADDR \
+ MT6389_BUCK_VS1_VOTER_SET
+#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK 0xFFF
+#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_ADDR \
+ MT6389_BUCK_VS1_VOTER_CLR
+#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK 0xFFF
+#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_ADDR \
+ MT6389_BUCK_VS1_VOTER_CFG
+#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT 0
+#define PMIC_BUCK_VS1_ELR_LEN_ADDR \
+ MT6389_BUCK_VS1_ELR_NUM
+#define PMIC_BUCK_VS1_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VS1_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VS1_VOSEL_ADDR \
+ MT6389_BUCK_VS1_ELR0
+#define PMIC_RG_BUCK_VS1_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VS1_VOSEL_SHIFT 0
+#define PMIC_BUCK_VS2_ANA_ID_ADDR \
+ MT6389_BUCK_VS2_DSN_ID
+#define PMIC_BUCK_VS2_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VS2_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VS2_DIG_ID_ADDR \
+ MT6389_BUCK_VS2_DSN_ID
+#define PMIC_BUCK_VS2_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VS2_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VS2_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VS2_DSN_REV0
+#define PMIC_BUCK_VS2_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VS2_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VS2_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VS2_DSN_REV0
+#define PMIC_BUCK_VS2_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VS2_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VS2_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VS2_DSN_REV0
+#define PMIC_BUCK_VS2_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VS2_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VS2_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VS2_DSN_REV0
+#define PMIC_BUCK_VS2_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VS2_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VS2_DSN_CBS_ADDR \
+ MT6389_BUCK_VS2_DSN_DBI
+#define PMIC_BUCK_VS2_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VS2_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VS2_DSN_BIX_ADDR \
+ MT6389_BUCK_VS2_DSN_DBI
+#define PMIC_BUCK_VS2_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VS2_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VS2_DSN_ESP_ADDR \
+ MT6389_BUCK_VS2_DSN_DBI
+#define PMIC_BUCK_VS2_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VS2_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VS2_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VS2_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VS2_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VS2_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VS2_DSN_DXI
+#define PMIC_BUCK_VS2_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VS2_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VS2_EN_ADDR \
+ MT6389_BUCK_VS2_CON0
+#define PMIC_RG_BUCK_VS2_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS2_LP_ADDR \
+ MT6389_BUCK_VS2_CON0
+#define PMIC_RG_BUCK_VS2_LP_MASK 0x1
+#define PMIC_RG_BUCK_VS2_LP_SHIFT 1
+#define PMIC_RG_BUCK_VS2_CON0_SET_ADDR \
+ MT6389_BUCK_VS2_CON0_SET
+#define PMIC_RG_BUCK_VS2_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS2_CON0_CLR_ADDR \
+ MT6389_BUCK_VS2_CON0_CLR
+#define PMIC_RG_BUCK_VS2_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_ADDR \
+ MT6389_BUCK_VS2_CON1
+#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT 0
+#define PMIC_RG_BUCK_VS2_SELR2R_CTRL_ADDR \
+ MT6389_BUCK_VS2_SLP_CON
+#define PMIC_RG_BUCK_VS2_SELR2R_CTRL_MASK 0x1
+#define PMIC_RG_BUCK_VS2_SELR2R_CTRL_SHIFT 0
+#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VS2_CFG0
+#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VS2_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VS2_CFG0
+#define PMIC_RG_BUCK_VS2_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VS2_CFG0
+#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VS2_SFCHG_REN_ADDR \
+ MT6389_BUCK_VS2_CFG0
+#define PMIC_RG_BUCK_VS2_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_SFCHG_REN_SHIFT 15
+#define PMIC_RG_BUCK_VS2_HW0_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS2_HW1_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_BUCK_VS2_HW2_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_BUCK_VS2_HW3_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_BUCK_VS2_HW4_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW4_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW4_OP_EN_SHIFT 4
+#define PMIC_RG_BUCK_VS2_HW5_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW5_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW5_OP_EN_SHIFT 5
+#define PMIC_RG_BUCK_VS2_HW6_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW6_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW6_OP_EN_SHIFT 6
+#define PMIC_RG_BUCK_VS2_HW7_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW7_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW7_OP_EN_SHIFT 7
+#define PMIC_RG_BUCK_VS2_HW8_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW8_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW8_OP_EN_SHIFT 8
+#define PMIC_RG_BUCK_VS2_HW9_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW9_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW9_OP_EN_SHIFT 9
+#define PMIC_RG_BUCK_VS2_HW10_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW10_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW10_OP_EN_SHIFT 10
+#define PMIC_RG_BUCK_VS2_HW11_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW11_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW11_OP_EN_SHIFT 11
+#define PMIC_RG_BUCK_VS2_HW12_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW12_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW12_OP_EN_SHIFT 12
+#define PMIC_RG_BUCK_VS2_HW13_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW13_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW13_OP_EN_SHIFT 13
+#define PMIC_RG_BUCK_VS2_HW14_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_HW14_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW14_OP_EN_SHIFT 14
+#define PMIC_RG_BUCK_VS2_SW_OP_EN_ADDR \
+ MT6389_BUCK_VS2_OP_EN
+#define PMIC_RG_BUCK_VS2_SW_OP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_SW_OP_EN_SHIFT 15
+#define PMIC_RG_BUCK_VS2_OP_EN_SET_ADDR \
+ MT6389_BUCK_VS2_OP_EN_SET
+#define PMIC_RG_BUCK_VS2_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS2_OP_EN_CLR_ADDR \
+ MT6389_BUCK_VS2_OP_EN_CLR
+#define PMIC_RG_BUCK_VS2_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_BUCK_VS2_HW3_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_BUCK_VS2_HW4_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW4_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW4_OP_CFG_SHIFT 4
+#define PMIC_RG_BUCK_VS2_HW5_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW5_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW5_OP_CFG_SHIFT 5
+#define PMIC_RG_BUCK_VS2_HW6_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW6_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW6_OP_CFG_SHIFT 6
+#define PMIC_RG_BUCK_VS2_HW7_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW7_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW7_OP_CFG_SHIFT 7
+#define PMIC_RG_BUCK_VS2_HW8_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW8_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW8_OP_CFG_SHIFT 8
+#define PMIC_RG_BUCK_VS2_HW9_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW9_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW9_OP_CFG_SHIFT 9
+#define PMIC_RG_BUCK_VS2_HW10_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW10_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW10_OP_CFG_SHIFT 10
+#define PMIC_RG_BUCK_VS2_HW11_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW11_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW11_OP_CFG_SHIFT 11
+#define PMIC_RG_BUCK_VS2_HW12_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW12_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW12_OP_CFG_SHIFT 12
+#define PMIC_RG_BUCK_VS2_HW13_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW13_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW13_OP_CFG_SHIFT 13
+#define PMIC_RG_BUCK_VS2_HW14_OP_CFG_ADDR \
+ MT6389_BUCK_VS2_OP_CFG
+#define PMIC_RG_BUCK_VS2_HW14_OP_CFG_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW14_OP_CFG_SHIFT 14
+#define PMIC_RG_BUCK_VS2_OP_CFG_SET_ADDR \
+ MT6389_BUCK_VS2_OP_CFG_SET
+#define PMIC_RG_BUCK_VS2_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_ADDR \
+ MT6389_BUCK_VS2_OP_CFG_CLR
+#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS2_HW0_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW0_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW0_OP_MODE_SHIFT 0
+#define PMIC_RG_BUCK_VS2_HW1_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW1_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW1_OP_MODE_SHIFT 1
+#define PMIC_RG_BUCK_VS2_HW2_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW2_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW2_OP_MODE_SHIFT 2
+#define PMIC_RG_BUCK_VS2_HW3_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW3_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW3_OP_MODE_SHIFT 3
+#define PMIC_RG_BUCK_VS2_HW4_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW4_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW4_OP_MODE_SHIFT 4
+#define PMIC_RG_BUCK_VS2_HW5_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW5_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW5_OP_MODE_SHIFT 5
+#define PMIC_RG_BUCK_VS2_HW6_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW6_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW6_OP_MODE_SHIFT 6
+#define PMIC_RG_BUCK_VS2_HW7_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW7_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW7_OP_MODE_SHIFT 7
+#define PMIC_RG_BUCK_VS2_HW8_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW8_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW8_OP_MODE_SHIFT 8
+#define PMIC_RG_BUCK_VS2_HW9_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW9_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW9_OP_MODE_SHIFT 9
+#define PMIC_RG_BUCK_VS2_HW10_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW10_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW10_OP_MODE_SHIFT 10
+#define PMIC_RG_BUCK_VS2_HW11_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW11_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW11_OP_MODE_SHIFT 11
+#define PMIC_RG_BUCK_VS2_HW12_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW12_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW12_OP_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VS2_HW13_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW13_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW13_OP_MODE_SHIFT 13
+#define PMIC_RG_BUCK_VS2_HW14_OP_MODE_ADDR \
+ MT6389_BUCK_VS2_OP_MODE
+#define PMIC_RG_BUCK_VS2_HW14_OP_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_HW14_OP_MODE_SHIFT 14
+#define PMIC_RG_BUCK_VS2_OP_MODE_SET_ADDR \
+ MT6389_BUCK_VS2_OP_MODE_SET
+#define PMIC_RG_BUCK_VS2_OP_MODE_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_MODE_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS2_OP_MODE_CLR_ADDR \
+ MT6389_BUCK_VS2_OP_MODE_CLR
+#define PMIC_RG_BUCK_VS2_OP_MODE_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VS2_OP_MODE_CLR_SHIFT 0
+#define PMIC_DA_VS2_VOSEL_ADDR \
+ MT6389_BUCK_VS2_DBG0
+#define PMIC_DA_VS2_VOSEL_MASK 0x7F
+#define PMIC_DA_VS2_VOSEL_SHIFT 0
+#define PMIC_DA_VS2_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VS2_DBG0
+#define PMIC_DA_VS2_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VS2_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VS2_EN_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_EN_MASK 0x1
+#define PMIC_DA_VS2_EN_SHIFT 0
+#define PMIC_DA_VS2_STB_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_STB_MASK 0x1
+#define PMIC_DA_VS2_STB_SHIFT 1
+#define PMIC_DA_VS2_LOOP_SEL_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_LOOP_SEL_MASK 0x1
+#define PMIC_DA_VS2_LOOP_SEL_SHIFT 2
+#define PMIC_DA_VS2_R2R_PDN_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_R2R_PDN_MASK 0x1
+#define PMIC_DA_VS2_R2R_PDN_SHIFT 3
+#define PMIC_DA_VS2_DVS_EN_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_DVS_EN_MASK 0x1
+#define PMIC_DA_VS2_DVS_EN_SHIFT 4
+#define PMIC_DA_VS2_DVS_DOWN_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VS2_DVS_DOWN_SHIFT 5
+#define PMIC_DA_VS2_SSH_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_SSH_MASK 0x1
+#define PMIC_DA_VS2_SSH_SHIFT 6
+#define PMIC_DA_VS2_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_DA_VS2_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VS2_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_RG_BUCK_VS2_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_RG_BUCK_VS2_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VS2_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VS2_CK_SW_EN_ADDR \
+ MT6389_BUCK_VS2_DBG1
+#define PMIC_RG_BUCK_VS2_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VS2_CK_SW_EN_SHIFT 13
+#define PMIC_RG_BUCK_VS2_VOTER_EN_ADDR \
+ MT6389_BUCK_VS2_VOTER
+#define PMIC_RG_BUCK_VS2_VOTER_EN_MASK 0xFFF
+#define PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT 0
+#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_ADDR \
+ MT6389_BUCK_VS2_VOTER_SET
+#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK 0xFFF
+#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT 0
+#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_ADDR \
+ MT6389_BUCK_VS2_VOTER_CLR
+#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK 0xFFF
+#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_ADDR \
+ MT6389_BUCK_VS2_VOTER_CFG
+#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT 0
+#define PMIC_BUCK_VS2_ELR_LEN_ADDR \
+ MT6389_BUCK_VS2_ELR_NUM
+#define PMIC_BUCK_VS2_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_VS2_ELR_LEN_SHIFT 0
+#define PMIC_RG_BUCK_VS2_VOSEL_ADDR \
+ MT6389_BUCK_VS2_ELR0
+#define PMIC_RG_BUCK_VS2_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VS2_VOSEL_SHIFT 0
+#define PMIC_BUCK_VPA_ANA_ID_ADDR \
+ MT6389_BUCK_VPA_DSN_ID
+#define PMIC_BUCK_VPA_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_VPA_ANA_ID_SHIFT 0
+#define PMIC_BUCK_VPA_DIG_ID_ADDR \
+ MT6389_BUCK_VPA_DSN_ID
+#define PMIC_BUCK_VPA_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_VPA_DIG_ID_SHIFT 8
+#define PMIC_BUCK_VPA_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_VPA_DSN_REV0
+#define PMIC_BUCK_VPA_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VPA_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_VPA_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_VPA_DSN_REV0
+#define PMIC_BUCK_VPA_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VPA_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_VPA_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_VPA_DSN_REV0
+#define PMIC_BUCK_VPA_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_VPA_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_VPA_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_VPA_DSN_REV0
+#define PMIC_BUCK_VPA_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_VPA_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_VPA_DSN_CBS_ADDR \
+ MT6389_BUCK_VPA_DSN_DBI
+#define PMIC_BUCK_VPA_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_VPA_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_VPA_DSN_BIX_ADDR \
+ MT6389_BUCK_VPA_DSN_DBI
+#define PMIC_BUCK_VPA_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_VPA_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_VPA_DSN_ESP_ADDR \
+ MT6389_BUCK_VPA_DSN_DBI
+#define PMIC_BUCK_VPA_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_VPA_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_SHIFT 0
+#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_SHIFT 1
+#define PMIC_BUCK_VPA_DSN_FPI_PREOC_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_PREOC_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_PREOC_SHIFT 2
+#define PMIC_BUCK_VPA_DSN_FPI_VOTER_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_VOTER_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_VOTER_SHIFT 3
+#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_SHIFT 4
+#define PMIC_BUCK_VPA_DSN_FPI_DLC_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_DLC_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_DLC_SHIFT 5
+#define PMIC_BUCK_VPA_DSN_FPI_TRAP_ADDR \
+ MT6389_BUCK_VPA_DSN_DXI
+#define PMIC_BUCK_VPA_DSN_FPI_TRAP_MASK 0x1
+#define PMIC_BUCK_VPA_DSN_FPI_TRAP_SHIFT 6
+#define PMIC_RG_BUCK_VPA_EN_ADDR \
+ MT6389_BUCK_VPA_CON0
+#define PMIC_RG_BUCK_VPA_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_EN_SHIFT 0
+#define PMIC_RG_BUCK_VPA_LP_ADDR \
+ MT6389_BUCK_VPA_CON0
+#define PMIC_RG_BUCK_VPA_LP_MASK 0x1
+#define PMIC_RG_BUCK_VPA_LP_SHIFT 1
+#define PMIC_RG_BUCK_VPA_CON0_SET_ADDR \
+ MT6389_BUCK_VPA_CON0_SET
+#define PMIC_RG_BUCK_VPA_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPA_CON0_SET_SHIFT 0
+#define PMIC_RG_BUCK_VPA_CON0_CLR_ADDR \
+ MT6389_BUCK_VPA_CON0_CLR
+#define PMIC_RG_BUCK_VPA_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_BUCK_VPA_CON0_CLR_SHIFT 0
+#define PMIC_RG_BUCK_VPA_VOSEL_ADDR \
+ MT6389_BUCK_VPA_CON1
+#define PMIC_RG_BUCK_VPA_VOSEL_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_VOSEL_SHIFT 0
+#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_ADDR \
+ MT6389_BUCK_VPA_CFG0
+#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_BUCK_VPA_SFCHG_FEN_ADDR \
+ MT6389_BUCK_VPA_CFG0
+#define PMIC_RG_BUCK_VPA_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_ADDR \
+ MT6389_BUCK_VPA_CFG0
+#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_BUCK_VPA_SFCHG_REN_ADDR \
+ MT6389_BUCK_VPA_CFG0
+#define PMIC_RG_BUCK_VPA_SFCHG_REN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_SFCHG_REN_SHIFT 15
+#define PMIC_DA_VPA_VOSEL_ADDR \
+ MT6389_BUCK_VPA_DBG0
+#define PMIC_DA_VPA_VOSEL_MASK 0x7F
+#define PMIC_DA_VPA_VOSEL_SHIFT 0
+#define PMIC_DA_VPA_VOSEL_GRAY_ADDR \
+ MT6389_BUCK_VPA_DBG0
+#define PMIC_DA_VPA_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VPA_VOSEL_GRAY_SHIFT 8
+#define PMIC_DA_VPA_EN_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_EN_MASK 0x1
+#define PMIC_DA_VPA_EN_SHIFT 0
+#define PMIC_DA_VPA_STB_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_STB_MASK 0x1
+#define PMIC_DA_VPA_STB_SHIFT 1
+#define PMIC_DA_VPA_LP_TRANST_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_LP_TRANST_MASK 0x1
+#define PMIC_DA_VPA_LP_TRANST_SHIFT 5
+#define PMIC_DA_VPA_DVS_BW_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_DVS_BW_MASK 0x1
+#define PMIC_DA_VPA_DVS_BW_SHIFT 6
+#define PMIC_DA_VPA_DVS_DOWN_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_DVS_DOWN_MASK 0x1
+#define PMIC_DA_VPA_DVS_DOWN_SHIFT 7
+#define PMIC_DA_VPA_MINFREQ_DISCHARGE_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_MINFREQ_DISCHARGE_MASK 0x1
+#define PMIC_DA_VPA_MINFREQ_DISCHARGE_SHIFT 8
+#define PMIC_DA_VPA_DVS_UP_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_DVS_UP_MASK 0x1
+#define PMIC_DA_VPA_DVS_UP_SHIFT 9
+#define PMIC_DA_VPA_LOW_IQ_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_DA_VPA_LOW_IQ_MASK 0x1
+#define PMIC_DA_VPA_LOW_IQ_SHIFT 10
+#define PMIC_RG_BUCK_VPA_CK_SW_MODE_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_RG_BUCK_VPA_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_BUCK_VPA_CK_SW_MODE_SHIFT 12
+#define PMIC_RG_BUCK_VPA_CK_SW_EN_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_RG_BUCK_VPA_CK_SW_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_CK_SW_EN_SHIFT 13
+#define PMIC_RG_BUCK_VPA_OC_PROTECT_EN_ADDR \
+ MT6389_BUCK_VPA_DBG1
+#define PMIC_RG_BUCK_VPA_OC_PROTECT_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_OC_PROTECT_EN_SHIFT 14
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_ADDR \
+ MT6389_BUCK_VPA_DLC_CON0
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_SHIFT 0
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_ADDR \
+ MT6389_BUCK_VPA_DLC_CON0
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_SHIFT 8
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_ADDR \
+ MT6389_BUCK_VPA_DLC_CON1
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_SHIFT 8
+#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_ADDR \
+ MT6389_BUCK_VPA_DLC_CON2
+#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_SHIFT 0
+#define PMIC_RG_BUCK_VPA_DLC_ADDR \
+ MT6389_BUCK_VPA_DLC_CON2
+#define PMIC_RG_BUCK_VPA_DLC_MASK 0x7
+#define PMIC_RG_BUCK_VPA_DLC_SHIFT 8
+#define PMIC_DA_VPA_DLC_ADDR \
+ MT6389_BUCK_VPA_DLC_CON2
+#define PMIC_DA_VPA_DLC_MASK 0x7
+#define PMIC_DA_VPA_DLC_SHIFT 12
+#define PMIC_RG_BUCK_VPA_MSFG_EN_ADDR \
+ MT6389_BUCK_VPA_MSFG_CON0
+#define PMIC_RG_BUCK_VPA_MSFG_EN_MASK 0x1
+#define PMIC_RG_BUCK_VPA_MSFG_EN_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_ADDR \
+ MT6389_BUCK_VPA_MSFG_CON1
+#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_ADDR \
+ MT6389_BUCK_VPA_MSFG_CON1
+#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE0
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE0
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE1
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE1
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE2
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_ADDR \
+ MT6389_BUCK_VPA_MSFG_RRATE2
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_ADDR \
+ MT6389_BUCK_VPA_MSFG_RTHD0
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_ADDR \
+ MT6389_BUCK_VPA_MSFG_RTHD0
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_ADDR \
+ MT6389_BUCK_VPA_MSFG_RTHD1
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_ADDR \
+ MT6389_BUCK_VPA_MSFG_RTHD1
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_ADDR \
+ MT6389_BUCK_VPA_MSFG_RTHD2
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE1
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE1
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE2
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_ADDR \
+ MT6389_BUCK_VPA_MSFG_FRATE2
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_MASK 0x3F
+#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_ADDR \
+ MT6389_BUCK_VPA_MSFG_FTHD0
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_ADDR \
+ MT6389_BUCK_VPA_MSFG_FTHD0
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_ADDR \
+ MT6389_BUCK_VPA_MSFG_FTHD1
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_SHIFT 0
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_ADDR \
+ MT6389_BUCK_VPA_MSFG_FTHD1
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_SHIFT 8
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_ADDR \
+ MT6389_BUCK_VPA_MSFG_FTHD2
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_MASK 0x7F
+#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_SHIFT 0
+#define PMIC_BUCK_ANA0_ANA_ID_ADDR \
+ MT6389_BUCK_ANA0_DSN_ID
+#define PMIC_BUCK_ANA0_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_ANA0_ANA_ID_SHIFT 0
+#define PMIC_BUCK_ANA0_DIG_ID_ADDR \
+ MT6389_BUCK_ANA0_DSN_ID
+#define PMIC_BUCK_ANA0_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_ANA0_DIG_ID_SHIFT 8
+#define PMIC_BUCK_ANA0_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_ANA0_DSN_REV0
+#define PMIC_BUCK_ANA0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_ANA0_DSN_REV0
+#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_ANA0_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_ANA0_DSN_REV0
+#define PMIC_BUCK_ANA0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_ANA0_DSN_REV0
+#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_ANA0_DSN_CBS_ADDR \
+ MT6389_BUCK_ANA0_DSN_DBI
+#define PMIC_BUCK_ANA0_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_ANA0_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_ANA0_DSN_BIX_ADDR \
+ MT6389_BUCK_ANA0_DSN_DBI
+#define PMIC_BUCK_ANA0_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_ANA0_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_ANA0_DSN_ESP_ADDR \
+ MT6389_BUCK_ANA0_DSN_DBI
+#define PMIC_BUCK_ANA0_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_ANA0_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_ANA0_DSN_FPI_ADDR \
+ MT6389_BUCK_ANA0_DSN_FPI
+#define PMIC_BUCK_ANA0_DSN_FPI_MASK 0xFF
+#define PMIC_BUCK_ANA0_DSN_FPI_SHIFT 0
+#define PMIC_RG_SMPS_TESTMODE_B_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_TESTMODE_B_MASK 0x3F
+#define PMIC_RG_SMPS_TESTMODE_B_SHIFT 0
+#define PMIC_RG_AUTOK_RST_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_AUTOK_RST_MASK 0x1
+#define PMIC_RG_AUTOK_RST_SHIFT 6
+#define PMIC_RG_SMPS_DISAUTOK_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_DISAUTOK_MASK 0x1
+#define PMIC_RG_SMPS_DISAUTOK_SHIFT 7
+#define PMIC_RG_SMPS_VSNS_SEL_EN_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_VSNS_SEL_EN_MASK 0x1
+#define PMIC_RG_SMPS_VSNS_SEL_EN_SHIFT 8
+#define PMIC_RG_SMPS_VSNS_SEL_HSIDE_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_VSNS_SEL_HSIDE_MASK 0x1
+#define PMIC_RG_SMPS_VSNS_SEL_HSIDE_SHIFT 9
+#define PMIC_RG_SMPS_VSNS_SEL_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_VSNS_SEL_MASK 0x7
+#define PMIC_RG_SMPS_VSNS_SEL_SHIFT 10
+#define PMIC_RG_SMPS_SSC_EN_ADDR \
+ MT6389_SMPS_ANA_CON0
+#define PMIC_RG_SMPS_SSC_EN_MASK 0x1
+#define PMIC_RG_SMPS_SSC_EN_SHIFT 13
+#define PMIC_RG_VPROC_SR_VBAT_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_SR_VBAT_MASK 0x1
+#define PMIC_RG_VPROC_SR_VBAT_SHIFT 0
+#define PMIC_RG_VPROC_NDIS_EN_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_NDIS_EN_MASK 0x1
+#define PMIC_RG_VPROC_NDIS_EN_SHIFT 1
+#define PMIC_RG_VPROC_SR_EN_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_SR_EN_MASK 0x1
+#define PMIC_RG_VPROC_SR_EN_SHIFT 2
+#define PMIC_RG_VPROC_SLEEP_TIME_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VPROC_SLEEP_TIME_SHIFT 3
+#define PMIC_RG_VPROC_LOOPSEL_DIS_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_LOOPSEL_DIS_MASK 0x1
+#define PMIC_RG_VPROC_LOOPSEL_DIS_SHIFT 5
+#define PMIC_RG_VPROC_TB_DIS_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_TB_DIS_MASK 0x1
+#define PMIC_RG_VPROC_TB_DIS_SHIFT 6
+#define PMIC_RG_VPROC_TB_PFM_OFF_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_TB_PFM_OFF_MASK 0x1
+#define PMIC_RG_VPROC_TB_PFM_OFF_SHIFT 7
+#define PMIC_RG_VPROC_TB_VREFSEL_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_TB_VREFSEL_MASK 0x3
+#define PMIC_RG_VPROC_TB_VREFSEL_SHIFT 8
+#define PMIC_RG_VPROC_TB_WIDTH_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VPROC_TB_WIDTH_SHIFT 10
+#define PMIC_RG_VPROC_DUMMY_LOAD_EN_ADDR \
+ MT6389_VPROC_ANA_CON0
+#define PMIC_RG_VPROC_DUMMY_LOAD_EN_MASK 0x1
+#define PMIC_RG_VPROC_DUMMY_LOAD_EN_SHIFT 12
+#define PMIC_RGS_VPROC_DIG_MON_ADDR \
+ MT6389_VPROC_ANA_CON1
+#define PMIC_RGS_VPROC_DIG_MON_MASK 0x1
+#define PMIC_RGS_VPROC_DIG_MON_SHIFT 9
+#define PMIC_RG_VPROC_UG_SR_ADDR \
+ MT6389_VPROC_ANA_CON1
+#define PMIC_RG_VPROC_UG_SR_MASK 0x3
+#define PMIC_RG_VPROC_UG_SR_SHIFT 10
+#define PMIC_RG_VPROC_LG_SR_ADDR \
+ MT6389_VPROC_ANA_CON1
+#define PMIC_RG_VPROC_LG_SR_MASK 0x3
+#define PMIC_RG_VPROC_LG_SR_SHIFT 12
+#define PMIC_RG_VPROC_TMDL_ADDR \
+ MT6389_VPROC_ANA_CON1
+#define PMIC_RG_VPROC_TMDL_MASK 0x1
+#define PMIC_RG_VPROC_TMDL_SHIFT 14
+#define PMIC_RG_VPROC_FUGON_ADDR \
+ MT6389_VPROC_ANA_CON1
+#define PMIC_RG_VPROC_FUGON_MASK 0x1
+#define PMIC_RG_VPROC_FUGON_SHIFT 15
+#define PMIC_RG_VPROC_FLGON_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_FLGON_MASK 0x1
+#define PMIC_RG_VPROC_FLGON_SHIFT 0
+#define PMIC_RG_VPROC_FCCM_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_FCCM_MASK 0x1
+#define PMIC_RG_VPROC_FCCM_SHIFT 1
+#define PMIC_RG_VPROC_NONAUDIBLE_EN_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VPROC_NONAUDIBLE_EN_SHIFT 2
+#define PMIC_RG_VPROC_RETENTION_EN_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_RETENTION_EN_MASK 0x1
+#define PMIC_RG_VPROC_RETENTION_EN_SHIFT 3
+#define PMIC_RG_VPROC_VDIFFPFM_OFF_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VPROC_VDIFFPFM_OFF_SHIFT 4
+#define PMIC_RG_VPROC_DIGMON_SEL_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VPROC_DIGMON_SEL_SHIFT 5
+#define PMIC_RG_VPROC_OCN_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_OCN_MASK 0x7
+#define PMIC_RG_VPROC_OCN_SHIFT 8
+#define PMIC_RG_VPROC_OCP_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RG_VPROC_OCP_MASK 0x7
+#define PMIC_RG_VPROC_OCP_SHIFT 11
+#define PMIC_RGS_VPROC_OC_STATUS_ADDR \
+ MT6389_VPROC_ANA_CON2
+#define PMIC_RGS_VPROC_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VPROC_OC_STATUS_SHIFT 14
+#define PMIC_RG_VPROC_RSV1_ADDR \
+ MT6389_VPROC_ANA_CON3
+#define PMIC_RG_VPROC_RSV1_MASK 0xFF
+#define PMIC_RG_VPROC_RSV1_SHIFT 0
+#define PMIC_RG_VPROC_RSV2_ADDR \
+ MT6389_VPROC_ANA_CON3
+#define PMIC_RG_VPROC_RSV2_MASK 0xFF
+#define PMIC_RG_VPROC_RSV2_SHIFT 8
+#define PMIC_RG_VPROC_UG_ON_SR_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VPROC_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VPROC_NLIM_GATING_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VPROC_NLIM_GATING_SHIFT 2
+#define PMIC_RG_VPROC_NLIM_SRF_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VPROC_NLIM_SRF_SHIFT 3
+#define PMIC_RG_VPROC_POTECT_KEY_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VPROC_POTECT_KEY_SHIFT 4
+#define PMIC_RG_VPROC_LXR_EN_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_LXR_EN_MASK 0x1
+#define PMIC_RG_VPROC_LXR_EN_SHIFT 6
+#define PMIC_RG_VPROC_GPIO_OUTPUT_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VPROC_GPIO_OUTPUT_SHIFT 7
+#define PMIC_RG_VPROC_PARKB_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_PARKB_MASK 0x7
+#define PMIC_RG_VPROC_PARKB_SHIFT 8
+#define PMIC_RG_VPROC_MOS_TMODE_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VPROC_MOS_TMODE_SHIFT 11
+#define PMIC_RG_VPROC_DRV_FORCEFAST_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_DRV_FORCEFAST_MASK 0x1
+#define PMIC_RG_VPROC_DRV_FORCEFAST_SHIFT 12
+#define PMIC_RG_VPROC_PFM_FP_CUTB_ADDR \
+ MT6389_VPROC_ANA_CON4
+#define PMIC_RG_VPROC_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VPROC_PFM_FP_CUTB_SHIFT 13
+#define PMIC_RG_VPROC_VDIFFCAP_EN_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_VDIFFCAP_EN_MASK 0x1
+#define PMIC_RG_VPROC_VDIFFCAP_EN_SHIFT 0
+#define PMIC_RG_VPROC_VBAT_HI_DIS_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_VBAT_HI_DIS_MASK 0x1
+#define PMIC_RG_VPROC_VBAT_HI_DIS_SHIFT 1
+#define PMIC_RG_VPROC_VBAT_LOW_DIS_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_VBAT_LOW_DIS_MASK 0x1
+#define PMIC_RG_VPROC_VBAT_LOW_DIS_SHIFT 2
+#define PMIC_RG_VPROC_VOUT_HI_DIS_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_VOUT_HI_DIS_MASK 0x1
+#define PMIC_RG_VPROC_VOUT_HI_DIS_SHIFT 3
+#define PMIC_RG_VPROC_VDIFF_OFF_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VPROC_VDIFF_OFF_SHIFT 4
+#define PMIC_RG_VPROC_SLP_RSV_ADDR \
+ MT6389_VPROC_ANA_CON5
+#define PMIC_RG_VPROC_SLP_RSV_MASK 0xFF
+#define PMIC_RG_VPROC_SLP_RSV_SHIFT 5
+#define PMIC_RG_VCORE_SR_VBAT_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_SR_VBAT_MASK 0x1
+#define PMIC_RG_VCORE_SR_VBAT_SHIFT 0
+#define PMIC_RG_VCORE_NDIS_EN_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_NDIS_EN_MASK 0x1
+#define PMIC_RG_VCORE_NDIS_EN_SHIFT 1
+#define PMIC_RG_VCORE_SR_EN_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_SR_EN_MASK 0x1
+#define PMIC_RG_VCORE_SR_EN_SHIFT 2
+#define PMIC_RG_VCORE_SLEEP_TIME_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VCORE_SLEEP_TIME_SHIFT 3
+#define PMIC_RG_VCORE_LOOPSEL_DIS_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_LOOPSEL_DIS_MASK 0x1
+#define PMIC_RG_VCORE_LOOPSEL_DIS_SHIFT 5
+#define PMIC_RG_VCORE_TB_DIS_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_TB_DIS_MASK 0x1
+#define PMIC_RG_VCORE_TB_DIS_SHIFT 6
+#define PMIC_RG_VCORE_TB_PFM_OFF_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_TB_PFM_OFF_MASK 0x1
+#define PMIC_RG_VCORE_TB_PFM_OFF_SHIFT 7
+#define PMIC_RG_VCORE_TB_VREFSEL_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_TB_VREFSEL_MASK 0x3
+#define PMIC_RG_VCORE_TB_VREFSEL_SHIFT 8
+#define PMIC_RG_VCORE_TB_WIDTH_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VCORE_TB_WIDTH_SHIFT 10
+#define PMIC_RG_VCORE_DUMMY_LOAD_EN_ADDR \
+ MT6389_VCORE_ANA_CON0
+#define PMIC_RG_VCORE_DUMMY_LOAD_EN_MASK 0x1
+#define PMIC_RG_VCORE_DUMMY_LOAD_EN_SHIFT 12
+#define PMIC_RGS_VCORE_DIG_MON_ADDR \
+ MT6389_VCORE_ANA_CON1
+#define PMIC_RGS_VCORE_DIG_MON_MASK 0x1
+#define PMIC_RGS_VCORE_DIG_MON_SHIFT 9
+#define PMIC_RG_VCORE_UG_SR_ADDR \
+ MT6389_VCORE_ANA_CON1
+#define PMIC_RG_VCORE_UG_SR_MASK 0x3
+#define PMIC_RG_VCORE_UG_SR_SHIFT 10
+#define PMIC_RG_VCORE_LG_SR_ADDR \
+ MT6389_VCORE_ANA_CON1
+#define PMIC_RG_VCORE_LG_SR_MASK 0x3
+#define PMIC_RG_VCORE_LG_SR_SHIFT 12
+#define PMIC_RG_VCORE_TMDL_ADDR \
+ MT6389_VCORE_ANA_CON1
+#define PMIC_RG_VCORE_TMDL_MASK 0x1
+#define PMIC_RG_VCORE_TMDL_SHIFT 14
+#define PMIC_RG_VCORE_FUGON_ADDR \
+ MT6389_VCORE_ANA_CON1
+#define PMIC_RG_VCORE_FUGON_MASK 0x1
+#define PMIC_RG_VCORE_FUGON_SHIFT 15
+#define PMIC_RG_VCORE_FLGON_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_FLGON_MASK 0x1
+#define PMIC_RG_VCORE_FLGON_SHIFT 0
+#define PMIC_RG_VCORE_FCCM_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_FCCM_MASK 0x1
+#define PMIC_RG_VCORE_FCCM_SHIFT 1
+#define PMIC_RG_VCORE_NONAUDIBLE_EN_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VCORE_NONAUDIBLE_EN_SHIFT 2
+#define PMIC_RG_VCORE_RETENTION_EN_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_RETENTION_EN_MASK 0x1
+#define PMIC_RG_VCORE_RETENTION_EN_SHIFT 3
+#define PMIC_RG_VCORE_VDIFFPFM_OFF_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VCORE_VDIFFPFM_OFF_SHIFT 4
+#define PMIC_RG_VCORE_DIGMON_SEL_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VCORE_DIGMON_SEL_SHIFT 5
+#define PMIC_RG_VCORE_OCN_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_OCN_MASK 0x7
+#define PMIC_RG_VCORE_OCN_SHIFT 8
+#define PMIC_RG_VCORE_OCP_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RG_VCORE_OCP_MASK 0x7
+#define PMIC_RG_VCORE_OCP_SHIFT 11
+#define PMIC_RGS_VCORE_OC_STATUS_ADDR \
+ MT6389_VCORE_ANA_CON2
+#define PMIC_RGS_VCORE_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VCORE_OC_STATUS_SHIFT 14
+#define PMIC_RG_VCORE_RSV1_ADDR \
+ MT6389_VCORE_ANA_CON3
+#define PMIC_RG_VCORE_RSV1_MASK 0xFF
+#define PMIC_RG_VCORE_RSV1_SHIFT 0
+#define PMIC_RG_VCORE_RSV2_ADDR \
+ MT6389_VCORE_ANA_CON3
+#define PMIC_RG_VCORE_RSV2_MASK 0xFF
+#define PMIC_RG_VCORE_RSV2_SHIFT 8
+#define PMIC_RG_VCORE_UG_ON_SR_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VCORE_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VCORE_NLIM_GATING_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VCORE_NLIM_GATING_SHIFT 2
+#define PMIC_RG_VCORE_NLIM_SRF_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VCORE_NLIM_SRF_SHIFT 3
+#define PMIC_RG_VCORE_POTECT_KEY_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VCORE_POTECT_KEY_SHIFT 4
+#define PMIC_RG_VCORE_LXR_EN_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_LXR_EN_MASK 0x1
+#define PMIC_RG_VCORE_LXR_EN_SHIFT 6
+#define PMIC_RG_VCORE_GPIO_OUTPUT_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VCORE_GPIO_OUTPUT_SHIFT 7
+#define PMIC_RG_VCORE_PARKB_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_PARKB_MASK 0x7
+#define PMIC_RG_VCORE_PARKB_SHIFT 8
+#define PMIC_RG_VCORE_MOS_TMODE_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VCORE_MOS_TMODE_SHIFT 11
+#define PMIC_RG_VCORE_DRV_FORCEFAST_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_DRV_FORCEFAST_MASK 0x1
+#define PMIC_RG_VCORE_DRV_FORCEFAST_SHIFT 12
+#define PMIC_RG_VCORE_PFM_FP_CUTB_ADDR \
+ MT6389_VCORE_ANA_CON4
+#define PMIC_RG_VCORE_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VCORE_PFM_FP_CUTB_SHIFT 13
+#define PMIC_RG_VCORE_VDIFFCAP_EN_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_VDIFFCAP_EN_MASK 0x1
+#define PMIC_RG_VCORE_VDIFFCAP_EN_SHIFT 0
+#define PMIC_RG_VCORE_VBAT_HI_DIS_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_VBAT_HI_DIS_MASK 0x1
+#define PMIC_RG_VCORE_VBAT_HI_DIS_SHIFT 1
+#define PMIC_RG_VCORE_VBAT_LOW_DIS_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_VBAT_LOW_DIS_MASK 0x1
+#define PMIC_RG_VCORE_VBAT_LOW_DIS_SHIFT 2
+#define PMIC_RG_VCORE_VOUT_HI_DIS_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_VOUT_HI_DIS_MASK 0x1
+#define PMIC_RG_VCORE_VOUT_HI_DIS_SHIFT 3
+#define PMIC_RG_VCORE_VDIFF_OFF_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VCORE_VDIFF_OFF_SHIFT 4
+#define PMIC_RG_VCORE_SLP_RSV_ADDR \
+ MT6389_VCORE_ANA_CON5
+#define PMIC_RG_VCORE_SLP_RSV_MASK 0xFF
+#define PMIC_RG_VCORE_SLP_RSV_SHIFT 5
+#define PMIC_BUCK_ANA0_ELR_LEN_ADDR \
+ MT6389_BUCK_ANA0_ELR_NUM
+#define PMIC_BUCK_ANA0_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_ANA0_ELR_LEN_SHIFT 0
+#define PMIC_RG_VPROC_DRIVER_SR_TRIM_ADDR \
+ MT6389_SMPS_ELR_0
+#define PMIC_RG_VPROC_DRIVER_SR_TRIM_MASK 0x7
+#define PMIC_RG_VPROC_DRIVER_SR_TRIM_SHIFT 0
+#define PMIC_RG_VPROC_CCOMP_ADDR \
+ MT6389_SMPS_ELR_0
+#define PMIC_RG_VPROC_CCOMP_MASK 0x3
+#define PMIC_RG_VPROC_CCOMP_SHIFT 3
+#define PMIC_RG_VPROC_RCOMP_ADDR \
+ MT6389_SMPS_ELR_0
+#define PMIC_RG_VPROC_RCOMP_MASK 0xF
+#define PMIC_RG_VPROC_RCOMP_SHIFT 5
+#define PMIC_RG_VPROC_NLIM_TRIM_ADDR \
+ MT6389_SMPS_ELR_0
+#define PMIC_RG_VPROC_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VPROC_NLIM_TRIM_SHIFT 9
+#define PMIC_RG_VPROC_PWMRAMP_SLP_ADDR \
+ MT6389_SMPS_ELR_0
+#define PMIC_RG_VPROC_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VPROC_PWMRAMP_SLP_SHIFT 13
+#define PMIC_RG_VPROC_CSNSLP_TRIM_ADDR \
+ MT6389_SMPS_ELR_1
+#define PMIC_RG_VPROC_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VPROC_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VPROC_ZC_TRIM_ADDR \
+ MT6389_SMPS_ELR_1
+#define PMIC_RG_VPROC_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VPROC_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VPROC_COTRAMP_SLP_ADDR \
+ MT6389_SMPS_ELR_1
+#define PMIC_RG_VPROC_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VPROC_COTRAMP_SLP_SHIFT 6
+#define PMIC_RG_VPROC_RCS_ADDR \
+ MT6389_SMPS_ELR_1
+#define PMIC_RG_VPROC_RCS_MASK 0x7
+#define PMIC_RG_VPROC_RCS_SHIFT 9
+#define PMIC_RG_VPROC_CSPSLP_TRIM_ADDR \
+ MT6389_SMPS_ELR_2
+#define PMIC_RG_VPROC_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VPROC_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VPROC_PFM_PEAK_TRIM_ADDR \
+ MT6389_SMPS_ELR_3
+#define PMIC_RG_VPROC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VPROC_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VPROC_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_SMPS_ELR_3
+#define PMIC_RG_VPROC_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VPROC_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VCORE_DRIVER_SR_TRIM_ADDR \
+ MT6389_SMPS_ELR_4
+#define PMIC_RG_VCORE_DRIVER_SR_TRIM_MASK 0x7
+#define PMIC_RG_VCORE_DRIVER_SR_TRIM_SHIFT 0
+#define PMIC_RG_VCORE_CCOMP_ADDR \
+ MT6389_SMPS_ELR_4
+#define PMIC_RG_VCORE_CCOMP_MASK 0x3
+#define PMIC_RG_VCORE_CCOMP_SHIFT 3
+#define PMIC_RG_VCORE_RCOMP_ADDR \
+ MT6389_SMPS_ELR_4
+#define PMIC_RG_VCORE_RCOMP_MASK 0xF
+#define PMIC_RG_VCORE_RCOMP_SHIFT 5
+#define PMIC_RG_VCORE_NLIM_TRIM_ADDR \
+ MT6389_SMPS_ELR_4
+#define PMIC_RG_VCORE_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VCORE_NLIM_TRIM_SHIFT 9
+#define PMIC_RG_VCORE_PWMRAMP_SLP_ADDR \
+ MT6389_SMPS_ELR_4
+#define PMIC_RG_VCORE_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VCORE_PWMRAMP_SLP_SHIFT 13
+#define PMIC_RG_VCORE_CSNSLP_TRIM_ADDR \
+ MT6389_SMPS_ELR_5
+#define PMIC_RG_VCORE_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VCORE_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VCORE_ZC_TRIM_ADDR \
+ MT6389_SMPS_ELR_5
+#define PMIC_RG_VCORE_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VCORE_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VCORE_COTRAMP_SLP_ADDR \
+ MT6389_SMPS_ELR_5
+#define PMIC_RG_VCORE_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VCORE_COTRAMP_SLP_SHIFT 6
+#define PMIC_RG_VCORE_RCS_ADDR \
+ MT6389_SMPS_ELR_5
+#define PMIC_RG_VCORE_RCS_MASK 0x7
+#define PMIC_RG_VCORE_RCS_SHIFT 9
+#define PMIC_RG_VCORE_CSPSLP_TRIM_ADDR \
+ MT6389_SMPS_ELR_6
+#define PMIC_RG_VCORE_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VCORE_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VCORE_PFM_PEAK_TRIM_ADDR \
+ MT6389_SMPS_ELR_7
+#define PMIC_RG_VCORE_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VCORE_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VCORE_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_SMPS_ELR_7
+#define PMIC_RG_VCORE_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VCORE_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VS1_TRIMH_ADDR \
+ MT6389_SMPS_ELR_8
+#define PMIC_RG_VS1_TRIMH_MASK 0xF
+#define PMIC_RG_VS1_TRIMH_SHIFT 0
+#define PMIC_RG_VS2_TRIMH_ADDR \
+ MT6389_SMPS_ELR_8
+#define PMIC_RG_VS2_TRIMH_MASK 0xF
+#define PMIC_RG_VS2_TRIMH_SHIFT 4
+#define PMIC_RG_VDRAM1_TRIMH_ADDR \
+ MT6389_SMPS_ELR_8
+#define PMIC_RG_VDRAM1_TRIMH_MASK 0xF
+#define PMIC_RG_VDRAM1_TRIMH_SHIFT 8
+#define PMIC_RG_VPROC_TRIMH_ADDR \
+ MT6389_SMPS_ELR_8
+#define PMIC_RG_VPROC_TRIMH_MASK 0xF
+#define PMIC_RG_VPROC_TRIMH_SHIFT 12
+#define PMIC_RG_VCORE_TRIMH_ADDR \
+ MT6389_SMPS_ELR_9
+#define PMIC_RG_VCORE_TRIMH_MASK 0xF
+#define PMIC_RG_VCORE_TRIMH_SHIFT 0
+#define PMIC_RG_VMODEM_TRIMH_ADDR \
+ MT6389_SMPS_ELR_9
+#define PMIC_RG_VMODEM_TRIMH_MASK 0xF
+#define PMIC_RG_VMODEM_TRIMH_SHIFT 4
+#define PMIC_RG_VSRAM_OTHERS_TRIMH_ADDR \
+ MT6389_SMPS_ELR_9
+#define PMIC_RG_VSRAM_OTHERS_TRIMH_MASK 0xF
+#define PMIC_RG_VSRAM_OTHERS_TRIMH_SHIFT 8
+#define PMIC_RG_VPA_TRIMH_ADDR \
+ MT6389_SMPS_ELR_9
+#define PMIC_RG_VPA_TRIMH_MASK 0xF
+#define PMIC_RG_VPA_TRIMH_SHIFT 12
+#define PMIC_RG_VSRAM_PROC_TRIMH_ADDR \
+ MT6389_SMPS_ELR_10
+#define PMIC_RG_VSRAM_PROC_TRIMH_MASK 0x1F
+#define PMIC_RG_VSRAM_PROC_TRIMH_SHIFT 0
+#define PMIC_BUCK_ANA1_ANA_ID_ADDR \
+ MT6389_BUCK_ANA1_DSN_ID
+#define PMIC_BUCK_ANA1_ANA_ID_MASK 0xFF
+#define PMIC_BUCK_ANA1_ANA_ID_SHIFT 0
+#define PMIC_BUCK_ANA1_DIG_ID_ADDR \
+ MT6389_BUCK_ANA1_DSN_ID
+#define PMIC_BUCK_ANA1_DIG_ID_MASK 0xFF
+#define PMIC_BUCK_ANA1_DIG_ID_SHIFT 8
+#define PMIC_BUCK_ANA1_ANA_MINOR_REV_ADDR \
+ MT6389_BUCK_ANA1_DSN_REV0
+#define PMIC_BUCK_ANA1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_ADDR \
+ MT6389_BUCK_ANA1_DSN_REV0
+#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_BUCK_ANA1_DIG_MINOR_REV_ADDR \
+ MT6389_BUCK_ANA1_DSN_REV0
+#define PMIC_BUCK_ANA1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_ADDR \
+ MT6389_BUCK_ANA1_DSN_REV0
+#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_BUCK_ANA1_DSN_CBS_ADDR \
+ MT6389_BUCK_ANA1_DSN_DBI
+#define PMIC_BUCK_ANA1_DSN_CBS_MASK 0x3
+#define PMIC_BUCK_ANA1_DSN_CBS_SHIFT 0
+#define PMIC_BUCK_ANA1_DSN_BIX_ADDR \
+ MT6389_BUCK_ANA1_DSN_DBI
+#define PMIC_BUCK_ANA1_DSN_BIX_MASK 0x3
+#define PMIC_BUCK_ANA1_DSN_BIX_SHIFT 2
+#define PMIC_BUCK_ANA1_DSN_ESP_ADDR \
+ MT6389_BUCK_ANA1_DSN_DBI
+#define PMIC_BUCK_ANA1_DSN_ESP_MASK 0xFF
+#define PMIC_BUCK_ANA1_DSN_ESP_SHIFT 8
+#define PMIC_BUCK_ANA1_DSN_FPI_ADDR \
+ MT6389_BUCK_ANA1_DSN_FPI
+#define PMIC_BUCK_ANA1_DSN_FPI_MASK 0xFF
+#define PMIC_BUCK_ANA1_DSN_FPI_SHIFT 0
+#define PMIC_RG_VMODEM_SR_VBAT_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_SR_VBAT_MASK 0x1
+#define PMIC_RG_VMODEM_SR_VBAT_SHIFT 0
+#define PMIC_RG_VMODEM_NDIS_EN_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_NDIS_EN_MASK 0x1
+#define PMIC_RG_VMODEM_NDIS_EN_SHIFT 1
+#define PMIC_RG_VMODEM_SR_EN_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_SR_EN_MASK 0x1
+#define PMIC_RG_VMODEM_SR_EN_SHIFT 2
+#define PMIC_RG_VMODEM_SLEEP_TIME_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VMODEM_SLEEP_TIME_SHIFT 3
+#define PMIC_RG_VMODEM_LOOPSEL_DIS_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_LOOPSEL_DIS_MASK 0x1
+#define PMIC_RG_VMODEM_LOOPSEL_DIS_SHIFT 5
+#define PMIC_RG_VMODEM_TB_DIS_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_TB_DIS_MASK 0x1
+#define PMIC_RG_VMODEM_TB_DIS_SHIFT 6
+#define PMIC_RG_VMODEM_TB_PFM_OFF_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_TB_PFM_OFF_MASK 0x1
+#define PMIC_RG_VMODEM_TB_PFM_OFF_SHIFT 7
+#define PMIC_RG_VMODEM_TB_VREFSEL_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_TB_VREFSEL_MASK 0x3
+#define PMIC_RG_VMODEM_TB_VREFSEL_SHIFT 8
+#define PMIC_RG_VMODEM_TB_WIDTH_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VMODEM_TB_WIDTH_SHIFT 10
+#define PMIC_RG_VMODEM_DUMMY_LOAD_EN_ADDR \
+ MT6389_VMODEM_ANA_CON0
+#define PMIC_RG_VMODEM_DUMMY_LOAD_EN_MASK 0x1
+#define PMIC_RG_VMODEM_DUMMY_LOAD_EN_SHIFT 12
+#define PMIC_RGS_VMODEM_DIG_MON_ADDR \
+ MT6389_VMODEM_ANA_CON1
+#define PMIC_RGS_VMODEM_DIG_MON_MASK 0x1
+#define PMIC_RGS_VMODEM_DIG_MON_SHIFT 9
+#define PMIC_RG_VMODEM_UG_SR_ADDR \
+ MT6389_VMODEM_ANA_CON1
+#define PMIC_RG_VMODEM_UG_SR_MASK 0x3
+#define PMIC_RG_VMODEM_UG_SR_SHIFT 10
+#define PMIC_RG_VMODEM_LG_SR_ADDR \
+ MT6389_VMODEM_ANA_CON1
+#define PMIC_RG_VMODEM_LG_SR_MASK 0x3
+#define PMIC_RG_VMODEM_LG_SR_SHIFT 12
+#define PMIC_RG_VMODEM_TMDL_ADDR \
+ MT6389_VMODEM_ANA_CON1
+#define PMIC_RG_VMODEM_TMDL_MASK 0x1
+#define PMIC_RG_VMODEM_TMDL_SHIFT 14
+#define PMIC_RG_VMODEM_FUGON_ADDR \
+ MT6389_VMODEM_ANA_CON1
+#define PMIC_RG_VMODEM_FUGON_MASK 0x1
+#define PMIC_RG_VMODEM_FUGON_SHIFT 15
+#define PMIC_RG_VMODEM_FLGON_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_FLGON_MASK 0x1
+#define PMIC_RG_VMODEM_FLGON_SHIFT 0
+#define PMIC_RG_VMODEM_FCCM_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_FCCM_MASK 0x1
+#define PMIC_RG_VMODEM_FCCM_SHIFT 1
+#define PMIC_RG_VMODEM_NONAUDIBLE_EN_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VMODEM_NONAUDIBLE_EN_SHIFT 2
+#define PMIC_RG_VMODEM_RETENTION_EN_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_RETENTION_EN_MASK 0x1
+#define PMIC_RG_VMODEM_RETENTION_EN_SHIFT 3
+#define PMIC_RG_VMODEM_VDIFFPFM_OFF_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VMODEM_VDIFFPFM_OFF_SHIFT 4
+#define PMIC_RG_VMODEM_DIGMON_SEL_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VMODEM_DIGMON_SEL_SHIFT 5
+#define PMIC_RG_VMODEM_OCN_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_OCN_MASK 0x7
+#define PMIC_RG_VMODEM_OCN_SHIFT 8
+#define PMIC_RG_VMODEM_OCP_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RG_VMODEM_OCP_MASK 0x7
+#define PMIC_RG_VMODEM_OCP_SHIFT 11
+#define PMIC_RGS_VMODEM_OC_STATUS_ADDR \
+ MT6389_VMODEM_ANA_CON2
+#define PMIC_RGS_VMODEM_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VMODEM_OC_STATUS_SHIFT 14
+#define PMIC_RG_VMODEM_RSV1_ADDR \
+ MT6389_VMODEM_ANA_CON3
+#define PMIC_RG_VMODEM_RSV1_MASK 0xFF
+#define PMIC_RG_VMODEM_RSV1_SHIFT 0
+#define PMIC_RG_VMODEM_RSV2_ADDR \
+ MT6389_VMODEM_ANA_CON3
+#define PMIC_RG_VMODEM_RSV2_MASK 0xFF
+#define PMIC_RG_VMODEM_RSV2_SHIFT 8
+#define PMIC_RG_VMODEM_UG_ON_SR_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VMODEM_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VMODEM_NLIM_GATING_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VMODEM_NLIM_GATING_SHIFT 2
+#define PMIC_RG_VMODEM_NLIM_SRF_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VMODEM_NLIM_SRF_SHIFT 3
+#define PMIC_RG_VMODEM_POTECT_KEY_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VMODEM_POTECT_KEY_SHIFT 4
+#define PMIC_RG_VMODEM_LXR_EN_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_LXR_EN_MASK 0x1
+#define PMIC_RG_VMODEM_LXR_EN_SHIFT 6
+#define PMIC_RG_VMODEM_GPIO_OUTPUT_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VMODEM_GPIO_OUTPUT_SHIFT 7
+#define PMIC_RG_VMODEM_PARKB_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_PARKB_MASK 0x7
+#define PMIC_RG_VMODEM_PARKB_SHIFT 8
+#define PMIC_RG_VMODEM_MOS_TMODE_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VMODEM_MOS_TMODE_SHIFT 11
+#define PMIC_RG_VMODEM_DRV_FORCEFAST_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_DRV_FORCEFAST_MASK 0x1
+#define PMIC_RG_VMODEM_DRV_FORCEFAST_SHIFT 12
+#define PMIC_RG_VMODEM_PFM_FP_CUTB_ADDR \
+ MT6389_VMODEM_ANA_CON4
+#define PMIC_RG_VMODEM_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VMODEM_PFM_FP_CUTB_SHIFT 13
+#define PMIC_RG_VMODEM_VDIFFCAP_EN_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_VDIFFCAP_EN_MASK 0x1
+#define PMIC_RG_VMODEM_VDIFFCAP_EN_SHIFT 0
+#define PMIC_RG_VMODEM_VBAT_HI_DIS_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_VBAT_HI_DIS_MASK 0x1
+#define PMIC_RG_VMODEM_VBAT_HI_DIS_SHIFT 1
+#define PMIC_RG_VMODEM_VBAT_LOW_DIS_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_VBAT_LOW_DIS_MASK 0x1
+#define PMIC_RG_VMODEM_VBAT_LOW_DIS_SHIFT 2
+#define PMIC_RG_VMODEM_VOUT_HI_DIS_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_VOUT_HI_DIS_MASK 0x1
+#define PMIC_RG_VMODEM_VOUT_HI_DIS_SHIFT 3
+#define PMIC_RG_VMODEM_VDIFF_OFF_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VMODEM_VDIFF_OFF_SHIFT 4
+#define PMIC_RG_VMODEM_SLP_RSV_ADDR \
+ MT6389_VMODEM_ANA_CON5
+#define PMIC_RG_VMODEM_SLP_RSV_MASK 0xFF
+#define PMIC_RG_VMODEM_SLP_RSV_SHIFT 5
+#define PMIC_RG_VS1_TB_DIS_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_TB_DIS_MASK 0x1
+#define PMIC_RG_VS1_TB_DIS_SHIFT 0
+#define PMIC_RG_VS1_FCCM_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_FCCM_MASK 0x1
+#define PMIC_RG_VS1_FCCM_SHIFT 1
+#define PMIC_RG_VS1_UG_SR_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_UG_SR_MASK 0x3
+#define PMIC_RG_VS1_UG_SR_SHIFT 2
+#define PMIC_RG_VS1_LG_SR_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_LG_SR_MASK 0x3
+#define PMIC_RG_VS1_LG_SR_SHIFT 4
+#define PMIC_RG_VS1_POTECT_KEY_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VS1_POTECT_KEY_SHIFT 6
+#define PMIC_RG_VS1_NLIM_GATING_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VS1_NLIM_GATING_SHIFT 8
+#define PMIC_RG_VS1_SLEEP_TIME_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VS1_SLEEP_TIME_SHIFT 9
+#define PMIC_RG_VS1_VREFUP_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_VREFUP_MASK 0x3
+#define PMIC_RG_VS1_VREFUP_SHIFT 11
+#define PMIC_RG_VS1_TB_WIDTH_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VS1_TB_WIDTH_SHIFT 13
+#define PMIC_RG_VS1_NDIS_EN_ADDR \
+ MT6389_VS1_ANA_CON0
+#define PMIC_RG_VS1_NDIS_EN_MASK 0x1
+#define PMIC_RG_VS1_NDIS_EN_SHIFT 15
+#define PMIC_RG_VS1_RSV1_ADDR \
+ MT6389_VS1_ANA_CON1
+#define PMIC_RG_VS1_RSV1_MASK 0xFF
+#define PMIC_RG_VS1_RSV1_SHIFT 0
+#define PMIC_RG_VS1_RSV2_ADDR \
+ MT6389_VS1_ANA_CON1
+#define PMIC_RG_VS1_RSV2_MASK 0xFF
+#define PMIC_RG_VS1_RSV2_SHIFT 8
+#define PMIC_RG_VS1_FUGON_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_FUGON_MASK 0x1
+#define PMIC_RG_VS1_FUGON_SHIFT 0
+#define PMIC_RG_VS1_FLGON_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_FLGON_MASK 0x1
+#define PMIC_RG_VS1_FLGON_SHIFT 1
+#define PMIC_RG_VS1_OCP_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_OCP_MASK 0x7
+#define PMIC_RG_VS1_OCP_SHIFT 2
+#define PMIC_RG_VS1_OCN_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_OCN_MASK 0x7
+#define PMIC_RG_VS1_OCN_SHIFT 5
+#define PMIC_RGS_VS1_OC_STATUS_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RGS_VS1_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VS1_OC_STATUS_SHIFT 8
+#define PMIC_RG_VS1_TMDL_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_TMDL_MASK 0x1
+#define PMIC_RG_VS1_TMDL_SHIFT 9
+#define PMIC_RGS_VS1_DIG_MON_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RGS_VS1_DIG_MON_MASK 0x1
+#define PMIC_RGS_VS1_DIG_MON_SHIFT 10
+#define PMIC_RG_VS1_NONAUDIBLE_EN_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VS1_NONAUDIBLE_EN_SHIFT 11
+#define PMIC_RG_VS1_LXR_EN_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_LXR_EN_MASK 0x1
+#define PMIC_RG_VS1_LXR_EN_SHIFT 12
+#define PMIC_RG_VS1_DIGMON_SEL_ADDR \
+ MT6389_VS1_ANA_CON2
+#define PMIC_RG_VS1_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VS1_DIGMON_SEL_SHIFT 13
+#define PMIC_RG_VS1_UG_ON_SR_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VS1_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VS1_GPIO_OUTPUT_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VS1_GPIO_OUTPUT_SHIFT 2
+#define PMIC_RG_VS1_PARKB_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_PARKB_MASK 0x7
+#define PMIC_RG_VS1_PARKB_SHIFT 3
+#define PMIC_RG_VS1_NLIM_SRF_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VS1_NLIM_SRF_SHIFT 6
+#define PMIC_RG_VS1_PFM_FP_CUTB_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VS1_PFM_FP_CUTB_SHIFT 7
+#define PMIC_RG_VS1_MOS_TMODE_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VS1_MOS_TMODE_SHIFT 8
+#define PMIC_RG_VS1_DISPG_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_DISPG_MASK 0x1
+#define PMIC_RG_VS1_DISPG_SHIFT 9
+#define PMIC_RG_VS1_VBATHI_PK_DIS_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_VBATHI_PK_DIS_MASK 0x1
+#define PMIC_RG_VS1_VBATHI_PK_DIS_SHIFT 10
+#define PMIC_RG_VS1_PKBS_ADDR \
+ MT6389_VS1_ANA_CON3
+#define PMIC_RG_VS1_PKBS_MASK 0x1
+#define PMIC_RG_VS1_PKBS_SHIFT 11
+#define PMIC_RG_VS1_VDIFFPFM_OFF_ADDR \
+ MT6389_VS1_ANA_CON4
+#define PMIC_RG_VS1_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VS1_VDIFFPFM_OFF_SHIFT 0
+#define PMIC_RG_VS1_VDIFF_OFF_ADDR \
+ MT6389_VS1_ANA_CON4
+#define PMIC_RG_VS1_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VS1_VDIFF_OFF_SHIFT 1
+#define PMIC_RG_VS1_VDIFF_CAP_EN_ADDR \
+ MT6389_VS1_ANA_CON4
+#define PMIC_RG_VS1_VDIFF_CAP_EN_MASK 0x1
+#define PMIC_RG_VS1_VDIFF_CAP_EN_SHIFT 2
+#define PMIC_RG_VS2_TB_DIS_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_TB_DIS_MASK 0x1
+#define PMIC_RG_VS2_TB_DIS_SHIFT 0
+#define PMIC_RG_VS2_FCCM_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_FCCM_MASK 0x1
+#define PMIC_RG_VS2_FCCM_SHIFT 1
+#define PMIC_RG_VS2_UG_SR_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_UG_SR_MASK 0x3
+#define PMIC_RG_VS2_UG_SR_SHIFT 2
+#define PMIC_RG_VS2_LG_SR_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_LG_SR_MASK 0x3
+#define PMIC_RG_VS2_LG_SR_SHIFT 4
+#define PMIC_RG_VS2_POTECT_KEY_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VS2_POTECT_KEY_SHIFT 6
+#define PMIC_RG_VS2_NLIM_GATING_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VS2_NLIM_GATING_SHIFT 8
+#define PMIC_RG_VS2_SLEEP_TIME_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VS2_SLEEP_TIME_SHIFT 9
+#define PMIC_RG_VS2_VREFUP_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_VREFUP_MASK 0x3
+#define PMIC_RG_VS2_VREFUP_SHIFT 11
+#define PMIC_RG_VS2_TB_WIDTH_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VS2_TB_WIDTH_SHIFT 13
+#define PMIC_RG_VS2_NDIS_EN_ADDR \
+ MT6389_VS2_ANA_CON0
+#define PMIC_RG_VS2_NDIS_EN_MASK 0x1
+#define PMIC_RG_VS2_NDIS_EN_SHIFT 15
+#define PMIC_RG_VS2_RSV1_ADDR \
+ MT6389_VS2_ANA_CON1
+#define PMIC_RG_VS2_RSV1_MASK 0xFF
+#define PMIC_RG_VS2_RSV1_SHIFT 0
+#define PMIC_RG_VS2_RSV2_ADDR \
+ MT6389_VS2_ANA_CON1
+#define PMIC_RG_VS2_RSV2_MASK 0xFF
+#define PMIC_RG_VS2_RSV2_SHIFT 8
+#define PMIC_RG_VS2_FUGON_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_FUGON_MASK 0x1
+#define PMIC_RG_VS2_FUGON_SHIFT 0
+#define PMIC_RG_VS2_FLGON_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_FLGON_MASK 0x1
+#define PMIC_RG_VS2_FLGON_SHIFT 1
+#define PMIC_RG_VS2_OCP_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_OCP_MASK 0x7
+#define PMIC_RG_VS2_OCP_SHIFT 2
+#define PMIC_RG_VS2_OCN_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_OCN_MASK 0x7
+#define PMIC_RG_VS2_OCN_SHIFT 5
+#define PMIC_RGS_VS2_OC_STATUS_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RGS_VS2_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VS2_OC_STATUS_SHIFT 8
+#define PMIC_RG_VS2_TMDL_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_TMDL_MASK 0x1
+#define PMIC_RG_VS2_TMDL_SHIFT 9
+#define PMIC_RGS_VS2_DIG_MON_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RGS_VS2_DIG_MON_MASK 0x1
+#define PMIC_RGS_VS2_DIG_MON_SHIFT 10
+#define PMIC_RG_VS2_NONAUDIBLE_EN_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VS2_NONAUDIBLE_EN_SHIFT 11
+#define PMIC_RG_VS2_LXR_EN_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_LXR_EN_MASK 0x1
+#define PMIC_RG_VS2_LXR_EN_SHIFT 12
+#define PMIC_RG_VS2_DIGMON_SEL_ADDR \
+ MT6389_VS2_ANA_CON2
+#define PMIC_RG_VS2_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VS2_DIGMON_SEL_SHIFT 13
+#define PMIC_RG_VS2_UG_ON_SR_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VS2_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VS2_GPIO_OUTPUT_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VS2_GPIO_OUTPUT_SHIFT 2
+#define PMIC_RG_VS2_PARKB_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_PARKB_MASK 0x7
+#define PMIC_RG_VS2_PARKB_SHIFT 3
+#define PMIC_RG_VS2_NLIM_SRF_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VS2_NLIM_SRF_SHIFT 6
+#define PMIC_RG_VS2_PFM_FP_CUTB_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VS2_PFM_FP_CUTB_SHIFT 7
+#define PMIC_RG_VS2_MOS_TMODE_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VS2_MOS_TMODE_SHIFT 8
+#define PMIC_RG_VS2_DISPG_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_DISPG_MASK 0x1
+#define PMIC_RG_VS2_DISPG_SHIFT 9
+#define PMIC_RG_VS2_VBATHI_PK_DIS_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_VBATHI_PK_DIS_MASK 0x1
+#define PMIC_RG_VS2_VBATHI_PK_DIS_SHIFT 10
+#define PMIC_RG_VS2_PKBS_ADDR \
+ MT6389_VS2_ANA_CON3
+#define PMIC_RG_VS2_PKBS_MASK 0x1
+#define PMIC_RG_VS2_PKBS_SHIFT 11
+#define PMIC_RG_VS2_VDIFFPFM_OFF_ADDR \
+ MT6389_VS2_ANA_CON4
+#define PMIC_RG_VS2_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VS2_VDIFFPFM_OFF_SHIFT 0
+#define PMIC_RG_VS2_VDIFF_OFF_ADDR \
+ MT6389_VS2_ANA_CON4
+#define PMIC_RG_VS2_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VS2_VDIFF_OFF_SHIFT 1
+#define PMIC_RG_VS2_VDIFF_CAP_EN_ADDR \
+ MT6389_VS2_ANA_CON4
+#define PMIC_RG_VS2_VDIFF_CAP_EN_MASK 0x1
+#define PMIC_RG_VS2_VDIFF_CAP_EN_SHIFT 2
+#define PMIC_RG_VPA_NDIS_EN_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_NDIS_EN_MASK 0x1
+#define PMIC_RG_VPA_NDIS_EN_SHIFT 0
+#define PMIC_RG_VPA_MODESET_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_MODESET_MASK 0x1
+#define PMIC_RG_VPA_MODESET_SHIFT 1
+#define PMIC_RG_VPA_CC_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_CC_MASK 0x3
+#define PMIC_RG_VPA_CC_SHIFT 2
+#define PMIC_RG_VPA_CSR_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_CSR_MASK 0x3
+#define PMIC_RG_VPA_CSR_SHIFT 4
+#define PMIC_RG_VPA_CSMIR_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_CSMIR_MASK 0x3
+#define PMIC_RG_VPA_CSMIR_SHIFT 6
+#define PMIC_RG_VPA_CSL_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_CSL_MASK 0x3
+#define PMIC_RG_VPA_CSL_SHIFT 8
+#define PMIC_RG_VPA_SLP_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_SLP_MASK 0x3
+#define PMIC_RG_VPA_SLP_SHIFT 10
+#define PMIC_RG_VPA_ZXFT_L_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_ZXFT_L_MASK 0x1
+#define PMIC_RG_VPA_ZXFT_L_SHIFT 12
+#define PMIC_RG_VPA_CP_FWUPOFF_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_CP_FWUPOFF_MASK 0x1
+#define PMIC_RG_VPA_CP_FWUPOFF_SHIFT 13
+#define PMIC_RG_VPA_NONAUDIBLE_EN_ADDR \
+ MT6389_VPA_ANA_CON0
+#define PMIC_RG_VPA_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VPA_NONAUDIBLE_EN_SHIFT 14
+#define PMIC_RG_VPA_RZSEL_ADDR \
+ MT6389_VPA_ANA_CON1
+#define PMIC_RG_VPA_RZSEL_MASK 0x3
+#define PMIC_RG_VPA_RZSEL_SHIFT 0
+#define PMIC_RG_VPA_SLEW_ADDR \
+ MT6389_VPA_ANA_CON1
+#define PMIC_RG_VPA_SLEW_MASK 0x3
+#define PMIC_RG_VPA_SLEW_SHIFT 2
+#define PMIC_RG_VPA_SLEW_NMOS_ADDR \
+ MT6389_VPA_ANA_CON1
+#define PMIC_RG_VPA_SLEW_NMOS_MASK 0x3
+#define PMIC_RG_VPA_SLEW_NMOS_SHIFT 4
+#define PMIC_RG_VPA_MIN_ON_ADDR \
+ MT6389_VPA_ANA_CON1
+#define PMIC_RG_VPA_MIN_ON_MASK 0x3
+#define PMIC_RG_VPA_MIN_ON_SHIFT 6
+#define PMIC_RG_VPA_BURST_SEL_ADDR \
+ MT6389_VPA_ANA_CON1
+#define PMIC_RG_VPA_BURST_SEL_MASK 0x3
+#define PMIC_RG_VPA_BURST_SEL_SHIFT 8
+#define PMIC_RG_VPA_ZC_ADDR \
+ MT6389_VPA_ANA_CON2
+#define PMIC_RG_VPA_ZC_MASK 0x3
+#define PMIC_RG_VPA_ZC_SHIFT 0
+#define PMIC_RG_VPA_RSV1_ADDR \
+ MT6389_VPA_ANA_CON2
+#define PMIC_RG_VPA_RSV1_MASK 0xFF
+#define PMIC_RG_VPA_RSV1_SHIFT 8
+#define PMIC_RG_VPA_RSV2_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RG_VPA_RSV2_MASK 0xFF
+#define PMIC_RG_VPA_RSV2_SHIFT 0
+#define PMIC_RGS_VPA_OC_STATUS_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RGS_VPA_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VPA_OC_STATUS_SHIFT 8
+#define PMIC_RGS_VPA_AZC_ZX_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RGS_VPA_AZC_ZX_MASK 0x1
+#define PMIC_RGS_VPA_AZC_ZX_SHIFT 9
+#define PMIC_RGS_VPA_DIG_MON_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RGS_VPA_DIG_MON_MASK 0x1
+#define PMIC_RGS_VPA_DIG_MON_SHIFT 10
+#define PMIC_RG_VPA_PFM_DLC1_VTH_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RG_VPA_PFM_DLC1_VTH_MASK 0x3
+#define PMIC_RG_VPA_PFM_DLC1_VTH_SHIFT 11
+#define PMIC_RG_VPA_PFM_DLC2_VTH_ADDR \
+ MT6389_VPA_ANA_CON3
+#define PMIC_RG_VPA_PFM_DLC2_VTH_MASK 0x3
+#define PMIC_RG_VPA_PFM_DLC2_VTH_SHIFT 13
+#define PMIC_RG_VPA_PFM_DLC3_VTH_ADDR \
+ MT6389_VPA_ANA_CON4
+#define PMIC_RG_VPA_PFM_DLC3_VTH_MASK 0x3
+#define PMIC_RG_VPA_PFM_DLC3_VTH_SHIFT 0
+#define PMIC_RG_VPA_PFM_DLC4_VTH_ADDR \
+ MT6389_VPA_ANA_CON4
+#define PMIC_RG_VPA_PFM_DLC4_VTH_MASK 0x3
+#define PMIC_RG_VPA_PFM_DLC4_VTH_SHIFT 2
+#define PMIC_RG_VPA_ZXFT_H_ADDR \
+ MT6389_VPA_ANA_CON4
+#define PMIC_RG_VPA_ZXFT_H_MASK 0x1
+#define PMIC_RG_VPA_ZXFT_H_SHIFT 4
+#define PMIC_RG_VPA_DECODE_TMB_ADDR \
+ MT6389_VPA_ANA_CON4
+#define PMIC_RG_VPA_DECODE_TMB_MASK 0x1
+#define PMIC_RG_VPA_DECODE_TMB_SHIFT 5
+#define PMIC_RG_VPA_RSV3_ADDR \
+ MT6389_VPA_ANA_CON4
+#define PMIC_RG_VPA_RSV3_MASK 0xFF
+#define PMIC_RG_VPA_RSV3_SHIFT 8
+#define PMIC_RG_VPA_DGM_RSV1_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DGM_RSV1_V18_MASK 0xFF
+#define PMIC_RG_VPA_DGM_RSV1_V18_SHIFT 0
+#define PMIC_RG_VPA_DGM_EN_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DGM_EN_V18_MASK 0x1
+#define PMIC_RG_VPA_DGM_EN_V18_SHIFT 8
+#define PMIC_RG_VPA_DGM_IMAX_SEL_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DGM_IMAX_SEL_V18_MASK 0x3
+#define PMIC_RG_VPA_DGM_IMAX_SEL_V18_SHIFT 9
+#define PMIC_RG_VPA_DGM_S0_VTH_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DGM_S0_VTH_V18_MASK 0x3
+#define PMIC_RG_VPA_DGM_S0_VTH_V18_SHIFT 11
+#define PMIC_RG_VPA_DGM_S1_VTH_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DGM_S1_VTH_V18_MASK 0x3
+#define PMIC_RG_VPA_DGM_S1_VTH_V18_SHIFT 13
+#define PMIC_RG_VPA_DVS_HYS_EN_V18_ADDR \
+ MT6389_VPA_ANA_CON5
+#define PMIC_RG_VPA_DVS_HYS_EN_V18_MASK 0x1
+#define PMIC_RG_VPA_DVS_HYS_EN_V18_SHIFT 15
+#define PMIC_RG_VPA_DGM_RSV2_V18_ADDR \
+ MT6389_VPA_ANA_CON6
+#define PMIC_RG_VPA_DGM_RSV2_V18_MASK 0xFF
+#define PMIC_RG_VPA_DGM_RSV2_V18_SHIFT 0
+#define PMIC_RG_VPA_DGM_S2_VTH_V18_ADDR \
+ MT6389_VPA_ANA_CON6
+#define PMIC_RG_VPA_DGM_S2_VTH_V18_MASK 0x3
+#define PMIC_RG_VPA_DGM_S2_VTH_V18_SHIFT 8
+#define PMIC_RG_VPA_DGM_S3_VTH_V18_ADDR \
+ MT6389_VPA_ANA_CON6
+#define PMIC_RG_VPA_DGM_S3_VTH_V18_MASK 0x3
+#define PMIC_RG_VPA_DGM_S3_VTH_V18_SHIFT 10
+#define PMIC_RG_VPA_HYS_VTH_V18_ADDR \
+ MT6389_VPA_ANA_CON6
+#define PMIC_RG_VPA_HYS_VTH_V18_MASK 0x3
+#define PMIC_RG_VPA_HYS_VTH_V18_SHIFT 12
+#define PMIC_RG_VDRAM1_TB_DIS_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_TB_DIS_MASK 0x1
+#define PMIC_RG_VDRAM1_TB_DIS_SHIFT 0
+#define PMIC_RG_VDRAM1_FCCM_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_FCCM_MASK 0x1
+#define PMIC_RG_VDRAM1_FCCM_SHIFT 1
+#define PMIC_RG_VDRAM1_UG_SR_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_UG_SR_MASK 0x3
+#define PMIC_RG_VDRAM1_UG_SR_SHIFT 2
+#define PMIC_RG_VDRAM1_LG_SR_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_LG_SR_MASK 0x3
+#define PMIC_RG_VDRAM1_LG_SR_SHIFT 4
+#define PMIC_RG_VDRAM1_POTECT_KEY_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VDRAM1_POTECT_KEY_SHIFT 6
+#define PMIC_RG_VDRAM1_NLIM_GATING_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VDRAM1_NLIM_GATING_SHIFT 8
+#define PMIC_RG_VDRAM1_SLEEP_TIME_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VDRAM1_SLEEP_TIME_SHIFT 9
+#define PMIC_RG_VDRAM1_VREFUP_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_VREFUP_MASK 0x3
+#define PMIC_RG_VDRAM1_VREFUP_SHIFT 11
+#define PMIC_RG_VDRAM1_TB_WIDTH_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VDRAM1_TB_WIDTH_SHIFT 13
+#define PMIC_RG_VDRAM1_NDIS_EN_ADDR \
+ MT6389_VDRAM1_ANA_CON0
+#define PMIC_RG_VDRAM1_NDIS_EN_MASK 0x1
+#define PMIC_RG_VDRAM1_NDIS_EN_SHIFT 15
+#define PMIC_RG_VDRAM1_RSV1_ADDR \
+ MT6389_VDRAM1_ANA_CON1
+#define PMIC_RG_VDRAM1_RSV1_MASK 0xFF
+#define PMIC_RG_VDRAM1_RSV1_SHIFT 0
+#define PMIC_RG_VDRAM1_RSV2_ADDR \
+ MT6389_VDRAM1_ANA_CON1
+#define PMIC_RG_VDRAM1_RSV2_MASK 0xFF
+#define PMIC_RG_VDRAM1_RSV2_SHIFT 8
+#define PMIC_RG_VDRAM1_FUGON_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_FUGON_MASK 0x1
+#define PMIC_RG_VDRAM1_FUGON_SHIFT 0
+#define PMIC_RG_VDRAM1_FLGON_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_FLGON_MASK 0x1
+#define PMIC_RG_VDRAM1_FLGON_SHIFT 1
+#define PMIC_RG_VDRAM1_OCP_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_OCP_MASK 0x7
+#define PMIC_RG_VDRAM1_OCP_SHIFT 2
+#define PMIC_RG_VDRAM1_OCN_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_OCN_MASK 0x7
+#define PMIC_RG_VDRAM1_OCN_SHIFT 5
+#define PMIC_RGS_VDRAM1_OC_STATUS_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RGS_VDRAM1_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VDRAM1_OC_STATUS_SHIFT 8
+#define PMIC_RG_VDRAM1_TMDL_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_TMDL_MASK 0x1
+#define PMIC_RG_VDRAM1_TMDL_SHIFT 9
+#define PMIC_RGS_VDRAM1_DIG_MON_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RGS_VDRAM1_DIG_MON_MASK 0x1
+#define PMIC_RGS_VDRAM1_DIG_MON_SHIFT 10
+#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_SHIFT 11
+#define PMIC_RG_VDRAM1_LXR_EN_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_LXR_EN_MASK 0x1
+#define PMIC_RG_VDRAM1_LXR_EN_SHIFT 12
+#define PMIC_RG_VDRAM1_DIGMON_SEL_ADDR \
+ MT6389_VDRAM1_ANA_CON2
+#define PMIC_RG_VDRAM1_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VDRAM1_DIGMON_SEL_SHIFT 13
+#define PMIC_RG_VDRAM1_UG_ON_SR_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VDRAM1_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VDRAM1_GPIO_OUTPUT_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VDRAM1_GPIO_OUTPUT_SHIFT 2
+#define PMIC_RG_VDRAM1_PARKB_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_PARKB_MASK 0x7
+#define PMIC_RG_VDRAM1_PARKB_SHIFT 3
+#define PMIC_RG_VDRAM1_NLIM_SRF_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VDRAM1_NLIM_SRF_SHIFT 6
+#define PMIC_RG_VDRAM1_PFM_FP_CUTB_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VDRAM1_PFM_FP_CUTB_SHIFT 7
+#define PMIC_RG_VDRAM1_MOS_TMODE_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VDRAM1_MOS_TMODE_SHIFT 8
+#define PMIC_RG_VDRAM1_DISPG_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_DISPG_MASK 0x1
+#define PMIC_RG_VDRAM1_DISPG_SHIFT 9
+#define PMIC_RG_VDRAM1_VBATHI_PK_DIS_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_VBATHI_PK_DIS_MASK 0x1
+#define PMIC_RG_VDRAM1_VBATHI_PK_DIS_SHIFT 10
+#define PMIC_RG_VDRAM1_PKBS_ADDR \
+ MT6389_VDRAM1_ANA_CON3
+#define PMIC_RG_VDRAM1_PKBS_MASK 0x1
+#define PMIC_RG_VDRAM1_PKBS_SHIFT 11
+#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_ADDR \
+ MT6389_VDRAM1_ANA_CON4
+#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_SHIFT 0
+#define PMIC_RG_VDRAM1_VDIFF_OFF_ADDR \
+ MT6389_VDRAM1_ANA_CON4
+#define PMIC_RG_VDRAM1_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VDRAM1_VDIFF_OFF_SHIFT 1
+#define PMIC_RG_VDRAM1_VDIFF_CAP_EN_ADDR \
+ MT6389_VDRAM1_ANA_CON4
+#define PMIC_RG_VDRAM1_VDIFF_CAP_EN_MASK 0x1
+#define PMIC_RG_VDRAM1_VDIFF_CAP_EN_SHIFT 2
+#define PMIC_RG_VSRAM_OTHERS_SR_VBAT_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_SR_VBAT_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_SR_VBAT_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_SHIFT 1
+#define PMIC_RG_VSRAM_OTHERS_SR_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_SR_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_SR_EN_SHIFT 2
+#define PMIC_RG_VSRAM_OTHERS_SLEEP_TIME_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_SLEEP_TIME_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_SLEEP_TIME_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_LOOPSEL_DIS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_LOOPSEL_DIS_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_LOOPSEL_DIS_SHIFT 5
+#define PMIC_RG_VSRAM_OTHERS_TB_DIS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_TB_DIS_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_TB_DIS_SHIFT 6
+#define PMIC_RG_VSRAM_OTHERS_TB_PFM_OFF_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_TB_PFM_OFF_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_TB_PFM_OFF_SHIFT 7
+#define PMIC_RG_VSRAM_OTHERS_TB_VREFSEL_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_TB_VREFSEL_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_TB_VREFSEL_SHIFT 8
+#define PMIC_RG_VSRAM_OTHERS_TB_WIDTH_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_TB_WIDTH_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_TB_WIDTH_SHIFT 10
+#define PMIC_RG_VSRAM_OTHERS_DUMMY_LOAD_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON0
+#define PMIC_RG_VSRAM_OTHERS_DUMMY_LOAD_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_DUMMY_LOAD_EN_SHIFT 12
+#define PMIC_RGS_VSRAM_OTHERS_DIG_MON_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON1
+#define PMIC_RGS_VSRAM_OTHERS_DIG_MON_MASK 0x1
+#define PMIC_RGS_VSRAM_OTHERS_DIG_MON_SHIFT 9
+#define PMIC_RG_VSRAM_OTHERS_UG_SR_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON1
+#define PMIC_RG_VSRAM_OTHERS_UG_SR_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_UG_SR_SHIFT 10
+#define PMIC_RG_VSRAM_OTHERS_LG_SR_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON1
+#define PMIC_RG_VSRAM_OTHERS_LG_SR_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_LG_SR_SHIFT 12
+#define PMIC_RG_VSRAM_OTHERS_TMDL_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON1
+#define PMIC_RG_VSRAM_OTHERS_TMDL_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_TMDL_SHIFT 14
+#define PMIC_RG_VSRAM_OTHERS_FUGON_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON1
+#define PMIC_RG_VSRAM_OTHERS_FUGON_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_FUGON_SHIFT 15
+#define PMIC_RG_VSRAM_OTHERS_FLGON_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_FLGON_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_FLGON_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_FCCM_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_FCCM_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_FCCM_SHIFT 1
+#define PMIC_RG_VSRAM_OTHERS_NONAUDIBLE_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_NONAUDIBLE_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_NONAUDIBLE_EN_SHIFT 2
+#define PMIC_RG_VSRAM_OTHERS_RETENTION_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_RETENTION_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_RETENTION_EN_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_VDIFFPFM_OFF_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_VDIFFPFM_OFF_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VDIFFPFM_OFF_SHIFT 4
+#define PMIC_RG_VSRAM_OTHERS_DIGMON_SEL_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_DIGMON_SEL_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_DIGMON_SEL_SHIFT 5
+#define PMIC_RG_VSRAM_OTHERS_OCN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_OCN_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_OCN_SHIFT 8
+#define PMIC_RG_VSRAM_OTHERS_OCP_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RG_VSRAM_OTHERS_OCP_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_OCP_SHIFT 11
+#define PMIC_RGS_VSRAM_OTHERS_OC_STATUS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON2
+#define PMIC_RGS_VSRAM_OTHERS_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VSRAM_OTHERS_OC_STATUS_SHIFT 14
+#define PMIC_RG_VSRAM_OTHERS_RSV1_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON3
+#define PMIC_RG_VSRAM_OTHERS_RSV1_MASK 0xFF
+#define PMIC_RG_VSRAM_OTHERS_RSV1_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_RSV2_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON3
+#define PMIC_RG_VSRAM_OTHERS_RSV2_MASK 0xFF
+#define PMIC_RG_VSRAM_OTHERS_RSV2_SHIFT 8
+#define PMIC_RG_VSRAM_OTHERS_UG_ON_SR_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_UG_ON_SR_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_UG_ON_SR_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_NLIM_GATING_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_NLIM_GATING_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_NLIM_GATING_SHIFT 2
+#define PMIC_RG_VSRAM_OTHERS_NLIM_SRF_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_NLIM_SRF_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_NLIM_SRF_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_POTECT_KEY_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_POTECT_KEY_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_POTECT_KEY_SHIFT 4
+#define PMIC_RG_VSRAM_OTHERS_LXR_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_LXR_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_LXR_EN_SHIFT 6
+#define PMIC_RG_VSRAM_OTHERS_GPIO_OUTPUT_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_GPIO_OUTPUT_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_GPIO_OUTPUT_SHIFT 7
+#define PMIC_RG_VSRAM_OTHERS_PARKB_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_PARKB_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_PARKB_SHIFT 8
+#define PMIC_RG_VSRAM_OTHERS_MOS_TMODE_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_MOS_TMODE_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_MOS_TMODE_SHIFT 11
+#define PMIC_RG_VSRAM_OTHERS_DRV_FORCEFAST_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_DRV_FORCEFAST_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_DRV_FORCEFAST_SHIFT 12
+#define PMIC_RG_VSRAM_OTHERS_PFM_FP_CUTB_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON4
+#define PMIC_RG_VSRAM_OTHERS_PFM_FP_CUTB_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_PFM_FP_CUTB_SHIFT 13
+#define PMIC_RG_VSRAM_OTHERS_VDIFFCAP_EN_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_VDIFFCAP_EN_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VDIFFCAP_EN_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_VBAT_HI_DIS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_VBAT_HI_DIS_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VBAT_HI_DIS_SHIFT 1
+#define PMIC_RG_VSRAM_OTHERS_VBAT_LOW_DIS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_VBAT_LOW_DIS_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VBAT_LOW_DIS_SHIFT 2
+#define PMIC_RG_VSRAM_OTHERS_VOUT_HI_DIS_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_VOUT_HI_DIS_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VOUT_HI_DIS_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_VDIFF_OFF_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_VDIFF_OFF_MASK 0x1
+#define PMIC_RG_VSRAM_OTHERS_VDIFF_OFF_SHIFT 4
+#define PMIC_RG_VSRAM_OTHERS_SLP_RSV_ADDR \
+ MT6389_VSRAM_OTHERS_ANA_CON5
+#define PMIC_RG_VSRAM_OTHERS_SLP_RSV_MASK 0xFF
+#define PMIC_RG_VSRAM_OTHERS_SLP_RSV_SHIFT 5
+#define PMIC_BUCK_ANA1_ELR_LEN_ADDR \
+ MT6389_BUCK_ANA1_ELR_NUM
+#define PMIC_BUCK_ANA1_ELR_LEN_MASK 0xFF
+#define PMIC_BUCK_ANA1_ELR_LEN_SHIFT 0
+#define PMIC_RG_VMODEM_DRIVER_SR_TRIM_ADDR \
+ MT6389_VMODEM_ELR_0
+#define PMIC_RG_VMODEM_DRIVER_SR_TRIM_MASK 0x7
+#define PMIC_RG_VMODEM_DRIVER_SR_TRIM_SHIFT 0
+#define PMIC_RG_VMODEM_CCOMP_ADDR \
+ MT6389_VMODEM_ELR_0
+#define PMIC_RG_VMODEM_CCOMP_MASK 0x3
+#define PMIC_RG_VMODEM_CCOMP_SHIFT 3
+#define PMIC_RG_VMODEM_RCOMP_ADDR \
+ MT6389_VMODEM_ELR_0
+#define PMIC_RG_VMODEM_RCOMP_MASK 0xF
+#define PMIC_RG_VMODEM_RCOMP_SHIFT 5
+#define PMIC_RG_VMODEM_NLIM_TRIM_ADDR \
+ MT6389_VMODEM_ELR_0
+#define PMIC_RG_VMODEM_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VMODEM_NLIM_TRIM_SHIFT 9
+#define PMIC_RG_VMODEM_PWMRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_0
+#define PMIC_RG_VMODEM_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VMODEM_PWMRAMP_SLP_SHIFT 13
+#define PMIC_RG_VMODEM_CSNSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_1
+#define PMIC_RG_VMODEM_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VMODEM_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VMODEM_ZC_TRIM_ADDR \
+ MT6389_VMODEM_ELR_1
+#define PMIC_RG_VMODEM_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VMODEM_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VMODEM_COTRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_1
+#define PMIC_RG_VMODEM_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VMODEM_COTRAMP_SLP_SHIFT 6
+#define PMIC_RG_VMODEM_RCS_ADDR \
+ MT6389_VMODEM_ELR_1
+#define PMIC_RG_VMODEM_RCS_MASK 0x7
+#define PMIC_RG_VMODEM_RCS_SHIFT 9
+#define PMIC_RG_VMODEM_CSPSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_2
+#define PMIC_RG_VMODEM_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VMODEM_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VMODEM_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_3
+#define PMIC_RG_VMODEM_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VMODEM_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VMODEM_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_3
+#define PMIC_RG_VMODEM_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VMODEM_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VS1_CSNSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_4
+#define PMIC_RG_VS1_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VS1_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VS1_RCOMP_ADDR \
+ MT6389_VMODEM_ELR_4
+#define PMIC_RG_VS1_RCOMP_MASK 0xF
+#define PMIC_RG_VS1_RCOMP_SHIFT 4
+#define PMIC_RG_VS1_CCOMP_ADDR \
+ MT6389_VMODEM_ELR_4
+#define PMIC_RG_VS1_CCOMP_MASK 0x3
+#define PMIC_RG_VS1_CCOMP_SHIFT 8
+#define PMIC_RG_VS1_PWMRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_4
+#define PMIC_RG_VS1_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VS1_PWMRAMP_SLP_SHIFT 10
+#define PMIC_RG_VS1_COTRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_4
+#define PMIC_RG_VS1_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VS1_COTRAMP_SLP_SHIFT 13
+#define PMIC_RG_VS1_CSPSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_5
+#define PMIC_RG_VS1_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VS1_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VS1_ZC_TRIM_ADDR \
+ MT6389_VMODEM_ELR_5
+#define PMIC_RG_VS1_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VS1_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VS1_LDO_SENSE_ADDR \
+ MT6389_VMODEM_ELR_5
+#define PMIC_RG_VS1_LDO_SENSE_MASK 0x1
+#define PMIC_RG_VS1_LDO_SENSE_SHIFT 6
+#define PMIC_RG_VS1_NLIM_TRIM_ADDR \
+ MT6389_VMODEM_ELR_5
+#define PMIC_RG_VS1_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VS1_NLIM_TRIM_SHIFT 7
+#define PMIC_RG_VS1_RCS_ADDR \
+ MT6389_VMODEM_ELR_5
+#define PMIC_RG_VS1_RCS_MASK 0x7
+#define PMIC_RG_VS1_RCS_SHIFT 11
+#define PMIC_RG_VS1_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_6
+#define PMIC_RG_VS1_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VS1_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VS1_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_6
+#define PMIC_RG_VS1_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VS1_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VS2_CSNSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_7
+#define PMIC_RG_VS2_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VS2_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VS2_RCOMP_ADDR \
+ MT6389_VMODEM_ELR_7
+#define PMIC_RG_VS2_RCOMP_MASK 0xF
+#define PMIC_RG_VS2_RCOMP_SHIFT 4
+#define PMIC_RG_VS2_CCOMP_ADDR \
+ MT6389_VMODEM_ELR_7
+#define PMIC_RG_VS2_CCOMP_MASK 0x3
+#define PMIC_RG_VS2_CCOMP_SHIFT 8
+#define PMIC_RG_VS2_PWMRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_7
+#define PMIC_RG_VS2_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VS2_PWMRAMP_SLP_SHIFT 10
+#define PMIC_RG_VS2_COTRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_7
+#define PMIC_RG_VS2_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VS2_COTRAMP_SLP_SHIFT 13
+#define PMIC_RG_VS2_CSPSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_8
+#define PMIC_RG_VS2_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VS2_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VS2_ZC_TRIM_ADDR \
+ MT6389_VMODEM_ELR_8
+#define PMIC_RG_VS2_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VS2_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VS2_LDO_SENSE_ADDR \
+ MT6389_VMODEM_ELR_8
+#define PMIC_RG_VS2_LDO_SENSE_MASK 0x1
+#define PMIC_RG_VS2_LDO_SENSE_SHIFT 6
+#define PMIC_RG_VS2_NLIM_TRIM_ADDR \
+ MT6389_VMODEM_ELR_8
+#define PMIC_RG_VS2_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VS2_NLIM_TRIM_SHIFT 7
+#define PMIC_RG_VS2_RCS_ADDR \
+ MT6389_VMODEM_ELR_8
+#define PMIC_RG_VS2_RCS_MASK 0x7
+#define PMIC_RG_VS2_RCS_SHIFT 11
+#define PMIC_RG_VS2_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_9
+#define PMIC_RG_VS2_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VS2_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VS2_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_9
+#define PMIC_RG_VS2_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VS2_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VDRAM1_CSNSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_10
+#define PMIC_RG_VDRAM1_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VDRAM1_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VDRAM1_RCOMP_ADDR \
+ MT6389_VMODEM_ELR_10
+#define PMIC_RG_VDRAM1_RCOMP_MASK 0xF
+#define PMIC_RG_VDRAM1_RCOMP_SHIFT 4
+#define PMIC_RG_VDRAM1_CCOMP_ADDR \
+ MT6389_VMODEM_ELR_10
+#define PMIC_RG_VDRAM1_CCOMP_MASK 0x3
+#define PMIC_RG_VDRAM1_CCOMP_SHIFT 8
+#define PMIC_RG_VDRAM1_PWMRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_10
+#define PMIC_RG_VDRAM1_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VDRAM1_PWMRAMP_SLP_SHIFT 10
+#define PMIC_RG_VDRAM1_COTRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_10
+#define PMIC_RG_VDRAM1_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VDRAM1_COTRAMP_SLP_SHIFT 13
+#define PMIC_RG_VDRAM1_CSPSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_11
+#define PMIC_RG_VDRAM1_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VDRAM1_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VDRAM1_ZC_TRIM_ADDR \
+ MT6389_VMODEM_ELR_11
+#define PMIC_RG_VDRAM1_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VDRAM1_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VDRAM1_LDO_SENSE_ADDR \
+ MT6389_VMODEM_ELR_11
+#define PMIC_RG_VDRAM1_LDO_SENSE_MASK 0x1
+#define PMIC_RG_VDRAM1_LDO_SENSE_SHIFT 6
+#define PMIC_RG_VDRAM1_NLIM_TRIM_ADDR \
+ MT6389_VMODEM_ELR_11
+#define PMIC_RG_VDRAM1_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VDRAM1_NLIM_TRIM_SHIFT 7
+#define PMIC_RG_VDRAM1_RCS_ADDR \
+ MT6389_VMODEM_ELR_11
+#define PMIC_RG_VDRAM1_RCS_MASK 0x7
+#define PMIC_RG_VDRAM1_RCS_SHIFT 11
+#define PMIC_RG_VDRAM1_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_12
+#define PMIC_RG_VDRAM1_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VDRAM1_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VDRAM1_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_12
+#define PMIC_RG_VDRAM1_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VDRAM1_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_DRIVER_SR_TRIM_ADDR \
+ MT6389_VMODEM_ELR_13
+#define PMIC_RG_VSRAM_OTHERS_DRIVER_SR_TRIM_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_DRIVER_SR_TRIM_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_CCOMP_ADDR \
+ MT6389_VMODEM_ELR_13
+#define PMIC_RG_VSRAM_OTHERS_CCOMP_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_CCOMP_SHIFT 3
+#define PMIC_RG_VSRAM_OTHERS_RCOMP_ADDR \
+ MT6389_VMODEM_ELR_13
+#define PMIC_RG_VSRAM_OTHERS_RCOMP_MASK 0xF
+#define PMIC_RG_VSRAM_OTHERS_RCOMP_SHIFT 5
+#define PMIC_RG_VSRAM_OTHERS_NLIM_TRIM_ADDR \
+ MT6389_VMODEM_ELR_13
+#define PMIC_RG_VSRAM_OTHERS_NLIM_TRIM_MASK 0xF
+#define PMIC_RG_VSRAM_OTHERS_NLIM_TRIM_SHIFT 9
+#define PMIC_RG_VSRAM_OTHERS_PWMRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_13
+#define PMIC_RG_VSRAM_OTHERS_PWMRAMP_SLP_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_PWMRAMP_SLP_SHIFT 13
+#define PMIC_RG_VSRAM_OTHERS_CSNSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_14
+#define PMIC_RG_VSRAM_OTHERS_CSNSLP_TRIM_MASK 0xF
+#define PMIC_RG_VSRAM_OTHERS_CSNSLP_TRIM_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_ZC_TRIM_ADDR \
+ MT6389_VMODEM_ELR_14
+#define PMIC_RG_VSRAM_OTHERS_ZC_TRIM_MASK 0x3
+#define PMIC_RG_VSRAM_OTHERS_ZC_TRIM_SHIFT 4
+#define PMIC_RG_VSRAM_OTHERS_COTRAMP_SLP_ADDR \
+ MT6389_VMODEM_ELR_14
+#define PMIC_RG_VSRAM_OTHERS_COTRAMP_SLP_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_COTRAMP_SLP_SHIFT 6
+#define PMIC_RG_VSRAM_OTHERS_RCS_ADDR \
+ MT6389_VMODEM_ELR_14
+#define PMIC_RG_VSRAM_OTHERS_RCS_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_RCS_SHIFT 9
+#define PMIC_RG_VSRAM_OTHERS_CSPSLP_TRIM_ADDR \
+ MT6389_VMODEM_ELR_15
+#define PMIC_RG_VSRAM_OTHERS_CSPSLP_TRIM_MASK 0xF
+#define PMIC_RG_VSRAM_OTHERS_CSPSLP_TRIM_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_16
+#define PMIC_RG_VSRAM_OTHERS_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_PFM_PEAK_TRIM_SHIFT 0
+#define PMIC_RG_VSRAM_OTHERS_SONIC_PFM_PEAK_TRIM_ADDR \
+ MT6389_VMODEM_ELR_16
+#define PMIC_RG_VSRAM_OTHERS_SONIC_PFM_PEAK_TRIM_MASK 0x7
+#define PMIC_RG_VSRAM_OTHERS_SONIC_PFM_PEAK_TRIM_SHIFT 3
+#define PMIC_RG_VS1_RPSI_TRIM_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS1_RPSI_TRIM_MASK 0x7
+#define PMIC_RG_VS1_RPSI_TRIM_SHIFT 0
+#define PMIC_RG_VS1_4R2R_VDIFF_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS1_4R2R_VDIFF_MASK 0x1
+#define PMIC_RG_VS1_4R2R_VDIFF_SHIFT 3
+#define PMIC_RG_VS1_1A_SEL_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS1_1A_SEL_MASK 0x1
+#define PMIC_RG_VS1_1A_SEL_SHIFT 4
+#define PMIC_RG_VS2_RPSI_TRIM_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS2_RPSI_TRIM_MASK 0x7
+#define PMIC_RG_VS2_RPSI_TRIM_SHIFT 5
+#define PMIC_RG_VS2_4R2R_VDIFF_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS2_4R2R_VDIFF_MASK 0x1
+#define PMIC_RG_VS2_4R2R_VDIFF_SHIFT 8
+#define PMIC_RG_VS2_1A_SEL_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VS2_1A_SEL_MASK 0x1
+#define PMIC_RG_VS2_1A_SEL_SHIFT 9
+#define PMIC_RG_VPA_NLIM_SEL_ADDR \
+ MT6389_VMODEM_ELR_17
+#define PMIC_RG_VPA_NLIM_SEL_MASK 0xF
+#define PMIC_RG_VPA_NLIM_SEL_SHIFT 10
+#define PMIC_RG_VDRAM1_RPSI_TRIM_ADDR \
+ MT6389_VMODEM_ELR_18
+#define PMIC_RG_VDRAM1_RPSI_TRIM_MASK 0x7
+#define PMIC_RG_VDRAM1_RPSI_TRIM_SHIFT 0
+#define PMIC_RG_VDRAM1_4R2R_VDIFF_ADDR \
+ MT6389_VMODEM_ELR_18
+#define PMIC_RG_VDRAM1_4R2R_VDIFF_MASK 0x1
+#define PMIC_RG_VDRAM1_4R2R_VDIFF_SHIFT 3
+#define PMIC_RG_VDRAM1_1A_SEL_ADDR \
+ MT6389_VMODEM_ELR_18
+#define PMIC_RG_VDRAM1_1A_SEL_MASK 0x1
+#define PMIC_RG_VDRAM1_1A_SEL_SHIFT 4
+#define PMIC_LDO_TOP_ANA_ID_ADDR \
+ MT6389_LDO_TOP_ID
+#define PMIC_LDO_TOP_ANA_ID_MASK 0xFF
+#define PMIC_LDO_TOP_ANA_ID_SHIFT 0
+#define PMIC_LDO_TOP_DIG_ID_ADDR \
+ MT6389_LDO_TOP_ID
+#define PMIC_LDO_TOP_DIG_ID_MASK 0xFF
+#define PMIC_LDO_TOP_DIG_ID_SHIFT 8
+#define PMIC_LDO_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_TOP_REV0
+#define PMIC_LDO_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_TOP_REV0
+#define PMIC_LDO_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_TOP_REV0
+#define PMIC_LDO_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_TOP_REV0
+#define PMIC_LDO_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_TOP_CBS_ADDR \
+ MT6389_LDO_TOP_DBI
+#define PMIC_LDO_TOP_CBS_MASK 0x3
+#define PMIC_LDO_TOP_CBS_SHIFT 0
+#define PMIC_LDO_TOP_BIX_ADDR \
+ MT6389_LDO_TOP_DBI
+#define PMIC_LDO_TOP_BIX_MASK 0x3
+#define PMIC_LDO_TOP_BIX_SHIFT 2
+#define PMIC_LDO_TOP_ESP_ADDR \
+ MT6389_LDO_TOP_DBI
+#define PMIC_LDO_TOP_ESP_MASK 0xFF
+#define PMIC_LDO_TOP_ESP_SHIFT 8
+#define PMIC_LDO_TOP_FPI_ADDR \
+ MT6389_LDO_TOP_DXI
+#define PMIC_LDO_TOP_FPI_MASK 0xFF
+#define PMIC_LDO_TOP_FPI_SHIFT 0
+#define PMIC_LDO_TOP_CLK_OFFSET_ADDR \
+ MT6389_LDO_TPM0
+#define PMIC_LDO_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_LDO_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_LDO_TOP_RST_OFFSET_ADDR \
+ MT6389_LDO_TPM0
+#define PMIC_LDO_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_LDO_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_LDO_TOP_INT_OFFSET_ADDR \
+ MT6389_LDO_TPM1
+#define PMIC_LDO_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_LDO_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_LDO_TOP_INT_LEN_ADDR \
+ MT6389_LDO_TPM1
+#define PMIC_LDO_TOP_INT_LEN_MASK 0xFF
+#define PMIC_LDO_TOP_INT_LEN_SHIFT 8
+#define PMIC_RG_LDO_32K_CK_PDN_ADDR \
+ MT6389_LDO_TOP_CKPDN_CON0
+#define PMIC_RG_LDO_32K_CK_PDN_MASK 0x1
+#define PMIC_RG_LDO_32K_CK_PDN_SHIFT 0
+#define PMIC_RG_LDO_INTRP_CK_PDN_ADDR \
+ MT6389_LDO_TOP_CKPDN_CON0
+#define PMIC_RG_LDO_INTRP_CK_PDN_MASK 0x1
+#define PMIC_RG_LDO_INTRP_CK_PDN_SHIFT 1
+#define PMIC_RG_LDO_1M_CK_PDN_ADDR \
+ MT6389_LDO_TOP_CKPDN_CON0
+#define PMIC_RG_LDO_1M_CK_PDN_MASK 0x1
+#define PMIC_RG_LDO_1M_CK_PDN_SHIFT 2
+#define PMIC_RG_LDO_26M_CK_PDN_ADDR \
+ MT6389_LDO_TOP_CKPDN_CON0
+#define PMIC_RG_LDO_26M_CK_PDN_MASK 0x1
+#define PMIC_RG_LDO_26M_CK_PDN_SHIFT 3
+#define PMIC_RG_LDO_32K_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_TOP_CKHWEN_CON0
+#define PMIC_RG_LDO_32K_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_LDO_32K_CK_PDN_HWEN_SHIFT 0
+#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_TOP_CKHWEN_CON0
+#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_SHIFT 1
+#define PMIC_RG_LDO_1M_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_TOP_CKHWEN_CON0
+#define PMIC_RG_LDO_1M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_LDO_1M_CK_PDN_HWEN_SHIFT 2
+#define PMIC_RG_LDO_26M_CK_PDN_HWEN_ADDR \
+ MT6389_TOP_TOP_CKHWEN_CON0
+#define PMIC_RG_LDO_26M_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_LDO_26M_CK_PDN_HWEN_SHIFT 3
+#define PMIC_RG_LDO_DCM_MODE_ADDR \
+ MT6389_LDO_TOP_CLK_DCM_CON0
+#define PMIC_RG_LDO_DCM_MODE_MASK 0x1
+#define PMIC_RG_LDO_DCM_MODE_SHIFT 0
+#define PMIC_RG_INT_EN_VFE28_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VFE28_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VFE28_OC_SHIFT 0
+#define PMIC_RG_INT_EN_VRF18_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VRF18_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VRF18_OC_SHIFT 1
+#define PMIC_RG_INT_EN_VRF12_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VRF12_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VRF12_OC_SHIFT 2
+#define PMIC_RG_INT_EN_VGP3_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VGP3_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VGP3_OC_SHIFT 3
+#define PMIC_RG_INT_EN_VCN33_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VCN33_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VCN33_OC_SHIFT 4
+#define PMIC_RG_INT_EN_VCN18_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VCN18_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VCN18_OC_SHIFT 5
+#define PMIC_RG_INT_EN_VA12_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VA12_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VA12_OC_SHIFT 6
+#define PMIC_RG_INT_EN_VA09_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VA09_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VA09_OC_SHIFT 7
+#define PMIC_RG_INT_EN_VAUX18_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VAUX18_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VAUX18_OC_SHIFT 8
+#define PMIC_RG_INT_EN_VAUD28_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VAUD28_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VAUD28_OC_SHIFT 9
+#define PMIC_RG_INT_EN_VIO18_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VIO18_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VIO18_OC_SHIFT 10
+#define PMIC_RG_INT_EN_VIO33_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VIO33_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VIO33_OC_SHIFT 11
+#define PMIC_RG_INT_EN_VGP1_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VGP1_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VGP1_OC_SHIFT 12
+#define PMIC_RG_INT_EN_VGP2_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VGP2_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VGP2_OC_SHIFT 13
+#define PMIC_RG_INT_EN_VSRAM_PROC_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VSRAM_PROC_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VSRAM_PROC_OC_SHIFT 14
+#define PMIC_RG_INT_EN_VDRAM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON0
+#define PMIC_RG_INT_EN_VDRAM2_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VDRAM2_OC_SHIFT 15
+#define PMIC_LDO_INT_CON0_SET_ADDR \
+ MT6389_LDO_TOP_INT_CON0_SET
+#define PMIC_LDO_INT_CON0_SET_MASK 0xFFFF
+#define PMIC_LDO_INT_CON0_SET_SHIFT 0
+#define PMIC_LDO_INT_CON0_CLR_ADDR \
+ MT6389_LDO_TOP_INT_CON0_CLR
+#define PMIC_LDO_INT_CON0_CLR_MASK 0xFFFF
+#define PMIC_LDO_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_VFE28_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VFE28_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VFE28_OC_SHIFT 0
+#define PMIC_RG_INT_MASK_VRF18_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VRF18_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VRF18_OC_SHIFT 1
+#define PMIC_RG_INT_MASK_VRF12_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VRF12_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VRF12_OC_SHIFT 2
+#define PMIC_RG_INT_MASK_VGP3_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VGP3_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VGP3_OC_SHIFT 3
+#define PMIC_RG_INT_MASK_VCN33_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VCN33_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VCN33_OC_SHIFT 4
+#define PMIC_RG_INT_MASK_VCN18_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VCN18_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VCN18_OC_SHIFT 5
+#define PMIC_RG_INT_MASK_VA12_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VA12_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VA12_OC_SHIFT 6
+#define PMIC_RG_INT_MASK_VA09_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VA09_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VA09_OC_SHIFT 7
+#define PMIC_RG_INT_MASK_VAUX18_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VAUX18_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VAUX18_OC_SHIFT 8
+#define PMIC_RG_INT_MASK_VAUD28_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VAUD28_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VAUD28_OC_SHIFT 9
+#define PMIC_RG_INT_MASK_VIO18_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VIO18_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VIO18_OC_SHIFT 10
+#define PMIC_RG_INT_MASK_VIO33_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VIO33_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VIO33_OC_SHIFT 11
+#define PMIC_RG_INT_MASK_VGP1_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VGP1_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VGP1_OC_SHIFT 12
+#define PMIC_RG_INT_MASK_VGP2_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VGP2_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VGP2_OC_SHIFT 13
+#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_SHIFT 14
+#define PMIC_RG_INT_MASK_VDRAM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_VDRAM2_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VDRAM2_OC_SHIFT 15
+#define PMIC_LDO_INT_MASK_CON0_SET_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0_SET
+#define PMIC_LDO_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_LDO_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_LDO_INT_MASK_CON0_CLR_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON0_CLR
+#define PMIC_LDO_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_LDO_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_VFE28_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VFE28_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VFE28_OC_SHIFT 0
+#define PMIC_RG_INT_STATUS_VRF18_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VRF18_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VRF18_OC_SHIFT 1
+#define PMIC_RG_INT_STATUS_VRF12_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VRF12_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VRF12_OC_SHIFT 2
+#define PMIC_RG_INT_STATUS_VGP3_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VGP3_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VGP3_OC_SHIFT 3
+#define PMIC_RG_INT_STATUS_VCN33_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VCN33_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VCN33_OC_SHIFT 4
+#define PMIC_RG_INT_STATUS_VCN18_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VCN18_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VCN18_OC_SHIFT 5
+#define PMIC_RG_INT_STATUS_VA12_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VA12_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VA12_OC_SHIFT 6
+#define PMIC_RG_INT_STATUS_VA09_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VA09_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VA09_OC_SHIFT 7
+#define PMIC_RG_INT_STATUS_VAUX18_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VAUX18_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VAUX18_OC_SHIFT 8
+#define PMIC_RG_INT_STATUS_VAUD28_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VAUD28_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VAUD28_OC_SHIFT 9
+#define PMIC_RG_INT_STATUS_VIO18_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VIO18_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VIO18_OC_SHIFT 10
+#define PMIC_RG_INT_STATUS_VIO33_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VIO33_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VIO33_OC_SHIFT 11
+#define PMIC_RG_INT_STATUS_VGP1_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VGP1_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VGP1_OC_SHIFT 12
+#define PMIC_RG_INT_STATUS_VGP2_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VGP2_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VGP2_OC_SHIFT 13
+#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_SHIFT 14
+#define PMIC_RG_INT_STATUS_VDRAM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_VDRAM2_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VDRAM2_OC_SHIFT 15
+#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_VGP3_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VGP3_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VGP3_OC_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_VA12_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VA12_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VA12_OC_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_VA09_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VA09_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VA09_OC_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_SHIFT 8
+#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_SHIFT 9
+#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_SHIFT 10
+#define PMIC_RG_INT_RAW_STATUS_VIO33_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VIO33_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VIO33_OC_SHIFT 11
+#define PMIC_RG_INT_RAW_STATUS_VGP1_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VGP1_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VGP1_OC_SHIFT 12
+#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_SHIFT 13
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_SHIFT 14
+#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_SHIFT 15
+#define PMIC_RG_INT_EN_VMCH_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VMCH_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VMCH_OC_SHIFT 0
+#define PMIC_RG_INT_EN_VEMC_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VEMC_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VEMC_OC_SHIFT 1
+#define PMIC_RG_INT_EN_VSIM1_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VSIM1_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VSIM1_OC_SHIFT 2
+#define PMIC_RG_INT_EN_VSIM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VSIM2_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VSIM2_OC_SHIFT 3
+#define PMIC_RG_INT_EN_VUSB_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VUSB_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VUSB_OC_SHIFT 4
+#define PMIC_RG_INT_EN_VXO22_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VXO22_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VXO22_OC_SHIFT 5
+#define PMIC_RG_INT_EN_VRFCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VRFCK_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VRFCK_OC_SHIFT 6
+#define PMIC_RG_INT_EN_VBBCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1
+#define PMIC_RG_INT_EN_VBBCK_OC_MASK 0x1
+#define PMIC_RG_INT_EN_VBBCK_OC_SHIFT 7
+#define PMIC_LDO_INT_CON1_SET_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1_SET
+#define PMIC_LDO_INT_CON1_SET_MASK 0xFFFF
+#define PMIC_LDO_INT_CON1_SET_SHIFT 0
+#define PMIC_LDO_INT_CON1_CLR_ADDR \
+ MT6389_LDO_TOP_INT_MASK_CON1_CLR
+#define PMIC_LDO_INT_CON1_CLR_MASK 0xFFFF
+#define PMIC_LDO_INT_CON1_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_VMCH_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VMCH_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VMCH_OC_SHIFT 0
+#define PMIC_RG_INT_MASK_VEMC_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VEMC_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VEMC_OC_SHIFT 1
+#define PMIC_RG_INT_MASK_VSIM1_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VSIM1_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VSIM1_OC_SHIFT 2
+#define PMIC_RG_INT_MASK_VSIM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VSIM2_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VSIM2_OC_SHIFT 3
+#define PMIC_RG_INT_MASK_VUSB_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VUSB_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VUSB_OC_SHIFT 4
+#define PMIC_RG_INT_MASK_VXO22_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VXO22_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VXO22_OC_SHIFT 5
+#define PMIC_RG_INT_MASK_VRFCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VRFCK_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VRFCK_OC_SHIFT 6
+#define PMIC_RG_INT_MASK_VBBCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_CON1
+#define PMIC_RG_INT_MASK_VBBCK_OC_MASK 0x1
+#define PMIC_RG_INT_MASK_VBBCK_OC_SHIFT 7
+#define PMIC_LDO_INT_MASK_CON1_SET_ADDR \
+ MT6389_LDO_TOP_INT_CON1_SET
+#define PMIC_LDO_INT_MASK_CON1_SET_MASK 0xFFFF
+#define PMIC_LDO_INT_MASK_CON1_SET_SHIFT 0
+#define PMIC_LDO_INT_MASK_CON1_CLR_ADDR \
+ MT6389_LDO_TOP_INT_CON1_CLR
+#define PMIC_LDO_INT_MASK_CON1_CLR_MASK 0xFFFF
+#define PMIC_LDO_INT_MASK_CON1_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_VMCH_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VMCH_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VMCH_OC_SHIFT 0
+#define PMIC_RG_INT_STATUS_VEMC_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VEMC_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VEMC_OC_SHIFT 1
+#define PMIC_RG_INT_STATUS_VSIM1_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VSIM1_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VSIM1_OC_SHIFT 2
+#define PMIC_RG_INT_STATUS_VSIM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VSIM2_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VSIM2_OC_SHIFT 3
+#define PMIC_RG_INT_STATUS_VUSB_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VUSB_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VUSB_OC_SHIFT 4
+#define PMIC_RG_INT_STATUS_VXO22_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VXO22_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VXO22_OC_SHIFT 5
+#define PMIC_RG_INT_STATUS_VRFCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VRFCK_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VRFCK_OC_SHIFT 6
+#define PMIC_RG_INT_STATUS_VBBCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_STATUS1
+#define PMIC_RG_INT_STATUS_VBBCK_OC_MASK 0x1
+#define PMIC_RG_INT_STATUS_VBBCK_OC_SHIFT 7
+#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_SHIFT 1
+#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_SHIFT 2
+#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_SHIFT 3
+#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_SHIFT 4
+#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_SHIFT 5
+#define PMIC_RG_INT_RAW_STATUS_VRFCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VRFCK_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VRFCK_OC_SHIFT 6
+#define PMIC_RG_INT_RAW_STATUS_VBBCK_OC_ADDR \
+ MT6389_LDO_TOP_INT_RAW_STATUS1
+#define PMIC_RG_INT_RAW_STATUS_VBBCK_OC_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_VBBCK_OC_SHIFT 7
+#define PMIC_RG_LDO_MON_FLAG_SEL_ADDR \
+ MT6389_LDO_TEST_CON0
+#define PMIC_RG_LDO_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_LDO_MON_FLAG_SEL_SHIFT 0
+#define PMIC_RG_LDO_INT_FLAG_EN_ADDR \
+ MT6389_LDO_TEST_CON0
+#define PMIC_RG_LDO_INT_FLAG_EN_MASK 0x1
+#define PMIC_RG_LDO_INT_FLAG_EN_SHIFT 9
+#define PMIC_RG_LDO_MON_GRP_SEL_ADDR \
+ MT6389_LDO_TEST_CON0
+#define PMIC_RG_LDO_MON_GRP_SEL_MASK 0x1
+#define PMIC_RG_LDO_MON_GRP_SEL_SHIFT 10
+#define PMIC_RG_LDO_L_E_LP_DIS_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_L_E_LP_DIS_MASK 0x1
+#define PMIC_RG_LDO_L_E_LP_DIS_SHIFT 0
+#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_MASK 0x1
+#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_SHIFT 1
+#define PMIC_RG_LDO_LP_PROT_DISABLE_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_LP_PROT_DISABLE_MASK 0x1
+#define PMIC_RG_LDO_LP_PROT_DISABLE_SHIFT 2
+#define PMIC_RG_LDO_SLEEP_CTRL_MODE_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_SLEEP_CTRL_MODE_MASK 0x1
+#define PMIC_RG_LDO_SLEEP_CTRL_MODE_SHIFT 3
+#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_SHIFT 4
+#define PMIC_RG_LDO_EINT_POL_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_EINT_POL_MASK 0x1
+#define PMIC_RG_LDO_EINT_POL_SHIFT 6
+#define PMIC_RG_LDO_IVGENCHK_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_IVGENCHK_MASK 0x1
+#define PMIC_RG_LDO_IVGENCHK_SHIFT 7
+#define PMIC_RG_LDO_TOP_RSV1_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_TOP_RSV1_MASK 0xF
+#define PMIC_RG_LDO_TOP_RSV1_SHIFT 8
+#define PMIC_RG_LDO_TOP_RSV0_ADDR \
+ MT6389_LDO_TOP_CON0
+#define PMIC_RG_LDO_TOP_RSV0_MASK 0xF
+#define PMIC_RG_LDO_TOP_RSV0_SHIFT 12
+#define PMIC_LDO_WRITE_KEY_ADDR \
+ MT6389_LDO_TOP_CON1
+#define PMIC_LDO_WRITE_KEY_MASK 0xFFFF
+#define PMIC_LDO_WRITE_KEY_SHIFT 0
+#define PMIC_RG_VRTC28_EN_ADDR \
+ MT6389_VRTC28_CON
+#define PMIC_RG_VRTC28_EN_MASK 0x1
+#define PMIC_RG_VRTC28_EN_SHIFT 1
+#define PMIC_DA_VRTC28_EN_ADDR \
+ MT6389_VRTC28_CON
+#define PMIC_DA_VRTC28_EN_MASK 0x1
+#define PMIC_DA_VRTC28_EN_SHIFT 15
+#define PMIC_RG_VAUX18_OFF_ACKTIME_SEL_ADDR \
+ MT6389_VAUX18_ACK
+#define PMIC_RG_VAUX18_OFF_ACKTIME_SEL_MASK 0x1
+#define PMIC_RG_VAUX18_OFF_ACKTIME_SEL_SHIFT 0
+#define PMIC_RG_VAUX18_LP_ACKTIME_SEL_ADDR \
+ MT6389_VAUX18_ACK
+#define PMIC_RG_VAUX18_LP_ACKTIME_SEL_MASK 0x1
+#define PMIC_RG_VAUX18_LP_ACKTIME_SEL_SHIFT 1
+#define PMIC_RG_TREF_EN_ADDR \
+ MT6389_TREF_CON
+#define PMIC_RG_TREF_EN_MASK 0x1
+#define PMIC_RG_TREF_EN_SHIFT 1
+#define PMIC_RG_TREF_OFF_ACKTIME_SEL_ADDR \
+ MT6389_TREF_CON
+#define PMIC_RG_TREF_OFF_ACKTIME_SEL_MASK 0x1
+#define PMIC_RG_TREF_OFF_ACKTIME_SEL_SHIFT 8
+#define PMIC_DA_TREF_EN_ADDR \
+ MT6389_TREF_CON
+#define PMIC_DA_TREF_EN_MASK 0x1
+#define PMIC_DA_TREF_EN_SHIFT 15
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_ADDR \
+ MT6389_VOW_DVS_CON
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_MASK 0x1
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_SHIFT 0
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_ADDR \
+ MT6389_VOW_DVS_CON
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_MASK 0x1
+#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_SHIFT 1
+#define PMIC_DA_VDRAM2_VOSEL_ADDR \
+ MT6389_VDRAM2_MON
+#define PMIC_DA_VDRAM2_VOSEL_MASK 0xF
+#define PMIC_DA_VDRAM2_VOSEL_SHIFT 0
+#define PMIC_DA_VDRAM2_VOCAL_ADDR \
+ MT6389_VDRAM2_MON
+#define PMIC_DA_VDRAM2_VOCAL_MASK 0xF
+#define PMIC_DA_VDRAM2_VOCAL_SHIFT 4
+#define PMIC_LDO_TOP_ELR_LEN_ADDR \
+ MT6389_LDO_TOP_ELR_NUM
+#define PMIC_LDO_TOP_ELR_LEN_MASK 0xFF
+#define PMIC_LDO_TOP_ELR_LEN_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_ADDR \
+ MT6389_LDO_TOP_ELR
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_SHIFT 0
+#define PMIC_RG_VDRAM2_VOSEL_0_ADDR \
+ MT6389_LDO_VDRAM2_ELR_0
+#define PMIC_RG_VDRAM2_VOSEL_0_MASK 0xF
+#define PMIC_RG_VDRAM2_VOSEL_0_SHIFT 0
+#define PMIC_RG_VDRAM2_VOCAL_0_ADDR \
+ MT6389_LDO_VDRAM2_ELR_0
+#define PMIC_RG_VDRAM2_VOCAL_0_MASK 0xF
+#define PMIC_RG_VDRAM2_VOCAL_0_SHIFT 8
+#define PMIC_RG_VDRAM2_VOSEL_1_ADDR \
+ MT6389_LDO_VDRAM2_ELR_1
+#define PMIC_RG_VDRAM2_VOSEL_1_MASK 0xF
+#define PMIC_RG_VDRAM2_VOSEL_1_SHIFT 0
+#define PMIC_RG_VDRAM2_VOCAL_1_ADDR \
+ MT6389_LDO_VDRAM2_ELR_1
+#define PMIC_RG_VDRAM2_VOCAL_1_MASK 0xF
+#define PMIC_RG_VDRAM2_VOCAL_1_SHIFT 8
+#define PMIC_LDO_GNR0_ANA_ID_ADDR \
+ MT6389_LDO_GNR0_DSN_ID
+#define PMIC_LDO_GNR0_ANA_ID_MASK 0xFF
+#define PMIC_LDO_GNR0_ANA_ID_SHIFT 0
+#define PMIC_LDO_GNR0_DIG_ID_ADDR \
+ MT6389_LDO_GNR0_DSN_ID
+#define PMIC_LDO_GNR0_DIG_ID_MASK 0xFF
+#define PMIC_LDO_GNR0_DIG_ID_SHIFT 8
+#define PMIC_LDO_GNR0_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_GNR0_DSN_REV0
+#define PMIC_LDO_GNR0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_GNR0_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR0_DSN_REV0
+#define PMIC_LDO_GNR0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_GNR0_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_GNR0_DSN_REV0
+#define PMIC_LDO_GNR0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_GNR0_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR0_DSN_REV0
+#define PMIC_LDO_GNR0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_GNR0_DSN_CBS_ADDR \
+ MT6389_LDO_GNR0_DSN_DBI
+#define PMIC_LDO_GNR0_DSN_CBS_MASK 0x3
+#define PMIC_LDO_GNR0_DSN_CBS_SHIFT 0
+#define PMIC_LDO_GNR0_DSN_BIX_ADDR \
+ MT6389_LDO_GNR0_DSN_DBI
+#define PMIC_LDO_GNR0_DSN_BIX_MASK 0x3
+#define PMIC_LDO_GNR0_DSN_BIX_SHIFT 2
+#define PMIC_LDO_GNR0_DSN_ESP_ADDR \
+ MT6389_LDO_GNR0_DSN_DBI
+#define PMIC_LDO_GNR0_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_GNR0_DSN_ESP_SHIFT 8
+#define PMIC_LDO_GNR0_DSN_FPI_ADDR \
+ MT6389_LDO_GNR0_DSN_DXI
+#define PMIC_LDO_GNR0_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_GNR0_DSN_FPI_SHIFT 0
+#define PMIC_RG_LDO_VFE28_EN_ADDR \
+ MT6389_LDO_VFE28_CON0
+#define PMIC_RG_LDO_VFE28_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_EN_SHIFT 0
+#define PMIC_RG_LDO_VFE28_LP_ADDR \
+ MT6389_LDO_VFE28_CON0
+#define PMIC_RG_LDO_VFE28_LP_MASK 0x1
+#define PMIC_RG_LDO_VFE28_LP_SHIFT 1
+#define PMIC_RG_LDO_VFE28_STBTD_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VFE28_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VFE28_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VFE28_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VFE28_OC_MODE_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VFE28_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VFE28_OC_TSEL_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VFE28_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VFE28_CK_SW_MODE_ADDR \
+ MT6389_LDO_VFE28_CON1
+#define PMIC_RG_LDO_VFE28_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VFE28_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VFE28_B_EN_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_B_EN_MASK 0x1
+#define PMIC_DA_VFE28_B_EN_SHIFT 0
+#define PMIC_DA_VFE28_B_STB_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_B_STB_MASK 0x1
+#define PMIC_DA_VFE28_B_STB_SHIFT 1
+#define PMIC_DA_VFE28_B_LP_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_B_LP_MASK 0x1
+#define PMIC_DA_VFE28_B_LP_SHIFT 2
+#define PMIC_DA_VFE28_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VFE28_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VFE28_OCFB_EN_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_OCFB_EN_MASK 0x1
+#define PMIC_DA_VFE28_OCFB_EN_SHIFT 5
+#define PMIC_DA_VFE28_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VFE28_MON
+#define PMIC_DA_VFE28_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VFE28_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VFE28_HW0_OP_EN_ADDR \
+ MT6389_LDO_VFE28_OP_EN
+#define PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VFE28_HW1_OP_EN_ADDR \
+ MT6389_LDO_VFE28_OP_EN
+#define PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VFE28_HW2_OP_EN_ADDR \
+ MT6389_LDO_VFE28_OP_EN
+#define PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VFE28_HW3_OP_EN_ADDR \
+ MT6389_LDO_VFE28_OP_EN
+#define PMIC_RG_LDO_VFE28_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VFE28_SW_OP_EN_ADDR \
+ MT6389_LDO_VFE28_OP_EN
+#define PMIC_RG_LDO_VFE28_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR \
+ MT6389_LDO_VFE28_OP_EN_SET
+#define PMIC_RG_LDO_VFE28_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR \
+ MT6389_LDO_VFE28_OP_EN_CLR
+#define PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VFE28_OP_CFG
+#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VFE28_OP_CFG
+#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VFE28_OP_CFG
+#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VFE28_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VFE28_OP_CFG
+#define PMIC_RG_LDO_VFE28_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VFE28_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR \
+ MT6389_LDO_VFE28_OP_CFG_SET
+#define PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VFE28_OP_CFG_CLR
+#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRF18_EN_ADDR \
+ MT6389_LDO_VRF18_CON0
+#define PMIC_RG_LDO_VRF18_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_EN_SHIFT 0
+#define PMIC_RG_LDO_VRF18_LP_ADDR \
+ MT6389_LDO_VRF18_CON0
+#define PMIC_RG_LDO_VRF18_LP_MASK 0x1
+#define PMIC_RG_LDO_VRF18_LP_SHIFT 1
+#define PMIC_RG_LDO_VRF18_STBTD_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VRF18_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VRF18_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VRF18_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VRF18_OC_MODE_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRF18_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VRF18_OC_TSEL_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VRF18_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VRF18_CK_SW_MODE_ADDR \
+ MT6389_LDO_VRF18_CON1
+#define PMIC_RG_LDO_VRF18_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRF18_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VRF18_B_EN_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_B_EN_MASK 0x1
+#define PMIC_DA_VRF18_B_EN_SHIFT 0
+#define PMIC_DA_VRF18_B_STB_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_B_STB_MASK 0x1
+#define PMIC_DA_VRF18_B_STB_SHIFT 1
+#define PMIC_DA_VRF18_B_LP_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_B_LP_MASK 0x1
+#define PMIC_DA_VRF18_B_LP_SHIFT 2
+#define PMIC_DA_VRF18_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VRF18_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VRF18_OCFB_EN_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_OCFB_EN_MASK 0x1
+#define PMIC_DA_VRF18_OCFB_EN_SHIFT 5
+#define PMIC_DA_VRF18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRF18_MON
+#define PMIC_DA_VRF18_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VRF18_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VRF18_HW0_OP_EN_ADDR \
+ MT6389_LDO_VRF18_OP_EN
+#define PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VRF18_HW1_OP_EN_ADDR \
+ MT6389_LDO_VRF18_OP_EN
+#define PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VRF18_HW2_OP_EN_ADDR \
+ MT6389_LDO_VRF18_OP_EN
+#define PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VRF18_HW3_OP_EN_ADDR \
+ MT6389_LDO_VRF18_OP_EN
+#define PMIC_RG_LDO_VRF18_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VRF18_SW_OP_EN_ADDR \
+ MT6389_LDO_VRF18_OP_EN
+#define PMIC_RG_LDO_VRF18_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR \
+ MT6389_LDO_VRF18_OP_EN_SET
+#define PMIC_RG_LDO_VRF18_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR \
+ MT6389_LDO_VRF18_OP_EN_CLR
+#define PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VRF18_OP_CFG
+#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VRF18_OP_CFG
+#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VRF18_OP_CFG
+#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VRF18_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VRF18_OP_CFG
+#define PMIC_RG_LDO_VRF18_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF18_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR \
+ MT6389_LDO_VRF18_OP_CFG_SET
+#define PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VRF18_OP_CFG_CLR
+#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRF12_EN_ADDR \
+ MT6389_LDO_VRF12_CON0
+#define PMIC_RG_LDO_VRF12_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_EN_SHIFT 0
+#define PMIC_RG_LDO_VRF12_LP_ADDR \
+ MT6389_LDO_VRF12_CON0
+#define PMIC_RG_LDO_VRF12_LP_MASK 0x1
+#define PMIC_RG_LDO_VRF12_LP_SHIFT 1
+#define PMIC_RG_LDO_VRF12_STBTD_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VRF12_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VRF12_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VRF12_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VRF12_OC_MODE_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRF12_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VRF12_OC_TSEL_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VRF12_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VRF12_CK_SW_MODE_ADDR \
+ MT6389_LDO_VRF12_CON1
+#define PMIC_RG_LDO_VRF12_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRF12_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VRF12_B_EN_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_B_EN_MASK 0x1
+#define PMIC_DA_VRF12_B_EN_SHIFT 0
+#define PMIC_DA_VRF12_B_STB_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_B_STB_MASK 0x1
+#define PMIC_DA_VRF12_B_STB_SHIFT 1
+#define PMIC_DA_VRF12_B_LP_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_B_LP_MASK 0x1
+#define PMIC_DA_VRF12_B_LP_SHIFT 2
+#define PMIC_DA_VRF12_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VRF12_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VRF12_OCFB_EN_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_OCFB_EN_MASK 0x1
+#define PMIC_DA_VRF12_OCFB_EN_SHIFT 5
+#define PMIC_DA_VRF12_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRF12_MON
+#define PMIC_DA_VRF12_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VRF12_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VRF12_HW0_OP_EN_ADDR \
+ MT6389_LDO_VRF12_OP_EN
+#define PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VRF12_HW1_OP_EN_ADDR \
+ MT6389_LDO_VRF12_OP_EN
+#define PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VRF12_HW2_OP_EN_ADDR \
+ MT6389_LDO_VRF12_OP_EN
+#define PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VRF12_HW3_OP_EN_ADDR \
+ MT6389_LDO_VRF12_OP_EN
+#define PMIC_RG_LDO_VRF12_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VRF12_SW_OP_EN_ADDR \
+ MT6389_LDO_VRF12_OP_EN
+#define PMIC_RG_LDO_VRF12_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR \
+ MT6389_LDO_VRF12_OP_EN_SET
+#define PMIC_RG_LDO_VRF12_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR \
+ MT6389_LDO_VRF12_OP_EN_CLR
+#define PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VRF12_OP_CFG
+#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VRF12_OP_CFG
+#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VRF12_OP_CFG
+#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VRF12_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VRF12_OP_CFG
+#define PMIC_RG_LDO_VRF12_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRF12_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR \
+ MT6389_LDO_VRF12_OP_CFG_SET
+#define PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VRF12_OP_CFG_CLR
+#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VGP3_EN_ADDR \
+ MT6389_LDO_VGP3_CON0
+#define PMIC_RG_LDO_VGP3_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP3_LP_ADDR \
+ MT6389_LDO_VGP3_CON0
+#define PMIC_RG_LDO_VGP3_LP_MASK 0x1
+#define PMIC_RG_LDO_VGP3_LP_SHIFT 1
+#define PMIC_RG_LDO_VGP3_STBTD_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VGP3_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VGP3_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP3_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VGP3_OC_MODE_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP3_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VGP3_OC_TSEL_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VGP3_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VGP3_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VGP3_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VGP3_CK_SW_MODE_ADDR \
+ MT6389_LDO_VGP3_CON1
+#define PMIC_RG_LDO_VGP3_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP3_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VGP3_B_EN_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_B_EN_MASK 0x1
+#define PMIC_DA_VGP3_B_EN_SHIFT 0
+#define PMIC_DA_VGP3_B_STB_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_B_STB_MASK 0x1
+#define PMIC_DA_VGP3_B_STB_SHIFT 1
+#define PMIC_DA_VGP3_B_LP_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_B_LP_MASK 0x1
+#define PMIC_DA_VGP3_B_LP_SHIFT 2
+#define PMIC_DA_VGP3_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VGP3_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VGP3_OCFB_EN_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_OCFB_EN_MASK 0x1
+#define PMIC_DA_VGP3_OCFB_EN_SHIFT 5
+#define PMIC_DA_VGP3_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP3_MON
+#define PMIC_DA_VGP3_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VGP3_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VGP3_HW0_OP_EN_ADDR \
+ MT6389_LDO_VGP3_OP_EN
+#define PMIC_RG_LDO_VGP3_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP3_HW1_OP_EN_ADDR \
+ MT6389_LDO_VGP3_OP_EN
+#define PMIC_RG_LDO_VGP3_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VGP3_HW2_OP_EN_ADDR \
+ MT6389_LDO_VGP3_OP_EN
+#define PMIC_RG_LDO_VGP3_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP3_HW3_OP_EN_ADDR \
+ MT6389_LDO_VGP3_OP_EN
+#define PMIC_RG_LDO_VGP3_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VGP3_SW_OP_EN_ADDR \
+ MT6389_LDO_VGP3_OP_EN
+#define PMIC_RG_LDO_VGP3_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP3_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VGP3_OP_EN_SET_ADDR \
+ MT6389_LDO_VGP3_OP_EN_SET
+#define PMIC_RG_LDO_VGP3_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP3_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP3_OP_EN_CLR_ADDR \
+ MT6389_LDO_VGP3_OP_EN_CLR
+#define PMIC_RG_LDO_VGP3_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP3_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VGP3_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VGP3_OP_CFG
+#define PMIC_RG_LDO_VGP3_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VGP3_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VGP3_OP_CFG
+#define PMIC_RG_LDO_VGP3_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VGP3_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VGP3_OP_CFG
+#define PMIC_RG_LDO_VGP3_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VGP3_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VGP3_OP_CFG
+#define PMIC_RG_LDO_VGP3_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP3_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VGP3_OP_CFG_SET_ADDR \
+ MT6389_LDO_VGP3_OP_CFG_SET
+#define PMIC_RG_LDO_VGP3_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP3_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP3_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VGP3_OP_CFG_CLR
+#define PMIC_RG_LDO_VGP3_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP3_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VCN33_EN_0_ADDR \
+ MT6389_LDO_VCN33_CON0
+#define PMIC_RG_LDO_VCN33_EN_0_MASK 0x1
+#define PMIC_RG_LDO_VCN33_EN_0_SHIFT 0
+#define PMIC_RG_LDO_VCN33_LP_ADDR \
+ MT6389_LDO_VCN33_CON0
+#define PMIC_RG_LDO_VCN33_LP_MASK 0x1
+#define PMIC_RG_LDO_VCN33_LP_SHIFT 1
+#define PMIC_RG_LDO_VCN33_STBTD_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VCN33_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VCN33_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VCN33_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VCN33_OC_MODE_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VCN33_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VCN33_OC_TSEL_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VCN33_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VCN33_CK_SW_MODE_ADDR \
+ MT6389_LDO_VCN33_CON1
+#define PMIC_RG_LDO_VCN33_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VCN33_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VCN33_B_EN_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_B_EN_MASK 0x1
+#define PMIC_DA_VCN33_B_EN_SHIFT 0
+#define PMIC_DA_VCN33_B_STB_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_B_STB_MASK 0x1
+#define PMIC_DA_VCN33_B_STB_SHIFT 1
+#define PMIC_DA_VCN33_B_LP_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_B_LP_MASK 0x1
+#define PMIC_DA_VCN33_B_LP_SHIFT 2
+#define PMIC_DA_VCN33_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VCN33_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VCN33_OCFB_EN_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_OCFB_EN_MASK 0x1
+#define PMIC_DA_VCN33_OCFB_EN_SHIFT 5
+#define PMIC_DA_VCN33_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VCN33_MON
+#define PMIC_DA_VCN33_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VCN33_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VCN33_HW0_OP_EN_ADDR \
+ MT6389_LDO_VCN33_OP_EN
+#define PMIC_RG_LDO_VCN33_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VCN33_HW1_OP_EN_ADDR \
+ MT6389_LDO_VCN33_OP_EN
+#define PMIC_RG_LDO_VCN33_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VCN33_HW2_OP_EN_ADDR \
+ MT6389_LDO_VCN33_OP_EN
+#define PMIC_RG_LDO_VCN33_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VCN33_HW3_OP_EN_ADDR \
+ MT6389_LDO_VCN33_OP_EN
+#define PMIC_RG_LDO_VCN33_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VCN33_SW_OP_EN_ADDR \
+ MT6389_LDO_VCN33_OP_EN
+#define PMIC_RG_LDO_VCN33_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN33_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VCN33_OP_EN_SET_ADDR \
+ MT6389_LDO_VCN33_OP_EN_SET
+#define PMIC_RG_LDO_VCN33_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN33_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VCN33_OP_EN_CLR_ADDR \
+ MT6389_LDO_VCN33_OP_EN_CLR
+#define PMIC_RG_LDO_VCN33_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN33_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VCN33_OP_CFG
+#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VCN33_OP_CFG
+#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VCN33_OP_CFG
+#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VCN33_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VCN33_OP_CFG
+#define PMIC_RG_LDO_VCN33_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN33_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VCN33_OP_CFG_SET_ADDR \
+ MT6389_LDO_VCN33_OP_CFG_SET
+#define PMIC_RG_LDO_VCN33_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN33_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VCN33_OP_CFG_CLR
+#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VCN33_EN_1_ADDR \
+ MT6389_LDO_VCN33_MULTI_SW
+#define PMIC_RG_LDO_VCN33_EN_1_MASK 0x1
+#define PMIC_RG_LDO_VCN33_EN_1_SHIFT 15
+#define PMIC_RG_LDO_VCN18_EN_ADDR \
+ MT6389_LDO_VCN18_CON0
+#define PMIC_RG_LDO_VCN18_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_EN_SHIFT 0
+#define PMIC_RG_LDO_VCN18_LP_ADDR \
+ MT6389_LDO_VCN18_CON0
+#define PMIC_RG_LDO_VCN18_LP_MASK 0x1
+#define PMIC_RG_LDO_VCN18_LP_SHIFT 1
+#define PMIC_RG_LDO_VCN18_STBTD_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VCN18_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VCN18_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VCN18_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VCN18_OC_MODE_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VCN18_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VCN18_OC_TSEL_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VCN18_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VCN18_CK_SW_MODE_ADDR \
+ MT6389_LDO_VCN18_CON1
+#define PMIC_RG_LDO_VCN18_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VCN18_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VCN18_B_EN_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_B_EN_MASK 0x1
+#define PMIC_DA_VCN18_B_EN_SHIFT 0
+#define PMIC_DA_VCN18_B_STB_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_B_STB_MASK 0x1
+#define PMIC_DA_VCN18_B_STB_SHIFT 1
+#define PMIC_DA_VCN18_B_LP_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_B_LP_MASK 0x1
+#define PMIC_DA_VCN18_B_LP_SHIFT 2
+#define PMIC_DA_VCN18_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VCN18_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VCN18_OCFB_EN_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_OCFB_EN_MASK 0x1
+#define PMIC_DA_VCN18_OCFB_EN_SHIFT 5
+#define PMIC_DA_VCN18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VCN18_MON
+#define PMIC_DA_VCN18_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VCN18_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VCN18_HW0_OP_EN_ADDR \
+ MT6389_LDO_VCN18_OP_EN
+#define PMIC_RG_LDO_VCN18_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VCN18_HW1_OP_EN_ADDR \
+ MT6389_LDO_VCN18_OP_EN
+#define PMIC_RG_LDO_VCN18_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VCN18_HW2_OP_EN_ADDR \
+ MT6389_LDO_VCN18_OP_EN
+#define PMIC_RG_LDO_VCN18_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VCN18_HW3_OP_EN_ADDR \
+ MT6389_LDO_VCN18_OP_EN
+#define PMIC_RG_LDO_VCN18_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VCN18_SW_OP_EN_ADDR \
+ MT6389_LDO_VCN18_OP_EN
+#define PMIC_RG_LDO_VCN18_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VCN18_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VCN18_OP_EN_SET_ADDR \
+ MT6389_LDO_VCN18_OP_EN_SET
+#define PMIC_RG_LDO_VCN18_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN18_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VCN18_OP_EN_CLR_ADDR \
+ MT6389_LDO_VCN18_OP_EN_CLR
+#define PMIC_RG_LDO_VCN18_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN18_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VCN18_OP_CFG
+#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VCN18_OP_CFG
+#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VCN18_OP_CFG
+#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VCN18_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VCN18_OP_CFG
+#define PMIC_RG_LDO_VCN18_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VCN18_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VCN18_OP_CFG_SET_ADDR \
+ MT6389_LDO_VCN18_OP_CFG_SET
+#define PMIC_RG_LDO_VCN18_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN18_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VCN18_OP_CFG_CLR
+#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_SHIFT 0
+#define PMIC_LDO_GNR1_ANA_ID_ADDR \
+ MT6389_LDO_GNR1_DSN_ID
+#define PMIC_LDO_GNR1_ANA_ID_MASK 0xFF
+#define PMIC_LDO_GNR1_ANA_ID_SHIFT 0
+#define PMIC_LDO_GNR1_DIG_ID_ADDR \
+ MT6389_LDO_GNR1_DSN_ID
+#define PMIC_LDO_GNR1_DIG_ID_MASK 0xFF
+#define PMIC_LDO_GNR1_DIG_ID_SHIFT 8
+#define PMIC_LDO_GNR1_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_GNR1_DSN_REV0
+#define PMIC_LDO_GNR1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_GNR1_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR1_DSN_REV0
+#define PMIC_LDO_GNR1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_GNR1_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_GNR1_DSN_REV0
+#define PMIC_LDO_GNR1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_GNR1_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR1_DSN_REV0
+#define PMIC_LDO_GNR1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_GNR1_DSN_CBS_ADDR \
+ MT6389_LDO_GNR1_DSN_DBI
+#define PMIC_LDO_GNR1_DSN_CBS_MASK 0x3
+#define PMIC_LDO_GNR1_DSN_CBS_SHIFT 0
+#define PMIC_LDO_GNR1_DSN_BIX_ADDR \
+ MT6389_LDO_GNR1_DSN_DBI
+#define PMIC_LDO_GNR1_DSN_BIX_MASK 0x3
+#define PMIC_LDO_GNR1_DSN_BIX_SHIFT 2
+#define PMIC_LDO_GNR1_DSN_ESP_ADDR \
+ MT6389_LDO_GNR1_DSN_DBI
+#define PMIC_LDO_GNR1_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_GNR1_DSN_ESP_SHIFT 8
+#define PMIC_LDO_GNR1_DSN_FPI_ADDR \
+ MT6389_LDO_GNR1_DSN_DXI
+#define PMIC_LDO_GNR1_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_GNR1_DSN_FPI_SHIFT 0
+#define PMIC_RG_LDO_VA12_EN_ADDR \
+ MT6389_LDO_VA12_CON0
+#define PMIC_RG_LDO_VA12_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_EN_SHIFT 0
+#define PMIC_RG_LDO_VA12_LP_ADDR \
+ MT6389_LDO_VA12_CON0
+#define PMIC_RG_LDO_VA12_LP_MASK 0x1
+#define PMIC_RG_LDO_VA12_LP_SHIFT 1
+#define PMIC_RG_LDO_VA12_STBTD_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VA12_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VA12_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VA12_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VA12_OC_MODE_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VA12_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VA12_OC_TSEL_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VA12_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VA12_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VA12_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VA12_CK_SW_MODE_ADDR \
+ MT6389_LDO_VA12_CON1
+#define PMIC_RG_LDO_VA12_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VA12_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VA12_B_EN_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_B_EN_MASK 0x1
+#define PMIC_DA_VA12_B_EN_SHIFT 0
+#define PMIC_DA_VA12_B_STB_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_B_STB_MASK 0x1
+#define PMIC_DA_VA12_B_STB_SHIFT 1
+#define PMIC_DA_VA12_B_LP_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_B_LP_MASK 0x1
+#define PMIC_DA_VA12_B_LP_SHIFT 2
+#define PMIC_DA_VA12_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VA12_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VA12_OCFB_EN_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_OCFB_EN_MASK 0x1
+#define PMIC_DA_VA12_OCFB_EN_SHIFT 5
+#define PMIC_DA_VA12_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VA12_MON
+#define PMIC_DA_VA12_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VA12_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VA12_HW0_OP_EN_ADDR \
+ MT6389_LDO_VA12_OP_EN
+#define PMIC_RG_LDO_VA12_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VA12_HW1_OP_EN_ADDR \
+ MT6389_LDO_VA12_OP_EN
+#define PMIC_RG_LDO_VA12_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VA12_HW2_OP_EN_ADDR \
+ MT6389_LDO_VA12_OP_EN
+#define PMIC_RG_LDO_VA12_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VA12_HW3_OP_EN_ADDR \
+ MT6389_LDO_VA12_OP_EN
+#define PMIC_RG_LDO_VA12_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VA12_SW_OP_EN_ADDR \
+ MT6389_LDO_VA12_OP_EN
+#define PMIC_RG_LDO_VA12_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA12_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VA12_OP_EN_SET_ADDR \
+ MT6389_LDO_VA12_OP_EN_SET
+#define PMIC_RG_LDO_VA12_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VA12_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VA12_OP_EN_CLR_ADDR \
+ MT6389_LDO_VA12_OP_EN_CLR
+#define PMIC_RG_LDO_VA12_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VA12_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VA12_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VA12_OP_CFG
+#define PMIC_RG_LDO_VA12_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VA12_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VA12_OP_CFG
+#define PMIC_RG_LDO_VA12_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VA12_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VA12_OP_CFG
+#define PMIC_RG_LDO_VA12_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VA12_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VA12_OP_CFG
+#define PMIC_RG_LDO_VA12_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA12_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VA12_OP_CFG_SET_ADDR \
+ MT6389_LDO_VA12_OP_CFG_SET
+#define PMIC_RG_LDO_VA12_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VA12_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VA12_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VA12_OP_CFG_CLR
+#define PMIC_RG_LDO_VA12_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VA12_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VA09_EN_ADDR \
+ MT6389_LDO_VA09_CON0
+#define PMIC_RG_LDO_VA09_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_EN_SHIFT 0
+#define PMIC_RG_LDO_VA09_LP_ADDR \
+ MT6389_LDO_VA09_CON0
+#define PMIC_RG_LDO_VA09_LP_MASK 0x1
+#define PMIC_RG_LDO_VA09_LP_SHIFT 1
+#define PMIC_RG_LDO_VA09_STBTD_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VA09_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VA09_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VA09_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VA09_OC_MODE_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VA09_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VA09_OC_TSEL_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VA09_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VA09_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VA09_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VA09_CK_SW_MODE_ADDR \
+ MT6389_LDO_VA09_CON1
+#define PMIC_RG_LDO_VA09_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VA09_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VA09_B_EN_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_B_EN_MASK 0x1
+#define PMIC_DA_VA09_B_EN_SHIFT 0
+#define PMIC_DA_VA09_B_STB_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_B_STB_MASK 0x1
+#define PMIC_DA_VA09_B_STB_SHIFT 1
+#define PMIC_DA_VA09_B_LP_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_B_LP_MASK 0x1
+#define PMIC_DA_VA09_B_LP_SHIFT 2
+#define PMIC_DA_VA09_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VA09_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VA09_OCFB_EN_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_OCFB_EN_MASK 0x1
+#define PMIC_DA_VA09_OCFB_EN_SHIFT 5
+#define PMIC_DA_VA09_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VA09_MON
+#define PMIC_DA_VA09_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VA09_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VA09_HW0_OP_EN_ADDR \
+ MT6389_LDO_VA09_OP_EN
+#define PMIC_RG_LDO_VA09_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VA09_HW1_OP_EN_ADDR \
+ MT6389_LDO_VA09_OP_EN
+#define PMIC_RG_LDO_VA09_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VA09_HW2_OP_EN_ADDR \
+ MT6389_LDO_VA09_OP_EN
+#define PMIC_RG_LDO_VA09_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VA09_HW3_OP_EN_ADDR \
+ MT6389_LDO_VA09_OP_EN
+#define PMIC_RG_LDO_VA09_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VA09_SW_OP_EN_ADDR \
+ MT6389_LDO_VA09_OP_EN
+#define PMIC_RG_LDO_VA09_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VA09_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VA09_OP_EN_SET_ADDR \
+ MT6389_LDO_VA09_OP_EN_SET
+#define PMIC_RG_LDO_VA09_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VA09_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VA09_OP_EN_CLR_ADDR \
+ MT6389_LDO_VA09_OP_EN_CLR
+#define PMIC_RG_LDO_VA09_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VA09_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VA09_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VA09_OP_CFG
+#define PMIC_RG_LDO_VA09_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VA09_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VA09_OP_CFG
+#define PMIC_RG_LDO_VA09_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VA09_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VA09_OP_CFG
+#define PMIC_RG_LDO_VA09_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VA09_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VA09_OP_CFG
+#define PMIC_RG_LDO_VA09_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VA09_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VA09_OP_CFG_SET_ADDR \
+ MT6389_LDO_VA09_OP_CFG_SET
+#define PMIC_RG_LDO_VA09_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VA09_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VA09_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VA09_OP_CFG_CLR
+#define PMIC_RG_LDO_VA09_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VA09_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_EN_ADDR \
+ MT6389_LDO_VAUX18_CON0
+#define PMIC_RG_LDO_VAUX18_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_EN_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_LP_ADDR \
+ MT6389_LDO_VAUX18_CON0
+#define PMIC_RG_LDO_VAUX18_LP_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_LP_SHIFT 1
+#define PMIC_RG_LDO_VAUX18_STBTD_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VAUX18_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VAUX18_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VAUX18_OC_MODE_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VAUX18_OC_TSEL_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_ADDR \
+ MT6389_LDO_VAUX18_CON1
+#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VAUX18_B_EN_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_B_EN_MASK 0x1
+#define PMIC_DA_VAUX18_B_EN_SHIFT 0
+#define PMIC_DA_VAUX18_B_STB_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_B_STB_MASK 0x1
+#define PMIC_DA_VAUX18_B_STB_SHIFT 1
+#define PMIC_DA_VAUX18_B_LP_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_B_LP_MASK 0x1
+#define PMIC_DA_VAUX18_B_LP_SHIFT 2
+#define PMIC_DA_VAUX18_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VAUX18_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VAUX18_OCFB_EN_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_OCFB_EN_MASK 0x1
+#define PMIC_DA_VAUX18_OCFB_EN_SHIFT 5
+#define PMIC_DA_VAUX18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VAUX18_MON
+#define PMIC_DA_VAUX18_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VAUX18_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_ADDR \
+ MT6389_LDO_VAUX18_OP_EN
+#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_ADDR \
+ MT6389_LDO_VAUX18_OP_EN
+#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_ADDR \
+ MT6389_LDO_VAUX18_OP_EN
+#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VAUX18_HW3_OP_EN_ADDR \
+ MT6389_LDO_VAUX18_OP_EN
+#define PMIC_RG_LDO_VAUX18_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VAUX18_SW_OP_EN_ADDR \
+ MT6389_LDO_VAUX18_OP_EN
+#define PMIC_RG_LDO_VAUX18_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VAUX18_OP_EN_SET_ADDR \
+ MT6389_LDO_VAUX18_OP_EN_SET
+#define PMIC_RG_LDO_VAUX18_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUX18_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_ADDR \
+ MT6389_LDO_VAUX18_OP_EN_CLR
+#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG
+#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG
+#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG
+#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VAUX18_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG
+#define PMIC_RG_LDO_VAUX18_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUX18_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG_SET
+#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VAUX18_OP_CFG_CLR
+#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_EN_ADDR \
+ MT6389_LDO_VAUD28_CON0
+#define PMIC_RG_LDO_VAUD28_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_EN_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_LP_ADDR \
+ MT6389_LDO_VAUD28_CON0
+#define PMIC_RG_LDO_VAUD28_LP_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_LP_SHIFT 1
+#define PMIC_RG_LDO_VAUD28_STBTD_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VAUD28_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VAUD28_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VAUD28_OC_MODE_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VAUD28_OC_TSEL_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_ADDR \
+ MT6389_LDO_VAUD28_CON1
+#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VAUD28_B_EN_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_B_EN_MASK 0x1
+#define PMIC_DA_VAUD28_B_EN_SHIFT 0
+#define PMIC_DA_VAUD28_B_STB_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_B_STB_MASK 0x1
+#define PMIC_DA_VAUD28_B_STB_SHIFT 1
+#define PMIC_DA_VAUD28_B_LP_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_B_LP_MASK 0x1
+#define PMIC_DA_VAUD28_B_LP_SHIFT 2
+#define PMIC_DA_VAUD28_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VAUD28_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VAUD28_OCFB_EN_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_OCFB_EN_MASK 0x1
+#define PMIC_DA_VAUD28_OCFB_EN_SHIFT 5
+#define PMIC_DA_VAUD28_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VAUD28_MON
+#define PMIC_DA_VAUD28_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VAUD28_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_ADDR \
+ MT6389_LDO_VAUD28_OP_EN
+#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_ADDR \
+ MT6389_LDO_VAUD28_OP_EN
+#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_ADDR \
+ MT6389_LDO_VAUD28_OP_EN
+#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VAUD28_HW3_OP_EN_ADDR \
+ MT6389_LDO_VAUD28_OP_EN
+#define PMIC_RG_LDO_VAUD28_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VAUD28_SW_OP_EN_ADDR \
+ MT6389_LDO_VAUD28_OP_EN
+#define PMIC_RG_LDO_VAUD28_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VAUD28_OP_EN_SET_ADDR \
+ MT6389_LDO_VAUD28_OP_EN_SET
+#define PMIC_RG_LDO_VAUD28_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUD28_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_ADDR \
+ MT6389_LDO_VAUD28_OP_EN_CLR
+#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG
+#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG
+#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG
+#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VAUD28_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG
+#define PMIC_RG_LDO_VAUD28_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VAUD28_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG_SET
+#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VAUD28_OP_CFG_CLR
+#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VIO18_EN_ADDR \
+ MT6389_LDO_VIO18_CON0
+#define PMIC_RG_LDO_VIO18_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_EN_SHIFT 0
+#define PMIC_RG_LDO_VIO18_LP_ADDR \
+ MT6389_LDO_VIO18_CON0
+#define PMIC_RG_LDO_VIO18_LP_MASK 0x1
+#define PMIC_RG_LDO_VIO18_LP_SHIFT 1
+#define PMIC_RG_LDO_VIO18_STBTD_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VIO18_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VIO18_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VIO18_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VIO18_OC_MODE_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VIO18_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VIO18_OC_TSEL_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VIO18_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VIO18_CK_SW_MODE_ADDR \
+ MT6389_LDO_VIO18_CON1
+#define PMIC_RG_LDO_VIO18_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VIO18_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VIO18_B_EN_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_B_EN_MASK 0x1
+#define PMIC_DA_VIO18_B_EN_SHIFT 0
+#define PMIC_DA_VIO18_B_STB_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_B_STB_MASK 0x1
+#define PMIC_DA_VIO18_B_STB_SHIFT 1
+#define PMIC_DA_VIO18_B_LP_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_B_LP_MASK 0x1
+#define PMIC_DA_VIO18_B_LP_SHIFT 2
+#define PMIC_DA_VIO18_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VIO18_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VIO18_OCFB_EN_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_OCFB_EN_MASK 0x1
+#define PMIC_DA_VIO18_OCFB_EN_SHIFT 5
+#define PMIC_DA_VIO18_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VIO18_MON
+#define PMIC_DA_VIO18_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VIO18_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VIO18_HW0_OP_EN_ADDR \
+ MT6389_LDO_VIO18_OP_EN
+#define PMIC_RG_LDO_VIO18_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VIO18_HW1_OP_EN_ADDR \
+ MT6389_LDO_VIO18_OP_EN
+#define PMIC_RG_LDO_VIO18_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VIO18_HW2_OP_EN_ADDR \
+ MT6389_LDO_VIO18_OP_EN
+#define PMIC_RG_LDO_VIO18_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VIO18_HW3_OP_EN_ADDR \
+ MT6389_LDO_VIO18_OP_EN
+#define PMIC_RG_LDO_VIO18_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VIO18_SW_OP_EN_ADDR \
+ MT6389_LDO_VIO18_OP_EN
+#define PMIC_RG_LDO_VIO18_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO18_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VIO18_OP_EN_SET_ADDR \
+ MT6389_LDO_VIO18_OP_EN_SET
+#define PMIC_RG_LDO_VIO18_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO18_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VIO18_OP_EN_CLR_ADDR \
+ MT6389_LDO_VIO18_OP_EN_CLR
+#define PMIC_RG_LDO_VIO18_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO18_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VIO18_OP_CFG
+#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VIO18_OP_CFG
+#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VIO18_OP_CFG
+#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VIO18_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VIO18_OP_CFG
+#define PMIC_RG_LDO_VIO18_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO18_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VIO18_OP_CFG_SET_ADDR \
+ MT6389_LDO_VIO18_OP_CFG_SET
+#define PMIC_RG_LDO_VIO18_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO18_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VIO18_OP_CFG_CLR
+#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VIO33_EN_ADDR \
+ MT6389_LDO_VIO33_CON0
+#define PMIC_RG_LDO_VIO33_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_EN_SHIFT 0
+#define PMIC_RG_LDO_VIO33_LP_ADDR \
+ MT6389_LDO_VIO33_CON0
+#define PMIC_RG_LDO_VIO33_LP_MASK 0x1
+#define PMIC_RG_LDO_VIO33_LP_SHIFT 1
+#define PMIC_RG_LDO_VIO33_STBTD_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VIO33_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VIO33_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VIO33_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VIO33_OC_MODE_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VIO33_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VIO33_OC_TSEL_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VIO33_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VIO33_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VIO33_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VIO33_CK_SW_MODE_ADDR \
+ MT6389_LDO_VIO33_CON1
+#define PMIC_RG_LDO_VIO33_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VIO33_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VIO33_B_EN_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_B_EN_MASK 0x1
+#define PMIC_DA_VIO33_B_EN_SHIFT 0
+#define PMIC_DA_VIO33_B_STB_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_B_STB_MASK 0x1
+#define PMIC_DA_VIO33_B_STB_SHIFT 1
+#define PMIC_DA_VIO33_B_LP_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_B_LP_MASK 0x1
+#define PMIC_DA_VIO33_B_LP_SHIFT 2
+#define PMIC_DA_VIO33_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VIO33_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VIO33_OCFB_EN_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_OCFB_EN_MASK 0x1
+#define PMIC_DA_VIO33_OCFB_EN_SHIFT 5
+#define PMIC_DA_VIO33_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VIO33_MON
+#define PMIC_DA_VIO33_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VIO33_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VIO33_HW0_OP_EN_ADDR \
+ MT6389_LDO_VIO33_OP_EN
+#define PMIC_RG_LDO_VIO33_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VIO33_HW1_OP_EN_ADDR \
+ MT6389_LDO_VIO33_OP_EN
+#define PMIC_RG_LDO_VIO33_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VIO33_HW2_OP_EN_ADDR \
+ MT6389_LDO_VIO33_OP_EN
+#define PMIC_RG_LDO_VIO33_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VIO33_HW3_OP_EN_ADDR \
+ MT6389_LDO_VIO33_OP_EN
+#define PMIC_RG_LDO_VIO33_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VIO33_SW_OP_EN_ADDR \
+ MT6389_LDO_VIO33_OP_EN
+#define PMIC_RG_LDO_VIO33_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VIO33_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VIO33_OP_EN_SET_ADDR \
+ MT6389_LDO_VIO33_OP_EN_SET
+#define PMIC_RG_LDO_VIO33_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO33_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VIO33_OP_EN_CLR_ADDR \
+ MT6389_LDO_VIO33_OP_EN_CLR
+#define PMIC_RG_LDO_VIO33_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO33_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VIO33_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VIO33_OP_CFG
+#define PMIC_RG_LDO_VIO33_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VIO33_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VIO33_OP_CFG
+#define PMIC_RG_LDO_VIO33_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VIO33_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VIO33_OP_CFG
+#define PMIC_RG_LDO_VIO33_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VIO33_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VIO33_OP_CFG
+#define PMIC_RG_LDO_VIO33_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VIO33_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VIO33_OP_CFG_SET_ADDR \
+ MT6389_LDO_VIO33_OP_CFG_SET
+#define PMIC_RG_LDO_VIO33_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO33_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VIO33_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VIO33_OP_CFG_CLR
+#define PMIC_RG_LDO_VIO33_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VIO33_OP_CFG_CLR_SHIFT 0
+#define PMIC_LDO_GNR2_ANA_ID_ADDR \
+ MT6389_LDO_GNR2_DSN_ID
+#define PMIC_LDO_GNR2_ANA_ID_MASK 0xFF
+#define PMIC_LDO_GNR2_ANA_ID_SHIFT 0
+#define PMIC_LDO_GNR2_DIG_ID_ADDR \
+ MT6389_LDO_GNR2_DSN_ID
+#define PMIC_LDO_GNR2_DIG_ID_MASK 0xFF
+#define PMIC_LDO_GNR2_DIG_ID_SHIFT 8
+#define PMIC_LDO_GNR2_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_GNR2_DSN_REV0
+#define PMIC_LDO_GNR2_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR2_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_GNR2_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR2_DSN_REV0
+#define PMIC_LDO_GNR2_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR2_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_GNR2_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_GNR2_DSN_REV0
+#define PMIC_LDO_GNR2_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR2_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_GNR2_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR2_DSN_REV0
+#define PMIC_LDO_GNR2_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR2_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_GNR2_DSN_CBS_ADDR \
+ MT6389_LDO_GNR2_DSN_DBI
+#define PMIC_LDO_GNR2_DSN_CBS_MASK 0x3
+#define PMIC_LDO_GNR2_DSN_CBS_SHIFT 0
+#define PMIC_LDO_GNR2_DSN_BIX_ADDR \
+ MT6389_LDO_GNR2_DSN_DBI
+#define PMIC_LDO_GNR2_DSN_BIX_MASK 0x3
+#define PMIC_LDO_GNR2_DSN_BIX_SHIFT 2
+#define PMIC_LDO_GNR2_DSN_ESP_ADDR \
+ MT6389_LDO_GNR2_DSN_DBI
+#define PMIC_LDO_GNR2_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_GNR2_DSN_ESP_SHIFT 8
+#define PMIC_LDO_GNR2_DSN_FPI_ADDR \
+ MT6389_LDO_GNR2_DSN_DXI
+#define PMIC_LDO_GNR2_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_GNR2_DSN_FPI_SHIFT 0
+#define PMIC_RG_LDO_VGP1_EN_ADDR \
+ MT6389_LDO_VGP1_CON0
+#define PMIC_RG_LDO_VGP1_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP1_LP_ADDR \
+ MT6389_LDO_VGP1_CON0
+#define PMIC_RG_LDO_VGP1_LP_MASK 0x1
+#define PMIC_RG_LDO_VGP1_LP_SHIFT 1
+#define PMIC_RG_LDO_VGP1_STBTD_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VGP1_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VGP1_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP1_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VGP1_OC_MODE_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP1_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VGP1_OC_TSEL_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VGP1_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VGP1_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VGP1_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VGP1_CK_SW_MODE_ADDR \
+ MT6389_LDO_VGP1_CON1
+#define PMIC_RG_LDO_VGP1_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP1_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VGP1_B_EN_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_B_EN_MASK 0x1
+#define PMIC_DA_VGP1_B_EN_SHIFT 0
+#define PMIC_DA_VGP1_B_STB_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_B_STB_MASK 0x1
+#define PMIC_DA_VGP1_B_STB_SHIFT 1
+#define PMIC_DA_VGP1_B_LP_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_B_LP_MASK 0x1
+#define PMIC_DA_VGP1_B_LP_SHIFT 2
+#define PMIC_DA_VGP1_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VGP1_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VGP1_OCFB_EN_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_OCFB_EN_MASK 0x1
+#define PMIC_DA_VGP1_OCFB_EN_SHIFT 5
+#define PMIC_DA_VGP1_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP1_MON
+#define PMIC_DA_VGP1_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VGP1_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VGP1_HW0_OP_EN_ADDR \
+ MT6389_LDO_VGP1_OP_EN
+#define PMIC_RG_LDO_VGP1_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP1_HW1_OP_EN_ADDR \
+ MT6389_LDO_VGP1_OP_EN
+#define PMIC_RG_LDO_VGP1_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VGP1_HW2_OP_EN_ADDR \
+ MT6389_LDO_VGP1_OP_EN
+#define PMIC_RG_LDO_VGP1_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP1_HW3_OP_EN_ADDR \
+ MT6389_LDO_VGP1_OP_EN
+#define PMIC_RG_LDO_VGP1_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VGP1_SW_OP_EN_ADDR \
+ MT6389_LDO_VGP1_OP_EN
+#define PMIC_RG_LDO_VGP1_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP1_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VGP1_OP_EN_SET_ADDR \
+ MT6389_LDO_VGP1_OP_EN_SET
+#define PMIC_RG_LDO_VGP1_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP1_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP1_OP_EN_CLR_ADDR \
+ MT6389_LDO_VGP1_OP_EN_CLR
+#define PMIC_RG_LDO_VGP1_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP1_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VGP1_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VGP1_OP_CFG
+#define PMIC_RG_LDO_VGP1_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VGP1_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VGP1_OP_CFG
+#define PMIC_RG_LDO_VGP1_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VGP1_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VGP1_OP_CFG
+#define PMIC_RG_LDO_VGP1_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VGP1_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VGP1_OP_CFG
+#define PMIC_RG_LDO_VGP1_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP1_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VGP1_OP_CFG_SET_ADDR \
+ MT6389_LDO_VGP1_OP_CFG_SET
+#define PMIC_RG_LDO_VGP1_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP1_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP1_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VGP1_OP_CFG_CLR
+#define PMIC_RG_LDO_VGP1_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP1_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VGP2_EN_ADDR \
+ MT6389_LDO_VGP2_CON0
+#define PMIC_RG_LDO_VGP2_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP2_LP_ADDR \
+ MT6389_LDO_VGP2_CON0
+#define PMIC_RG_LDO_VGP2_LP_MASK 0x1
+#define PMIC_RG_LDO_VGP2_LP_SHIFT 1
+#define PMIC_RG_LDO_VGP2_STBTD_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VGP2_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VGP2_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP2_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VGP2_OC_MODE_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP2_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VGP2_OC_TSEL_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VGP2_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VGP2_CK_SW_MODE_ADDR \
+ MT6389_LDO_VGP2_CON1
+#define PMIC_RG_LDO_VGP2_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VGP2_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VGP2_B_EN_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_B_EN_MASK 0x1
+#define PMIC_DA_VGP2_B_EN_SHIFT 0
+#define PMIC_DA_VGP2_B_STB_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_B_STB_MASK 0x1
+#define PMIC_DA_VGP2_B_STB_SHIFT 1
+#define PMIC_DA_VGP2_B_LP_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_B_LP_MASK 0x1
+#define PMIC_DA_VGP2_B_LP_SHIFT 2
+#define PMIC_DA_VGP2_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VGP2_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VGP2_OCFB_EN_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_OCFB_EN_MASK 0x1
+#define PMIC_DA_VGP2_OCFB_EN_SHIFT 5
+#define PMIC_DA_VGP2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VGP2_MON
+#define PMIC_DA_VGP2_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VGP2_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VGP2_HW0_OP_EN_ADDR \
+ MT6389_LDO_VGP2_OP_EN
+#define PMIC_RG_LDO_VGP2_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VGP2_HW1_OP_EN_ADDR \
+ MT6389_LDO_VGP2_OP_EN
+#define PMIC_RG_LDO_VGP2_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VGP2_HW2_OP_EN_ADDR \
+ MT6389_LDO_VGP2_OP_EN
+#define PMIC_RG_LDO_VGP2_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VGP2_HW3_OP_EN_ADDR \
+ MT6389_LDO_VGP2_OP_EN
+#define PMIC_RG_LDO_VGP2_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VGP2_SW_OP_EN_ADDR \
+ MT6389_LDO_VGP2_OP_EN
+#define PMIC_RG_LDO_VGP2_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VGP2_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VGP2_OP_EN_SET_ADDR \
+ MT6389_LDO_VGP2_OP_EN_SET
+#define PMIC_RG_LDO_VGP2_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP2_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP2_OP_EN_CLR_ADDR \
+ MT6389_LDO_VGP2_OP_EN_CLR
+#define PMIC_RG_LDO_VGP2_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP2_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VGP2_OP_CFG
+#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VGP2_OP_CFG
+#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VGP2_OP_CFG
+#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VGP2_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VGP2_OP_CFG
+#define PMIC_RG_LDO_VGP2_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VGP2_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VGP2_OP_CFG_SET_ADDR \
+ MT6389_LDO_VGP2_OP_CFG_SET
+#define PMIC_RG_LDO_VGP2_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP2_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VGP2_OP_CFG_CLR
+#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_EN_ADDR \
+ MT6389_LDO_VDRAM2_CON0
+#define PMIC_RG_LDO_VDRAM2_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_EN_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_LP_ADDR \
+ MT6389_LDO_VDRAM2_CON0
+#define PMIC_RG_LDO_VDRAM2_LP_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_LP_SHIFT 1
+#define PMIC_RG_LDO_VDRAM2_STBTD_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VDRAM2_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VDRAM2_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VDRAM2_OC_MODE_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VDRAM2_OC_TSEL_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_ADDR \
+ MT6389_LDO_VDRAM2_CON1
+#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VDRAM2_B_EN_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_B_EN_MASK 0x1
+#define PMIC_DA_VDRAM2_B_EN_SHIFT 0
+#define PMIC_DA_VDRAM2_B_STB_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_B_STB_MASK 0x1
+#define PMIC_DA_VDRAM2_B_STB_SHIFT 1
+#define PMIC_DA_VDRAM2_B_LP_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_B_LP_MASK 0x1
+#define PMIC_DA_VDRAM2_B_LP_SHIFT 2
+#define PMIC_DA_VDRAM2_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VDRAM2_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VDRAM2_OCFB_EN_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_OCFB_EN_MASK 0x1
+#define PMIC_DA_VDRAM2_OCFB_EN_SHIFT 5
+#define PMIC_DA_VDRAM2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VDRAM2_MON
+#define PMIC_DA_VDRAM2_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VDRAM2_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_EN_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN
+#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN_SET
+#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_ADDR \
+ MT6389_LDO_VDRAM2_OP_EN_CLR
+#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VDRAM2_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG_SET
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VDRAM2_OP_CFG_CLR
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VMCH_EN_ADDR \
+ MT6389_LDO_VMCH_CON0
+#define PMIC_RG_LDO_VMCH_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_EN_SHIFT 0
+#define PMIC_RG_LDO_VMCH_LP_ADDR \
+ MT6389_LDO_VMCH_CON0
+#define PMIC_RG_LDO_VMCH_LP_MASK 0x1
+#define PMIC_RG_LDO_VMCH_LP_SHIFT 1
+#define PMIC_RG_LDO_VMCH_STBTD_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VMCH_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VMCH_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VMCH_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VMCH_OC_MODE_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VMCH_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VMCH_OC_TSEL_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VMCH_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VMCH_CK_SW_MODE_ADDR \
+ MT6389_LDO_VMCH_CON1
+#define PMIC_RG_LDO_VMCH_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VMCH_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VMCH_B_EN_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_B_EN_MASK 0x1
+#define PMIC_DA_VMCH_B_EN_SHIFT 0
+#define PMIC_DA_VMCH_B_STB_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_B_STB_MASK 0x1
+#define PMIC_DA_VMCH_B_STB_SHIFT 1
+#define PMIC_DA_VMCH_B_LP_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_B_LP_MASK 0x1
+#define PMIC_DA_VMCH_B_LP_SHIFT 2
+#define PMIC_DA_VMCH_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VMCH_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VMCH_OCFB_EN_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_OCFB_EN_MASK 0x1
+#define PMIC_DA_VMCH_OCFB_EN_SHIFT 5
+#define PMIC_DA_VMCH_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VMCH_MON
+#define PMIC_DA_VMCH_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VMCH_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VMCH_HW0_OP_EN_ADDR \
+ MT6389_LDO_VMCH_OP_EN
+#define PMIC_RG_LDO_VMCH_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VMCH_HW1_OP_EN_ADDR \
+ MT6389_LDO_VMCH_OP_EN
+#define PMIC_RG_LDO_VMCH_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VMCH_HW2_OP_EN_ADDR \
+ MT6389_LDO_VMCH_OP_EN
+#define PMIC_RG_LDO_VMCH_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VMCH_HW3_OP_EN_ADDR \
+ MT6389_LDO_VMCH_OP_EN
+#define PMIC_RG_LDO_VMCH_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VMCH_SW_OP_EN_ADDR \
+ MT6389_LDO_VMCH_OP_EN
+#define PMIC_RG_LDO_VMCH_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VMCH_OP_EN_SET_ADDR \
+ MT6389_LDO_VMCH_OP_EN_SET
+#define PMIC_RG_LDO_VMCH_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VMCH_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VMCH_OP_EN_CLR_ADDR \
+ MT6389_LDO_VMCH_OP_EN_CLR
+#define PMIC_RG_LDO_VMCH_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VMCH_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VMCH_OP_CFG
+#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VMCH_OP_CFG
+#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VMCH_OP_CFG
+#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VMCH_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VMCH_OP_CFG
+#define PMIC_RG_LDO_VMCH_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VMCH_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VMCH_OP_CFG_SET_ADDR \
+ MT6389_LDO_VMCH_OP_CFG_SET
+#define PMIC_RG_LDO_VMCH_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VMCH_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VMCH_OP_CFG_CLR
+#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VMCH_EINT_EN_ADDR \
+ MT6389_LDO_VMCH_EINT
+#define PMIC_RG_LDO_VMCH_EINT_EN_MASK 0x1
+#define PMIC_RG_LDO_VMCH_EINT_EN_SHIFT 0
+#define PMIC_RG_LDO_VEMC_EN_ADDR \
+ MT6389_LDO_VEMC_CON0
+#define PMIC_RG_LDO_VEMC_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_EN_SHIFT 0
+#define PMIC_RG_LDO_VEMC_LP_ADDR \
+ MT6389_LDO_VEMC_CON0
+#define PMIC_RG_LDO_VEMC_LP_MASK 0x1
+#define PMIC_RG_LDO_VEMC_LP_SHIFT 1
+#define PMIC_RG_LDO_VEMC_STBTD_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VEMC_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VEMC_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VEMC_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VEMC_OC_MODE_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VEMC_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VEMC_OC_TSEL_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VEMC_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VEMC_CK_SW_MODE_ADDR \
+ MT6389_LDO_VEMC_CON1
+#define PMIC_RG_LDO_VEMC_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VEMC_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VEMC_B_EN_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_B_EN_MASK 0x1
+#define PMIC_DA_VEMC_B_EN_SHIFT 0
+#define PMIC_DA_VEMC_B_STB_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_B_STB_MASK 0x1
+#define PMIC_DA_VEMC_B_STB_SHIFT 1
+#define PMIC_DA_VEMC_B_LP_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_B_LP_MASK 0x1
+#define PMIC_DA_VEMC_B_LP_SHIFT 2
+#define PMIC_DA_VEMC_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VEMC_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VEMC_OCFB_EN_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_OCFB_EN_MASK 0x1
+#define PMIC_DA_VEMC_OCFB_EN_SHIFT 5
+#define PMIC_DA_VEMC_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VEMC_MON
+#define PMIC_DA_VEMC_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VEMC_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VEMC_HW0_OP_EN_ADDR \
+ MT6389_LDO_VEMC_OP_EN
+#define PMIC_RG_LDO_VEMC_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VEMC_HW1_OP_EN_ADDR \
+ MT6389_LDO_VEMC_OP_EN
+#define PMIC_RG_LDO_VEMC_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VEMC_HW2_OP_EN_ADDR \
+ MT6389_LDO_VEMC_OP_EN
+#define PMIC_RG_LDO_VEMC_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VEMC_HW3_OP_EN_ADDR \
+ MT6389_LDO_VEMC_OP_EN
+#define PMIC_RG_LDO_VEMC_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VEMC_SW_OP_EN_ADDR \
+ MT6389_LDO_VEMC_OP_EN
+#define PMIC_RG_LDO_VEMC_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VEMC_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VEMC_OP_EN_SET_ADDR \
+ MT6389_LDO_VEMC_OP_EN_SET
+#define PMIC_RG_LDO_VEMC_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VEMC_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VEMC_OP_EN_CLR_ADDR \
+ MT6389_LDO_VEMC_OP_EN_CLR
+#define PMIC_RG_LDO_VEMC_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VEMC_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VEMC_OP_CFG
+#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VEMC_OP_CFG
+#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VEMC_OP_CFG
+#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VEMC_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VEMC_OP_CFG
+#define PMIC_RG_LDO_VEMC_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VEMC_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VEMC_OP_CFG_SET_ADDR \
+ MT6389_LDO_VEMC_OP_CFG_SET
+#define PMIC_RG_LDO_VEMC_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VEMC_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VEMC_OP_CFG_CLR
+#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_EN_ADDR \
+ MT6389_LDO_VSIM1_CON0
+#define PMIC_RG_LDO_VSIM1_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_EN_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_LP_ADDR \
+ MT6389_LDO_VSIM1_CON0
+#define PMIC_RG_LDO_VSIM1_LP_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_LP_SHIFT 1
+#define PMIC_RG_LDO_VSIM1_STBTD_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VSIM1_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VSIM1_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VSIM1_OC_MODE_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VSIM1_OC_TSEL_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_ADDR \
+ MT6389_LDO_VSIM1_CON1
+#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VSIM1_B_EN_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_B_EN_MASK 0x1
+#define PMIC_DA_VSIM1_B_EN_SHIFT 0
+#define PMIC_DA_VSIM1_B_STB_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_B_STB_MASK 0x1
+#define PMIC_DA_VSIM1_B_STB_SHIFT 1
+#define PMIC_DA_VSIM1_B_LP_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_B_LP_MASK 0x1
+#define PMIC_DA_VSIM1_B_LP_SHIFT 2
+#define PMIC_DA_VSIM1_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VSIM1_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VSIM1_OCFB_EN_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_OCFB_EN_MASK 0x1
+#define PMIC_DA_VSIM1_OCFB_EN_SHIFT 5
+#define PMIC_DA_VSIM1_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSIM1_MON
+#define PMIC_DA_VSIM1_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VSIM1_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_ADDR \
+ MT6389_LDO_VSIM1_OP_EN
+#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_ADDR \
+ MT6389_LDO_VSIM1_OP_EN
+#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_ADDR \
+ MT6389_LDO_VSIM1_OP_EN
+#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VSIM1_HW3_OP_EN_ADDR \
+ MT6389_LDO_VSIM1_OP_EN
+#define PMIC_RG_LDO_VSIM1_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VSIM1_SW_OP_EN_ADDR \
+ MT6389_LDO_VSIM1_OP_EN
+#define PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR \
+ MT6389_LDO_VSIM1_OP_EN_SET
+#define PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR \
+ MT6389_LDO_VSIM1_OP_EN_CLR
+#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG
+#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG
+#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG
+#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VSIM1_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG
+#define PMIC_RG_LDO_VSIM1_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG_SET
+#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VSIM1_OP_CFG_CLR
+#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSIM1_EINT_EN_ADDR \
+ MT6389_LDO_VSIM1_EINT
+#define PMIC_RG_LDO_VSIM1_EINT_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM1_EINT_EN_SHIFT 0
+#define PMIC_LDO_GNR3_ANA_ID_ADDR \
+ MT6389_LDO_GNR3_DSN_ID
+#define PMIC_LDO_GNR3_ANA_ID_MASK 0xFF
+#define PMIC_LDO_GNR3_ANA_ID_SHIFT 0
+#define PMIC_LDO_GNR3_DIG_ID_ADDR \
+ MT6389_LDO_GNR3_DSN_ID
+#define PMIC_LDO_GNR3_DIG_ID_MASK 0xFF
+#define PMIC_LDO_GNR3_DIG_ID_SHIFT 8
+#define PMIC_LDO_GNR3_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_GNR3_DSN_REV0
+#define PMIC_LDO_GNR3_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR3_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_GNR3_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR3_DSN_REV0
+#define PMIC_LDO_GNR3_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR3_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_GNR3_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_GNR3_DSN_REV0
+#define PMIC_LDO_GNR3_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_GNR3_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_GNR3_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_GNR3_DSN_REV0
+#define PMIC_LDO_GNR3_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_GNR3_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_GNR3_DSN_CBS_ADDR \
+ MT6389_LDO_GNR3_DSN_DBI
+#define PMIC_LDO_GNR3_DSN_CBS_MASK 0x3
+#define PMIC_LDO_GNR3_DSN_CBS_SHIFT 0
+#define PMIC_LDO_GNR3_DSN_BIX_ADDR \
+ MT6389_LDO_GNR3_DSN_DBI
+#define PMIC_LDO_GNR3_DSN_BIX_MASK 0x3
+#define PMIC_LDO_GNR3_DSN_BIX_SHIFT 2
+#define PMIC_LDO_GNR3_DSN_ESP_ADDR \
+ MT6389_LDO_GNR3_DSN_DBI
+#define PMIC_LDO_GNR3_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_GNR3_DSN_ESP_SHIFT 8
+#define PMIC_LDO_GNR3_DSN_FPI_ADDR \
+ MT6389_LDO_GNR3_DSN_DXI
+#define PMIC_LDO_GNR3_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_GNR3_DSN_FPI_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_EN_ADDR \
+ MT6389_LDO_VSIM2_CON0
+#define PMIC_RG_LDO_VSIM2_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_EN_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_LP_ADDR \
+ MT6389_LDO_VSIM2_CON0
+#define PMIC_RG_LDO_VSIM2_LP_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_LP_SHIFT 1
+#define PMIC_RG_LDO_VSIM2_STBTD_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VSIM2_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VSIM2_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VSIM2_OC_MODE_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VSIM2_OC_TSEL_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_ADDR \
+ MT6389_LDO_VSIM2_CON1
+#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VSIM2_B_EN_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_B_EN_MASK 0x1
+#define PMIC_DA_VSIM2_B_EN_SHIFT 0
+#define PMIC_DA_VSIM2_B_STB_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_B_STB_MASK 0x1
+#define PMIC_DA_VSIM2_B_STB_SHIFT 1
+#define PMIC_DA_VSIM2_B_LP_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_B_LP_MASK 0x1
+#define PMIC_DA_VSIM2_B_LP_SHIFT 2
+#define PMIC_DA_VSIM2_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VSIM2_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VSIM2_OCFB_EN_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_OCFB_EN_MASK 0x1
+#define PMIC_DA_VSIM2_OCFB_EN_SHIFT 5
+#define PMIC_DA_VSIM2_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSIM2_MON
+#define PMIC_DA_VSIM2_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VSIM2_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_ADDR \
+ MT6389_LDO_VSIM2_OP_EN
+#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_ADDR \
+ MT6389_LDO_VSIM2_OP_EN
+#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_ADDR \
+ MT6389_LDO_VSIM2_OP_EN
+#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VSIM2_HW3_OP_EN_ADDR \
+ MT6389_LDO_VSIM2_OP_EN
+#define PMIC_RG_LDO_VSIM2_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VSIM2_SW_OP_EN_ADDR \
+ MT6389_LDO_VSIM2_OP_EN
+#define PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR \
+ MT6389_LDO_VSIM2_OP_EN_SET
+#define PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR \
+ MT6389_LDO_VSIM2_OP_EN_CLR
+#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG
+#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG
+#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG
+#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VSIM2_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG
+#define PMIC_RG_LDO_VSIM2_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG_SET
+#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VSIM2_OP_CFG_CLR
+#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSIM2_EINT_EN_ADDR \
+ MT6389_LDO_VSIM2_EINT
+#define PMIC_RG_LDO_VSIM2_EINT_EN_MASK 0x1
+#define PMIC_RG_LDO_VSIM2_EINT_EN_SHIFT 0
+#define PMIC_RG_LDO_VUSB_EN_ADDR \
+ MT6389_LDO_VUSB_CON0
+#define PMIC_RG_LDO_VUSB_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_EN_SHIFT 0
+#define PMIC_RG_LDO_VUSB_LP_ADDR \
+ MT6389_LDO_VUSB_CON0
+#define PMIC_RG_LDO_VUSB_LP_MASK 0x1
+#define PMIC_RG_LDO_VUSB_LP_SHIFT 1
+#define PMIC_RG_LDO_VUSB_STBTD_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VUSB_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VUSB_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VUSB_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VUSB_OC_MODE_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VUSB_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VUSB_OC_TSEL_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VUSB_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VUSB_CK_SW_MODE_ADDR \
+ MT6389_LDO_VUSB_CON1
+#define PMIC_RG_LDO_VUSB_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VUSB_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VUSB_B_EN_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_B_EN_MASK 0x1
+#define PMIC_DA_VUSB_B_EN_SHIFT 0
+#define PMIC_DA_VUSB_B_STB_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_B_STB_MASK 0x1
+#define PMIC_DA_VUSB_B_STB_SHIFT 1
+#define PMIC_DA_VUSB_B_LP_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_B_LP_MASK 0x1
+#define PMIC_DA_VUSB_B_LP_SHIFT 2
+#define PMIC_DA_VUSB_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VUSB_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VUSB_OCFB_EN_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_OCFB_EN_MASK 0x1
+#define PMIC_DA_VUSB_OCFB_EN_SHIFT 5
+#define PMIC_DA_VUSB_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VUSB_MON
+#define PMIC_DA_VUSB_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VUSB_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VUSB_HW0_OP_EN_ADDR \
+ MT6389_LDO_VUSB_OP_EN
+#define PMIC_RG_LDO_VUSB_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VUSB_HW1_OP_EN_ADDR \
+ MT6389_LDO_VUSB_OP_EN
+#define PMIC_RG_LDO_VUSB_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VUSB_HW2_OP_EN_ADDR \
+ MT6389_LDO_VUSB_OP_EN
+#define PMIC_RG_LDO_VUSB_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VUSB_HW3_OP_EN_ADDR \
+ MT6389_LDO_VUSB_OP_EN
+#define PMIC_RG_LDO_VUSB_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VUSB_SW_OP_EN_ADDR \
+ MT6389_LDO_VUSB_OP_EN
+#define PMIC_RG_LDO_VUSB_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VUSB_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VUSB_OP_EN_SET_ADDR \
+ MT6389_LDO_VUSB_OP_EN_SET
+#define PMIC_RG_LDO_VUSB_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VUSB_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VUSB_OP_EN_CLR_ADDR \
+ MT6389_LDO_VUSB_OP_EN_CLR
+#define PMIC_RG_LDO_VUSB_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VUSB_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VUSB_OP_CFG
+#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VUSB_OP_CFG
+#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VUSB_OP_CFG
+#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VUSB_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VUSB_OP_CFG
+#define PMIC_RG_LDO_VUSB_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VUSB_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VUSB_OP_CFG_SET_ADDR \
+ MT6389_LDO_VUSB_OP_CFG_SET
+#define PMIC_RG_LDO_VUSB_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VUSB_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VUSB_OP_CFG_CLR
+#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VXO22_EN_ADDR \
+ MT6389_LDO_VXO22_CON0
+#define PMIC_RG_LDO_VXO22_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_EN_SHIFT 0
+#define PMIC_RG_LDO_VXO22_LP_ADDR \
+ MT6389_LDO_VXO22_CON0
+#define PMIC_RG_LDO_VXO22_LP_MASK 0x1
+#define PMIC_RG_LDO_VXO22_LP_SHIFT 1
+#define PMIC_RG_LDO_VXO22_STBTD_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VXO22_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VXO22_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VXO22_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VXO22_OC_MODE_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VXO22_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VXO22_OC_TSEL_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VXO22_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VXO22_CK_SW_MODE_ADDR \
+ MT6389_LDO_VXO22_CON1
+#define PMIC_RG_LDO_VXO22_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VXO22_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VXO22_B_EN_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_B_EN_MASK 0x1
+#define PMIC_DA_VXO22_B_EN_SHIFT 0
+#define PMIC_DA_VXO22_B_STB_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_B_STB_MASK 0x1
+#define PMIC_DA_VXO22_B_STB_SHIFT 1
+#define PMIC_DA_VXO22_B_LP_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_B_LP_MASK 0x1
+#define PMIC_DA_VXO22_B_LP_SHIFT 2
+#define PMIC_DA_VXO22_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VXO22_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VXO22_OCFB_EN_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_OCFB_EN_MASK 0x1
+#define PMIC_DA_VXO22_OCFB_EN_SHIFT 5
+#define PMIC_DA_VXO22_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VXO22_MON
+#define PMIC_DA_VXO22_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VXO22_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VXO22_HW0_OP_EN_ADDR \
+ MT6389_LDO_VXO22_OP_EN
+#define PMIC_RG_LDO_VXO22_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VXO22_HW1_OP_EN_ADDR \
+ MT6389_LDO_VXO22_OP_EN
+#define PMIC_RG_LDO_VXO22_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VXO22_HW2_OP_EN_ADDR \
+ MT6389_LDO_VXO22_OP_EN
+#define PMIC_RG_LDO_VXO22_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VXO22_HW3_OP_EN_ADDR \
+ MT6389_LDO_VXO22_OP_EN
+#define PMIC_RG_LDO_VXO22_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VXO22_SW_OP_EN_ADDR \
+ MT6389_LDO_VXO22_OP_EN
+#define PMIC_RG_LDO_VXO22_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VXO22_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VXO22_OP_EN_SET_ADDR \
+ MT6389_LDO_VXO22_OP_EN_SET
+#define PMIC_RG_LDO_VXO22_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VXO22_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VXO22_OP_EN_CLR_ADDR \
+ MT6389_LDO_VXO22_OP_EN_CLR
+#define PMIC_RG_LDO_VXO22_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VXO22_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VXO22_OP_CFG
+#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VXO22_OP_CFG
+#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VXO22_OP_CFG
+#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VXO22_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VXO22_OP_CFG
+#define PMIC_RG_LDO_VXO22_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VXO22_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VXO22_OP_CFG_SET_ADDR \
+ MT6389_LDO_VXO22_OP_CFG_SET
+#define PMIC_RG_LDO_VXO22_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VXO22_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VXO22_OP_CFG_CLR
+#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_EN_ADDR \
+ MT6389_LDO_VRFCK_CON0
+#define PMIC_RG_LDO_VRFCK_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_EN_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_LP_ADDR \
+ MT6389_LDO_VRFCK_CON0
+#define PMIC_RG_LDO_VRFCK_LP_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_LP_SHIFT 1
+#define PMIC_RG_LDO_VRFCK_STBTD_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VRFCK_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VRFCK_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VRFCK_OC_MODE_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VRFCK_OC_TSEL_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VRFCK_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VRFCK_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VRFCK_CK_SW_MODE_ADDR \
+ MT6389_LDO_VRFCK_CON1
+#define PMIC_RG_LDO_VRFCK_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VRFCK_B_EN_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_B_EN_MASK 0x1
+#define PMIC_DA_VRFCK_B_EN_SHIFT 0
+#define PMIC_DA_VRFCK_B_STB_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_B_STB_MASK 0x1
+#define PMIC_DA_VRFCK_B_STB_SHIFT 1
+#define PMIC_DA_VRFCK_B_LP_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_B_LP_MASK 0x1
+#define PMIC_DA_VRFCK_B_LP_SHIFT 2
+#define PMIC_DA_VRFCK_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VRFCK_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VRFCK_OCFB_EN_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_OCFB_EN_MASK 0x1
+#define PMIC_DA_VRFCK_OCFB_EN_SHIFT 5
+#define PMIC_DA_VRFCK_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VRFCK_MON
+#define PMIC_DA_VRFCK_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VRFCK_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VRFCK_HW0_OP_EN_ADDR \
+ MT6389_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_HW1_OP_EN_ADDR \
+ MT6389_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VRFCK_HW2_OP_EN_ADDR \
+ MT6389_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VRFCK_HW3_OP_EN_ADDR \
+ MT6389_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VRFCK_SW_OP_EN_ADDR \
+ MT6389_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VRFCK_OP_EN_SET_ADDR \
+ MT6389_LDO_VRFCK_OP_EN_SET
+#define PMIC_RG_LDO_VRFCK_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRFCK_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_OP_EN_CLR_ADDR \
+ MT6389_LDO_VRFCK_OP_EN_CLR
+#define PMIC_RG_LDO_VRFCK_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRFCK_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG
+#define PMIC_RG_LDO_VRFCK_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG
+#define PMIC_RG_LDO_VRFCK_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VRFCK_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG
+#define PMIC_RG_LDO_VRFCK_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VRFCK_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG
+#define PMIC_RG_LDO_VRFCK_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VRFCK_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VRFCK_OP_CFG_SET_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG_SET
+#define PMIC_RG_LDO_VRFCK_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VRFCK_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VRFCK_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VRFCK_OP_CFG_CLR
+#define PMIC_RG_LDO_VRFCK_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VRFCK_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_EN_ADDR \
+ MT6389_LDO_VBBCK_CON0
+#define PMIC_RG_LDO_VBBCK_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_EN_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_LP_ADDR \
+ MT6389_LDO_VBBCK_CON0
+#define PMIC_RG_LDO_VBBCK_LP_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_LP_SHIFT 1
+#define PMIC_RG_LDO_VBBCK_STBTD_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VBBCK_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VBBCK_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VBBCK_OC_MODE_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VBBCK_OC_TSEL_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VBBCK_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VBBCK_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VBBCK_CK_SW_MODE_ADDR \
+ MT6389_LDO_VBBCK_CON1
+#define PMIC_RG_LDO_VBBCK_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VBBCK_B_EN_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_B_EN_MASK 0x1
+#define PMIC_DA_VBBCK_B_EN_SHIFT 0
+#define PMIC_DA_VBBCK_B_STB_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_B_STB_MASK 0x1
+#define PMIC_DA_VBBCK_B_STB_SHIFT 1
+#define PMIC_DA_VBBCK_B_LP_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_B_LP_MASK 0x1
+#define PMIC_DA_VBBCK_B_LP_SHIFT 2
+#define PMIC_DA_VBBCK_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VBBCK_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VBBCK_OCFB_EN_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_OCFB_EN_MASK 0x1
+#define PMIC_DA_VBBCK_OCFB_EN_SHIFT 5
+#define PMIC_DA_VBBCK_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VBBCK_MON
+#define PMIC_DA_VBBCK_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VBBCK_DUMMY_LOAD_SHIFT 6
+#define PMIC_RG_LDO_VBBCK_HW0_OP_EN_ADDR \
+ MT6389_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_HW1_OP_EN_ADDR \
+ MT6389_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VBBCK_HW2_OP_EN_ADDR \
+ MT6389_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VBBCK_HW3_OP_EN_ADDR \
+ MT6389_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VBBCK_SW_OP_EN_ADDR \
+ MT6389_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VBBCK_OP_EN_SET_ADDR \
+ MT6389_LDO_VBBCK_OP_EN_SET
+#define PMIC_RG_LDO_VBBCK_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VBBCK_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_OP_EN_CLR_ADDR \
+ MT6389_LDO_VBBCK_OP_EN_CLR
+#define PMIC_RG_LDO_VBBCK_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VBBCK_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG
+#define PMIC_RG_LDO_VBBCK_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG
+#define PMIC_RG_LDO_VBBCK_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VBBCK_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG
+#define PMIC_RG_LDO_VBBCK_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VBBCK_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG
+#define PMIC_RG_LDO_VBBCK_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VBBCK_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VBBCK_OP_CFG_SET_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG_SET
+#define PMIC_RG_LDO_VBBCK_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VBBCK_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VBBCK_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VBBCK_OP_CFG_CLR
+#define PMIC_RG_LDO_VBBCK_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VBBCK_OP_CFG_CLR_SHIFT 0
+#define PMIC_LDO_VSRAM0_ANA_ID_ADDR \
+ MT6389_LDO_VSRAM0_DSN_ID
+#define PMIC_LDO_VSRAM0_ANA_ID_MASK 0xFF
+#define PMIC_LDO_VSRAM0_ANA_ID_SHIFT 0
+#define PMIC_LDO_VSRAM0_DIG_ID_ADDR \
+ MT6389_LDO_VSRAM0_DSN_ID
+#define PMIC_LDO_VSRAM0_DIG_ID_MASK 0xFF
+#define PMIC_LDO_VSRAM0_DIG_ID_SHIFT 8
+#define PMIC_LDO_VSRAM0_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_VSRAM0_DSN_REV0
+#define PMIC_LDO_VSRAM0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_VSRAM0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_VSRAM0_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_VSRAM0_DSN_REV0
+#define PMIC_LDO_VSRAM0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_VSRAM0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_VSRAM0_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_VSRAM0_DSN_REV0
+#define PMIC_LDO_VSRAM0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_VSRAM0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_VSRAM0_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_VSRAM0_DSN_REV0
+#define PMIC_LDO_VSRAM0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_VSRAM0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_VSRAM0_DSN_CBS_ADDR \
+ MT6389_LDO_VSRAM0_DSN_DBI
+#define PMIC_LDO_VSRAM0_DSN_CBS_MASK 0x3
+#define PMIC_LDO_VSRAM0_DSN_CBS_SHIFT 0
+#define PMIC_LDO_VSRAM0_DSN_BIX_ADDR \
+ MT6389_LDO_VSRAM0_DSN_DBI
+#define PMIC_LDO_VSRAM0_DSN_BIX_MASK 0x3
+#define PMIC_LDO_VSRAM0_DSN_BIX_SHIFT 2
+#define PMIC_LDO_VSRAM0_DSN_ESP_ADDR \
+ MT6389_LDO_VSRAM0_DSN_DBI
+#define PMIC_LDO_VSRAM0_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_VSRAM0_DSN_ESP_SHIFT 8
+#define PMIC_LDO_VSRAM0_DSN_FPI_ADDR \
+ MT6389_LDO_VSRAM0_DSN_DXI
+#define PMIC_LDO_VSRAM0_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_VSRAM0_DSN_FPI_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON0
+#define PMIC_RG_LDO_VSRAM_PROC_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_EN_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_LP_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON0
+#define PMIC_RG_LDO_VSRAM_PROC_LP_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_LP_SHIFT 1
+#define PMIC_RG_LDO_VSRAM_PROC_STBTD_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_STBTD_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_PROC_STBTD_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_LINE_ENHANCE_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_LINE_ENHANCE_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_LINE_ENHANCE_EN_SHIFT 2
+#define PMIC_RG_LDO_VSRAM_PROC_OC_FUNC_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_FUNC_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_FUNC_EN_SHIFT 4
+#define PMIC_RG_LDO_VSRAM_PROC_OC_MODE_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_MODE_SHIFT 5
+#define PMIC_RG_LDO_VSRAM_PROC_OC_TSEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_TSEL_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_OC_TSEL_SHIFT 6
+#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_SHIFT 8
+#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_ADDR \
+ MT6389_LDO_VSRAM_PROC_CON1
+#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_SHIFT 15
+#define PMIC_DA_VSRAM_PROC_B_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_B_EN_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_B_EN_SHIFT 0
+#define PMIC_DA_VSRAM_PROC_B_STB_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_B_STB_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_B_STB_SHIFT 1
+#define PMIC_DA_VSRAM_PROC_B_LP_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_B_LP_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_B_LP_SHIFT 2
+#define PMIC_DA_VSRAM_PROC_LINE_ENHANCE_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_LINE_ENHANCE_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_LINE_ENHANCE_SHIFT 3
+#define PMIC_DA_VSRAM_PROC_OCFB_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_OCFB_EN_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_OCFB_EN_SHIFT 5
+#define PMIC_DA_VSRAM_PROC_DUMMY_LOAD_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_DUMMY_LOAD_MASK 0x3
+#define PMIC_DA_VSRAM_PROC_DUMMY_LOAD_SHIFT 6
+#define PMIC_DA_VSRAM_PROC_VSLEEP_SEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_VSLEEP_SEL_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_VSLEEP_SEL_SHIFT 8
+#define PMIC_DA_VSRAM_PROC_R2R_PDN_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_R2R_PDN_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_R2R_PDN_SHIFT 9
+#define PMIC_DA_VSRAM_PROC_TRACK_NDIS_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_MON
+#define PMIC_DA_VSRAM_PROC_TRACK_NDIS_EN_MASK 0x1
+#define PMIC_DA_VSRAM_PROC_TRACK_NDIS_EN_SHIFT 10
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_ADDR \
+ MT6389_LDO_VSRAM_PROC_VOSEL0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_SHIFT 0
+#define PMIC_LDO_VSRAM_PROC_WDTDBG_VOSEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_VOSEL0
+#define PMIC_LDO_VSRAM_PROC_WDTDBG_VOSEL_MASK 0x7F
+#define PMIC_LDO_VSRAM_PROC_WDTDBG_VOSEL_SHIFT 8
+#define PMIC_DA_VSRAM_PROC_VOSEL_GRAY_ADDR \
+ MT6389_LDO_VSRAM_PROC_VOSEL1
+#define PMIC_DA_VSRAM_PROC_VOSEL_GRAY_MASK 0x7F
+#define PMIC_DA_VSRAM_PROC_VOSEL_GRAY_SHIFT 0
+#define PMIC_DA_VSRAM_PROC_VOSEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_VOSEL1
+#define PMIC_DA_VSRAM_PROC_VOSEL_MASK 0x7F
+#define PMIC_DA_VSRAM_PROC_VOSEL_SHIFT 8
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_ADDR \
+ MT6389_LDO_VSRAM_PROC_SFCHG
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_ADDR \
+ MT6389_LDO_VSRAM_PROC_SFCHG
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_SHIFT 7
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_ADDR \
+ MT6389_LDO_VSRAM_PROC_SFCHG
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_SHIFT 8
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_ADDR \
+ MT6389_LDO_VSRAM_PROC_SFCHG
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_SHIFT 15
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_ADDR \
+ MT6389_LDO_VSRAM_PROC_DVS
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_ADDR \
+ MT6389_LDO_VSRAM_PROC_DVS
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_SHIFT 4
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_ADDR \
+ MT6389_LDO_VSRAM_PROC_DVS
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_SHIFT 6
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_SHIFT 1
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_SHIFT 2
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_EN_SHIFT 3
+#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN
+#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_SHIFT 15
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN_SET
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_EN_CLR
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_SHIFT 1
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_SHIFT 2
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_CFG_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_CFG_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_HW3_OP_CFG_SHIFT 3
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG_SET
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_MASK 0xFFFF
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_ADDR \
+ MT6389_LDO_VSRAM_PROC_OP_CFG_CLR
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_MASK 0xFFFF
+#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_EN_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK0
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_EN_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_EN_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_MODE_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK0
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_MODE_MASK 0x1
+#define PMIC_RG_LDO_VSRAM_PROC_TRACK_MODE_SHIFT 1
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_DELTA_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK1
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_DELTA_MASK 0xF
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_DELTA_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK1
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET_SHIFT 8
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK2
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_ADDR \
+ MT6389_LDO_VSRAM_PROC_TRACK2
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB_SHIFT 8
+#define PMIC_LDO_VSRAM0_ELR_LEN_ADDR \
+ MT6389_LDO_VSRAM0_ELR_NUM
+#define PMIC_LDO_VSRAM0_ELR_LEN_MASK 0xFF
+#define PMIC_LDO_VSRAM0_ELR_LEN_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_ELR_0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_MASK 0x7F
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SHIFT 0
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LIMIT_SEL_ADDR \
+ MT6389_LDO_VSRAM_PROC_ELR_1
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LIMIT_SEL_MASK 0x3
+#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_LIMIT_SEL_SHIFT 0
+#define PMIC_LDO_ANA0_ANA_ID_ADDR \
+ MT6389_LDO_ANA0_DSN_ID
+#define PMIC_LDO_ANA0_ANA_ID_MASK 0xFF
+#define PMIC_LDO_ANA0_ANA_ID_SHIFT 0
+#define PMIC_LDO_ANA0_DIG_ID_ADDR \
+ MT6389_LDO_ANA0_DSN_ID
+#define PMIC_LDO_ANA0_DIG_ID_MASK 0xFF
+#define PMIC_LDO_ANA0_DIG_ID_SHIFT 8
+#define PMIC_LDO_ANA0_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_ANA0_DSN_REV0
+#define PMIC_LDO_ANA0_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA0_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_ANA0_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA0_DSN_REV0
+#define PMIC_LDO_ANA0_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA0_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_ANA0_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_ANA0_DSN_REV0
+#define PMIC_LDO_ANA0_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA0_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_ANA0_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA0_DSN_REV0
+#define PMIC_LDO_ANA0_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA0_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_ANA0_DSN_CBS_ADDR \
+ MT6389_LDO_ANA0_DSN_DBI
+#define PMIC_LDO_ANA0_DSN_CBS_MASK 0x3
+#define PMIC_LDO_ANA0_DSN_CBS_SHIFT 0
+#define PMIC_LDO_ANA0_DSN_BIX_ADDR \
+ MT6389_LDO_ANA0_DSN_DBI
+#define PMIC_LDO_ANA0_DSN_BIX_MASK 0x3
+#define PMIC_LDO_ANA0_DSN_BIX_SHIFT 2
+#define PMIC_LDO_ANA0_DSN_ESP_ADDR \
+ MT6389_LDO_ANA0_DSN_DBI
+#define PMIC_LDO_ANA0_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_ANA0_DSN_ESP_SHIFT 8
+#define PMIC_LDO_ANA0_DSN_FPI_ADDR \
+ MT6389_LDO_ANA0_DSN_FPI
+#define PMIC_LDO_ANA0_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_ANA0_DSN_FPI_SHIFT 0
+#define PMIC_RG_VFE28_VOCAL_ADDR \
+ MT6389_VFE28_ANA_CON0
+#define PMIC_RG_VFE28_VOCAL_MASK 0xF
+#define PMIC_RG_VFE28_VOCAL_SHIFT 0
+#define PMIC_RG_VFE28_VOSEL_ADDR \
+ MT6389_VFE28_ANA_CON0
+#define PMIC_RG_VFE28_VOSEL_MASK 0xF
+#define PMIC_RG_VFE28_VOSEL_SHIFT 8
+#define PMIC_RG_VFE28_NDIS_EN_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_NDIS_EN_MASK 0x1
+#define PMIC_RG_VFE28_NDIS_EN_SHIFT 0
+#define PMIC_RG_VFE28_STB_SEL_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_STB_SEL_MASK 0x1
+#define PMIC_RG_VFE28_STB_SEL_SHIFT 1
+#define PMIC_RG_VFE28_RSV_1_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_RSV_1_MASK 0x1
+#define PMIC_RG_VFE28_RSV_1_SHIFT 2
+#define PMIC_RG_VFE28_OC_LP_EN_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VFE28_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VFE28_MEASURE_FT_EN_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VFE28_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VFE28_OC_STATUS_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RGS_VFE28_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VFE28_OC_STATUS_SHIFT 5
+#define PMIC_RG_VFE28_OC_LEVEL_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VFE28_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VFE28_OC_TRIM_ADDR \
+ MT6389_VFE28_ANA_CON1
+#define PMIC_RG_VFE28_OC_TRIM_MASK 0x7
+#define PMIC_RG_VFE28_OC_TRIM_SHIFT 8
+#define PMIC_RG_VAUX18_VOCAL_ADDR \
+ MT6389_VAUX18_ANA_CON0
+#define PMIC_RG_VAUX18_VOCAL_MASK 0xF
+#define PMIC_RG_VAUX18_VOCAL_SHIFT 0
+#define PMIC_RG_VAUX18_VOSEL_ADDR \
+ MT6389_VAUX18_ANA_CON0
+#define PMIC_RG_VAUX18_VOSEL_MASK 0xF
+#define PMIC_RG_VAUX18_VOSEL_SHIFT 8
+#define PMIC_RG_VAUX18_NDIS_EN_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RG_VAUX18_NDIS_EN_MASK 0x1
+#define PMIC_RG_VAUX18_NDIS_EN_SHIFT 0
+#define PMIC_RG_VAUX18_RSV_1_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RG_VAUX18_RSV_1_MASK 0x1
+#define PMIC_RG_VAUX18_RSV_1_SHIFT 1
+#define PMIC_RG_VAUX18_OC_LP_EN_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RG_VAUX18_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VAUX18_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VAUX18_MEASURE_FT_EN_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RG_VAUX18_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VAUX18_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VAUX18_OC_STATUS_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RGS_VAUX18_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VAUX18_OC_STATUS_SHIFT 4
+#define PMIC_RG_VAUX18_OC_TRIM_ADDR \
+ MT6389_VAUX18_ANA_CON1
+#define PMIC_RG_VAUX18_OC_TRIM_MASK 0x7
+#define PMIC_RG_VAUX18_OC_TRIM_SHIFT 5
+#define PMIC_RG_VAUD28_VOCAL_ADDR \
+ MT6389_VAUD28_ANA_CON0
+#define PMIC_RG_VAUD28_VOCAL_MASK 0xF
+#define PMIC_RG_VAUD28_VOCAL_SHIFT 0
+#define PMIC_RG_VAUD28_VOSEL_ADDR \
+ MT6389_VAUD28_ANA_CON0
+#define PMIC_RG_VAUD28_VOSEL_MASK 0xF
+#define PMIC_RG_VAUD28_VOSEL_SHIFT 8
+#define PMIC_RG_VAUD28_NDIS_EN_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RG_VAUD28_NDIS_EN_MASK 0x1
+#define PMIC_RG_VAUD28_NDIS_EN_SHIFT 0
+#define PMIC_RG_VAUD28_RSV_1_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RG_VAUD28_RSV_1_MASK 0x1
+#define PMIC_RG_VAUD28_RSV_1_SHIFT 1
+#define PMIC_RG_VAUD28_OC_LP_EN_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RG_VAUD28_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VAUD28_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VAUD28_MEASURE_FT_EN_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RG_VAUD28_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VAUD28_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VAUD28_OC_STATUS_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RGS_VAUD28_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VAUD28_OC_STATUS_SHIFT 4
+#define PMIC_RG_VAUD28_OC_TRIM_ADDR \
+ MT6389_VAUD28_ANA_CON1
+#define PMIC_RG_VAUD28_OC_TRIM_MASK 0x7
+#define PMIC_RG_VAUD28_OC_TRIM_SHIFT 5
+#define PMIC_RG_VUSB_VOCAL_ADDR \
+ MT6389_VUSB_ANA_CON0
+#define PMIC_RG_VUSB_VOCAL_MASK 0xF
+#define PMIC_RG_VUSB_VOCAL_SHIFT 0
+#define PMIC_RG_VUSB_VOSEL_ADDR \
+ MT6389_VUSB_ANA_CON0
+#define PMIC_RG_VUSB_VOSEL_MASK 0xF
+#define PMIC_RG_VUSB_VOSEL_SHIFT 8
+#define PMIC_RG_VUSB_NDIS_EN_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RG_VUSB_NDIS_EN_MASK 0x1
+#define PMIC_RG_VUSB_NDIS_EN_SHIFT 0
+#define PMIC_RG_VUSB_RSV_1_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RG_VUSB_RSV_1_MASK 0x1
+#define PMIC_RG_VUSB_RSV_1_SHIFT 1
+#define PMIC_RG_VUSB_OC_LP_EN_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RG_VUSB_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VUSB_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VUSB_MEASURE_FT_EN_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RG_VUSB_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VUSB_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VUSB_OC_STATUS_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RGS_VUSB_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VUSB_OC_STATUS_SHIFT 4
+#define PMIC_RG_VUSB_OC_TRIM_ADDR \
+ MT6389_VUSB_ANA_CON1
+#define PMIC_RG_VUSB_OC_TRIM_MASK 0x7
+#define PMIC_RG_VUSB_OC_TRIM_SHIFT 5
+#define PMIC_RG_VCN33_VOCAL_ADDR \
+ MT6389_VCN33_ANA_CON0
+#define PMIC_RG_VCN33_VOCAL_MASK 0xF
+#define PMIC_RG_VCN33_VOCAL_SHIFT 0
+#define PMIC_RG_VCN33_VOSEL_ADDR \
+ MT6389_VCN33_ANA_CON0
+#define PMIC_RG_VCN33_VOSEL_MASK 0xF
+#define PMIC_RG_VCN33_VOSEL_SHIFT 8
+#define PMIC_RG_VCN33_NDIS_EN_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_NDIS_EN_MASK 0x1
+#define PMIC_RG_VCN33_NDIS_EN_SHIFT 0
+#define PMIC_RG_VCN33_STB_SEL_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_STB_SEL_MASK 0x1
+#define PMIC_RG_VCN33_STB_SEL_SHIFT 1
+#define PMIC_RG_VCN33_RSV_1_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_RSV_1_MASK 0x1
+#define PMIC_RG_VCN33_RSV_1_SHIFT 2
+#define PMIC_RG_VCN33_OC_LP_EN_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VCN33_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VCN33_MEASURE_FT_EN_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VCN33_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VCN33_OC_STATUS_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RGS_VCN33_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VCN33_OC_STATUS_SHIFT 5
+#define PMIC_RG_VCN33_OC_LEVEL_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VCN33_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VCN33_OC_TRIM_ADDR \
+ MT6389_VCN33_ANA_CON1
+#define PMIC_RG_VCN33_OC_TRIM_MASK 0x7
+#define PMIC_RG_VCN33_OC_TRIM_SHIFT 8
+#define PMIC_RG_VEMC_VOCAL_ADDR \
+ MT6389_VEMC_ANA_CON0
+#define PMIC_RG_VEMC_VOCAL_MASK 0xF
+#define PMIC_RG_VEMC_VOCAL_SHIFT 0
+#define PMIC_RG_VEMC_VOSEL_ADDR \
+ MT6389_VEMC_ANA_CON0
+#define PMIC_RG_VEMC_VOSEL_MASK 0xF
+#define PMIC_RG_VEMC_VOSEL_SHIFT 8
+#define PMIC_RG_VEMC_NDIS_EN_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RG_VEMC_NDIS_EN_MASK 0x1
+#define PMIC_RG_VEMC_NDIS_EN_SHIFT 0
+#define PMIC_RG_VEMC_RSV_1_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RG_VEMC_RSV_1_MASK 0x1
+#define PMIC_RG_VEMC_RSV_1_SHIFT 1
+#define PMIC_RG_VEMC_OC_LP_EN_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RG_VEMC_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VEMC_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VEMC_MEASURE_FT_EN_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RG_VEMC_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VEMC_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VEMC_OC_STATUS_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RGS_VEMC_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VEMC_OC_STATUS_SHIFT 4
+#define PMIC_RG_VEMC_OC_TRIM_ADDR \
+ MT6389_VEMC_ANA_CON1
+#define PMIC_RG_VEMC_OC_TRIM_MASK 0x7
+#define PMIC_RG_VEMC_OC_TRIM_SHIFT 5
+#define PMIC_RG_VSIM1_VOCAL_ADDR \
+ MT6389_VSIM1_ANA_CON0
+#define PMIC_RG_VSIM1_VOCAL_MASK 0xF
+#define PMIC_RG_VSIM1_VOCAL_SHIFT 0
+#define PMIC_RG_VSIM1_VOSEL_ADDR \
+ MT6389_VSIM1_ANA_CON0
+#define PMIC_RG_VSIM1_VOSEL_MASK 0xF
+#define PMIC_RG_VSIM1_VOSEL_SHIFT 8
+#define PMIC_RG_VSIM1_NDIS_EN_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_NDIS_EN_MASK 0x1
+#define PMIC_RG_VSIM1_NDIS_EN_SHIFT 0
+#define PMIC_RG_VSIM1_STB_SEL_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_STB_SEL_MASK 0x1
+#define PMIC_RG_VSIM1_STB_SEL_SHIFT 1
+#define PMIC_RG_VSIM1_RSV_1_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_RSV_1_MASK 0x1
+#define PMIC_RG_VSIM1_RSV_1_SHIFT 2
+#define PMIC_RG_VSIM1_OC_LP_EN_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VSIM1_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VSIM1_MEASURE_FT_EN_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VSIM1_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VSIM1_OC_STATUS_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RGS_VSIM1_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VSIM1_OC_STATUS_SHIFT 5
+#define PMIC_RG_VSIM1_OC_LEVEL_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VSIM1_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VSIM1_OC_TRIM_ADDR \
+ MT6389_VSIM1_ANA_CON1
+#define PMIC_RG_VSIM1_OC_TRIM_MASK 0x7
+#define PMIC_RG_VSIM1_OC_TRIM_SHIFT 8
+#define PMIC_RG_VSIM2_VOCAL_ADDR \
+ MT6389_VSIM2_ANA_CON0
+#define PMIC_RG_VSIM2_VOCAL_MASK 0xF
+#define PMIC_RG_VSIM2_VOCAL_SHIFT 0
+#define PMIC_RG_VSIM2_VOSEL_ADDR \
+ MT6389_VSIM2_ANA_CON0
+#define PMIC_RG_VSIM2_VOSEL_MASK 0xF
+#define PMIC_RG_VSIM2_VOSEL_SHIFT 8
+#define PMIC_RG_VSIM2_NDIS_EN_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_NDIS_EN_MASK 0x1
+#define PMIC_RG_VSIM2_NDIS_EN_SHIFT 0
+#define PMIC_RG_VSIM2_STB_SEL_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_STB_SEL_MASK 0x1
+#define PMIC_RG_VSIM2_STB_SEL_SHIFT 1
+#define PMIC_RG_VSIM2_RSV_1_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_RSV_1_MASK 0x1
+#define PMIC_RG_VSIM2_RSV_1_SHIFT 2
+#define PMIC_RG_VSIM2_OC_LP_EN_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VSIM2_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VSIM2_MEASURE_FT_EN_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VSIM2_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VSIM2_OC_STATUS_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RGS_VSIM2_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VSIM2_OC_STATUS_SHIFT 5
+#define PMIC_RG_VSIM2_OC_LEVEL_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VSIM2_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VSIM2_OC_TRIM_ADDR \
+ MT6389_VSIM2_ANA_CON1
+#define PMIC_RG_VSIM2_OC_TRIM_MASK 0x7
+#define PMIC_RG_VSIM2_OC_TRIM_SHIFT 8
+#define PMIC_RG_VMCH_VOCAL_ADDR \
+ MT6389_VMCH_ANA_CON0
+#define PMIC_RG_VMCH_VOCAL_MASK 0xF
+#define PMIC_RG_VMCH_VOCAL_SHIFT 0
+#define PMIC_RG_VMCH_VOSEL_ADDR \
+ MT6389_VMCH_ANA_CON0
+#define PMIC_RG_VMCH_VOSEL_MASK 0xF
+#define PMIC_RG_VMCH_VOSEL_SHIFT 8
+#define PMIC_RG_VMCH_NDIS_EN_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_NDIS_EN_MASK 0x1
+#define PMIC_RG_VMCH_NDIS_EN_SHIFT 0
+#define PMIC_RG_VMCH_STB_SEL_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_STB_SEL_MASK 0x1
+#define PMIC_RG_VMCH_STB_SEL_SHIFT 1
+#define PMIC_RG_VMCH_RSV_1_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_RSV_1_MASK 0x1
+#define PMIC_RG_VMCH_RSV_1_SHIFT 2
+#define PMIC_RG_VMCH_OC_LP_EN_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VMCH_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VMCH_MEASURE_FT_EN_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VMCH_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VMCH_OC_STATUS_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RGS_VMCH_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VMCH_OC_STATUS_SHIFT 5
+#define PMIC_RG_VMCH_OC_TRIM_ADDR \
+ MT6389_VMCH_ANA_CON1
+#define PMIC_RG_VMCH_OC_TRIM_MASK 0x7
+#define PMIC_RG_VMCH_OC_TRIM_SHIFT 6
+#define PMIC_RG_VIO33_VOCAL_ADDR \
+ MT6389_VIO33_ANA_CON0
+#define PMIC_RG_VIO33_VOCAL_MASK 0xF
+#define PMIC_RG_VIO33_VOCAL_SHIFT 0
+#define PMIC_RG_VIO33_VOSEL_ADDR \
+ MT6389_VIO33_ANA_CON0
+#define PMIC_RG_VIO33_VOSEL_MASK 0xF
+#define PMIC_RG_VIO33_VOSEL_SHIFT 8
+#define PMIC_RG_VIO33_NDIS_EN_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RG_VIO33_NDIS_EN_MASK 0x1
+#define PMIC_RG_VIO33_NDIS_EN_SHIFT 0
+#define PMIC_RG_VIO33_RSV_1_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RG_VIO33_RSV_1_MASK 0x1
+#define PMIC_RG_VIO33_RSV_1_SHIFT 1
+#define PMIC_RG_VIO33_OC_LP_EN_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RG_VIO33_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VIO33_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VIO33_MEASURE_FT_EN_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RG_VIO33_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VIO33_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VIO33_OC_STATUS_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RGS_VIO33_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VIO33_OC_STATUS_SHIFT 4
+#define PMIC_RG_VIO33_OC_TRIM_ADDR \
+ MT6389_VIO33_ANA_CON1
+#define PMIC_RG_VIO33_OC_TRIM_MASK 0x7
+#define PMIC_RG_VIO33_OC_TRIM_SHIFT 5
+#define PMIC_RG_VGP1_VOCAL_ADDR \
+ MT6389_VGP1_ANA_CON0
+#define PMIC_RG_VGP1_VOCAL_MASK 0xF
+#define PMIC_RG_VGP1_VOCAL_SHIFT 0
+#define PMIC_RG_VGP1_VOSEL_ADDR \
+ MT6389_VGP1_ANA_CON0
+#define PMIC_RG_VGP1_VOSEL_MASK 0xF
+#define PMIC_RG_VGP1_VOSEL_SHIFT 8
+#define PMIC_RG_VGP1_NDIS_EN_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_NDIS_EN_MASK 0x1
+#define PMIC_RG_VGP1_NDIS_EN_SHIFT 0
+#define PMIC_RG_VGP1_STB_SEL_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_STB_SEL_MASK 0x1
+#define PMIC_RG_VGP1_STB_SEL_SHIFT 1
+#define PMIC_RG_VGP1_RSV_1_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_RSV_1_MASK 0x1
+#define PMIC_RG_VGP1_RSV_1_SHIFT 2
+#define PMIC_RG_VGP1_OC_LP_EN_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VGP1_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VGP1_MEASURE_FT_EN_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VGP1_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VGP1_OC_STATUS_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RGS_VGP1_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VGP1_OC_STATUS_SHIFT 5
+#define PMIC_RG_VGP1_OC_LEVEL_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VGP1_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VGP1_OC_TRIM_ADDR \
+ MT6389_VGP1_ANA_CON1
+#define PMIC_RG_VGP1_OC_TRIM_MASK 0x7
+#define PMIC_RG_VGP1_OC_TRIM_SHIFT 8
+#define PMIC_RG_VGP2_VOCAL_ADDR \
+ MT6389_VGP2_ANA_CON0
+#define PMIC_RG_VGP2_VOCAL_MASK 0xF
+#define PMIC_RG_VGP2_VOCAL_SHIFT 0
+#define PMIC_RG_VGP2_VOSEL_ADDR \
+ MT6389_VGP2_ANA_CON0
+#define PMIC_RG_VGP2_VOSEL_MASK 0xF
+#define PMIC_RG_VGP2_VOSEL_SHIFT 8
+#define PMIC_RG_VGP2_NDIS_EN_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_NDIS_EN_MASK 0x1
+#define PMIC_RG_VGP2_NDIS_EN_SHIFT 0
+#define PMIC_RG_VGP2_STB_SEL_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_STB_SEL_MASK 0x1
+#define PMIC_RG_VGP2_STB_SEL_SHIFT 1
+#define PMIC_RG_VGP2_RSV_1_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_RSV_1_MASK 0x1
+#define PMIC_RG_VGP2_RSV_1_SHIFT 2
+#define PMIC_RG_VGP2_OC_LP_EN_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VGP2_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VGP2_MEASURE_FT_EN_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VGP2_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VGP2_OC_STATUS_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RGS_VGP2_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VGP2_OC_STATUS_SHIFT 5
+#define PMIC_RG_VGP2_OC_LEVEL_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VGP2_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VGP2_OC_TRIM_ADDR \
+ MT6389_VGP2_ANA_CON1
+#define PMIC_RG_VGP2_OC_TRIM_MASK 0x7
+#define PMIC_RG_VGP2_OC_TRIM_SHIFT 8
+#define PMIC_RG_ADLDO_RSV_ADDR \
+ MT6389_ADLDO_ANA_CON0
+#define PMIC_RG_ADLDO_RSV_MASK 0x3F
+#define PMIC_RG_ADLDO_RSV_SHIFT 0
+#define PMIC_LDO_ANA0_ELR_LEN_ADDR \
+ MT6389_LDO_ANA0_ELR_NUM
+#define PMIC_LDO_ANA0_ELR_LEN_MASK 0xFF
+#define PMIC_LDO_ANA0_ELR_LEN_SHIFT 0
+#define PMIC_RG_VFE28_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VFE28_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VFE28_VO_F_TRIM_SHIFT 0
+#define PMIC_RG_VFE28_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VFE28_VOTRIM_MASK 0xF
+#define PMIC_RG_VFE28_VOTRIM_SHIFT 1
+#define PMIC_RG_VAUX18_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VAUX18_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VAUX18_VO_F_TRIM_SHIFT 5
+#define PMIC_RG_VAUX18_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VAUX18_VOTRIM_MASK 0xF
+#define PMIC_RG_VAUX18_VOTRIM_SHIFT 6
+#define PMIC_RG_VAUX18_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VAUX18_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VAUX18_OC_LEVEL_SHIFT 10
+#define PMIC_RG_VAUX18_STB_SEL_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VAUX18_STB_SEL_MASK 0x1
+#define PMIC_RG_VAUX18_STB_SEL_SHIFT 12
+#define PMIC_RG_VAUD28_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_0
+#define PMIC_RG_VAUD28_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VAUD28_VO_F_TRIM_SHIFT 13
+#define PMIC_RG_VAUD28_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VAUD28_VOTRIM_MASK 0xF
+#define PMIC_RG_VAUD28_VOTRIM_SHIFT 0
+#define PMIC_RG_VAUD28_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VAUD28_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VAUD28_OC_LEVEL_SHIFT 4
+#define PMIC_RG_VAUD28_STB_SEL_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VAUD28_STB_SEL_MASK 0x1
+#define PMIC_RG_VAUD28_STB_SEL_SHIFT 6
+#define PMIC_RG_VUSB_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VUSB_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VUSB_VO_F_TRIM_SHIFT 7
+#define PMIC_RG_VUSB_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VUSB_VOTRIM_MASK 0xF
+#define PMIC_RG_VUSB_VOTRIM_SHIFT 8
+#define PMIC_RG_VUSB_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VUSB_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VUSB_OC_LEVEL_SHIFT 12
+#define PMIC_RG_VUSB_STB_SEL_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VUSB_STB_SEL_MASK 0x1
+#define PMIC_RG_VUSB_STB_SEL_SHIFT 14
+#define PMIC_RG_VCN33_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_1
+#define PMIC_RG_VCN33_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VCN33_VO_F_TRIM_SHIFT 15
+#define PMIC_RG_VCN33_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VCN33_VOTRIM_MASK 0xF
+#define PMIC_RG_VCN33_VOTRIM_SHIFT 0
+#define PMIC_RG_VEMC_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VEMC_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VEMC_VO_F_TRIM_SHIFT 4
+#define PMIC_RG_VEMC_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VEMC_VOTRIM_MASK 0xF
+#define PMIC_RG_VEMC_VOTRIM_SHIFT 5
+#define PMIC_RG_VEMC_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VEMC_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VEMC_OC_LEVEL_SHIFT 9
+#define PMIC_RG_VEMC_STB_SEL_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VEMC_STB_SEL_MASK 0x1
+#define PMIC_RG_VEMC_STB_SEL_SHIFT 11
+#define PMIC_RG_VSIM1_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_2
+#define PMIC_RG_VSIM1_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VSIM1_VO_F_TRIM_SHIFT 12
+#define PMIC_RG_VSIM1_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VSIM1_VOTRIM_MASK 0xF
+#define PMIC_RG_VSIM1_VOTRIM_SHIFT 0
+#define PMIC_RG_VSIM2_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VSIM2_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VSIM2_VO_F_TRIM_SHIFT 4
+#define PMIC_RG_VSIM2_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VSIM2_VOTRIM_MASK 0xF
+#define PMIC_RG_VSIM2_VOTRIM_SHIFT 5
+#define PMIC_RG_VMCH_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VMCH_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VMCH_VO_F_TRIM_SHIFT 9
+#define PMIC_RG_VMCH_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VMCH_VOTRIM_MASK 0xF
+#define PMIC_RG_VMCH_VOTRIM_SHIFT 10
+#define PMIC_RG_VMCH_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_3
+#define PMIC_RG_VMCH_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VMCH_OC_LEVEL_SHIFT 14
+#define PMIC_RG_VIO33_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VIO33_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VIO33_VO_F_TRIM_SHIFT 0
+#define PMIC_RG_VIO33_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VIO33_VOTRIM_MASK 0xF
+#define PMIC_RG_VIO33_VOTRIM_SHIFT 1
+#define PMIC_RG_VIO33_OC_LEVEL_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VIO33_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VIO33_OC_LEVEL_SHIFT 5
+#define PMIC_RG_VIO33_STB_SEL_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VIO33_STB_SEL_MASK 0x1
+#define PMIC_RG_VIO33_STB_SEL_SHIFT 7
+#define PMIC_RG_VGP1_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VGP1_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VGP1_VO_F_TRIM_SHIFT 8
+#define PMIC_RG_VGP1_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VGP1_VOTRIM_MASK 0xF
+#define PMIC_RG_VGP1_VOTRIM_SHIFT 9
+#define PMIC_RG_VGP2_VO_F_TRIM_ADDR \
+ MT6389_VFE28_ELR_4
+#define PMIC_RG_VGP2_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VGP2_VO_F_TRIM_SHIFT 13
+#define PMIC_RG_VGP2_VOTRIM_ADDR \
+ MT6389_VFE28_ELR_5
+#define PMIC_RG_VGP2_VOTRIM_MASK 0xF
+#define PMIC_RG_VGP2_VOTRIM_SHIFT 0
+#define PMIC_RG_VRTC28_BIAS_SEL_ADDR \
+ MT6389_VFE28_ELR_5
+#define PMIC_RG_VRTC28_BIAS_SEL_MASK 0x1
+#define PMIC_RG_VRTC28_BIAS_SEL_SHIFT 4
+#define PMIC_RG_VRTC28_NDIS_EN_ADDR \
+ MT6389_VFE28_ELR_5
+#define PMIC_RG_VRTC28_NDIS_EN_MASK 0x1
+#define PMIC_RG_VRTC28_NDIS_EN_SHIFT 5
+#define PMIC_LDO_ANA1_ANA_ID_ADDR \
+ MT6389_LDO_ANA1_DSN_ID
+#define PMIC_LDO_ANA1_ANA_ID_MASK 0xFF
+#define PMIC_LDO_ANA1_ANA_ID_SHIFT 0
+#define PMIC_LDO_ANA1_DIG_ID_ADDR \
+ MT6389_LDO_ANA1_DSN_ID
+#define PMIC_LDO_ANA1_DIG_ID_MASK 0xFF
+#define PMIC_LDO_ANA1_DIG_ID_SHIFT 8
+#define PMIC_LDO_ANA1_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_ANA1_DSN_REV0
+#define PMIC_LDO_ANA1_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA1_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_ANA1_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA1_DSN_REV0
+#define PMIC_LDO_ANA1_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA1_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_ANA1_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_ANA1_DSN_REV0
+#define PMIC_LDO_ANA1_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA1_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_ANA1_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA1_DSN_REV0
+#define PMIC_LDO_ANA1_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA1_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_ANA1_DSN_CBS_ADDR \
+ MT6389_LDO_ANA1_DSN_DBI
+#define PMIC_LDO_ANA1_DSN_CBS_MASK 0x3
+#define PMIC_LDO_ANA1_DSN_CBS_SHIFT 0
+#define PMIC_LDO_ANA1_DSN_BIX_ADDR \
+ MT6389_LDO_ANA1_DSN_DBI
+#define PMIC_LDO_ANA1_DSN_BIX_MASK 0x3
+#define PMIC_LDO_ANA1_DSN_BIX_SHIFT 2
+#define PMIC_LDO_ANA1_DSN_ESP_ADDR \
+ MT6389_LDO_ANA1_DSN_DBI
+#define PMIC_LDO_ANA1_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_ANA1_DSN_ESP_SHIFT 8
+#define PMIC_LDO_ANA1_DSN_FPI_ADDR \
+ MT6389_LDO_ANA1_DSN_FPI
+#define PMIC_LDO_ANA1_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_ANA1_DSN_FPI_SHIFT 0
+#define PMIC_RG_VRF18_VOCAL_ADDR \
+ MT6389_VRF18_ANA_CON0
+#define PMIC_RG_VRF18_VOCAL_MASK 0xF
+#define PMIC_RG_VRF18_VOCAL_SHIFT 0
+#define PMIC_RG_VRF18_VOSEL_ADDR \
+ MT6389_VRF18_ANA_CON0
+#define PMIC_RG_VRF18_VOSEL_MASK 0xF
+#define PMIC_RG_VRF18_VOSEL_SHIFT 8
+#define PMIC_RG_VRF18_NDIS_EN_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_NDIS_EN_MASK 0x1
+#define PMIC_RG_VRF18_NDIS_EN_SHIFT 0
+#define PMIC_RG_VRF18_STB_SEL_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_STB_SEL_MASK 0x1
+#define PMIC_RG_VRF18_STB_SEL_SHIFT 1
+#define PMIC_RG_VRF18_RSV_1_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_RSV_1_MASK 0x1
+#define PMIC_RG_VRF18_RSV_1_SHIFT 2
+#define PMIC_RG_VRF18_OC_LP_EN_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VRF18_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VRF18_MEASURE_FT_EN_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VRF18_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VRF18_OC_STATUS_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RGS_VRF18_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VRF18_OC_STATUS_SHIFT 5
+#define PMIC_RG_VRF18_OC_LEVEL_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VRF18_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VRF18_OC_TRIM_ADDR \
+ MT6389_VRF18_ANA_CON1
+#define PMIC_RG_VRF18_OC_TRIM_MASK 0x7
+#define PMIC_RG_VRF18_OC_TRIM_SHIFT 8
+#define PMIC_RG_VGP3_VOCAL_ADDR \
+ MT6389_VGP3_ANA_CON0
+#define PMIC_RG_VGP3_VOCAL_MASK 0xF
+#define PMIC_RG_VGP3_VOCAL_SHIFT 0
+#define PMIC_RG_VGP3_VOSEL_ADDR \
+ MT6389_VGP3_ANA_CON0
+#define PMIC_RG_VGP3_VOSEL_MASK 0xF
+#define PMIC_RG_VGP3_VOSEL_SHIFT 8
+#define PMIC_RG_VGP3_NDIS_EN_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_NDIS_EN_MASK 0x1
+#define PMIC_RG_VGP3_NDIS_EN_SHIFT 0
+#define PMIC_RG_VGP3_STB_SEL_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_STB_SEL_MASK 0x1
+#define PMIC_RG_VGP3_STB_SEL_SHIFT 1
+#define PMIC_RG_VGP3_RSV_1_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_RSV_1_MASK 0x1
+#define PMIC_RG_VGP3_RSV_1_SHIFT 2
+#define PMIC_RG_VGP3_OC_LP_EN_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VGP3_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VGP3_MEASURE_FT_EN_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VGP3_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VGP3_OC_STATUS_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RGS_VGP3_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VGP3_OC_STATUS_SHIFT 5
+#define PMIC_RG_VGP3_OC_LEVEL_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VGP3_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VGP3_OC_TRIM_ADDR \
+ MT6389_VGP3_ANA_CON1
+#define PMIC_RG_VGP3_OC_TRIM_MASK 0x7
+#define PMIC_RG_VGP3_OC_TRIM_SHIFT 8
+#define PMIC_RG_VCN18_VOCAL_ADDR \
+ MT6389_VCN18_ANA_CON0
+#define PMIC_RG_VCN18_VOCAL_MASK 0xF
+#define PMIC_RG_VCN18_VOCAL_SHIFT 0
+#define PMIC_RG_VCN18_VOSEL_ADDR \
+ MT6389_VCN18_ANA_CON0
+#define PMIC_RG_VCN18_VOSEL_MASK 0xF
+#define PMIC_RG_VCN18_VOSEL_SHIFT 8
+#define PMIC_RG_VCN18_NDIS_EN_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_NDIS_EN_MASK 0x1
+#define PMIC_RG_VCN18_NDIS_EN_SHIFT 0
+#define PMIC_RG_VCN18_STB_SEL_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_STB_SEL_MASK 0x1
+#define PMIC_RG_VCN18_STB_SEL_SHIFT 1
+#define PMIC_RG_VCN18_RSV_1_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_RSV_1_MASK 0x1
+#define PMIC_RG_VCN18_RSV_1_SHIFT 2
+#define PMIC_RG_VCN18_OC_LP_EN_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VCN18_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VCN18_MEASURE_FT_EN_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VCN18_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VCN18_OC_STATUS_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RGS_VCN18_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VCN18_OC_STATUS_SHIFT 5
+#define PMIC_RG_VCN18_OC_LEVEL_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VCN18_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VCN18_OC_TRIM_ADDR \
+ MT6389_VCN18_ANA_CON1
+#define PMIC_RG_VCN18_OC_TRIM_MASK 0x7
+#define PMIC_RG_VCN18_OC_TRIM_SHIFT 8
+#define PMIC_RG_VIO18_VOCAL_ADDR \
+ MT6389_VIO18_ANA_CON0
+#define PMIC_RG_VIO18_VOCAL_MASK 0xF
+#define PMIC_RG_VIO18_VOCAL_SHIFT 0
+#define PMIC_RG_VIO18_VOSEL_ADDR \
+ MT6389_VIO18_ANA_CON0
+#define PMIC_RG_VIO18_VOSEL_MASK 0xF
+#define PMIC_RG_VIO18_VOSEL_SHIFT 8
+#define PMIC_RG_VIO18_NDIS_EN_ADDR \
+ MT6389_VIO18_ANA_CON1
+#define PMIC_RG_VIO18_NDIS_EN_MASK 0x1
+#define PMIC_RG_VIO18_NDIS_EN_SHIFT 0
+#define PMIC_RG_VIO18_RSV_1_ADDR \
+ MT6389_VIO18_ANA_CON1
+#define PMIC_RG_VIO18_RSV_1_MASK 0x1
+#define PMIC_RG_VIO18_RSV_1_SHIFT 1
+#define PMIC_RG_VIO18_OC_LP_EN_ADDR \
+ MT6389_VIO18_ANA_CON1
+#define PMIC_RG_VIO18_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VIO18_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VIO18_MEASURE_FT_EN_ADDR \
+ MT6389_VIO18_ANA_CON1
+#define PMIC_RG_VIO18_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VIO18_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VIO18_OC_STATUS_ADDR \
+ MT6389_VIO18_ANA_CON1
+#define PMIC_RGS_VIO18_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VIO18_OC_STATUS_SHIFT 4
+#define PMIC_RG_SLDO20_RSV_ADDR \
+ MT6389_SLDO20_ANA_CON0
+#define PMIC_RG_SLDO20_RSV_MASK 0x3F
+#define PMIC_RG_SLDO20_RSV_SHIFT 0
+#define PMIC_RG_VRF12_VOCAL_ADDR \
+ MT6389_VRF12_ANA_CON0
+#define PMIC_RG_VRF12_VOCAL_MASK 0xF
+#define PMIC_RG_VRF12_VOCAL_SHIFT 0
+#define PMIC_RG_VRF12_VOSEL_ADDR \
+ MT6389_VRF12_ANA_CON0
+#define PMIC_RG_VRF12_VOSEL_MASK 0xF
+#define PMIC_RG_VRF12_VOSEL_SHIFT 8
+#define PMIC_RG_VRF12_NDIS_EN_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_NDIS_EN_MASK 0x1
+#define PMIC_RG_VRF12_NDIS_EN_SHIFT 0
+#define PMIC_RG_VRF12_STB_SEL_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_STB_SEL_MASK 0x1
+#define PMIC_RG_VRF12_STB_SEL_SHIFT 1
+#define PMIC_RG_VRF12_RSV_1_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_RSV_1_MASK 0x1
+#define PMIC_RG_VRF12_RSV_1_SHIFT 2
+#define PMIC_RG_VRF12_OC_LP_EN_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VRF12_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VRF12_MEASURE_FT_EN_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VRF12_MEASURE_FT_EN_SHIFT 4
+#define PMIC_RGS_VRF12_OC_STATUS_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RGS_VRF12_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VRF12_OC_STATUS_SHIFT 5
+#define PMIC_RG_VRF12_OC_LEVEL_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VRF12_OC_LEVEL_SHIFT 6
+#define PMIC_RG_VRF12_OC_TRIM_ADDR \
+ MT6389_VRF12_ANA_CON1
+#define PMIC_RG_VRF12_OC_TRIM_MASK 0x7
+#define PMIC_RG_VRF12_OC_TRIM_SHIFT 8
+#define PMIC_RG_VA09_VOCAL_ADDR \
+ MT6389_VA09_ANA_CON0
+#define PMIC_RG_VA09_VOCAL_MASK 0xF
+#define PMIC_RG_VA09_VOCAL_SHIFT 0
+#define PMIC_RG_VA09_VOSEL_ADDR \
+ MT6389_VA09_ANA_CON0
+#define PMIC_RG_VA09_VOSEL_MASK 0xF
+#define PMIC_RG_VA09_VOSEL_SHIFT 8
+#define PMIC_RG_VA09_NDIS_EN_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RG_VA09_NDIS_EN_MASK 0x1
+#define PMIC_RG_VA09_NDIS_EN_SHIFT 0
+#define PMIC_RG_VA09_RSV_1_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RG_VA09_RSV_1_MASK 0x1
+#define PMIC_RG_VA09_RSV_1_SHIFT 1
+#define PMIC_RG_VA09_OC_LP_EN_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RG_VA09_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VA09_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VA09_MEASURE_FT_EN_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RG_VA09_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VA09_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VA09_OC_STATUS_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RGS_VA09_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VA09_OC_STATUS_SHIFT 4
+#define PMIC_RG_VA09_OC_TRIM_ADDR \
+ MT6389_VA09_ANA_CON1
+#define PMIC_RG_VA09_OC_TRIM_MASK 0x7
+#define PMIC_RG_VA09_OC_TRIM_SHIFT 5
+#define PMIC_RG_VA12_VOCAL_ADDR \
+ MT6389_VA12_ANA_CON0
+#define PMIC_RG_VA12_VOCAL_MASK 0xF
+#define PMIC_RG_VA12_VOCAL_SHIFT 0
+#define PMIC_RG_VA12_VOSEL_ADDR \
+ MT6389_VA12_ANA_CON0
+#define PMIC_RG_VA12_VOSEL_MASK 0xF
+#define PMIC_RG_VA12_VOSEL_SHIFT 8
+#define PMIC_RG_VA12_NDIS_EN_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RG_VA12_NDIS_EN_MASK 0x1
+#define PMIC_RG_VA12_NDIS_EN_SHIFT 0
+#define PMIC_RG_VA12_RSV_1_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RG_VA12_RSV_1_MASK 0x1
+#define PMIC_RG_VA12_RSV_1_SHIFT 1
+#define PMIC_RG_VA12_OC_LP_EN_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RG_VA12_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VA12_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VA12_MEASURE_FT_EN_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RG_VA12_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VA12_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VA12_OC_STATUS_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RGS_VA12_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VA12_OC_STATUS_SHIFT 4
+#define PMIC_RG_VA12_OC_TRIM_ADDR \
+ MT6389_VA12_ANA_CON1
+#define PMIC_RG_VA12_OC_TRIM_MASK 0x7
+#define PMIC_RG_VA12_OC_TRIM_SHIFT 5
+#define PMIC_RG_VSRAM_PROC_NDIS_EN_ADDR \
+ MT6389_VSRAM_PROC_ANA_CON0
+#define PMIC_RG_VSRAM_PROC_NDIS_EN_MASK 0x1
+#define PMIC_RG_VSRAM_PROC_NDIS_EN_SHIFT 4
+#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_ADDR \
+ MT6389_VSRAM_PROC_ANA_CON0
+#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_MASK 0x3
+#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_SHIFT 5
+#define PMIC_RG_VSRAM_PROC_OC_LP_EN_ADDR \
+ MT6389_VSRAM_PROC_ANA_CON0
+#define PMIC_RG_VSRAM_PROC_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VSRAM_PROC_OC_LP_EN_SHIFT 7
+#define PMIC_RG_VSRAM_PROC_MEASURE_FT_EN_ADDR \
+ MT6389_VSRAM_PROC_ANA_CON0
+#define PMIC_RG_VSRAM_PROC_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VSRAM_PROC_MEASURE_FT_EN_SHIFT 8
+#define PMIC_RGS_VSRAM_PROC_OC_STATUS_ADDR \
+ MT6389_VSRAM_PROC_ANA_CON0
+#define PMIC_RGS_VSRAM_PROC_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VSRAM_PROC_OC_STATUS_SHIFT 9
+#define PMIC_RG_VDRAM2_NDIS_EN_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RG_VDRAM2_NDIS_EN_MASK 0x1
+#define PMIC_RG_VDRAM2_NDIS_EN_SHIFT 0
+#define PMIC_RG_VDRAM2_RSV_1_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RG_VDRAM2_RSV_1_MASK 0x1
+#define PMIC_RG_VDRAM2_RSV_1_SHIFT 1
+#define PMIC_RG_VDRAM2_OC_LP_EN_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RG_VDRAM2_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VDRAM2_OC_LP_EN_SHIFT 2
+#define PMIC_RG_VDRAM2_MEASURE_FT_EN_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RG_VDRAM2_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VDRAM2_MEASURE_FT_EN_SHIFT 3
+#define PMIC_RGS_VDRAM2_OC_STATUS_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RGS_VDRAM2_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VDRAM2_OC_STATUS_SHIFT 4
+#define PMIC_RG_VDRAM2_OC_TRIM_ADDR \
+ MT6389_VDRAM2_ANA_CON0
+#define PMIC_RG_VDRAM2_OC_TRIM_MASK 0x7
+#define PMIC_RG_VDRAM2_OC_TRIM_SHIFT 5
+#define PMIC_RG_SLDO14_RSV_ADDR \
+ MT6389_SLDO14_ANA_CON0
+#define PMIC_RG_SLDO14_RSV_MASK 0x3F
+#define PMIC_RG_SLDO14_RSV_SHIFT 0
+#define PMIC_LDO_ANA1_ELR_LEN_ADDR \
+ MT6389_LDO_ANA1_ELR_NUM
+#define PMIC_LDO_ANA1_ELR_LEN_MASK 0xFF
+#define PMIC_LDO_ANA1_ELR_LEN_SHIFT 0
+#define PMIC_RG_VRF18_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VRF18_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VRF18_VO_F_TRIM_SHIFT 0
+#define PMIC_RG_VRF18_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VRF18_VOTRIM_MASK 0xF
+#define PMIC_RG_VRF18_VOTRIM_SHIFT 1
+#define PMIC_RG_VGP3_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VGP3_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VGP3_VO_F_TRIM_SHIFT 5
+#define PMIC_RG_VGP3_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VGP3_VOTRIM_MASK 0xF
+#define PMIC_RG_VGP3_VOTRIM_SHIFT 6
+#define PMIC_RG_VCN18_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VCN18_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VCN18_VO_F_TRIM_SHIFT 10
+#define PMIC_RG_VCN18_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VCN18_VOTRIM_MASK 0xF
+#define PMIC_RG_VCN18_VOTRIM_SHIFT 11
+#define PMIC_RG_VIO18_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_0
+#define PMIC_RG_VIO18_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VIO18_VO_F_TRIM_SHIFT 15
+#define PMIC_RG_VIO18_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VIO18_VOTRIM_MASK 0xF
+#define PMIC_RG_VIO18_VOTRIM_SHIFT 0
+#define PMIC_RG_VIO18_OC_LEVEL_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VIO18_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VIO18_OC_LEVEL_SHIFT 4
+#define PMIC_RG_VIO18_OC_TRIM_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VIO18_OC_TRIM_MASK 0x7
+#define PMIC_RG_VIO18_OC_TRIM_SHIFT 6
+#define PMIC_RG_VIO18_STB_SEL_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VIO18_STB_SEL_MASK 0x1
+#define PMIC_RG_VIO18_STB_SEL_SHIFT 9
+#define PMIC_RG_VRF12_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VRF12_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VRF12_VO_F_TRIM_SHIFT 10
+#define PMIC_RG_VRF12_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VRF12_VOTRIM_MASK 0xF
+#define PMIC_RG_VRF12_VOTRIM_SHIFT 11
+#define PMIC_RG_VA09_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_1
+#define PMIC_RG_VA09_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VA09_VO_F_TRIM_SHIFT 15
+#define PMIC_RG_VA09_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA09_VOTRIM_MASK 0xF
+#define PMIC_RG_VA09_VOTRIM_SHIFT 0
+#define PMIC_RG_VA09_OC_LEVEL_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA09_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VA09_OC_LEVEL_SHIFT 4
+#define PMIC_RG_VA09_STB_SEL_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA09_STB_SEL_MASK 0x1
+#define PMIC_RG_VA09_STB_SEL_SHIFT 6
+#define PMIC_RG_VA12_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA12_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VA12_VO_F_TRIM_SHIFT 7
+#define PMIC_RG_VA12_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA12_VOTRIM_MASK 0xF
+#define PMIC_RG_VA12_VOTRIM_SHIFT 8
+#define PMIC_RG_VA12_OC_LEVEL_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA12_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VA12_OC_LEVEL_SHIFT 12
+#define PMIC_RG_VA12_STB_SEL_ADDR \
+ MT6389_VRF18_ELR_2
+#define PMIC_RG_VA12_STB_SEL_MASK 0x1
+#define PMIC_RG_VA12_STB_SEL_SHIFT 14
+#define PMIC_RG_VSRAM_PROC_OC_LEVEL_ADDR \
+ MT6389_VRF18_ELR_3
+#define PMIC_RG_VSRAM_PROC_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VSRAM_PROC_OC_LEVEL_SHIFT 0
+#define PMIC_RG_VSRAM_PROC_RSV_H_ADDR \
+ MT6389_VRF18_ELR_3
+#define PMIC_RG_VSRAM_PROC_RSV_H_MASK 0xF
+#define PMIC_RG_VSRAM_PROC_RSV_H_SHIFT 2
+#define PMIC_RG_VSRAM_PROC_RSV_L_ADDR \
+ MT6389_VRF18_ELR_3
+#define PMIC_RG_VSRAM_PROC_RSV_L_MASK 0xF
+#define PMIC_RG_VSRAM_PROC_RSV_L_SHIFT 6
+#define PMIC_RG_VDRAM2_VO_F_TRIM_ADDR \
+ MT6389_VRF18_ELR_3
+#define PMIC_RG_VDRAM2_VO_F_TRIM_MASK 0x1
+#define PMIC_RG_VDRAM2_VO_F_TRIM_SHIFT 10
+#define PMIC_RG_VDRAM2_VOTRIM_ADDR \
+ MT6389_VRF18_ELR_3
+#define PMIC_RG_VDRAM2_VOTRIM_MASK 0xF
+#define PMIC_RG_VDRAM2_VOTRIM_SHIFT 11
+#define PMIC_RG_VDRAM2_OC_LEVEL_ADDR \
+ MT6389_VRF18_ELR_4
+#define PMIC_RG_VDRAM2_OC_LEVEL_MASK 0x3
+#define PMIC_RG_VDRAM2_OC_LEVEL_SHIFT 0
+#define PMIC_RG_VDRAM2_STB_SEL_ADDR \
+ MT6389_VRF18_ELR_4
+#define PMIC_RG_VDRAM2_STB_SEL_MASK 0x1
+#define PMIC_RG_VDRAM2_STB_SEL_SHIFT 2
+#define PMIC_LDO_ANA2_ANA_ID_ADDR \
+ MT6389_LDO_ANA2_DSN_ID
+#define PMIC_LDO_ANA2_ANA_ID_MASK 0xFF
+#define PMIC_LDO_ANA2_ANA_ID_SHIFT 0
+#define PMIC_LDO_ANA2_DIG_ID_ADDR \
+ MT6389_LDO_ANA2_DSN_ID
+#define PMIC_LDO_ANA2_DIG_ID_MASK 0xFF
+#define PMIC_LDO_ANA2_DIG_ID_SHIFT 8
+#define PMIC_LDO_ANA2_ANA_MINOR_REV_ADDR \
+ MT6389_LDO_ANA2_DSN_REV0
+#define PMIC_LDO_ANA2_ANA_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA2_ANA_MINOR_REV_SHIFT 0
+#define PMIC_LDO_ANA2_ANA_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA2_DSN_REV0
+#define PMIC_LDO_ANA2_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA2_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_LDO_ANA2_DIG_MINOR_REV_ADDR \
+ MT6389_LDO_ANA2_DSN_REV0
+#define PMIC_LDO_ANA2_DIG_MINOR_REV_MASK 0xF
+#define PMIC_LDO_ANA2_DIG_MINOR_REV_SHIFT 8
+#define PMIC_LDO_ANA2_DIG_MAJOR_REV_ADDR \
+ MT6389_LDO_ANA2_DSN_REV0
+#define PMIC_LDO_ANA2_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_LDO_ANA2_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_LDO_ANA2_DSN_CBS_ADDR \
+ MT6389_LDO_ANA2_DSN_DBI
+#define PMIC_LDO_ANA2_DSN_CBS_MASK 0x3
+#define PMIC_LDO_ANA2_DSN_CBS_SHIFT 0
+#define PMIC_LDO_ANA2_DSN_BIX_ADDR \
+ MT6389_LDO_ANA2_DSN_DBI
+#define PMIC_LDO_ANA2_DSN_BIX_MASK 0x3
+#define PMIC_LDO_ANA2_DSN_BIX_SHIFT 2
+#define PMIC_LDO_ANA2_DSN_ESP_ADDR \
+ MT6389_LDO_ANA2_DSN_DBI
+#define PMIC_LDO_ANA2_DSN_ESP_MASK 0xFF
+#define PMIC_LDO_ANA2_DSN_ESP_SHIFT 8
+#define PMIC_LDO_ANA2_DSN_FPI_ADDR \
+ MT6389_LDO_ANA2_DSN_FPI
+#define PMIC_LDO_ANA2_DSN_FPI_MASK 0xFF
+#define PMIC_LDO_ANA2_DSN_FPI_SHIFT 0
+#define PMIC_RG_VXO22_VOCAL_ADDR \
+ MT6389_VXO22_ANA_CON0
+#define PMIC_RG_VXO22_VOCAL_MASK 0xF
+#define PMIC_RG_VXO22_VOCAL_SHIFT 0
+#define PMIC_RG_VXO22_VOSEL_ADDR \
+ MT6389_VXO22_ANA_CON0
+#define PMIC_RG_VXO22_VOSEL_MASK 0xF
+#define PMIC_RG_VXO22_VOSEL_SHIFT 8
+#define PMIC_RG_VXO22_RSV_1_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RG_VXO22_RSV_1_MASK 0x1
+#define PMIC_RG_VXO22_RSV_1_SHIFT 2
+#define PMIC_RG_VXO22_OC_LP_EN_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RG_VXO22_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VXO22_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VXO22_ULP_IQ_CLAMP_EN_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RG_VXO22_ULP_IQ_CLAMP_EN_MASK 0x1
+#define PMIC_RG_VXO22_ULP_IQ_CLAMP_EN_SHIFT 4
+#define PMIC_RG_VXO22_ULP_BIASX2_EN_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RG_VXO22_ULP_BIASX2_EN_MASK 0x1
+#define PMIC_RG_VXO22_ULP_BIASX2_EN_SHIFT 5
+#define PMIC_RG_VXO22_MEASURE_FT_EN_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RG_VXO22_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VXO22_MEASURE_FT_EN_SHIFT 6
+#define PMIC_RGS_VXO22_OC_STATUS_ADDR \
+ MT6389_VXO22_ANA_CON1
+#define PMIC_RGS_VXO22_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VXO22_OC_STATUS_SHIFT 7
+#define PMIC_RG_VRFCK_VOCAL_ADDR \
+ MT6389_VRFCK_ANA_CON0
+#define PMIC_RG_VRFCK_VOCAL_MASK 0xF
+#define PMIC_RG_VRFCK_VOCAL_SHIFT 0
+#define PMIC_RG_VRFCK_VOSEL_ADDR \
+ MT6389_VRFCK_ANA_CON0
+#define PMIC_RG_VRFCK_VOSEL_MASK 0xF
+#define PMIC_RG_VRFCK_VOSEL_SHIFT 8
+#define PMIC_RG_VRFCK_RSV_1_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_RSV_1_MASK 0x1
+#define PMIC_RG_VRFCK_RSV_1_SHIFT 2
+#define PMIC_RG_VRFCK_OC_LP_EN_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VRFCK_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VRFCK_ULP_IQ_CLAMP_EN_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_ULP_IQ_CLAMP_EN_MASK 0x1
+#define PMIC_RG_VRFCK_ULP_IQ_CLAMP_EN_SHIFT 4
+#define PMIC_RG_VRFCK_ULP_BIASX2_EN_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_ULP_BIASX2_EN_MASK 0x1
+#define PMIC_RG_VRFCK_ULP_BIASX2_EN_SHIFT 5
+#define PMIC_RG_VRFCK_MEASURE_FT_EN_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VRFCK_MEASURE_FT_EN_SHIFT 6
+#define PMIC_RGS_VRFCK_OC_STATUS_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RGS_VRFCK_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VRFCK_OC_STATUS_SHIFT 7
+#define PMIC_RG_VRFCK_CAS_CSEL_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_CAS_CSEL_MASK 0x3
+#define PMIC_RG_VRFCK_CAS_CSEL_SHIFT 8
+#define PMIC_RG_VRFCK_CAS_ISEL_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_CAS_ISEL_MASK 0xF
+#define PMIC_RG_VRFCK_CAS_ISEL_SHIFT 10
+#define PMIC_RG_VRFCK_CAS_RSEL_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_CAS_RSEL_MASK 0x1
+#define PMIC_RG_VRFCK_CAS_RSEL_SHIFT 14
+#define PMIC_RG_VRFCK_CAS_STB_ADDR \
+ MT6389_VRFCK_ANA_CON1
+#define PMIC_RG_VRFCK_CAS_STB_MASK 0x1
+#define PMIC_RG_VRFCK_CAS_STB_SHIFT 15
+#define PMIC_RG_VRFCK_1_VOCAL_ADDR \
+ MT6389_VRFCK_1_ANA_CON0
+#define PMIC_RG_VRFCK_1_VOCAL_MASK 0xF
+#define PMIC_RG_VRFCK_1_VOCAL_SHIFT 0
+#define PMIC_RG_VRFCK_1_VOSEL_ADDR \
+ MT6389_VRFCK_1_ANA_CON0
+#define PMIC_RG_VRFCK_1_VOSEL_MASK 0xF
+#define PMIC_RG_VRFCK_1_VOSEL_SHIFT 8
+#define PMIC_RG_VRFCK_1_RSV_1_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RG_VRFCK_1_RSV_1_MASK 0x1
+#define PMIC_RG_VRFCK_1_RSV_1_SHIFT 2
+#define PMIC_RG_VRFCK_1_OC_LP_EN_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RG_VRFCK_1_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VRFCK_1_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VRFCK_1_ULP_IQ_CLAMP_EN_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RG_VRFCK_1_ULP_IQ_CLAMP_EN_MASK 0x1
+#define PMIC_RG_VRFCK_1_ULP_IQ_CLAMP_EN_SHIFT 4
+#define PMIC_RG_VRFCK_1_ULP_BIASX2_EN_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RG_VRFCK_1_ULP_BIASX2_EN_MASK 0x1
+#define PMIC_RG_VRFCK_1_ULP_BIASX2_EN_SHIFT 5
+#define PMIC_RG_VRFCK_1_MEASURE_FT_EN_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RG_VRFCK_1_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VRFCK_1_MEASURE_FT_EN_SHIFT 6
+#define PMIC_RGS_VRFCK_1_OC_STATUS_ADDR \
+ MT6389_VRFCK_1_ANA_CON1
+#define PMIC_RGS_VRFCK_1_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VRFCK_1_OC_STATUS_SHIFT 7
+#define PMIC_RG_VBBCK_VOCAL_ADDR \
+ MT6389_VBBCK_ANA_CON0
+#define PMIC_RG_VBBCK_VOCAL_MASK 0xF
+#define PMIC_RG_VBBCK_VOCAL_SHIFT 0
+#define PMIC_RG_VBBCK_VOSEL_ADDR \
+ MT6389_VBBCK_ANA_CON0
+#define PMIC_RG_VBBCK_VOSEL_MASK 0xF
+#define PMIC_RG_VBBCK_VOSEL_SHIFT 8
+#define PMIC_RG_VBBCK_RSV_1_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RG_VBBCK_RSV_1_MASK 0x1
+#define PMIC_RG_VBBCK_RSV_1_SHIFT 2
+#define PMIC_RG_VBBCK_OC_LP_EN_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RG_VBBCK_OC_LP_EN_MASK 0x1
+#define PMIC_RG_VBBCK_OC_LP_EN_SHIFT 3
+#define PMIC_RG_VBBCK_ULP_IQ_CLAMP_EN_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RG_VBBCK_ULP_IQ_CLAMP_EN_MASK 0x1
+#define PMIC_RG_VBBCK_ULP_IQ_CLAMP_EN_SHIFT 4
+#define PMIC_RG_VBBCK_ULP_BIASX2_EN_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RG_VBBCK_ULP_BIASX2_EN_MASK 0x1
+#define PMIC_RG_VBBCK_ULP_BIASX2_EN_SHIFT 5
+#define PMIC_RG_VBBCK_MEASURE_FT_EN_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RG_VBBCK_MEASURE_FT_EN_MASK 0x1
+#define PMIC_RG_VBBCK_MEASURE_FT_EN_SHIFT 6
+#define PMIC_RGS_VBBCK_OC_STATUS_ADDR \
+ MT6389_VBBCK_ANA_CON1
+#define PMIC_RGS_VBBCK_OC_STATUS_MASK 0x1
+#define PMIC_RGS_VBBCK_OC_STATUS_SHIFT 7
+#define PMIC_LDO_ANA2_ELR_LEN_ADDR \
+ MT6389_LDO_ANA2_ELR_NUM
+#define PMIC_LDO_ANA2_ELR_LEN_MASK 0xFF
+#define PMIC_LDO_ANA2_ELR_LEN_SHIFT 0
+#define PMIC_RG_VXO22_VOTRIM_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VXO22_VOTRIM_MASK 0xF
+#define PMIC_RG_VXO22_VOTRIM_SHIFT 0
+#define PMIC_RG_VXO22_NDIS_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VXO22_NDIS_EN_MASK 0x1
+#define PMIC_RG_VXO22_NDIS_EN_SHIFT 4
+#define PMIC_RG_VRFCK_VOTRIM_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_VOTRIM_MASK 0xF
+#define PMIC_RG_VRFCK_VOTRIM_SHIFT 5
+#define PMIC_RG_VRFCK_NDIS_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_NDIS_EN_MASK 0x1
+#define PMIC_RG_VRFCK_NDIS_EN_SHIFT 9
+#define PMIC_RG_VRFCK_HV_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_HV_EN_MASK 0x1
+#define PMIC_RG_VRFCK_HV_EN_SHIFT 10
+#define PMIC_RG_VRFCK_CAS_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_CAS_EN_MASK 0x1
+#define PMIC_RG_VRFCK_CAS_EN_SHIFT 11
+#define PMIC_RG_VRFCK_1_VOTRIM_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_1_VOTRIM_MASK 0xF
+#define PMIC_RG_VRFCK_1_VOTRIM_SHIFT 12
+#define PMIC_RG_VRFCK_1_NDIS_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_1
+#define PMIC_RG_VRFCK_1_NDIS_EN_MASK 0x1
+#define PMIC_RG_VRFCK_1_NDIS_EN_SHIFT 0
+#define PMIC_RG_VBBCK_VOTRIM_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_1
+#define PMIC_RG_VBBCK_VOTRIM_MASK 0xF
+#define PMIC_RG_VBBCK_VOTRIM_SHIFT 1
+#define PMIC_RG_VBBCK_NDIS_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_1
+#define PMIC_RG_VBBCK_NDIS_EN_MASK 0x1
+#define PMIC_RG_VBBCK_NDIS_EN_SHIFT 5
+#define PMIC_RG_VBBCK_HV_EN_ADDR \
+ MT6389_DCXO_ADLDO_BIAS_ELR_1
+#define PMIC_RG_VBBCK_HV_EN_MASK 0x1
+#define PMIC_RG_VBBCK_HV_EN_SHIFT 6
+#define PMIC_AUD_TOP_ANA_ID_ADDR \
+ MT6389_AUD_TOP_ID
+#define PMIC_AUD_TOP_ANA_ID_MASK 0xFF
+#define PMIC_AUD_TOP_ANA_ID_SHIFT 0
+#define PMIC_AUD_TOP_DIG_ID_ADDR \
+ MT6389_AUD_TOP_ID
+#define PMIC_AUD_TOP_DIG_ID_MASK 0xFF
+#define PMIC_AUD_TOP_DIG_ID_SHIFT 8
+#define PMIC_AUD_TOP_ANA_MINOR_REV_ADDR \
+ MT6389_AUD_TOP_REV0
+#define PMIC_AUD_TOP_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUD_TOP_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUD_TOP_ANA_MAJOR_REV_ADDR \
+ MT6389_AUD_TOP_REV0
+#define PMIC_AUD_TOP_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUD_TOP_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUD_TOP_DIG_MINOR_REV_ADDR \
+ MT6389_AUD_TOP_REV0
+#define PMIC_AUD_TOP_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUD_TOP_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUD_TOP_DIG_MAJOR_REV_ADDR \
+ MT6389_AUD_TOP_REV0
+#define PMIC_AUD_TOP_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUD_TOP_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUD_TOP_CBS_ADDR \
+ MT6389_AUD_TOP_DBI
+#define PMIC_AUD_TOP_CBS_MASK 0x3
+#define PMIC_AUD_TOP_CBS_SHIFT 0
+#define PMIC_AUD_TOP_BIX_ADDR \
+ MT6389_AUD_TOP_DBI
+#define PMIC_AUD_TOP_BIX_MASK 0x3
+#define PMIC_AUD_TOP_BIX_SHIFT 2
+#define PMIC_AUD_TOP_ESP_ADDR \
+ MT6389_AUD_TOP_DBI
+#define PMIC_AUD_TOP_ESP_MASK 0xFF
+#define PMIC_AUD_TOP_ESP_SHIFT 8
+#define PMIC_AUD_TOP_FPI_ADDR \
+ MT6389_AUD_TOP_DXI
+#define PMIC_AUD_TOP_FPI_MASK 0xFF
+#define PMIC_AUD_TOP_FPI_SHIFT 0
+#define PMIC_AUD_TOP_CLK_OFFSET_ADDR \
+ MT6389_AUD_TOP_CKPDN_TPM0
+#define PMIC_AUD_TOP_CLK_OFFSET_MASK 0xFF
+#define PMIC_AUD_TOP_CLK_OFFSET_SHIFT 0
+#define PMIC_AUD_TOP_RST_OFFSET_ADDR \
+ MT6389_AUD_TOP_CKPDN_TPM0
+#define PMIC_AUD_TOP_RST_OFFSET_MASK 0xFF
+#define PMIC_AUD_TOP_RST_OFFSET_SHIFT 8
+#define PMIC_AUD_TOP_INT_OFFSET_ADDR \
+ MT6389_AUD_TOP_CKPDN_TPM1
+#define PMIC_AUD_TOP_INT_OFFSET_MASK 0xFF
+#define PMIC_AUD_TOP_INT_OFFSET_SHIFT 0
+#define PMIC_AUD_TOP_INT_LEN_ADDR \
+ MT6389_AUD_TOP_CKPDN_TPM1
+#define PMIC_AUD_TOP_INT_LEN_MASK 0xFF
+#define PMIC_AUD_TOP_INT_LEN_SHIFT 8
+#define PMIC_RG_AUD_CK_PDN_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0
+#define PMIC_RG_AUD_CK_PDN_MASK 0x1
+#define PMIC_RG_AUD_CK_PDN_SHIFT 1
+#define PMIC_RG_AUDIF_CK_PDN_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0
+#define PMIC_RG_AUDIF_CK_PDN_MASK 0x1
+#define PMIC_RG_AUDIF_CK_PDN_SHIFT 2
+#define PMIC_RG_AUD_INTRP_CK_PDN_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0
+#define PMIC_RG_AUD_INTRP_CK_PDN_MASK 0x1
+#define PMIC_RG_AUD_INTRP_CK_PDN_SHIFT 3
+#define PMIC_RG_ZCD13M_CK_PDN_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0
+#define PMIC_RG_ZCD13M_CK_PDN_MASK 0x1
+#define PMIC_RG_ZCD13M_CK_PDN_SHIFT 5
+#define PMIC_RG_AUDNCP_CK_PDN_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0
+#define PMIC_RG_AUDNCP_CK_PDN_MASK 0x1
+#define PMIC_RG_AUDNCP_CK_PDN_SHIFT 6
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0_SET
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x7F
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_CKPDN_CON0_CLR
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x7F
+#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_SHIFT 0
+#define PMIC_RG_AUD_CK_CKSEL_ADDR \
+ MT6389_AUD_TOP_CKSEL_CON0
+#define PMIC_RG_AUD_CK_CKSEL_MASK 0x1
+#define PMIC_RG_AUD_CK_CKSEL_SHIFT 2
+#define PMIC_RG_AUDIF_CK_CKSEL_ADDR \
+ MT6389_AUD_TOP_CKSEL_CON0
+#define PMIC_RG_AUDIF_CK_CKSEL_MASK 0x1
+#define PMIC_RG_AUDIF_CK_CKSEL_SHIFT 3
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_ADDR \
+ MT6389_AUD_TOP_CKSEL_CON0_SET
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xF
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_CKSEL_CON0_CLR
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xF
+#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_SHIFT 0
+#define PMIC_RG_AUD26M_CK_TST_DIS_ADDR \
+ MT6389_AUD_TOP_CKTST_CON0
+#define PMIC_RG_AUD26M_CK_TST_DIS_MASK 0x1
+#define PMIC_RG_AUD26M_CK_TST_DIS_SHIFT 0
+#define PMIC_RG_AUD_CK_TSTSEL_ADDR \
+ MT6389_AUD_TOP_CKTST_CON0
+#define PMIC_RG_AUD_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUD_CK_TSTSEL_SHIFT 2
+#define PMIC_RG_AUDIF_CK_TSTSEL_ADDR \
+ MT6389_AUD_TOP_CKTST_CON0
+#define PMIC_RG_AUDIF_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUDIF_CK_TSTSEL_SHIFT 3
+#define PMIC_RG_AUD26M_CK_TSTSEL_ADDR \
+ MT6389_AUD_TOP_CKTST_CON0
+#define PMIC_RG_AUD26M_CK_TSTSEL_MASK 0x1
+#define PMIC_RG_AUD26M_CK_TSTSEL_SHIFT 4
+#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_ADDR \
+ MT6389_AUD_TOP_CLK_HWEN_CON0
+#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
+#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_SHIFT 0
+#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_ADDR \
+ MT6389_AUD_TOP_CLK_HWEN_CON0_SET
+#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_CLK_HWEN_CON0_CLR
+#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SHIFT 0
+#define PMIC_RG_AUDIO_RST_ADDR \
+ MT6389_AUD_TOP_RST_CON0
+#define PMIC_RG_AUDIO_RST_MASK 0x1
+#define PMIC_RG_AUDIO_RST_SHIFT 0
+#define PMIC_RG_ZCD_RST_ADDR \
+ MT6389_AUD_TOP_RST_CON0
+#define PMIC_RG_ZCD_RST_MASK 0x1
+#define PMIC_RG_ZCD_RST_SHIFT 2
+#define PMIC_RG_AUDNCP_RST_ADDR \
+ MT6389_AUD_TOP_RST_CON0
+#define PMIC_RG_AUDNCP_RST_MASK 0x1
+#define PMIC_RG_AUDNCP_RST_SHIFT 3
+#define PMIC_RG_AUD_TOP_RST_CON0_SET_ADDR \
+ MT6389_AUD_TOP_RST_CON0_SET
+#define PMIC_RG_AUD_TOP_RST_CON0_SET_MASK 0xF
+#define PMIC_RG_AUD_TOP_RST_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_TOP_RST_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_RST_CON0_CLR
+#define PMIC_RG_AUD_TOP_RST_CON0_CLR_MASK 0xF
+#define PMIC_RG_AUD_TOP_RST_CON0_CLR_SHIFT 0
+#define PMIC_BANK_AUDIO_SWRST_ADDR \
+ MT6389_AUD_TOP_RST_BANK_CON0
+#define PMIC_BANK_AUDIO_SWRST_MASK 0x1
+#define PMIC_BANK_AUDIO_SWRST_SHIFT 1
+#define PMIC_BANK_AUDZCD_SWRST_ADDR \
+ MT6389_AUD_TOP_RST_BANK_CON0
+#define PMIC_BANK_AUDZCD_SWRST_MASK 0x1
+#define PMIC_BANK_AUDZCD_SWRST_SHIFT 2
+#define PMIC_RG_INT_EN_AUDIO_ADDR \
+ MT6389_AUD_TOP_INT_CON0
+#define PMIC_RG_INT_EN_AUDIO_MASK 0x1
+#define PMIC_RG_INT_EN_AUDIO_SHIFT 0
+#define PMIC_RG_AUD_INT_CON0_SET_ADDR \
+ MT6389_AUD_TOP_INT_CON0_SET
+#define PMIC_RG_AUD_INT_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_AUD_INT_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_INT_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_INT_CON0_CLR
+#define PMIC_RG_AUD_INT_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_AUD_INT_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_MASK_AUDIO_ADDR \
+ MT6389_AUD_TOP_INT_MASK_CON0
+#define PMIC_RG_INT_MASK_AUDIO_MASK 0x1
+#define PMIC_RG_INT_MASK_AUDIO_SHIFT 0
+#define PMIC_RG_AUD_INT_MASK_CON0_SET_ADDR \
+ MT6389_AUD_TOP_INT_MASK_CON0_SET
+#define PMIC_RG_AUD_INT_MASK_CON0_SET_MASK 0xFFFF
+#define PMIC_RG_AUD_INT_MASK_CON0_SET_SHIFT 0
+#define PMIC_RG_AUD_INT_MASK_CON0_CLR_ADDR \
+ MT6389_AUD_TOP_INT_MASK_CON0_CLR
+#define PMIC_RG_AUD_INT_MASK_CON0_CLR_MASK 0xFFFF
+#define PMIC_RG_AUD_INT_MASK_CON0_CLR_SHIFT 0
+#define PMIC_RG_INT_STATUS_AUDIO_ADDR \
+ MT6389_AUD_TOP_INT_STATUS0
+#define PMIC_RG_INT_STATUS_AUDIO_MASK 0x1
+#define PMIC_RG_INT_STATUS_AUDIO_SHIFT 0
+#define PMIC_RG_INT_RAW_STATUS_AUDIO_ADDR \
+ MT6389_AUD_TOP_INT_RAW_STATUS0
+#define PMIC_RG_INT_RAW_STATUS_AUDIO_MASK 0x1
+#define PMIC_RG_INT_RAW_STATUS_AUDIO_SHIFT 0
+#define PMIC_RG_AUD_TOP_INT_POLARITY_ADDR \
+ MT6389_AUD_TOP_INT_MISC_CON0
+#define PMIC_RG_AUD_TOP_INT_POLARITY_MASK 0x1
+#define PMIC_RG_AUD_TOP_INT_POLARITY_SHIFT 0
+#define PMIC_RG_DIVCKS_CHG_ADDR \
+ MT6389_AUDNCP_CLKDIV_CON0
+#define PMIC_RG_DIVCKS_CHG_MASK 0x1
+#define PMIC_RG_DIVCKS_CHG_SHIFT 0
+#define PMIC_RG_DIVCKS_ON_ADDR \
+ MT6389_AUDNCP_CLKDIV_CON1
+#define PMIC_RG_DIVCKS_ON_MASK 0x1
+#define PMIC_RG_DIVCKS_ON_SHIFT 0
+#define PMIC_RG_DIVCKS_PRG_ADDR \
+ MT6389_AUDNCP_CLKDIV_CON2
+#define PMIC_RG_DIVCKS_PRG_MASK 0x1FF
+#define PMIC_RG_DIVCKS_PRG_SHIFT 0
+#define PMIC_RG_DIVCKS_PWD_NCP_ADDR \
+ MT6389_AUDNCP_CLKDIV_CON3
+#define PMIC_RG_DIVCKS_PWD_NCP_MASK 0x1
+#define PMIC_RG_DIVCKS_PWD_NCP_SHIFT 0
+#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_ADDR \
+ MT6389_AUDNCP_CLKDIV_CON4
+#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
+#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT 0
+#define PMIC_RG_AUD_TOP_MON_SEL_ADDR \
+ MT6389_AUD_TOP_MON_CON0
+#define PMIC_RG_AUD_TOP_MON_SEL_MASK 0x7
+#define PMIC_RG_AUD_TOP_MON_SEL_SHIFT 0
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_ADDR \
+ MT6389_AUD_TOP_MON_CON0
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xFF
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_SHIFT 3
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_ADDR \
+ MT6389_AUD_TOP_MON_CON0
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1
+#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_SHIFT 11
+#define PMIC_AUDIO_DIG_ANA_ID_ADDR \
+ MT6389_AUDIO_DIG_DSN_ID
+#define PMIC_AUDIO_DIG_ANA_ID_MASK 0xFF
+#define PMIC_AUDIO_DIG_ANA_ID_SHIFT 0
+#define PMIC_AUDIO_DIG_DIG_ID_ADDR \
+ MT6389_AUDIO_DIG_DSN_ID
+#define PMIC_AUDIO_DIG_DIG_ID_MASK 0xFF
+#define PMIC_AUDIO_DIG_DIG_ID_SHIFT 8
+#define PMIC_AUDIO_DIG_ANA_MINOR_REV_ADDR \
+ MT6389_AUDIO_DIG_DSN_REV0
+#define PMIC_AUDIO_DIG_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUDIO_DIG_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_ADDR \
+ MT6389_AUDIO_DIG_DSN_REV0
+#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUDIO_DIG_DIG_MINOR_REV_ADDR \
+ MT6389_AUDIO_DIG_DSN_REV0
+#define PMIC_AUDIO_DIG_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUDIO_DIG_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_ADDR \
+ MT6389_AUDIO_DIG_DSN_REV0
+#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUDIO_DIG_DSN_CBS_ADDR \
+ MT6389_AUDIO_DIG_DSN_DBI
+#define PMIC_AUDIO_DIG_DSN_CBS_MASK 0x3
+#define PMIC_AUDIO_DIG_DSN_CBS_SHIFT 0
+#define PMIC_AUDIO_DIG_DSN_BIX_ADDR \
+ MT6389_AUDIO_DIG_DSN_DBI
+#define PMIC_AUDIO_DIG_DSN_BIX_MASK 0x3
+#define PMIC_AUDIO_DIG_DSN_BIX_SHIFT 2
+#define PMIC_AUDIO_DIG_ESP_ADDR \
+ MT6389_AUDIO_DIG_DSN_DBI
+#define PMIC_AUDIO_DIG_ESP_MASK 0xFF
+#define PMIC_AUDIO_DIG_ESP_SHIFT 8
+#define PMIC_AUDIO_DIG_DSN_FPI_ADDR \
+ MT6389_AUDIO_DIG_DSN_DXI
+#define PMIC_AUDIO_DIG_DSN_FPI_MASK 0xFF
+#define PMIC_AUDIO_DIG_DSN_FPI_SHIFT 0
+#define PMIC_AFE_ON_ADDR \
+ MT6389_AFE_UL_DL_CON0
+#define PMIC_AFE_ON_MASK 0x1
+#define PMIC_AFE_ON_SHIFT 0
+#define PMIC_AFE_DL_LR_SWAP_ADDR \
+ MT6389_AFE_UL_DL_CON0
+#define PMIC_AFE_DL_LR_SWAP_MASK 0x1
+#define PMIC_AFE_DL_LR_SWAP_SHIFT 14
+#define PMIC_AFE_UL_LR_SWAP_ADDR \
+ MT6389_AFE_UL_DL_CON0
+#define PMIC_AFE_UL_LR_SWAP_MASK 0x1
+#define PMIC_AFE_UL_LR_SWAP_SHIFT 15
+#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_ADDR \
+ MT6389_AFE_DL_SRC2_CON0_L
+#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
+#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_SHIFT 0
+#define PMIC_C_TWO_DIGITAL_MIC_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_H
+#define PMIC_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
+#define PMIC_C_TWO_DIGITAL_MIC_CTL_SHIFT 7
+#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_H
+#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
+#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_SHIFT 8
+#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_H
+#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
+#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_SHIFT 11
+#define PMIC_UL_SRC_ON_TMP_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_L
+#define PMIC_UL_SRC_ON_TMP_CTL_MASK 0x1
+#define PMIC_UL_SRC_ON_TMP_CTL_SHIFT 0
+#define PMIC_UL_SDM_3_LEVEL_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_L
+#define PMIC_UL_SDM_3_LEVEL_CTL_MASK 0x1
+#define PMIC_UL_SDM_3_LEVEL_CTL_SHIFT 1
+#define PMIC_UL_LOOP_BACK_MODE_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_L
+#define PMIC_UL_LOOP_BACK_MODE_CTL_MASK 0x1
+#define PMIC_UL_LOOP_BACK_MODE_CTL_SHIFT 2
+#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_L
+#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
+#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_SHIFT 5
+#define PMIC_DMIC_LOW_POWER_MODE_CTL_ADDR \
+ MT6389_AFE_UL_SRC_CON0_L
+#define PMIC_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
+#define PMIC_DMIC_LOW_POWER_MODE_CTL_SHIFT 14
+#define PMIC_DL_SINE_ON_ADDR \
+ MT6389_AFE_TOP_CON0
+#define PMIC_DL_SINE_ON_MASK 0x1
+#define PMIC_DL_SINE_ON_SHIFT 0
+#define PMIC_UL_SINE_ON_ADDR \
+ MT6389_AFE_TOP_CON0
+#define PMIC_UL_SINE_ON_MASK 0x1
+#define PMIC_UL_SINE_ON_SHIFT 1
+#define PMIC_MTKAIF_SINE_ON_ADDR \
+ MT6389_AFE_TOP_CON0
+#define PMIC_MTKAIF_SINE_ON_MASK 0x1
+#define PMIC_MTKAIF_SINE_ON_SHIFT 2
+#define PMIC_PDN_AFE_DL_PREDIST_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_AFE_DL_PREDIST_CTL_MASK 0x1
+#define PMIC_PDN_AFE_DL_PREDIST_CTL_SHIFT 0
+#define PMIC_PDN_AFE_TESTMODEL_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_AFE_TESTMODEL_CTL_MASK 0x1
+#define PMIC_PDN_AFE_TESTMODEL_CTL_SHIFT 1
+#define PMIC_PWR_CLK_DIS_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PWR_CLK_DIS_CTL_MASK 0x1
+#define PMIC_PWR_CLK_DIS_CTL_SHIFT 2
+#define PMIC_PDN_I2S_DL_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_I2S_DL_CTL_MASK 0x1
+#define PMIC_PDN_I2S_DL_CTL_SHIFT 3
+#define PMIC_PDN_ADC_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_ADC_CTL_MASK 0x1
+#define PMIC_PDN_ADC_CTL_SHIFT 5
+#define PMIC_PDN_DAC_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_DAC_CTL_MASK 0x1
+#define PMIC_PDN_DAC_CTL_SHIFT 6
+#define PMIC_PDN_AFE_CTL_ADDR \
+ MT6389_AUDIO_TOP_CON0
+#define PMIC_PDN_AFE_CTL_MASK 0x1
+#define PMIC_PDN_AFE_CTL_SHIFT 7
+#define PMIC_AFE_MON_SEL_ADDR \
+ MT6389_AFE_MON_DEBUG0
+#define PMIC_AFE_MON_SEL_MASK 0xF
+#define PMIC_AFE_MON_SEL_SHIFT 0
+#define PMIC_AUDIO_SYS_TOP_MON_SEL_ADDR \
+ MT6389_AFE_MON_DEBUG0
+#define PMIC_AUDIO_SYS_TOP_MON_SEL_MASK 0x1F
+#define PMIC_AUDIO_SYS_TOP_MON_SEL_SHIFT 8
+#define PMIC_AUDIO_SYS_TOP_MON_SWAP_ADDR \
+ MT6389_AFE_MON_DEBUG0
+#define PMIC_AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
+#define PMIC_AUDIO_SYS_TOP_MON_SWAP_SHIFT 14
+#define PMIC_CCI_SCRAMBLER_EN_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_SCRAMBLER_EN_MASK 0x1
+#define PMIC_CCI_SCRAMBLER_EN_SHIFT 0
+#define PMIC_CCI_AUD_SDM_7BIT_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_SDM_7BIT_SEL_MASK 0x1
+#define PMIC_CCI_AUD_SDM_7BIT_SEL_SHIFT 1
+#define PMIC_CCI_AUD_SDM_MUTER_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_SDM_MUTER_MASK 0x1
+#define PMIC_CCI_AUD_SDM_MUTER_SHIFT 2
+#define PMIC_CCI_AUD_SDM_MUTEL_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_SDM_MUTEL_MASK 0x1
+#define PMIC_CCI_AUD_SDM_MUTEL_SHIFT 3
+#define PMIC_CCI_AUD_SPLIT_TEST_EN_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_SPLIT_TEST_EN_MASK 0x1
+#define PMIC_CCI_AUD_SPLIT_TEST_EN_SHIFT 4
+#define PMIC_CCI_ZERO_PAD_DISABLE_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_ZERO_PAD_DISABLE_MASK 0x1
+#define PMIC_CCI_ZERO_PAD_DISABLE_SHIFT 5
+#define PMIC_CCI_AUD_IDAC_TEST_EN_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_IDAC_TEST_EN_MASK 0x1
+#define PMIC_CCI_AUD_IDAC_TEST_EN_SHIFT 6
+#define PMIC_CCI_SPLT_SCRMB_ON_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_SPLT_SCRMB_ON_MASK 0x1
+#define PMIC_CCI_SPLT_SCRMB_ON_SHIFT 7
+#define PMIC_CCI_SPLT_SCRMB_CLK_ON_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
+#define PMIC_CCI_SPLT_SCRMB_CLK_ON_SHIFT 8
+#define PMIC_CCI_RAND_EN_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_RAND_EN_MASK 0x1
+#define PMIC_CCI_RAND_EN_SHIFT 9
+#define PMIC_CCI_LCH_INV_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_LCH_INV_MASK 0x1
+#define PMIC_CCI_LCH_INV_SHIFT 10
+#define PMIC_CCI_SCRAMBLER_CG_EN_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_SCRAMBLER_CG_EN_MASK 0x1
+#define PMIC_CCI_SCRAMBLER_CG_EN_SHIFT 11
+#define PMIC_CCI_AUDIO_FIFO_WPTR_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUDIO_FIFO_WPTR_MASK 0x7
+#define PMIC_CCI_AUDIO_FIFO_WPTR_SHIFT 12
+#define PMIC_CCI_AUD_ANACK_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON0
+#define PMIC_CCI_AUD_ANACK_SEL_MASK 0x1
+#define PMIC_CCI_AUD_ANACK_SEL_SHIFT 15
+#define PMIC_AUD_SDM_TEST_R_ADDR \
+ MT6389_AFUNC_AUD_CON1
+#define PMIC_AUD_SDM_TEST_R_MASK 0xFF
+#define PMIC_AUD_SDM_TEST_R_SHIFT 0
+#define PMIC_AUD_SDM_TEST_L_ADDR \
+ MT6389_AFUNC_AUD_CON1
+#define PMIC_AUD_SDM_TEST_L_MASK 0xFF
+#define PMIC_AUD_SDM_TEST_L_SHIFT 8
+#define PMIC_CCI_ACD_FUNC_RSTB_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_ACD_FUNC_RSTB_MASK 0x1
+#define PMIC_CCI_ACD_FUNC_RSTB_SHIFT 0
+#define PMIC_CCI_AFIFO_CLK_PWDB_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_AFIFO_CLK_PWDB_MASK 0x1
+#define PMIC_CCI_AFIFO_CLK_PWDB_SHIFT 1
+#define PMIC_CCI_ACD_MODE_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_ACD_MODE_MASK 0x1
+#define PMIC_CCI_ACD_MODE_SHIFT 2
+#define PMIC_CCI_AUDIO_FIFO_ENABLE_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_AUDIO_FIFO_ENABLE_MASK 0x1
+#define PMIC_CCI_AUDIO_FIFO_ENABLE_SHIFT 3
+#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
+#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_SHIFT 4
+#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
+#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_SHIFT 6
+#define PMIC_CCI_AUD_DAC_ANA_MUTE_ADDR \
+ MT6389_AFUNC_AUD_CON2
+#define PMIC_CCI_AUD_DAC_ANA_MUTE_MASK 0x1
+#define PMIC_CCI_AUD_DAC_ANA_MUTE_SHIFT 7
+#define PMIC_DIGMIC_TESTCK_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON3
+#define PMIC_DIGMIC_TESTCK_SEL_MASK 0x1
+#define PMIC_DIGMIC_TESTCK_SEL_SHIFT 0
+#define PMIC_DIGMIC_TESTCK_SRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON3
+#define PMIC_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
+#define PMIC_DIGMIC_TESTCK_SRC_SEL_SHIFT 4
+#define PMIC_SDM_TESTCK_SRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON3
+#define PMIC_SDM_TESTCK_SRC_SEL_MASK 0x7
+#define PMIC_SDM_TESTCK_SRC_SEL_SHIFT 8
+#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON3
+#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
+#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_SHIFT 12
+#define PMIC_SDM_ANA13M_TESTCK_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON3
+#define PMIC_SDM_ANA13M_TESTCK_SEL_MASK 0x1
+#define PMIC_SDM_ANA13M_TESTCK_SEL_SHIFT 15
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SHIFT 0
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
+#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_SHIFT 3
+#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
+#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_SHIFT 4
+#define PMIC_UL_FIFO_WDATA_TESTEN_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_WDATA_TESTEN_MASK 0x1
+#define PMIC_UL_FIFO_WDATA_TESTEN_SHIFT 5
+#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
+#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SHIFT 6
+#define PMIC_UL_FIFO_WCLK_INV_ADDR \
+ MT6389_AFUNC_AUD_CON4
+#define PMIC_UL_FIFO_WCLK_INV_MASK 0x1
+#define PMIC_UL_FIFO_WCLK_INV_SHIFT 8
+#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON5
+#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_MASK 0xFF
+#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_SHIFT 0
+#define PMIC_R_AUD_DAC_POS_LARGE_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON5
+#define PMIC_R_AUD_DAC_POS_LARGE_MONO_MASK 0xFF
+#define PMIC_R_AUD_DAC_POS_LARGE_MONO_SHIFT 8
+#define PMIC_R_AUD_DAC_SGEN_SW_RSTB_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_SGEN_SW_RSTB_MASK 0x1
+#define PMIC_R_AUD_DAC_SGEN_SW_RSTB_SHIFT 0
+#define PMIC_R_AUD_DAC_MONO_SEL_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_MONO_SEL_MASK 0x1
+#define PMIC_R_AUD_DAC_MONO_SEL_SHIFT 3
+#define PMIC_R_AUD_DAC_NEG_TINY_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
+#define PMIC_R_AUD_DAC_NEG_TINY_MONO_SHIFT 4
+#define PMIC_R_AUD_DAC_POS_TINY_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_POS_TINY_MONO_MASK 0x3
+#define PMIC_R_AUD_DAC_POS_TINY_MONO_SHIFT 6
+#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_MASK 0xF
+#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_SHIFT 8
+#define PMIC_R_AUD_DAC_POS_SMALL_MONO_ADDR \
+ MT6389_AFUNC_AUD_CON6
+#define PMIC_R_AUD_DAC_POS_SMALL_MONO_MASK 0xF
+#define PMIC_R_AUD_DAC_POS_SMALL_MONO_SHIFT 12
+#define PMIC_AUD_SCR_OUT_R_ADDR \
+ MT6389_AFUNC_AUD_MON0
+#define PMIC_AUD_SCR_OUT_R_MASK 0xFF
+#define PMIC_AUD_SCR_OUT_R_SHIFT 0
+#define PMIC_AUD_SCR_OUT_L_ADDR \
+ MT6389_AFUNC_AUD_MON0
+#define PMIC_AUD_SCR_OUT_L_MASK 0xFF
+#define PMIC_AUD_SCR_OUT_L_SHIFT 8
+#define PMIC_RGS_AUDRCTUNE0READ_ADDR \
+ MT6389_AUDRC_TUNE_MON0
+#define PMIC_RGS_AUDRCTUNE0READ_MASK 0x1F
+#define PMIC_RGS_AUDRCTUNE0READ_SHIFT 0
+#define PMIC_RGS_AUDRCTUNE1READ_ADDR \
+ MT6389_AUDRC_TUNE_MON0
+#define PMIC_RGS_AUDRCTUNE1READ_MASK 0x1F
+#define PMIC_RGS_AUDRCTUNE1READ_SHIFT 8
+#define PMIC_ASYNC_TEST_OUT_BCK_ADDR \
+ MT6389_AUDRC_TUNE_MON0
+#define PMIC_ASYNC_TEST_OUT_BCK_MASK 0x1
+#define PMIC_ASYNC_TEST_OUT_BCK_SHIFT 15
+#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0
+#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_SHIFT 0
+#define PMIC_AFE_RESERVED_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0
+#define PMIC_AFE_RESERVED_MASK 0x7FFF
+#define PMIC_AFE_RESERVED_SHIFT 1
+#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1
+#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
+#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_SHIFT 0
+#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1
+#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
+#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_SHIFT 1
+#define PMIC_MTKAIF_RXIF_FIFO_STATUS_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON0
+#define PMIC_MTKAIF_RXIF_FIFO_STATUS_MASK 0xFFF
+#define PMIC_MTKAIF_RXIF_FIFO_STATUS_SHIFT 0
+#define PMIC_MTKAIFTX_V3_SDATA_OUT1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON0
+#define PMIC_MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
+#define PMIC_MTKAIFTX_V3_SDATA_OUT1_SHIFT 12
+#define PMIC_MTKAIFTX_V3_SDATA_OUT2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON0
+#define PMIC_MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
+#define PMIC_MTKAIFTX_V3_SDATA_OUT2_SHIFT 13
+#define PMIC_MTKAIFTX_V3_SYNC_OUT_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON0
+#define PMIC_MTKAIFTX_V3_SYNC_OUT_MASK 0x1
+#define PMIC_MTKAIFTX_V3_SYNC_OUT_SHIFT 14
+#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_MASK 0xFF
+#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_SHIFT 0
+#define PMIC_MTKAIF_RXIF_INVALID_FLAG_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
+#define PMIC_MTKAIF_RXIF_INVALID_FLAG_SHIFT 8
+#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
+#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_SHIFT 11
+#define PMIC_MTKAIFRX_V3_SDATA_IN1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIFRX_V3_SDATA_IN1_MASK 0x1
+#define PMIC_MTKAIFRX_V3_SDATA_IN1_SHIFT 12
+#define PMIC_MTKAIFRX_V3_SDATA_IN2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIFRX_V3_SDATA_IN2_MASK 0x1
+#define PMIC_MTKAIFRX_V3_SDATA_IN2_SHIFT 13
+#define PMIC_MTKAIFRX_V3_SYNC_IN_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON1
+#define PMIC_MTKAIFRX_V3_SYNC_IN_MASK 0x1
+#define PMIC_MTKAIFRX_V3_SYNC_IN_SHIFT 14
+#define PMIC_MTKAIF_TXIF_IN_CH1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON2
+#define PMIC_MTKAIF_TXIF_IN_CH1_MASK 0xFF
+#define PMIC_MTKAIF_TXIF_IN_CH1_SHIFT 0
+#define PMIC_MTKAIF_TXIF_IN_CH2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON2
+#define PMIC_MTKAIF_TXIF_IN_CH2_MASK 0xFF
+#define PMIC_MTKAIF_TXIF_IN_CH2_SHIFT 8
+#define PMIC_MTKAIF_RXIF_OUT_CH1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON3
+#define PMIC_MTKAIF_RXIF_OUT_CH1_MASK 0xFF
+#define PMIC_MTKAIF_RXIF_OUT_CH1_SHIFT 0
+#define PMIC_MTKAIF_RXIF_OUT_CH2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_MON3
+#define PMIC_MTKAIF_RXIF_OUT_CH2_MASK 0xFF
+#define PMIC_MTKAIF_RXIF_OUT_CH2_SHIFT 8
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_SHIFT 0
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
+#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_SHIFT 1
+#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
+#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_SHIFT 2
+#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
+#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_SHIFT 4
+#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
+#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_SHIFT 5
+#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
+#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_SHIFT 6
+#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_SHIFT 8
+#define PMIC_RG_MTKAIF_RXIF_CLKINV_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_CFG0
+#define PMIC_RG_MTKAIF_RXIF_CLKINV_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_CLKINV_SHIFT 15
+#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG0
+#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_SHIFT 0
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG0
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_SHIFT 3
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG0
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_SHIFT 4
+#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG0
+#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
+#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_SHIFT 8
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG0
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xF
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_SHIFT 12
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG1
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xF
+#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SHIFT 0
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG1
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xF
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SHIFT 4
+#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG1
+#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xF
+#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SHIFT 8
+#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG1
+#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xF
+#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SHIFT 12
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG2
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xFFF
+#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SHIFT 0
+#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG2
+#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SHIFT 12
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG3
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
+#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SHIFT 3
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_RX_CFG3
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
+#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SHIFT 4
+#define PMIC_RG_MTKAIF_SYNC_WORD1_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_TX_CFG1
+#define PMIC_RG_MTKAIF_SYNC_WORD1_MASK 0x7
+#define PMIC_RG_MTKAIF_SYNC_WORD1_SHIFT 0
+#define PMIC_RG_MTKAIF_SYNC_WORD2_ADDR \
+ MT6389_AFE_ADDA_MTKAIF_TX_CFG1
+#define PMIC_RG_MTKAIF_SYNC_WORD2_MASK 0x7
+#define PMIC_RG_MTKAIF_SYNC_WORD2_SHIFT 4
+#define PMIC_R_AUD_SDM_MUTE_R_ADDR \
+ MT6389_AFE_SGEN_CFG0
+#define PMIC_R_AUD_SDM_MUTE_R_MASK 0x1
+#define PMIC_R_AUD_SDM_MUTE_R_SHIFT 4
+#define PMIC_R_AUD_SDM_MUTE_L_ADDR \
+ MT6389_AFE_SGEN_CFG0
+#define PMIC_R_AUD_SDM_MUTE_L_MASK 0x1
+#define PMIC_R_AUD_SDM_MUTE_L_SHIFT 5
+#define PMIC_C_MUTE_SW_CTL_ADDR \
+ MT6389_AFE_SGEN_CFG0
+#define PMIC_C_MUTE_SW_CTL_MASK 0x1
+#define PMIC_C_MUTE_SW_CTL_SHIFT 6
+#define PMIC_C_DAC_EN_CTL_ADDR \
+ MT6389_AFE_SGEN_CFG0
+#define PMIC_C_DAC_EN_CTL_MASK 0x1
+#define PMIC_C_DAC_EN_CTL_SHIFT 7
+#define PMIC_C_AMP_DIV_CH1_CTL_ADDR \
+ MT6389_AFE_SGEN_CFG0
+#define PMIC_C_AMP_DIV_CH1_CTL_MASK 0xF
+#define PMIC_C_AMP_DIV_CH1_CTL_SHIFT 12
+#define PMIC_C_FREQ_DIV_CH1_CTL_ADDR \
+ MT6389_AFE_SGEN_CFG1
+#define PMIC_C_FREQ_DIV_CH1_CTL_MASK 0x1F
+#define PMIC_C_FREQ_DIV_CH1_CTL_SHIFT 0
+#define PMIC_C_SGEN_RCH_INV_8BIT_ADDR \
+ MT6389_AFE_SGEN_CFG1
+#define PMIC_C_SGEN_RCH_INV_8BIT_MASK 0x1
+#define PMIC_C_SGEN_RCH_INV_8BIT_SHIFT 14
+#define PMIC_C_SGEN_RCH_INV_5BIT_ADDR \
+ MT6389_AFE_SGEN_CFG1
+#define PMIC_C_SGEN_RCH_INV_5BIT_MASK 0x1
+#define PMIC_C_SGEN_RCH_INV_5BIT_SHIFT 15
+#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_ADDR \
+ MT6389_AFE_ADC_ASYNC_FIFO_CFG
+#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
+#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_SHIFT 1
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_ADDR \
+ MT6389_AFE_ADC_ASYNC_FIFO_CFG
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_SHIFT 4
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_ADDR \
+ MT6389_AFE_ADC_ASYNC_FIFO_CFG
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
+#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_SHIFT 5
+#define PMIC_DCCLK_GEN_ON_ADDR \
+ MT6389_AFE_DCCLK_CFG0
+#define PMIC_DCCLK_GEN_ON_MASK 0x1
+#define PMIC_DCCLK_GEN_ON_SHIFT 0
+#define PMIC_DCCLK_PDN_ADDR \
+ MT6389_AFE_DCCLK_CFG0
+#define PMIC_DCCLK_PDN_MASK 0x1
+#define PMIC_DCCLK_PDN_SHIFT 1
+#define PMIC_DCCLK_INV_ADDR \
+ MT6389_AFE_DCCLK_CFG0
+#define PMIC_DCCLK_INV_MASK 0x1
+#define PMIC_DCCLK_INV_SHIFT 4
+#define PMIC_DCCLK_DIV_ADDR \
+ MT6389_AFE_DCCLK_CFG0
+#define PMIC_DCCLK_DIV_MASK 0x7FF
+#define PMIC_DCCLK_DIV_SHIFT 5
+#define PMIC_DCCLK_PHASE_SEL_ADDR \
+ MT6389_AFE_DCCLK_CFG1
+#define PMIC_DCCLK_PHASE_SEL_MASK 0xF
+#define PMIC_DCCLK_PHASE_SEL_SHIFT 4
+#define PMIC_DCCLK_RESYNC_BYPASS_ADDR \
+ MT6389_AFE_DCCLK_CFG1
+#define PMIC_DCCLK_RESYNC_BYPASS_MASK 0x1
+#define PMIC_DCCLK_RESYNC_BYPASS_SHIFT 8
+#define PMIC_RESYNC_SRC_CK_INV_ADDR \
+ MT6389_AFE_DCCLK_CFG1
+#define PMIC_RESYNC_SRC_CK_INV_MASK 0x1
+#define PMIC_RESYNC_SRC_CK_INV_SHIFT 9
+#define PMIC_RESYNC_SRC_SEL_ADDR \
+ MT6389_AFE_DCCLK_CFG1
+#define PMIC_RESYNC_SRC_SEL_MASK 0x3
+#define PMIC_RESYNC_SRC_SEL_SHIFT 10
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_ADDR \
+ MT6389_AUDIO_DIG_CFG
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7F
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_SHIFT 0
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_ADDR \
+ MT6389_AUDIO_DIG_CFG
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SHIFT 7
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_ADDR \
+ MT6389_AUDIO_DIG_CFG
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7F
+#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_SHIFT 8
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_ADDR \
+ MT6389_AUDIO_DIG_CFG
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
+#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SHIFT 15
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_ADDR \
+ MT6389_AFE_AUD_PAD_TOP
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_SHIFT 8
+#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_ADDR \
+ MT6389_AFE_AUD_PAD_TOP
+#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
+#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SHIFT 11
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_ADDR \
+ MT6389_AFE_AUD_PAD_TOP
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
+#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_SHIFT 12
+#define PMIC_ADDA_AUD_PAD_TOP_MON_ADDR \
+ MT6389_AFE_AUD_PAD_TOP_MON
+#define PMIC_ADDA_AUD_PAD_TOP_MON_MASK 0xFFFF
+#define PMIC_ADDA_AUD_PAD_TOP_MON_SHIFT 0
+#define PMIC_ADDA_AUD_PAD_TOP_MON1_ADDR \
+ MT6389_AFE_AUD_PAD_TOP_MON1
+#define PMIC_ADDA_AUD_PAD_TOP_MON1_MASK 0xFFFF
+#define PMIC_ADDA_AUD_PAD_TOP_MON1_SHIFT 0
+#define PMIC_AFE_CG_EN_MON_ADDR \
+ MT6389_AFE_CG_EN_MON
+#define PMIC_AFE_CG_EN_MON_MASK 0x3F
+#define PMIC_AFE_CG_EN_MON_SHIFT 0
+#define PMIC_AUDENC_ANA_ID_ADDR \
+ MT6389_AUDENC_DSN_ID
+#define PMIC_AUDENC_ANA_ID_MASK 0xFF
+#define PMIC_AUDENC_ANA_ID_SHIFT 0
+#define PMIC_AUDENC_DIG_ID_ADDR \
+ MT6389_AUDENC_DSN_ID
+#define PMIC_AUDENC_DIG_ID_MASK 0xFF
+#define PMIC_AUDENC_DIG_ID_SHIFT 8
+#define PMIC_AUDENC_ANA_MINOR_REV_ADDR \
+ MT6389_AUDENC_DSN_REV0
+#define PMIC_AUDENC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUDENC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUDENC_ANA_MAJOR_REV_ADDR \
+ MT6389_AUDENC_DSN_REV0
+#define PMIC_AUDENC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUDENC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUDENC_DIG_MINOR_REV_ADDR \
+ MT6389_AUDENC_DSN_REV0
+#define PMIC_AUDENC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUDENC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUDENC_DIG_MAJOR_REV_ADDR \
+ MT6389_AUDENC_DSN_REV0
+#define PMIC_AUDENC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUDENC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUDENC_DSN_CBS_ADDR \
+ MT6389_AUDENC_DSN_DBI
+#define PMIC_AUDENC_DSN_CBS_MASK 0x3
+#define PMIC_AUDENC_DSN_CBS_SHIFT 0
+#define PMIC_AUDENC_DSN_BIX_ADDR \
+ MT6389_AUDENC_DSN_DBI
+#define PMIC_AUDENC_DSN_BIX_MASK 0x3
+#define PMIC_AUDENC_DSN_BIX_SHIFT 2
+#define PMIC_AUDENC_DSN_ESP_ADDR \
+ MT6389_AUDENC_DSN_DBI
+#define PMIC_AUDENC_DSN_ESP_MASK 0xFF
+#define PMIC_AUDENC_DSN_ESP_SHIFT 8
+#define PMIC_AUDENC_DSN_FPI_ADDR \
+ MT6389_AUDENC_DSN_FPI
+#define PMIC_AUDENC_DSN_FPI_MASK 0xFF
+#define PMIC_AUDENC_DSN_FPI_SHIFT 0
+#define PMIC_RG_AUDPREAMPLON_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLON_MASK 0x1
+#define PMIC_RG_AUDPREAMPLON_SHIFT 0
+#define PMIC_RG_AUDPREAMPLDCCEN_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLDCCEN_MASK 0x1
+#define PMIC_RG_AUDPREAMPLDCCEN_SHIFT 1
+#define PMIC_RG_AUDPREAMPLDCRPECHARGE_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLDCRPECHARGE_MASK 0x1
+#define PMIC_RG_AUDPREAMPLDCRPECHARGE_SHIFT 2
+#define PMIC_RG_AUDPREAMPLPGATEST_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLPGATEST_MASK 0x1
+#define PMIC_RG_AUDPREAMPLPGATEST_SHIFT 3
+#define PMIC_RG_AUDPREAMPLVSCALE_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLVSCALE_MASK 0x3
+#define PMIC_RG_AUDPREAMPLVSCALE_SHIFT 4
+#define PMIC_RG_AUDPREAMPLINPUTSEL_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLINPUTSEL_MASK 0x3
+#define PMIC_RG_AUDPREAMPLINPUTSEL_SHIFT 6
+#define PMIC_RG_AUDPREAMPLGAIN_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLGAIN_MASK 0x7
+#define PMIC_RG_AUDPREAMPLGAIN_SHIFT 8
+#define PMIC_RG_AUDADCLPWRUP_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDADCLPWRUP_MASK 0x1
+#define PMIC_RG_AUDADCLPWRUP_SHIFT 12
+#define PMIC_RG_AUDADCLINPUTSEL_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDADCLINPUTSEL_MASK 0x3
+#define PMIC_RG_AUDADCLINPUTSEL_SHIFT 13
+#define PMIC_RG_AUDPREAMPLSE_ADDR \
+ MT6389_AUDENC_ANA_CON0
+#define PMIC_RG_AUDPREAMPLSE_MASK 0x1
+#define PMIC_RG_AUDPREAMPLSE_SHIFT 15
+#define PMIC_RG_AUDPREAMPRON_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRON_MASK 0x1
+#define PMIC_RG_AUDPREAMPRON_SHIFT 0
+#define PMIC_RG_AUDPREAMPRDCCEN_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRDCCEN_MASK 0x1
+#define PMIC_RG_AUDPREAMPRDCCEN_SHIFT 1
+#define PMIC_RG_AUDPREAMPRDCRPECHARGE_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRDCRPECHARGE_MASK 0x1
+#define PMIC_RG_AUDPREAMPRDCRPECHARGE_SHIFT 2
+#define PMIC_RG_AUDPREAMPRPGATEST_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRPGATEST_MASK 0x1
+#define PMIC_RG_AUDPREAMPRPGATEST_SHIFT 3
+#define PMIC_RG_AUDPREAMPRVSCALE_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRVSCALE_MASK 0x3
+#define PMIC_RG_AUDPREAMPRVSCALE_SHIFT 4
+#define PMIC_RG_AUDPREAMPRINPUTSEL_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRINPUTSEL_MASK 0x3
+#define PMIC_RG_AUDPREAMPRINPUTSEL_SHIFT 6
+#define PMIC_RG_AUDPREAMPRGAIN_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRGAIN_MASK 0x7
+#define PMIC_RG_AUDPREAMPRGAIN_SHIFT 8
+#define PMIC_RG_AUDADCRPWRUP_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDADCRPWRUP_MASK 0x1
+#define PMIC_RG_AUDADCRPWRUP_SHIFT 12
+#define PMIC_RG_AUDADCRINPUTSEL_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDADCRINPUTSEL_MASK 0x3
+#define PMIC_RG_AUDADCRINPUTSEL_SHIFT 13
+#define PMIC_RG_AUDPREAMPRSE_ADDR \
+ MT6389_AUDENC_ANA_CON1
+#define PMIC_RG_AUDPREAMPRSE_MASK 0x1
+#define PMIC_RG_AUDPREAMPRSE_SHIFT 15
+#define PMIC_RG_AUDULHALFBIAS_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDULHALFBIAS_MASK 0x1
+#define PMIC_RG_AUDULHALFBIAS_SHIFT 0
+#define PMIC_RG_AUDGLBMADLPWEN_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDGLBMADLPWEN_MASK 0x1
+#define PMIC_RG_AUDGLBMADLPWEN_SHIFT 1
+#define PMIC_RG_AUDPREAMPLPEN_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDPREAMPLPEN_MASK 0x1
+#define PMIC_RG_AUDPREAMPLPEN_SHIFT 2
+#define PMIC_RG_AUDADC1STSTAGELPEN_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADC1STSTAGELPEN_MASK 0x1
+#define PMIC_RG_AUDADC1STSTAGELPEN_SHIFT 3
+#define PMIC_RG_AUDADC2NDSTAGELPEN_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADC2NDSTAGELPEN_MASK 0x1
+#define PMIC_RG_AUDADC2NDSTAGELPEN_SHIFT 4
+#define PMIC_RG_AUDADCFLASHLPEN_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADCFLASHLPEN_MASK 0x1
+#define PMIC_RG_AUDADCFLASHLPEN_SHIFT 5
+#define PMIC_RG_AUDPREAMPIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDPREAMPIDDTEST_MASK 0x3
+#define PMIC_RG_AUDPREAMPIDDTEST_SHIFT 6
+#define PMIC_RG_AUDADC1STSTAGEIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
+#define PMIC_RG_AUDADC1STSTAGEIDDTEST_SHIFT 8
+#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
+#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 10
+#define PMIC_RG_AUDADCREFBUFIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADCREFBUFIDDTEST_MASK 0x3
+#define PMIC_RG_AUDADCREFBUFIDDTEST_SHIFT 12
+#define PMIC_RG_AUDADCFLASHIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON2
+#define PMIC_RG_AUDADCFLASHIDDTEST_MASK 0x3
+#define PMIC_RG_AUDADCFLASHIDDTEST_SHIFT 14
+#define PMIC_RG_AUDADCDAC0P25FS_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_AUDADCDAC0P25FS_MASK 0x1
+#define PMIC_RG_AUDADCDAC0P25FS_SHIFT 0
+#define PMIC_RG_AUDADCCLKSEL_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_AUDADCCLKSEL_MASK 0x1
+#define PMIC_RG_AUDADCCLKSEL_SHIFT 1
+#define PMIC_RG_AUDADCCLKSOURCE_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_AUDADCCLKSOURCE_MASK 0x3
+#define PMIC_RG_AUDADCCLKSOURCE_SHIFT 2
+#define PMIC_RG_AUDPREAMPAAFEN_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_AUDPREAMPAAFEN_MASK 0x1
+#define PMIC_RG_AUDPREAMPAAFEN_SHIFT 8
+#define PMIC_RG_DCCVCMBUFLPMODSEL_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_DCCVCMBUFLPMODSEL_MASK 0x1
+#define PMIC_RG_DCCVCMBUFLPMODSEL_SHIFT 9
+#define PMIC_RG_DCCVCMBUFLPSWEN_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_DCCVCMBUFLPSWEN_MASK 0x1
+#define PMIC_RG_DCCVCMBUFLPSWEN_SHIFT 10
+#define PMIC_RG_AUDSPAREPGA_ADDR \
+ MT6389_AUDENC_ANA_CON3
+#define PMIC_RG_AUDSPAREPGA_MASK 0x1
+#define PMIC_RG_AUDSPAREPGA_SHIFT 11
+#define PMIC_RG_AUDADC1STSTAGESDENB_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADC1STSTAGESDENB_MASK 0x1
+#define PMIC_RG_AUDADC1STSTAGESDENB_SHIFT 0
+#define PMIC_RG_AUDADC2NDSTAGERESET_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADC2NDSTAGERESET_MASK 0x1
+#define PMIC_RG_AUDADC2NDSTAGERESET_SHIFT 1
+#define PMIC_RG_AUDADC3RDSTAGERESET_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADC3RDSTAGERESET_MASK 0x1
+#define PMIC_RG_AUDADC3RDSTAGERESET_SHIFT 2
+#define PMIC_RG_AUDADCFSRESET_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCFSRESET_MASK 0x1
+#define PMIC_RG_AUDADCFSRESET_SHIFT 3
+#define PMIC_RG_AUDADCWIDECM_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCWIDECM_MASK 0x1
+#define PMIC_RG_AUDADCWIDECM_SHIFT 4
+#define PMIC_RG_AUDADCNOPATEST_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCNOPATEST_MASK 0x1
+#define PMIC_RG_AUDADCNOPATEST_SHIFT 5
+#define PMIC_RG_AUDADCBYPASS_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCBYPASS_MASK 0x1
+#define PMIC_RG_AUDADCBYPASS_SHIFT 6
+#define PMIC_RG_AUDADCFFBYPASS_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCFFBYPASS_MASK 0x1
+#define PMIC_RG_AUDADCFFBYPASS_SHIFT 7
+#define PMIC_RG_AUDADCDACFBCURRENT_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCDACFBCURRENT_MASK 0x1
+#define PMIC_RG_AUDADCDACFBCURRENT_SHIFT 8
+#define PMIC_RG_AUDADCDACIDDTEST_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCDACIDDTEST_MASK 0x3
+#define PMIC_RG_AUDADCDACIDDTEST_SHIFT 9
+#define PMIC_RG_AUDADCDACNRZ_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCDACNRZ_MASK 0x1
+#define PMIC_RG_AUDADCDACNRZ_SHIFT 11
+#define PMIC_RG_AUDADCNODEM_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCNODEM_MASK 0x1
+#define PMIC_RG_AUDADCNODEM_SHIFT 12
+#define PMIC_RG_AUDADCDACTEST_ADDR \
+ MT6389_AUDENC_ANA_CON4
+#define PMIC_RG_AUDADCDACTEST_MASK 0x1
+#define PMIC_RG_AUDADCDACTEST_SHIFT 13
+#define PMIC_RG_CLKSQ_EN_ADDR \
+ MT6389_AUDENC_ANA_CON5
+#define PMIC_RG_CLKSQ_EN_MASK 0x1
+#define PMIC_RG_CLKSQ_EN_SHIFT 0
+#define PMIC_RG_CLKSQ_IN_SEL_ADDR \
+ MT6389_AUDENC_ANA_CON5
+#define PMIC_RG_CLKSQ_IN_SEL_MASK 0x1
+#define PMIC_RG_CLKSQ_IN_SEL_SHIFT 1
+#define PMIC_RG_AUDSPARE2VA28_ADDR \
+ MT6389_AUDENC_ANA_CON5
+#define PMIC_RG_AUDSPARE2VA28_MASK 0x3FFF
+#define PMIC_RG_AUDSPARE2VA28_SHIFT 2
+#define PMIC_RG_AUDRCTUNEL_ADDR \
+ MT6389_AUDENC_ANA_CON6
+#define PMIC_RG_AUDRCTUNEL_MASK 0x1F
+#define PMIC_RG_AUDRCTUNEL_SHIFT 0
+#define PMIC_RG_AUDRCTUNELSEL_ADDR \
+ MT6389_AUDENC_ANA_CON6
+#define PMIC_RG_AUDRCTUNELSEL_MASK 0x1
+#define PMIC_RG_AUDRCTUNELSEL_SHIFT 5
+#define PMIC_RG_AUDRCTUNER_ADDR \
+ MT6389_AUDENC_ANA_CON6
+#define PMIC_RG_AUDRCTUNER_MASK 0x1F
+#define PMIC_RG_AUDRCTUNER_SHIFT 8
+#define PMIC_RG_AUDRCTUNERSEL_ADDR \
+ MT6389_AUDENC_ANA_CON6
+#define PMIC_RG_AUDRCTUNERSEL_MASK 0x1
+#define PMIC_RG_AUDRCTUNERSEL_SHIFT 13
+#define PMIC_RG_AUDSPAREVA28_ADDR \
+ MT6389_AUDENC_ANA_CON7
+#define PMIC_RG_AUDSPAREVA28_MASK 0xF
+#define PMIC_RG_AUDSPAREVA28_SHIFT 0
+#define PMIC_RG_AUDSPAREVA18_ADDR \
+ MT6389_AUDENC_ANA_CON7
+#define PMIC_RG_AUDSPAREVA18_MASK 0xF
+#define PMIC_RG_AUDSPAREVA18_SHIFT 4
+#define PMIC_RG_AUDENCSPAREVA28_ADDR \
+ MT6389_AUDENC_ANA_CON7
+#define PMIC_RG_AUDENCSPAREVA28_MASK 0xF
+#define PMIC_RG_AUDENCSPAREVA28_SHIFT 8
+#define PMIC_RG_AUDENCSPAREVA18_ADDR \
+ MT6389_AUDENC_ANA_CON7
+#define PMIC_RG_AUDENCSPAREVA18_MASK 0xF
+#define PMIC_RG_AUDENCSPAREVA18_SHIFT 12
+#define PMIC_RG_AUDDIGMICEN_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_AUDDIGMICEN_MASK 0x1
+#define PMIC_RG_AUDDIGMICEN_SHIFT 0
+#define PMIC_RG_AUDDIGMICBIAS_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_AUDDIGMICBIAS_MASK 0x3
+#define PMIC_RG_AUDDIGMICBIAS_SHIFT 1
+#define PMIC_RG_DMICHPCLKEN_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_DMICHPCLKEN_MASK 0x1
+#define PMIC_RG_DMICHPCLKEN_SHIFT 3
+#define PMIC_RG_AUDDIGMICPDUTY_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_AUDDIGMICPDUTY_MASK 0x3
+#define PMIC_RG_AUDDIGMICPDUTY_SHIFT 4
+#define PMIC_RG_AUDDIGMICNDUTY_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_AUDDIGMICNDUTY_MASK 0x3
+#define PMIC_RG_AUDDIGMICNDUTY_SHIFT 6
+#define PMIC_RG_DMICMONEN_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_DMICMONEN_MASK 0x1
+#define PMIC_RG_DMICMONEN_SHIFT 8
+#define PMIC_RG_DMICMONSEL_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_DMICMONSEL_MASK 0x7
+#define PMIC_RG_DMICMONSEL_SHIFT 9
+#define PMIC_RG_AUDSPAREVMIC_ADDR \
+ MT6389_AUDENC_ANA_CON8
+#define PMIC_RG_AUDSPAREVMIC_MASK 0xF
+#define PMIC_RG_AUDSPAREVMIC_SHIFT 12
+#define PMIC_RG_AUDPWDBMICBIAS0_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDPWDBMICBIAS0_MASK 0x1
+#define PMIC_RG_AUDPWDBMICBIAS0_SHIFT 0
+#define PMIC_RG_AUDMICBIAS0BYPASSEN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0BYPASSEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0BYPASSEN_SHIFT 1
+#define PMIC_RG_AUDMICBIAS0LOWPEN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0LOWPEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0LOWPEN_SHIFT 2
+#define PMIC_RG_AUDMICBIAS0VREF_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0VREF_MASK 0x7
+#define PMIC_RG_AUDMICBIAS0VREF_SHIFT 4
+#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_SHIFT 8
+#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_SHIFT 9
+#define PMIC_RG_AUDMICBIAS0DCSW0NEN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW0NEN_SHIFT 10
+#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_SHIFT 12
+#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_SHIFT 13
+#define PMIC_RG_AUDMICBIAS0DCSW2NEN_ADDR \
+ MT6389_AUDENC_ANA_CON9
+#define PMIC_RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS0DCSW2NEN_SHIFT 14
+#define PMIC_RG_AUDPWDBMICBIAS1_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDPWDBMICBIAS1_MASK 0x1
+#define PMIC_RG_AUDPWDBMICBIAS1_SHIFT 0
+#define PMIC_RG_AUDMICBIAS1BYPASSEN_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDMICBIAS1BYPASSEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS1BYPASSEN_SHIFT 1
+#define PMIC_RG_AUDMICBIAS1LOWPEN_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDMICBIAS1LOWPEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2
+#define PMIC_RG_AUDMICBIAS1VREF_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDMICBIAS1VREF_MASK 0x7
+#define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4
+#define PMIC_RG_AUDMICBIAS1DCSW1PEN_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT 8
+#define PMIC_RG_AUDMICBIAS1DCSW1NEN_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
+#define PMIC_RG_AUDMICBIAS1DCSW1NEN_SHIFT 9
+#define PMIC_RG_BANDGAPGEN_ADDR \
+ MT6389_AUDENC_ANA_CON10
+#define PMIC_RG_BANDGAPGEN_MASK 0x1
+#define PMIC_RG_BANDGAPGEN_SHIFT 12
+#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
+#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT 0
+#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
+#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT 1
+#define PMIC_RG_AUDACCDETVIN1PULLLOW_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETVIN1PULLLOW_MASK 0x1
+#define PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT 2
+#define PMIC_RG_AUDACCDETVTHACAL_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETVTHACAL_MASK 0x1
+#define PMIC_RG_AUDACCDETVTHACAL_SHIFT 4
+#define PMIC_RG_AUDACCDETVTHBCAL_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETVTHBCAL_MASK 0x1
+#define PMIC_RG_AUDACCDETVTHBCAL_SHIFT 5
+#define PMIC_RG_AUDACCDETTVDET_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_AUDACCDETTVDET_MASK 0x1
+#define PMIC_RG_AUDACCDETTVDET_SHIFT 6
+#define PMIC_RG_ACCDETSEL_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_ACCDETSEL_MASK 0x1
+#define PMIC_RG_ACCDETSEL_SHIFT 7
+#define PMIC_RG_SWBUFMODSEL_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_SWBUFMODSEL_MASK 0x1
+#define PMIC_RG_SWBUFMODSEL_SHIFT 8
+#define PMIC_RG_SWBUFSWEN_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_SWBUFSWEN_MASK 0x1
+#define PMIC_RG_SWBUFSWEN_SHIFT 9
+#define PMIC_RG_EINTCOMPVTH_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_EINTCOMPVTH_MASK 0x1
+#define PMIC_RG_EINTCOMPVTH_SHIFT 10
+#define PMIC_RG_EINTCONFIGACCDET_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_EINTCONFIGACCDET_MASK 0x1
+#define PMIC_RG_EINTCONFIGACCDET_SHIFT 11
+#define PMIC_RG_EINTHIRENB_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_EINTHIRENB_MASK 0x1
+#define PMIC_RG_EINTHIRENB_SHIFT 12
+#define PMIC_RG_ACCDETSPAREVA28_ADDR \
+ MT6389_AUDENC_ANA_CON11
+#define PMIC_RG_ACCDETSPAREVA28_MASK 0x7
+#define PMIC_RG_ACCDETSPAREVA28_SHIFT 13
+#define PMIC_RGS_AUDRCTUNELREAD_ADDR \
+ MT6389_AUDENC_ANA_CON12
+#define PMIC_RGS_AUDRCTUNELREAD_MASK 0x1F
+#define PMIC_RGS_AUDRCTUNELREAD_SHIFT 0
+#define PMIC_RGS_AUDRCTUNERREAD_ADDR \
+ MT6389_AUDENC_ANA_CON12
+#define PMIC_RGS_AUDRCTUNERREAD_MASK 0x1F
+#define PMIC_RGS_AUDRCTUNERREAD_SHIFT 8
+#define PMIC_AUDDEC_ANA_ID_ADDR \
+ MT6389_AUDDEC_DSN_ID
+#define PMIC_AUDDEC_ANA_ID_MASK 0xFF
+#define PMIC_AUDDEC_ANA_ID_SHIFT 0
+#define PMIC_AUDDEC_DIG_ID_ADDR \
+ MT6389_AUDDEC_DSN_ID
+#define PMIC_AUDDEC_DIG_ID_MASK 0xFF
+#define PMIC_AUDDEC_DIG_ID_SHIFT 8
+#define PMIC_AUDDEC_ANA_MINOR_REV_ADDR \
+ MT6389_AUDDEC_DSN_REV0
+#define PMIC_AUDDEC_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUDDEC_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUDDEC_ANA_MAJOR_REV_ADDR \
+ MT6389_AUDDEC_DSN_REV0
+#define PMIC_AUDDEC_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUDDEC_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUDDEC_DIG_MINOR_REV_ADDR \
+ MT6389_AUDDEC_DSN_REV0
+#define PMIC_AUDDEC_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUDDEC_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUDDEC_DIG_MAJOR_REV_ADDR \
+ MT6389_AUDDEC_DSN_REV0
+#define PMIC_AUDDEC_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUDDEC_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUDDEC_DSN_CBS_ADDR \
+ MT6389_AUDDEC_DSN_DBI
+#define PMIC_AUDDEC_DSN_CBS_MASK 0x3
+#define PMIC_AUDDEC_DSN_CBS_SHIFT 0
+#define PMIC_AUDDEC_DSN_BIX_ADDR \
+ MT6389_AUDDEC_DSN_DBI
+#define PMIC_AUDDEC_DSN_BIX_MASK 0x3
+#define PMIC_AUDDEC_DSN_BIX_SHIFT 2
+#define PMIC_AUDDEC_DSN_ESP_ADDR \
+ MT6389_AUDDEC_DSN_DBI
+#define PMIC_AUDDEC_DSN_ESP_MASK 0xFF
+#define PMIC_AUDDEC_DSN_ESP_SHIFT 8
+#define PMIC_AUDDEC_DSN_FPI_ADDR \
+ MT6389_AUDDEC_DSN_FPI
+#define PMIC_AUDDEC_DSN_FPI_MASK 0xFF
+#define PMIC_AUDDEC_DSN_FPI_SHIFT 0
+#define PMIC_RG_AUDDACLPWRUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDDACLPWRUP_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDDACRPWRUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDDACRPWRUP_VAUDP15_SHIFT 1
+#define PMIC_RG_AUD_DAC_PWR_UP_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
+#define PMIC_RG_AUD_DAC_PWR_UP_VA28_SHIFT 2
+#define PMIC_RG_AUD_DAC_PWL_UP_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
+#define PMIC_RG_AUD_DAC_PWL_UP_VA28_SHIFT 3
+#define PMIC_RG_AUDOUT0_MUX_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUDOUT0_MUX_VAUDP28_MASK 0x7
+#define PMIC_RG_AUDOUT0_MUX_VAUDP28_SHIFT 4
+#define PMIC_RG_AUDOUT1_MUX_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUDOUT1_MUX_VAUDP28_MASK 0x7
+#define PMIC_RG_AUDOUT1_MUX_VAUDP28_SHIFT 8
+#define PMIC_RG_AUDOUT2_MUX_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON0
+#define PMIC_RG_AUDOUT2_MUX_VAUDP28_MASK 0x7
+#define PMIC_RG_AUDOUT2_MUX_VAUDP28_SHIFT 12
+#define PMIC_RG_AUDVCMBUF_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCMBUF_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCMBUF_EN_VAUDP28_SHIFT 0
+#define PMIC_RG_AUDVCMBUF_VOSEL_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCMBUF_VOSEL_VAUDP28_MASK 0x7
+#define PMIC_RG_AUDVCMBUF_VOSEL_VAUDP28_SHIFT 4
+#define PMIC_RG_AUDVCM2OUT0P_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT0P_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT0P_SW_EN_VAUDP28_SHIFT 8
+#define PMIC_RG_AUDVCM2OUT0N_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT0N_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT0N_SW_EN_VAUDP28_SHIFT 9
+#define PMIC_RG_AUDVCM2OUT1P_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT1P_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT1P_SW_EN_VAUDP28_SHIFT 10
+#define PMIC_RG_AUDVCM2OUT1N_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT1N_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT1N_SW_EN_VAUDP28_SHIFT 11
+#define PMIC_RG_AUDVCM2OUT2P_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT2P_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT2P_SW_EN_VAUDP28_SHIFT 12
+#define PMIC_RG_AUDVCM2OUT2N_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON1
+#define PMIC_RG_AUDVCM2OUT2N_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2OUT2N_SW_EN_VAUDP28_SHIFT 13
+#define PMIC_RG_AUDVCM2VIN0P_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_AUDVCM2VIN0P_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2VIN0P_SW_EN_VAUDP28_SHIFT 0
+#define PMIC_RG_AUDVCM2VIN0N_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_AUDVCM2VIN0N_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2VIN0N_SW_EN_VAUDP28_SHIFT 1
+#define PMIC_RG_AUDVCM2VIN1P_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_AUDVCM2VIN1P_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2VIN1P_SW_EN_VAUDP28_SHIFT 2
+#define PMIC_RG_AUDVCM2VIN1N_SW_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_AUDVCM2VIN1N_SW_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDVCM2VIN1N_SW_EN_VAUDP28_SHIFT 3
+#define PMIC_RG_AUDREFN_DERES_EN_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_AUDREFN_DERES_EN_VAUDP28_MASK 0x1
+#define PMIC_RG_AUDREFN_DERES_EN_VAUDP28_SHIFT 4
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON2
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_SHIFT 8
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON3
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP28_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP28_SHIFT 0
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP28_ADDR \
+ MT6389_AUDDEC_ANA_CON3
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP28_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP28_SHIFT 8
+#define PMIC_RG_AUDHSPWRUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSPWRUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSPWRUP_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_SHIFT 1
+#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT 2
+#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_SHIFT 4
+#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT 5
+#define PMIC_RG_AUDHSSTARTUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSSTARTUP_VAUDP15_SHIFT 6
+#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT 7
+#define PMIC_RG_HSINPUTSTBENH_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
+#define PMIC_RG_HSINPUTSTBENH_VAUDP15_SHIFT 8
+#define PMIC_RG_HSINPUTRESET0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_HSINPUTRESET0_VAUDP15_MASK 0x1
+#define PMIC_RG_HSINPUTRESET0_VAUDP15_SHIFT 9
+#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
+#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_SHIFT 10
+#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON4
+#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT 11
+#define PMIC_RG_AUDLOLPWRUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOLPWRUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOLPWRUP_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_SHIFT 1
+#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_SHIFT 2
+#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_SHIFT 4
+#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_SHIFT 5
+#define PMIC_RG_AUDLOSTARTUP_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_AUDLOSTARTUP_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOSTARTUP_VAUDP15_SHIFT 6
+#define PMIC_RG_LOINPUTSTBENH_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_LOINPUTSTBENH_VAUDP15_MASK 0x1
+#define PMIC_RG_LOINPUTSTBENH_VAUDP15_SHIFT 7
+#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_SHIFT 8
+#define PMIC_RG_LOINPUTRESET0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_LOINPUTRESET0_VAUDP15_MASK 0x1
+#define PMIC_RG_LOINPUTRESET0_VAUDP15_SHIFT 9
+#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1
+#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_SHIFT 10
+#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON5
+#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_SHIFT 11
+#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xF
+#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT 4
+#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT 6
+#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT 8
+#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT 10
+#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON6
+#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT 12
+#define PMIC_RG_ABIDEC_RSVD0_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON7
+#define PMIC_RG_ABIDEC_RSVD0_VA28_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD0_VA28_SHIFT 0
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON7
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_SHIFT 8
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON8
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_SHIFT 0
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON8
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_MASK 0xFF
+#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_SHIFT 8
+#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON9
+#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7
+#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON9
+#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_SHIFT 3
+#define PMIC_RG_AUDBIASADJ_0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON9
+#define PMIC_RG_AUDBIASADJ_0_VAUDP15_MASK 0x1FF
+#define PMIC_RG_AUDBIASADJ_0_VAUDP15_SHIFT 7
+#define PMIC_RG_AUDBIASADJ_1_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON10
+#define PMIC_RG_AUDBIASADJ_1_VAUDP15_MASK 0xFF
+#define PMIC_RG_AUDBIASADJ_1_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON10
+#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_SHIFT 8
+#define PMIC_RG_RSTB_DECODER_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_RSTB_DECODER_VA28_MASK 0x1
+#define PMIC_RG_RSTB_DECODER_VA28_SHIFT 0
+#define PMIC_RG_SEL_DECODER_96K_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_SEL_DECODER_96K_VA28_MASK 0x1
+#define PMIC_RG_SEL_DECODER_96K_VA28_SHIFT 1
+#define PMIC_RG_SEL_DELAY_VCORE_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_SEL_DELAY_VCORE_MASK 0x1
+#define PMIC_RG_SEL_DELAY_VCORE_SHIFT 2
+#define PMIC_RG_AUDGLB_PWRDN_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_AUDGLB_PWRDN_VA28_MASK 0x1
+#define PMIC_RG_AUDGLB_PWRDN_VA28_SHIFT 4
+#define PMIC_RG_RSTB_ENCODER_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_RSTB_ENCODER_VA28_MASK 0x1
+#define PMIC_RG_RSTB_ENCODER_VA28_SHIFT 5
+#define PMIC_RG_SEL_ENCODER_96K_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON11
+#define PMIC_RG_SEL_ENCODER_96K_VA28_MASK 0x1
+#define PMIC_RG_SEL_ENCODER_96K_VA28_SHIFT 6
+#define PMIC_RG_HCLDO_EN_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_HCLDO_EN_VA18_MASK 0x1
+#define PMIC_RG_HCLDO_EN_VA18_SHIFT 0
+#define PMIC_RG_HCLDO_PDDIS_EN_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
+#define PMIC_RG_HCLDO_PDDIS_EN_VA18_SHIFT 1
+#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT 2
+#define PMIC_RG_LCLDO_EN_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_EN_VA18_MASK 0x1
+#define PMIC_RG_LCLDO_EN_VA18_SHIFT 4
+#define PMIC_RG_LCLDO_PDDIS_EN_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
+#define PMIC_RG_LCLDO_PDDIS_EN_VA18_SHIFT 5
+#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT 6
+#define PMIC_RG_LCLDO_ENC_EN_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_ENC_EN_VA28_MASK 0x1
+#define PMIC_RG_LCLDO_ENC_EN_VA28_SHIFT 8
+#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
+#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 9
+#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
+#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 10
+#define PMIC_RG_VA33REFGEN_EN_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_VA33REFGEN_EN_VA18_MASK 0x1
+#define PMIC_RG_VA33REFGEN_EN_VA18_SHIFT 12
+#define PMIC_RG_VA28REFGEN_EN_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_VA28REFGEN_EN_VA28_MASK 0x1
+#define PMIC_RG_VA28REFGEN_EN_VA28_SHIFT 13
+#define PMIC_RG_HCLDO_VOSEL_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_HCLDO_VOSEL_VA18_MASK 0x1
+#define PMIC_RG_HCLDO_VOSEL_VA18_SHIFT 14
+#define PMIC_RG_LCLDO_VOSEL_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON12
+#define PMIC_RG_LCLDO_VOSEL_VA18_MASK 0x1
+#define PMIC_RG_LCLDO_VOSEL_VA18_SHIFT 15
+#define PMIC_RG_NVREG_EN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON13
+#define PMIC_RG_NVREG_EN_VAUDP15_MASK 0x1
+#define PMIC_RG_NVREG_EN_VAUDP15_SHIFT 0
+#define PMIC_RG_NVREG_PULL0V_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON13
+#define PMIC_RG_NVREG_PULL0V_VAUDP15_MASK 0x1
+#define PMIC_RG_NVREG_PULL0V_VAUDP15_SHIFT 1
+#define PMIC_RG_AUDPMU_RSD0_VAUDP15_ADDR \
+ MT6389_AUDDEC_ANA_CON13
+#define PMIC_RG_AUDPMU_RSD0_VAUDP15_MASK 0xF
+#define PMIC_RG_AUDPMU_RSD0_VAUDP15_SHIFT 4
+#define PMIC_RG_AUDPMU_RSD0_VA18_ADDR \
+ MT6389_AUDDEC_ANA_CON13
+#define PMIC_RG_AUDPMU_RSD0_VA18_MASK 0xF
+#define PMIC_RG_AUDPMU_RSD0_VA18_SHIFT 8
+#define PMIC_RG_AUDPMU_RSD0_VA28_ADDR \
+ MT6389_AUDDEC_ANA_CON13
+#define PMIC_RG_AUDPMU_RSD0_VA28_MASK 0xF
+#define PMIC_RG_AUDPMU_RSD0_VA28_SHIFT 12
+#define PMIC_AUDDEC_ELR_LEN_ADDR \
+ MT6389_AUDDEC_ELR_NUM
+#define PMIC_AUDDEC_ELR_LEN_MASK 0xFF
+#define PMIC_AUDDEC_ELR_LEN_SHIFT 0
+#define PMIC_RG_AUDHSTRIM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDHSTRIM_VAUDP15_MASK 0xF
+#define PMIC_RG_AUDHSTRIM_VAUDP15_SHIFT 0
+#define PMIC_RG_AUDHSFINETRIM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDHSFINETRIM_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDHSFINETRIM_VAUDP15_SHIFT 4
+#define PMIC_RG_AUDHSTRIM_EN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDHSTRIM_EN_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDHSTRIM_EN_VAUDP15_SHIFT 6
+#define PMIC_RG_AUDLOLTRIM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDLOLTRIM_VAUDP15_MASK 0xF
+#define PMIC_RG_AUDLOLTRIM_VAUDP15_SHIFT 7
+#define PMIC_RG_AUDLOLFINETRIM_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDLOLFINETRIM_VAUDP15_MASK 0x3
+#define PMIC_RG_AUDLOLFINETRIM_VAUDP15_SHIFT 11
+#define PMIC_RG_AUDLOLTRIM_EN_VAUDP15_ADDR \
+ MT6389_AUDDEC_ELR_0
+#define PMIC_RG_AUDLOLTRIM_EN_VAUDP15_MASK 0x1
+#define PMIC_RG_AUDLOLTRIM_EN_VAUDP15_SHIFT 13
+#define PMIC_AUDZCD_ANA_ID_ADDR \
+ MT6389_AUDZCD_DSN_ID
+#define PMIC_AUDZCD_ANA_ID_MASK 0xFF
+#define PMIC_AUDZCD_ANA_ID_SHIFT 0
+#define PMIC_AUDZCD_DIG_ID_ADDR \
+ MT6389_AUDZCD_DSN_ID
+#define PMIC_AUDZCD_DIG_ID_MASK 0xFF
+#define PMIC_AUDZCD_DIG_ID_SHIFT 8
+#define PMIC_AUDZCD_ANA_MINOR_REV_ADDR \
+ MT6389_AUDZCD_DSN_REV0
+#define PMIC_AUDZCD_ANA_MINOR_REV_MASK 0xF
+#define PMIC_AUDZCD_ANA_MINOR_REV_SHIFT 0
+#define PMIC_AUDZCD_ANA_MAJOR_REV_ADDR \
+ MT6389_AUDZCD_DSN_REV0
+#define PMIC_AUDZCD_ANA_MAJOR_REV_MASK 0xF
+#define PMIC_AUDZCD_ANA_MAJOR_REV_SHIFT 4
+#define PMIC_AUDZCD_DIG_MINOR_REV_ADDR \
+ MT6389_AUDZCD_DSN_REV0
+#define PMIC_AUDZCD_DIG_MINOR_REV_MASK 0xF
+#define PMIC_AUDZCD_DIG_MINOR_REV_SHIFT 8
+#define PMIC_AUDZCD_DIG_MAJOR_REV_ADDR \
+ MT6389_AUDZCD_DSN_REV0
+#define PMIC_AUDZCD_DIG_MAJOR_REV_MASK 0xF
+#define PMIC_AUDZCD_DIG_MAJOR_REV_SHIFT 12
+#define PMIC_AUDZCD_DSN_CBS_ADDR \
+ MT6389_AUDZCD_DSN_DBI
+#define PMIC_AUDZCD_DSN_CBS_MASK 0x3
+#define PMIC_AUDZCD_DSN_CBS_SHIFT 0
+#define PMIC_AUDZCD_DSN_BIX_ADDR \
+ MT6389_AUDZCD_DSN_DBI
+#define PMIC_AUDZCD_DSN_BIX_MASK 0x3
+#define PMIC_AUDZCD_DSN_BIX_SHIFT 2
+#define PMIC_AUDZCD_DSN_ESP_ADDR \
+ MT6389_AUDZCD_DSN_DBI
+#define PMIC_AUDZCD_DSN_ESP_MASK 0xFF
+#define PMIC_AUDZCD_DSN_ESP_SHIFT 8
+#define PMIC_AUDZCD_DSN_FPI_ADDR \
+ MT6389_AUDZCD_DSN_FPI
+#define PMIC_AUDZCD_DSN_FPI_MASK 0xFF
+#define PMIC_AUDZCD_DSN_FPI_SHIFT 0
+#define PMIC_RG_AUDZCDENABLE_ADDR \
+ MT6389_ZCD_CON0
+#define PMIC_RG_AUDZCDENABLE_MASK 0x1
+#define PMIC_RG_AUDZCDENABLE_SHIFT 0
+#define PMIC_RG_AUDZCDGAINSTEPTIME_ADDR \
+ MT6389_ZCD_CON0
+#define PMIC_RG_AUDZCDGAINSTEPTIME_MASK 0x7
+#define PMIC_RG_AUDZCDGAINSTEPTIME_SHIFT 1
+#define PMIC_RG_AUDZCDGAINSTEPSIZE_ADDR \
+ MT6389_ZCD_CON0
+#define PMIC_RG_AUDZCDGAINSTEPSIZE_MASK 0x3
+#define PMIC_RG_AUDZCDGAINSTEPSIZE_SHIFT 4
+#define PMIC_RG_AUDZCDTIMEOUTMODESEL_ADDR \
+ MT6389_ZCD_CON0
+#define PMIC_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
+#define PMIC_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6
+#define PMIC_RG_AUDLOLGAIN_ADDR \
+ MT6389_ZCD_CON1
+#define PMIC_RG_AUDLOLGAIN_MASK 0x1F
+#define PMIC_RG_AUDLOLGAIN_SHIFT 0
+#define PMIC_RG_AUDLORGAIN_ADDR \
+ MT6389_ZCD_CON1
+#define PMIC_RG_AUDLORGAIN_MASK 0x1F
+#define PMIC_RG_AUDLORGAIN_SHIFT 7
+#define PMIC_RG_AUDHPLGAIN_ADDR \
+ MT6389_ZCD_CON2
+#define PMIC_RG_AUDHPLGAIN_MASK 0x1F
+#define PMIC_RG_AUDHPLGAIN_SHIFT 0
+#define PMIC_RG_AUDHPRGAIN_ADDR \
+ MT6389_ZCD_CON2
+#define PMIC_RG_AUDHPRGAIN_MASK 0x1F
+#define PMIC_RG_AUDHPRGAIN_SHIFT 7
+#define PMIC_RG_AUDHSGAIN_ADDR \
+ MT6389_ZCD_CON3
+#define PMIC_RG_AUDHSGAIN_MASK 0x1F
+#define PMIC_RG_AUDHSGAIN_SHIFT 0
+#define PMIC_RG_AUDIVLGAIN_ADDR \
+ MT6389_ZCD_CON4
+#define PMIC_RG_AUDIVLGAIN_MASK 0x7
+#define PMIC_RG_AUDIVLGAIN_SHIFT 0
+#define PMIC_RG_AUDIVRGAIN_ADDR \
+ MT6389_ZCD_CON4
+#define PMIC_RG_AUDIVRGAIN_MASK 0x7
+#define PMIC_RG_AUDIVRGAIN_SHIFT 8
+#define PMIC_RG_AUDINTGAIN1_ADDR \
+ MT6389_ZCD_CON5
+#define PMIC_RG_AUDINTGAIN1_MASK 0x3F
+#define PMIC_RG_AUDINTGAIN1_SHIFT 0
+#define PMIC_RG_AUDINTGAIN2_ADDR \
+ MT6389_ZCD_CON5
+#define PMIC_RG_AUDINTGAIN2_MASK 0x3F
+#define PMIC_RG_AUDINTGAIN2_SHIFT 8
+
+enum PMU_FLAGS_LIST {
+ PMIC_TOP0_ANA_ID,
+ PMIC_TOP0_DIG_ID,
+ PMIC_TOP0_ANA_MINOR_REV,
+ PMIC_TOP0_ANA_MAJOR_REV,
+ PMIC_TOP0_DIG_MINOR_REV,
+ PMIC_TOP0_DIG_MAJOR_REV,
+ PMIC_TOP0_DSN_CBS,
+ PMIC_TOP0_DSN_BIX,
+ PMIC_TOP0_DSN_ESP,
+ PMIC_TOP0_DSN_FPI,
+ PMIC_HWCID,
+ PMIC_SWCID,
+ PMIC_STS_ENB,
+ PMIC_STS_RBOOT,
+ PMIC_STS_UVLO,
+ PMIC_STS_PGFAIL,
+ PMIC_STS_PSOC,
+ PMIC_STS_THRDN,
+ PMIC_STS_WRST,
+ PMIC_STS_CRST,
+ PMIC_STS_RESET_B,
+ PMIC_STS_PROTECT,
+ PMIC_STS_BWDT,
+ PMIC_STS_DDLO,
+ PMIC_STS_WDT,
+ PMIC_STS_KEYPWR,
+ PMIC_STS_OVLO,
+ PMIC_RG_POFFSTS_CLR,
+ PMIC_RG_PONSTS_CLR,
+ PMIC_VEMC_PG_DEB,
+ PMIC_VIO18_PG_DEB,
+ PMIC_VSRAM_PROC_PG_DEB,
+ PMIC_VPROC_PG_DEB,
+ PMIC_VA12_PG_DEB,
+ PMIC_VA09_PG_DEB,
+ PMIC_VSRAM_OTHERS_PG_DEB,
+ PMIC_VBBCK_PG_DEB,
+ PMIC_VRFCK_PG_DEB,
+ PMIC_VS1_PG_DEB,
+ PMIC_VMODEM_PG_DEB,
+ PMIC_VCORE_PG_DEB,
+ PMIC_VS2_PG_DEB,
+ PMIC_VRTC_PG_DEB,
+ PMIC_VAUX18_PG_DEB,
+ PMIC_VXO22_PG_DEB,
+ PMIC_VAUD28_PG_DEB,
+ PMIC_VUSB_PG_DEB,
+ PMIC_VDRAM2_PG_DEB,
+ PMIC_VDRAM1_PG_DEB,
+ PMIC_VIO33_PG_DEB,
+ PMIC_STRUP_VEMC_PG_STATUS,
+ PMIC_STRUP_VIO18_PG_STATUS,
+ PMIC_STRUP_VSRAM_PROC_PG_STATUS,
+ PMIC_STRUP_VPROC_PG_STATUS,
+ PMIC_STRUP_VA12_PG_STATUS,
+ PMIC_STRUP_VA09_PG_STATUS,
+ PMIC_STRUP_VSRAM_OTHERS_PG_STATUS,
+ PMIC_STRUP_VBBCK_PG_STATUS,
+ PMIC_STRUP_VRFCK_PG_STATUS,
+ PMIC_STRUP_VS1_PG_STATUS,
+ PMIC_STRUP_VMODEM_PG_STATUS,
+ PMIC_STRUP_VCORE_PG_STATUS,
+ PMIC_STRUP_VS2_PG_STATUS,
+ PMIC_STRUP_VRTC_PG_STATUS,
+ PMIC_STRUP_VAUX18_PG_STATUS,
+ PMIC_STRUP_VXO22_PG_STATUS,
+ PMIC_STRUP_VAUD28_PG_STATUS,
+ PMIC_STRUP_VUSB_PG_STATUS,
+ PMIC_STRUP_VDRAM2_PG_STATUS,
+ PMIC_STRUP_VDRAM1_PG_STATUS,
+ PMIC_STRUP_VIO33_PG_STATUS,
+ PMIC_STRUP_VEMC_OC_STATUS,
+ PMIC_STRUP_VIO18_OC_STATUS,
+ PMIC_STRUP_VSRAM_PROC_OC_STATUS,
+ PMIC_STRUP_VPROC_OC_STATUS,
+ PMIC_STRUP_VA12_OC_STATUS,
+ PMIC_STRUP_VA09_OC_STATUS,
+ PMIC_STRUP_VSRAM_OTHERS_OC_STATUS,
+ PMIC_STRUP_VBBCK_OC_STATUS,
+ PMIC_STRUP_VRFCK_OC_STATUS,
+ PMIC_STRUP_VS1_OC_STATUS,
+ PMIC_STRUP_VMODEM_OC_STATUS,
+ PMIC_STRUP_VCORE_OC_STATUS,
+ PMIC_STRUP_VS2_OC_STATUS,
+ PMIC_STRUP_VRTC_OC_STATUS,
+ PMIC_STRUP_VAUX18_OC_STATUS,
+ PMIC_STRUP_VXO22_OC_STATUS,
+ PMIC_STRUP_VAUD28_OC_STATUS,
+ PMIC_STRUP_VUSB_OC_STATUS,
+ PMIC_STRUP_VDRAM2_OC_STATUS,
+ PMIC_STRUP_VDRAM1_OC_STATUS,
+ PMIC_STRUP_VIO33_OC_STATUS,
+ PMIC_PMU_THERMAL_DEB,
+ PMIC_STRUP_THERMAL_STATUS,
+ PMIC_RG_SRCLKEN_IN0_EN,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE,
+ PMIC_RG_SRCLKEN_IN1_EN,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE,
+ PMIC_RG_SRCLKEN_IN_SYNC_EN,
+ PMIC_RG_OSC_EN_AUTO_OFF,
+ PMIC_TEST_OUT,
+ PMIC_RG_MON_FLAG_SEL,
+ PMIC_RG_MON_GRP_SEL,
+ PMIC_RG_NANDTREE_MODE,
+ PMIC_RG_TEST_AUXADC,
+ PMIC_RG_EFUSE_MODE,
+ PMIC_RG_TEST_STRUP,
+ PMIC_TESTMODE_SW,
+ PMIC_PMU_TEST_MODE_SCAN,
+ PMIC_PWRKEY_DEB,
+ PMIC_CHRDET_DEB,
+ PMIC_HOMEKEY_DEB,
+ PMIC_RG_PMU_TDSEL,
+ PMIC_RG_SPI_TDSEL,
+ PMIC_RG_AUD_TDSEL,
+ PMIC_RG_E32CAL_TDSEL,
+ PMIC_RG_PMU_RDSEL,
+ PMIC_RG_SPI_RDSEL,
+ PMIC_RG_AUD_RDSEL,
+ PMIC_RG_E32CAL_RDSEL,
+ PMIC_RG_SMT_WDTRSTB_IN,
+ PMIC_RG_SMT_SRCLKEN_IN0,
+ PMIC_RG_SMT_SRCLKEN_IN1,
+ PMIC_RG_SMT_RTC_32K1V8_0,
+ PMIC_RG_SMT_RTC_32K1V8_1,
+ PMIC_RG_SMT_RTC_32K1V8_2,
+ PMIC_RG_SMT_SD_CARD_DET_N,
+ PMIC_RG_SMT_SPI_CLK,
+ PMIC_RG_SMT_SPI_CSN,
+ PMIC_RG_SMT_SPI_MOSI,
+ PMIC_RG_SMT_SPI_MISO,
+ PMIC_RG_SMT_AUD_CLK_MOSI,
+ PMIC_RG_SMT_AUD_DAT_MOSI0,
+ PMIC_RG_SMT_AUD_SYNC_MOSI,
+ PMIC_RG_SMT_AUD_CLK_MISO,
+ PMIC_RG_SMT_AUD_DAT_MISO0,
+ PMIC_RG_SMT_AUD_DAT_MISO1,
+ PMIC_RG_SMT_AUD_SYNC_MISO,
+ PMIC_RG_TOP_RSV0,
+ PMIC_RG_TOP_RSV1,
+ PMIC_RG_OCTL_SRCLKEN_IN0,
+ PMIC_RG_OCTL_SRCLKEN_IN1,
+ PMIC_RG_OCTL_RTC_32K1V8_0,
+ PMIC_RG_OCTL_RTC_32K1V8_1,
+ PMIC_RG_OCTL_SPI_CLK,
+ PMIC_RG_OCTL_SPI_CSN,
+ PMIC_RG_OCTL_SPI_MOSI,
+ PMIC_RG_OCTL_SPI_MISO,
+ PMIC_RG_OCTL_AUD_CLK_MOSI,
+ PMIC_RG_OCTL_AUD_DAT_MOSI0,
+ PMIC_RG_OCTL_AUD_SYNC_MOSI,
+ PMIC_RG_OCTL_AUD_CLK_MISO,
+ PMIC_RG_OCTL_AUD_DAT_MISO0,
+ PMIC_RG_OCTL_AUD_DAT_MISO1,
+ PMIC_RG_OCTL_AUD_SYNC_MISO,
+ PMIC_RG_OCTL_RTC_32K1V8_2,
+ PMIC_RG_OCTL_SD_CARD_DET_N,
+ PMIC_RG_SRCLKEN_IN0_FILTER_EN,
+ PMIC_RG_SRCLKEN_IN1_FILTER_EN,
+ PMIC_RG_RTC32K_1V8_0_FILTER_EN,
+ PMIC_RG_RTC32K_1V8_1_FILTER_EN,
+ PMIC_RG_SPI_CLK_FILTER_EN,
+ PMIC_RG_SPI_CSN_FILTER_EN,
+ PMIC_RG_SPI_MOSI_FILTER_EN,
+ PMIC_RG_SPI_MISO_FILTER_EN,
+ PMIC_RG_AUD_CLK_MOSI_FILTER_EN,
+ PMIC_RG_AUD_DAT_MOSI0_FILTER_EN,
+ PMIC_RG_AUD_SYNC_MOSI_FILTER_EN,
+ PMIC_RG_AUD_CLK_MISO_FILTER_EN,
+ PMIC_RG_AUD_DAT_MISO0_FILTER_EN,
+ PMIC_RG_AUD_DAT_MISO1_FILTER_EN,
+ PMIC_RG_AUD_SYNC_MISO_FILTER_EN,
+ PMIC_RG_RTC32K_1V8_2_FILTER_EN,
+ PMIC_RG_WDTRSTB_IN_FILTER_EN,
+ PMIC_RG_SD_CARD_DET_N_FILTER_EN,
+ PMIC_RG_SRCLKEN_IN0_RCSEL,
+ PMIC_RG_SRCLKEN_IN1_RCSEL,
+ PMIC_RG_RTC32K_1V8_0_RCSEL,
+ PMIC_RG_RTC32K_1V8_1_RCSEL,
+ PMIC_RG_SPI_CLK_RCSEL,
+ PMIC_RG_SPI_CSN_RCSEL,
+ PMIC_RG_SPI_MOSI_RCSEL,
+ PMIC_RG_SPI_MISO_RCSEL,
+ PMIC_RG_AUD_CLK_MOSI_RCSEL,
+ PMIC_RG_AUD_DAT_MOSI0_RCSEL,
+ PMIC_RG_AUD_SYNC_MOSI_RCSEL,
+ PMIC_RG_AUD_CLK_MISO_RCSEL,
+ PMIC_RG_AUD_DAT_MISO0_RCSEL,
+ PMIC_RG_AUD_DAT_MISO1_RCSEL,
+ PMIC_RG_AUD_SYNC_MISO_RCSEL,
+ PMIC_RG_RTC32K_1V8_2_RCSEL,
+ PMIC_RG_WDTRSTB_IN_RCSEL,
+ PMIC_RG_SD_CARD_DET_N_RCSEL,
+ PMIC_TOP_STATUS,
+ PMIC_TOP_STATUS_SET,
+ PMIC_TOP_STATUS_CLR,
+ PMIC_VM_MODE,
+ PMIC_TOP1_ANA_ID,
+ PMIC_TOP1_DIG_ID,
+ PMIC_TOP1_ANA_MINOR_REV,
+ PMIC_TOP1_ANA_MAJOR_REV,
+ PMIC_TOP1_DIG_MINOR_REV,
+ PMIC_TOP1_DIG_MAJOR_REV,
+ PMIC_TOP1_DSN_CBS,
+ PMIC_TOP1_DSN_BIX,
+ PMIC_TOP1_DSN_ESP,
+ PMIC_TOP1_DSN_FPI,
+ PMIC_GPIO_DIR0,
+ PMIC_GPIO_DIR0_SET,
+ PMIC_GPIO_DIR0_CLR,
+ PMIC_GPIO_DIR1,
+ PMIC_GPIO_DIR1_SET,
+ PMIC_GPIO_DIR1_CLR,
+ PMIC_GPIO_PULLEN0,
+ PMIC_GPIO_PULLEN0_SET,
+ PMIC_GPIO_PULLEN0_CLR,
+ PMIC_GPIO_PULLEN1,
+ PMIC_GPIO_PULLEN1_SET,
+ PMIC_GPIO_PULLEN1_CLR,
+ PMIC_GPIO_PULLSEL0,
+ PMIC_GPIO_PULLSEL0_SET,
+ PMIC_GPIO_PULLSEL0_CLR,
+ PMIC_GPIO_PULLSEL1,
+ PMIC_GPIO_PULLSEL1_SET,
+ PMIC_GPIO_PULLSEL1_CLR,
+ PMIC_GPIO_DINV0,
+ PMIC_GPIO_DINV0_SET,
+ PMIC_GPIO_DINV0_CLR,
+ PMIC_GPIO_DINV1,
+ PMIC_GPIO_DINV1_SET,
+ PMIC_GPIO_DINV1_CLR,
+ PMIC_GPIO_DOUT0,
+ PMIC_GPIO_DOUT0_SET,
+ PMIC_GPIO_DOUT0_CLR,
+ PMIC_GPIO_DOUT1,
+ PMIC_GPIO_DOUT1_SET,
+ PMIC_GPIO_DOUT1_CLR,
+ PMIC_GPIO_PI0,
+ PMIC_GPIO_PI1,
+ PMIC_GPIO_POE0,
+ PMIC_GPIO_POE1,
+ PMIC_GPIO0_MODE,
+ PMIC_GPIO1_MODE,
+ PMIC_GPIO2_MODE,
+ PMIC_GPIO3_MODE,
+ PMIC_GPIO_MODE0_SET,
+ PMIC_GPIO_MODE0_CLR,
+ PMIC_GPIO4_MODE,
+ PMIC_GPIO5_MODE,
+ PMIC_GPIO6_MODE,
+ PMIC_GPIO7_MODE,
+ PMIC_GPIO_MODE1_SET,
+ PMIC_GPIO_MODE1_CLR,
+ PMIC_GPIO8_MODE,
+ PMIC_GPIO9_MODE,
+ PMIC_GPIO10_MODE,
+ PMIC_GPIO11_MODE,
+ PMIC_GPIO_MODE2_SET,
+ PMIC_GPIO_MODE2_CLR,
+ PMIC_GPIO12_MODE,
+ PMIC_GPIO13_MODE,
+ PMIC_GPIO14_MODE,
+ PMIC_GPIO15_MODE,
+ PMIC_GPIO_MODE3_SET,
+ PMIC_GPIO_MODE3_CLR,
+ PMIC_GPIO16_MODE,
+ PMIC_GPIO_MODE4_SET,
+ PMIC_GPIO_MODE4_CLR,
+ PMIC_GPIO_RSV,
+ PMIC_TOP2_ANA_ID,
+ PMIC_TOP2_DIG_ID,
+ PMIC_TOP2_ANA_MINOR_REV,
+ PMIC_TOP2_ANA_MAJOR_REV,
+ PMIC_TOP2_DIG_MINOR_REV,
+ PMIC_TOP2_DIG_MAJOR_REV,
+ PMIC_TOP2_DSN_CBS,
+ PMIC_TOP2_DSN_BIX,
+ PMIC_TOP2_DSN_ESP,
+ PMIC_TOP2_DSN_FPI,
+ PMIC_TOP_CLK_OFFSET,
+ PMIC_TOP_RST_OFFSET,
+ PMIC_TOP_INT_OFFSET,
+ PMIC_TOP_INT_LEN,
+ PMIC_RG_SCK32K_CK_PDN,
+ PMIC_RG_INTRP_CK_PDN,
+ PMIC_RG_EFUSE_CK_PDN,
+ PMIC_RG_CK_PDN_RSV0,
+ PMIC_RG_CK_PDN_RSV1,
+ PMIC_RG_SPI_CK_PDN,
+ PMIC_RG_CK_PDN_RSV2,
+ PMIC_RG_PMU32K_CK_PDN,
+ PMIC_RG_FQMTR_32K_CK_PDN,
+ PMIC_RG_FQMTR_CK_PDN,
+ PMIC_RG_PMU128K_CK_PDN,
+ PMIC_RG_RTC26M_CK_PDN,
+ PMIC_RG_RTC32K_CK_PDN,
+ PMIC_TOP_CKPDN_CON0_SET,
+ PMIC_TOP_CKPDN_CON0_CLR,
+ PMIC_RG_RTC32K_1V8_0_PDN,
+ PMIC_RG_RTC32K_1V8_1_PDN,
+ PMIC_RG_TRIM_128K_CK_PDN,
+ PMIC_RG_BGR_TEST_CK_PDN,
+ PMIC_RG_PCHR_TEST_CK_PDN,
+ PMIC_RG_RTC32K_1V8_2_PDN,
+ PMIC_TOP_CKPDN_CON1_SET,
+ PMIC_TOP_CKPDN_CON1_CLR,
+ PMIC_RG_FQMTR_CK_CKSEL,
+ PMIC_RG_RTC_32K1V8_SEL,
+ PMIC_RG_BGR_TEST_CK_SEL_CKSEL,
+ PMIC_RG_PCHR_TEST_CK_CKSEL,
+ PMIC_RG_PMU_26M_CK_SEL_HWEN,
+ PMIC_RG_PMU_26M_CK_SEL,
+ PMIC_RG_PMU_1M_CK_SEL_HWEN,
+ PMIC_RG_PMU_1M_CK_SEL,
+ PMIC_RG_PMU32K_CK_CKSEL,
+ PMIC_RG_TOP_CKSEL_CON0_RSV,
+ PMIC_TOP_CKSEL_CON0_SET,
+ PMIC_TOP_CKSEL_CON0_CLR,
+ PMIC_RG_SRCVOLTEN_SW,
+ PMIC_RG_VOWEN_SW,
+ PMIC_RG_SRCVOLTEN_MODE,
+ PMIC_RG_VOWEN_MODE,
+ PMIC_RG_TOP_CKSEL_CON2_RSV,
+ PMIC_TOP_CKSEL_CON1_SET,
+ PMIC_TOP_CKSEL_CON1_CLR,
+ PMIC_RG_REG_CK_DIVSEL,
+ PMIC_TOP_CKDIVSEL_CON0_RSV,
+ PMIC_TOP_CKDIVSEL_CON0_SET,
+ PMIC_TOP_CKDIVSEL_CON0_CLR,
+ PMIC_RG_EFUSE_CK_PDN_HWEN,
+ PMIC_RG_EINT_32K_CK_PDN_HWEN,
+ PMIC_RG_RTC26M_CK_PDN_HWEN,
+ PMIC_TOP_CKHWEN_CON0_RSV,
+ PMIC_TOP_CKHWEN_CON0_SET,
+ PMIC_TOP_CKHWEN_CON0_CLR,
+ PMIC_RG_PMU128K_CK_TST_DIS,
+ PMIC_RG_DCXO_1M_CK_TST_DIS,
+ PMIC_RG_DCXO_26M_CK_TST_DIS,
+ PMIC_RG_XO_CLK_26M_DIG_TST_DIS,
+ PMIC_RG_RTC_26M_CK_TST_DIS,
+ PMIC_RG_RTC_32K_CK_TST_DIS,
+ PMIC_RG_SCK_32K_CK_TST_DIS,
+ PMIC_TOP_CKTST_CON0_RSV,
+ PMIC_RG_PMU128K_CK_TSTSEL,
+ PMIC_RG_DCXO_1M_CK_TSTSEL,
+ PMIC_RG_DCXO_26M_CK_TSTSEL,
+ PMIC_RG_XO_CLK_26M_DIG_TSTSEL,
+ PMIC_RG_RTC_26M_CK_TSTSEL,
+ PMIC_RG_RTC_32K_CK_TSTSEL,
+ PMIC_RG_SCK_32K_CK_TSTSEL,
+ PMIC_RG_EFUSE_CK_TSTSEL,
+ PMIC_RG_BGR_TEST_CK_TSTSEL,
+ PMIC_RG_PCHR_TEST_CK_TSTSEL,
+ PMIC_RG_FQMTR_CK_TSTSEL,
+ PMIC_RG_DCXO1M_TSTCK_SEL,
+ PMIC_RG_DCXO26M_CKEN_BUCK_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_BUCK_SW,
+ PMIC_RG_DCXO26M_CKEN_BM_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_BM_SW,
+ PMIC_RG_DCXO26M_CKEN_HK_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_HK_SW,
+ PMIC_RG_DCXO26M_CKEN_LDO_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_LDO_SW,
+ PMIC_RG_DCXO26M_CKEN_SCK_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_SCK_SW,
+ PMIC_RG_DCXO26M_CKEN_MDB_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_MDB_SW,
+ PMIC_RG_DCXO1M_CKEN_BUCK_SW_SEL,
+ PMIC_RG_DCXO1M_CKEN_BUCK_SW,
+ PMIC_RG_DCXO1M_CKEN_LDO_SW_SEL,
+ PMIC_RG_DCXO1M_CKEN_LDO_SW,
+ PMIC_RG_DCXO1M_CKEN_HK_SW_SEL,
+ PMIC_RG_DCXO1M_CKEN_HK_SW,
+ PMIC_RG_TOP_MDB_DCM_SW_MODE,
+ PMIC_RG_TOP_MDB_DCM_SW_EN,
+ PMIC_RG_SCK_MDB_DCM_SW_MODE,
+ PMIC_RG_SCK_MDB_DCM_SW_EN,
+ PMIC_RG_LDO_MDB_DCM_SW_MODE,
+ PMIC_RG_LDO_MDB_DCM_SW_EN,
+ PMIC_RG_BUCK_MDB_DCM_SW_MODE,
+ PMIC_RG_BUCK_MDB_DCM_SW_EN,
+ PMIC_RG_MDB_DCXO26M_DCM_LP_EN,
+ PMIC_RG_EFUSE_MAN_RST,
+ PMIC_RG_DRIVER_RST,
+ PMIC_RG_FQMTR_RST,
+ PMIC_RG_RTC_RST,
+ PMIC_RG_TYPE_C_CC_RST,
+ PMIC_RG_CLK_TRIM_RST,
+ PMIC_RG_BUCK_SRCLKEN_RST,
+ PMIC_TOP_RST_CON0_SET,
+ PMIC_TOP_RST_CON0_CLR,
+ PMIC_RG_BUCK_PROT_PMPP_RST,
+ PMIC_RG_SPK_RST,
+ PMIC_RG_FT_VR_SYSRSTB,
+ PMIC_RG_LDO_CALI_RST,
+ PMIC_TOP_RST_CON1_RSV,
+ PMIC_TOP_RST_CON1_SET,
+ PMIC_TOP_RST_CON1_CLR,
+ PMIC_RG_CHR_LDO_DET_MODE,
+ PMIC_RG_CHR_LDO_DET_SW,
+ PMIC_RG_CHRWDT_FLAG_MODE,
+ PMIC_RG_CHRWDT_FLAG_SW,
+ PMIC_TOP_RST_CON2_RSV,
+ PMIC_RG_GPIO_RST_SEL,
+ PMIC_RG_WDTRSTB_EN,
+ PMIC_RG_WDTRSTB_MODE,
+ PMIC_WDTRSTB_STATUS,
+ PMIC_WDTRSTB_STATUS_CLR,
+ PMIC_RG_WDTRSTB_FB_EN,
+ PMIC_RG_WDTRSTB_DEB,
+ PMIC_RG_PWRKEY_KEY_MODE,
+ PMIC_RG_PWRKEY_RST_EN,
+ PMIC_RG_PWRRST_TMR_DIS,
+ PMIC_RG_PWRKEY_RST_TD,
+ PMIC_TOP_RST_MISC_RSV,
+ PMIC_TOP_RST_MISC_SET,
+ PMIC_TOP_RST_MISC_CLR,
+ PMIC_VPWRIN_RSTB_STATUS,
+ PMIC_DDLO_RSTB_STATUS,
+ PMIC_UVLO_RSTB_STATUS,
+ PMIC_RTC_DDLO_RSTB_STATUS,
+ PMIC_CHRWDT_REG_RSTB_STATUS,
+ PMIC_CHRDET_REG_RSTB_STATUS,
+ PMIC_BWDT_DDLO_RSTB_STATUS,
+ PMIC_TOP_RST_STATUS_RSV,
+ PMIC_TOP_RST_STATUS_SET,
+ PMIC_TOP_RST_STATUS_CLR,
+ PMIC_TOP2_ELR_LEN,
+ PMIC_RG_TOP2_RSV0,
+ PMIC_RG_TOP2_RSV1,
+ PMIC_TOP3_ANA_ID,
+ PMIC_TOP3_DIG_ID,
+ PMIC_TOP3_ANA_MINOR_REV,
+ PMIC_TOP3_ANA_MAJOR_REV,
+ PMIC_TOP3_DIG_MINOR_REV,
+ PMIC_TOP3_DIG_MAJOR_REV,
+ PMIC_TOP3_DSN_CBS,
+ PMIC_TOP3_DSN_BIX,
+ PMIC_TOP3_DSN_ESP,
+ PMIC_TOP3_DSN_FPI,
+ PMIC_RG_INT_EN_SPI_CMD_ALERT,
+ PMIC_MISC_TOP_INT_CON0_SET,
+ PMIC_MISC_TOP_INT_CON0_CLR,
+ PMIC_RG_INT_MASK_SPI_CMD_ALERT,
+ PMIC_MISC_TOP_INT_MASK_CON0_SET,
+ PMIC_MISC_TOP_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_SPI_CMD_ALERT,
+ PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT,
+ PMIC_RG_INT_MASK_BUCK_TOP,
+ PMIC_RG_INT_MASK_LDO_TOP,
+ PMIC_RG_INT_MASK_PSC_TOP,
+ PMIC_RG_INT_MASK_SCK_TOP,
+ PMIC_RG_INT_MASK_BM_TOP,
+ PMIC_RG_INT_MASK_HK_TOP,
+ PMIC_RG_INT_MASK_XPP_TOP,
+ PMIC_RG_INT_MASK_AUD_TOP,
+ PMIC_RG_INT_MASK_MISC_TOP,
+ PMIC_TOP_INT_MASK_CON0_SET,
+ PMIC_TOP_INT_MASK_CON0_CLR,
+ PMIC_INT_STATUS_BUCK_TOP,
+ PMIC_INT_STATUS_LDO_TOP,
+ PMIC_INT_STATUS_PSC_TOP,
+ PMIC_INT_STATUS_SCK_TOP,
+ PMIC_INT_STATUS_BM_TOP,
+ PMIC_INT_STATUS_HK_TOP,
+ PMIC_INT_STATUS_XPP_TOP,
+ PMIC_INT_STATUS_AUD_TOP,
+ PMIC_INT_STATUS_MISC_TOP,
+ PMIC_INT_STATUS_TOP_RSV,
+ PMIC_INT_RAW_STATUS_BUCK_TOP,
+ PMIC_INT_RAW_STATUS_LDO_TOP,
+ PMIC_INT_RAW_STATUS_PSC_TOP,
+ PMIC_INT_RAW_STATUS_SCK_TOP,
+ PMIC_INT_RAW_STATUS_BM_TOP,
+ PMIC_INT_RAW_STATUS_HK_TOP,
+ PMIC_INT_RAW_STATUS_XPP_TOP,
+ PMIC_INT_RAW_STATUS_AUD_TOP,
+ PMIC_INT_RAW_STATUS_MISC_TOP,
+ PMIC_INT_RAW_STATUS_TOP_RSV,
+ PMIC_RG_INT_POLARITY,
+ PMIC_RG_DCXO26M_CKEN_SW_SEL,
+ PMIC_RG_DCXO26M_CKEN_SW,
+ PMIC_RG_DCXO1M_CKEN_SW_SEL,
+ PMIC_RG_DCXO1M_CKEN_SW,
+ PMIC_PMRC_EN,
+ PMIC_PMRC_EN_SET,
+ PMIC_PMRC_EN_CLR,
+ PMIC_RG_VR_SPM_MODE,
+ PMIC_RG_VR_MD_MODE,
+ PMIC_RG_VR_SSHUB_MODE,
+ PMIC_PMRC_CON1_SET,
+ PMIC_PMRC_CON1_CLR,
+ PMIC_RG_SRCLKEN2_MODE,
+ PMIC_RG_SRCLKEN3_MODE,
+ PMIC_PLT0_ANA_ID,
+ PMIC_PLT0_DIG_ID,
+ PMIC_PLT0_ANA_MINOR_REV,
+ PMIC_PLT0_ANA_MAJOR_REV,
+ PMIC_PLT0_DIG_MINOR_REV,
+ PMIC_PLT0_DIG_MAJOR_REV,
+ PMIC_PLT0_DSN_CBS,
+ PMIC_PLT0_DSN_BIX,
+ PMIC_PLT0_DSN_ESP,
+ PMIC_PLT0_DSN_FPI,
+ PMIC_RG_OSC_128K_TRIM_EN,
+ PMIC_RG_OSC_128K_TRIM_RATE,
+ PMIC_DA_OSC_128K_TRIM,
+ PMIC_RG_OTP_PA,
+ PMIC_RG_OTP_PDIN,
+ PMIC_RG_OTP_PTM,
+ PMIC_RG_OTP_PWE,
+ PMIC_RG_OTP_PPROG,
+ PMIC_RG_OTP_PWE_SRC,
+ PMIC_RG_OTP_PROG_PKEY,
+ PMIC_RG_OTP_RD_PKEY,
+ PMIC_RG_OTP_RD_TRIG,
+ PMIC_RG_RD_RDY_BYPASS,
+ PMIC_RG_SKIP_OTP_OUT,
+ PMIC_RG_OTP_RD_SW,
+ PMIC_RG_OTP_DOUT_SW,
+ PMIC_RG_OTP_RD_BUSY,
+ PMIC_RG_OTP_RD_ACK,
+ PMIC_RG_OTP_PA_SW,
+ PMIC_OTP_DOUT_0,
+ PMIC_OTP_DOUT_1,
+ PMIC_OTP_DOUT_2,
+ PMIC_OTP_DOUT_HW,
+ PMIC_RG_OTP_PROG_MACRO_SEL,
+ PMIC_RG_OTP_MISMATCH_PA_CLR,
+ PMIC_RG_OTP_MISMATCH_PA_0,
+ PMIC_RG_OTP_MISMATCH_PA_1,
+ PMIC_TMA_KEY,
+ PMIC_TOP_MDB_RSV0,
+ PMIC_TOP_MDB_RSV1,
+ PMIC_RG_MDB_DM1_DS_EN,
+ PMIC_RG_AUTO_LOAD_FORCE,
+ PMIC_RG_OTP_WRITE_SEL,
+ PMIC_RG_TOP_MDB_BRIDGE_BYPASS_EN,
+ PMIC_RG_SCK_MDB_BRIDGE_BYPASS_EN,
+ PMIC_RG_LDO_MDB_BRIDGE_BYPASS_EN,
+ PMIC_RG_BUCK_MDB_BRIDGE_BYPASS_EN,
+ PMIC_RG_MDB_BRDG_ACS_SUSPEND,
+ PMIC_RG_MDB_BRDG_ACS_DEEPIDLE,
+ PMIC_PLT0_ELR_LEN,
+ PMIC_RG_OSC_128K_TRIM,
+ PMIC_SPISLV_ANA_ID,
+ PMIC_SPISLV_DIG_ID,
+ PMIC_SPISLV_ANA_MINOR_REV,
+ PMIC_SPISLV_ANA_MAJOR_REV,
+ PMIC_SPISLV_DIG_MINOR_REV,
+ PMIC_SPISLV_DIG_MAJOR_REV,
+ PMIC_SPISLV_DSN_CBS,
+ PMIC_SPISLV_DSN_BIX,
+ PMIC_SPISLV_DSN_ESP,
+ PMIC_SPISLV_DSN_FPI,
+ PMIC_RG_SPI_MISO_MODE_SEL,
+ PMIC_RG_EN_RECORD,
+ PMIC_RG_RD_RECORD_EN,
+ PMIC_RG_SPI_RSV,
+ PMIC_DEW_DIO_EN,
+ PMIC_DEW_READ_TEST,
+ PMIC_DEW_WRITE_TEST,
+ PMIC_DEW_CRC_SWRST,
+ PMIC_DEW_CRC_EN,
+ PMIC_DEW_CRC_VAL,
+ PMIC_DEW_CIPHER_KEY_SEL,
+ PMIC_DEW_CIPHER_IV_SEL,
+ PMIC_DEW_CIPHER_EN,
+ PMIC_DEW_CIPHER_RDY,
+ PMIC_DEW_CIPHER_MODE,
+ PMIC_DEW_CIPHER_SWRST,
+ PMIC_DEW_RDDMY_NO,
+ PMIC_RG_SPI_DLY_SEL,
+ PMIC_RECORD_CMD0,
+ PMIC_RECORD_CMD1,
+ PMIC_RECORD_CMD2,
+ PMIC_RECORD_CMD3,
+ PMIC_RECORD_CMD4,
+ PMIC_RECORD_CMD5,
+ PMIC_RECORD_WDATA0,
+ PMIC_RECORD_WDATA1,
+ PMIC_RECORD_WDATA2,
+ PMIC_RECORD_WDATA3,
+ PMIC_RECORD_WDATA4,
+ PMIC_RECORD_WDATA5,
+ PMIC_RG_ADDR_TARGET,
+ PMIC_RG_ADDR_MASK,
+ PMIC_RG_WDATA_TARGET,
+ PMIC_RG_WDATA_MASK,
+ PMIC_RG_SPI_RECORD_CLR,
+ PMIC_RG_CMD_ALERT_CLR,
+ PMIC_SPISLV_KEY,
+ PMIC_INT_TYPE_CON0,
+ PMIC_INT_TYPE_CON0_SET,
+ PMIC_INT_TYPE_CON0_CLR,
+ PMIC_CPU_INT_STA,
+ PMIC_MD32_INT_STA,
+ PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE,
+ PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST,
+ PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE,
+ PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST,
+ PMIC_RG_SRCLKEN_IN2_EN,
+ PMIC_RG_SRCLKEN_IN3_EN,
+ PMIC_SCK_TOP_ANA_ID,
+ PMIC_SCK_TOP_DIG_ID,
+ PMIC_SCK_TOP_ANA_MINOR_REV,
+ PMIC_SCK_TOP_ANA_MAJOR_REV,
+ PMIC_SCK_TOP_DIG_MINOR_REV,
+ PMIC_SCK_TOP_DIG_MAJOR_REV,
+ PMIC_SCK_TOP_CBS,
+ PMIC_SCK_TOP_BIX,
+ PMIC_SCK_TOP_ESP,
+ PMIC_SCK_TOP_FPI,
+ PMIC_SCK_TOP_CLK_OFFSET,
+ PMIC_SCK_TOP_RST_OFFSET,
+ PMIC_SCK_TOP_INT_OFFSET,
+ PMIC_SCK_TOP_INT_LEN,
+ PMIC_SCK_TOP_XTAL_SEL,
+ PMIC_SCK_TOP_RESERVED,
+ PMIC_XOSC32_ENB_DET,
+ PMIC_SCK_TOP_TEST_OUT,
+ PMIC_SCK_TOP_MON_FLAG_SEL,
+ PMIC_SCK_TOP_MON_GRP_SEL,
+ PMIC_RG_RTC_SEC_MCLK_PDN,
+ PMIC_RG_EOSC_CALI_TEST_CK_PDN,
+ PMIC_RG_RTC_EOSC32_CK_PDN,
+ PMIC_RG_RTC_SEC_32K_CK_PDN,
+ PMIC_RG_RTC_MCLK_PDN,
+ PMIC_RG_RTC_32K_CK_PDN,
+ PMIC_RG_RTC_26M_CK_PDN,
+ PMIC_RG_RTC_2SEC_OFF_DET_PDN,
+ PMIC_RG_RTC_INTRP_CK_PDN,
+ PMIC_SCK_TOP_CKPDN_CON0_SET,
+ PMIC_SCK_TOP_CKPDN_CON0_CLR,
+ PMIC_RG_RTC_26M_CK_PDN_HWEN,
+ PMIC_RG_RTC_MCLK_PDN_HWEN,
+ PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN,
+ PMIC_RG_RTC_SEC_MCLK_PDN_HWEN,
+ PMIC_RG_RTC_INTRP_CK_PDN_HWEN,
+ PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1,
+ PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0,
+ PMIC_SCK_TOP_CKHWEN_CON_SET,
+ PMIC_SCK_TOP_CKHWEN_CON_CLR,
+ PMIC_RG_RTC_CK_TSTSEL_RSV,
+ PMIC_RG_RTCDET_CK_TSTSEL,
+ PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL,
+ PMIC_RG_RTC_EOSC32_CK_TSTSEL,
+ PMIC_RG_RTC_SWRST,
+ PMIC_RG_RTC_SEC_SWRST,
+ PMIC_RG_BANK_RTC_SWRST,
+ PMIC_RG_BANK_RTC_SEC_SWRST,
+ PMIC_RG_BANK_EOSC_CALI_SWRST,
+ PMIC_RG_BANK_SCK_TOP_SWRST,
+ PMIC_RG_BANK_FQMTR_RST,
+ PMIC_SCK_TOP_RST_CON0_SET,
+ PMIC_SCK_TOP_RST_CON0_CLR,
+ PMIC_RG_INT_EN_RTC,
+ PMIC_SCK_TOP_INT_CON0_SET,
+ PMIC_SCK_TOP_INT_CON0_CLR,
+ PMIC_RG_INT_MASK_RTC,
+ PMIC_SCK_TOP_INT_MASK_CON0_SET,
+ PMIC_SCK_TOP_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_RTC,
+ PMIC_RG_INT_RAW_STATUS_RTC,
+ PMIC_SCK_TOP_POLARITY,
+ PMIC_EOSC_CALI_START,
+ PMIC_EOSC_CALI_TD,
+ PMIC_EOSC_CALI_TEST,
+ PMIC_EOSC_CALI_DCXO_RDY_TD,
+ PMIC_FRC_VTCXO0_ON,
+ PMIC_EOSC_CALI_RSV,
+ PMIC_MIX_EOSC32_STP_LPDTB,
+ PMIC_MIX_EOSC32_STP_LPDEN,
+ PMIC_MIX_XOSC32_STP_PWDB,
+ PMIC_MIX_XOSC32_STP_LPDTB,
+ PMIC_MIX_XOSC32_STP_LPDEN,
+ PMIC_MIX_XOSC32_STP_LPDRST,
+ PMIC_MIX_XOSC32_STP_CALI,
+ PMIC_STMP_MODE,
+ PMIC_MIX_EOSC32_STP_CHOP_EN,
+ PMIC_MIX_DCXO_STP_LVSH_EN,
+ PMIC_MIX_PMU_STP_DDLO_VRTC,
+ PMIC_MIX_PMU_STP_DDLO_VRTC_EN,
+ PMIC_MIX_RTC_STP_XOSC32_ENB,
+ PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE,
+ PMIC_MIX_EOSC32_STP_RSV,
+ PMIC_MIX_EOSC32_VCT_EN,
+ PMIC_MIX_EOSC32_OPT,
+ PMIC_MIX_DCXO_STP_LVSH_EN_INT,
+ PMIC_MIX_RTC_GPIO_COREDETB,
+ PMIC_MIX_RTC_GPIO_F32KOB,
+ PMIC_MIX_RTC_GPIO_GPO,
+ PMIC_MIX_RTC_GPIO_OE,
+ PMIC_MIX_RTC_STP_DEBUG_OUT,
+ PMIC_MIX_RTC_STP_DEBUG_SEL,
+ PMIC_MIX_RTC_STP_K_EOSC32_EN,
+ PMIC_MIX_RTC_STP_EMBCK_SEL,
+ PMIC_MIX_STP_BBWAKEUP,
+ PMIC_MIX_STP_RTC_DDLO,
+ PMIC_MIX_RTC_XOSC32_ENB,
+ PMIC_MIX_EFUSE_XOSC32_ENB_OPT,
+ PMIC_RG_RTC_TEST_OUT,
+ PMIC_RG_RTC_DIG_TEST_IN,
+ PMIC_RG_RTC_DIG_TEST_MODE,
+ PMIC_FQMTR_TCKSEL,
+ PMIC_FQMTR_BUSY,
+ PMIC_FQMTR_DCXO26M_EN,
+ PMIC_FQMTR_EN,
+ PMIC_FQMTR_WINSET,
+ PMIC_FQMTR_DATA,
+ PMIC_XO_SOC_VOTE,
+ PMIC_XO_WCN_VOTE,
+ PMIC_XO_NFC_VOTE,
+ PMIC_XO_CEL_VOTE,
+ PMIC_XO_EXT_VOTE,
+ PMIC_XO_MODE_CONN_BT_MASK,
+ PMIC_XO_BUF_CONN_BT_MASK,
+ PMIC_RTC_ANA_ID,
+ PMIC_RTC_DIG_ID,
+ PMIC_RTC_ANA_MINOR_REV,
+ PMIC_RTC_ANA_MAJOR_REV,
+ PMIC_RTC_DIG_MINOR_REV,
+ PMIC_RTC_DIG_MAJOR_REV,
+ PMIC_RTC_DSN_CBS,
+ PMIC_RTC_DSN_BIX,
+ PMIC_RTC_DSN_ESP,
+ PMIC_RTC_DSN_FPI,
+ PMIC_BBPU,
+ PMIC_CLRPKY,
+ PMIC_RELOAD,
+ PMIC_CBUSY,
+ PMIC_ALARM_STATUS,
+ PMIC_KEY_BBPU,
+ PMIC_ALSTA,
+ PMIC_TCSTA,
+ PMIC_LPSTA,
+ PMIC_AL_EN,
+ PMIC_TC_EN,
+ PMIC_ONESHOT,
+ PMIC_LP_EN,
+ PMIC_SECCII,
+ PMIC_MINCII,
+ PMIC_HOUCII,
+ PMIC_DOMCII,
+ PMIC_DOWCII,
+ PMIC_MTHCII,
+ PMIC_YEACII,
+ PMIC_SECCII_1_2,
+ PMIC_SECCII_1_4,
+ PMIC_SECCII_1_8,
+ PMIC_SEC_MSK,
+ PMIC_MIN_MSK,
+ PMIC_HOU_MSK,
+ PMIC_DOM_MSK,
+ PMIC_DOW_MSK,
+ PMIC_MTH_MSK,
+ PMIC_YEA_MSK,
+ PMIC_TC_SECOND,
+ PMIC_TC_MINUTE,
+ PMIC_TC_HOUR,
+ PMIC_TC_DOM,
+ PMIC_TC_DOW,
+ PMIC_TC_MONTH,
+ PMIC_RTC_MACRO_ID,
+ PMIC_TC_YEAR,
+ PMIC_AL_SECOND,
+ PMIC_BBPU_AUTO_PDN_SEL,
+ PMIC_BBPU_2SEC_CK_SEL,
+ PMIC_BBPU_2SEC_EN,
+ PMIC_BBPU_2SEC_MODE,
+ PMIC_BBPU_2SEC_STAT_CLEAR,
+ PMIC_BBPU_2SEC_STAT_STA,
+ PMIC_RTC_LPD_OPT,
+ PMIC_K_EOSC32_VTCXO_ON_SEL,
+ PMIC_AL_MINUTE,
+ PMIC_AL_HOUR,
+ PMIC_NEW_SPARE0,
+ PMIC_AL_DOM,
+ PMIC_NEW_SPARE1,
+ PMIC_AL_DOW,
+ PMIC_RG_EOSC_CALI_TD,
+ PMIC_NEW_SPARE2,
+ PMIC_AL_MONTH,
+ PMIC_NEW_SPARE3,
+ PMIC_AL_YEAR,
+ PMIC_RTC_K_EOSC_RSV,
+ PMIC_XOSCCALI,
+ PMIC_RTC_XOSC32_ENB,
+ PMIC_RTC_EMBCK_SEL_MODE,
+ PMIC_RTC_EMBCK_SRC_SEL,
+ PMIC_RTC_EMBCK_SEL_OPTION,
+ PMIC_RTC_GPS_CKOUT_EN,
+ PMIC_RTC_EOSC32_VCT_EN,
+ PMIC_RTC_EOSC32_CHOP_EN,
+ PMIC_RTC_GP_OSC32_CON,
+ PMIC_RTC_REG_XOSC32_ENB,
+ PMIC_RTC_POWERKEY1,
+ PMIC_RTC_POWERKEY2,
+ PMIC_RTC_PDN1,
+ PMIC_RTC_PDN2,
+ PMIC_RTC_SPAR0,
+ PMIC_RTC_SPAR1,
+ PMIC_RTC_PROT,
+ PMIC_RTC_DIFF,
+ PMIC_POWER_DETECTED,
+ PMIC_K_EOSC32_RSV,
+ PMIC_CALI_RD_SEL,
+ PMIC_RTC_CALI,
+ PMIC_CALI_WR_SEL,
+ PMIC_K_EOSC32_OVERFLOW,
+ PMIC_WRTGR,
+ PMIC_VBAT_LPSTA_RAW,
+ PMIC_EOSC32_LPEN,
+ PMIC_XOSC32_LPEN,
+ PMIC_LPRST,
+ PMIC_CDBO,
+ PMIC_F32KOB,
+ PMIC_GPO,
+ PMIC_GOE,
+ PMIC_GSR,
+ PMIC_GSMT,
+ PMIC_GPEN,
+ PMIC_GPU,
+ PMIC_GE4,
+ PMIC_GE8,
+ PMIC_GPI,
+ PMIC_LPSTA_RAW,
+ PMIC_DAT0_LOCK,
+ PMIC_DAT1_LOCK,
+ PMIC_DAT2_LOCK,
+ PMIC_RTC_INT_CNT,
+ PMIC_RTC_SEC_DAT0,
+ PMIC_RTC_SEC_DAT1,
+ PMIC_RTC_SEC_DAT2,
+ PMIC_RTC_SEC_ANA_ID,
+ PMIC_RTC_SEC_DIG_ID,
+ PMIC_RTC_SEC_ANA_MINOR_REV,
+ PMIC_RTC_SEC_ANA_MAJOR_REV,
+ PMIC_RTC_SEC_DIG_MINOR_REV,
+ PMIC_RTC_SEC_DIG_MAJOR_REV,
+ PMIC_RTC_SEC_DSN_CBS,
+ PMIC_RTC_SEC_DSN_BIX,
+ PMIC_RTC_SEC_DSN_ESP,
+ PMIC_RTC_SEC_DSN_FPI,
+ PMIC_TC_SECOND_SEC,
+ PMIC_TC_MINUTE_SEC,
+ PMIC_TC_HOUR_SEC,
+ PMIC_TC_DOM_SEC,
+ PMIC_TC_DOW_SEC,
+ PMIC_TC_MONTH_SEC,
+ PMIC_TC_YEAR_SEC,
+ PMIC_RTC_SEC_CK_PDN,
+ PMIC_RTC_SEC_WRTGR,
+ PMIC_DCXO_ANA_ID,
+ PMIC_DCXO_DIG_ID,
+ PMIC_DCXO_ANA_MINOR_REV,
+ PMIC_DCXO_ANA_MAJOR_REV,
+ PMIC_DCXO_DIG_MINOR_REV,
+ PMIC_DCXO_DIG_MAJOR_REV,
+ PMIC_DCXO_DSN_CBS,
+ PMIC_DCXO_DSN_BIX,
+ PMIC_DCXO_DSN_ESP,
+ PMIC_DCXO_DSN_FPI,
+ PMIC_XO_EXTBUF1_MODE,
+ PMIC_XO_EXTBUF1_EN_M,
+ PMIC_XO_EXTBUF2_MODE,
+ PMIC_XO_EXTBUF2_EN_M,
+ PMIC_XO_EXTBUF3_MODE,
+ PMIC_XO_EXTBUF3_EN_M,
+ PMIC_XO_EXTBUF4_MODE,
+ PMIC_XO_EXTBUF4_EN_M,
+ PMIC_XO_BB_LPM_EN_M,
+ PMIC_XO_ENBB_MAN,
+ PMIC_XO_ENBB_EN_M,
+ PMIC_XO_CLKSEL_MAN,
+ PMIC_DCXO_CW00_SET,
+ PMIC_DCXO_CW00_CLR,
+ PMIC_XO_CLKSEL_EN_M,
+ PMIC_XO_EXTBUF1_CKG_MAN,
+ PMIC_XO_EXTBUF1_CKG_EN_M,
+ PMIC_XO_EXTBUF2_CKG_MAN,
+ PMIC_XO_EXTBUF2_CKG_EN_M,
+ PMIC_XO_EXTBUF3_CKG_MAN,
+ PMIC_XO_EXTBUF3_CKG_EN_M,
+ PMIC_XO_EXTBUF4_CKG_MAN,
+ PMIC_XO_EXTBUF4_CKG_EN_M,
+ PMIC_XO_HV_PBUF_MAN,
+ PMIC_XO_HV_PBUF_EN_SYNC_M,
+ PMIC_XO_HV_PBUFBIAS_EN_M,
+ PMIC_XO_LV_PBUF_MAN,
+ PMIC_XO_LV_PBUFBIAS_EN_M,
+ PMIC_XO_LV_PBUF_EN_M,
+ PMIC_XO_BBLPM_CKSEL_M,
+ PMIC_XO_EN32K_MAN,
+ PMIC_XO_EN32K_M,
+ PMIC_RG_XO_CBANK_POL,
+ PMIC_XO_XMODE_M,
+ PMIC_XO_STRUP_MODE,
+ PMIC_RG_XO_PCTAT_CCOMP,
+ PMIC_RG_XO_VTEST_SEL_MUX,
+ PMIC_XO_SWRST,
+ PMIC_XO_CBANK_SYNC_DYN,
+ PMIC_XO_PCTAT_EN_MAN,
+ PMIC_XO_PCTAT_EN_M,
+ PMIC_XO_PMU_CKEN_M,
+ PMIC_XO_PMU_CKEN_MAN,
+ PMIC_XO_EXTBUF6_CKG_MAN,
+ PMIC_XO_EXTBUF6_CKG_EN_M,
+ PMIC_XO_EXTBUF7_CKG_MAN,
+ PMIC_XO_EXTBUF7_CKG_EN_M,
+ PMIC_RG_XO_CORE_LPM_ISEL,
+ PMIC_XO_FPM_ISEL_M,
+ PMIC_XO_CDAC_FPM,
+ PMIC_XO_CDAC_LPM,
+ PMIC_XO_32KDIV_NFRAC_FPM,
+ PMIC_XO_COFST_FPM,
+ PMIC_XO_32KDIV_NFRAC_LPM,
+ PMIC_XO_COFST_LPM,
+ PMIC_XO_CORE_MAN,
+ PMIC_XO_CORE_EN_M,
+ PMIC_XO_CORE_TURBO_EN_SYNC_M,
+ PMIC_RG_XO_PCTAT_IS_EN,
+ PMIC_XO_STARTUP_EN_M,
+ PMIC_RG_XO_CMP_GSEL,
+ PMIC_XO_CORE_VBSEL_SYNC_M,
+ PMIC_XO_CORE_FPMBIAS_EN_M,
+ PMIC_XO_CORE_LPMCF_SYNC_FPM,
+ PMIC_XO_CORE_LPMCF_SYNC_LPM,
+ PMIC_RG_XO_CORE_LPM_ISEL_MAN,
+ PMIC_RG_XO_CORE_LPM_IDAC,
+ PMIC_XO_AAC_CMP_MAN,
+ PMIC_XO_AAC_EN_M,
+ PMIC_XO_PMIC_TOP_DIG_SW,
+ PMIC_XO_CMP_EN_M,
+ PMIC_XO_AAC_VSEL_M,
+ PMIC_RG_XO_AAC_X1EN,
+ PMIC_RG_XO_LVBUF_CKSEL,
+ PMIC_RG_XO_RFCK_EXTBUF_LP,
+ PMIC_RG_XO_BBCK_EXTBUF_LP,
+ PMIC_XO_AAC_FPM_TIME,
+ PMIC_XO_AAC_ISEL_MAN,
+ PMIC_XO_AAC_FPM_SWEN,
+ PMIC_XO_32KDIV_SWRST,
+ PMIC_XO_32KDIV_RATIO_MAN,
+ PMIC_XO_32KDIV_TEST_EN,
+ PMIC_XO_CTL_SYNC_BUF_MAN,
+ PMIC_XO_CTL_SYNC_BUF_EN_M,
+ PMIC_RG_XO_HV_PBUF_VSET,
+ PMIC_XO_EXTBUF6_MODE,
+ PMIC_XO_EXTBUF6_EN_M,
+ PMIC_XO_EXTBUF7_MODE,
+ PMIC_XO_EXTBUF7_EN_M,
+ PMIC_DCXO_CW09_SET,
+ PMIC_DCXO_CW09_CLR,
+ PMIC_XO_MDB_TBO_EN_SEL,
+ PMIC_XO_EXTBUF4_CLKSEL_MAN,
+ PMIC_XO_VIO18PG_BUFEN,
+ PMIC_XO_CAL_EN_MAN,
+ PMIC_XO_CAL_EN_M,
+ PMIC_RG_XO_CORE_OSCTD,
+ PMIC_XO_THADC_EN,
+ PMIC_RG_XO_SYNC_CKPOL,
+ PMIC_RG_XO_CORE_FPM_IDAC,
+ PMIC_RG_XO_CTL_POL,
+ PMIC_RG_XO_CTL_SYNC_BYP,
+ PMIC_RG_XO_VXO22PG_MAN,
+ PMIC_RG_XO_HV_PBUF_BYP,
+ PMIC_RG_XO_HV_PBUF_ENCL,
+ PMIC_RG_XO_CORE_VGBIAS_VSET,
+ PMIC_XO_CORE_TURBO_EN_SYNC_MAN,
+ PMIC_RG_XO_HV_PBUF_ISET,
+ PMIC_RG_XO_HEATER_SEL,
+ PMIC_RG_XO_RESERVED6,
+ PMIC_RG_XO_VOW_EN,
+ PMIC_RG_XO_LV_PBUF_ISET,
+ PMIC_RG_XO_LV_PBUF_FPMISET,
+ PMIC_XO_BB_LPM_EN_SEL,
+ PMIC_XO_EXTBUF1_BBLPM_EN_MASK,
+ PMIC_XO_EXTBUF2_BBLPM_EN_MASK,
+ PMIC_XO_EXTBUF3_BBLPM_EN_MASK,
+ PMIC_XO_EXTBUF4_BBLPM_EN_MASK,
+ PMIC_XO_EXTBUF6_BBLPM_EN_MASK,
+ PMIC_XO_EXTBUF7_BBLPM_EN_MASK,
+ PMIC_RG_XO_DIG26M_DIV4_32KDIV,
+ PMIC_RG_XO_BBLPM_FREQ_FPM,
+ PMIC_RG_XO_EXTBUF2_INV,
+ PMIC_RG_XO_EXTBUF3_INV,
+ PMIC_XO_THADC_EN_MAN,
+ PMIC_XO_EXTBUF2_CLKSEL_MAN,
+ PMIC_RG_XO_AUDIO_EN,
+ PMIC_RG_XO_AUDIO_ATTEN,
+ PMIC_RG_XO_EXTBUF2_SRSEL,
+ PMIC_RG_XO_DIG26M_DEGLITCH,
+ PMIC_RG_XO_EXTBUF4_SRSEL,
+ PMIC_RG_XO_DIG26M_DIV2_SW_MAN,
+ PMIC_RG_XO_EXTBUF1_HD,
+ PMIC_RG_XO_EXTBUF3_HD,
+ PMIC_RG_XO_EXTBUF6_HD,
+ PMIC_RG_XO_EXTBUF7_HD,
+ PMIC_XO_STA_CTL_MAN,
+ PMIC_XO_STA_CTL_M,
+ PMIC_XO_VBBCK_EN_MAN,
+ PMIC_XO_VBBCK_EN_M,
+ PMIC_XO_VRFCK_EN_MAN,
+ PMIC_XO_VRFCK_EN_M,
+ PMIC_XO_RESERVED2,
+ PMIC_RG_XO_RESERVED1,
+ PMIC_RG_XO_RESERVED2,
+ PMIC_XO_STATIC_AUXOUT_SEL,
+ PMIC_XO_AUXOUT_SEL,
+ PMIC_XO_STATIC_AUXOUT,
+ PMIC_RG_XO_PCTAT_BG_EN,
+ PMIC_RG_XO_PCTAT_RPTAT_SEL,
+ PMIC_RG_XO_PCTAT_IPTAT_SEL,
+ PMIC_RG_XO_PCTAT_RCTAT_SEL,
+ PMIC_RG_XO_PCTAT_ICTAT_SEL,
+ PMIC_RG_XO_CBANK_SYNC_BYP,
+ PMIC_RG_XO_PCTAT_VCTAT_SEL,
+ PMIC_RG_XO_PCTAT_VTEMP,
+ PMIC_RG_XO_CORE_LPM_PMICBIAS,
+ PMIC_RG_XO_EXTBUF1_RSEL,
+ PMIC_RG_XO_EXTBUF2_RSEL,
+ PMIC_RG_XO_EXTBUF3_RSEL,
+ PMIC_RG_XO_EXTBUF4_RSEL,
+ PMIC_RG_XO_EXTBUF7_RSEL,
+ PMIC_DCXO_ELR_LEN,
+ PMIC_RG_XO_DIG26M_DIV2,
+ PMIC_XO_PWRKEY_RSTB_SEL,
+ PMIC_XO_ELR_RESERVED,
+ PMIC_PSC_TOP_ANA_ID,
+ PMIC_PSC_TOP_DIG_ID,
+ PMIC_PSC_TOP_ANA_MINOR_REV,
+ PMIC_PSC_TOP_ANA_MAJOR_REV,
+ PMIC_PSC_TOP_DIG_MINOR_REV,
+ PMIC_PSC_TOP_DIG_MAJOR_REV,
+ PMIC_PSC_TOP_CBS,
+ PMIC_PSC_TOP_BIX,
+ PMIC_PSC_TOP_ESP,
+ PMIC_PSC_TOP_FPI,
+ PMIC_PSC_TOP_CLK_OFFSET,
+ PMIC_PSC_TOP_RST_OFFSET,
+ PMIC_PSC_TOP_INT_OFFSET,
+ PMIC_PSC_TOP_INT_LEN,
+ PMIC_RG_CHRDET_32K_CK_PDN,
+ PMIC_RG_STRUP_LONG_PRESS_RST,
+ PMIC_RG_PSEQ_PWRMSK_RST_SEL,
+ PMIC_BANK_STRUP_SWRST,
+ PMIC_BANK_PSEQ_SWRST,
+ PMIC_BANK_CHRDET_SWRST,
+ PMIC_RG_CHRDET_RST,
+ PMIC_RG_INT_EN_ENB_R,
+ PMIC_RG_INT_EN_PMIC_RESET_B_H2L,
+ PMIC_RG_INT_EN_NI_LBAT_INT,
+ PMIC_RG_INT_EN_CHRDET,
+ PMIC_RG_INT_EN_CHRDET_EDGE,
+ PMIC_PSC_INT_CON0_SET,
+ PMIC_PSC_INT_CON0_CLR,
+ PMIC_RG_INT_MASK_ENB_R,
+ PMIC_RG_INT_MASK_PMIC_RESET_B_H2L,
+ PMIC_RG_INT_MASK_NI_LBAT_INT,
+ PMIC_RG_INT_MASK_CHRDET,
+ PMIC_RG_INT_MASK_CHRDET_EDGE,
+ PMIC_PSC_INT_MASK_CON0_SET,
+ PMIC_PSC_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_ENB_R,
+ PMIC_RG_INT_STATUS_PMIC_RESET_B_H2L,
+ PMIC_RG_INT_STATUS_NI_LBAT_INT,
+ PMIC_RG_INT_STATUS_CHRDET,
+ PMIC_RG_INT_STATUS_CHRDET_EDGE,
+ PMIC_RG_INT_RAW_STATUS_ENB_R,
+ PMIC_RG_INT_RAW_STATUS_PMIC_RESET_B_H2L,
+ PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT,
+ PMIC_RG_INT_RAW_STATUS_CHRDET,
+ PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE,
+ PMIC_RG_PSC_INT_POLARITY,
+ PMIC_INT_MISC_CON_SET,
+ PMIC_INT_MISC_CON_CLR,
+ PMIC_RG_PSC_MON_GRP_SEL,
+ PMIC_RG_MBS_PSC_KEY,
+ PMIC_STRUP_ANA_ID,
+ PMIC_STRUP_DIG_ID,
+ PMIC_STRUP_ANA_MINOR_REV,
+ PMIC_STRUP_ANA_MAJOR_REV,
+ PMIC_STRUP_DIG_MINOR_REV,
+ PMIC_STRUP_DIG_MAJOR_REV,
+ PMIC_STRUP_CBS,
+ PMIC_STRUP_BIX,
+ PMIC_STRUP_DSN_ESP,
+ PMIC_STRUP_DSN_FPI,
+ PMIC_RG_TM_OUT,
+ PMIC_RG_THR_TMODE,
+ PMIC_RG_THRDET_SEL,
+ PMIC_RG_STRUP_THR_SEL,
+ PMIC_RG_VREF_BG,
+ PMIC_RG_RST_DRVSEL,
+ PMIC_RG_PMU_RSV,
+ PMIC_RG_PMU_RSV1,
+ PMIC_RG_PMU_RSV2,
+ PMIC_RGS_ANA_CHIP_ID,
+ PMIC_RGS_VUSB_PG_STATUS,
+ PMIC_RGS_VAUX18_PG_STATUS,
+ PMIC_RGS_VAUD28_PG_STATUS,
+ PMIC_RGS_VXO22_PG_STATUS,
+ PMIC_RGS_VEMC_PG_STATUS,
+ PMIC_RGS_VIO18_PG_STATUS,
+ PMIC_RGS_VIO33_PG_STATUS,
+ PMIC_RGS_VSRAM_PROC_PG_STATUS,
+ PMIC_RGS_VA12_PG_STATUS,
+ PMIC_RGS_VA09_PG_STATUS,
+ PMIC_RGS_VRFCK_PG_STATUS,
+ PMIC_RGS_VRFCK_1_PG_STATUS,
+ PMIC_RGS_VBBCK_PG_STATUS,
+ PMIC_RGS_VRTC28_PG_STATUS,
+ PMIC_RGS_VS1_PG_STATUS,
+ PMIC_RGS_VMODEM_PG_STATUS,
+ PMIC_RGS_VPROC_PG_STATUS,
+ PMIC_RGS_VCORE_PG_STATUS,
+ PMIC_RGS_VSRAM_OTHERS_PG_STATUS,
+ PMIC_RGS_VDRAM1_PG_STATUS,
+ PMIC_RGS_VDRAM2_PG_STATUS,
+ PMIC_RGS_VS2_PG_STATUS,
+ PMIC_STRUP_ELR_LEN,
+ PMIC_RG_STRUP_IREF_TRIM,
+ PMIC_RG_THR_LOC_SEL,
+ PMIC_RG_THR1_140_TRIM,
+ PMIC_RG_THR1_RSV0,
+ PMIC_RG_THR1_110_TRIM,
+ PMIC_RG_THR1_RSV1,
+ PMIC_RG_THR2_140_TRIM,
+ PMIC_RG_THR2_RSV0,
+ PMIC_RG_THR2_110_TRIM,
+ PMIC_RG_THR2_RSV1,
+ PMIC_RG_THR3_140_TRIM,
+ PMIC_RG_THR3_RSV0,
+ PMIC_RG_THR3_110_TRIM,
+ PMIC_RG_THR3_RSV1,
+ PMIC_RG_THR4_140_TRIM,
+ PMIC_RG_THR4_RSV0,
+ PMIC_RG_THR4_110_TRIM,
+ PMIC_RG_THR4_RSV1,
+ PMIC_PSEQ_ANA_ID,
+ PMIC_PSEQ_DIG_ID,
+ PMIC_PSEQ_ANA_MINOR_REV,
+ PMIC_PSEQ_ANA_MAJOR_REV,
+ PMIC_PSEQ_DIG_MINOR_REV,
+ PMIC_PSEQ_DIG_MAJOR_REV,
+ PMIC_PSEQ_CBS,
+ PMIC_PSEQ_BIX,
+ PMIC_PSEQ_ESP,
+ PMIC_PSEQ_FPI,
+ PMIC_RG_USBDL_MODE,
+ PMIC_RG_WDTRST_ACT,
+ PMIC_RG_CRST,
+ PMIC_RG_WRST,
+ PMIC_RG_CRST_INTV,
+ PMIC_RG_WRST_INTV,
+ PMIC_RG_WDTRST_EN,
+ PMIC_RG_KEYPWR_VCORE_OPT,
+ PMIC_RG_KEYPWR_VXO22_OPT,
+ PMIC_RG_KEYPWR_VIO18_OPT,
+ PMIC_RG_RSV_SWREG,
+ PMIC_RG_STRUP_THR_CLR,
+ PMIC_RG_UVLO_DEC_EN,
+ PMIC_RG_POR_FLAG,
+ PMIC_RGS_CHRDET,
+ PMIC_USBDL,
+ PMIC_RG_STRUP_THER_DEB_RTD,
+ PMIC_RG_STRUP_THER_DEB_FTD,
+ PMIC_RG_STRUP_EXT_PMIC_EN,
+ PMIC_RG_STRUP_EXT_PMIC_SEL,
+ PMIC_RGS_EXT_PMIC_PG,
+ PMIC_DA_EXT_PMIC_EN1,
+ PMIC_DA_EXT_PMIC_EN2,
+ PMIC_RG_EXT_PMIC_PG_DEBTD,
+ PMIC_RG_RTC_SPAR_DEB_EN,
+ PMIC_RG_RTC_ALARM_DEB_EN,
+ PMIC_RG_STRUP_VIO33_PG_H2L_EN,
+ PMIC_RG_STRUP_VEMC_PG_H2L_EN,
+ PMIC_RG_STRUP_VIO18_PG_H2L_EN,
+ PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN,
+ PMIC_RG_STRUP_VPROC_PG_H2L_EN,
+ PMIC_RG_STRUP_VA12_PG_H2L_EN,
+ PMIC_RG_STRUP_VA09_PG_H2L_EN,
+ PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN,
+ PMIC_RG_STRUP_VBBCK_PG_H2L_EN,
+ PMIC_RG_STRUP_VRFCK_PG_H2L_EN,
+ PMIC_RG_STRUP_VS1_PG_H2L_EN,
+ PMIC_RG_STRUP_VMODEM_PG_H2L_EN,
+ PMIC_RG_STRUP_VCORE_PG_H2L_EN,
+ PMIC_RG_STRUP_VS2_PG_H2L_EN,
+ PMIC_RG_STRUP_VRTC_PG_H2L_EN,
+ PMIC_RG_STRUP_VAUX18_PG_H2L_EN,
+ PMIC_RG_STRUP_VAUD28_PG_H2L_EN,
+ PMIC_RG_STRUP_VUSB_PG_H2L_EN,
+ PMIC_RG_STRUP_VDRAM2_PG_H2L_EN,
+ PMIC_RG_STRUP_VDRAM1_PG_H2L_EN,
+ PMIC_RG_STRUP_RSV0_00_ENB,
+ PMIC_RG_STRUP_RSV0_01_ENB,
+ PMIC_RG_STRUP_RSV0_02_ENB,
+ PMIC_RG_STRUP_RSV0_03_ENB,
+ PMIC_RG_STRUP_RSV0_04_ENB,
+ PMIC_RG_STRUP_RSV0_05_ENB,
+ PMIC_RG_STRUP_RSV0_06_ENB,
+ PMIC_RG_STRUP_RSV0_07_ENB,
+ PMIC_RG_STRUP_RSV0_08_ENB,
+ PMIC_RG_STRUP_RSV0_09_ENB,
+ PMIC_RG_STRUP_RSV0_10_ENB,
+ PMIC_RG_STRUP_RSV0_11_ENB,
+ PMIC_RG_STRUP_RSV0_12_ENB,
+ PMIC_RG_STRUP_RSV0_13_ENB,
+ PMIC_RG_STRUP_RSV0_14_ENB,
+ PMIC_RG_STRUP_RSV0_15_ENB,
+ PMIC_RG_STRUP_RSV0_20_ENB,
+ PMIC_RG_STRUP_RSV0_19_ENB,
+ PMIC_RG_STRUP_RSV0_18_ENB,
+ PMIC_RG_STRUP_RSV0_17_ENB,
+ PMIC_RG_STRUP_RSV0_16_ENB,
+ PMIC_RG_STRUP_RSV1_00_ENB,
+ PMIC_RG_STRUP_RSV1_01_ENB,
+ PMIC_RG_STRUP_RSV1_02_ENB,
+ PMIC_RG_STRUP_VPROC_OC_ENB,
+ PMIC_RG_STRUP_RSV1_04_ENB,
+ PMIC_RG_STRUP_RSV1_05_ENB,
+ PMIC_RG_STRUP_VSRAM_OTHERS_OC_ENB,
+ PMIC_RG_STRUP_RSV1_07_ENB,
+ PMIC_RG_STRUP_RSV1_08_ENB,
+ PMIC_RG_STRUP_VS1_OC_ENB,
+ PMIC_RG_STRUP_VMODEM_OC_ENB,
+ PMIC_RG_STRUP_VCORE_OC_ENB,
+ PMIC_RG_STRUP_VS2_OC_ENB,
+ PMIC_RG_STRUP_VRTC_OC_ENB,
+ PMIC_RG_STRUP_RSV1_14_ENB,
+ PMIC_RG_STRUP_RSV1_15_ENB,
+ PMIC_RG_STRUP_RSV1_19_ENB,
+ PMIC_RG_STRUP_RSV1_18_ENB,
+ PMIC_RG_STRUP_RSV1_17_ENB,
+ PMIC_RG_STRUP_VDRAM1_OC_ENB,
+ PMIC_RG_STRUP_RSV1_16_ENB,
+ PMIC_RG_PSEQ_FORCE_ON,
+ PMIC_RG_PSEQ_FORCE_TEST_EN,
+ PMIC_RG_PSEQ_BYPASS_DEB,
+ PMIC_RG_PSEQ_BYPASS_SEQ,
+ PMIC_RG_PSEQ_LPBWDT_ACC,
+ PMIC_RG_PSEQ_FORCE_ALL_DOFF,
+ PMIC_RG_PSEQ_PG_CK_SEL,
+ PMIC_RG_THM_SHDN_EN,
+ PMIC_RG_STRUP_UVLO_U1U2_SEL,
+ PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL,
+ PMIC_RG_THR_TEST,
+ PMIC_RG_STRUP_ENVTEM,
+ PMIC_RG_STRUP_ENVTEM_CTRL,
+ PMIC_DDUVLO_DEB_EN,
+ PMIC_RG_STRUP_FT_CTRL,
+ PMIC_RG_BIASGEN_FORCE,
+ PMIC_RG_STRUP_PWRON,
+ PMIC_RG_STRUP_PWRON_SEL,
+ PMIC_RG_BIASGEN,
+ PMIC_RG_BIASGEN_SEL,
+ PMIC_RG_DCXO_PMU_CKEN,
+ PMIC_RG_DCXO_PMU_CKEN_SEL,
+ PMIC_STRUP_DIG_IO_PG_FORCE,
+ PMIC_RG_ATST_PG_CHK,
+ PMIC_RG_STRUP_PG_DEB_MODE,
+ PMIC_RG_OVLO_FCMPL_SW_SEL,
+ PMIC_RG_OVLO_FCMPL_SW,
+ PMIC_RG_UVLO_VSYS_VTH_SW_SEL,
+ PMIC_RG_UVLO_VSYS_VTH_SW,
+ PMIC_RG_STATUS_B,
+ PMIC_RG_TPO_REF_ENB,
+ PMIC_RG_TPO_REF_ENB_SW_MODE,
+ PMIC_RG_BYPASS_CLROC,
+ PMIC_RG_PMIC_ENB_DEB_SEL,
+ PMIC_RG_PMIC_ENB_DLY_SEL,
+ PMIC_RG_PMIC_RESET_B_DEB_SEL,
+ PMIC_RG_PMIC_RESET_B_DLY_SEL,
+ PMIC_RG_CPS_W_KEY,
+ PMIC_RG_SLOT_INTV_DOWN,
+ PMIC_RG_DSEQ_LEN,
+ PMIC_RG_VXO22_DSA,
+ PMIC_RG_VAUX18_DSA,
+ PMIC_RG_VRTC_DSA,
+ PMIC_RG_VS2_DSA,
+ PMIC_RG_VCORE_DSA,
+ PMIC_RG_VMODEM_DSA,
+ PMIC_RG_VS1_DSA,
+ PMIC_RG_VRFCK_DSA,
+ PMIC_RG_VBBCK_DSA,
+ PMIC_RG_VSRAM_OTHERS_DSA,
+ PMIC_RG_VA09_DSA,
+ PMIC_RG_VA12_DSA,
+ PMIC_RG_VPROC_DSA,
+ PMIC_RG_VSRAM_PROC_DSA,
+ PMIC_RG_VIO18_DSA,
+ PMIC_RG_VEMC_DSA,
+ PMIC_RG_VIO33_DSA,
+ PMIC_RG_VDRAM1_DSA,
+ PMIC_RG_VDRAM2_DSA,
+ PMIC_RG_VUSB_DSA,
+ PMIC_RG_VAUD28_DSA,
+ PMIC_PSEQ_ELR_LEN,
+ PMIC_RG_BWDT_EN,
+ PMIC_RG_BWDT_TSEL,
+ PMIC_RG_PSEQ_ELR_RSV1,
+ PMIC_RG_BWDT_TD,
+ PMIC_RG_BWDT_CHRTD,
+ PMIC_RG_BWDT_DDLO_TD,
+ PMIC_RG_SLOT_INTV_UP,
+ PMIC_RG_SEQ_LEN,
+ PMIC_RG_PSEQ_ELR_RSV0,
+ PMIC_RG_PSPG_SHDN_ENB,
+ PMIC_RG_PSEQ_F32K_FORCE,
+ PMIC_RG_STRUP_VDRAM1_PG_ENB,
+ PMIC_RG_SMPS_IVGEN_SEL,
+ PMIC_RG_CPS_S0EXT_ENB,
+ PMIC_RG_CPS_S0EXT_TD,
+ PMIC_RG_SDN_DLY_ENB,
+ PMIC_RG_STRUP_VDRAM2_PG_ENB,
+ PMIC_RG_LDO_PG_STB_MODE,
+ PMIC_RG_STRUP_EXT_PMIC_PG_ENB,
+ PMIC_RG_PROTECT_DIS,
+ PMIC_RG_STRUP_VEMC_PG_ENB,
+ PMIC_RG_STRUP_VIO18_PG_ENB,
+ PMIC_RG_STRUP_VSRAM_PROC_PG_ENB,
+ PMIC_RG_STRUP_VPROC_PG_ENB,
+ PMIC_RG_STRUP_VA12_PG_ENB,
+ PMIC_RG_STRUP_VA09_PG_ENB,
+ PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB,
+ PMIC_RG_STRUP_VBBCK_PG_ENB,
+ PMIC_RG_STRUP_VRFCK_PG_ENB,
+ PMIC_RG_STRUP_VS1_PG_ENB,
+ PMIC_RG_STRUP_VMODEM_PG_ENB,
+ PMIC_RG_STRUP_VCORE_PG_ENB,
+ PMIC_RG_STRUP_VS2_PG_ENB,
+ PMIC_RG_STRUP_VRTC_PG_ENB,
+ PMIC_RG_STRUP_VAUX18_PG_ENB,
+ PMIC_RG_STRUP_VXO22_PG_ENB,
+ PMIC_RG_STRUP_VEMC_OC_ENB,
+ PMIC_RG_STRUP_VIO18_OC_ENB,
+ PMIC_RG_STRUP_VSRAM_PROC_OC_ENB,
+ PMIC_RG_STRUP_VAUX18_OC_ENB,
+ PMIC_RG_STRUP_VA12_OC_ENB,
+ PMIC_RG_STRUP_VA09_OC_ENB,
+ PMIC_RG_STRUP_VXO22_OC_ENB,
+ PMIC_RG_STRUP_VBBCK_OC_ENB,
+ PMIC_RG_STRUP_VRFCK_OC_ENB,
+ PMIC_RG_STRUP_VAUD28_OC_ENB,
+ PMIC_RG_STRUP_VUSB_OC_ENB,
+ PMIC_RG_STRUP_VDRAM2_OC_ENB,
+ PMIC_RG_STRUP_VIO33_OC_ENB,
+ PMIC_RG_STRUP_VUSB_PG_ENB,
+ PMIC_RG_STRUP_VIO33_PG_ENB,
+ PMIC_RG_STRUP_VAUD28_PG_ENB,
+ PMIC_RG_VXO22_USA,
+ PMIC_RG_VAUX18_USA,
+ PMIC_RG_VRTC_USA,
+ PMIC_RG_VS2_USA,
+ PMIC_RG_VCORE_USA,
+ PMIC_RG_VMODEM_USA,
+ PMIC_RG_VS1_USA,
+ PMIC_RG_VRFCK_USA,
+ PMIC_RG_VBBCK_USA,
+ PMIC_RG_VSRAM_OTHERS_USA,
+ PMIC_RG_VA09_USA,
+ PMIC_RG_VA12_USA,
+ PMIC_RG_VPROC_USA,
+ PMIC_RG_VSRAM_PROC_USA,
+ PMIC_RG_VIO18_USA,
+ PMIC_RG_VEMC_USA,
+ PMIC_RG_VIO33_USA,
+ PMIC_RG_VDRAM1_USA,
+ PMIC_RG_VDRAM2_USA,
+ PMIC_RG_VUSB_USA,
+ PMIC_RG_VAUD28_USA,
+ PMIC_CHRDET_ANA_ID,
+ PMIC_CHRDET_DIG_ID,
+ PMIC_CHRDET_ANA_MINOR_REV,
+ PMIC_CHRDET_ANA_MAJOR_REV,
+ PMIC_CHRDET_DIG_MINOR_REV,
+ PMIC_CHRDET_DIG_MAJOR_REV,
+ PMIC_CHRDET_CBS,
+ PMIC_CHRDET_BIX,
+ PMIC_CHRDET_ESP,
+ PMIC_CHRDET_FPI,
+ PMIC_RG_BGR_TEST_RSTB,
+ PMIC_RG_BGR_TEST_EN,
+ PMIC_RG_BGR_UNCHOP,
+ PMIC_RG_BGR_UNCHOP_PH,
+ PMIC_RG_UVLO_VTHL,
+ PMIC_RG_OVLO_VTH_SEL,
+ PMIC_RG_LBAT_INT_VTH,
+ PMIC_RG_PCHR_RV,
+ PMIC_RG_VCDT_EN,
+ PMIC_CHRDET_ELR_LEN,
+ PMIC_RG_BGR_TRIM,
+ PMIC_RG_BGR_TRIM_EN,
+ PMIC_RG_BGR_RSEL,
+ PMIC_RG_OVLO_EN,
+ PMIC_RG_VCDT_VTH_TRIM,
+ PMIC_HK_TOP_ANA_ID,
+ PMIC_HK_TOP_DIG_ID,
+ PMIC_HK_TOP_ANA_MINOR_REV,
+ PMIC_HK_TOP_ANA_MAJOR_REV,
+ PMIC_HK_TOP_DIG_MINOR_REV,
+ PMIC_HK_TOP_DIG_MAJOR_REV,
+ PMIC_HK_TOP_CBS,
+ PMIC_HK_TOP_BIX,
+ PMIC_HK_TOP_ESP,
+ PMIC_HK_TOP_FPI,
+ PMIC_HK_CLK_OFFSET,
+ PMIC_HK_RST_OFFSET,
+ PMIC_HK_INT_OFFSET,
+ PMIC_HK_INT_LEN,
+ PMIC_RG_AUXADC_26M_CK_PDN_HWEN,
+ PMIC_RG_AUXADC_26M_CK_PDN,
+ PMIC_RG_AUXADC_CK_PDN_HWEN,
+ PMIC_RG_AUXADC_CK_PDN,
+ PMIC_RG_AUXADC_RNG_CK_PDN_HWEN,
+ PMIC_RG_AUXADC_RNG_CK_PDN,
+ PMIC_RG_AUXADC_1M_CK_PDN,
+ PMIC_RG_AUXADC_32K_CK_PDN,
+ PMIC_RG_HK_INTRP_CK_PDN_HWEN,
+ PMIC_RG_HK_INTRP_CK_PDN,
+ PMIC_RG_AUXADC_26M_CK_TSTSEL,
+ PMIC_RG_AUXADC_CK_TSTSEL,
+ PMIC_RG_AUXADC_RNG_CK_TSTSEL,
+ PMIC_RG_AUXADC_1M_CK_TSTSEL,
+ PMIC_RG_AUXADC_32K_CK_TSTSEL,
+ PMIC_RG_HK_INTRP_CK_TSTSEL,
+ PMIC_RG_AUXADC_RST,
+ PMIC_RG_AUXADC_REG_RST,
+ PMIC_BANK_HK_TOP_SWRST,
+ PMIC_BANK_AUXADC_SWRST,
+ PMIC_BANK_AUXADC_DIG_1_SWRST,
+ PMIC_BANK_AUXADC_DIG_2_SWRST,
+ PMIC_BANK_AUXADC_DIG_3_SWRST,
+ PMIC_BANK_AUXADC_DIG_4_SWRST,
+ PMIC_BANK_AUXADC_DIG_5_SWRST,
+ PMIC_BANK_AUXADC_DIG_6_SWRST,
+ PMIC_BANK_AUXADC_DIG_7_SWRST,
+ PMIC_BANK_AUXADC_DIG_8_SWRST,
+ PMIC_BANK_AUXADC_DIG_9_SWRST,
+ PMIC_RG_INT_EN_BAT_H,
+ PMIC_RG_INT_EN_BAT_L,
+ PMIC_RG_INT_EN_BAT2_H,
+ PMIC_RG_INT_EN_BAT2_L,
+ PMIC_RG_INT_EN_BAT_TEMP_H,
+ PMIC_RG_INT_EN_BAT_TEMP_L,
+ PMIC_RG_INT_EN_THR_H,
+ PMIC_RG_INT_EN_THR_L,
+ PMIC_RG_INT_EN_AUXADC_IMP,
+ PMIC_RG_INT_EN_NAG_C_DLTV,
+ PMIC_HK_INT_CON0_SET,
+ PMIC_HK_INT_CON0_CLR,
+ PMIC_RG_INT_EN_INTER1_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER1_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER2_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER2_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER3_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER3_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER4_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER4_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER5_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER5_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER6_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER6_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER7_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER7_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER8_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER8_DET_DIV_L,
+ PMIC_HK_INT_CON1_SET,
+ PMIC_HK_INT_CON1_CLR,
+ PMIC_RG_INT_EN_INTER9_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER9_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER10_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER10_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER11_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER11_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER12_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER12_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER13_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER13_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER14_DET_DIV_H,
+ PMIC_RG_INT_EN_INTER14_DET_DIV_L,
+ PMIC_RG_INT_EN_INTER1_DET_H,
+ PMIC_RG_INT_EN_INTER1_DET_L,
+ PMIC_HK_INT_CON2_SET,
+ PMIC_HK_INT_CON2_CLR,
+ PMIC_RG_INT_EN_INTER2_DET_H,
+ PMIC_RG_INT_EN_INTER2_DET_L,
+ PMIC_RG_INT_EN_INTER3_DET_H,
+ PMIC_RG_INT_EN_INTER3_DET_L,
+ PMIC_RG_INT_EN_INTER4_DET_H,
+ PMIC_RG_INT_EN_INTER4_DET_L,
+ PMIC_RG_INT_EN_INTER5_DET_H,
+ PMIC_RG_INT_EN_INTER5_DET_L,
+ PMIC_RG_INT_EN_INTER6_DET_H,
+ PMIC_RG_INT_EN_INTER6_DET_L,
+ PMIC_RG_INT_EN_INTER7_DET_H,
+ PMIC_RG_INT_EN_INTER7_DET_L,
+ PMIC_RG_INT_EN_INTER8_DET_H,
+ PMIC_RG_INT_EN_INTER8_DET_L,
+ PMIC_RG_INT_EN_INTER9_DET_H,
+ PMIC_RG_INT_EN_INTER9_DET_L,
+ PMIC_HK_INT_CON3_SET,
+ PMIC_HK_INT_CON3_CLR,
+ PMIC_RG_INT_MASK_BAT_H,
+ PMIC_RG_INT_MASK_BAT_L,
+ PMIC_RG_INT_MASK_BAT2_H,
+ PMIC_RG_INT_MASK_BAT2_L,
+ PMIC_RG_INT_MASK_BAT_TEMP_H,
+ PMIC_RG_INT_MASK_BAT_TEMP_L,
+ PMIC_RG_INT_MASK_THR_H,
+ PMIC_RG_INT_MASK_THR_L,
+ PMIC_RG_INT_MASK_AUXADC_IMP,
+ PMIC_RG_INT_MASK_NAG_C_DLTV,
+ PMIC_HK_INT_MASK_CON0_SET,
+ PMIC_HK_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_MASK_INTER1_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER1_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER2_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER2_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER3_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER3_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER4_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER4_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER5_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER5_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER6_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER6_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER7_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER7_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER8_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER8_DET_DIV_L,
+ PMIC_HK_INT_MASK_CON1_SET,
+ PMIC_HK_INT_MASK_CON1_CLR,
+ PMIC_RG_INT_MASK_INTER9_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER9_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER10_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER10_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER11_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER11_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER12_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER12_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER13_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER13_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER14_DET_DIV_H,
+ PMIC_RG_INT_MASK_INTER14_DET_DIV_L,
+ PMIC_RG_INT_MASK_INTER1_DET_H,
+ PMIC_RG_INT_MASK_INTER1_DET_L,
+ PMIC_HK_INT_MASK_CON2_SET,
+ PMIC_HK_INT_MASK_CON2_CLR,
+ PMIC_RG_INT_MASK_INTER2_DET_H,
+ PMIC_RG_INT_MASK_INTER2_DET_L,
+ PMIC_RG_INT_MASK_INTER3_DET_H,
+ PMIC_RG_INT_MASK_INTER3_DET_L,
+ PMIC_RG_INT_MASK_INTER4_DET_H,
+ PMIC_RG_INT_MASK_INTER4_DET_L,
+ PMIC_RG_INT_MASK_INTER5_DET_H,
+ PMIC_RG_INT_MASK_INTER5_DET_L,
+ PMIC_RG_INT_MASK_INTER6_DET_H,
+ PMIC_RG_INT_MASK_INTER6_DET_L,
+ PMIC_RG_INT_MASK_INTER7_DET_H,
+ PMIC_RG_INT_MASK_INTER7_DET_L,
+ PMIC_RG_INT_MASK_INTER8_DET_H,
+ PMIC_RG_INT_MASK_INTER8_DET_L,
+ PMIC_RG_INT_MASK_INTER9_DET_H,
+ PMIC_RG_INT_MASK_INTER9_DET_L,
+ PMIC_HK_INT_MASK_CON3_SET,
+ PMIC_HK_INT_MASK_CON3_CLR,
+ PMIC_RG_INT_STATUS_BAT_H,
+ PMIC_RG_INT_STATUS_BAT_L,
+ PMIC_RG_INT_STATUS_BAT2_H,
+ PMIC_RG_INT_STATUS_BAT2_L,
+ PMIC_RG_INT_STATUS_BAT_TEMP_H,
+ PMIC_RG_INT_STATUS_BAT_TEMP_L,
+ PMIC_RG_INT_STATUS_THR_H,
+ PMIC_RG_INT_STATUS_THR_L,
+ PMIC_RG_INT_STATUS_AUXADC_IMP,
+ PMIC_RG_INT_STATUS_NAG_C_DLTV,
+ PMIC_RG_INT_STATUS_INTER1_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER1_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER2_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER2_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER3_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER3_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER4_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER4_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER5_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER5_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER6_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER6_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER7_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER7_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER8_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER8_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER9_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER9_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER10_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER10_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER11_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER11_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER12_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER12_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER13_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER13_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER14_DET_DIV_H,
+ PMIC_RG_INT_STATUS_INTER14_DET_DIV_L,
+ PMIC_RG_INT_STATUS_INTER1_DET_H,
+ PMIC_RG_INT_STATUS_INTER1_DET_L,
+ PMIC_RG_INT_STATUS_INTER2_DET_H,
+ PMIC_RG_INT_STATUS_INTER2_DET_L,
+ PMIC_RG_INT_STATUS_INTER3_DET_H,
+ PMIC_RG_INT_STATUS_INTER3_DET_L,
+ PMIC_RG_INT_STATUS_INTER4_DET_H,
+ PMIC_RG_INT_STATUS_INTER4_DET_L,
+ PMIC_RG_INT_STATUS_INTER5_DET_H,
+ PMIC_RG_INT_STATUS_INTER5_DET_L,
+ PMIC_RG_INT_STATUS_INTER6_DET_H,
+ PMIC_RG_INT_STATUS_INTER6_DET_L,
+ PMIC_RG_INT_STATUS_INTER7_DET_H,
+ PMIC_RG_INT_STATUS_INTER7_DET_L,
+ PMIC_RG_INT_STATUS_INTER8_DET_H,
+ PMIC_RG_INT_STATUS_INTER8_DET_L,
+ PMIC_RG_INT_STATUS_INTER9_DET_H,
+ PMIC_RG_INT_STATUS_INTER9_DET_L,
+ PMIC_RG_INT_RAW_STATUS_BAT_H,
+ PMIC_RG_INT_RAW_STATUS_BAT_L,
+ PMIC_RG_INT_RAW_STATUS_BAT2_H,
+ PMIC_RG_INT_RAW_STATUS_BAT2_L,
+ PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H,
+ PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L,
+ PMIC_RG_INT_RAW_STATUS_THR_H,
+ PMIC_RG_INT_RAW_STATUS_THR_L,
+ PMIC_RG_INT_RAW_STATUS_AUXADC_IMP,
+ PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV,
+ PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER1_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER2_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER3_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER4_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER5_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER6_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER7_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER8_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER9_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER10_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER11_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER12_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER13_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_H,
+ PMIC_RG_INT_RAW_STATUS_INTER14_DET_DIV_L,
+ PMIC_RG_INT_RAW_STATUS_INTER1_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER1_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER2_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER2_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER3_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER3_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER4_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER4_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER5_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER5_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER6_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER6_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER7_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER7_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER8_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER8_DET_L,
+ PMIC_RG_INT_RAW_STATUS_INTER9_DET_H,
+ PMIC_RG_INT_RAW_STATUS_INTER9_DET_L,
+ PMIC_RG_CLK_MON_FLAG_EN,
+ PMIC_RG_CLK_MON_FLAG_SEL,
+ PMIC_RG_INT_MON_FLAG_EN,
+ PMIC_RG_INT_MON_FLAG_SEL,
+ PMIC_RG_HK_MON_FLAG_SEL,
+ PMIC_RG_MON_FLAG_SEL_AUXADC,
+ PMIC_RG_ADCIN_VSEN_MUX_EN,
+ PMIC_RG_BATON_TDET_EN,
+ PMIC_RG_ADCIN_VSEN_EXT_BATON_EN,
+ PMIC_RG_ADCIN_VBAT_EN,
+ PMIC_RG_ADCIN_VSEN_EN,
+ PMIC_RG_ADCIN_CHR_EN,
+ PMIC_RG_AUXADC_DIFFBUF_SWEN,
+ PMIC_RG_AUXADC_DIFFBUF_EN,
+ PMIC_DA_ADCIN_VBAT_EN,
+ PMIC_DA_AUXADC_VBAT_EN,
+ PMIC_DA_ADCIN_VSEN_MUX_EN,
+ PMIC_DA_ADCIN_VSEN_EN,
+ PMIC_DA_ADCIN_CHR_EN,
+ PMIC_DA_BATON_TDET_EN,
+ PMIC_DA_ADCIN_BATID_SW_EN,
+ PMIC_DA_AUXADC_DIFFBUF_EN,
+ PMIC_RG_HK_STRUP_AUXADC_START_SW,
+ PMIC_RG_HK_STRUP_AUXADC_RSTB_SW,
+ PMIC_RG_HK_STRUP_AUXADC_START_SEL,
+ PMIC_RG_HK_STRUP_AUXADC_RSTB_SEL,
+ PMIC_RG_HK_STRUP_AUXADC_RPCNT_MAX,
+ PMIC_RG_VAUX18_AUXADC_STB_SWEN,
+ PMIC_RG_VAUX18_AUXADC_STB_EN,
+ PMIC_RG_VAUX18_AUXADC_ACK_SWEN,
+ PMIC_RG_VAUX18_AUXADC_ACK_EN,
+ PMIC_RG_VBIF28_AUXADC_STB_SWEN,
+ PMIC_RG_VBIF28_AUXADC_STB_EN,
+ PMIC_RG_VBIF28_AUXADC_ACK_SWEN,
+ PMIC_RG_VBIF28_AUXADC_ACK_EN,
+ PMIC_RG_VTREF_AUXADC_STB_SWEN,
+ PMIC_RG_VTREF_AUXADC_STB_EN,
+ PMIC_RG_VTREF_AUXADC_ACK_SWEN,
+ PMIC_RG_VTREF_AUXADC_ACK_EN,
+ PMIC_RG_VTREF_AUXADC_PWDB_SWEN,
+ PMIC_RG_VTREF_AUXADC_PWDB_EN,
+ PMIC_RG_VTREF_AUXADC_REQ_SWEN,
+ PMIC_RG_VTREF_AUXADC_REQ_EN,
+ PMIC_DD_AUXADC_VAUX18_REQ,
+ PMIC_DD_VAUX18_AUXADC_STB,
+ PMIC_DD_AUXADC_VAUX18_PWDB,
+ PMIC_DD_VAUX18_AUXADC_ACK,
+ PMIC_DD_AUXADC_VBIF28_REQ,
+ PMIC_DD_VBIF28_AUXADC_STB,
+ PMIC_DD_AUXADC_VBIF28_PWDB,
+ PMIC_DD_VBIF28_AUXADC_ACK,
+ PMIC_DD_AUXADC_VTREF_REQ,
+ PMIC_DD_VTREF_AUXADC_STB,
+ PMIC_DD_AUXADC_VTREF_PWDB,
+ PMIC_DD_VTREF_AUXADC_ACK,
+ PMIC_HK_AUXADC_KEY,
+ PMIC_AUXADC_ANA_ID,
+ PMIC_AUXADC_DIG_ID,
+ PMIC_AUXADC_ANA_MINOR_REV,
+ PMIC_AUXADC_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_MAJOR_REV,
+ PMIC_AUXADC_DSN_CBS,
+ PMIC_AUXADC_DSN_BIX,
+ PMIC_AUXADC_DSN_ESP,
+ PMIC_AUXADC_DSN_FPI,
+ PMIC_RG_AUX_RSV,
+ PMIC_RG_AUXADC_CALI,
+ PMIC_RG_VBUF_BYP,
+ PMIC_RG_VBUF_CALEN,
+ PMIC_RG_VBUF_EXTEN,
+ PMIC_RG_AUXADC_RNG_EN,
+ PMIC_RG_AUXADC_NOISE_RES,
+ PMIC_AUXADC_DIG_1_ANA_ID,
+ PMIC_AUXADC_DIG_1_DIG_ID,
+ PMIC_AUXADC_DIG_1_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_1_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_1_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_1_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_1_DSN_CBS,
+ PMIC_AUXADC_DIG_1_DSN_BIX,
+ PMIC_AUXADC_DIG_1_DSN_ESP,
+ PMIC_AUXADC_DIG_1_DSN_FPI,
+ PMIC_AUXADC_ADC_OUT_CH0,
+ PMIC_AUXADC_ADC_RDY_CH0,
+ PMIC_AUXADC_ADC_OUT_CH1,
+ PMIC_AUXADC_ADC_RDY_CH1,
+ PMIC_AUXADC_ADC_OUT_CH2,
+ PMIC_AUXADC_ADC_RDY_CH2,
+ PMIC_AUXADC_ADC_OUT_CH3,
+ PMIC_AUXADC_ADC_RDY_CH3,
+ PMIC_AUXADC_ADC_OUT_CH4,
+ PMIC_AUXADC_ADC_RDY_CH4,
+ PMIC_AUXADC_ADC_OUT_CH5,
+ PMIC_AUXADC_ADC_RDY_CH5,
+ PMIC_AUXADC_ADC_OUT_CH6,
+ PMIC_AUXADC_ADC_RDY_CH6,
+ PMIC_AUXADC_ADC_OUT_CH7,
+ PMIC_AUXADC_ADC_RDY_CH7,
+ PMIC_AUXADC_ADC_OUT_CH8,
+ PMIC_AUXADC_ADC_RDY_CH8,
+ PMIC_AUXADC_ADC_OUT_CH9,
+ PMIC_AUXADC_ADC_RDY_CH9,
+ PMIC_AUXADC_ADC_OUT_CH10,
+ PMIC_AUXADC_ADC_RDY_CH10,
+ PMIC_AUXADC_ADC_OUT_CH11,
+ PMIC_AUXADC_ADC_RDY_CH11,
+ PMIC_AUXADC_ADC_OUT_CH14_15,
+ PMIC_AUXADC_ADC_RDY_CH14_15,
+ PMIC_AUXADC_ADC_OUT_CH7_BY_GPS,
+ PMIC_AUXADC_ADC_RDY_CH7_BY_GPS,
+ PMIC_AUXADC_ADC_OUT_CH7_BY_MD,
+ PMIC_AUXADC_ADC_RDY_CH7_BY_MD,
+ PMIC_AUXADC_ADC_OUT_CH7_BY_AP,
+ PMIC_AUXADC_ADC_RDY_CH7_BY_AP,
+ PMIC_AUXADC_ADC_OUT_CH4_BY_MD,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_MD,
+ PMIC_AUXADC_ADC_OUT_PWRON_PCHR,
+ PMIC_AUXADC_ADC_RDY_PWRON_PCHR,
+ PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR,
+ PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR,
+ PMIC_AUXADC_ADC_OUT_CH0_BY_MD,
+ PMIC_AUXADC_ADC_RDY_CH0_BY_MD,
+ PMIC_AUXADC_ADC_OUT_CH0_BY_AP,
+ PMIC_AUXADC_ADC_RDY_CH0_BY_AP,
+ PMIC_AUXADC_ADC_OUT_CH1_BY_MD,
+ PMIC_AUXADC_ADC_RDY_CH1_BY_MD,
+ PMIC_AUXADC_ADC_OUT_CH1_BY_AP,
+ PMIC_AUXADC_ADC_RDY_CH1_BY_AP,
+ PMIC_AUXADC_ADC_OUT_FGADC_PCHR,
+ PMIC_AUXADC_ADC_RDY_FGADC_PCHR,
+ PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR,
+ PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR,
+ PMIC_AUXADC_ADC_OUT_RAW,
+ PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS,
+ PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS,
+ PMIC_AUXADC_ADC_OUT_DCXO_BY_MD,
+ PMIC_AUXADC_ADC_RDY_DCXO_BY_MD,
+ PMIC_AUXADC_ADC_OUT_DCXO_BY_AP,
+ PMIC_AUXADC_ADC_RDY_DCXO_BY_AP,
+ PMIC_AUXADC_ADC_OUT_BATID,
+ PMIC_AUXADC_ADC_RDY_BATID,
+ PMIC_AUXADC_ADC_OUT_CH4_BY_THR1,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR1,
+ PMIC_AUXADC_ADC_OUT_CH4_BY_THR2,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR2,
+ PMIC_AUXADC_ADC_OUT_CH4_BY_THR3,
+ PMIC_AUXADC_ADC_RDY_CH4_BY_THR3,
+ PMIC_AUXADC_ADC_OUT_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_RDY_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_OUT_DCXO_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_RDY_DCXO_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_OUT_MDRT_MERGE,
+ PMIC_AUXADC_ADC_RDY_MDRT_MERGE,
+ PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MERGE,
+ PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MERGE,
+ PMIC_AUXADC_ADC_BUSY_IN,
+ PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_BUSY_IN_MDRT_WAKEUP,
+ PMIC_AUXADC_ADC_BUSY_IN_WAKEUP,
+ PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP,
+ PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD,
+ PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS,
+ PMIC_AUXADC_ADC_BUSY_IN_SHARE,
+ PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR,
+ PMIC_AUXADC_ADC_BUSY_IN_GPS_AP,
+ PMIC_AUXADC_ADC_BUSY_IN_GPS_MD,
+ PMIC_AUXADC_ADC_BUSY_IN_GPS,
+ PMIC_AUXADC_ADC_BUSY_IN_THR_MD,
+ PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR,
+ PMIC_AUXADC_ADC_BUSY_IN_BATID,
+ PMIC_AUXADC_ADC_BUSY_IN_PWRON,
+ PMIC_AUXADC_ADC_BUSY_IN_THR1,
+ PMIC_AUXADC_ADC_BUSY_IN_THR2,
+ PMIC_AUXADC_ADC_BUSY_IN_THR3,
+ PMIC_AUXADC_SAMPLE_LIST_15_0,
+ PMIC_AUXADC_SAMPLE_LIST_31_16,
+ PMIC_AUXADC_SAMPLE_LIST_47_32,
+ PMIC_AUXADC_SAMPLE_LIST_63_48,
+ PMIC_AUXADC_SAMPLE_LIST_79_64,
+ PMIC_AUXADC_DIG_2_ANA_ID,
+ PMIC_AUXADC_DIG_2_DIG_ID,
+ PMIC_AUXADC_DIG_2_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_2_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_2_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_2_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_2_DSN_CBS,
+ PMIC_AUXADC_DIG_2_DSN_BIX,
+ PMIC_AUXADC_DIG_2_DSN_ESP,
+ PMIC_AUXADC_DIG_2_DSN_FPI,
+ PMIC_AUXADC_RQST_CH0,
+ PMIC_AUXADC_RQST_CH1,
+ PMIC_AUXADC_RQST_CH2,
+ PMIC_AUXADC_RQST_CH3,
+ PMIC_AUXADC_RQST_CH4,
+ PMIC_AUXADC_RQST_CH5,
+ PMIC_AUXADC_RQST_CH6,
+ PMIC_AUXADC_RQST_CH7,
+ PMIC_AUXADC_RQST_CH8,
+ PMIC_AUXADC_RQST_CH9,
+ PMIC_AUXADC_RQST_CH10,
+ PMIC_AUXADC_RQST_CH11,
+ PMIC_AUXADC_RQST_CH12,
+ PMIC_AUXADC_RQST_CH13,
+ PMIC_AUXADC_RQST_CH14,
+ PMIC_AUXADC_RQST_CH15,
+ PMIC_AUXADC_RQST_CH0_BY_MD,
+ PMIC_AUXADC_RQST_CH1_BY_MD,
+ PMIC_AUXADC_RQST_CH4_BY_MD,
+ PMIC_AUXADC_RQST_CH7_BY_MD,
+ PMIC_AUXADC_RQST_CH7_BY_GPS,
+ PMIC_AUXADC_RQST_DCXO_BY_MD,
+ PMIC_AUXADC_RQST_DCXO_BY_GPS,
+ PMIC_AUXADC_RQST_BATID,
+ PMIC_AUXADC_RQST_CH4_BY_THR1,
+ PMIC_AUXADC_RQST_CH4_BY_THR2,
+ PMIC_AUXADC_RQST_CH4_BY_THR3,
+ PMIC_AUXADC_RQST_RSV1,
+ PMIC_AUXADC_RQST_INTER1_DIV,
+ PMIC_AUXADC_RQST_INTER2_DIV,
+ PMIC_AUXADC_RQST_INTER3_DIV,
+ PMIC_AUXADC_RQST_INTER4_DIV,
+ PMIC_AUXADC_RQST_INTER5_DIV,
+ PMIC_AUXADC_RQST_INTER6_DIV,
+ PMIC_AUXADC_RQST_INTER7_DIV,
+ PMIC_AUXADC_RQST_INTER8_DIV,
+ PMIC_AUXADC_RQST_INTER9_DIV,
+ PMIC_AUXADC_RQST_INTER10_DIV,
+ PMIC_AUXADC_RQST_INTER11_DIV,
+ PMIC_AUXADC_RQST_INTER12_DIV,
+ PMIC_AUXADC_RQST_INTER13_DIV,
+ PMIC_AUXADC_RQST_INTER14_DIV,
+ PMIC_AUXADC_RQST_INTER1,
+ PMIC_AUXADC_RQST_INTER2,
+ PMIC_AUXADC_RQST_INTER3,
+ PMIC_AUXADC_RQST_INTER4,
+ PMIC_AUXADC_RQST_INTER5,
+ PMIC_AUXADC_RQST_INTER6,
+ PMIC_AUXADC_RQST_INTER7,
+ PMIC_AUXADC_RQST_INTER8,
+ PMIC_AUXADC_RQST_INTER9,
+ PMIC_AUXADC_RQST_TREF,
+ PMIC_AUXADC_RQST_EXT1,
+ PMIC_AUXADC_RQST_EXT2,
+ PMIC_AUXADC_RQST_EXT3,
+ PMIC_AUXADC_RQST_EXT4,
+ PMIC_AUXADC_RQST_EXT5,
+ PMIC_AUXADC_RQST_EXT6,
+ PMIC_AUXADC_RQST_EXT7,
+ PMIC_AUXADC_RQST_EXT8,
+ PMIC_AUXADC_DIG_3_ANA_ID,
+ PMIC_AUXADC_DIG_3_DIG_ID,
+ PMIC_AUXADC_DIG_3_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_3_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_3_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_3_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_3_DSN_CBS,
+ PMIC_AUXADC_DIG_3_DSN_BIX,
+ PMIC_AUXADC_DIG_3_DSN_ESP,
+ PMIC_AUXADC_DIG_3_DSN_FPI,
+ PMIC_AUXADC_CK_ON_EXTD,
+ PMIC_AUXADC_SRCLKEN_SRC_SEL,
+ PMIC_AUXADC_ADC_PWDB,
+ PMIC_AUXADC_ADC_PWDB_SWCTRL,
+ PMIC_AUXADC_STRUP_CK_ON_ENB,
+ PMIC_AUXADC_SRCLKEN_CK_EN,
+ PMIC_AUXADC_CK_AON_GPS,
+ PMIC_AUXADC_CK_AON_MD,
+ PMIC_AUXADC_CK_AON,
+ PMIC_AUXADC_CON0_SET,
+ PMIC_AUXADC_CON0_CLR,
+ PMIC_AUXADC_AVG_NUM_SMALL,
+ PMIC_AUXADC_AVG_NUM_LARGE,
+ PMIC_AUXADC_SPL_NUM_SMALL,
+ PMIC_AUXADC_AVG_NUM_SEL,
+ PMIC_AUXADC_AVG_NUM_SEL_SHARE,
+ PMIC_AUXADC_AVG_NUM_SEL_LBAT,
+ PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP,
+ PMIC_AUXADC_AVG_NUM_SEL_WAKEUP,
+ PMIC_AUXADC_SPL_NUM_LARGE,
+ PMIC_AUXADC_SPL_NUM_SLEEP,
+ PMIC_AUXADC_SPL_NUM_SLEEP_SEL,
+ PMIC_AUXADC_SPL_NUM_SEL,
+ PMIC_AUXADC_SPL_NUM_SEL_SHARE,
+ PMIC_AUXADC_SPL_NUM_SEL_LBAT,
+ PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP,
+ PMIC_AUXADC_SPL_NUM_SEL_WAKEUP,
+ PMIC_AUXADC_SPL_NUM_CH0,
+ PMIC_AUXADC_SPL_NUM_CH3,
+ PMIC_AUXADC_SPL_NUM_CH7,
+ PMIC_AUXADC_SPL_NUM_CH6,
+ PMIC_AUXADC_SPL_NUM_CH8,
+ PMIC_AUXADC_SPL_NUM_CH12,
+ PMIC_AUXADC_SPL_NUM_CH13,
+ PMIC_AUXADC_AVG_NUM_CH12,
+ PMIC_AUXADC_AVG_NUM_LBAT,
+ PMIC_AUXADC_AVG_NUM_CH7,
+ PMIC_AUXADC_AVG_NUM_CH3,
+ PMIC_AUXADC_AVG_NUM_CH0,
+ PMIC_AUXADC_AVG_NUM_CH13,
+ PMIC_AUXADC_AVG_NUM_HPC,
+ PMIC_AUXADC_AVG_NUM_DCXO,
+ PMIC_AUXADC_AVG_NUM_CH7_WAKEUP,
+ PMIC_AUXADC_AVG_NUM_BTMP,
+ PMIC_AUXADC_AVG_NUM_NAG,
+ PMIC_AUXADC_AVG_NUM_DCXO_WAKEUP,
+ PMIC_AUXADC_AVG_NUM_CH8,
+ PMIC_AUXADC_AVG_NUM_CH6,
+ PMIC_AUXADC_AVG_NUM_ZCV,
+ PMIC_AUXADC_TRIM_CH0_SEL,
+ PMIC_AUXADC_TRIM_CH1_SEL,
+ PMIC_AUXADC_TRIM_CH2_SEL,
+ PMIC_AUXADC_TRIM_CH3_SEL,
+ PMIC_AUXADC_TRIM_CH4_SEL,
+ PMIC_AUXADC_TRIM_CH5_SEL,
+ PMIC_AUXADC_TRIM_CH6_SEL,
+ PMIC_AUXADC_TRIM_CH7_SEL,
+ PMIC_AUXADC_TRIM_CH8_SEL,
+ PMIC_AUXADC_TRIM_CH9_SEL,
+ PMIC_AUXADC_TRIM_CH10_SEL,
+ PMIC_AUXADC_TRIM_CH11_SEL,
+ PMIC_AUXADC_TRIM_CH12_SEL,
+ PMIC_AUXADC_TRIM_CH13_SEL,
+ PMIC_AUXADC_ADC_2S_COMP_ENB,
+ PMIC_AUXADC_ADC_TRIM_COMP,
+ PMIC_AUXADC_RNG_EN,
+ PMIC_AUXADC_TEST_MODE,
+ PMIC_AUXADC_BIT_SEL,
+ PMIC_AUXADC_START_SW,
+ PMIC_AUXADC_START_SWCTRL,
+ PMIC_AUXADC_TS_VBE_SEL,
+ PMIC_AUXADC_TS_VBE_SEL_SWCTRL,
+ PMIC_AUXADC_VBUF_EN,
+ PMIC_AUXADC_VBUF_EN_SWCTRL,
+ PMIC_AUXADC_OUT_SEL,
+ PMIC_AUXADC_DA_DAC,
+ PMIC_AUXADC_DA_DAC_SWCTRL,
+ PMIC_AD_AUXADC_COMP,
+ PMIC_AUXADC_ADCIN_VSEN_EN,
+ PMIC_AUXADC_ADCIN_VBAT_EN,
+ PMIC_AUXADC_ADCIN_VSEN_MUX_EN,
+ PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN,
+ PMIC_AUXADC_ADCIN_CHR_EN,
+ PMIC_AUXADC_ADCIN_BATON_TDET_EN,
+ PMIC_AUXADC_ACCDET_ANASWCTRL_EN,
+ PMIC_AUXADC_XO_THADC_EN,
+ PMIC_AUXADC_ADCIN_BATID_SW_EN,
+ PMIC_AUXADC_VXO22_EN,
+ PMIC_AUXADC_DIG0_RSV0,
+ PMIC_AUXADC_CHSEL,
+ PMIC_AUXADC_SWCTRL_EN,
+ PMIC_AUXADC_SOURCE_LBAT_SEL,
+ PMIC_AUXADC_SOURCE_LBAT2_SEL,
+ PMIC_AUXADC_START_EXTD,
+ PMIC_AUXADC_DAC_EXTD,
+ PMIC_AUXADC_DAC_EXTD_EN,
+ PMIC_AUXADC_START_SHADE_NUM,
+ PMIC_AUXADC_START_SHADE_EN,
+ PMIC_AUXADC_START_SHADE_SEL,
+ PMIC_AUXADC_ADC_RDY_WAKEUP_CLR,
+ PMIC_AUXADC_ADC_RDY_FGADC_CLR,
+ PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR,
+ PMIC_AUXADC_ADC_RDY_PWRON_CLR,
+ PMIC_AUXADC_DIG0_RSV1,
+ PMIC_AUXADC_STATE_CS_S,
+ PMIC_AUXADC_DATA_REUSE_SEL,
+ PMIC_AUXADC_CH0_DATA_REUSE_SEL,
+ PMIC_AUXADC_CH1_DATA_REUSE_SEL,
+ PMIC_AUXADC_DCXO_DATA_REUSE_SEL,
+ PMIC_AUXADC_DATA_REUSE_EN,
+ PMIC_AUXADC_CH0_DATA_REUSE_EN,
+ PMIC_AUXADC_CH1_DATA_REUSE_EN,
+ PMIC_AUXADC_DCXO_DATA_REUSE_EN,
+ PMIC_AUXADC_AUTORPT_PRD,
+ PMIC_AUXADC_AUTORPT_EN,
+ PMIC_AUXADC_ACCDET_AUTO_SPL,
+ PMIC_AUXADC_ACCDET_AUTO_RQST_CLR,
+ PMIC_AUXADC_ACCDET_DIG1_RSV0,
+ PMIC_AUXADC_ACCDET_DIG0_RSV0,
+ PMIC_AUXADC_FGADC_START_SW,
+ PMIC_AUXADC_FGADC_START_SEL,
+ PMIC_AUXADC_IMP_FGADC_R_SW,
+ PMIC_AUXADC_IMP_FGADC_R_SEL,
+ PMIC_AUXADC_BAT_PLUGIN_START_SW,
+ PMIC_AUXADC_BAT_PLUGIN_START_SEL,
+ PMIC_AUXADC_DBG_DIG0_RSV2,
+ PMIC_AUXADC_DBG_DIG1_RSV2,
+ PMIC_AUXADC_DIG_3_ELR_LEN,
+ PMIC_EFUSE_GAIN_CH7_TRIM,
+ PMIC_EFUSE_OFFSET_CH7_TRIM,
+ PMIC_EFUSE_GAIN_CH4_TRIM,
+ PMIC_EFUSE_OFFSET_CH4_TRIM,
+ PMIC_EFUSE_GAIN_CH0_TRIM,
+ PMIC_EFUSE_OFFSET_CH0_TRIM,
+ PMIC_AUXADC_SW_GAIN_TRIM,
+ PMIC_AUXADC_SW_OFFSET_TRIM,
+ PMIC_AUXADC_EFUSE_ID,
+ PMIC_AUXADC_EFUSE_O_SLOPE,
+ PMIC_AUXADC_EFUSE_O_SLOPE_SIGN,
+ PMIC_AUXADC_EFUSE_DEGC_CALI,
+ PMIC_AUXADC_EFUSE_ADC_CALI_EN,
+ PMIC_AUXADC_EFUSE_RSV0,
+ PMIC_AUXADC_EFUSE_O_VTS,
+ PMIC_AUXADC_EFUSE_RSV1,
+ PMIC_AUXADC_EFUSE_O_VTS_2,
+ PMIC_AUXADC_EFUSE_RSV2,
+ PMIC_AUXADC_EFUSE_O_VTS_3,
+ PMIC_AUXADC_EFUSE_RSV3,
+ PMIC_AUXADC_EFUSE_O_VTS_4,
+ PMIC_AUXADC_EFUSE_RSV4,
+ PMIC_AUXADC_EFUSE_GAIN_AUX,
+ PMIC_AUXADC_EFUSE_RSV5,
+ PMIC_AUXADC_EFUSE_GAIN_BGRL,
+ PMIC_AUXADC_EFUSE_GAIN_BGRH,
+ PMIC_AUXADC_EFUSE_RSV6,
+ PMIC_AUXADC_EFUSE_CALI_FROM_EFUSE_EN,
+ PMIC_AUXADC_EFUSE_ADC_BGRCALI_EN,
+ PMIC_AUXADC_EFUSE_ADC_AUXCALI_EN,
+ PMIC_AUXADC_EFUSE_TRMPL_CALI,
+ PMIC_AUXADC_EFUSE_TRMPH_CALI,
+ PMIC_AUXADC_EFUSE_SIGN_BGRL,
+ PMIC_AUXADC_EFUSE_SIGN_BGRH,
+ PMIC_AUXADC_EFUSE_SIGN_AUX,
+ PMIC_AUXADC_EFUSE_RSV7,
+ PMIC_AUXADC_EFUSE_VBG12,
+ PMIC_AUXADC_EFUSE_VAUX18,
+ PMIC_EFUSE_GAIN_CH13_TRIM,
+ PMIC_EFUSE_OFFSET_CH13_TRIM,
+ PMIC_EFUSE_GAIN_CH12_TRIM,
+ PMIC_EFUSE_OFFSET_CH12_TRIM,
+ PMIC_EFUSE_GAIN_CH8_TRIM,
+ PMIC_EFUSE_OFFSET_CH8_TRIM,
+ PMIC_EFUSE_GAIN_CH6_TRIM,
+ PMIC_EFUSE_OFFSET_CH6_TRIM,
+ PMIC_EFUSE_GAIN_CH2_TRIM,
+ PMIC_EFUSE_OFFSET_CH2_TRIM,
+ PMIC_AUXADC_DIG_4_ANA_ID,
+ PMIC_AUXADC_DIG_4_DIG_ID,
+ PMIC_AUXADC_DIG_4_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_4_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_4_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_4_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_4_DSN_CBS,
+ PMIC_AUXADC_DIG_4_DSN_BIX,
+ PMIC_AUXADC_DIG_4_DSN_ESP,
+ PMIC_AUXADC_DIG_4_DSN_FPI,
+ PMIC_AUXADC_IMP_EN,
+ PMIC_AUXADC_IMP_PRD_SEL,
+ PMIC_AUXADC_IMP_CNT_SEL,
+ PMIC_AUXADC_IMPEDANCE_CHSEL,
+ PMIC_AUXADC_IMPEDANCE_IRQ_STATUS,
+ PMIC_AUXADC_IMP_START,
+ PMIC_AUXADC_IMP_STATE,
+ PMIC_AUXADC_IMP_COUNT,
+ PMIC_AUXADC_IMP_FGADC_R_S,
+ PMIC_FGADC_AUXADC_IMP_R_DONE_S,
+ PMIC_AUXADC_ADC_OUT_IMP,
+ PMIC_AUXADC_ADC_RDY_IMP,
+ PMIC_AUXADC_ADC_OUT_IMP_AVG,
+ PMIC_AUXADC_ADC_RDY_IMP_AVG,
+ PMIC_AUXADC_IMP_CK_SW_EN,
+ PMIC_AUXADC_IMP_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_IMP,
+ PMIC_AUXADC_LBAT_EN,
+ PMIC_AUXADC_LBAT_DET_PRD_SEL,
+ PMIC_AUXADC_LBAT_DEBT_MAX_SEL,
+ PMIC_AUXADC_LBAT_DEBT_MIN_SEL,
+ PMIC_AUXADC_LBAT_VOLT_MAX,
+ PMIC_AUXADC_LBAT_IRQ_EN_MAX,
+ PMIC_AUXADC_LBAT_DET_MAX,
+ PMIC_AUXADC_LBAT_MAX_IRQ_B,
+ PMIC_AUXADC_LBAT_VOLT_MIN,
+ PMIC_AUXADC_LBAT_IRQ_EN_MIN,
+ PMIC_AUXADC_LBAT_DET_MIN,
+ PMIC_AUXADC_LBAT_MIN_IRQ_B,
+ PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_LBAT_STATE,
+ PMIC_AUXADC_LBAT_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_LBAT,
+ PMIC_AUXADC_ADC_RDY_LBAT,
+ PMIC_AUXADC_LBAT_CK_SW_EN,
+ PMIC_AUXADC_LBAT_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_LBAT,
+ PMIC_AUXADC_BAT_TEMP_EN,
+ PMIC_AUXADC_BAT_TEMP_FROZE_EN,
+ PMIC_AUXADC_BAT_TEMP_DET_PRD_SEL,
+ PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SEL,
+ PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SEL,
+ PMIC_AUXADC_BAT_TEMP_VOLT_MAX,
+ PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX,
+ PMIC_AUXADC_BAT_TEMP_DET_MAX,
+ PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B,
+ PMIC_AUXADC_BAT_TEMP_VOLT_MIN,
+ PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN,
+ PMIC_AUXADC_BAT_TEMP_DET_MIN,
+ PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B,
+ PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_BAT_TEMP_STATE,
+ PMIC_AUXADC_BAT_TEMP_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_BAT_TEMP,
+ PMIC_AUXADC_ADC_RDY_BAT_TEMP,
+ PMIC_AUXADC_BAT_TEMP_CK_SW_EN,
+ PMIC_AUXADC_BAT_TEMP_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP,
+ PMIC_AUXADC_LBAT2_EN,
+ PMIC_AUXADC_LBAT2_DET_PRD_SEL,
+ PMIC_AUXADC_LBAT2_DEBT_MAX_SEL,
+ PMIC_AUXADC_LBAT2_DEBT_MIN_SEL,
+ PMIC_AUXADC_LBAT2_VOLT_MAX,
+ PMIC_AUXADC_LBAT2_IRQ_EN_MAX,
+ PMIC_AUXADC_LBAT2_DET_MAX,
+ PMIC_AUXADC_LBAT2_MAX_IRQ_B,
+ PMIC_AUXADC_LBAT2_VOLT_MIN,
+ PMIC_AUXADC_LBAT2_IRQ_EN_MIN,
+ PMIC_AUXADC_LBAT2_DET_MIN,
+ PMIC_AUXADC_LBAT2_MIN_IRQ_B,
+ PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_LBAT2_STATE,
+ PMIC_AUXADC_LBAT2_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_LBAT2,
+ PMIC_AUXADC_ADC_RDY_LBAT2,
+ PMIC_AUXADC_LBAT2_CK_SW_EN,
+ PMIC_AUXADC_LBAT2_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_LBAT2,
+ PMIC_AUXADC_THR_EN,
+ PMIC_AUXADC_THR_DET_PRD_SEL,
+ PMIC_AUXADC_THR_DEBT_MAX_SEL,
+ PMIC_AUXADC_THR_DEBT_MIN_SEL,
+ PMIC_AUXADC_THR_VOLT_MAX,
+ PMIC_AUXADC_THR_IRQ_EN_MAX,
+ PMIC_AUXADC_THR_DET_MAX,
+ PMIC_AUXADC_THR_MAX_IRQ_B,
+ PMIC_AUXADC_THR_VOLT_MIN,
+ PMIC_AUXADC_THR_IRQ_EN_MIN,
+ PMIC_AUXADC_THR_DET_MIN,
+ PMIC_AUXADC_THR_MIN_IRQ_B,
+ PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_THR_STATE,
+ PMIC_AUXADC_THR_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_THR_HW,
+ PMIC_AUXADC_ADC_RDY_THR_HW,
+ PMIC_AUXADC_THR_CK_SW_EN,
+ PMIC_AUXADC_THR_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_THR_HW,
+ PMIC_AUXADC_MDRT_DET_PRD_SEL,
+ PMIC_AUXADC_MDRT_DET_EN,
+ PMIC_AUXADC_MDRT_DET_WKUP_START_CNT,
+ PMIC_AUXADC_MDRT_DET_WKUP_START_CLR,
+ PMIC_AUXADC_MDRT_DET_WKUP_START,
+ PMIC_AUXADC_MDRT_DET_WKUP_START_SEL,
+ PMIC_AUXADC_MDRT_DET_WKUP_EN,
+ PMIC_AUXADC_MDRT_DET_SRCLKEN_IND,
+ PMIC_AUXADC_MDRT_STATE,
+ PMIC_AUXADC_MDRT_START,
+ PMIC_AUXADC_ADC_OUT_MDRT,
+ PMIC_AUXADC_ADC_RDY_MDRT,
+ PMIC_AUXADC_MDRT_CK_SW_EN,
+ PMIC_AUXADC_MDRT_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_MDRT,
+ PMIC_AUXADC_DCXO_MDRT_DET_PRD_SEL,
+ PMIC_AUXADC_DCXO_MDRT_DET_EN,
+ PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT,
+ PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR,
+ PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START,
+ PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL,
+ PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN,
+ PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND,
+ PMIC_AUXADC_DCXO_MDRT_STATE,
+ PMIC_AUXADC_DCXO_MDRT_START,
+ PMIC_AUXADC_ADC_OUT_DCXO_MDRT,
+ PMIC_AUXADC_ADC_RDY_DCXO_MDRT,
+ PMIC_AUXADC_DCXO_MDRT_CK_SW_EN,
+ PMIC_AUXADC_DCXO_MDRT_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT,
+ PMIC_AUXADC_RSV_1RSV0,
+ PMIC_AUXADC_NEW_PRIORITY_LIST_SEL,
+ PMIC_AUXADC_DIG_5_ANA_ID,
+ PMIC_AUXADC_DIG_5_DIG_ID,
+ PMIC_AUXADC_DIG_5_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_5_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_5_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_5_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_5_DSN_CBS,
+ PMIC_AUXADC_DIG_5_DSN_BIX,
+ PMIC_AUXADC_DIG_5_DSN_ESP,
+ PMIC_AUXADC_DIG_5_DSN_FPI,
+ PMIC_AUXADC_ADC_OUT_INTER1_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER1_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER2_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER2_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER3_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER3_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER4_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER4_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER5_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER5_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER6_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER6_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER7_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER7_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER8_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER8_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER9_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER9_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER10_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER10_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER11_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER11_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER12_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER12_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER13_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER13_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER14_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER14_DIV,
+ PMIC_AUXADC_ADC_OUT_INTER1,
+ PMIC_AUXADC_ADC_RDY_INTER1,
+ PMIC_AUXADC_ADC_OUT_INTER2,
+ PMIC_AUXADC_ADC_RDY_INTER2,
+ PMIC_AUXADC_ADC_OUT_INTER3,
+ PMIC_AUXADC_ADC_RDY_INTER3,
+ PMIC_AUXADC_ADC_OUT_INTER4,
+ PMIC_AUXADC_ADC_RDY_INTER4,
+ PMIC_AUXADC_ADC_OUT_INTER5,
+ PMIC_AUXADC_ADC_RDY_INTER5,
+ PMIC_AUXADC_ADC_OUT_INTER6,
+ PMIC_AUXADC_ADC_RDY_INTER6,
+ PMIC_AUXADC_ADC_OUT_INTER7,
+ PMIC_AUXADC_ADC_RDY_INTER7,
+ PMIC_AUXADC_ADC_OUT_INTER8,
+ PMIC_AUXADC_ADC_RDY_INTER8,
+ PMIC_AUXADC_ADC_OUT_INTER9,
+ PMIC_AUXADC_ADC_RDY_INTER9,
+ PMIC_AUXADC_ADC_OUT_TREF,
+ PMIC_AUXADC_ADC_RDY_TREF,
+ PMIC_AUXADC_ADC_OUT_EXT1,
+ PMIC_AUXADC_ADC_RDY_EXT1,
+ PMIC_AUXADC_ADC_OUT_EXT2,
+ PMIC_AUXADC_ADC_RDY_EXT2,
+ PMIC_AUXADC_ADC_OUT_EXT3,
+ PMIC_AUXADC_ADC_RDY_EXT3,
+ PMIC_AUXADC_ADC_OUT_EXT4,
+ PMIC_AUXADC_ADC_RDY_EXT4,
+ PMIC_AUXADC_ADC_OUT_EXT5,
+ PMIC_AUXADC_ADC_RDY_EXT5,
+ PMIC_AUXADC_ADC_OUT_EXT6,
+ PMIC_AUXADC_ADC_RDY_EXT6,
+ PMIC_AUXADC_ADC_OUT_EXT7,
+ PMIC_AUXADC_ADC_RDY_EXT7,
+ PMIC_AUXADC_ADC_OUT_EXT8,
+ PMIC_AUXADC_ADC_RDY_EXT8,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER1_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER2_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER3_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER4_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER5_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER6_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER7_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER8_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER9_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER10_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER11_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER12_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER13_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER14_DIV,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER1,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER2,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER3,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER4,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER5,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER6,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER7,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER8,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER9,
+ PMIC_AUXADC_ADC_BUSY_IN_TREF,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT1,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT2,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT3,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT4,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT5,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT6,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT7,
+ PMIC_AUXADC_ADC_BUSY_IN_EXT8,
+ PMIC_AUXADC_INTER1_DIV_EN,
+ PMIC_AUXADC_INTER2_DIV_EN,
+ PMIC_AUXADC_INTER3_DIV_EN,
+ PMIC_AUXADC_INTER4_DIV_EN,
+ PMIC_AUXADC_INTER5_DIV_EN,
+ PMIC_AUXADC_INTER6_DIV_EN,
+ PMIC_AUXADC_INTER7_DIV_EN,
+ PMIC_AUXADC_INTER8_DIV_EN,
+ PMIC_AUXADC_INTER9_DIV_EN,
+ PMIC_AUXADC_INTER10_DIV_EN,
+ PMIC_AUXADC_INTER11_DIV_EN,
+ PMIC_AUXADC_INTER12_DIV_EN,
+ PMIC_AUXADC_INTER13_DIV_EN,
+ PMIC_AUXADC_INTER14_DIV_EN,
+ PMIC_AUXADC_INTER1_EN,
+ PMIC_AUXADC_INTER2_EN,
+ PMIC_AUXADC_INTER3_EN,
+ PMIC_AUXADC_INTER4_EN,
+ PMIC_AUXADC_INTER5_EN,
+ PMIC_AUXADC_INTER6_EN,
+ PMIC_AUXADC_INTER7_EN,
+ PMIC_AUXADC_INTER8_EN,
+ PMIC_AUXADC_INTER9_EN,
+ PMIC_AUXADC_EXT1_EN,
+ PMIC_AUXADC_EXT2_EN,
+ PMIC_AUXADC_EXT3_EN,
+ PMIC_AUXADC_EXT4_EN,
+ PMIC_AUXADC_EXT5_EN,
+ PMIC_AUXADC_EXT6_EN,
+ PMIC_AUXADC_EXT7_EN,
+ PMIC_AUXADC_EXT8_EN,
+ PMIC_RG_AUXADC_TREF_SW_MODE,
+ PMIC_AUXADC_TREF_SW_EN,
+ PMIC_AUXADC_TREF_EN,
+ PMIC_AUXADC_DIG_6_ANA_ID,
+ PMIC_AUXADC_DIG_6_DIG_ID,
+ PMIC_AUXADC_DIG_6_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_6_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_6_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_6_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_6_DSN_CBS,
+ PMIC_AUXADC_DIG_6_DSN_BIX,
+ PMIC_AUXADC_DIG_6_DSN_ESP,
+ PMIC_AUXADC_DIG_6_DSN_FPI,
+ PMIC_AUXADC_NAG_EN,
+ PMIC_AUXADC_NAG_CLR,
+ PMIC_AUXADC_NAG_VBAT1_SEL,
+ PMIC_AUXADC_NAG_PRD_SEL,
+ PMIC_AUXADC_NAG_IRQ_EN,
+ PMIC_AUXADC_NAG_C_DLTV_IRQ,
+ PMIC_AUXADC_NAG_ZCV,
+ PMIC_AUXADC_NAG_C_DLTV_TH_15_0,
+ PMIC_AUXADC_NAG_C_DLTV_TH_26_16,
+ PMIC_AUXADC_NAG_CNT_15_0,
+ PMIC_AUXADC_NAG_CNT_25_16,
+ PMIC_AUXADC_NAG_DLTV,
+ PMIC_AUXADC_NAG_C_DLTV_15_0,
+ PMIC_AUXADC_NAG_C_DLTV_26_16,
+ PMIC_AUXADC_NAG_AUXADC_START,
+ PMIC_AUXADC_NAG_STATE,
+ PMIC_AUXADC_ADC_OUT_NAG,
+ PMIC_AUXADC_ADC_RDY_NAG,
+ PMIC_AUXADC_NAG_CK_SW_EN,
+ PMIC_AUXADC_NAG_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_NAG,
+ PMIC_AUXADC_INTER1_DET_DIV_EN,
+ PMIC_AUXADC_INTER1_DET_DIV_DET_PRD_SEL,
+ PMIC_AUXADC_INTER1_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER1_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER1_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER1_DET_DIV_DET_MAX,
+ PMIC_AUXADC_INTER1_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER1_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER1_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER1_DET_DIV_DET_MIN,
+ PMIC_AUXADC_INTER1_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER1_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER1_DET_DIV_STATE,
+ PMIC_AUXADC_INTER1_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER1_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER1_DET_DIV,
+ PMIC_AUXADC_INTER1_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER1_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET_DIV,
+ PMIC_AUXADC_INTER2_DET_DIV_EN,
+ PMIC_AUXADC_INTER2_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER2_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER2_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER2_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER2_DET_DIV_MAX,
+ PMIC_AUXADC_INTER2_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER2_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER2_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER2_DET_DIV_MIN,
+ PMIC_AUXADC_INTER2_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER2_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER2_DET_DIV_STATE,
+ PMIC_AUXADC_INTER2_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER2_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER2_DET_DIV,
+ PMIC_AUXADC_INTER2_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER2_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET_DIV,
+ PMIC_AUXADC_INTER3_DET_DIV_EN,
+ PMIC_AUXADC_INTER3_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER3_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER3_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER3_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER3_DET_DIV_MAX,
+ PMIC_AUXADC_INTER3_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER3_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER3_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER3_DET_DIV_MIN,
+ PMIC_AUXADC_INTER3_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER3_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER3_DET_DIV_STATE,
+ PMIC_AUXADC_INTER3_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER3_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER3_DET_DIV,
+ PMIC_AUXADC_INTER3_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER3_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET_DIV,
+ PMIC_AUXADC_INTER4_DET_DIV_EN,
+ PMIC_AUXADC_INTER4_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER4_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER4_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER4_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER4_DET_DIV_MAX,
+ PMIC_AUXADC_INTER4_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER4_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER4_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER4_DET_DIV_MIN,
+ PMIC_AUXADC_INTER4_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER4_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER4_DET_DIV_STATE,
+ PMIC_AUXADC_INTER4_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER4_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER4_DET_DIV,
+ PMIC_AUXADC_INTER4_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER4_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET_DIV,
+ PMIC_AUXADC_INTER5_DET_DIV_EN,
+ PMIC_AUXADC_INTER5_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER5_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER5_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER5_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER5_DET_DIV_MAX,
+ PMIC_AUXADC_INTER5_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER5_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER5_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER5_DET_DIV_MIN,
+ PMIC_AUXADC_INTER5_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER5_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER5_DET_DIV_STATE,
+ PMIC_AUXADC_INTER5_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER5_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER5_DET_DIV,
+ PMIC_AUXADC_INTER5_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER5_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET_DIV,
+ PMIC_AUXADC_DIG_7_ANA_ID,
+ PMIC_AUXADC_DIG_7_DIG_ID,
+ PMIC_AUXADC_DIG_7_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_7_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_7_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_7_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_7_DSN_CBS,
+ PMIC_AUXADC_DIG_7_DSN_BIX,
+ PMIC_AUXADC_DIG_7_DSN_ESP,
+ PMIC_AUXADC_DIG_7_DSN_FPI,
+ PMIC_AUXADC_INTER6_DET_DIV_EN,
+ PMIC_AUXADC_INTER6_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER6_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER6_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER6_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER6_DET_DIV_MAX,
+ PMIC_AUXADC_INTER6_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER6_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER6_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER6_DET_DIV_MIN,
+ PMIC_AUXADC_INTER6_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER6_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER6_DET_DIV_STATE,
+ PMIC_AUXADC_INTER6_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER6_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER6_DET_DIV,
+ PMIC_AUXADC_INTER6_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER6_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET_DIV,
+ PMIC_AUXADC_INTER7_DET_DIV_EN,
+ PMIC_AUXADC_INTER7_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER7_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER7_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER7_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER7_DET_DIV_MAX,
+ PMIC_AUXADC_INTER7_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER7_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER7_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER7_DET_DIV_MIN,
+ PMIC_AUXADC_INTER7_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER7_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER7_DET_DIV_STATE,
+ PMIC_AUXADC_INTER7_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER7_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER7_DET_DIV,
+ PMIC_AUXADC_INTER7_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER7_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET_DIV,
+ PMIC_AUXADC_INTER8_DET_DIV_EN,
+ PMIC_AUXADC_INTER8_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER8_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER8_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER8_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER8_DET_DIV_MAX,
+ PMIC_AUXADC_INTER8_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER8_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER8_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER8_DET_DIV_MIN,
+ PMIC_AUXADC_INTER8_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER8_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER8_DET_DIV_STATE,
+ PMIC_AUXADC_INTER8_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER8_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER8_DET_DIV,
+ PMIC_AUXADC_INTER8_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER8_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET_DIV,
+ PMIC_AUXADC_INTER9_DET_DIV_EN,
+ PMIC_AUXADC_INTER9_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER9_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER9_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER9_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER9_DET_DIV_MAX,
+ PMIC_AUXADC_INTER9_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER9_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER9_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER9_DET_DIV_MIN,
+ PMIC_AUXADC_INTER9_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER9_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER9_DET_DIV_STATE,
+ PMIC_AUXADC_INTER9_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER9_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER9_DET_DIV,
+ PMIC_AUXADC_INTER9_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER9_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET_DIV,
+ PMIC_AUXADC_INTER10_DET_DIV_EN,
+ PMIC_AUXADC_INTER10_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER10_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER10_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER10_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER10_DET_DIV_MAX,
+ PMIC_AUXADC_INTER10_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER10_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER10_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER10_DET_DIV_MIN,
+ PMIC_AUXADC_INTER10_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER10_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER10_DET_DIV_STATE,
+ PMIC_AUXADC_INTER10_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER10_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER10_DET_DIV,
+ PMIC_AUXADC_INTER10_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER10_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER10_DET_DIV,
+ PMIC_AUXADC_INTER11_DET_DIV_EN,
+ PMIC_AUXADC_INTER11_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER11_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER11_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER11_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER11_DET_DIV_MAX,
+ PMIC_AUXADC_INTER11_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER11_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER11_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER11_DET_DIV_MIN,
+ PMIC_AUXADC_INTER11_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER11_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER11_DET_DIV_STATE,
+ PMIC_AUXADC_INTER11_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER11_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER11_DET_DIV,
+ PMIC_AUXADC_INTER11_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER11_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER11_DET_DIV,
+ PMIC_AUXADC_DIG_8_ANA_ID,
+ PMIC_AUXADC_DIG_8_DIG_ID,
+ PMIC_AUXADC_DIG_8_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_8_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_8_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_8_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_8_DSN_CBS,
+ PMIC_AUXADC_DIG_8_DSN_BIX,
+ PMIC_AUXADC_DIG_8_DSN_ESP,
+ PMIC_AUXADC_DIG_8_DSN_FPI,
+ PMIC_AUXADC_INTER12_DET_DIV_EN,
+ PMIC_AUXADC_INTER12_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER12_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER12_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER12_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER12_DET_DIV_MAX,
+ PMIC_AUXADC_INTER12_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER12_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER12_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER12_DET_DIV_MIN,
+ PMIC_AUXADC_INTER12_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER12_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER12_DET_DIV_STATE,
+ PMIC_AUXADC_INTER12_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER12_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER12_DET_DIV,
+ PMIC_AUXADC_INTER12_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER12_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER12_DET_DIV,
+ PMIC_AUXADC_INTER13_DET_DIV_EN,
+ PMIC_AUXADC_INTER13_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER13_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER13_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER13_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER13_DET_DIV_MAX,
+ PMIC_AUXADC_INTER13_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER13_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER13_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER13_DET_DIV_MIN,
+ PMIC_AUXADC_INTER13_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER13_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER13_DET_DIV_STATE,
+ PMIC_AUXADC_INTER13_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER13_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER13_DET_DIV,
+ PMIC_AUXADC_INTER13_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER13_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER13_DET_DIV,
+ PMIC_AUXADC_INTER14_DET_DIV_EN,
+ PMIC_AUXADC_INTER14_DET_DIV_PRD_SEL,
+ PMIC_AUXADC_INTER14_DET_DIV_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER14_DET_DIV_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER14_DET_DIV_VOLT_MAX,
+ PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER14_DET_DIV_MAX,
+ PMIC_AUXADC_INTER14_DET_DIV_MAX_IRQ_B,
+ PMIC_AUXADC_INTER14_DET_DIV_VOLT_MIN,
+ PMIC_AUXADC_INTER14_DET_DIV_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER14_DET_DIV_MIN,
+ PMIC_AUXADC_INTER14_DET_DIV_MIN_IRQ_B,
+ PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER14_DET_DIV_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER14_DET_DIV_STATE,
+ PMIC_AUXADC_INTER14_DET_DIV_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER14_DET_DIV,
+ PMIC_AUXADC_ADC_RDY_INTER14_DET_DIV,
+ PMIC_AUXADC_INTER14_DET_DIV_CK_SW_EN,
+ PMIC_AUXADC_INTER14_DET_DIV_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER14_DET_DIV,
+ PMIC_AUXADC_INTER1_DET_EN,
+ PMIC_AUXADC_INTER1_DET_PRD_SEL,
+ PMIC_AUXADC_INTER1_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER1_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER1_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER1_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER1_DET_MAX,
+ PMIC_AUXADC_INTER1_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER1_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER1_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER1_DET_MIN,
+ PMIC_AUXADC_INTER1_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER1_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER1_DET_STATE,
+ PMIC_AUXADC_INTER1_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER1_DET,
+ PMIC_AUXADC_ADC_RDY_INTER1_DET,
+ PMIC_AUXADC_INTER1_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER1_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER1_DET,
+ PMIC_AUXADC_INTER2_DET_EN,
+ PMIC_AUXADC_INTER2_DET_PRD_SEL,
+ PMIC_AUXADC_INTER2_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER2_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER2_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER2_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER2_DET_MAX,
+ PMIC_AUXADC_INTER2_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER2_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER2_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER2_DET_MIN,
+ PMIC_AUXADC_INTER2_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER2_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER2_DET_STATE,
+ PMIC_AUXADC_INTER2_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER2_DET,
+ PMIC_AUXADC_ADC_RDY_INTER2_DET,
+ PMIC_AUXADC_INTER2_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER2_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER2_DET,
+ PMIC_AUXADC_INTER3_DET_EN,
+ PMIC_AUXADC_INTER3_DET_PRD_SEL,
+ PMIC_AUXADC_INTER3_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER3_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER3_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER3_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER3_DET_MAX,
+ PMIC_AUXADC_INTER3_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER3_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER3_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER3_DET_MIN,
+ PMIC_AUXADC_INTER3_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER3_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER3_DET_STATE,
+ PMIC_AUXADC_INTER3_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER3_DET,
+ PMIC_AUXADC_ADC_RDY_INTER3_DET,
+ PMIC_AUXADC_INTER3_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER3_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER3_DET,
+ PMIC_AUXADC_DIG_9_ANA_ID,
+ PMIC_AUXADC_DIG_9_DIG_ID,
+ PMIC_AUXADC_DIG_9_ANA_MINOR_REV,
+ PMIC_AUXADC_DIG_9_ANA_MAJOR_REV,
+ PMIC_AUXADC_DIG_9_DIG_MINOR_REV,
+ PMIC_AUXADC_DIG_9_DIG_MAJOR_REV,
+ PMIC_AUXADC_DIG_9_DSN_CBS,
+ PMIC_AUXADC_DIG_9_DSN_BIX,
+ PMIC_AUXADC_DIG_9_DSN_ESP,
+ PMIC_AUXADC_DIG_9_DSN_FPI,
+ PMIC_AUXADC_INTER4_DET_EN,
+ PMIC_AUXADC_INTER4_DET_PRD_SEL,
+ PMIC_AUXADC_INTER4_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER4_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER4_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER4_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER4_DET_MAX,
+ PMIC_AUXADC_INTER4_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER4_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER4_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER4_DET_MIN,
+ PMIC_AUXADC_INTER4_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER4_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER4_DET_STATE,
+ PMIC_AUXADC_INTER4_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER4_DET,
+ PMIC_AUXADC_ADC_RDY_INTER4_DET,
+ PMIC_AUXADC_INTER4_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER4_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER4_DET,
+ PMIC_AUXADC_INTER5_DET_EN,
+ PMIC_AUXADC_INTER5_DET_PRD_SEL,
+ PMIC_AUXADC_INTER5_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER5_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER5_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER5_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER5_DET_MAX,
+ PMIC_AUXADC_INTER5_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER5_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER5_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER5_DET_MIN,
+ PMIC_AUXADC_INTER5_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER5_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER5_DET_STATE,
+ PMIC_AUXADC_INTER5_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER5_DET,
+ PMIC_AUXADC_ADC_RDY_INTER5_DET,
+ PMIC_AUXADC_INTER5_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER5_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER5_DET,
+ PMIC_AUXADC_INTER6_DET_EN,
+ PMIC_AUXADC_INTER6_DET_PRD_SEL,
+ PMIC_AUXADC_INTER6_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER6_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER6_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER6_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER6_DET_MAX,
+ PMIC_AUXADC_INTER6_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER6_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER6_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER6_DET_MIN,
+ PMIC_AUXADC_INTER6_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER6_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER6_DET_STATE,
+ PMIC_AUXADC_INTER6_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER6_DET,
+ PMIC_AUXADC_ADC_RDY_INTER6_DET,
+ PMIC_AUXADC_INTER6_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER6_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER6_DET,
+ PMIC_AUXADC_INTER7_DET_EN,
+ PMIC_AUXADC_INTER7_DET_PRD_SEL,
+ PMIC_AUXADC_INTER7_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER7_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER7_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER7_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER7_DET_MAX,
+ PMIC_AUXADC_INTER7_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER7_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER7_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER7_DET_MIN,
+ PMIC_AUXADC_INTER7_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER7_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER7_DET_STATE,
+ PMIC_AUXADC_INTER7_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER7_DET,
+ PMIC_AUXADC_ADC_RDY_INTER7_DET,
+ PMIC_AUXADC_INTER7_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER7_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER7_DET,
+ PMIC_AUXADC_INTER8_DET_EN,
+ PMIC_AUXADC_INTER8_DET_PRD_SEL,
+ PMIC_AUXADC_INTER8_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER8_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER8_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER8_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER8_DET_MAX,
+ PMIC_AUXADC_INTER8_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER8_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER8_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER8_DET_MIN,
+ PMIC_AUXADC_INTER8_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER8_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER8_DET_STATE,
+ PMIC_AUXADC_INTER8_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER8_DET,
+ PMIC_AUXADC_ADC_RDY_INTER8_DET,
+ PMIC_AUXADC_INTER8_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER8_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER8_DET,
+ PMIC_AUXADC_INTER9_DET_EN,
+ PMIC_AUXADC_INTER9_DET_PRD_SEL,
+ PMIC_AUXADC_INTER9_DET_DEBT_MAX_SEL,
+ PMIC_AUXADC_INTER9_DET_DEBT_MIN_SEL,
+ PMIC_AUXADC_INTER9_DET_VOLT_MAX,
+ PMIC_AUXADC_INTER9_DET_IRQ_EN_MAX,
+ PMIC_AUXADC_INTER9_DET_MAX,
+ PMIC_AUXADC_INTER9_DET_MAX_IRQ_B,
+ PMIC_AUXADC_INTER9_DET_VOLT_MIN,
+ PMIC_AUXADC_INTER9_DET_IRQ_EN_MIN,
+ PMIC_AUXADC_INTER9_DET_MIN,
+ PMIC_AUXADC_INTER9_DET_MIN_IRQ_B,
+ PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MAX,
+ PMIC_AUXADC_INTER9_DET_DEBOUNCE_COUNT_MIN,
+ PMIC_AUXADC_INTER9_DET_STATE,
+ PMIC_AUXADC_INTER9_DET_AUXADC_START,
+ PMIC_AUXADC_ADC_OUT_INTER9_DET,
+ PMIC_AUXADC_ADC_RDY_INTER9_DET,
+ PMIC_AUXADC_INTER9_DET_CK_SW_EN,
+ PMIC_AUXADC_INTER9_DET_CK_SW_MODE,
+ PMIC_AUXADC_ADC_BUSY_IN_INTER9_DET,
+ PMIC_BUCK_TOP_ANA_ID,
+ PMIC_BUCK_TOP_DIG_ID,
+ PMIC_BUCK_TOP_ANA_MINOR_REV,
+ PMIC_BUCK_TOP_ANA_MAJOR_REV,
+ PMIC_BUCK_TOP_DIG_MINOR_REV,
+ PMIC_BUCK_TOP_DIG_MAJOR_REV,
+ PMIC_BUCK_TOP_CBS,
+ PMIC_BUCK_TOP_BIX,
+ PMIC_BUCK_TOP_ESP,
+ PMIC_BUCK_TOP_FPI,
+ PMIC_BUCK_TOP_CLK_OFFSET,
+ PMIC_BUCK_TOP_RST_OFFSET,
+ PMIC_BUCK_TOP_INT_OFFSET,
+ PMIC_BUCK_TOP_INT_LEN,
+ PMIC_RG_BUCK32K_CK_PDN,
+ PMIC_RG_BUCK1M_CK_PDN,
+ PMIC_RG_BUCK26M_CK_PDN,
+ PMIC_RG_BUCK_ANA_CK_PDN,
+ PMIC_RG_BUCK_ANA_AUTO_OFF_DIS,
+ PMIC_RG_SMPS_26M_CK_TST_DIS,
+ PMIC_RG_SMPS_26M_CK_TSTSEL,
+ PMIC_RG_BUCK_TOP_CLK_CON0_SET,
+ PMIC_RG_BUCK_TOP_CLK_CON0_CLR,
+ PMIC_RG_BUCK32K_CK_PDN_HWEN,
+ PMIC_RG_BUCK1M_CK_PDN_HWEN,
+ PMIC_RG_BUCK26M_CK_PDN_HWEN,
+ PMIC_RG_BUCK_SLEEP_CTRL_MODE,
+ PMIC_RG_BUCK_OSC_EN_MODE,
+ PMIC_RG_BUCK_OSC_EN_SW,
+ PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET,
+ PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR,
+ PMIC_RG_INT_EN_VPROC_OC,
+ PMIC_RG_INT_EN_VCORE_OC,
+ PMIC_RG_INT_EN_VSRAM_OTHERS_OC,
+ PMIC_RG_INT_EN_VMODEM_OC,
+ PMIC_RG_INT_EN_VDRAM1_OC,
+ PMIC_RG_INT_EN_VS1_OC,
+ PMIC_RG_INT_EN_VS2_OC,
+ PMIC_RG_INT_EN_VPA_OC,
+ PMIC_RG_BUCK_TOP_INT_EN_CON0_SET,
+ PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR,
+ PMIC_RG_INT_MASK_VPROC_OC,
+ PMIC_RG_INT_MASK_VCORE_OC,
+ PMIC_RG_INT_MASK_VSRAM_OTHERS_OC,
+ PMIC_RG_INT_MASK_VMODEM_OC,
+ PMIC_RG_INT_MASK_VDRAM1_OC,
+ PMIC_RG_INT_MASK_VS1_OC,
+ PMIC_RG_INT_MASK_VS2_OC,
+ PMIC_RG_INT_MASK_VPA_OC,
+ PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET,
+ PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_VPROC_OC,
+ PMIC_RG_INT_STATUS_VCORE_OC,
+ PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC,
+ PMIC_RG_INT_STATUS_VMODEM_OC,
+ PMIC_RG_INT_STATUS_VDRAM1_OC,
+ PMIC_RG_INT_STATUS_VS1_OC,
+ PMIC_RG_INT_STATUS_VS2_OC,
+ PMIC_RG_INT_STATUS_VPA_OC,
+ PMIC_RG_INT_RAW_STATUS_VPROC_OC,
+ PMIC_RG_INT_RAW_STATUS_VCORE_OC,
+ PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC,
+ PMIC_RG_INT_RAW_STATUS_VMODEM_OC,
+ PMIC_RG_INT_RAW_STATUS_VDRAM1_OC,
+ PMIC_RG_INT_RAW_STATUS_VS1_OC,
+ PMIC_RG_INT_RAW_STATUS_VS2_OC,
+ PMIC_RG_INT_RAW_STATUS_VPA_OC,
+ PMIC_RG_VOW_BUCK_VCORE_DVS_DONE,
+ PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE,
+ PMIC_RG_BUCK_STB_MAX,
+ PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX,
+ PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX,
+ PMIC_RG_BUCK_VPA_MINFREQ_LATENCY_MAX,
+ PMIC_RG_BUCK_VPA_MINFREQ_DURATION_MAX,
+ PMIC_RG_BUCK_VPROC_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VCORE_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VS1_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VS2_OC_SDN_STATUS,
+ PMIC_RG_BUCK_VPA_OC_SDN_STATUS,
+ PMIC_BUCK_TOP_WRITE_KEY,
+ PMIC_DA_BUCK_SSC_FREQ,
+ PMIC_RG_BUCK_K_RST_DONE,
+ PMIC_RG_BUCK_K_MAP_SEL,
+ PMIC_RG_BUCK_K_ONCE_EN,
+ PMIC_RG_BUCK_K_ONCE,
+ PMIC_RG_BUCK_K_START_MANUAL,
+ PMIC_RG_BUCK_K_SRC_SEL,
+ PMIC_RG_BUCK_K_AUTO_EN,
+ PMIC_RG_BUCK_K_INV,
+ PMIC_RG_BUCK_K_CK_EN,
+ PMIC_BUCK_K_RESULT,
+ PMIC_BUCK_K_DONE,
+ PMIC_BUCK_K_CONTROL,
+ PMIC_DA_SMPS_OSC_CAL,
+ PMIC_RG_BUCK_K_BUCK_CK_CNT,
+ PMIC_BUCK_VPROC_WDTDBG_VOSEL,
+ PMIC_BUCK_VCORE_WDTDBG_VOSEL,
+ PMIC_BUCK_VSRAM_OTHERS_WDTDBG_VOSEL,
+ PMIC_BUCK_VMODEM_WDTDBG_VOSEL,
+ PMIC_BUCK_VDRAM1_WDTDBG_VOSEL,
+ PMIC_BUCK_VS1_WDTDBG_VOSEL,
+ PMIC_BUCK_VS2_WDTDBG_VOSEL,
+ PMIC_BUCK_VPA_WDTDBG_VOSEL,
+ PMIC_BUCK_TOP_ELR_LEN,
+ PMIC_RG_BUCK_VPROC_OC_SDN_EN,
+ PMIC_RG_BUCK_VCORE_OC_SDN_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OC_SDN_EN,
+ PMIC_RG_BUCK_VMODEM_OC_SDN_EN,
+ PMIC_RG_BUCK_VDRAM1_OC_SDN_EN,
+ PMIC_RG_BUCK_VS1_OC_SDN_EN,
+ PMIC_RG_BUCK_VS2_OC_SDN_EN,
+ PMIC_RG_BUCK_VPA_OC_SDN_EN,
+ PMIC_RG_BUCK_DCM_MODE,
+ PMIC_RG_BUCK_K_CONTROL_SMPS,
+ PMIC_RG_BUCK_VPROC_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL,
+ PMIC_RG_BUCK_VDRAM1_VOSEL_LP2,
+ PMIC_BUCK_VPROC_ANA_ID,
+ PMIC_BUCK_VPROC_DIG_ID,
+ PMIC_BUCK_VPROC_ANA_MINOR_REV,
+ PMIC_BUCK_VPROC_ANA_MAJOR_REV,
+ PMIC_BUCK_VPROC_DIG_MINOR_REV,
+ PMIC_BUCK_VPROC_DIG_MAJOR_REV,
+ PMIC_BUCK_VPROC_DSN_CBS,
+ PMIC_BUCK_VPROC_DSN_BIX,
+ PMIC_BUCK_VPROC_DSN_ESP,
+ PMIC_BUCK_VPROC_DSN_FPI_SSHUB,
+ PMIC_BUCK_VPROC_DSN_FPI_TRACKING,
+ PMIC_BUCK_VPROC_DSN_FPI_PREOC,
+ PMIC_BUCK_VPROC_DSN_FPI_VOTER,
+ PMIC_BUCK_VPROC_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VPROC_DSN_FPI_DLC,
+ PMIC_BUCK_VPROC_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VPROC_EN,
+ PMIC_RG_BUCK_VPROC_LP,
+ PMIC_RG_BUCK_VPROC_CON0_SET,
+ PMIC_RG_BUCK_VPROC_CON0_CLR,
+ PMIC_RG_BUCK_VPROC_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VPROC_SELR2R_CTRL,
+ PMIC_RG_BUCK_VPROC_SFCHG_FRATE,
+ PMIC_RG_BUCK_VPROC_SFCHG_FEN,
+ PMIC_RG_BUCK_VPROC_SFCHG_RRATE,
+ PMIC_RG_BUCK_VPROC_SFCHG_REN,
+ PMIC_RG_BUCK_VPROC_HW0_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW1_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW2_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW3_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW4_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW5_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW6_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW7_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW8_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW9_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW10_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW11_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW12_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW13_OP_EN,
+ PMIC_RG_BUCK_VPROC_HW14_OP_EN,
+ PMIC_RG_BUCK_VPROC_SW_OP_EN,
+ PMIC_RG_BUCK_VPROC_OP_EN_SET,
+ PMIC_RG_BUCK_VPROC_OP_EN_CLR,
+ PMIC_RG_BUCK_VPROC_HW0_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW1_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW2_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW3_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW4_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW5_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW6_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW7_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW8_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW9_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW10_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW11_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW12_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW13_OP_CFG,
+ PMIC_RG_BUCK_VPROC_HW14_OP_CFG,
+ PMIC_RG_BUCK_VPROC_OP_CFG_SET,
+ PMIC_RG_BUCK_VPROC_OP_CFG_CLR,
+ PMIC_RG_BUCK_VPROC_HW0_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW1_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW2_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW3_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW4_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW5_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW6_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW7_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW8_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW9_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW10_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW11_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW12_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW13_OP_MODE,
+ PMIC_RG_BUCK_VPROC_HW14_OP_MODE,
+ PMIC_RG_BUCK_VPROC_OP_MODE_SET,
+ PMIC_RG_BUCK_VPROC_OP_MODE_CLR,
+ PMIC_DA_VPROC_VOSEL,
+ PMIC_DA_VPROC_VOSEL_GRAY,
+ PMIC_DA_VPROC_EN,
+ PMIC_DA_VPROC_STB,
+ PMIC_DA_VPROC_LOOP_SEL,
+ PMIC_DA_VPROC_R2R_PDN,
+ PMIC_DA_VPROC_DVS_EN,
+ PMIC_DA_VPROC_DVS_DOWN,
+ PMIC_DA_VPROC_SSH,
+ PMIC_DA_VPROC_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VPROC_CK_SW_MODE,
+ PMIC_RG_BUCK_VPROC_CK_SW_EN,
+ PMIC_RG_BUCK_VPROC_TRACK_STALL_BYPASS,
+ PMIC_BUCK_VPROC_ELR_LEN,
+ PMIC_RG_BUCK_VPROC_VOSEL,
+ PMIC_BUCK_VCORE_ANA_ID,
+ PMIC_BUCK_VCORE_DIG_ID,
+ PMIC_BUCK_VCORE_ANA_MINOR_REV,
+ PMIC_BUCK_VCORE_ANA_MAJOR_REV,
+ PMIC_BUCK_VCORE_DIG_MINOR_REV,
+ PMIC_BUCK_VCORE_DIG_MAJOR_REV,
+ PMIC_BUCK_VCORE_DSN_CBS,
+ PMIC_BUCK_VCORE_DSN_BIX,
+ PMIC_BUCK_VCORE_DSN_ESP,
+ PMIC_BUCK_VCORE_DSN_FPI_SSHUB,
+ PMIC_BUCK_VCORE_DSN_FPI_TRACKING,
+ PMIC_BUCK_VCORE_DSN_FPI_PREOC,
+ PMIC_BUCK_VCORE_DSN_FPI_VOTER,
+ PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VCORE_DSN_FPI_DLC,
+ PMIC_BUCK_VCORE_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VCORE_EN,
+ PMIC_RG_BUCK_VCORE_LP,
+ PMIC_RG_BUCK_VCORE_CON0_SET,
+ PMIC_RG_BUCK_VCORE_CON0_CLR,
+ PMIC_RG_BUCK_VCORE_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VCORE_SELR2R_CTRL,
+ PMIC_RG_BUCK_VCORE_SFCHG_FRATE,
+ PMIC_RG_BUCK_VCORE_SFCHG_FEN,
+ PMIC_RG_BUCK_VCORE_SFCHG_RRATE,
+ PMIC_RG_BUCK_VCORE_SFCHG_REN,
+ PMIC_RG_BUCK_VCORE_HW0_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW1_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW2_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW3_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW4_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW5_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW6_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW7_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW8_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW9_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW10_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW11_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW12_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW13_OP_EN,
+ PMIC_RG_BUCK_VCORE_HW14_OP_EN,
+ PMIC_RG_BUCK_VCORE_SW_OP_EN,
+ PMIC_RG_BUCK_VCORE_OP_EN_SET,
+ PMIC_RG_BUCK_VCORE_OP_EN_CLR,
+ PMIC_RG_BUCK_VCORE_HW0_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW1_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW2_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW3_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW4_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW5_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW6_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW7_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW8_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW9_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW10_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW11_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW12_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW13_OP_CFG,
+ PMIC_RG_BUCK_VCORE_HW14_OP_CFG,
+ PMIC_RG_BUCK_VCORE_OP_CFG_SET,
+ PMIC_RG_BUCK_VCORE_OP_CFG_CLR,
+ PMIC_RG_BUCK_VCORE_HW0_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW1_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW2_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW3_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW4_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW5_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW6_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW7_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW8_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW9_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW10_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW11_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW12_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW13_OP_MODE,
+ PMIC_RG_BUCK_VCORE_HW14_OP_MODE,
+ PMIC_RG_BUCK_VCORE_OP_MODE_SET,
+ PMIC_RG_BUCK_VCORE_OP_MODE_CLR,
+ PMIC_DA_VCORE_VOSEL,
+ PMIC_DA_VCORE_VOSEL_GRAY,
+ PMIC_DA_VCORE_EN,
+ PMIC_DA_VCORE_STB,
+ PMIC_DA_VCORE_LOOP_SEL,
+ PMIC_DA_VCORE_R2R_PDN,
+ PMIC_DA_VCORE_DVS_EN,
+ PMIC_DA_VCORE_DVS_DOWN,
+ PMIC_DA_VCORE_SSH,
+ PMIC_DA_VCORE_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VCORE_CK_SW_MODE,
+ PMIC_RG_BUCK_VCORE_CK_SW_EN,
+ PMIC_BUCK_VCORE_ELR_LEN,
+ PMIC_RG_BUCK_VCORE_VOSEL,
+ PMIC_BUCK_VSRAM_OTHERS_ANA_ID,
+ PMIC_BUCK_VSRAM_OTHERS_DIG_ID,
+ PMIC_BUCK_VSRAM_OTHERS_ANA_MINOR_REV,
+ PMIC_BUCK_VSRAM_OTHERS_ANA_MAJOR_REV,
+ PMIC_BUCK_VSRAM_OTHERS_DIG_MINOR_REV,
+ PMIC_BUCK_VSRAM_OTHERS_DIG_MAJOR_REV,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_CBS,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_BIX,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_ESP,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_SSHUB,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRACKING,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_PREOC,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_VOTER,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_DLC,
+ PMIC_BUCK_VSRAM_OTHERS_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VSRAM_OTHERS_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_LP,
+ PMIC_RG_BUCK_VSRAM_OTHERS_CON0_SET,
+ PMIC_RG_BUCK_VSRAM_OTHERS_CON0_CLR,
+ PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SELR2R_CTRL,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FRATE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_FEN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_RRATE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SFCHG_REN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_SW_OP_EN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_SET,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_EN_CLR,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_CFG,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_SET,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_CFG_CLR,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW0_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW1_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW2_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW3_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW4_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW5_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW6_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW7_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW8_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW9_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW10_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW11_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW12_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW13_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_HW14_OP_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_SET,
+ PMIC_RG_BUCK_VSRAM_OTHERS_OP_MODE_CLR,
+ PMIC_DA_VSRAM_OTHERS_VOSEL,
+ PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY,
+ PMIC_DA_VSRAM_OTHERS_EN,
+ PMIC_DA_VSRAM_OTHERS_STB,
+ PMIC_DA_VSRAM_OTHERS_LOOP_SEL,
+ PMIC_DA_VSRAM_OTHERS_R2R_PDN,
+ PMIC_DA_VSRAM_OTHERS_DVS_EN,
+ PMIC_DA_VSRAM_OTHERS_DVS_DOWN,
+ PMIC_DA_VSRAM_OTHERS_SSH,
+ PMIC_DA_VSRAM_OTHERS_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_MODE,
+ PMIC_RG_BUCK_VSRAM_OTHERS_CK_SW_EN,
+ PMIC_BUCK_VSRAM_OTHERS_ELR_LEN,
+ PMIC_RG_BUCK_VSRAM_OTHERS_VOSEL,
+ PMIC_BUCK_VMODEM_ANA_ID,
+ PMIC_BUCK_VMODEM_DIG_ID,
+ PMIC_BUCK_VMODEM_ANA_MINOR_REV,
+ PMIC_BUCK_VMODEM_ANA_MAJOR_REV,
+ PMIC_BUCK_VMODEM_DIG_MINOR_REV,
+ PMIC_BUCK_VMODEM_DIG_MAJOR_REV,
+ PMIC_BUCK_VMODEM_DSN_CBS,
+ PMIC_BUCK_VMODEM_DSN_BIX,
+ PMIC_BUCK_VMODEM_DSN_ESP,
+ PMIC_BUCK_VMODEM_DSN_FPI_SSHUB,
+ PMIC_BUCK_VMODEM_DSN_FPI_TRACKING,
+ PMIC_BUCK_VMODEM_DSN_FPI_PREOC,
+ PMIC_BUCK_VMODEM_DSN_FPI_VOTER,
+ PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VMODEM_DSN_FPI_DLC,
+ PMIC_BUCK_VMODEM_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VMODEM_EN,
+ PMIC_RG_BUCK_VMODEM_LP,
+ PMIC_RG_BUCK_VMODEM_CON0_SET,
+ PMIC_RG_BUCK_VMODEM_CON0_CLR,
+ PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VMODEM_SELR2R_CTRL,
+ PMIC_RG_BUCK_VMODEM_SFCHG_FRATE,
+ PMIC_RG_BUCK_VMODEM_SFCHG_FEN,
+ PMIC_RG_BUCK_VMODEM_SFCHG_RRATE,
+ PMIC_RG_BUCK_VMODEM_SFCHG_REN,
+ PMIC_RG_BUCK_VMODEM_HW0_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW1_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW2_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW3_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW4_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW5_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW6_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW7_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW8_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW9_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW10_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW11_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW12_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW13_OP_EN,
+ PMIC_RG_BUCK_VMODEM_HW14_OP_EN,
+ PMIC_RG_BUCK_VMODEM_SW_OP_EN,
+ PMIC_RG_BUCK_VMODEM_OP_EN_SET,
+ PMIC_RG_BUCK_VMODEM_OP_EN_CLR,
+ PMIC_RG_BUCK_VMODEM_HW0_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW1_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW2_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW3_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW4_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW5_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW6_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW7_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW8_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW9_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW10_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW11_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW12_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW13_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_HW14_OP_CFG,
+ PMIC_RG_BUCK_VMODEM_OP_CFG_SET,
+ PMIC_RG_BUCK_VMODEM_OP_CFG_CLR,
+ PMIC_RG_BUCK_VMODEM_HW0_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW1_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW2_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW3_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW4_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW5_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW6_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW7_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW8_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW9_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW10_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW11_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW12_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW13_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_HW14_OP_MODE,
+ PMIC_RG_BUCK_VMODEM_OP_MODE_SET,
+ PMIC_RG_BUCK_VMODEM_OP_MODE_CLR,
+ PMIC_DA_VMODEM_VOSEL,
+ PMIC_DA_VMODEM_VOSEL_GRAY,
+ PMIC_DA_VMODEM_EN,
+ PMIC_DA_VMODEM_STB,
+ PMIC_DA_VMODEM_LOOP_SEL,
+ PMIC_DA_VMODEM_R2R_PDN,
+ PMIC_DA_VMODEM_DVS_EN,
+ PMIC_DA_VMODEM_DVS_DOWN,
+ PMIC_DA_VMODEM_SSH,
+ PMIC_DA_VMODEM_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VMODEM_CK_SW_MODE,
+ PMIC_RG_BUCK_VMODEM_CK_SW_EN,
+ PMIC_BUCK_VMODEM_ELR_LEN,
+ PMIC_RG_BUCK_VMODEM_VOSEL,
+ PMIC_BUCK_VDRAM1_ANA_ID,
+ PMIC_BUCK_VDRAM1_DIG_ID,
+ PMIC_BUCK_VDRAM1_ANA_MINOR_REV,
+ PMIC_BUCK_VDRAM1_ANA_MAJOR_REV,
+ PMIC_BUCK_VDRAM1_DIG_MINOR_REV,
+ PMIC_BUCK_VDRAM1_DIG_MAJOR_REV,
+ PMIC_BUCK_VDRAM1_DSN_CBS,
+ PMIC_BUCK_VDRAM1_DSN_BIX,
+ PMIC_BUCK_VDRAM1_DSN_ESP,
+ PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB,
+ PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING,
+ PMIC_BUCK_VDRAM1_DSN_FPI_PREOC,
+ PMIC_BUCK_VDRAM1_DSN_FPI_VOTER,
+ PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VDRAM1_DSN_FPI_DLC,
+ PMIC_BUCK_VDRAM1_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VDRAM1_EN,
+ PMIC_RG_BUCK_VDRAM1_LP,
+ PMIC_RG_BUCK_VDRAM1_CON0_SET,
+ PMIC_RG_BUCK_VDRAM1_CON0_CLR,
+ PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VDRAM1_SELR2R_CTRL,
+ PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE,
+ PMIC_RG_BUCK_VDRAM1_SFCHG_FEN,
+ PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE,
+ PMIC_RG_BUCK_VDRAM1_SFCHG_REN,
+ PMIC_RG_BUCK_VDRAM1_HW0_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW1_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW2_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW3_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW4_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW5_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW6_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW7_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW8_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW9_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW10_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW11_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW12_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW13_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_HW14_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_SW_OP_EN,
+ PMIC_RG_BUCK_VDRAM1_OP_EN_SET,
+ PMIC_RG_BUCK_VDRAM1_OP_EN_CLR,
+ PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW3_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW4_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW5_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW6_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW7_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW8_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW9_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW10_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW11_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW12_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW13_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_HW14_OP_CFG,
+ PMIC_RG_BUCK_VDRAM1_OP_CFG_SET,
+ PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR,
+ PMIC_RG_BUCK_VDRAM1_HW0_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW1_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW2_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW3_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW4_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW5_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW6_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW7_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW8_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW9_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW10_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW11_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW12_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW13_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_HW14_OP_MODE,
+ PMIC_RG_BUCK_VDRAM1_OP_MODE_SET,
+ PMIC_RG_BUCK_VDRAM1_OP_MODE_CLR,
+ PMIC_DA_VDRAM1_VOSEL,
+ PMIC_DA_VDRAM1_VOSEL_GRAY,
+ PMIC_DA_VDRAM1_EN,
+ PMIC_DA_VDRAM1_STB,
+ PMIC_DA_VDRAM1_LOOP_SEL,
+ PMIC_DA_VDRAM1_R2R_PDN,
+ PMIC_DA_VDRAM1_DVS_EN,
+ PMIC_DA_VDRAM1_DVS_DOWN,
+ PMIC_DA_VDRAM1_SSH,
+ PMIC_DA_VDRAM1_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VDRAM1_CK_SW_MODE,
+ PMIC_RG_BUCK_VDRAM1_CK_SW_EN,
+ PMIC_BUCK_VDRAM1_ELR_LEN,
+ PMIC_RG_BUCK_VDRAM1_VOSEL,
+ PMIC_BUCK_VS1_ANA_ID,
+ PMIC_BUCK_VS1_DIG_ID,
+ PMIC_BUCK_VS1_ANA_MINOR_REV,
+ PMIC_BUCK_VS1_ANA_MAJOR_REV,
+ PMIC_BUCK_VS1_DIG_MINOR_REV,
+ PMIC_BUCK_VS1_DIG_MAJOR_REV,
+ PMIC_BUCK_VS1_DSN_CBS,
+ PMIC_BUCK_VS1_DSN_BIX,
+ PMIC_BUCK_VS1_DSN_ESP,
+ PMIC_BUCK_VS1_DSN_FPI_SSHUB,
+ PMIC_BUCK_VS1_DSN_FPI_TRACKING,
+ PMIC_BUCK_VS1_DSN_FPI_PREOC,
+ PMIC_BUCK_VS1_DSN_FPI_VOTER,
+ PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VS1_DSN_FPI_DLC,
+ PMIC_BUCK_VS1_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VS1_EN,
+ PMIC_RG_BUCK_VS1_LP,
+ PMIC_RG_BUCK_VS1_CON0_SET,
+ PMIC_RG_BUCK_VS1_CON0_CLR,
+ PMIC_RG_BUCK_VS1_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VS1_SELR2R_CTRL,
+ PMIC_RG_BUCK_VS1_SFCHG_FRATE,
+ PMIC_RG_BUCK_VS1_SFCHG_FEN,
+ PMIC_RG_BUCK_VS1_SFCHG_RRATE,
+ PMIC_RG_BUCK_VS1_SFCHG_REN,
+ PMIC_RG_BUCK_VS1_HW0_OP_EN,
+ PMIC_RG_BUCK_VS1_HW1_OP_EN,
+ PMIC_RG_BUCK_VS1_HW2_OP_EN,
+ PMIC_RG_BUCK_VS1_HW3_OP_EN,
+ PMIC_RG_BUCK_VS1_HW4_OP_EN,
+ PMIC_RG_BUCK_VS1_HW5_OP_EN,
+ PMIC_RG_BUCK_VS1_HW6_OP_EN,
+ PMIC_RG_BUCK_VS1_HW7_OP_EN,
+ PMIC_RG_BUCK_VS1_HW8_OP_EN,
+ PMIC_RG_BUCK_VS1_HW9_OP_EN,
+ PMIC_RG_BUCK_VS1_HW10_OP_EN,
+ PMIC_RG_BUCK_VS1_HW11_OP_EN,
+ PMIC_RG_BUCK_VS1_HW12_OP_EN,
+ PMIC_RG_BUCK_VS1_HW13_OP_EN,
+ PMIC_RG_BUCK_VS1_HW14_OP_EN,
+ PMIC_RG_BUCK_VS1_SW_OP_EN,
+ PMIC_RG_BUCK_VS1_OP_EN_SET,
+ PMIC_RG_BUCK_VS1_OP_EN_CLR,
+ PMIC_RG_BUCK_VS1_HW0_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW1_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW2_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW3_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW4_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW5_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW6_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW7_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW8_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW9_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW10_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW11_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW12_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW13_OP_CFG,
+ PMIC_RG_BUCK_VS1_HW14_OP_CFG,
+ PMIC_RG_BUCK_VS1_OP_CFG_SET,
+ PMIC_RG_BUCK_VS1_OP_CFG_CLR,
+ PMIC_RG_BUCK_VS1_HW0_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW1_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW2_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW3_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW4_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW5_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW6_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW7_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW8_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW9_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW10_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW11_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW12_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW13_OP_MODE,
+ PMIC_RG_BUCK_VS1_HW14_OP_MODE,
+ PMIC_RG_BUCK_VS1_OP_MODE_SET,
+ PMIC_RG_BUCK_VS1_OP_MODE_CLR,
+ PMIC_DA_VS1_VOSEL,
+ PMIC_DA_VS1_VOSEL_GRAY,
+ PMIC_DA_VS1_EN,
+ PMIC_DA_VS1_STB,
+ PMIC_DA_VS1_LOOP_SEL,
+ PMIC_DA_VS1_R2R_PDN,
+ PMIC_DA_VS1_DVS_EN,
+ PMIC_DA_VS1_DVS_DOWN,
+ PMIC_DA_VS1_SSH,
+ PMIC_DA_VS1_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VS1_CK_SW_MODE,
+ PMIC_RG_BUCK_VS1_CK_SW_EN,
+ PMIC_RG_BUCK_VS1_VOTER_EN,
+ PMIC_RG_BUCK_VS1_VOTER_EN_SET,
+ PMIC_RG_BUCK_VS1_VOTER_EN_CLR,
+ PMIC_RG_BUCK_VS1_VOTER_VOSEL,
+ PMIC_BUCK_VS1_ELR_LEN,
+ PMIC_RG_BUCK_VS1_VOSEL,
+ PMIC_BUCK_VS2_ANA_ID,
+ PMIC_BUCK_VS2_DIG_ID,
+ PMIC_BUCK_VS2_ANA_MINOR_REV,
+ PMIC_BUCK_VS2_ANA_MAJOR_REV,
+ PMIC_BUCK_VS2_DIG_MINOR_REV,
+ PMIC_BUCK_VS2_DIG_MAJOR_REV,
+ PMIC_BUCK_VS2_DSN_CBS,
+ PMIC_BUCK_VS2_DSN_BIX,
+ PMIC_BUCK_VS2_DSN_ESP,
+ PMIC_BUCK_VS2_DSN_FPI_SSHUB,
+ PMIC_BUCK_VS2_DSN_FPI_TRACKING,
+ PMIC_BUCK_VS2_DSN_FPI_PREOC,
+ PMIC_BUCK_VS2_DSN_FPI_VOTER,
+ PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VS2_DSN_FPI_DLC,
+ PMIC_BUCK_VS2_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VS2_EN,
+ PMIC_RG_BUCK_VS2_LP,
+ PMIC_RG_BUCK_VS2_CON0_SET,
+ PMIC_RG_BUCK_VS2_CON0_CLR,
+ PMIC_RG_BUCK_VS2_VOSEL_SLEEP,
+ PMIC_RG_BUCK_VS2_SELR2R_CTRL,
+ PMIC_RG_BUCK_VS2_SFCHG_FRATE,
+ PMIC_RG_BUCK_VS2_SFCHG_FEN,
+ PMIC_RG_BUCK_VS2_SFCHG_RRATE,
+ PMIC_RG_BUCK_VS2_SFCHG_REN,
+ PMIC_RG_BUCK_VS2_HW0_OP_EN,
+ PMIC_RG_BUCK_VS2_HW1_OP_EN,
+ PMIC_RG_BUCK_VS2_HW2_OP_EN,
+ PMIC_RG_BUCK_VS2_HW3_OP_EN,
+ PMIC_RG_BUCK_VS2_HW4_OP_EN,
+ PMIC_RG_BUCK_VS2_HW5_OP_EN,
+ PMIC_RG_BUCK_VS2_HW6_OP_EN,
+ PMIC_RG_BUCK_VS2_HW7_OP_EN,
+ PMIC_RG_BUCK_VS2_HW8_OP_EN,
+ PMIC_RG_BUCK_VS2_HW9_OP_EN,
+ PMIC_RG_BUCK_VS2_HW10_OP_EN,
+ PMIC_RG_BUCK_VS2_HW11_OP_EN,
+ PMIC_RG_BUCK_VS2_HW12_OP_EN,
+ PMIC_RG_BUCK_VS2_HW13_OP_EN,
+ PMIC_RG_BUCK_VS2_HW14_OP_EN,
+ PMIC_RG_BUCK_VS2_SW_OP_EN,
+ PMIC_RG_BUCK_VS2_OP_EN_SET,
+ PMIC_RG_BUCK_VS2_OP_EN_CLR,
+ PMIC_RG_BUCK_VS2_HW0_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW1_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW2_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW3_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW4_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW5_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW6_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW7_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW8_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW9_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW10_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW11_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW12_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW13_OP_CFG,
+ PMIC_RG_BUCK_VS2_HW14_OP_CFG,
+ PMIC_RG_BUCK_VS2_OP_CFG_SET,
+ PMIC_RG_BUCK_VS2_OP_CFG_CLR,
+ PMIC_RG_BUCK_VS2_HW0_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW1_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW2_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW3_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW4_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW5_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW6_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW7_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW8_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW9_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW10_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW11_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW12_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW13_OP_MODE,
+ PMIC_RG_BUCK_VS2_HW14_OP_MODE,
+ PMIC_RG_BUCK_VS2_OP_MODE_SET,
+ PMIC_RG_BUCK_VS2_OP_MODE_CLR,
+ PMIC_DA_VS2_VOSEL,
+ PMIC_DA_VS2_VOSEL_GRAY,
+ PMIC_DA_VS2_EN,
+ PMIC_DA_VS2_STB,
+ PMIC_DA_VS2_LOOP_SEL,
+ PMIC_DA_VS2_R2R_PDN,
+ PMIC_DA_VS2_DVS_EN,
+ PMIC_DA_VS2_DVS_DOWN,
+ PMIC_DA_VS2_SSH,
+ PMIC_DA_VS2_MINFREQ_DISCHARGE,
+ PMIC_RG_BUCK_VS2_CK_SW_MODE,
+ PMIC_RG_BUCK_VS2_CK_SW_EN,
+ PMIC_RG_BUCK_VS2_VOTER_EN,
+ PMIC_RG_BUCK_VS2_VOTER_EN_SET,
+ PMIC_RG_BUCK_VS2_VOTER_EN_CLR,
+ PMIC_RG_BUCK_VS2_VOTER_VOSEL,
+ PMIC_BUCK_VS2_ELR_LEN,
+ PMIC_RG_BUCK_VS2_VOSEL,
+ PMIC_BUCK_VPA_ANA_ID,
+ PMIC_BUCK_VPA_DIG_ID,
+ PMIC_BUCK_VPA_ANA_MINOR_REV,
+ PMIC_BUCK_VPA_ANA_MAJOR_REV,
+ PMIC_BUCK_VPA_DIG_MINOR_REV,
+ PMIC_BUCK_VPA_DIG_MAJOR_REV,
+ PMIC_BUCK_VPA_DSN_CBS,
+ PMIC_BUCK_VPA_DSN_BIX,
+ PMIC_BUCK_VPA_DSN_ESP,
+ PMIC_BUCK_VPA_DSN_FPI_SSHUB,
+ PMIC_BUCK_VPA_DSN_FPI_TRACKING,
+ PMIC_BUCK_VPA_DSN_FPI_PREOC,
+ PMIC_BUCK_VPA_DSN_FPI_VOTER,
+ PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC,
+ PMIC_BUCK_VPA_DSN_FPI_DLC,
+ PMIC_BUCK_VPA_DSN_FPI_TRAP,
+ PMIC_RG_BUCK_VPA_EN,
+ PMIC_RG_BUCK_VPA_LP,
+ PMIC_RG_BUCK_VPA_CON0_SET,
+ PMIC_RG_BUCK_VPA_CON0_CLR,
+ PMIC_RG_BUCK_VPA_VOSEL,
+ PMIC_RG_BUCK_VPA_SFCHG_FRATE,
+ PMIC_RG_BUCK_VPA_SFCHG_FEN,
+ PMIC_RG_BUCK_VPA_SFCHG_RRATE,
+ PMIC_RG_BUCK_VPA_SFCHG_REN,
+ PMIC_DA_VPA_VOSEL,
+ PMIC_DA_VPA_VOSEL_GRAY,
+ PMIC_DA_VPA_EN,
+ PMIC_DA_VPA_STB,
+ PMIC_DA_VPA_LP_TRANST,
+ PMIC_DA_VPA_DVS_BW,
+ PMIC_DA_VPA_DVS_DOWN,
+ PMIC_DA_VPA_MINFREQ_DISCHARGE,
+ PMIC_DA_VPA_DVS_UP,
+ PMIC_DA_VPA_LOW_IQ,
+ PMIC_RG_BUCK_VPA_CK_SW_MODE,
+ PMIC_RG_BUCK_VPA_CK_SW_EN,
+ PMIC_RG_BUCK_VPA_OC_PROTECT_EN,
+ PMIC_RG_BUCK_VPA_VOSEL_DLC011,
+ PMIC_RG_BUCK_VPA_VOSEL_DLC111,
+ PMIC_RG_BUCK_VPA_VOSEL_DLC001,
+ PMIC_RG_BUCK_VPA_DLC_MAP_EN,
+ PMIC_RG_BUCK_VPA_DLC,
+ PMIC_DA_VPA_DLC,
+ PMIC_RG_BUCK_VPA_MSFG_EN,
+ PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO,
+ PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE0,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE1,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE2,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE3,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE4,
+ PMIC_RG_BUCK_VPA_MSFG_RRATE5,
+ PMIC_RG_BUCK_VPA_MSFG_RTHD0,
+ PMIC_RG_BUCK_VPA_MSFG_RTHD1,
+ PMIC_RG_BUCK_VPA_MSFG_RTHD2,
+ PMIC_RG_BUCK_VPA_MSFG_RTHD3,
+ PMIC_RG_BUCK_VPA_MSFG_RTHD4,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE0,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE1,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE2,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE3,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE4,
+ PMIC_RG_BUCK_VPA_MSFG_FRATE5,
+ PMIC_RG_BUCK_VPA_MSFG_FTHD0,
+ PMIC_RG_BUCK_VPA_MSFG_FTHD1,
+ PMIC_RG_BUCK_VPA_MSFG_FTHD2,
+ PMIC_RG_BUCK_VPA_MSFG_FTHD3,
+ PMIC_RG_BUCK_VPA_MSFG_FTHD4,
+ PMIC_BUCK_ANA0_ANA_ID,
+ PMIC_BUCK_ANA0_DIG_ID,
+ PMIC_BUCK_ANA0_ANA_MINOR_REV,
+ PMIC_BUCK_ANA0_ANA_MAJOR_REV,
+ PMIC_BUCK_ANA0_DIG_MINOR_REV,
+ PMIC_BUCK_ANA0_DIG_MAJOR_REV,
+ PMIC_BUCK_ANA0_DSN_CBS,
+ PMIC_BUCK_ANA0_DSN_BIX,
+ PMIC_BUCK_ANA0_DSN_ESP,
+ PMIC_BUCK_ANA0_DSN_FPI,
+ PMIC_RG_SMPS_TESTMODE_B,
+ PMIC_RG_AUTOK_RST,
+ PMIC_RG_SMPS_DISAUTOK,
+ PMIC_RG_SMPS_VSNS_SEL_EN,
+ PMIC_RG_SMPS_VSNS_SEL_HSIDE,
+ PMIC_RG_SMPS_VSNS_SEL,
+ PMIC_RG_SMPS_SSC_EN,
+ PMIC_RG_VPROC_SR_VBAT,
+ PMIC_RG_VPROC_NDIS_EN,
+ PMIC_RG_VPROC_SR_EN,
+ PMIC_RG_VPROC_SLEEP_TIME,
+ PMIC_RG_VPROC_LOOPSEL_DIS,
+ PMIC_RG_VPROC_TB_DIS,
+ PMIC_RG_VPROC_TB_PFM_OFF,
+ PMIC_RG_VPROC_TB_VREFSEL,
+ PMIC_RG_VPROC_TB_WIDTH,
+ PMIC_RG_VPROC_DUMMY_LOAD_EN,
+ PMIC_RGS_VPROC_DIG_MON,
+ PMIC_RG_VPROC_UG_SR,
+ PMIC_RG_VPROC_LG_SR,
+ PMIC_RG_VPROC_TMDL,
+ PMIC_RG_VPROC_FUGON,
+ PMIC_RG_VPROC_FLGON,
+ PMIC_RG_VPROC_FCCM,
+ PMIC_RG_VPROC_NONAUDIBLE_EN,
+ PMIC_RG_VPROC_RETENTION_EN,
+ PMIC_RG_VPROC_VDIFFPFM_OFF,
+ PMIC_RG_VPROC_DIGMON_SEL,
+ PMIC_RG_VPROC_OCN,
+ PMIC_RG_VPROC_OCP,
+ PMIC_RGS_VPROC_OC_STATUS,
+ PMIC_RG_VPROC_RSV1,
+ PMIC_RG_VPROC_RSV2,
+ PMIC_RG_VPROC_UG_ON_SR,
+ PMIC_RG_VPROC_NLIM_GATING,
+ PMIC_RG_VPROC_NLIM_SRF,
+ PMIC_RG_VPROC_POTECT_KEY,
+ PMIC_RG_VPROC_LXR_EN,
+ PMIC_RG_VPROC_GPIO_OUTPUT,
+ PMIC_RG_VPROC_PARKB,
+ PMIC_RG_VPROC_MOS_TMODE,
+ PMIC_RG_VPROC_DRV_FORCEFAST,
+ PMIC_RG_VPROC_PFM_FP_CUTB,
+ PMIC_RG_VPROC_VDIFFCAP_EN,
+ PMIC_RG_VPROC_VBAT_HI_DIS,
+ PMIC_RG_VPROC_VBAT_LOW_DIS,
+ PMIC_RG_VPROC_VOUT_HI_DIS,
+ PMIC_RG_VPROC_VDIFF_OFF,
+ PMIC_RG_VPROC_SLP_RSV,
+ PMIC_RG_VCORE_SR_VBAT,
+ PMIC_RG_VCORE_NDIS_EN,
+ PMIC_RG_VCORE_SR_EN,
+ PMIC_RG_VCORE_SLEEP_TIME,
+ PMIC_RG_VCORE_LOOPSEL_DIS,
+ PMIC_RG_VCORE_TB_DIS,
+ PMIC_RG_VCORE_TB_PFM_OFF,
+ PMIC_RG_VCORE_TB_VREFSEL,
+ PMIC_RG_VCORE_TB_WIDTH,
+ PMIC_RG_VCORE_DUMMY_LOAD_EN,
+ PMIC_RGS_VCORE_DIG_MON,
+ PMIC_RG_VCORE_UG_SR,
+ PMIC_RG_VCORE_LG_SR,
+ PMIC_RG_VCORE_TMDL,
+ PMIC_RG_VCORE_FUGON,
+ PMIC_RG_VCORE_FLGON,
+ PMIC_RG_VCORE_FCCM,
+ PMIC_RG_VCORE_NONAUDIBLE_EN,
+ PMIC_RG_VCORE_RETENTION_EN,
+ PMIC_RG_VCORE_VDIFFPFM_OFF,
+ PMIC_RG_VCORE_DIGMON_SEL,
+ PMIC_RG_VCORE_OCN,
+ PMIC_RG_VCORE_OCP,
+ PMIC_RGS_VCORE_OC_STATUS,
+ PMIC_RG_VCORE_RSV1,
+ PMIC_RG_VCORE_RSV2,
+ PMIC_RG_VCORE_UG_ON_SR,
+ PMIC_RG_VCORE_NLIM_GATING,
+ PMIC_RG_VCORE_NLIM_SRF,
+ PMIC_RG_VCORE_POTECT_KEY,
+ PMIC_RG_VCORE_LXR_EN,
+ PMIC_RG_VCORE_GPIO_OUTPUT,
+ PMIC_RG_VCORE_PARKB,
+ PMIC_RG_VCORE_MOS_TMODE,
+ PMIC_RG_VCORE_DRV_FORCEFAST,
+ PMIC_RG_VCORE_PFM_FP_CUTB,
+ PMIC_RG_VCORE_VDIFFCAP_EN,
+ PMIC_RG_VCORE_VBAT_HI_DIS,
+ PMIC_RG_VCORE_VBAT_LOW_DIS,
+ PMIC_RG_VCORE_VOUT_HI_DIS,
+ PMIC_RG_VCORE_VDIFF_OFF,
+ PMIC_RG_VCORE_SLP_RSV,
+ PMIC_BUCK_ANA0_ELR_LEN,
+ PMIC_RG_VPROC_DRIVER_SR_TRIM,
+ PMIC_RG_VPROC_CCOMP,
+ PMIC_RG_VPROC_RCOMP,
+ PMIC_RG_VPROC_NLIM_TRIM,
+ PMIC_RG_VPROC_PWMRAMP_SLP,
+ PMIC_RG_VPROC_CSNSLP_TRIM,
+ PMIC_RG_VPROC_ZC_TRIM,
+ PMIC_RG_VPROC_COTRAMP_SLP,
+ PMIC_RG_VPROC_RCS,
+ PMIC_RG_VPROC_CSPSLP_TRIM,
+ PMIC_RG_VPROC_PFM_PEAK_TRIM,
+ PMIC_RG_VPROC_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VCORE_DRIVER_SR_TRIM,
+ PMIC_RG_VCORE_CCOMP,
+ PMIC_RG_VCORE_RCOMP,
+ PMIC_RG_VCORE_NLIM_TRIM,
+ PMIC_RG_VCORE_PWMRAMP_SLP,
+ PMIC_RG_VCORE_CSNSLP_TRIM,
+ PMIC_RG_VCORE_ZC_TRIM,
+ PMIC_RG_VCORE_COTRAMP_SLP,
+ PMIC_RG_VCORE_RCS,
+ PMIC_RG_VCORE_CSPSLP_TRIM,
+ PMIC_RG_VCORE_PFM_PEAK_TRIM,
+ PMIC_RG_VCORE_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VS1_TRIMH,
+ PMIC_RG_VS2_TRIMH,
+ PMIC_RG_VDRAM1_TRIMH,
+ PMIC_RG_VPROC_TRIMH,
+ PMIC_RG_VCORE_TRIMH,
+ PMIC_RG_VMODEM_TRIMH,
+ PMIC_RG_VSRAM_OTHERS_TRIMH,
+ PMIC_RG_VPA_TRIMH,
+ PMIC_RG_VSRAM_PROC_TRIMH,
+ PMIC_BUCK_ANA1_ANA_ID,
+ PMIC_BUCK_ANA1_DIG_ID,
+ PMIC_BUCK_ANA1_ANA_MINOR_REV,
+ PMIC_BUCK_ANA1_ANA_MAJOR_REV,
+ PMIC_BUCK_ANA1_DIG_MINOR_REV,
+ PMIC_BUCK_ANA1_DIG_MAJOR_REV,
+ PMIC_BUCK_ANA1_DSN_CBS,
+ PMIC_BUCK_ANA1_DSN_BIX,
+ PMIC_BUCK_ANA1_DSN_ESP,
+ PMIC_BUCK_ANA1_DSN_FPI,
+ PMIC_RG_VMODEM_SR_VBAT,
+ PMIC_RG_VMODEM_NDIS_EN,
+ PMIC_RG_VMODEM_SR_EN,
+ PMIC_RG_VMODEM_SLEEP_TIME,
+ PMIC_RG_VMODEM_LOOPSEL_DIS,
+ PMIC_RG_VMODEM_TB_DIS,
+ PMIC_RG_VMODEM_TB_PFM_OFF,
+ PMIC_RG_VMODEM_TB_VREFSEL,
+ PMIC_RG_VMODEM_TB_WIDTH,
+ PMIC_RG_VMODEM_DUMMY_LOAD_EN,
+ PMIC_RGS_VMODEM_DIG_MON,
+ PMIC_RG_VMODEM_UG_SR,
+ PMIC_RG_VMODEM_LG_SR,
+ PMIC_RG_VMODEM_TMDL,
+ PMIC_RG_VMODEM_FUGON,
+ PMIC_RG_VMODEM_FLGON,
+ PMIC_RG_VMODEM_FCCM,
+ PMIC_RG_VMODEM_NONAUDIBLE_EN,
+ PMIC_RG_VMODEM_RETENTION_EN,
+ PMIC_RG_VMODEM_VDIFFPFM_OFF,
+ PMIC_RG_VMODEM_DIGMON_SEL,
+ PMIC_RG_VMODEM_OCN,
+ PMIC_RG_VMODEM_OCP,
+ PMIC_RGS_VMODEM_OC_STATUS,
+ PMIC_RG_VMODEM_RSV1,
+ PMIC_RG_VMODEM_RSV2,
+ PMIC_RG_VMODEM_UG_ON_SR,
+ PMIC_RG_VMODEM_NLIM_GATING,
+ PMIC_RG_VMODEM_NLIM_SRF,
+ PMIC_RG_VMODEM_POTECT_KEY,
+ PMIC_RG_VMODEM_LXR_EN,
+ PMIC_RG_VMODEM_GPIO_OUTPUT,
+ PMIC_RG_VMODEM_PARKB,
+ PMIC_RG_VMODEM_MOS_TMODE,
+ PMIC_RG_VMODEM_DRV_FORCEFAST,
+ PMIC_RG_VMODEM_PFM_FP_CUTB,
+ PMIC_RG_VMODEM_VDIFFCAP_EN,
+ PMIC_RG_VMODEM_VBAT_HI_DIS,
+ PMIC_RG_VMODEM_VBAT_LOW_DIS,
+ PMIC_RG_VMODEM_VOUT_HI_DIS,
+ PMIC_RG_VMODEM_VDIFF_OFF,
+ PMIC_RG_VMODEM_SLP_RSV,
+ PMIC_RG_VS1_TB_DIS,
+ PMIC_RG_VS1_FCCM,
+ PMIC_RG_VS1_UG_SR,
+ PMIC_RG_VS1_LG_SR,
+ PMIC_RG_VS1_POTECT_KEY,
+ PMIC_RG_VS1_NLIM_GATING,
+ PMIC_RG_VS1_SLEEP_TIME,
+ PMIC_RG_VS1_VREFUP,
+ PMIC_RG_VS1_TB_WIDTH,
+ PMIC_RG_VS1_NDIS_EN,
+ PMIC_RG_VS1_RSV1,
+ PMIC_RG_VS1_RSV2,
+ PMIC_RG_VS1_FUGON,
+ PMIC_RG_VS1_FLGON,
+ PMIC_RG_VS1_OCP,
+ PMIC_RG_VS1_OCN,
+ PMIC_RGS_VS1_OC_STATUS,
+ PMIC_RG_VS1_TMDL,
+ PMIC_RGS_VS1_DIG_MON,
+ PMIC_RG_VS1_NONAUDIBLE_EN,
+ PMIC_RG_VS1_LXR_EN,
+ PMIC_RG_VS1_DIGMON_SEL,
+ PMIC_RG_VS1_UG_ON_SR,
+ PMIC_RG_VS1_GPIO_OUTPUT,
+ PMIC_RG_VS1_PARKB,
+ PMIC_RG_VS1_NLIM_SRF,
+ PMIC_RG_VS1_PFM_FP_CUTB,
+ PMIC_RG_VS1_MOS_TMODE,
+ PMIC_RG_VS1_DISPG,
+ PMIC_RG_VS1_VBATHI_PK_DIS,
+ PMIC_RG_VS1_PKBS,
+ PMIC_RG_VS1_VDIFFPFM_OFF,
+ PMIC_RG_VS1_VDIFF_OFF,
+ PMIC_RG_VS1_VDIFF_CAP_EN,
+ PMIC_RG_VS2_TB_DIS,
+ PMIC_RG_VS2_FCCM,
+ PMIC_RG_VS2_UG_SR,
+ PMIC_RG_VS2_LG_SR,
+ PMIC_RG_VS2_POTECT_KEY,
+ PMIC_RG_VS2_NLIM_GATING,
+ PMIC_RG_VS2_SLEEP_TIME,
+ PMIC_RG_VS2_VREFUP,
+ PMIC_RG_VS2_TB_WIDTH,
+ PMIC_RG_VS2_NDIS_EN,
+ PMIC_RG_VS2_RSV1,
+ PMIC_RG_VS2_RSV2,
+ PMIC_RG_VS2_FUGON,
+ PMIC_RG_VS2_FLGON,
+ PMIC_RG_VS2_OCP,
+ PMIC_RG_VS2_OCN,
+ PMIC_RGS_VS2_OC_STATUS,
+ PMIC_RG_VS2_TMDL,
+ PMIC_RGS_VS2_DIG_MON,
+ PMIC_RG_VS2_NONAUDIBLE_EN,
+ PMIC_RG_VS2_LXR_EN,
+ PMIC_RG_VS2_DIGMON_SEL,
+ PMIC_RG_VS2_UG_ON_SR,
+ PMIC_RG_VS2_GPIO_OUTPUT,
+ PMIC_RG_VS2_PARKB,
+ PMIC_RG_VS2_NLIM_SRF,
+ PMIC_RG_VS2_PFM_FP_CUTB,
+ PMIC_RG_VS2_MOS_TMODE,
+ PMIC_RG_VS2_DISPG,
+ PMIC_RG_VS2_VBATHI_PK_DIS,
+ PMIC_RG_VS2_PKBS,
+ PMIC_RG_VS2_VDIFFPFM_OFF,
+ PMIC_RG_VS2_VDIFF_OFF,
+ PMIC_RG_VS2_VDIFF_CAP_EN,
+ PMIC_RG_VPA_NDIS_EN,
+ PMIC_RG_VPA_MODESET,
+ PMIC_RG_VPA_CC,
+ PMIC_RG_VPA_CSR,
+ PMIC_RG_VPA_CSMIR,
+ PMIC_RG_VPA_CSL,
+ PMIC_RG_VPA_SLP,
+ PMIC_RG_VPA_ZXFT_L,
+ PMIC_RG_VPA_CP_FWUPOFF,
+ PMIC_RG_VPA_NONAUDIBLE_EN,
+ PMIC_RG_VPA_RZSEL,
+ PMIC_RG_VPA_SLEW,
+ PMIC_RG_VPA_SLEW_NMOS,
+ PMIC_RG_VPA_MIN_ON,
+ PMIC_RG_VPA_BURST_SEL,
+ PMIC_RG_VPA_ZC,
+ PMIC_RG_VPA_RSV1,
+ PMIC_RG_VPA_RSV2,
+ PMIC_RGS_VPA_OC_STATUS,
+ PMIC_RGS_VPA_AZC_ZX,
+ PMIC_RGS_VPA_DIG_MON,
+ PMIC_RG_VPA_PFM_DLC1_VTH,
+ PMIC_RG_VPA_PFM_DLC2_VTH,
+ PMIC_RG_VPA_PFM_DLC3_VTH,
+ PMIC_RG_VPA_PFM_DLC4_VTH,
+ PMIC_RG_VPA_ZXFT_H,
+ PMIC_RG_VPA_DECODE_TMB,
+ PMIC_RG_VPA_RSV3,
+ PMIC_RG_VPA_DGM_RSV1_V18,
+ PMIC_RG_VPA_DGM_EN_V18,
+ PMIC_RG_VPA_DGM_IMAX_SEL_V18,
+ PMIC_RG_VPA_DGM_S0_VTH_V18,
+ PMIC_RG_VPA_DGM_S1_VTH_V18,
+ PMIC_RG_VPA_DVS_HYS_EN_V18,
+ PMIC_RG_VPA_DGM_RSV2_V18,
+ PMIC_RG_VPA_DGM_S2_VTH_V18,
+ PMIC_RG_VPA_DGM_S3_VTH_V18,
+ PMIC_RG_VPA_HYS_VTH_V18,
+ PMIC_RG_VDRAM1_TB_DIS,
+ PMIC_RG_VDRAM1_FCCM,
+ PMIC_RG_VDRAM1_UG_SR,
+ PMIC_RG_VDRAM1_LG_SR,
+ PMIC_RG_VDRAM1_POTECT_KEY,
+ PMIC_RG_VDRAM1_NLIM_GATING,
+ PMIC_RG_VDRAM1_SLEEP_TIME,
+ PMIC_RG_VDRAM1_VREFUP,
+ PMIC_RG_VDRAM1_TB_WIDTH,
+ PMIC_RG_VDRAM1_NDIS_EN,
+ PMIC_RG_VDRAM1_RSV1,
+ PMIC_RG_VDRAM1_RSV2,
+ PMIC_RG_VDRAM1_FUGON,
+ PMIC_RG_VDRAM1_FLGON,
+ PMIC_RG_VDRAM1_OCP,
+ PMIC_RG_VDRAM1_OCN,
+ PMIC_RGS_VDRAM1_OC_STATUS,
+ PMIC_RG_VDRAM1_TMDL,
+ PMIC_RGS_VDRAM1_DIG_MON,
+ PMIC_RG_VDRAM1_NONAUDIBLE_EN,
+ PMIC_RG_VDRAM1_LXR_EN,
+ PMIC_RG_VDRAM1_DIGMON_SEL,
+ PMIC_RG_VDRAM1_UG_ON_SR,
+ PMIC_RG_VDRAM1_GPIO_OUTPUT,
+ PMIC_RG_VDRAM1_PARKB,
+ PMIC_RG_VDRAM1_NLIM_SRF,
+ PMIC_RG_VDRAM1_PFM_FP_CUTB,
+ PMIC_RG_VDRAM1_MOS_TMODE,
+ PMIC_RG_VDRAM1_DISPG,
+ PMIC_RG_VDRAM1_VBATHI_PK_DIS,
+ PMIC_RG_VDRAM1_PKBS,
+ PMIC_RG_VDRAM1_VDIFFPFM_OFF,
+ PMIC_RG_VDRAM1_VDIFF_OFF,
+ PMIC_RG_VDRAM1_VDIFF_CAP_EN,
+ PMIC_RG_VSRAM_OTHERS_SR_VBAT,
+ PMIC_RG_VSRAM_OTHERS_NDIS_EN,
+ PMIC_RG_VSRAM_OTHERS_SR_EN,
+ PMIC_RG_VSRAM_OTHERS_SLEEP_TIME,
+ PMIC_RG_VSRAM_OTHERS_LOOPSEL_DIS,
+ PMIC_RG_VSRAM_OTHERS_TB_DIS,
+ PMIC_RG_VSRAM_OTHERS_TB_PFM_OFF,
+ PMIC_RG_VSRAM_OTHERS_TB_VREFSEL,
+ PMIC_RG_VSRAM_OTHERS_TB_WIDTH,
+ PMIC_RG_VSRAM_OTHERS_DUMMY_LOAD_EN,
+ PMIC_RGS_VSRAM_OTHERS_DIG_MON,
+ PMIC_RG_VSRAM_OTHERS_UG_SR,
+ PMIC_RG_VSRAM_OTHERS_LG_SR,
+ PMIC_RG_VSRAM_OTHERS_TMDL,
+ PMIC_RG_VSRAM_OTHERS_FUGON,
+ PMIC_RG_VSRAM_OTHERS_FLGON,
+ PMIC_RG_VSRAM_OTHERS_FCCM,
+ PMIC_RG_VSRAM_OTHERS_NONAUDIBLE_EN,
+ PMIC_RG_VSRAM_OTHERS_RETENTION_EN,
+ PMIC_RG_VSRAM_OTHERS_VDIFFPFM_OFF,
+ PMIC_RG_VSRAM_OTHERS_DIGMON_SEL,
+ PMIC_RG_VSRAM_OTHERS_OCN,
+ PMIC_RG_VSRAM_OTHERS_OCP,
+ PMIC_RGS_VSRAM_OTHERS_OC_STATUS,
+ PMIC_RG_VSRAM_OTHERS_RSV1,
+ PMIC_RG_VSRAM_OTHERS_RSV2,
+ PMIC_RG_VSRAM_OTHERS_UG_ON_SR,
+ PMIC_RG_VSRAM_OTHERS_NLIM_GATING,
+ PMIC_RG_VSRAM_OTHERS_NLIM_SRF,
+ PMIC_RG_VSRAM_OTHERS_POTECT_KEY,
+ PMIC_RG_VSRAM_OTHERS_LXR_EN,
+ PMIC_RG_VSRAM_OTHERS_GPIO_OUTPUT,
+ PMIC_RG_VSRAM_OTHERS_PARKB,
+ PMIC_RG_VSRAM_OTHERS_MOS_TMODE,
+ PMIC_RG_VSRAM_OTHERS_DRV_FORCEFAST,
+ PMIC_RG_VSRAM_OTHERS_PFM_FP_CUTB,
+ PMIC_RG_VSRAM_OTHERS_VDIFFCAP_EN,
+ PMIC_RG_VSRAM_OTHERS_VBAT_HI_DIS,
+ PMIC_RG_VSRAM_OTHERS_VBAT_LOW_DIS,
+ PMIC_RG_VSRAM_OTHERS_VOUT_HI_DIS,
+ PMIC_RG_VSRAM_OTHERS_VDIFF_OFF,
+ PMIC_RG_VSRAM_OTHERS_SLP_RSV,
+ PMIC_BUCK_ANA1_ELR_LEN,
+ PMIC_RG_VMODEM_DRIVER_SR_TRIM,
+ PMIC_RG_VMODEM_CCOMP,
+ PMIC_RG_VMODEM_RCOMP,
+ PMIC_RG_VMODEM_NLIM_TRIM,
+ PMIC_RG_VMODEM_PWMRAMP_SLP,
+ PMIC_RG_VMODEM_CSNSLP_TRIM,
+ PMIC_RG_VMODEM_ZC_TRIM,
+ PMIC_RG_VMODEM_COTRAMP_SLP,
+ PMIC_RG_VMODEM_RCS,
+ PMIC_RG_VMODEM_CSPSLP_TRIM,
+ PMIC_RG_VMODEM_PFM_PEAK_TRIM,
+ PMIC_RG_VMODEM_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VS1_CSNSLP_TRIM,
+ PMIC_RG_VS1_RCOMP,
+ PMIC_RG_VS1_CCOMP,
+ PMIC_RG_VS1_PWMRAMP_SLP,
+ PMIC_RG_VS1_COTRAMP_SLP,
+ PMIC_RG_VS1_CSPSLP_TRIM,
+ PMIC_RG_VS1_ZC_TRIM,
+ PMIC_RG_VS1_LDO_SENSE,
+ PMIC_RG_VS1_NLIM_TRIM,
+ PMIC_RG_VS1_RCS,
+ PMIC_RG_VS1_PFM_PEAK_TRIM,
+ PMIC_RG_VS1_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VS2_CSNSLP_TRIM,
+ PMIC_RG_VS2_RCOMP,
+ PMIC_RG_VS2_CCOMP,
+ PMIC_RG_VS2_PWMRAMP_SLP,
+ PMIC_RG_VS2_COTRAMP_SLP,
+ PMIC_RG_VS2_CSPSLP_TRIM,
+ PMIC_RG_VS2_ZC_TRIM,
+ PMIC_RG_VS2_LDO_SENSE,
+ PMIC_RG_VS2_NLIM_TRIM,
+ PMIC_RG_VS2_RCS,
+ PMIC_RG_VS2_PFM_PEAK_TRIM,
+ PMIC_RG_VS2_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VDRAM1_CSNSLP_TRIM,
+ PMIC_RG_VDRAM1_RCOMP,
+ PMIC_RG_VDRAM1_CCOMP,
+ PMIC_RG_VDRAM1_PWMRAMP_SLP,
+ PMIC_RG_VDRAM1_COTRAMP_SLP,
+ PMIC_RG_VDRAM1_CSPSLP_TRIM,
+ PMIC_RG_VDRAM1_ZC_TRIM,
+ PMIC_RG_VDRAM1_LDO_SENSE,
+ PMIC_RG_VDRAM1_NLIM_TRIM,
+ PMIC_RG_VDRAM1_RCS,
+ PMIC_RG_VDRAM1_PFM_PEAK_TRIM,
+ PMIC_RG_VDRAM1_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VSRAM_OTHERS_DRIVER_SR_TRIM,
+ PMIC_RG_VSRAM_OTHERS_CCOMP,
+ PMIC_RG_VSRAM_OTHERS_RCOMP,
+ PMIC_RG_VSRAM_OTHERS_NLIM_TRIM,
+ PMIC_RG_VSRAM_OTHERS_PWMRAMP_SLP,
+ PMIC_RG_VSRAM_OTHERS_CSNSLP_TRIM,
+ PMIC_RG_VSRAM_OTHERS_ZC_TRIM,
+ PMIC_RG_VSRAM_OTHERS_COTRAMP_SLP,
+ PMIC_RG_VSRAM_OTHERS_RCS,
+ PMIC_RG_VSRAM_OTHERS_CSPSLP_TRIM,
+ PMIC_RG_VSRAM_OTHERS_PFM_PEAK_TRIM,
+ PMIC_RG_VSRAM_OTHERS_SONIC_PFM_PEAK_TRIM,
+ PMIC_RG_VS1_RPSI_TRIM,
+ PMIC_RG_VS1_4R2R_VDIFF,
+ PMIC_RG_VS1_1A_SEL,
+ PMIC_RG_VS2_RPSI_TRIM,
+ PMIC_RG_VS2_4R2R_VDIFF,
+ PMIC_RG_VS2_1A_SEL,
+ PMIC_RG_VPA_NLIM_SEL,
+ PMIC_RG_VDRAM1_RPSI_TRIM,
+ PMIC_RG_VDRAM1_4R2R_VDIFF,
+ PMIC_RG_VDRAM1_1A_SEL,
+ PMIC_LDO_TOP_ANA_ID,
+ PMIC_LDO_TOP_DIG_ID,
+ PMIC_LDO_TOP_ANA_MINOR_REV,
+ PMIC_LDO_TOP_ANA_MAJOR_REV,
+ PMIC_LDO_TOP_DIG_MINOR_REV,
+ PMIC_LDO_TOP_DIG_MAJOR_REV,
+ PMIC_LDO_TOP_CBS,
+ PMIC_LDO_TOP_BIX,
+ PMIC_LDO_TOP_ESP,
+ PMIC_LDO_TOP_FPI,
+ PMIC_LDO_TOP_CLK_OFFSET,
+ PMIC_LDO_TOP_RST_OFFSET,
+ PMIC_LDO_TOP_INT_OFFSET,
+ PMIC_LDO_TOP_INT_LEN,
+ PMIC_RG_LDO_32K_CK_PDN,
+ PMIC_RG_LDO_INTRP_CK_PDN,
+ PMIC_RG_LDO_1M_CK_PDN,
+ PMIC_RG_LDO_26M_CK_PDN,
+ PMIC_RG_LDO_32K_CK_PDN_HWEN,
+ PMIC_RG_LDO_INTRP_CK_PDN_HWEN,
+ PMIC_RG_LDO_1M_CK_PDN_HWEN,
+ PMIC_RG_LDO_26M_CK_PDN_HWEN,
+ PMIC_RG_LDO_DCM_MODE,
+ PMIC_RG_INT_EN_VFE28_OC,
+ PMIC_RG_INT_EN_VRF18_OC,
+ PMIC_RG_INT_EN_VRF12_OC,
+ PMIC_RG_INT_EN_VGP3_OC,
+ PMIC_RG_INT_EN_VCN33_OC,
+ PMIC_RG_INT_EN_VCN18_OC,
+ PMIC_RG_INT_EN_VA12_OC,
+ PMIC_RG_INT_EN_VA09_OC,
+ PMIC_RG_INT_EN_VAUX18_OC,
+ PMIC_RG_INT_EN_VAUD28_OC,
+ PMIC_RG_INT_EN_VIO18_OC,
+ PMIC_RG_INT_EN_VIO33_OC,
+ PMIC_RG_INT_EN_VGP1_OC,
+ PMIC_RG_INT_EN_VGP2_OC,
+ PMIC_RG_INT_EN_VSRAM_PROC_OC,
+ PMIC_RG_INT_EN_VDRAM2_OC,
+ PMIC_LDO_INT_CON0_SET,
+ PMIC_LDO_INT_CON0_CLR,
+ PMIC_RG_INT_MASK_VFE28_OC,
+ PMIC_RG_INT_MASK_VRF18_OC,
+ PMIC_RG_INT_MASK_VRF12_OC,
+ PMIC_RG_INT_MASK_VGP3_OC,
+ PMIC_RG_INT_MASK_VCN33_OC,
+ PMIC_RG_INT_MASK_VCN18_OC,
+ PMIC_RG_INT_MASK_VA12_OC,
+ PMIC_RG_INT_MASK_VA09_OC,
+ PMIC_RG_INT_MASK_VAUX18_OC,
+ PMIC_RG_INT_MASK_VAUD28_OC,
+ PMIC_RG_INT_MASK_VIO18_OC,
+ PMIC_RG_INT_MASK_VIO33_OC,
+ PMIC_RG_INT_MASK_VGP1_OC,
+ PMIC_RG_INT_MASK_VGP2_OC,
+ PMIC_RG_INT_MASK_VSRAM_PROC_OC,
+ PMIC_RG_INT_MASK_VDRAM2_OC,
+ PMIC_LDO_INT_MASK_CON0_SET,
+ PMIC_LDO_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_VFE28_OC,
+ PMIC_RG_INT_STATUS_VRF18_OC,
+ PMIC_RG_INT_STATUS_VRF12_OC,
+ PMIC_RG_INT_STATUS_VGP3_OC,
+ PMIC_RG_INT_STATUS_VCN33_OC,
+ PMIC_RG_INT_STATUS_VCN18_OC,
+ PMIC_RG_INT_STATUS_VA12_OC,
+ PMIC_RG_INT_STATUS_VA09_OC,
+ PMIC_RG_INT_STATUS_VAUX18_OC,
+ PMIC_RG_INT_STATUS_VAUD28_OC,
+ PMIC_RG_INT_STATUS_VIO18_OC,
+ PMIC_RG_INT_STATUS_VIO33_OC,
+ PMIC_RG_INT_STATUS_VGP1_OC,
+ PMIC_RG_INT_STATUS_VGP2_OC,
+ PMIC_RG_INT_STATUS_VSRAM_PROC_OC,
+ PMIC_RG_INT_STATUS_VDRAM2_OC,
+ PMIC_RG_INT_RAW_STATUS_VFE28_OC,
+ PMIC_RG_INT_RAW_STATUS_VRF18_OC,
+ PMIC_RG_INT_RAW_STATUS_VRF12_OC,
+ PMIC_RG_INT_RAW_STATUS_VGP3_OC,
+ PMIC_RG_INT_RAW_STATUS_VCN33_OC,
+ PMIC_RG_INT_RAW_STATUS_VCN18_OC,
+ PMIC_RG_INT_RAW_STATUS_VA12_OC,
+ PMIC_RG_INT_RAW_STATUS_VA09_OC,
+ PMIC_RG_INT_RAW_STATUS_VAUX18_OC,
+ PMIC_RG_INT_RAW_STATUS_VAUD28_OC,
+ PMIC_RG_INT_RAW_STATUS_VIO18_OC,
+ PMIC_RG_INT_RAW_STATUS_VIO33_OC,
+ PMIC_RG_INT_RAW_STATUS_VGP1_OC,
+ PMIC_RG_INT_RAW_STATUS_VGP2_OC,
+ PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC,
+ PMIC_RG_INT_RAW_STATUS_VDRAM2_OC,
+ PMIC_RG_INT_EN_VMCH_OC,
+ PMIC_RG_INT_EN_VEMC_OC,
+ PMIC_RG_INT_EN_VSIM1_OC,
+ PMIC_RG_INT_EN_VSIM2_OC,
+ PMIC_RG_INT_EN_VUSB_OC,
+ PMIC_RG_INT_EN_VXO22_OC,
+ PMIC_RG_INT_EN_VRFCK_OC,
+ PMIC_RG_INT_EN_VBBCK_OC,
+ PMIC_LDO_INT_CON1_SET,
+ PMIC_LDO_INT_CON1_CLR,
+ PMIC_RG_INT_MASK_VMCH_OC,
+ PMIC_RG_INT_MASK_VEMC_OC,
+ PMIC_RG_INT_MASK_VSIM1_OC,
+ PMIC_RG_INT_MASK_VSIM2_OC,
+ PMIC_RG_INT_MASK_VUSB_OC,
+ PMIC_RG_INT_MASK_VXO22_OC,
+ PMIC_RG_INT_MASK_VRFCK_OC,
+ PMIC_RG_INT_MASK_VBBCK_OC,
+ PMIC_LDO_INT_MASK_CON1_SET,
+ PMIC_LDO_INT_MASK_CON1_CLR,
+ PMIC_RG_INT_STATUS_VMCH_OC,
+ PMIC_RG_INT_STATUS_VEMC_OC,
+ PMIC_RG_INT_STATUS_VSIM1_OC,
+ PMIC_RG_INT_STATUS_VSIM2_OC,
+ PMIC_RG_INT_STATUS_VUSB_OC,
+ PMIC_RG_INT_STATUS_VXO22_OC,
+ PMIC_RG_INT_STATUS_VRFCK_OC,
+ PMIC_RG_INT_STATUS_VBBCK_OC,
+ PMIC_RG_INT_RAW_STATUS_VMCH_OC,
+ PMIC_RG_INT_RAW_STATUS_VEMC_OC,
+ PMIC_RG_INT_RAW_STATUS_VSIM1_OC,
+ PMIC_RG_INT_RAW_STATUS_VSIM2_OC,
+ PMIC_RG_INT_RAW_STATUS_VUSB_OC,
+ PMIC_RG_INT_RAW_STATUS_VXO22_OC,
+ PMIC_RG_INT_RAW_STATUS_VRFCK_OC,
+ PMIC_RG_INT_RAW_STATUS_VBBCK_OC,
+ PMIC_RG_LDO_MON_FLAG_SEL,
+ PMIC_RG_LDO_INT_FLAG_EN,
+ PMIC_RG_LDO_MON_GRP_SEL,
+ PMIC_RG_LDO_L_E_LP_DIS,
+ PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS,
+ PMIC_RG_LDO_LP_PROT_DISABLE,
+ PMIC_RG_LDO_SLEEP_CTRL_MODE,
+ PMIC_RG_LDO_VSRAM_WAKEUP_TIME,
+ PMIC_RG_LDO_EINT_POL,
+ PMIC_RG_LDO_IVGENCHK,
+ PMIC_RG_LDO_TOP_RSV1,
+ PMIC_RG_LDO_TOP_RSV0,
+ PMIC_LDO_WRITE_KEY,
+ PMIC_RG_VRTC28_EN,
+ PMIC_DA_VRTC28_EN,
+ PMIC_RG_VAUX18_OFF_ACKTIME_SEL,
+ PMIC_RG_VAUX18_LP_ACKTIME_SEL,
+ PMIC_RG_TREF_EN,
+ PMIC_RG_TREF_OFF_ACKTIME_SEL,
+ PMIC_DA_TREF_EN,
+ PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE,
+ PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE,
+ PMIC_DA_VDRAM2_VOSEL,
+ PMIC_DA_VDRAM2_VOCAL,
+ PMIC_LDO_TOP_ELR_LEN,
+ PMIC_RG_LDO_VRFCK_ANA_SEL,
+ PMIC_RG_VDRAM2_VOSEL_0,
+ PMIC_RG_VDRAM2_VOCAL_0,
+ PMIC_RG_VDRAM2_VOSEL_1,
+ PMIC_RG_VDRAM2_VOCAL_1,
+ PMIC_LDO_GNR0_ANA_ID,
+ PMIC_LDO_GNR0_DIG_ID,
+ PMIC_LDO_GNR0_ANA_MINOR_REV,
+ PMIC_LDO_GNR0_ANA_MAJOR_REV,
+ PMIC_LDO_GNR0_DIG_MINOR_REV,
+ PMIC_LDO_GNR0_DIG_MAJOR_REV,
+ PMIC_LDO_GNR0_DSN_CBS,
+ PMIC_LDO_GNR0_DSN_BIX,
+ PMIC_LDO_GNR0_DSN_ESP,
+ PMIC_LDO_GNR0_DSN_FPI,
+ PMIC_RG_LDO_VFE28_EN,
+ PMIC_RG_LDO_VFE28_LP,
+ PMIC_RG_LDO_VFE28_STBTD,
+ PMIC_RG_LDO_VFE28_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VFE28_OC_FUNC_EN,
+ PMIC_RG_LDO_VFE28_OC_MODE,
+ PMIC_RG_LDO_VFE28_OC_TSEL,
+ PMIC_RG_LDO_VFE28_DUMMY_LOAD,
+ PMIC_RG_LDO_VFE28_CK_SW_MODE,
+ PMIC_DA_VFE28_B_EN,
+ PMIC_DA_VFE28_B_STB,
+ PMIC_DA_VFE28_B_LP,
+ PMIC_DA_VFE28_LINE_ENHANCE,
+ PMIC_DA_VFE28_OCFB_EN,
+ PMIC_DA_VFE28_DUMMY_LOAD,
+ PMIC_RG_LDO_VFE28_HW0_OP_EN,
+ PMIC_RG_LDO_VFE28_HW1_OP_EN,
+ PMIC_RG_LDO_VFE28_HW2_OP_EN,
+ PMIC_RG_LDO_VFE28_HW3_OP_EN,
+ PMIC_RG_LDO_VFE28_SW_OP_EN,
+ PMIC_RG_LDO_VFE28_OP_EN_SET,
+ PMIC_RG_LDO_VFE28_OP_EN_CLR,
+ PMIC_RG_LDO_VFE28_HW0_OP_CFG,
+ PMIC_RG_LDO_VFE28_HW1_OP_CFG,
+ PMIC_RG_LDO_VFE28_HW2_OP_CFG,
+ PMIC_RG_LDO_VFE28_HW3_OP_CFG,
+ PMIC_RG_LDO_VFE28_OP_CFG_SET,
+ PMIC_RG_LDO_VFE28_OP_CFG_CLR,
+ PMIC_RG_LDO_VRF18_EN,
+ PMIC_RG_LDO_VRF18_LP,
+ PMIC_RG_LDO_VRF18_STBTD,
+ PMIC_RG_LDO_VRF18_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VRF18_OC_FUNC_EN,
+ PMIC_RG_LDO_VRF18_OC_MODE,
+ PMIC_RG_LDO_VRF18_OC_TSEL,
+ PMIC_RG_LDO_VRF18_DUMMY_LOAD,
+ PMIC_RG_LDO_VRF18_CK_SW_MODE,
+ PMIC_DA_VRF18_B_EN,
+ PMIC_DA_VRF18_B_STB,
+ PMIC_DA_VRF18_B_LP,
+ PMIC_DA_VRF18_LINE_ENHANCE,
+ PMIC_DA_VRF18_OCFB_EN,
+ PMIC_DA_VRF18_DUMMY_LOAD,
+ PMIC_RG_LDO_VRF18_HW0_OP_EN,
+ PMIC_RG_LDO_VRF18_HW1_OP_EN,
+ PMIC_RG_LDO_VRF18_HW2_OP_EN,
+ PMIC_RG_LDO_VRF18_HW3_OP_EN,
+ PMIC_RG_LDO_VRF18_SW_OP_EN,
+ PMIC_RG_LDO_VRF18_OP_EN_SET,
+ PMIC_RG_LDO_VRF18_OP_EN_CLR,
+ PMIC_RG_LDO_VRF18_HW0_OP_CFG,
+ PMIC_RG_LDO_VRF18_HW1_OP_CFG,
+ PMIC_RG_LDO_VRF18_HW2_OP_CFG,
+ PMIC_RG_LDO_VRF18_HW3_OP_CFG,
+ PMIC_RG_LDO_VRF18_OP_CFG_SET,
+ PMIC_RG_LDO_VRF18_OP_CFG_CLR,
+ PMIC_RG_LDO_VRF12_EN,
+ PMIC_RG_LDO_VRF12_LP,
+ PMIC_RG_LDO_VRF12_STBTD,
+ PMIC_RG_LDO_VRF12_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VRF12_OC_FUNC_EN,
+ PMIC_RG_LDO_VRF12_OC_MODE,
+ PMIC_RG_LDO_VRF12_OC_TSEL,
+ PMIC_RG_LDO_VRF12_DUMMY_LOAD,
+ PMIC_RG_LDO_VRF12_CK_SW_MODE,
+ PMIC_DA_VRF12_B_EN,
+ PMIC_DA_VRF12_B_STB,
+ PMIC_DA_VRF12_B_LP,
+ PMIC_DA_VRF12_LINE_ENHANCE,
+ PMIC_DA_VRF12_OCFB_EN,
+ PMIC_DA_VRF12_DUMMY_LOAD,
+ PMIC_RG_LDO_VRF12_HW0_OP_EN,
+ PMIC_RG_LDO_VRF12_HW1_OP_EN,
+ PMIC_RG_LDO_VRF12_HW2_OP_EN,
+ PMIC_RG_LDO_VRF12_HW3_OP_EN,
+ PMIC_RG_LDO_VRF12_SW_OP_EN,
+ PMIC_RG_LDO_VRF12_OP_EN_SET,
+ PMIC_RG_LDO_VRF12_OP_EN_CLR,
+ PMIC_RG_LDO_VRF12_HW0_OP_CFG,
+ PMIC_RG_LDO_VRF12_HW1_OP_CFG,
+ PMIC_RG_LDO_VRF12_HW2_OP_CFG,
+ PMIC_RG_LDO_VRF12_HW3_OP_CFG,
+ PMIC_RG_LDO_VRF12_OP_CFG_SET,
+ PMIC_RG_LDO_VRF12_OP_CFG_CLR,
+ PMIC_RG_LDO_VGP3_EN,
+ PMIC_RG_LDO_VGP3_LP,
+ PMIC_RG_LDO_VGP3_STBTD,
+ PMIC_RG_LDO_VGP3_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VGP3_OC_FUNC_EN,
+ PMIC_RG_LDO_VGP3_OC_MODE,
+ PMIC_RG_LDO_VGP3_OC_TSEL,
+ PMIC_RG_LDO_VGP3_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP3_CK_SW_MODE,
+ PMIC_DA_VGP3_B_EN,
+ PMIC_DA_VGP3_B_STB,
+ PMIC_DA_VGP3_B_LP,
+ PMIC_DA_VGP3_LINE_ENHANCE,
+ PMIC_DA_VGP3_OCFB_EN,
+ PMIC_DA_VGP3_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP3_HW0_OP_EN,
+ PMIC_RG_LDO_VGP3_HW1_OP_EN,
+ PMIC_RG_LDO_VGP3_HW2_OP_EN,
+ PMIC_RG_LDO_VGP3_HW3_OP_EN,
+ PMIC_RG_LDO_VGP3_SW_OP_EN,
+ PMIC_RG_LDO_VGP3_OP_EN_SET,
+ PMIC_RG_LDO_VGP3_OP_EN_CLR,
+ PMIC_RG_LDO_VGP3_HW0_OP_CFG,
+ PMIC_RG_LDO_VGP3_HW1_OP_CFG,
+ PMIC_RG_LDO_VGP3_HW2_OP_CFG,
+ PMIC_RG_LDO_VGP3_HW3_OP_CFG,
+ PMIC_RG_LDO_VGP3_OP_CFG_SET,
+ PMIC_RG_LDO_VGP3_OP_CFG_CLR,
+ PMIC_RG_LDO_VCN33_EN_0,
+ PMIC_RG_LDO_VCN33_LP,
+ PMIC_RG_LDO_VCN33_STBTD,
+ PMIC_RG_LDO_VCN33_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VCN33_OC_FUNC_EN,
+ PMIC_RG_LDO_VCN33_OC_MODE,
+ PMIC_RG_LDO_VCN33_OC_TSEL,
+ PMIC_RG_LDO_VCN33_DUMMY_LOAD,
+ PMIC_RG_LDO_VCN33_CK_SW_MODE,
+ PMIC_DA_VCN33_B_EN,
+ PMIC_DA_VCN33_B_STB,
+ PMIC_DA_VCN33_B_LP,
+ PMIC_DA_VCN33_LINE_ENHANCE,
+ PMIC_DA_VCN33_OCFB_EN,
+ PMIC_DA_VCN33_DUMMY_LOAD,
+ PMIC_RG_LDO_VCN33_HW0_OP_EN,
+ PMIC_RG_LDO_VCN33_HW1_OP_EN,
+ PMIC_RG_LDO_VCN33_HW2_OP_EN,
+ PMIC_RG_LDO_VCN33_HW3_OP_EN,
+ PMIC_RG_LDO_VCN33_SW_OP_EN,
+ PMIC_RG_LDO_VCN33_OP_EN_SET,
+ PMIC_RG_LDO_VCN33_OP_EN_CLR,
+ PMIC_RG_LDO_VCN33_HW0_OP_CFG,
+ PMIC_RG_LDO_VCN33_HW1_OP_CFG,
+ PMIC_RG_LDO_VCN33_HW2_OP_CFG,
+ PMIC_RG_LDO_VCN33_HW3_OP_CFG,
+ PMIC_RG_LDO_VCN33_OP_CFG_SET,
+ PMIC_RG_LDO_VCN33_OP_CFG_CLR,
+ PMIC_RG_LDO_VCN33_EN_1,
+ PMIC_RG_LDO_VCN18_EN,
+ PMIC_RG_LDO_VCN18_LP,
+ PMIC_RG_LDO_VCN18_STBTD,
+ PMIC_RG_LDO_VCN18_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VCN18_OC_FUNC_EN,
+ PMIC_RG_LDO_VCN18_OC_MODE,
+ PMIC_RG_LDO_VCN18_OC_TSEL,
+ PMIC_RG_LDO_VCN18_DUMMY_LOAD,
+ PMIC_RG_LDO_VCN18_CK_SW_MODE,
+ PMIC_DA_VCN18_B_EN,
+ PMIC_DA_VCN18_B_STB,
+ PMIC_DA_VCN18_B_LP,
+ PMIC_DA_VCN18_LINE_ENHANCE,
+ PMIC_DA_VCN18_OCFB_EN,
+ PMIC_DA_VCN18_DUMMY_LOAD,
+ PMIC_RG_LDO_VCN18_HW0_OP_EN,
+ PMIC_RG_LDO_VCN18_HW1_OP_EN,
+ PMIC_RG_LDO_VCN18_HW2_OP_EN,
+ PMIC_RG_LDO_VCN18_HW3_OP_EN,
+ PMIC_RG_LDO_VCN18_SW_OP_EN,
+ PMIC_RG_LDO_VCN18_OP_EN_SET,
+ PMIC_RG_LDO_VCN18_OP_EN_CLR,
+ PMIC_RG_LDO_VCN18_HW0_OP_CFG,
+ PMIC_RG_LDO_VCN18_HW1_OP_CFG,
+ PMIC_RG_LDO_VCN18_HW2_OP_CFG,
+ PMIC_RG_LDO_VCN18_HW3_OP_CFG,
+ PMIC_RG_LDO_VCN18_OP_CFG_SET,
+ PMIC_RG_LDO_VCN18_OP_CFG_CLR,
+ PMIC_LDO_GNR1_ANA_ID,
+ PMIC_LDO_GNR1_DIG_ID,
+ PMIC_LDO_GNR1_ANA_MINOR_REV,
+ PMIC_LDO_GNR1_ANA_MAJOR_REV,
+ PMIC_LDO_GNR1_DIG_MINOR_REV,
+ PMIC_LDO_GNR1_DIG_MAJOR_REV,
+ PMIC_LDO_GNR1_DSN_CBS,
+ PMIC_LDO_GNR1_DSN_BIX,
+ PMIC_LDO_GNR1_DSN_ESP,
+ PMIC_LDO_GNR1_DSN_FPI,
+ PMIC_RG_LDO_VA12_EN,
+ PMIC_RG_LDO_VA12_LP,
+ PMIC_RG_LDO_VA12_STBTD,
+ PMIC_RG_LDO_VA12_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VA12_OC_FUNC_EN,
+ PMIC_RG_LDO_VA12_OC_MODE,
+ PMIC_RG_LDO_VA12_OC_TSEL,
+ PMIC_RG_LDO_VA12_DUMMY_LOAD,
+ PMIC_RG_LDO_VA12_CK_SW_MODE,
+ PMIC_DA_VA12_B_EN,
+ PMIC_DA_VA12_B_STB,
+ PMIC_DA_VA12_B_LP,
+ PMIC_DA_VA12_LINE_ENHANCE,
+ PMIC_DA_VA12_OCFB_EN,
+ PMIC_DA_VA12_DUMMY_LOAD,
+ PMIC_RG_LDO_VA12_HW0_OP_EN,
+ PMIC_RG_LDO_VA12_HW1_OP_EN,
+ PMIC_RG_LDO_VA12_HW2_OP_EN,
+ PMIC_RG_LDO_VA12_HW3_OP_EN,
+ PMIC_RG_LDO_VA12_SW_OP_EN,
+ PMIC_RG_LDO_VA12_OP_EN_SET,
+ PMIC_RG_LDO_VA12_OP_EN_CLR,
+ PMIC_RG_LDO_VA12_HW0_OP_CFG,
+ PMIC_RG_LDO_VA12_HW1_OP_CFG,
+ PMIC_RG_LDO_VA12_HW2_OP_CFG,
+ PMIC_RG_LDO_VA12_HW3_OP_CFG,
+ PMIC_RG_LDO_VA12_OP_CFG_SET,
+ PMIC_RG_LDO_VA12_OP_CFG_CLR,
+ PMIC_RG_LDO_VA09_EN,
+ PMIC_RG_LDO_VA09_LP,
+ PMIC_RG_LDO_VA09_STBTD,
+ PMIC_RG_LDO_VA09_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VA09_OC_FUNC_EN,
+ PMIC_RG_LDO_VA09_OC_MODE,
+ PMIC_RG_LDO_VA09_OC_TSEL,
+ PMIC_RG_LDO_VA09_DUMMY_LOAD,
+ PMIC_RG_LDO_VA09_CK_SW_MODE,
+ PMIC_DA_VA09_B_EN,
+ PMIC_DA_VA09_B_STB,
+ PMIC_DA_VA09_B_LP,
+ PMIC_DA_VA09_LINE_ENHANCE,
+ PMIC_DA_VA09_OCFB_EN,
+ PMIC_DA_VA09_DUMMY_LOAD,
+ PMIC_RG_LDO_VA09_HW0_OP_EN,
+ PMIC_RG_LDO_VA09_HW1_OP_EN,
+ PMIC_RG_LDO_VA09_HW2_OP_EN,
+ PMIC_RG_LDO_VA09_HW3_OP_EN,
+ PMIC_RG_LDO_VA09_SW_OP_EN,
+ PMIC_RG_LDO_VA09_OP_EN_SET,
+ PMIC_RG_LDO_VA09_OP_EN_CLR,
+ PMIC_RG_LDO_VA09_HW0_OP_CFG,
+ PMIC_RG_LDO_VA09_HW1_OP_CFG,
+ PMIC_RG_LDO_VA09_HW2_OP_CFG,
+ PMIC_RG_LDO_VA09_HW3_OP_CFG,
+ PMIC_RG_LDO_VA09_OP_CFG_SET,
+ PMIC_RG_LDO_VA09_OP_CFG_CLR,
+ PMIC_RG_LDO_VAUX18_EN,
+ PMIC_RG_LDO_VAUX18_LP,
+ PMIC_RG_LDO_VAUX18_STBTD,
+ PMIC_RG_LDO_VAUX18_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VAUX18_OC_FUNC_EN,
+ PMIC_RG_LDO_VAUX18_OC_MODE,
+ PMIC_RG_LDO_VAUX18_OC_TSEL,
+ PMIC_RG_LDO_VAUX18_DUMMY_LOAD,
+ PMIC_RG_LDO_VAUX18_CK_SW_MODE,
+ PMIC_DA_VAUX18_B_EN,
+ PMIC_DA_VAUX18_B_STB,
+ PMIC_DA_VAUX18_B_LP,
+ PMIC_DA_VAUX18_LINE_ENHANCE,
+ PMIC_DA_VAUX18_OCFB_EN,
+ PMIC_DA_VAUX18_DUMMY_LOAD,
+ PMIC_RG_LDO_VAUX18_HW0_OP_EN,
+ PMIC_RG_LDO_VAUX18_HW1_OP_EN,
+ PMIC_RG_LDO_VAUX18_HW2_OP_EN,
+ PMIC_RG_LDO_VAUX18_HW3_OP_EN,
+ PMIC_RG_LDO_VAUX18_SW_OP_EN,
+ PMIC_RG_LDO_VAUX18_OP_EN_SET,
+ PMIC_RG_LDO_VAUX18_OP_EN_CLR,
+ PMIC_RG_LDO_VAUX18_HW0_OP_CFG,
+ PMIC_RG_LDO_VAUX18_HW1_OP_CFG,
+ PMIC_RG_LDO_VAUX18_HW2_OP_CFG,
+ PMIC_RG_LDO_VAUX18_HW3_OP_CFG,
+ PMIC_RG_LDO_VAUX18_OP_CFG_SET,
+ PMIC_RG_LDO_VAUX18_OP_CFG_CLR,
+ PMIC_RG_LDO_VAUD28_EN,
+ PMIC_RG_LDO_VAUD28_LP,
+ PMIC_RG_LDO_VAUD28_STBTD,
+ PMIC_RG_LDO_VAUD28_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VAUD28_OC_FUNC_EN,
+ PMIC_RG_LDO_VAUD28_OC_MODE,
+ PMIC_RG_LDO_VAUD28_OC_TSEL,
+ PMIC_RG_LDO_VAUD28_DUMMY_LOAD,
+ PMIC_RG_LDO_VAUD28_CK_SW_MODE,
+ PMIC_DA_VAUD28_B_EN,
+ PMIC_DA_VAUD28_B_STB,
+ PMIC_DA_VAUD28_B_LP,
+ PMIC_DA_VAUD28_LINE_ENHANCE,
+ PMIC_DA_VAUD28_OCFB_EN,
+ PMIC_DA_VAUD28_DUMMY_LOAD,
+ PMIC_RG_LDO_VAUD28_HW0_OP_EN,
+ PMIC_RG_LDO_VAUD28_HW1_OP_EN,
+ PMIC_RG_LDO_VAUD28_HW2_OP_EN,
+ PMIC_RG_LDO_VAUD28_HW3_OP_EN,
+ PMIC_RG_LDO_VAUD28_SW_OP_EN,
+ PMIC_RG_LDO_VAUD28_OP_EN_SET,
+ PMIC_RG_LDO_VAUD28_OP_EN_CLR,
+ PMIC_RG_LDO_VAUD28_HW0_OP_CFG,
+ PMIC_RG_LDO_VAUD28_HW1_OP_CFG,
+ PMIC_RG_LDO_VAUD28_HW2_OP_CFG,
+ PMIC_RG_LDO_VAUD28_HW3_OP_CFG,
+ PMIC_RG_LDO_VAUD28_OP_CFG_SET,
+ PMIC_RG_LDO_VAUD28_OP_CFG_CLR,
+ PMIC_RG_LDO_VIO18_EN,
+ PMIC_RG_LDO_VIO18_LP,
+ PMIC_RG_LDO_VIO18_STBTD,
+ PMIC_RG_LDO_VIO18_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VIO18_OC_FUNC_EN,
+ PMIC_RG_LDO_VIO18_OC_MODE,
+ PMIC_RG_LDO_VIO18_OC_TSEL,
+ PMIC_RG_LDO_VIO18_DUMMY_LOAD,
+ PMIC_RG_LDO_VIO18_CK_SW_MODE,
+ PMIC_DA_VIO18_B_EN,
+ PMIC_DA_VIO18_B_STB,
+ PMIC_DA_VIO18_B_LP,
+ PMIC_DA_VIO18_LINE_ENHANCE,
+ PMIC_DA_VIO18_OCFB_EN,
+ PMIC_DA_VIO18_DUMMY_LOAD,
+ PMIC_RG_LDO_VIO18_HW0_OP_EN,
+ PMIC_RG_LDO_VIO18_HW1_OP_EN,
+ PMIC_RG_LDO_VIO18_HW2_OP_EN,
+ PMIC_RG_LDO_VIO18_HW3_OP_EN,
+ PMIC_RG_LDO_VIO18_SW_OP_EN,
+ PMIC_RG_LDO_VIO18_OP_EN_SET,
+ PMIC_RG_LDO_VIO18_OP_EN_CLR,
+ PMIC_RG_LDO_VIO18_HW0_OP_CFG,
+ PMIC_RG_LDO_VIO18_HW1_OP_CFG,
+ PMIC_RG_LDO_VIO18_HW2_OP_CFG,
+ PMIC_RG_LDO_VIO18_HW3_OP_CFG,
+ PMIC_RG_LDO_VIO18_OP_CFG_SET,
+ PMIC_RG_LDO_VIO18_OP_CFG_CLR,
+ PMIC_RG_LDO_VIO33_EN,
+ PMIC_RG_LDO_VIO33_LP,
+ PMIC_RG_LDO_VIO33_STBTD,
+ PMIC_RG_LDO_VIO33_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VIO33_OC_FUNC_EN,
+ PMIC_RG_LDO_VIO33_OC_MODE,
+ PMIC_RG_LDO_VIO33_OC_TSEL,
+ PMIC_RG_LDO_VIO33_DUMMY_LOAD,
+ PMIC_RG_LDO_VIO33_CK_SW_MODE,
+ PMIC_DA_VIO33_B_EN,
+ PMIC_DA_VIO33_B_STB,
+ PMIC_DA_VIO33_B_LP,
+ PMIC_DA_VIO33_LINE_ENHANCE,
+ PMIC_DA_VIO33_OCFB_EN,
+ PMIC_DA_VIO33_DUMMY_LOAD,
+ PMIC_RG_LDO_VIO33_HW0_OP_EN,
+ PMIC_RG_LDO_VIO33_HW1_OP_EN,
+ PMIC_RG_LDO_VIO33_HW2_OP_EN,
+ PMIC_RG_LDO_VIO33_HW3_OP_EN,
+ PMIC_RG_LDO_VIO33_SW_OP_EN,
+ PMIC_RG_LDO_VIO33_OP_EN_SET,
+ PMIC_RG_LDO_VIO33_OP_EN_CLR,
+ PMIC_RG_LDO_VIO33_HW0_OP_CFG,
+ PMIC_RG_LDO_VIO33_HW1_OP_CFG,
+ PMIC_RG_LDO_VIO33_HW2_OP_CFG,
+ PMIC_RG_LDO_VIO33_HW3_OP_CFG,
+ PMIC_RG_LDO_VIO33_OP_CFG_SET,
+ PMIC_RG_LDO_VIO33_OP_CFG_CLR,
+ PMIC_LDO_GNR2_ANA_ID,
+ PMIC_LDO_GNR2_DIG_ID,
+ PMIC_LDO_GNR2_ANA_MINOR_REV,
+ PMIC_LDO_GNR2_ANA_MAJOR_REV,
+ PMIC_LDO_GNR2_DIG_MINOR_REV,
+ PMIC_LDO_GNR2_DIG_MAJOR_REV,
+ PMIC_LDO_GNR2_DSN_CBS,
+ PMIC_LDO_GNR2_DSN_BIX,
+ PMIC_LDO_GNR2_DSN_ESP,
+ PMIC_LDO_GNR2_DSN_FPI,
+ PMIC_RG_LDO_VGP1_EN,
+ PMIC_RG_LDO_VGP1_LP,
+ PMIC_RG_LDO_VGP1_STBTD,
+ PMIC_RG_LDO_VGP1_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VGP1_OC_FUNC_EN,
+ PMIC_RG_LDO_VGP1_OC_MODE,
+ PMIC_RG_LDO_VGP1_OC_TSEL,
+ PMIC_RG_LDO_VGP1_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP1_CK_SW_MODE,
+ PMIC_DA_VGP1_B_EN,
+ PMIC_DA_VGP1_B_STB,
+ PMIC_DA_VGP1_B_LP,
+ PMIC_DA_VGP1_LINE_ENHANCE,
+ PMIC_DA_VGP1_OCFB_EN,
+ PMIC_DA_VGP1_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP1_HW0_OP_EN,
+ PMIC_RG_LDO_VGP1_HW1_OP_EN,
+ PMIC_RG_LDO_VGP1_HW2_OP_EN,
+ PMIC_RG_LDO_VGP1_HW3_OP_EN,
+ PMIC_RG_LDO_VGP1_SW_OP_EN,
+ PMIC_RG_LDO_VGP1_OP_EN_SET,
+ PMIC_RG_LDO_VGP1_OP_EN_CLR,
+ PMIC_RG_LDO_VGP1_HW0_OP_CFG,
+ PMIC_RG_LDO_VGP1_HW1_OP_CFG,
+ PMIC_RG_LDO_VGP1_HW2_OP_CFG,
+ PMIC_RG_LDO_VGP1_HW3_OP_CFG,
+ PMIC_RG_LDO_VGP1_OP_CFG_SET,
+ PMIC_RG_LDO_VGP1_OP_CFG_CLR,
+ PMIC_RG_LDO_VGP2_EN,
+ PMIC_RG_LDO_VGP2_LP,
+ PMIC_RG_LDO_VGP2_STBTD,
+ PMIC_RG_LDO_VGP2_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VGP2_OC_FUNC_EN,
+ PMIC_RG_LDO_VGP2_OC_MODE,
+ PMIC_RG_LDO_VGP2_OC_TSEL,
+ PMIC_RG_LDO_VGP2_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP2_CK_SW_MODE,
+ PMIC_DA_VGP2_B_EN,
+ PMIC_DA_VGP2_B_STB,
+ PMIC_DA_VGP2_B_LP,
+ PMIC_DA_VGP2_LINE_ENHANCE,
+ PMIC_DA_VGP2_OCFB_EN,
+ PMIC_DA_VGP2_DUMMY_LOAD,
+ PMIC_RG_LDO_VGP2_HW0_OP_EN,
+ PMIC_RG_LDO_VGP2_HW1_OP_EN,
+ PMIC_RG_LDO_VGP2_HW2_OP_EN,
+ PMIC_RG_LDO_VGP2_HW3_OP_EN,
+ PMIC_RG_LDO_VGP2_SW_OP_EN,
+ PMIC_RG_LDO_VGP2_OP_EN_SET,
+ PMIC_RG_LDO_VGP2_OP_EN_CLR,
+ PMIC_RG_LDO_VGP2_HW0_OP_CFG,
+ PMIC_RG_LDO_VGP2_HW1_OP_CFG,
+ PMIC_RG_LDO_VGP2_HW2_OP_CFG,
+ PMIC_RG_LDO_VGP2_HW3_OP_CFG,
+ PMIC_RG_LDO_VGP2_OP_CFG_SET,
+ PMIC_RG_LDO_VGP2_OP_CFG_CLR,
+ PMIC_RG_LDO_VDRAM2_EN,
+ PMIC_RG_LDO_VDRAM2_LP,
+ PMIC_RG_LDO_VDRAM2_STBTD,
+ PMIC_RG_LDO_VDRAM2_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VDRAM2_OC_FUNC_EN,
+ PMIC_RG_LDO_VDRAM2_OC_MODE,
+ PMIC_RG_LDO_VDRAM2_OC_TSEL,
+ PMIC_RG_LDO_VDRAM2_DUMMY_LOAD,
+ PMIC_RG_LDO_VDRAM2_CK_SW_MODE,
+ PMIC_DA_VDRAM2_B_EN,
+ PMIC_DA_VDRAM2_B_STB,
+ PMIC_DA_VDRAM2_B_LP,
+ PMIC_DA_VDRAM2_LINE_ENHANCE,
+ PMIC_DA_VDRAM2_OCFB_EN,
+ PMIC_DA_VDRAM2_DUMMY_LOAD,
+ PMIC_RG_LDO_VDRAM2_HW0_OP_EN,
+ PMIC_RG_LDO_VDRAM2_HW1_OP_EN,
+ PMIC_RG_LDO_VDRAM2_HW2_OP_EN,
+ PMIC_RG_LDO_VDRAM2_HW3_OP_EN,
+ PMIC_RG_LDO_VDRAM2_SW_OP_EN,
+ PMIC_RG_LDO_VDRAM2_OP_EN_SET,
+ PMIC_RG_LDO_VDRAM2_OP_EN_CLR,
+ PMIC_RG_LDO_VDRAM2_HW0_OP_CFG,
+ PMIC_RG_LDO_VDRAM2_HW1_OP_CFG,
+ PMIC_RG_LDO_VDRAM2_HW2_OP_CFG,
+ PMIC_RG_LDO_VDRAM2_HW3_OP_CFG,
+ PMIC_RG_LDO_VDRAM2_OP_CFG_SET,
+ PMIC_RG_LDO_VDRAM2_OP_CFG_CLR,
+ PMIC_RG_LDO_VMCH_EN,
+ PMIC_RG_LDO_VMCH_LP,
+ PMIC_RG_LDO_VMCH_STBTD,
+ PMIC_RG_LDO_VMCH_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VMCH_OC_FUNC_EN,
+ PMIC_RG_LDO_VMCH_OC_MODE,
+ PMIC_RG_LDO_VMCH_OC_TSEL,
+ PMIC_RG_LDO_VMCH_DUMMY_LOAD,
+ PMIC_RG_LDO_VMCH_CK_SW_MODE,
+ PMIC_DA_VMCH_B_EN,
+ PMIC_DA_VMCH_B_STB,
+ PMIC_DA_VMCH_B_LP,
+ PMIC_DA_VMCH_LINE_ENHANCE,
+ PMIC_DA_VMCH_OCFB_EN,
+ PMIC_DA_VMCH_DUMMY_LOAD,
+ PMIC_RG_LDO_VMCH_HW0_OP_EN,
+ PMIC_RG_LDO_VMCH_HW1_OP_EN,
+ PMIC_RG_LDO_VMCH_HW2_OP_EN,
+ PMIC_RG_LDO_VMCH_HW3_OP_EN,
+ PMIC_RG_LDO_VMCH_SW_OP_EN,
+ PMIC_RG_LDO_VMCH_OP_EN_SET,
+ PMIC_RG_LDO_VMCH_OP_EN_CLR,
+ PMIC_RG_LDO_VMCH_HW0_OP_CFG,
+ PMIC_RG_LDO_VMCH_HW1_OP_CFG,
+ PMIC_RG_LDO_VMCH_HW2_OP_CFG,
+ PMIC_RG_LDO_VMCH_HW3_OP_CFG,
+ PMIC_RG_LDO_VMCH_OP_CFG_SET,
+ PMIC_RG_LDO_VMCH_OP_CFG_CLR,
+ PMIC_RG_LDO_VMCH_EINT_EN,
+ PMIC_RG_LDO_VEMC_EN,
+ PMIC_RG_LDO_VEMC_LP,
+ PMIC_RG_LDO_VEMC_STBTD,
+ PMIC_RG_LDO_VEMC_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VEMC_OC_FUNC_EN,
+ PMIC_RG_LDO_VEMC_OC_MODE,
+ PMIC_RG_LDO_VEMC_OC_TSEL,
+ PMIC_RG_LDO_VEMC_DUMMY_LOAD,
+ PMIC_RG_LDO_VEMC_CK_SW_MODE,
+ PMIC_DA_VEMC_B_EN,
+ PMIC_DA_VEMC_B_STB,
+ PMIC_DA_VEMC_B_LP,
+ PMIC_DA_VEMC_LINE_ENHANCE,
+ PMIC_DA_VEMC_OCFB_EN,
+ PMIC_DA_VEMC_DUMMY_LOAD,
+ PMIC_RG_LDO_VEMC_HW0_OP_EN,
+ PMIC_RG_LDO_VEMC_HW1_OP_EN,
+ PMIC_RG_LDO_VEMC_HW2_OP_EN,
+ PMIC_RG_LDO_VEMC_HW3_OP_EN,
+ PMIC_RG_LDO_VEMC_SW_OP_EN,
+ PMIC_RG_LDO_VEMC_OP_EN_SET,
+ PMIC_RG_LDO_VEMC_OP_EN_CLR,
+ PMIC_RG_LDO_VEMC_HW0_OP_CFG,
+ PMIC_RG_LDO_VEMC_HW1_OP_CFG,
+ PMIC_RG_LDO_VEMC_HW2_OP_CFG,
+ PMIC_RG_LDO_VEMC_HW3_OP_CFG,
+ PMIC_RG_LDO_VEMC_OP_CFG_SET,
+ PMIC_RG_LDO_VEMC_OP_CFG_CLR,
+ PMIC_RG_LDO_VSIM1_EN,
+ PMIC_RG_LDO_VSIM1_LP,
+ PMIC_RG_LDO_VSIM1_STBTD,
+ PMIC_RG_LDO_VSIM1_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VSIM1_OC_FUNC_EN,
+ PMIC_RG_LDO_VSIM1_OC_MODE,
+ PMIC_RG_LDO_VSIM1_OC_TSEL,
+ PMIC_RG_LDO_VSIM1_DUMMY_LOAD,
+ PMIC_RG_LDO_VSIM1_CK_SW_MODE,
+ PMIC_DA_VSIM1_B_EN,
+ PMIC_DA_VSIM1_B_STB,
+ PMIC_DA_VSIM1_B_LP,
+ PMIC_DA_VSIM1_LINE_ENHANCE,
+ PMIC_DA_VSIM1_OCFB_EN,
+ PMIC_DA_VSIM1_DUMMY_LOAD,
+ PMIC_RG_LDO_VSIM1_HW0_OP_EN,
+ PMIC_RG_LDO_VSIM1_HW1_OP_EN,
+ PMIC_RG_LDO_VSIM1_HW2_OP_EN,
+ PMIC_RG_LDO_VSIM1_HW3_OP_EN,
+ PMIC_RG_LDO_VSIM1_SW_OP_EN,
+ PMIC_RG_LDO_VSIM1_OP_EN_SET,
+ PMIC_RG_LDO_VSIM1_OP_EN_CLR,
+ PMIC_RG_LDO_VSIM1_HW0_OP_CFG,
+ PMIC_RG_LDO_VSIM1_HW1_OP_CFG,
+ PMIC_RG_LDO_VSIM1_HW2_OP_CFG,
+ PMIC_RG_LDO_VSIM1_HW3_OP_CFG,
+ PMIC_RG_LDO_VSIM1_OP_CFG_SET,
+ PMIC_RG_LDO_VSIM1_OP_CFG_CLR,
+ PMIC_RG_LDO_VSIM1_EINT_EN,
+ PMIC_LDO_GNR3_ANA_ID,
+ PMIC_LDO_GNR3_DIG_ID,
+ PMIC_LDO_GNR3_ANA_MINOR_REV,
+ PMIC_LDO_GNR3_ANA_MAJOR_REV,
+ PMIC_LDO_GNR3_DIG_MINOR_REV,
+ PMIC_LDO_GNR3_DIG_MAJOR_REV,
+ PMIC_LDO_GNR3_DSN_CBS,
+ PMIC_LDO_GNR3_DSN_BIX,
+ PMIC_LDO_GNR3_DSN_ESP,
+ PMIC_LDO_GNR3_DSN_FPI,
+ PMIC_RG_LDO_VSIM2_EN,
+ PMIC_RG_LDO_VSIM2_LP,
+ PMIC_RG_LDO_VSIM2_STBTD,
+ PMIC_RG_LDO_VSIM2_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VSIM2_OC_FUNC_EN,
+ PMIC_RG_LDO_VSIM2_OC_MODE,
+ PMIC_RG_LDO_VSIM2_OC_TSEL,
+ PMIC_RG_LDO_VSIM2_DUMMY_LOAD,
+ PMIC_RG_LDO_VSIM2_CK_SW_MODE,
+ PMIC_DA_VSIM2_B_EN,
+ PMIC_DA_VSIM2_B_STB,
+ PMIC_DA_VSIM2_B_LP,
+ PMIC_DA_VSIM2_LINE_ENHANCE,
+ PMIC_DA_VSIM2_OCFB_EN,
+ PMIC_DA_VSIM2_DUMMY_LOAD,
+ PMIC_RG_LDO_VSIM2_HW0_OP_EN,
+ PMIC_RG_LDO_VSIM2_HW1_OP_EN,
+ PMIC_RG_LDO_VSIM2_HW2_OP_EN,
+ PMIC_RG_LDO_VSIM2_HW3_OP_EN,
+ PMIC_RG_LDO_VSIM2_SW_OP_EN,
+ PMIC_RG_LDO_VSIM2_OP_EN_SET,
+ PMIC_RG_LDO_VSIM2_OP_EN_CLR,
+ PMIC_RG_LDO_VSIM2_HW0_OP_CFG,
+ PMIC_RG_LDO_VSIM2_HW1_OP_CFG,
+ PMIC_RG_LDO_VSIM2_HW2_OP_CFG,
+ PMIC_RG_LDO_VSIM2_HW3_OP_CFG,
+ PMIC_RG_LDO_VSIM2_OP_CFG_SET,
+ PMIC_RG_LDO_VSIM2_OP_CFG_CLR,
+ PMIC_RG_LDO_VSIM2_EINT_EN,
+ PMIC_RG_LDO_VUSB_EN,
+ PMIC_RG_LDO_VUSB_LP,
+ PMIC_RG_LDO_VUSB_STBTD,
+ PMIC_RG_LDO_VUSB_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VUSB_OC_FUNC_EN,
+ PMIC_RG_LDO_VUSB_OC_MODE,
+ PMIC_RG_LDO_VUSB_OC_TSEL,
+ PMIC_RG_LDO_VUSB_DUMMY_LOAD,
+ PMIC_RG_LDO_VUSB_CK_SW_MODE,
+ PMIC_DA_VUSB_B_EN,
+ PMIC_DA_VUSB_B_STB,
+ PMIC_DA_VUSB_B_LP,
+ PMIC_DA_VUSB_LINE_ENHANCE,
+ PMIC_DA_VUSB_OCFB_EN,
+ PMIC_DA_VUSB_DUMMY_LOAD,
+ PMIC_RG_LDO_VUSB_HW0_OP_EN,
+ PMIC_RG_LDO_VUSB_HW1_OP_EN,
+ PMIC_RG_LDO_VUSB_HW2_OP_EN,
+ PMIC_RG_LDO_VUSB_HW3_OP_EN,
+ PMIC_RG_LDO_VUSB_SW_OP_EN,
+ PMIC_RG_LDO_VUSB_OP_EN_SET,
+ PMIC_RG_LDO_VUSB_OP_EN_CLR,
+ PMIC_RG_LDO_VUSB_HW0_OP_CFG,
+ PMIC_RG_LDO_VUSB_HW1_OP_CFG,
+ PMIC_RG_LDO_VUSB_HW2_OP_CFG,
+ PMIC_RG_LDO_VUSB_HW3_OP_CFG,
+ PMIC_RG_LDO_VUSB_OP_CFG_SET,
+ PMIC_RG_LDO_VUSB_OP_CFG_CLR,
+ PMIC_RG_LDO_VXO22_EN,
+ PMIC_RG_LDO_VXO22_LP,
+ PMIC_RG_LDO_VXO22_STBTD,
+ PMIC_RG_LDO_VXO22_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VXO22_OC_FUNC_EN,
+ PMIC_RG_LDO_VXO22_OC_MODE,
+ PMIC_RG_LDO_VXO22_OC_TSEL,
+ PMIC_RG_LDO_VXO22_DUMMY_LOAD,
+ PMIC_RG_LDO_VXO22_CK_SW_MODE,
+ PMIC_DA_VXO22_B_EN,
+ PMIC_DA_VXO22_B_STB,
+ PMIC_DA_VXO22_B_LP,
+ PMIC_DA_VXO22_LINE_ENHANCE,
+ PMIC_DA_VXO22_OCFB_EN,
+ PMIC_DA_VXO22_DUMMY_LOAD,
+ PMIC_RG_LDO_VXO22_HW0_OP_EN,
+ PMIC_RG_LDO_VXO22_HW1_OP_EN,
+ PMIC_RG_LDO_VXO22_HW2_OP_EN,
+ PMIC_RG_LDO_VXO22_HW3_OP_EN,
+ PMIC_RG_LDO_VXO22_SW_OP_EN,
+ PMIC_RG_LDO_VXO22_OP_EN_SET,
+ PMIC_RG_LDO_VXO22_OP_EN_CLR,
+ PMIC_RG_LDO_VXO22_HW0_OP_CFG,
+ PMIC_RG_LDO_VXO22_HW1_OP_CFG,
+ PMIC_RG_LDO_VXO22_HW2_OP_CFG,
+ PMIC_RG_LDO_VXO22_HW3_OP_CFG,
+ PMIC_RG_LDO_VXO22_OP_CFG_SET,
+ PMIC_RG_LDO_VXO22_OP_CFG_CLR,
+ PMIC_RG_LDO_VRFCK_EN,
+ PMIC_RG_LDO_VRFCK_LP,
+ PMIC_RG_LDO_VRFCK_STBTD,
+ PMIC_RG_LDO_VRFCK_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VRFCK_OC_FUNC_EN,
+ PMIC_RG_LDO_VRFCK_OC_MODE,
+ PMIC_RG_LDO_VRFCK_OC_TSEL,
+ PMIC_RG_LDO_VRFCK_DUMMY_LOAD,
+ PMIC_RG_LDO_VRFCK_CK_SW_MODE,
+ PMIC_DA_VRFCK_B_EN,
+ PMIC_DA_VRFCK_B_STB,
+ PMIC_DA_VRFCK_B_LP,
+ PMIC_DA_VRFCK_LINE_ENHANCE,
+ PMIC_DA_VRFCK_OCFB_EN,
+ PMIC_DA_VRFCK_DUMMY_LOAD,
+ PMIC_RG_LDO_VRFCK_HW0_OP_EN,
+ PMIC_RG_LDO_VRFCK_HW1_OP_EN,
+ PMIC_RG_LDO_VRFCK_HW2_OP_EN,
+ PMIC_RG_LDO_VRFCK_HW3_OP_EN,
+ PMIC_RG_LDO_VRFCK_SW_OP_EN,
+ PMIC_RG_LDO_VRFCK_OP_EN_SET,
+ PMIC_RG_LDO_VRFCK_OP_EN_CLR,
+ PMIC_RG_LDO_VRFCK_HW0_OP_CFG,
+ PMIC_RG_LDO_VRFCK_HW1_OP_CFG,
+ PMIC_RG_LDO_VRFCK_HW2_OP_CFG,
+ PMIC_RG_LDO_VRFCK_HW3_OP_CFG,
+ PMIC_RG_LDO_VRFCK_OP_CFG_SET,
+ PMIC_RG_LDO_VRFCK_OP_CFG_CLR,
+ PMIC_RG_LDO_VBBCK_EN,
+ PMIC_RG_LDO_VBBCK_LP,
+ PMIC_RG_LDO_VBBCK_STBTD,
+ PMIC_RG_LDO_VBBCK_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VBBCK_OC_FUNC_EN,
+ PMIC_RG_LDO_VBBCK_OC_MODE,
+ PMIC_RG_LDO_VBBCK_OC_TSEL,
+ PMIC_RG_LDO_VBBCK_DUMMY_LOAD,
+ PMIC_RG_LDO_VBBCK_CK_SW_MODE,
+ PMIC_DA_VBBCK_B_EN,
+ PMIC_DA_VBBCK_B_STB,
+ PMIC_DA_VBBCK_B_LP,
+ PMIC_DA_VBBCK_LINE_ENHANCE,
+ PMIC_DA_VBBCK_OCFB_EN,
+ PMIC_DA_VBBCK_DUMMY_LOAD,
+ PMIC_RG_LDO_VBBCK_HW0_OP_EN,
+ PMIC_RG_LDO_VBBCK_HW1_OP_EN,
+ PMIC_RG_LDO_VBBCK_HW2_OP_EN,
+ PMIC_RG_LDO_VBBCK_HW3_OP_EN,
+ PMIC_RG_LDO_VBBCK_SW_OP_EN,
+ PMIC_RG_LDO_VBBCK_OP_EN_SET,
+ PMIC_RG_LDO_VBBCK_OP_EN_CLR,
+ PMIC_RG_LDO_VBBCK_HW0_OP_CFG,
+ PMIC_RG_LDO_VBBCK_HW1_OP_CFG,
+ PMIC_RG_LDO_VBBCK_HW2_OP_CFG,
+ PMIC_RG_LDO_VBBCK_HW3_OP_CFG,
+ PMIC_RG_LDO_VBBCK_OP_CFG_SET,
+ PMIC_RG_LDO_VBBCK_OP_CFG_CLR,
+ PMIC_LDO_VSRAM0_ANA_ID,
+ PMIC_LDO_VSRAM0_DIG_ID,
+ PMIC_LDO_VSRAM0_ANA_MINOR_REV,
+ PMIC_LDO_VSRAM0_ANA_MAJOR_REV,
+ PMIC_LDO_VSRAM0_DIG_MINOR_REV,
+ PMIC_LDO_VSRAM0_DIG_MAJOR_REV,
+ PMIC_LDO_VSRAM0_DSN_CBS,
+ PMIC_LDO_VSRAM0_DSN_BIX,
+ PMIC_LDO_VSRAM0_DSN_ESP,
+ PMIC_LDO_VSRAM0_DSN_FPI,
+ PMIC_RG_LDO_VSRAM_PROC_EN,
+ PMIC_RG_LDO_VSRAM_PROC_LP,
+ PMIC_RG_LDO_VSRAM_PROC_STBTD,
+ PMIC_RG_LDO_VSRAM_PROC_LINE_ENHANCE_EN,
+ PMIC_RG_LDO_VSRAM_PROC_OC_FUNC_EN,
+ PMIC_RG_LDO_VSRAM_PROC_OC_MODE,
+ PMIC_RG_LDO_VSRAM_PROC_OC_TSEL,
+ PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD,
+ PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE,
+ PMIC_DA_VSRAM_PROC_B_EN,
+ PMIC_DA_VSRAM_PROC_B_STB,
+ PMIC_DA_VSRAM_PROC_B_LP,
+ PMIC_DA_VSRAM_PROC_LINE_ENHANCE,
+ PMIC_DA_VSRAM_PROC_OCFB_EN,
+ PMIC_DA_VSRAM_PROC_DUMMY_LOAD,
+ PMIC_DA_VSRAM_PROC_VSLEEP_SEL,
+ PMIC_DA_VSRAM_PROC_R2R_PDN,
+ PMIC_DA_VSRAM_PROC_TRACK_NDIS_EN,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP,
+ PMIC_LDO_VSRAM_PROC_WDTDBG_VOSEL,
+ PMIC_DA_VSRAM_PROC_VOSEL_GRAY,
+ PMIC_DA_VSRAM_PROC_VOSEL,
+ PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE,
+ PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN,
+ PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE,
+ PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN,
+ PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD,
+ PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL,
+ PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE,
+ PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN,
+ PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN,
+ PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN,
+ PMIC_RG_LDO_VSRAM_PROC_HW3_OP_EN,
+ PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN,
+ PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET,
+ PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR,
+ PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG,
+ PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG,
+ PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG,
+ PMIC_RG_LDO_VSRAM_PROC_HW3_OP_CFG,
+ PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET,
+ PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR,
+ PMIC_RG_LDO_VSRAM_PROC_TRACK_EN,
+ PMIC_RG_LDO_VSRAM_PROC_TRACK_MODE,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_DELTA,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_OFFSET,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_LB,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_HB,
+ PMIC_LDO_VSRAM0_ELR_LEN,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL,
+ PMIC_RG_LDO_VSRAM_PROC_VOSEL_LIMIT_SEL,
+ PMIC_LDO_ANA0_ANA_ID,
+ PMIC_LDO_ANA0_DIG_ID,
+ PMIC_LDO_ANA0_ANA_MINOR_REV,
+ PMIC_LDO_ANA0_ANA_MAJOR_REV,
+ PMIC_LDO_ANA0_DIG_MINOR_REV,
+ PMIC_LDO_ANA0_DIG_MAJOR_REV,
+ PMIC_LDO_ANA0_DSN_CBS,
+ PMIC_LDO_ANA0_DSN_BIX,
+ PMIC_LDO_ANA0_DSN_ESP,
+ PMIC_LDO_ANA0_DSN_FPI,
+ PMIC_RG_VFE28_VOCAL,
+ PMIC_RG_VFE28_VOSEL,
+ PMIC_RG_VFE28_NDIS_EN,
+ PMIC_RG_VFE28_STB_SEL,
+ PMIC_RG_VFE28_RSV_1,
+ PMIC_RG_VFE28_OC_LP_EN,
+ PMIC_RG_VFE28_MEASURE_FT_EN,
+ PMIC_RGS_VFE28_OC_STATUS,
+ PMIC_RG_VFE28_OC_LEVEL,
+ PMIC_RG_VFE28_OC_TRIM,
+ PMIC_RG_VAUX18_VOCAL,
+ PMIC_RG_VAUX18_VOSEL,
+ PMIC_RG_VAUX18_NDIS_EN,
+ PMIC_RG_VAUX18_RSV_1,
+ PMIC_RG_VAUX18_OC_LP_EN,
+ PMIC_RG_VAUX18_MEASURE_FT_EN,
+ PMIC_RGS_VAUX18_OC_STATUS,
+ PMIC_RG_VAUX18_OC_TRIM,
+ PMIC_RG_VAUD28_VOCAL,
+ PMIC_RG_VAUD28_VOSEL,
+ PMIC_RG_VAUD28_NDIS_EN,
+ PMIC_RG_VAUD28_RSV_1,
+ PMIC_RG_VAUD28_OC_LP_EN,
+ PMIC_RG_VAUD28_MEASURE_FT_EN,
+ PMIC_RGS_VAUD28_OC_STATUS,
+ PMIC_RG_VAUD28_OC_TRIM,
+ PMIC_RG_VUSB_VOCAL,
+ PMIC_RG_VUSB_VOSEL,
+ PMIC_RG_VUSB_NDIS_EN,
+ PMIC_RG_VUSB_RSV_1,
+ PMIC_RG_VUSB_OC_LP_EN,
+ PMIC_RG_VUSB_MEASURE_FT_EN,
+ PMIC_RGS_VUSB_OC_STATUS,
+ PMIC_RG_VUSB_OC_TRIM,
+ PMIC_RG_VCN33_VOCAL,
+ PMIC_RG_VCN33_VOSEL,
+ PMIC_RG_VCN33_NDIS_EN,
+ PMIC_RG_VCN33_STB_SEL,
+ PMIC_RG_VCN33_RSV_1,
+ PMIC_RG_VCN33_OC_LP_EN,
+ PMIC_RG_VCN33_MEASURE_FT_EN,
+ PMIC_RGS_VCN33_OC_STATUS,
+ PMIC_RG_VCN33_OC_LEVEL,
+ PMIC_RG_VCN33_OC_TRIM,
+ PMIC_RG_VEMC_VOCAL,
+ PMIC_RG_VEMC_VOSEL,
+ PMIC_RG_VEMC_NDIS_EN,
+ PMIC_RG_VEMC_RSV_1,
+ PMIC_RG_VEMC_OC_LP_EN,
+ PMIC_RG_VEMC_MEASURE_FT_EN,
+ PMIC_RGS_VEMC_OC_STATUS,
+ PMIC_RG_VEMC_OC_TRIM,
+ PMIC_RG_VSIM1_VOCAL,
+ PMIC_RG_VSIM1_VOSEL,
+ PMIC_RG_VSIM1_NDIS_EN,
+ PMIC_RG_VSIM1_STB_SEL,
+ PMIC_RG_VSIM1_RSV_1,
+ PMIC_RG_VSIM1_OC_LP_EN,
+ PMIC_RG_VSIM1_MEASURE_FT_EN,
+ PMIC_RGS_VSIM1_OC_STATUS,
+ PMIC_RG_VSIM1_OC_LEVEL,
+ PMIC_RG_VSIM1_OC_TRIM,
+ PMIC_RG_VSIM2_VOCAL,
+ PMIC_RG_VSIM2_VOSEL,
+ PMIC_RG_VSIM2_NDIS_EN,
+ PMIC_RG_VSIM2_STB_SEL,
+ PMIC_RG_VSIM2_RSV_1,
+ PMIC_RG_VSIM2_OC_LP_EN,
+ PMIC_RG_VSIM2_MEASURE_FT_EN,
+ PMIC_RGS_VSIM2_OC_STATUS,
+ PMIC_RG_VSIM2_OC_LEVEL,
+ PMIC_RG_VSIM2_OC_TRIM,
+ PMIC_RG_VMCH_VOCAL,
+ PMIC_RG_VMCH_VOSEL,
+ PMIC_RG_VMCH_NDIS_EN,
+ PMIC_RG_VMCH_STB_SEL,
+ PMIC_RG_VMCH_RSV_1,
+ PMIC_RG_VMCH_OC_LP_EN,
+ PMIC_RG_VMCH_MEASURE_FT_EN,
+ PMIC_RGS_VMCH_OC_STATUS,
+ PMIC_RG_VMCH_OC_TRIM,
+ PMIC_RG_VIO33_VOCAL,
+ PMIC_RG_VIO33_VOSEL,
+ PMIC_RG_VIO33_NDIS_EN,
+ PMIC_RG_VIO33_RSV_1,
+ PMIC_RG_VIO33_OC_LP_EN,
+ PMIC_RG_VIO33_MEASURE_FT_EN,
+ PMIC_RGS_VIO33_OC_STATUS,
+ PMIC_RG_VIO33_OC_TRIM,
+ PMIC_RG_VGP1_VOCAL,
+ PMIC_RG_VGP1_VOSEL,
+ PMIC_RG_VGP1_NDIS_EN,
+ PMIC_RG_VGP1_STB_SEL,
+ PMIC_RG_VGP1_RSV_1,
+ PMIC_RG_VGP1_OC_LP_EN,
+ PMIC_RG_VGP1_MEASURE_FT_EN,
+ PMIC_RGS_VGP1_OC_STATUS,
+ PMIC_RG_VGP1_OC_LEVEL,
+ PMIC_RG_VGP1_OC_TRIM,
+ PMIC_RG_VGP2_VOCAL,
+ PMIC_RG_VGP2_VOSEL,
+ PMIC_RG_VGP2_NDIS_EN,
+ PMIC_RG_VGP2_STB_SEL,
+ PMIC_RG_VGP2_RSV_1,
+ PMIC_RG_VGP2_OC_LP_EN,
+ PMIC_RG_VGP2_MEASURE_FT_EN,
+ PMIC_RGS_VGP2_OC_STATUS,
+ PMIC_RG_VGP2_OC_LEVEL,
+ PMIC_RG_VGP2_OC_TRIM,
+ PMIC_RG_ADLDO_RSV,
+ PMIC_LDO_ANA0_ELR_LEN,
+ PMIC_RG_VFE28_VO_F_TRIM,
+ PMIC_RG_VFE28_VOTRIM,
+ PMIC_RG_VAUX18_VO_F_TRIM,
+ PMIC_RG_VAUX18_VOTRIM,
+ PMIC_RG_VAUX18_OC_LEVEL,
+ PMIC_RG_VAUX18_STB_SEL,
+ PMIC_RG_VAUD28_VO_F_TRIM,
+ PMIC_RG_VAUD28_VOTRIM,
+ PMIC_RG_VAUD28_OC_LEVEL,
+ PMIC_RG_VAUD28_STB_SEL,
+ PMIC_RG_VUSB_VO_F_TRIM,
+ PMIC_RG_VUSB_VOTRIM,
+ PMIC_RG_VUSB_OC_LEVEL,
+ PMIC_RG_VUSB_STB_SEL,
+ PMIC_RG_VCN33_VO_F_TRIM,
+ PMIC_RG_VCN33_VOTRIM,
+ PMIC_RG_VEMC_VO_F_TRIM,
+ PMIC_RG_VEMC_VOTRIM,
+ PMIC_RG_VEMC_OC_LEVEL,
+ PMIC_RG_VEMC_STB_SEL,
+ PMIC_RG_VSIM1_VO_F_TRIM,
+ PMIC_RG_VSIM1_VOTRIM,
+ PMIC_RG_VSIM2_VO_F_TRIM,
+ PMIC_RG_VSIM2_VOTRIM,
+ PMIC_RG_VMCH_VO_F_TRIM,
+ PMIC_RG_VMCH_VOTRIM,
+ PMIC_RG_VMCH_OC_LEVEL,
+ PMIC_RG_VIO33_VO_F_TRIM,
+ PMIC_RG_VIO33_VOTRIM,
+ PMIC_RG_VIO33_OC_LEVEL,
+ PMIC_RG_VIO33_STB_SEL,
+ PMIC_RG_VGP1_VO_F_TRIM,
+ PMIC_RG_VGP1_VOTRIM,
+ PMIC_RG_VGP2_VO_F_TRIM,
+ PMIC_RG_VGP2_VOTRIM,
+ PMIC_RG_VRTC28_BIAS_SEL,
+ PMIC_RG_VRTC28_NDIS_EN,
+ PMIC_LDO_ANA1_ANA_ID,
+ PMIC_LDO_ANA1_DIG_ID,
+ PMIC_LDO_ANA1_ANA_MINOR_REV,
+ PMIC_LDO_ANA1_ANA_MAJOR_REV,
+ PMIC_LDO_ANA1_DIG_MINOR_REV,
+ PMIC_LDO_ANA1_DIG_MAJOR_REV,
+ PMIC_LDO_ANA1_DSN_CBS,
+ PMIC_LDO_ANA1_DSN_BIX,
+ PMIC_LDO_ANA1_DSN_ESP,
+ PMIC_LDO_ANA1_DSN_FPI,
+ PMIC_RG_VRF18_VOCAL,
+ PMIC_RG_VRF18_VOSEL,
+ PMIC_RG_VRF18_NDIS_EN,
+ PMIC_RG_VRF18_STB_SEL,
+ PMIC_RG_VRF18_RSV_1,
+ PMIC_RG_VRF18_OC_LP_EN,
+ PMIC_RG_VRF18_MEASURE_FT_EN,
+ PMIC_RGS_VRF18_OC_STATUS,
+ PMIC_RG_VRF18_OC_LEVEL,
+ PMIC_RG_VRF18_OC_TRIM,
+ PMIC_RG_VGP3_VOCAL,
+ PMIC_RG_VGP3_VOSEL,
+ PMIC_RG_VGP3_NDIS_EN,
+ PMIC_RG_VGP3_STB_SEL,
+ PMIC_RG_VGP3_RSV_1,
+ PMIC_RG_VGP3_OC_LP_EN,
+ PMIC_RG_VGP3_MEASURE_FT_EN,
+ PMIC_RGS_VGP3_OC_STATUS,
+ PMIC_RG_VGP3_OC_LEVEL,
+ PMIC_RG_VGP3_OC_TRIM,
+ PMIC_RG_VCN18_VOCAL,
+ PMIC_RG_VCN18_VOSEL,
+ PMIC_RG_VCN18_NDIS_EN,
+ PMIC_RG_VCN18_STB_SEL,
+ PMIC_RG_VCN18_RSV_1,
+ PMIC_RG_VCN18_OC_LP_EN,
+ PMIC_RG_VCN18_MEASURE_FT_EN,
+ PMIC_RGS_VCN18_OC_STATUS,
+ PMIC_RG_VCN18_OC_LEVEL,
+ PMIC_RG_VCN18_OC_TRIM,
+ PMIC_RG_VIO18_VOCAL,
+ PMIC_RG_VIO18_VOSEL,
+ PMIC_RG_VIO18_NDIS_EN,
+ PMIC_RG_VIO18_RSV_1,
+ PMIC_RG_VIO18_OC_LP_EN,
+ PMIC_RG_VIO18_MEASURE_FT_EN,
+ PMIC_RGS_VIO18_OC_STATUS,
+ PMIC_RG_SLDO20_RSV,
+ PMIC_RG_VRF12_VOCAL,
+ PMIC_RG_VRF12_VOSEL,
+ PMIC_RG_VRF12_NDIS_EN,
+ PMIC_RG_VRF12_STB_SEL,
+ PMIC_RG_VRF12_RSV_1,
+ PMIC_RG_VRF12_OC_LP_EN,
+ PMIC_RG_VRF12_MEASURE_FT_EN,
+ PMIC_RGS_VRF12_OC_STATUS,
+ PMIC_RG_VRF12_OC_LEVEL,
+ PMIC_RG_VRF12_OC_TRIM,
+ PMIC_RG_VA09_VOCAL,
+ PMIC_RG_VA09_VOSEL,
+ PMIC_RG_VA09_NDIS_EN,
+ PMIC_RG_VA09_RSV_1,
+ PMIC_RG_VA09_OC_LP_EN,
+ PMIC_RG_VA09_MEASURE_FT_EN,
+ PMIC_RGS_VA09_OC_STATUS,
+ PMIC_RG_VA09_OC_TRIM,
+ PMIC_RG_VA12_VOCAL,
+ PMIC_RG_VA12_VOSEL,
+ PMIC_RG_VA12_NDIS_EN,
+ PMIC_RG_VA12_RSV_1,
+ PMIC_RG_VA12_OC_LP_EN,
+ PMIC_RG_VA12_MEASURE_FT_EN,
+ PMIC_RGS_VA12_OC_STATUS,
+ PMIC_RG_VA12_OC_TRIM,
+ PMIC_RG_VSRAM_PROC_NDIS_EN,
+ PMIC_RG_VSRAM_PROC_NDIS_PLCUR,
+ PMIC_RG_VSRAM_PROC_OC_LP_EN,
+ PMIC_RG_VSRAM_PROC_MEASURE_FT_EN,
+ PMIC_RGS_VSRAM_PROC_OC_STATUS,
+ PMIC_RG_VDRAM2_NDIS_EN,
+ PMIC_RG_VDRAM2_RSV_1,
+ PMIC_RG_VDRAM2_OC_LP_EN,
+ PMIC_RG_VDRAM2_MEASURE_FT_EN,
+ PMIC_RGS_VDRAM2_OC_STATUS,
+ PMIC_RG_VDRAM2_OC_TRIM,
+ PMIC_RG_SLDO14_RSV,
+ PMIC_LDO_ANA1_ELR_LEN,
+ PMIC_RG_VRF18_VO_F_TRIM,
+ PMIC_RG_VRF18_VOTRIM,
+ PMIC_RG_VGP3_VO_F_TRIM,
+ PMIC_RG_VGP3_VOTRIM,
+ PMIC_RG_VCN18_VO_F_TRIM,
+ PMIC_RG_VCN18_VOTRIM,
+ PMIC_RG_VIO18_VO_F_TRIM,
+ PMIC_RG_VIO18_VOTRIM,
+ PMIC_RG_VIO18_OC_LEVEL,
+ PMIC_RG_VIO18_OC_TRIM,
+ PMIC_RG_VIO18_STB_SEL,
+ PMIC_RG_VRF12_VO_F_TRIM,
+ PMIC_RG_VRF12_VOTRIM,
+ PMIC_RG_VA09_VO_F_TRIM,
+ PMIC_RG_VA09_VOTRIM,
+ PMIC_RG_VA09_OC_LEVEL,
+ PMIC_RG_VA09_STB_SEL,
+ PMIC_RG_VA12_VO_F_TRIM,
+ PMIC_RG_VA12_VOTRIM,
+ PMIC_RG_VA12_OC_LEVEL,
+ PMIC_RG_VA12_STB_SEL,
+ PMIC_RG_VSRAM_PROC_OC_LEVEL,
+ PMIC_RG_VSRAM_PROC_RSV_H,
+ PMIC_RG_VSRAM_PROC_RSV_L,
+ PMIC_RG_VDRAM2_VO_F_TRIM,
+ PMIC_RG_VDRAM2_VOTRIM,
+ PMIC_RG_VDRAM2_OC_LEVEL,
+ PMIC_RG_VDRAM2_STB_SEL,
+ PMIC_LDO_ANA2_ANA_ID,
+ PMIC_LDO_ANA2_DIG_ID,
+ PMIC_LDO_ANA2_ANA_MINOR_REV,
+ PMIC_LDO_ANA2_ANA_MAJOR_REV,
+ PMIC_LDO_ANA2_DIG_MINOR_REV,
+ PMIC_LDO_ANA2_DIG_MAJOR_REV,
+ PMIC_LDO_ANA2_DSN_CBS,
+ PMIC_LDO_ANA2_DSN_BIX,
+ PMIC_LDO_ANA2_DSN_ESP,
+ PMIC_LDO_ANA2_DSN_FPI,
+ PMIC_RG_VXO22_VOCAL,
+ PMIC_RG_VXO22_VOSEL,
+ PMIC_RG_VXO22_RSV_1,
+ PMIC_RG_VXO22_OC_LP_EN,
+ PMIC_RG_VXO22_ULP_IQ_CLAMP_EN,
+ PMIC_RG_VXO22_ULP_BIASX2_EN,
+ PMIC_RG_VXO22_MEASURE_FT_EN,
+ PMIC_RGS_VXO22_OC_STATUS,
+ PMIC_RG_VRFCK_VOCAL,
+ PMIC_RG_VRFCK_VOSEL,
+ PMIC_RG_VRFCK_RSV_1,
+ PMIC_RG_VRFCK_OC_LP_EN,
+ PMIC_RG_VRFCK_ULP_IQ_CLAMP_EN,
+ PMIC_RG_VRFCK_ULP_BIASX2_EN,
+ PMIC_RG_VRFCK_MEASURE_FT_EN,
+ PMIC_RGS_VRFCK_OC_STATUS,
+ PMIC_RG_VRFCK_CAS_CSEL,
+ PMIC_RG_VRFCK_CAS_ISEL,
+ PMIC_RG_VRFCK_CAS_RSEL,
+ PMIC_RG_VRFCK_CAS_STB,
+ PMIC_RG_VRFCK_1_VOCAL,
+ PMIC_RG_VRFCK_1_VOSEL,
+ PMIC_RG_VRFCK_1_RSV_1,
+ PMIC_RG_VRFCK_1_OC_LP_EN,
+ PMIC_RG_VRFCK_1_ULP_IQ_CLAMP_EN,
+ PMIC_RG_VRFCK_1_ULP_BIASX2_EN,
+ PMIC_RG_VRFCK_1_MEASURE_FT_EN,
+ PMIC_RGS_VRFCK_1_OC_STATUS,
+ PMIC_RG_VBBCK_VOCAL,
+ PMIC_RG_VBBCK_VOSEL,
+ PMIC_RG_VBBCK_RSV_1,
+ PMIC_RG_VBBCK_OC_LP_EN,
+ PMIC_RG_VBBCK_ULP_IQ_CLAMP_EN,
+ PMIC_RG_VBBCK_ULP_BIASX2_EN,
+ PMIC_RG_VBBCK_MEASURE_FT_EN,
+ PMIC_RGS_VBBCK_OC_STATUS,
+ PMIC_LDO_ANA2_ELR_LEN,
+ PMIC_RG_VXO22_VOTRIM,
+ PMIC_RG_VXO22_NDIS_EN,
+ PMIC_RG_VRFCK_VOTRIM,
+ PMIC_RG_VRFCK_NDIS_EN,
+ PMIC_RG_VRFCK_HV_EN,
+ PMIC_RG_VRFCK_CAS_EN,
+ PMIC_RG_VRFCK_1_VOTRIM,
+ PMIC_RG_VRFCK_1_NDIS_EN,
+ PMIC_RG_VBBCK_VOTRIM,
+ PMIC_RG_VBBCK_NDIS_EN,
+ PMIC_RG_VBBCK_HV_EN,
+ PMIC_AUD_TOP_ANA_ID,
+ PMIC_AUD_TOP_DIG_ID,
+ PMIC_AUD_TOP_ANA_MINOR_REV,
+ PMIC_AUD_TOP_ANA_MAJOR_REV,
+ PMIC_AUD_TOP_DIG_MINOR_REV,
+ PMIC_AUD_TOP_DIG_MAJOR_REV,
+ PMIC_AUD_TOP_CBS,
+ PMIC_AUD_TOP_BIX,
+ PMIC_AUD_TOP_ESP,
+ PMIC_AUD_TOP_FPI,
+ PMIC_AUD_TOP_CLK_OFFSET,
+ PMIC_AUD_TOP_RST_OFFSET,
+ PMIC_AUD_TOP_INT_OFFSET,
+ PMIC_AUD_TOP_INT_LEN,
+ PMIC_RG_AUD_CK_PDN,
+ PMIC_RG_AUDIF_CK_PDN,
+ PMIC_RG_AUD_INTRP_CK_PDN,
+ PMIC_RG_ZCD13M_CK_PDN,
+ PMIC_RG_AUDNCP_CK_PDN,
+ PMIC_RG_AUD_TOP_CKPDN_CON0_SET,
+ PMIC_RG_AUD_TOP_CKPDN_CON0_CLR,
+ PMIC_RG_AUD_CK_CKSEL,
+ PMIC_RG_AUDIF_CK_CKSEL,
+ PMIC_RG_AUD_TOP_CKSEL_CON0_SET,
+ PMIC_RG_AUD_TOP_CKSEL_CON0_CLR,
+ PMIC_RG_AUD26M_CK_TST_DIS,
+ PMIC_RG_AUD_CK_TSTSEL,
+ PMIC_RG_AUDIF_CK_TSTSEL,
+ PMIC_RG_AUD26M_CK_TSTSEL,
+ PMIC_RG_AUD_INTRP_CK_PDN_HWEN,
+ PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET,
+ PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR,
+ PMIC_RG_AUDIO_RST,
+ PMIC_RG_ZCD_RST,
+ PMIC_RG_AUDNCP_RST,
+ PMIC_RG_AUD_TOP_RST_CON0_SET,
+ PMIC_RG_AUD_TOP_RST_CON0_CLR,
+ PMIC_BANK_AUDIO_SWRST,
+ PMIC_BANK_AUDZCD_SWRST,
+ PMIC_RG_INT_EN_AUDIO,
+ PMIC_RG_AUD_INT_CON0_SET,
+ PMIC_RG_AUD_INT_CON0_CLR,
+ PMIC_RG_INT_MASK_AUDIO,
+ PMIC_RG_AUD_INT_MASK_CON0_SET,
+ PMIC_RG_AUD_INT_MASK_CON0_CLR,
+ PMIC_RG_INT_STATUS_AUDIO,
+ PMIC_RG_INT_RAW_STATUS_AUDIO,
+ PMIC_RG_AUD_TOP_INT_POLARITY,
+ PMIC_RG_DIVCKS_CHG,
+ PMIC_RG_DIVCKS_ON,
+ PMIC_RG_DIVCKS_PRG,
+ PMIC_RG_DIVCKS_PWD_NCP,
+ PMIC_RG_DIVCKS_PWD_NCP_ST_SEL,
+ PMIC_RG_AUD_TOP_MON_SEL,
+ PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL,
+ PMIC_RG_AUD_CLK_INT_MON_FLAG_EN,
+ PMIC_AUDIO_DIG_ANA_ID,
+ PMIC_AUDIO_DIG_DIG_ID,
+ PMIC_AUDIO_DIG_ANA_MINOR_REV,
+ PMIC_AUDIO_DIG_ANA_MAJOR_REV,
+ PMIC_AUDIO_DIG_DIG_MINOR_REV,
+ PMIC_AUDIO_DIG_DIG_MAJOR_REV,
+ PMIC_AUDIO_DIG_DSN_CBS,
+ PMIC_AUDIO_DIG_DSN_BIX,
+ PMIC_AUDIO_DIG_ESP,
+ PMIC_AUDIO_DIG_DSN_FPI,
+ PMIC_AFE_ON,
+ PMIC_AFE_DL_LR_SWAP,
+ PMIC_AFE_UL_LR_SWAP,
+ PMIC_DL_2_SRC_ON_TMP_CTL_PRE,
+ PMIC_C_TWO_DIGITAL_MIC_CTL,
+ PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL,
+ PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL,
+ PMIC_UL_SRC_ON_TMP_CTL,
+ PMIC_UL_SDM_3_LEVEL_CTL,
+ PMIC_UL_LOOP_BACK_MODE_CTL,
+ PMIC_DIGMIC_3P25M_1P625M_SEL_CTL,
+ PMIC_DMIC_LOW_POWER_MODE_CTL,
+ PMIC_DL_SINE_ON,
+ PMIC_UL_SINE_ON,
+ PMIC_MTKAIF_SINE_ON,
+ PMIC_PDN_AFE_DL_PREDIST_CTL,
+ PMIC_PDN_AFE_TESTMODEL_CTL,
+ PMIC_PWR_CLK_DIS_CTL,
+ PMIC_PDN_I2S_DL_CTL,
+ PMIC_PDN_ADC_CTL,
+ PMIC_PDN_DAC_CTL,
+ PMIC_PDN_AFE_CTL,
+ PMIC_AFE_MON_SEL,
+ PMIC_AUDIO_SYS_TOP_MON_SEL,
+ PMIC_AUDIO_SYS_TOP_MON_SWAP,
+ PMIC_CCI_SCRAMBLER_EN,
+ PMIC_CCI_AUD_SDM_7BIT_SEL,
+ PMIC_CCI_AUD_SDM_MUTER,
+ PMIC_CCI_AUD_SDM_MUTEL,
+ PMIC_CCI_AUD_SPLIT_TEST_EN,
+ PMIC_CCI_ZERO_PAD_DISABLE,
+ PMIC_CCI_AUD_IDAC_TEST_EN,
+ PMIC_CCI_SPLT_SCRMB_ON,
+ PMIC_CCI_SPLT_SCRMB_CLK_ON,
+ PMIC_CCI_RAND_EN,
+ PMIC_CCI_LCH_INV,
+ PMIC_CCI_SCRAMBLER_CG_EN,
+ PMIC_CCI_AUDIO_FIFO_WPTR,
+ PMIC_CCI_AUD_ANACK_SEL,
+ PMIC_AUD_SDM_TEST_R,
+ PMIC_AUD_SDM_TEST_L,
+ PMIC_CCI_ACD_FUNC_RSTB,
+ PMIC_CCI_AFIFO_CLK_PWDB,
+ PMIC_CCI_ACD_MODE,
+ PMIC_CCI_AUDIO_FIFO_ENABLE,
+ PMIC_CCI_AUDIO_FIFO_CLKIN_INV,
+ PMIC_CCI_AUD_DAC_ANA_RSTB_SEL,
+ PMIC_CCI_AUD_DAC_ANA_MUTE,
+ PMIC_DIGMIC_TESTCK_SEL,
+ PMIC_DIGMIC_TESTCK_SRC_SEL,
+ PMIC_SDM_TESTCK_SRC_SEL,
+ PMIC_SDM_ANA13M_TESTCK_SRC_SEL,
+ PMIC_SDM_ANA13M_TESTCK_SEL,
+ PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL,
+ PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL,
+ PMIC_UL_FIFO_WDATA_TESTSRC_SEL,
+ PMIC_UL_FIFO_WDATA_TESTEN,
+ PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL,
+ PMIC_UL_FIFO_WCLK_INV,
+ PMIC_R_AUD_DAC_NEG_LARGE_MONO,
+ PMIC_R_AUD_DAC_POS_LARGE_MONO,
+ PMIC_R_AUD_DAC_SGEN_SW_RSTB,
+ PMIC_R_AUD_DAC_MONO_SEL,
+ PMIC_R_AUD_DAC_NEG_TINY_MONO,
+ PMIC_R_AUD_DAC_POS_TINY_MONO,
+ PMIC_R_AUD_DAC_NEG_SMALL_MONO,
+ PMIC_R_AUD_DAC_POS_SMALL_MONO,
+ PMIC_AUD_SCR_OUT_R,
+ PMIC_AUD_SCR_OUT_L,
+ PMIC_RGS_AUDRCTUNE0READ,
+ PMIC_RGS_AUDRCTUNE1READ,
+ PMIC_ASYNC_TEST_OUT_BCK,
+ PMIC_RG_MTKAIF_RXIF_FIFO_INTEN,
+ PMIC_AFE_RESERVED,
+ PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS,
+ PMIC_MTKAIF_RXIF_WR_FULL_STATUS,
+ PMIC_MTKAIF_RXIF_FIFO_STATUS,
+ PMIC_MTKAIFTX_V3_SDATA_OUT1,
+ PMIC_MTKAIFTX_V3_SDATA_OUT2,
+ PMIC_MTKAIFTX_V3_SYNC_OUT,
+ PMIC_MTKAIF_RXIF_INVALID_CYCLE,
+ PMIC_MTKAIF_RXIF_INVALID_FLAG,
+ PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG,
+ PMIC_MTKAIFRX_V3_SDATA_IN1,
+ PMIC_MTKAIFRX_V3_SDATA_IN2,
+ PMIC_MTKAIFRX_V3_SYNC_IN,
+ PMIC_MTKAIF_TXIF_IN_CH1,
+ PMIC_MTKAIF_TXIF_IN_CH2,
+ PMIC_MTKAIF_RXIF_OUT_CH1,
+ PMIC_MTKAIF_RXIF_OUT_CH2,
+ PMIC_RG_MTKAIF_LOOPBACK_TEST1,
+ PMIC_RG_MTKAIF_LOOPBACK_TEST2,
+ PMIC_RG_MTKAIF_PMIC_TXIF_8TO5,
+ PMIC_RG_MTKAIF_TXIF_PROTOCOL2,
+ PMIC_RG_MTKAIF_BYPASS_SRC_TEST,
+ PMIC_RG_MTKAIF_BYPASS_SRC_MODE,
+ PMIC_RG_MTKAIF_RXIF_PROTOCOL2,
+ PMIC_RG_MTKAIF_RXIF_CLKINV,
+ PMIC_RG_MTKAIF_RXIF_DATA_MODE,
+ PMIC_RG_MTKAIF_RXIF_DETECT_ON,
+ PMIC_RG_MTKAIF_RXIF_FIFO_RSP,
+ PMIC_RG_MTKAIF_RXIF_DATA_BIT,
+ PMIC_RG_MTKAIF_RXIF_VOICE_MODE,
+ PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2,
+ PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND,
+ PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND,
+ PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE,
+ PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE,
+ PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL,
+ PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2,
+ PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2,
+ PMIC_RG_MTKAIF_SYNC_WORD1,
+ PMIC_RG_MTKAIF_SYNC_WORD2,
+ PMIC_R_AUD_SDM_MUTE_R,
+ PMIC_R_AUD_SDM_MUTE_L,
+ PMIC_C_MUTE_SW_CTL,
+ PMIC_C_DAC_EN_CTL,
+ PMIC_C_AMP_DIV_CH1_CTL,
+ PMIC_C_FREQ_DIV_CH1_CTL,
+ PMIC_C_SGEN_RCH_INV_8BIT,
+ PMIC_C_SGEN_RCH_INV_5BIT,
+ PMIC_RG_AMIC_UL_ADC_CLK_SEL,
+ PMIC_RG_UL_ASYNC_FIFO_SOFT_RST,
+ PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN,
+ PMIC_DCCLK_GEN_ON,
+ PMIC_DCCLK_PDN,
+ PMIC_DCCLK_INV,
+ PMIC_DCCLK_DIV,
+ PMIC_DCCLK_PHASE_SEL,
+ PMIC_DCCLK_RESYNC_BYPASS,
+ PMIC_RESYNC_SRC_CK_INV,
+ PMIC_RESYNC_SRC_SEL,
+ PMIC_RG_AUD_PAD_TOP_PHASE_MODE,
+ PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK,
+ PMIC_RG_AUD_PAD_TOP_PHASE_MODE2,
+ PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK,
+ PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON,
+ PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2,
+ PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP,
+ PMIC_ADDA_AUD_PAD_TOP_MON,
+ PMIC_ADDA_AUD_PAD_TOP_MON1,
+ PMIC_AFE_CG_EN_MON,
+ PMIC_AUDENC_ANA_ID,
+ PMIC_AUDENC_DIG_ID,
+ PMIC_AUDENC_ANA_MINOR_REV,
+ PMIC_AUDENC_ANA_MAJOR_REV,
+ PMIC_AUDENC_DIG_MINOR_REV,
+ PMIC_AUDENC_DIG_MAJOR_REV,
+ PMIC_AUDENC_DSN_CBS,
+ PMIC_AUDENC_DSN_BIX,
+ PMIC_AUDENC_DSN_ESP,
+ PMIC_AUDENC_DSN_FPI,
+ PMIC_RG_AUDPREAMPLON,
+ PMIC_RG_AUDPREAMPLDCCEN,
+ PMIC_RG_AUDPREAMPLDCRPECHARGE,
+ PMIC_RG_AUDPREAMPLPGATEST,
+ PMIC_RG_AUDPREAMPLVSCALE,
+ PMIC_RG_AUDPREAMPLINPUTSEL,
+ PMIC_RG_AUDPREAMPLGAIN,
+ PMIC_RG_AUDADCLPWRUP,
+ PMIC_RG_AUDADCLINPUTSEL,
+ PMIC_RG_AUDPREAMPLSE,
+ PMIC_RG_AUDPREAMPRON,
+ PMIC_RG_AUDPREAMPRDCCEN,
+ PMIC_RG_AUDPREAMPRDCRPECHARGE,
+ PMIC_RG_AUDPREAMPRPGATEST,
+ PMIC_RG_AUDPREAMPRVSCALE,
+ PMIC_RG_AUDPREAMPRINPUTSEL,
+ PMIC_RG_AUDPREAMPRGAIN,
+ PMIC_RG_AUDADCRPWRUP,
+ PMIC_RG_AUDADCRINPUTSEL,
+ PMIC_RG_AUDPREAMPRSE,
+ PMIC_RG_AUDULHALFBIAS,
+ PMIC_RG_AUDGLBMADLPWEN,
+ PMIC_RG_AUDPREAMPLPEN,
+ PMIC_RG_AUDADC1STSTAGELPEN,
+ PMIC_RG_AUDADC2NDSTAGELPEN,
+ PMIC_RG_AUDADCFLASHLPEN,
+ PMIC_RG_AUDPREAMPIDDTEST,
+ PMIC_RG_AUDADC1STSTAGEIDDTEST,
+ PMIC_RG_AUDADC2NDSTAGEIDDTEST,
+ PMIC_RG_AUDADCREFBUFIDDTEST,
+ PMIC_RG_AUDADCFLASHIDDTEST,
+ PMIC_RG_AUDADCDAC0P25FS,
+ PMIC_RG_AUDADCCLKSEL,
+ PMIC_RG_AUDADCCLKSOURCE,
+ PMIC_RG_AUDPREAMPAAFEN,
+ PMIC_RG_DCCVCMBUFLPMODSEL,
+ PMIC_RG_DCCVCMBUFLPSWEN,
+ PMIC_RG_AUDSPAREPGA,
+ PMIC_RG_AUDADC1STSTAGESDENB,
+ PMIC_RG_AUDADC2NDSTAGERESET,
+ PMIC_RG_AUDADC3RDSTAGERESET,
+ PMIC_RG_AUDADCFSRESET,
+ PMIC_RG_AUDADCWIDECM,
+ PMIC_RG_AUDADCNOPATEST,
+ PMIC_RG_AUDADCBYPASS,
+ PMIC_RG_AUDADCFFBYPASS,
+ PMIC_RG_AUDADCDACFBCURRENT,
+ PMIC_RG_AUDADCDACIDDTEST,
+ PMIC_RG_AUDADCDACNRZ,
+ PMIC_RG_AUDADCNODEM,
+ PMIC_RG_AUDADCDACTEST,
+ PMIC_RG_CLKSQ_EN,
+ PMIC_RG_CLKSQ_IN_SEL,
+ PMIC_RG_AUDSPARE2VA28,
+ PMIC_RG_AUDRCTUNEL,
+ PMIC_RG_AUDRCTUNELSEL,
+ PMIC_RG_AUDRCTUNER,
+ PMIC_RG_AUDRCTUNERSEL,
+ PMIC_RG_AUDSPAREVA28,
+ PMIC_RG_AUDSPAREVA18,
+ PMIC_RG_AUDENCSPAREVA28,
+ PMIC_RG_AUDENCSPAREVA18,
+ PMIC_RG_AUDDIGMICEN,
+ PMIC_RG_AUDDIGMICBIAS,
+ PMIC_RG_DMICHPCLKEN,
+ PMIC_RG_AUDDIGMICPDUTY,
+ PMIC_RG_AUDDIGMICNDUTY,
+ PMIC_RG_DMICMONEN,
+ PMIC_RG_DMICMONSEL,
+ PMIC_RG_AUDSPAREVMIC,
+ PMIC_RG_AUDPWDBMICBIAS0,
+ PMIC_RG_AUDMICBIAS0BYPASSEN,
+ PMIC_RG_AUDMICBIAS0LOWPEN,
+ PMIC_RG_AUDMICBIAS0VREF,
+ PMIC_RG_AUDMICBIAS0DCSW0P1EN,
+ PMIC_RG_AUDMICBIAS0DCSW0P2EN,
+ PMIC_RG_AUDMICBIAS0DCSW0NEN,
+ PMIC_RG_AUDMICBIAS0DCSW2P1EN,
+ PMIC_RG_AUDMICBIAS0DCSW2P2EN,
+ PMIC_RG_AUDMICBIAS0DCSW2NEN,
+ PMIC_RG_AUDPWDBMICBIAS1,
+ PMIC_RG_AUDMICBIAS1BYPASSEN,
+ PMIC_RG_AUDMICBIAS1LOWPEN,
+ PMIC_RG_AUDMICBIAS1VREF,
+ PMIC_RG_AUDMICBIAS1DCSW1PEN,
+ PMIC_RG_AUDMICBIAS1DCSW1NEN,
+ PMIC_RG_BANDGAPGEN,
+ PMIC_RG_AUDACCDETMICBIAS0PULLLOW,
+ PMIC_RG_AUDACCDETMICBIAS1PULLLOW,
+ PMIC_RG_AUDACCDETVIN1PULLLOW,
+ PMIC_RG_AUDACCDETVTHACAL,
+ PMIC_RG_AUDACCDETVTHBCAL,
+ PMIC_RG_AUDACCDETTVDET,
+ PMIC_RG_ACCDETSEL,
+ PMIC_RG_SWBUFMODSEL,
+ PMIC_RG_SWBUFSWEN,
+ PMIC_RG_EINTCOMPVTH,
+ PMIC_RG_EINTCONFIGACCDET,
+ PMIC_RG_EINTHIRENB,
+ PMIC_RG_ACCDETSPAREVA28,
+ PMIC_RGS_AUDRCTUNELREAD,
+ PMIC_RGS_AUDRCTUNERREAD,
+ PMIC_AUDDEC_ANA_ID,
+ PMIC_AUDDEC_DIG_ID,
+ PMIC_AUDDEC_ANA_MINOR_REV,
+ PMIC_AUDDEC_ANA_MAJOR_REV,
+ PMIC_AUDDEC_DIG_MINOR_REV,
+ PMIC_AUDDEC_DIG_MAJOR_REV,
+ PMIC_AUDDEC_DSN_CBS,
+ PMIC_AUDDEC_DSN_BIX,
+ PMIC_AUDDEC_DSN_ESP,
+ PMIC_AUDDEC_DSN_FPI,
+ PMIC_RG_AUDDACLPWRUP_VAUDP15,
+ PMIC_RG_AUDDACRPWRUP_VAUDP15,
+ PMIC_RG_AUD_DAC_PWR_UP_VA28,
+ PMIC_RG_AUD_DAC_PWL_UP_VA28,
+ PMIC_RG_AUDOUT0_MUX_VAUDP28,
+ PMIC_RG_AUDOUT1_MUX_VAUDP28,
+ PMIC_RG_AUDOUT2_MUX_VAUDP28,
+ PMIC_RG_AUDVCMBUF_EN_VAUDP28,
+ PMIC_RG_AUDVCMBUF_VOSEL_VAUDP28,
+ PMIC_RG_AUDVCM2OUT0P_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2OUT0N_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2OUT1P_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2OUT1N_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2OUT2P_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2OUT2N_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2VIN0P_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2VIN0N_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2VIN1P_SW_EN_VAUDP28,
+ PMIC_RG_AUDVCM2VIN1N_SW_EN_VAUDP28,
+ PMIC_RG_AUDREFN_DERES_EN_VAUDP28,
+ PMIC_RG_ABIDEC_RSVD0_VAUDP28,
+ PMIC_RG_ABIDEC_RSVD1_VAUDP28,
+ PMIC_RG_ABIDEC_RSVD2_VAUDP28,
+ PMIC_RG_AUDHSPWRUP_VAUDP15,
+ PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15,
+ PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15,
+ PMIC_RG_AUDHSSCDISABLE_VAUDP15,
+ PMIC_RG_AUDHSBSCCURRENT_VAUDP15,
+ PMIC_RG_AUDHSSTARTUP_VAUDP15,
+ PMIC_RG_HSOUTPUTSTBENH_VAUDP15,
+ PMIC_RG_HSINPUTSTBENH_VAUDP15,
+ PMIC_RG_HSINPUTRESET0_VAUDP15,
+ PMIC_RG_HSOUTPUTRESET0_VAUDP15,
+ PMIC_RG_HSOUT_SHORTVCM_VAUDP15,
+ PMIC_RG_AUDLOLPWRUP_VAUDP15,
+ PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15,
+ PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15,
+ PMIC_RG_AUDLOLSCDISABLE_VAUDP15,
+ PMIC_RG_AUDLOLBSCCURRENT_VAUDP15,
+ PMIC_RG_AUDLOSTARTUP_VAUDP15,
+ PMIC_RG_LOINPUTSTBENH_VAUDP15,
+ PMIC_RG_LOOUTPUTSTBENH_VAUDP15,
+ PMIC_RG_LOINPUTRESET0_VAUDP15,
+ PMIC_RG_LOOUTPUTRESET0_VAUDP15,
+ PMIC_RG_LOOUT_SHORTVCM_VAUDP15,
+ PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15,
+ PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15,
+ PMIC_RG_AUDTRIMBUF_EN_VAUDP15,
+ PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15,
+ PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15,
+ PMIC_RG_AUDHPSPKDET_EN_VAUDP15,
+ PMIC_RG_ABIDEC_RSVD0_VA28,
+ PMIC_RG_ABIDEC_RSVD0_VAUDP15,
+ PMIC_RG_ABIDEC_RSVD1_VAUDP15,
+ PMIC_RG_ABIDEC_RSVD2_VAUDP15,
+ PMIC_RG_AUDZCDMUXSEL_VAUDP15,
+ PMIC_RG_AUDZCDCLKSEL_VAUDP15,
+ PMIC_RG_AUDBIASADJ_0_VAUDP15,
+ PMIC_RG_AUDBIASADJ_1_VAUDP15,
+ PMIC_RG_AUDIBIASPWRDN_VAUDP15,
+ PMIC_RG_RSTB_DECODER_VA28,
+ PMIC_RG_SEL_DECODER_96K_VA28,
+ PMIC_RG_SEL_DELAY_VCORE,
+ PMIC_RG_AUDGLB_PWRDN_VA28,
+ PMIC_RG_RSTB_ENCODER_VA28,
+ PMIC_RG_SEL_ENCODER_96K_VA28,
+ PMIC_RG_HCLDO_EN_VA18,
+ PMIC_RG_HCLDO_PDDIS_EN_VA18,
+ PMIC_RG_HCLDO_REMOTE_SENSE_VA18,
+ PMIC_RG_LCLDO_EN_VA18,
+ PMIC_RG_LCLDO_PDDIS_EN_VA18,
+ PMIC_RG_LCLDO_REMOTE_SENSE_VA18,
+ PMIC_RG_LCLDO_ENC_EN_VA28,
+ PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28,
+ PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28,
+ PMIC_RG_VA33REFGEN_EN_VA18,
+ PMIC_RG_VA28REFGEN_EN_VA28,
+ PMIC_RG_HCLDO_VOSEL_VA18,
+ PMIC_RG_LCLDO_VOSEL_VA18,
+ PMIC_RG_NVREG_EN_VAUDP15,
+ PMIC_RG_NVREG_PULL0V_VAUDP15,
+ PMIC_RG_AUDPMU_RSD0_VAUDP15,
+ PMIC_RG_AUDPMU_RSD0_VA18,
+ PMIC_RG_AUDPMU_RSD0_VA28,
+ PMIC_AUDDEC_ELR_LEN,
+ PMIC_RG_AUDHSTRIM_VAUDP15,
+ PMIC_RG_AUDHSFINETRIM_VAUDP15,
+ PMIC_RG_AUDHSTRIM_EN_VAUDP15,
+ PMIC_RG_AUDLOLTRIM_VAUDP15,
+ PMIC_RG_AUDLOLFINETRIM_VAUDP15,
+ PMIC_RG_AUDLOLTRIM_EN_VAUDP15,
+ PMIC_AUDZCD_ANA_ID,
+ PMIC_AUDZCD_DIG_ID,
+ PMIC_AUDZCD_ANA_MINOR_REV,
+ PMIC_AUDZCD_ANA_MAJOR_REV,
+ PMIC_AUDZCD_DIG_MINOR_REV,
+ PMIC_AUDZCD_DIG_MAJOR_REV,
+ PMIC_AUDZCD_DSN_CBS,
+ PMIC_AUDZCD_DSN_BIX,
+ PMIC_AUDZCD_DSN_ESP,
+ PMIC_AUDZCD_DSN_FPI,
+ PMIC_RG_AUDZCDENABLE,
+ PMIC_RG_AUDZCDGAINSTEPTIME,
+ PMIC_RG_AUDZCDGAINSTEPSIZE,
+ PMIC_RG_AUDZCDTIMEOUTMODESEL,
+ PMIC_RG_AUDLOLGAIN,
+ PMIC_RG_AUDLORGAIN,
+ PMIC_RG_AUDHPLGAIN,
+ PMIC_RG_AUDHPRGAIN,
+ PMIC_RG_AUDHSGAIN,
+ PMIC_RG_AUDIVLGAIN,
+ PMIC_RG_AUDIVRGAIN,
+ PMIC_RG_AUDINTGAIN1,
+ PMIC_RG_AUDINTGAIN2,
+ PMU_COMMAND_MAX
+};
+
+struct pmu_flag_table_entry_t {
+ enum PMU_FLAGS_LIST flagname;
+ unsigned short offset;
+ unsigned short mask;
+ unsigned char shift;
+};
+
+#endif /* _MT_PMIC_UPMU_HW_MT6389_H_ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/bgr.h b/src/bsp/lk/platform/mt2731/include/platform/bgr.h
new file mode 100644
index 0000000..3ff581a
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/bgr.h
@@ -0,0 +1,29 @@
+/*
+* Copyright (c) 2019 MediaTek Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining
+* a copy of this software and associated documentation files
+* (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be
+* included in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef __BGR_H__
+#define __BGR_H__
+
+void bgr_init(void);
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/clkbuf_ctl.h b/src/bsp/lk/platform/mt2731/include/platform/clkbuf_ctl.h
new file mode 100644
index 0000000..b59fd34
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/clkbuf_ctl.h
@@ -0,0 +1,68 @@
+/*
+* Copyright (c) 2019 MediaTek Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining
+* a copy of this software and associated documentation files
+* (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be
+* included in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+/**
+* @file clk_buf_ctl.h
+* @brief Driver for clock buffer control
+*
+*/
+#ifndef __CLK_BUF_CTL_H__
+#define __CLK_BUF_CTL_H__
+
+#include <compiler.h> /* For __WEAK */
+
+typedef enum {
+ CLK_BUF_SW_DISABLE = 0,
+ CLK_BUF_SW_ENABLE = 1,
+} CLK_BUF_SWCTRL_STATUS_T;
+
+/* clk_buf_id: users of clock buffer */
+enum clk_buf_id {
+ CLK_BUF_BB_MD = 0,
+ CLK_BUF_CONN,
+ CLK_BUF_AUDIO,
+ CLK_BUF_INVALID
+};
+
+/* xo_id: clock buffer list */
+enum xo_id {
+ XO_SOC = 0,
+ XO_WCN, /* GPS */
+ XO_NFC, /* Disabled in mt2731 */
+ XO_CEL,
+ XO_AUD, /* Disabled */
+ XO_PD, /* Disabled */
+ XO_EXT, /* Phy for PCIe&U3 */
+ XO_NUMBER
+};
+
+#define CLKBUF_NUM XO_NUMBER
+
+#define STA_CLK_ON 1
+#define STA_CLK_OFF 0
+
+/* NOP in mt6356 */
+__WEAK void mt_clkbuf_init(void);
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/cust_gpio_boot.h b/src/bsp/lk/platform/mt2731/include/platform/cust_gpio_boot.h
new file mode 100644
index 0000000..7009000
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/cust_gpio_boot.h
@@ -0,0 +1,1329 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef BOARD_SPECIFIC_CUST_GPIO_BOOT_H
+#define BOARD_SPECIFIC_CUST_GPIO_BOOT_H
+
+/* Configuration for GPIO16 */
+#define GPIO16_MODE GPIO_MODE_01
+#define GPIO16_DIR GPIO_DIR_IN
+#define GPIO16_PULLEN GPIO_PULL_DISABLE
+#define GPIO16_PULL GPIO_PULL_DOWN
+#define GPIO16_DATAOUT GPIO_OUT_ZERO
+#define GPIO16_SMT GPIO_SMT_DISABLE
+#define GPIO16_IES GPIO_IES_ENABLE
+/* Configuration for GPIO17 */
+#define GPIO17_MODE GPIO_MODE_01
+#define GPIO17_DIR GPIO_DIR_IN
+#define GPIO17_PULLEN GPIO_PULL_DISABLE
+#define GPIO17_PULL GPIO_PULL_DOWN
+#define GPIO17_DATAOUT GPIO_OUT_ZERO
+#define GPIO17_SMT GPIO_SMT_DISABLE
+#define GPIO17_IES GPIO_IES_ENABLE
+/* Configuration for GPIO18 */
+#define GPIO18_MODE GPIO_MODE_02
+#define GPIO18_DIR GPIO_DIR_IN
+#define GPIO18_PULLEN GPIO_PULL_DISABLE
+#define GPIO18_PULL GPIO_PULL_DOWN
+#define GPIO18_DATAOUT GPIO_OUT_ZERO
+#define GPIO18_SMT GPIO_SMT_DISABLE
+#define GPIO18_IES GPIO_IES_ENABLE
+/* Configuration for GPIO19 */
+#define GPIO19_MODE GPIO_MODE_02
+#define GPIO19_DIR GPIO_DIR_IN
+#define GPIO19_PULLEN GPIO_PULL_DISABLE
+#define GPIO19_PULL GPIO_PULL_DOWN
+#define GPIO19_DATAOUT GPIO_OUT_ZERO
+#define GPIO19_SMT GPIO_SMT_DISABLE
+#define GPIO19_IES GPIO_IES_ENABLE
+/* Configuration for GPIO20 */
+#define GPIO20_MODE GPIO_MODE_02
+#define GPIO20_DIR GPIO_DIR_IN
+#define GPIO20_PULLEN GPIO_PULL_DISABLE
+#define GPIO20_PULL GPIO_PULL_DOWN
+#define GPIO20_DATAOUT GPIO_OUT_ZERO
+#define GPIO20_SMT GPIO_SMT_DISABLE
+#define GPIO20_IES GPIO_IES_ENABLE
+/* Configuration for GPIO21 */
+#define GPIO21_MODE GPIO_MODE_02
+#define GPIO21_DIR GPIO_DIR_IN
+#define GPIO21_PULLEN GPIO_PULL_DISABLE
+#define GPIO21_PULL GPIO_PULL_DOWN
+#define GPIO21_DATAOUT GPIO_OUT_ZERO
+#define GPIO21_SMT GPIO_SMT_DISABLE
+#define GPIO21_IES GPIO_IES_ENABLE
+/* Configuration for GPIO22 */
+#define GPIO22_MODE GPIO_MODE_02
+#define GPIO22_DIR GPIO_DIR_IN
+#define GPIO22_PULLEN GPIO_PULL_DISABLE
+#define GPIO22_PULL GPIO_PULL_DOWN
+#define GPIO22_DATAOUT GPIO_OUT_ZERO
+#define GPIO22_SMT GPIO_SMT_DISABLE
+#define GPIO22_IES GPIO_IES_ENABLE
+/* Configuration for GPIO23 */
+#define GPIO23_MODE GPIO_MODE_02
+#define GPIO23_DIR GPIO_DIR_IN
+#define GPIO23_PULLEN GPIO_PULL_DISABLE
+#define GPIO23_PULL GPIO_PULL_DOWN
+#define GPIO23_DATAOUT GPIO_OUT_ZERO
+#define GPIO23_SMT GPIO_SMT_DISABLE
+#define GPIO23_IES GPIO_IES_ENABLE
+/* Configuration for GPIO0 */
+#define GPIO0_MODE GPIO_MODE_00
+#define GPIO0_DIR GPIO_DIR_OUT
+#define GPIO0_PULLEN GPIO_PULL_ENABLE
+#define GPIO0_PULL GPIO_PULL_UP
+#define GPIO0_DATAOUT GPIO_OUT_ZERO
+#define GPIO0_SMT GPIO_SMT_DISABLE
+#define GPIO0_IES GPIO_IES_ENABLE
+/* Configuration for GPIO1 */
+#define GPIO1_MODE GPIO_MODE_00
+#define GPIO1_DIR GPIO_DIR_IN
+#define GPIO1_PULLEN GPIO_PULL_ENABLE
+#define GPIO1_PULL GPIO_PULL_DOWN
+#define GPIO1_DATAOUT GPIO_OUT_ZERO
+#define GPIO1_SMT GPIO_SMT_DISABLE
+#define GPIO1_IES GPIO_IES_ENABLE
+/* Configuration for GPIO24 */
+#define GPIO24_MODE GPIO_MODE_01
+#define GPIO24_DIR GPIO_DIR_IN
+#define GPIO24_PULLEN GPIO_PULL_DISABLE
+#define GPIO24_PULL GPIO_PULL_DOWN
+#define GPIO24_DATAOUT GPIO_OUT_ZERO
+#define GPIO24_SMT GPIO_SMT_DISABLE
+#define GPIO24_IES GPIO_IES_ENABLE
+/* Configuration for GPIO25 */
+#define GPIO25_MODE GPIO_MODE_01
+#define GPIO25_DIR GPIO_DIR_IN
+#define GPIO25_PULLEN GPIO_PULL_DISABLE
+#define GPIO25_PULL GPIO_PULL_DOWN
+#define GPIO25_DATAOUT GPIO_OUT_ZERO
+#define GPIO25_SMT GPIO_SMT_DISABLE
+#define GPIO25_IES GPIO_IES_ENABLE
+/* Configuration for GPIO26 */
+#define GPIO26_MODE GPIO_MODE_01
+#define GPIO26_DIR GPIO_DIR_IN
+#define GPIO26_PULLEN GPIO_PULL_DISABLE
+#define GPIO26_PULL GPIO_PULL_DOWN
+#define GPIO26_DATAOUT GPIO_OUT_ZERO
+#define GPIO26_SMT GPIO_SMT_DISABLE
+#define GPIO26_IES GPIO_IES_ENABLE
+/* Configuration for GPIO27 */
+#define GPIO27_MODE GPIO_MODE_00
+#define GPIO27_DIR GPIO_DIR_IN
+#define GPIO27_PULLEN GPIO_PULL_ENABLE
+#define GPIO27_PULL GPIO_PULL_DOWN
+#define GPIO27_DATAOUT GPIO_OUT_ZERO
+#define GPIO27_SMT GPIO_SMT_DISABLE
+#define GPIO27_IES GPIO_IES_ENABLE
+/* Configuration for GPIO28 */
+#define GPIO28_MODE GPIO_MODE_00
+#define GPIO28_DIR GPIO_DIR_OUT
+#define GPIO28_PULLEN GPIO_PULL_DISABLE
+#define GPIO28_PULL GPIO_PULL_DOWN
+#define GPIO28_DATAOUT GPIO_OUT_ZERO
+#define GPIO28_SMT GPIO_SMT_DISABLE
+#define GPIO28_IES GPIO_IES_ENABLE
+/* Configuration for GPIO29 */
+#define GPIO29_MODE GPIO_MODE_01
+#define GPIO29_DIR GPIO_DIR_IN
+#define GPIO29_PULLEN GPIO_PULL_DISABLE
+#define GPIO29_PULL GPIO_PULL_DOWN
+#define GPIO29_DATAOUT GPIO_OUT_ZERO
+#define GPIO29_SMT GPIO_SMT_DISABLE
+#define GPIO29_IES GPIO_IES_ENABLE
+/* Configuration for GPIO30 */
+#define GPIO30_MODE GPIO_MODE_00
+#define GPIO30_DIR GPIO_DIR_OUT
+#define GPIO30_PULLEN GPIO_PULL_ENABLE
+#define GPIO30_PULL GPIO_PULL_UP
+#define GPIO30_DATAOUT GPIO_OUT_ONE
+#define GPIO30_SMT GPIO_SMT_ENABLE
+#define GPIO30_IES GPIO_IES_ENABLE
+/* Configuration for GPIO31 */
+#define GPIO31_MODE GPIO_MODE_01
+#define GPIO31_DIR GPIO_DIR_IN
+#define GPIO31_PULLEN GPIO_PULL_ENABLE
+#define GPIO31_PULL GPIO_PULL_DOWN
+#define GPIO31_DATAOUT GPIO_OUT_ZERO
+#define GPIO31_SMT GPIO_SMT_ENABLE
+#define GPIO31_IES GPIO_IES_ENABLE
+/* Configuration for GPIO32 */
+#define GPIO32_MODE GPIO_MODE_01
+#define GPIO32_DIR GPIO_DIR_IN
+#define GPIO32_PULLEN GPIO_PULL_ENABLE
+#define GPIO32_PULL GPIO_PULL_DOWN
+#define GPIO32_DATAOUT GPIO_OUT_ZERO
+#define GPIO32_SMT GPIO_SMT_ENABLE
+#define GPIO32_IES GPIO_IES_ENABLE
+/* Configuration for GPIO33 */
+#define GPIO33_MODE GPIO_MODE_01
+#define GPIO33_DIR GPIO_DIR_IN
+#define GPIO33_PULLEN GPIO_PULL_ENABLE
+#define GPIO33_PULL GPIO_PULL_DOWN
+#define GPIO33_DATAOUT GPIO_OUT_ZERO
+#define GPIO33_SMT GPIO_SMT_ENABLE
+#define GPIO33_IES GPIO_IES_ENABLE
+/* Configuration for GPIO34 */
+#define GPIO34_MODE GPIO_MODE_01
+#define GPIO34_DIR GPIO_DIR_IN
+#define GPIO34_PULLEN GPIO_PULL_ENABLE
+#define GPIO34_PULL GPIO_PULL_DOWN
+#define GPIO34_DATAOUT GPIO_OUT_ZERO
+#define GPIO34_SMT GPIO_SMT_ENABLE
+#define GPIO34_IES GPIO_IES_ENABLE
+/* Configuration for GPIO35 */
+#define GPIO35_MODE GPIO_MODE_01
+#define GPIO35_DIR GPIO_DIR_IN
+#define GPIO35_PULLEN GPIO_PULL_ENABLE
+#define GPIO35_PULL GPIO_PULL_DOWN
+#define GPIO35_DATAOUT GPIO_OUT_ZERO
+#define GPIO35_SMT GPIO_SMT_ENABLE
+#define GPIO35_IES GPIO_IES_ENABLE
+/* Configuration for GPIO36 */
+#define GPIO36_MODE GPIO_MODE_01
+#define GPIO36_DIR GPIO_DIR_IN
+#define GPIO36_PULLEN GPIO_PULL_ENABLE
+#define GPIO36_PULL GPIO_PULL_DOWN
+#define GPIO36_DATAOUT GPIO_OUT_ZERO
+#define GPIO36_SMT GPIO_SMT_ENABLE
+#define GPIO36_IES GPIO_IES_ENABLE
+/* Configuration for GPIO56 */
+#define GPIO56_MODE GPIO_MODE_01
+#define GPIO56_DIR GPIO_DIR_IN
+#define GPIO56_PULLEN GPIO_PULL_DISABLE
+#define GPIO56_PULL GPIO_PULL_DOWN
+#define GPIO56_DATAOUT GPIO_OUT_ZERO
+#define GPIO56_SMT GPIO_SMT_DISABLE
+#define GPIO56_IES GPIO_IES_ENABLE
+/* Configuration for GPIO57 */
+#define GPIO57_MODE GPIO_MODE_01
+#define GPIO57_DIR GPIO_DIR_IN
+#define GPIO57_PULLEN GPIO_PULL_ENABLE
+#define GPIO57_PULL GPIO_PULL_UP
+#define GPIO57_DATAOUT GPIO_OUT_ZERO
+#define GPIO57_SMT GPIO_SMT_DISABLE
+#define GPIO57_IES GPIO_IES_ENABLE
+/* Configuration for GPIO2 */
+#define GPIO2_MODE GPIO_MODE_00
+#define GPIO2_DIR GPIO_DIR_IN
+#define GPIO2_PULLEN GPIO_PULL_ENABLE
+#define GPIO2_PULL GPIO_PULL_DOWN
+#define GPIO2_DATAOUT GPIO_OUT_ZERO
+#define GPIO2_SMT GPIO_SMT_DISABLE
+#define GPIO2_IES GPIO_IES_ENABLE
+/* Configuration for GPIO37 */
+#define GPIO37_MODE GPIO_MODE_01
+#define GPIO37_DIR GPIO_DIR_IN
+#define GPIO37_PULLEN GPIO_PULL_ENABLE
+#define GPIO37_PULL GPIO_PULL_UP
+#define GPIO37_DATAOUT GPIO_OUT_ZERO
+#define GPIO37_SMT GPIO_SMT_ENABLE
+#define GPIO37_IES GPIO_IES_ENABLE
+/* Configuration for GPIO38 */
+#define GPIO38_MODE GPIO_MODE_01
+#define GPIO38_DIR GPIO_DIR_IN
+#define GPIO38_PULLEN GPIO_PULL_ENABLE
+#define GPIO38_PULL GPIO_PULL_UP
+#define GPIO38_DATAOUT GPIO_OUT_ZERO
+#define GPIO38_SMT GPIO_SMT_ENABLE
+#define GPIO38_IES GPIO_IES_ENABLE
+/* Configuration for GPIO39 */
+#define GPIO39_MODE GPIO_MODE_01
+#define GPIO39_DIR GPIO_DIR_IN
+#define GPIO39_PULLEN GPIO_PULL_ENABLE
+#define GPIO39_PULL GPIO_PULL_UP
+#define GPIO39_DATAOUT GPIO_OUT_ZERO
+#define GPIO39_SMT GPIO_SMT_ENABLE
+#define GPIO39_IES GPIO_IES_ENABLE
+/* Configuration for GPIO40 */
+#define GPIO40_MODE GPIO_MODE_01
+#define GPIO40_DIR GPIO_DIR_IN
+#define GPIO40_PULLEN GPIO_PULL_ENABLE
+#define GPIO40_PULL GPIO_PULL_UP
+#define GPIO40_DATAOUT GPIO_OUT_ZERO
+#define GPIO40_SMT GPIO_SMT_ENABLE
+#define GPIO40_IES GPIO_IES_ENABLE
+/* Configuration for GPIO41 */
+#define GPIO41_MODE GPIO_MODE_01
+#define GPIO41_DIR GPIO_DIR_IN
+#define GPIO41_PULLEN GPIO_PULL_ENABLE
+#define GPIO41_PULL GPIO_PULL_UP
+#define GPIO41_DATAOUT GPIO_OUT_ZERO
+#define GPIO41_SMT GPIO_SMT_ENABLE
+#define GPIO41_IES GPIO_IES_ENABLE
+/* Configuration for GPIO42 */
+#define GPIO42_MODE GPIO_MODE_01
+#define GPIO42_DIR GPIO_DIR_IN
+#define GPIO42_PULLEN GPIO_PULL_ENABLE
+#define GPIO42_PULL GPIO_PULL_UP
+#define GPIO42_DATAOUT GPIO_OUT_ZERO
+#define GPIO42_SMT GPIO_SMT_ENABLE
+#define GPIO42_IES GPIO_IES_ENABLE
+/* Configuration for GPIO43 */
+#define GPIO43_MODE GPIO_MODE_00
+#define GPIO43_DIR GPIO_DIR_IN
+#define GPIO43_PULLEN GPIO_PULL_ENABLE
+#define GPIO43_PULL GPIO_PULL_DOWN
+#define GPIO43_DATAOUT GPIO_OUT_ZERO
+#define GPIO43_SMT GPIO_SMT_DISABLE
+#define GPIO43_IES GPIO_IES_ENABLE
+/* Configuration for GPIO13 */
+#define GPIO13_MODE GPIO_MODE_00
+#define GPIO13_DIR GPIO_DIR_IN
+#define GPIO13_PULLEN GPIO_PULL_ENABLE
+#define GPIO13_PULL GPIO_PULL_DOWN
+#define GPIO13_DATAOUT GPIO_OUT_ZERO
+#define GPIO13_SMT GPIO_SMT_DISABLE
+#define GPIO13_IES GPIO_IES_ENABLE
+/* Configuration for GPIO14 */
+#define GPIO14_MODE GPIO_MODE_00
+#define GPIO14_DIR GPIO_DIR_IN
+#define GPIO14_PULLEN GPIO_PULL_ENABLE
+#define GPIO14_PULL GPIO_PULL_DOWN
+#define GPIO14_DATAOUT GPIO_OUT_ZERO
+#define GPIO14_SMT GPIO_SMT_DISABLE
+#define GPIO14_IES GPIO_IES_ENABLE
+/* Configuration for GPIO15 */
+#define GPIO15_MODE GPIO_MODE_00
+#define GPIO15_DIR GPIO_DIR_IN
+#define GPIO15_PULLEN GPIO_PULL_ENABLE
+#define GPIO15_PULL GPIO_PULL_DOWN
+#define GPIO15_DATAOUT GPIO_OUT_ZERO
+#define GPIO15_SMT GPIO_SMT_DISABLE
+#define GPIO15_IES GPIO_IES_ENABLE
+/* Configuration for GPIO47 */
+#define GPIO47_MODE GPIO_MODE_01
+#define GPIO47_DIR GPIO_DIR_OUT
+#define GPIO47_PULLEN GPIO_PULL_DISABLE
+#define GPIO47_PULL GPIO_PULL_DOWN
+#define GPIO47_DATAOUT GPIO_OUT_ZERO
+#define GPIO47_SMT GPIO_SMT_DISABLE
+#define GPIO47_IES GPIO_IES_ENABLE
+/* Configuration for GPIO48 */
+#define GPIO48_MODE GPIO_MODE_01
+#define GPIO48_DIR GPIO_DIR_IN
+#define GPIO48_PULLEN GPIO_PULL_ENABLE
+#define GPIO48_PULL GPIO_PULL_DOWN
+#define GPIO48_DATAOUT GPIO_OUT_ZERO
+#define GPIO48_SMT GPIO_SMT_DISABLE
+#define GPIO48_IES GPIO_IES_ENABLE
+/* Configuration for GPIO49 */
+#define GPIO49_MODE GPIO_MODE_01
+#define GPIO49_DIR GPIO_DIR_OUT
+#define GPIO49_PULLEN GPIO_PULL_DISABLE
+#define GPIO49_PULL GPIO_PULL_DOWN
+#define GPIO49_DATAOUT GPIO_OUT_ZERO
+#define GPIO49_SMT GPIO_SMT_DISABLE
+#define GPIO49_IES GPIO_IES_ENABLE
+/* Configuration for GPIO50 */
+#define GPIO50_MODE GPIO_MODE_01
+#define GPIO50_DIR GPIO_DIR_OUT
+#define GPIO50_PULLEN GPIO_PULL_DISABLE
+#define GPIO50_PULL GPIO_PULL_DOWN
+#define GPIO50_DATAOUT GPIO_OUT_ZERO
+#define GPIO50_SMT GPIO_SMT_DISABLE
+#define GPIO50_IES GPIO_IES_ENABLE
+/* Configuration for GPIO4 */
+#define GPIO4_MODE GPIO_MODE_04
+#define GPIO4_DIR GPIO_DIR_IN
+#define GPIO4_PULLEN GPIO_PULL_DISABLE
+#define GPIO4_PULL GPIO_PULL_DOWN
+#define GPIO4_DATAOUT GPIO_OUT_ZERO
+#define GPIO4_SMT GPIO_SMT_DISABLE
+#define GPIO4_IES GPIO_IES_ENABLE
+/* Configuration for GPIO5 */
+#define GPIO5_MODE GPIO_MODE_04
+#define GPIO5_DIR GPIO_DIR_IN
+#define GPIO5_PULLEN GPIO_PULL_DISABLE
+#define GPIO5_PULL GPIO_PULL_DOWN
+#define GPIO5_DATAOUT GPIO_OUT_ZERO
+#define GPIO5_SMT GPIO_SMT_DISABLE
+#define GPIO5_IES GPIO_IES_ENABLE
+/* Configuration for GPIO6 */
+#define GPIO6_MODE GPIO_MODE_04
+#define GPIO6_DIR GPIO_DIR_IN
+#define GPIO6_PULLEN GPIO_PULL_DISABLE
+#define GPIO6_PULL GPIO_PULL_DOWN
+#define GPIO6_DATAOUT GPIO_OUT_ZERO
+#define GPIO6_SMT GPIO_SMT_DISABLE
+#define GPIO6_IES GPIO_IES_ENABLE
+/* Configuration for GPIO7 */
+#define GPIO7_MODE GPIO_MODE_00
+#define GPIO7_DIR GPIO_DIR_IN
+#define GPIO7_PULLEN GPIO_PULL_ENABLE
+#define GPIO7_PULL GPIO_PULL_DOWN
+#define GPIO7_DATAOUT GPIO_OUT_ZERO
+#define GPIO7_SMT GPIO_SMT_DISABLE
+#define GPIO7_IES GPIO_IES_ENABLE
+/* Configuration for GPIO51 */
+#define GPIO51_MODE GPIO_MODE_01
+#define GPIO51_DIR GPIO_DIR_IN
+#define GPIO51_PULLEN GPIO_PULL_ENABLE
+#define GPIO51_PULL GPIO_PULL_DOWN
+#define GPIO51_DATAOUT GPIO_OUT_ZERO
+#define GPIO51_SMT GPIO_SMT_DISABLE
+#define GPIO51_IES GPIO_IES_ENABLE
+/* Configuration for GPIO52 */
+#define GPIO52_MODE GPIO_MODE_01
+#define GPIO52_DIR GPIO_DIR_IN
+#define GPIO52_PULLEN GPIO_PULL_ENABLE
+#define GPIO52_PULL GPIO_PULL_DOWN
+#define GPIO52_DATAOUT GPIO_OUT_ZERO
+#define GPIO52_SMT GPIO_SMT_DISABLE
+#define GPIO52_IES GPIO_IES_ENABLE
+/* Configuration for GPIO53 */
+#define GPIO53_MODE GPIO_MODE_01
+#define GPIO53_DIR GPIO_DIR_IN
+#define GPIO53_PULLEN GPIO_PULL_ENABLE
+#define GPIO53_PULL GPIO_PULL_DOWN
+#define GPIO53_DATAOUT GPIO_OUT_ZERO
+#define GPIO53_SMT GPIO_SMT_DISABLE
+#define GPIO53_IES GPIO_IES_ENABLE
+/* Configuration for GPIO54 */
+#define GPIO54_MODE GPIO_MODE_01
+#define GPIO54_DIR GPIO_DIR_IN
+#define GPIO54_PULLEN GPIO_PULL_DISABLE
+#define GPIO54_PULL GPIO_PULL_DOWN
+#define GPIO54_DATAOUT GPIO_OUT_ZERO
+#define GPIO54_SMT GPIO_SMT_DISABLE
+#define GPIO54_IES GPIO_IES_ENABLE
+/* Configuration for GPIO55 */
+#define GPIO55_MODE GPIO_MODE_01
+#define GPIO55_DIR GPIO_DIR_IN
+#define GPIO55_PULLEN GPIO_PULL_ENABLE
+#define GPIO55_PULL GPIO_PULL_UP
+#define GPIO55_DATAOUT GPIO_OUT_ZERO
+#define GPIO55_SMT GPIO_SMT_DISABLE
+#define GPIO55_IES GPIO_IES_ENABLE
+/* Configuration for GPIO3 */
+#define GPIO3_MODE GPIO_MODE_00
+#define GPIO3_DIR GPIO_DIR_IN
+#define GPIO3_PULLEN GPIO_PULL_ENABLE
+#define GPIO3_PULL GPIO_PULL_UP
+#define GPIO3_DATAOUT GPIO_OUT_ZERO
+#define GPIO3_SMT GPIO_SMT_DISABLE
+#define GPIO3_IES GPIO_IES_ENABLE
+/* Configuration for GPIO8 */
+#define GPIO8_MODE GPIO_MODE_00
+#define GPIO8_DIR GPIO_DIR_IN
+#define GPIO8_PULLEN GPIO_PULL_ENABLE
+#define GPIO8_PULL GPIO_PULL_DOWN
+#define GPIO8_DATAOUT GPIO_OUT_ZERO
+#define GPIO8_SMT GPIO_SMT_DISABLE
+#define GPIO8_IES GPIO_IES_ENABLE
+/* Configuration for GPIO58 */
+#define GPIO58_MODE GPIO_MODE_00
+#define GPIO58_DIR GPIO_DIR_IN
+#define GPIO58_PULLEN GPIO_PULL_ENABLE
+#define GPIO58_PULL GPIO_PULL_UP
+#define GPIO58_DATAOUT GPIO_OUT_ZERO
+#define GPIO58_SMT GPIO_SMT_DISABLE
+#define GPIO58_IES GPIO_IES_ENABLE
+/* Configuration for GPIO59 */
+#define GPIO59_MODE GPIO_MODE_02
+#define GPIO59_DIR GPIO_DIR_IN
+#define GPIO59_PULLEN GPIO_PULL_DISABLE
+#define GPIO59_PULL GPIO_PULL_DOWN
+#define GPIO59_DATAOUT GPIO_OUT_ZERO
+#define GPIO59_SMT GPIO_SMT_ENABLE
+#define GPIO59_IES GPIO_IES_ENABLE
+/* Configuration for GPIO60 */
+#define GPIO60_MODE GPIO_MODE_02
+#define GPIO60_DIR GPIO_DIR_IN
+#define GPIO60_PULLEN GPIO_PULL_DISABLE
+#define GPIO60_PULL GPIO_PULL_DOWN
+#define GPIO60_DATAOUT GPIO_OUT_ZERO
+#define GPIO60_SMT GPIO_SMT_ENABLE
+#define GPIO60_IES GPIO_IES_ENABLE
+/* Configuration for GPIO61 */
+#define GPIO61_MODE GPIO_MODE_02
+#define GPIO61_DIR GPIO_DIR_IN
+#define GPIO61_PULLEN GPIO_PULL_ENABLE
+#define GPIO61_PULL GPIO_PULL_UP
+#define GPIO61_DATAOUT GPIO_OUT_ZERO
+#define GPIO61_SMT GPIO_SMT_ENABLE
+#define GPIO61_IES GPIO_IES_ENABLE
+/* Configuration for GPIO62 */
+#define GPIO62_MODE GPIO_MODE_02
+#define GPIO62_DIR GPIO_DIR_IN
+#define GPIO62_PULLEN GPIO_PULL_DISABLE
+#define GPIO62_PULL GPIO_PULL_DOWN
+#define GPIO62_DATAOUT GPIO_OUT_ZERO
+#define GPIO62_SMT GPIO_SMT_ENABLE
+#define GPIO62_IES GPIO_IES_ENABLE
+/* Configuration for GPIO63 */
+#define GPIO63_MODE GPIO_MODE_02
+#define GPIO63_DIR GPIO_DIR_IN
+#define GPIO63_PULLEN GPIO_PULL_DISABLE
+#define GPIO63_PULL GPIO_PULL_DOWN
+#define GPIO63_DATAOUT GPIO_OUT_ZERO
+#define GPIO63_SMT GPIO_SMT_ENABLE
+#define GPIO63_IES GPIO_IES_ENABLE
+/* Configuration for GPIO64 */
+#define GPIO64_MODE GPIO_MODE_02
+#define GPIO64_DIR GPIO_DIR_IN
+#define GPIO64_PULLEN GPIO_PULL_DISABLE
+#define GPIO64_PULL GPIO_PULL_DOWN
+#define GPIO64_DATAOUT GPIO_OUT_ZERO
+#define GPIO64_SMT GPIO_SMT_ENABLE
+#define GPIO64_IES GPIO_IES_ENABLE
+/* Configuration for GPIO9 */
+#define GPIO9_MODE GPIO_MODE_02
+#define GPIO9_DIR GPIO_DIR_IN
+#define GPIO9_PULLEN GPIO_PULL_ENABLE
+#define GPIO9_PULL GPIO_PULL_DOWN
+#define GPIO9_DATAOUT GPIO_OUT_ZERO
+#define GPIO9_SMT GPIO_SMT_DISABLE
+#define GPIO9_IES GPIO_IES_ENABLE
+/* Configuration for GPIO65 */
+#define GPIO65_MODE GPIO_MODE_01
+#define GPIO65_DIR GPIO_DIR_IN
+#define GPIO65_PULLEN GPIO_PULL_DISABLE
+#define GPIO65_PULL GPIO_PULL_DOWN
+#define GPIO65_DATAOUT GPIO_OUT_ZERO
+#define GPIO65_SMT GPIO_SMT_DISABLE
+#define GPIO65_IES GPIO_IES_ENABLE
+/* Configuration for GPIO66 */
+#define GPIO66_MODE GPIO_MODE_01
+#define GPIO66_DIR GPIO_DIR_IN
+#define GPIO66_PULLEN GPIO_PULL_DISABLE
+#define GPIO66_PULL GPIO_PULL_DOWN
+#define GPIO66_DATAOUT GPIO_OUT_ZERO
+#define GPIO66_SMT GPIO_SMT_DISABLE
+#define GPIO66_IES GPIO_IES_ENABLE
+/* Configuration for GPIO67 */
+#define GPIO67_MODE GPIO_MODE_01
+#define GPIO67_DIR GPIO_DIR_IN
+#define GPIO67_PULLEN GPIO_PULL_DISABLE
+#define GPIO67_PULL GPIO_PULL_DOWN
+#define GPIO67_DATAOUT GPIO_OUT_ZERO
+#define GPIO67_SMT GPIO_SMT_DISABLE
+#define GPIO67_IES GPIO_IES_ENABLE
+/* Configuration for GPIO68 */
+#define GPIO68_MODE GPIO_MODE_01
+#define GPIO68_DIR GPIO_DIR_IN
+#define GPIO68_PULLEN GPIO_PULL_ENABLE
+#define GPIO68_PULL GPIO_PULL_DOWN
+#define GPIO68_DATAOUT GPIO_OUT_ZERO
+#define GPIO68_SMT GPIO_SMT_DISABLE
+#define GPIO68_IES GPIO_IES_ENABLE
+/* Configuration for GPIO69 */
+#define GPIO69_MODE GPIO_MODE_01
+#define GPIO69_DIR GPIO_DIR_IN
+#define GPIO69_PULLEN GPIO_PULL_ENABLE
+#define GPIO69_PULL GPIO_PULL_DOWN
+#define GPIO69_DATAOUT GPIO_OUT_ZERO
+#define GPIO69_SMT GPIO_SMT_DISABLE
+#define GPIO69_IES GPIO_IES_ENABLE
+/* Configuration for GPIO70 */
+#define GPIO70_MODE GPIO_MODE_01
+#define GPIO70_DIR GPIO_DIR_IN
+#define GPIO70_PULLEN GPIO_PULL_ENABLE
+#define GPIO70_PULL GPIO_PULL_DOWN
+#define GPIO70_DATAOUT GPIO_OUT_ZERO
+#define GPIO70_SMT GPIO_SMT_DISABLE
+#define GPIO70_IES GPIO_IES_ENABLE
+/* Configuration for GPIO71 */
+#define GPIO71_MODE GPIO_MODE_01
+#define GPIO71_DIR GPIO_DIR_IN
+#define GPIO71_PULLEN GPIO_PULL_DISABLE
+#define GPIO71_PULL GPIO_PULL_DOWN
+#define GPIO71_DATAOUT GPIO_OUT_ZERO
+#define GPIO71_SMT GPIO_SMT_DISABLE
+#define GPIO71_IES GPIO_IES_ENABLE
+/* Configuration for GPIO72 */
+#define GPIO72_MODE GPIO_MODE_01
+#define GPIO72_DIR GPIO_DIR_IN
+#define GPIO72_PULLEN GPIO_PULL_DISABLE
+#define GPIO72_PULL GPIO_PULL_DOWN
+#define GPIO72_DATAOUT GPIO_OUT_ZERO
+#define GPIO72_SMT GPIO_SMT_DISABLE
+#define GPIO72_IES GPIO_IES_ENABLE
+/* Configuration for GPIO73 */
+#define GPIO73_MODE GPIO_MODE_01
+#define GPIO73_DIR GPIO_DIR_IN
+#define GPIO73_PULLEN GPIO_PULL_ENABLE
+#define GPIO73_PULL GPIO_PULL_DOWN
+#define GPIO73_DATAOUT GPIO_OUT_ZERO
+#define GPIO73_SMT GPIO_SMT_DISABLE
+#define GPIO73_IES GPIO_IES_ENABLE
+/* Configuration for GPIO74 */
+#define GPIO74_MODE GPIO_MODE_01
+#define GPIO74_DIR GPIO_DIR_IN
+#define GPIO74_PULLEN GPIO_PULL_DISABLE
+#define GPIO74_PULL GPIO_PULL_DOWN
+#define GPIO74_DATAOUT GPIO_OUT_ZERO
+#define GPIO74_SMT GPIO_SMT_DISABLE
+#define GPIO74_IES GPIO_IES_ENABLE
+/* Configuration for GPIO75 */
+#define GPIO75_MODE GPIO_MODE_01
+#define GPIO75_DIR GPIO_DIR_IN
+#define GPIO75_PULLEN GPIO_PULL_ENABLE
+#define GPIO75_PULL GPIO_PULL_DOWN
+#define GPIO75_DATAOUT GPIO_OUT_ZERO
+#define GPIO75_SMT GPIO_SMT_DISABLE
+#define GPIO75_IES GPIO_IES_ENABLE
+/* Configuration for GPIO76 */
+#define GPIO76_MODE GPIO_MODE_01
+#define GPIO76_DIR GPIO_DIR_IN
+#define GPIO76_PULLEN GPIO_PULL_DISABLE
+#define GPIO76_PULL GPIO_PULL_DOWN
+#define GPIO76_DATAOUT GPIO_OUT_ZERO
+#define GPIO76_SMT GPIO_SMT_DISABLE
+#define GPIO76_IES GPIO_IES_ENABLE
+/* Configuration for GPIO77 */
+#define GPIO77_MODE GPIO_MODE_01
+#define GPIO77_DIR GPIO_DIR_IN
+#define GPIO77_PULLEN GPIO_PULL_DISABLE
+#define GPIO77_PULL GPIO_PULL_DOWN
+#define GPIO77_DATAOUT GPIO_OUT_ZERO
+#define GPIO77_SMT GPIO_SMT_DISABLE
+#define GPIO77_IES GPIO_IES_ENABLE
+/* Configuration for GPIO78 */
+#define GPIO78_MODE GPIO_MODE_01
+#define GPIO78_DIR GPIO_DIR_IN
+#define GPIO78_PULLEN GPIO_PULL_ENABLE
+#define GPIO78_PULL GPIO_PULL_DOWN
+#define GPIO78_DATAOUT GPIO_OUT_ZERO
+#define GPIO78_SMT GPIO_SMT_DISABLE
+#define GPIO78_IES GPIO_IES_ENABLE
+/* Configuration for GPIO79 */
+#define GPIO79_MODE GPIO_MODE_01
+#define GPIO79_DIR GPIO_DIR_IN
+#define GPIO79_PULLEN GPIO_PULL_DISABLE
+#define GPIO79_PULL GPIO_PULL_DOWN
+#define GPIO79_DATAOUT GPIO_OUT_ZERO
+#define GPIO79_SMT GPIO_SMT_DISABLE
+#define GPIO79_IES GPIO_IES_ENABLE
+/* Configuration for GPIO80 */
+#define GPIO80_MODE GPIO_MODE_01
+#define GPIO80_DIR GPIO_DIR_IN
+#define GPIO80_PULLEN GPIO_PULL_DISABLE
+#define GPIO80_PULL GPIO_PULL_DOWN
+#define GPIO80_DATAOUT GPIO_OUT_ZERO
+#define GPIO80_SMT GPIO_SMT_DISABLE
+#define GPIO80_IES GPIO_IES_ENABLE
+/* Configuration for GPIO81 */
+#define GPIO81_MODE GPIO_MODE_01
+#define GPIO81_DIR GPIO_DIR_IN
+#define GPIO81_PULLEN GPIO_PULL_DISABLE
+#define GPIO81_PULL GPIO_PULL_DOWN
+#define GPIO81_DATAOUT GPIO_OUT_ZERO
+#define GPIO81_SMT GPIO_SMT_DISABLE
+#define GPIO81_IES GPIO_IES_ENABLE
+/* Configuration for GPIO82 */
+#define GPIO82_MODE GPIO_MODE_01
+#define GPIO82_DIR GPIO_DIR_IN
+#define GPIO82_PULLEN GPIO_PULL_DISABLE
+#define GPIO82_PULL GPIO_PULL_DOWN
+#define GPIO82_DATAOUT GPIO_OUT_ZERO
+#define GPIO82_SMT GPIO_SMT_DISABLE
+#define GPIO82_IES GPIO_IES_ENABLE
+/* Configuration for GPIO83 */
+#define GPIO83_MODE GPIO_MODE_01
+#define GPIO83_DIR GPIO_DIR_IN
+#define GPIO83_PULLEN GPIO_PULL_DISABLE
+#define GPIO83_PULL GPIO_PULL_DOWN
+#define GPIO83_DATAOUT GPIO_OUT_ZERO
+#define GPIO83_SMT GPIO_SMT_DISABLE
+#define GPIO83_IES GPIO_IES_ENABLE
+/* Configuration for GPIO84 */
+#define GPIO84_MODE GPIO_MODE_01
+#define GPIO84_DIR GPIO_DIR_IN
+#define GPIO84_PULLEN GPIO_PULL_DISABLE
+#define GPIO84_PULL GPIO_PULL_DOWN
+#define GPIO84_DATAOUT GPIO_OUT_ZERO
+#define GPIO84_SMT GPIO_SMT_DISABLE
+#define GPIO84_IES GPIO_IES_ENABLE
+/* Configuration for GPIO85 */
+#define GPIO85_MODE GPIO_MODE_01
+#define GPIO85_DIR GPIO_DIR_IN
+#define GPIO85_PULLEN GPIO_PULL_DISABLE
+#define GPIO85_PULL GPIO_PULL_DOWN
+#define GPIO85_DATAOUT GPIO_OUT_ZERO
+#define GPIO85_SMT GPIO_SMT_DISABLE
+#define GPIO85_IES GPIO_IES_ENABLE
+/* Configuration for GPIO86 */
+#define GPIO86_MODE GPIO_MODE_01
+#define GPIO86_DIR GPIO_DIR_IN
+#define GPIO86_PULLEN GPIO_PULL_DISABLE
+#define GPIO86_PULL GPIO_PULL_DOWN
+#define GPIO86_DATAOUT GPIO_OUT_ZERO
+#define GPIO86_SMT GPIO_SMT_DISABLE
+#define GPIO86_IES GPIO_IES_ENABLE
+/* Configuration for GPIO87 */
+#define GPIO87_MODE GPIO_MODE_01
+#define GPIO87_DIR GPIO_DIR_IN
+#define GPIO87_PULLEN GPIO_PULL_DISABLE
+#define GPIO87_PULL GPIO_PULL_DOWN
+#define GPIO87_DATAOUT GPIO_OUT_ZERO
+#define GPIO87_SMT GPIO_SMT_DISABLE
+#define GPIO87_IES GPIO_IES_ENABLE
+/* Configuration for GPIO88 */
+#define GPIO88_MODE GPIO_MODE_01
+#define GPIO88_DIR GPIO_DIR_IN
+#define GPIO88_PULLEN GPIO_PULL_DISABLE
+#define GPIO88_PULL GPIO_PULL_DOWN
+#define GPIO88_DATAOUT GPIO_OUT_ZERO
+#define GPIO88_SMT GPIO_SMT_DISABLE
+#define GPIO88_IES GPIO_IES_ENABLE
+/* Configuration for GPIO89 */
+#define GPIO89_MODE GPIO_MODE_02
+#define GPIO89_DIR GPIO_DIR_IN
+#define GPIO89_PULLEN GPIO_PULL_DISABLE
+#define GPIO89_PULL GPIO_PULL_DOWN
+#define GPIO89_DATAOUT GPIO_OUT_ZERO
+#define GPIO89_SMT GPIO_SMT_DISABLE
+#define GPIO89_IES GPIO_IES_ENABLE
+/* Configuration for GPIO90 */
+#define GPIO90_MODE GPIO_MODE_02
+#define GPIO90_DIR GPIO_DIR_IN
+#define GPIO90_PULLEN GPIO_PULL_DISABLE
+#define GPIO90_PULL GPIO_PULL_DOWN
+#define GPIO90_DATAOUT GPIO_OUT_ZERO
+#define GPIO90_SMT GPIO_SMT_DISABLE
+#define GPIO90_IES GPIO_IES_ENABLE
+/* Configuration for GPIO91 */
+#define GPIO91_MODE GPIO_MODE_01
+#define GPIO91_DIR GPIO_DIR_IN
+#define GPIO91_PULLEN GPIO_PULL_DISABLE
+#define GPIO91_PULL GPIO_PULL_DOWN
+#define GPIO91_DATAOUT GPIO_OUT_ZERO
+#define GPIO91_SMT GPIO_SMT_DISABLE
+#define GPIO91_IES GPIO_IES_ENABLE
+/* Configuration for GPIO92 */
+#define GPIO92_MODE GPIO_MODE_01
+#define GPIO92_DIR GPIO_DIR_IN
+#define GPIO92_PULLEN GPIO_PULL_DISABLE
+#define GPIO92_PULL GPIO_PULL_DOWN
+#define GPIO92_DATAOUT GPIO_OUT_ZERO
+#define GPIO92_SMT GPIO_SMT_DISABLE
+#define GPIO92_IES GPIO_IES_ENABLE
+/* Configuration for GPIO10 */
+#define GPIO10_MODE GPIO_MODE_00
+#define GPIO10_DIR GPIO_DIR_IN
+#define GPIO10_PULLEN GPIO_PULL_ENABLE
+#define GPIO10_PULL GPIO_PULL_UP
+#define GPIO10_DATAOUT GPIO_OUT_ZERO
+#define GPIO10_SMT GPIO_SMT_DISABLE
+#define GPIO10_IES GPIO_IES_ENABLE
+/* Configuration for GPIO93 */
+#define GPIO93_MODE GPIO_MODE_00
+#define GPIO93_DIR GPIO_DIR_IN
+#define GPIO93_PULLEN GPIO_PULL_ENABLE
+#define GPIO93_PULL GPIO_PULL_UP
+#define GPIO93_DATAOUT GPIO_OUT_ZERO
+#define GPIO93_SMT GPIO_SMT_DISABLE
+#define GPIO93_IES GPIO_IES_ENABLE
+/* Configuration for GPIO94 */
+#define GPIO94_MODE GPIO_MODE_00
+#define GPIO94_DIR GPIO_DIR_OUT
+#define GPIO94_PULLEN GPIO_PULL_DISABLE
+#define GPIO94_PULL GPIO_PULL_UP
+#define GPIO94_DATAOUT GPIO_OUT_ZERO
+#define GPIO94_SMT GPIO_SMT_DISABLE
+#define GPIO94_IES GPIO_IES_ENABLE
+/* Configuration for GPIO95 */
+#define GPIO95_MODE GPIO_MODE_00
+#define GPIO95_DIR GPIO_DIR_IN
+#define GPIO95_PULLEN GPIO_PULL_ENABLE
+#define GPIO95_PULL GPIO_PULL_UP
+#define GPIO95_DATAOUT GPIO_OUT_ZERO
+#define GPIO95_SMT GPIO_SMT_DISABLE
+#define GPIO95_IES GPIO_IES_ENABLE
+/* Configuration for GPIO96 */
+#define GPIO96_MODE GPIO_MODE_00
+#define GPIO96_DIR GPIO_DIR_IN
+#define GPIO96_PULLEN GPIO_PULL_ENABLE
+#define GPIO96_PULL GPIO_PULL_UP
+#define GPIO96_DATAOUT GPIO_OUT_ZERO
+#define GPIO96_SMT GPIO_SMT_DISABLE
+#define GPIO96_IES GPIO_IES_ENABLE
+/* Configuration for GPIO97 */
+#define GPIO97_MODE GPIO_MODE_01
+#define GPIO97_DIR GPIO_DIR_IN
+#define GPIO97_PULLEN GPIO_PULL_DISABLE
+#define GPIO97_PULL GPIO_PULL_DOWN
+#define GPIO97_DATAOUT GPIO_OUT_ZERO
+#define GPIO97_SMT GPIO_SMT_DISABLE
+#define GPIO97_IES GPIO_IES_ENABLE
+/* Configuration for GPIO98 */
+#define GPIO98_MODE GPIO_MODE_01
+#define GPIO98_DIR GPIO_DIR_IN
+#define GPIO98_PULLEN GPIO_PULL_DISABLE
+#define GPIO98_PULL GPIO_PULL_DOWN
+#define GPIO98_DATAOUT GPIO_OUT_ZERO
+#define GPIO98_SMT GPIO_SMT_DISABLE
+#define GPIO98_IES GPIO_IES_ENABLE
+/* Configuration for GPIO99 */
+#define GPIO99_MODE GPIO_MODE_01
+#define GPIO99_DIR GPIO_DIR_IN
+#define GPIO99_PULLEN GPIO_PULL_DISABLE
+#define GPIO99_PULL GPIO_PULL_DOWN
+#define GPIO99_DATAOUT GPIO_OUT_ZERO
+#define GPIO99_SMT GPIO_SMT_DISABLE
+#define GPIO99_IES GPIO_IES_ENABLE
+/* Configuration for GPIO100 */
+#define GPIO100_MODE GPIO_MODE_01
+#define GPIO100_DIR GPIO_DIR_IN
+#define GPIO100_PULLEN GPIO_PULL_DISABLE
+#define GPIO100_PULL GPIO_PULL_DOWN
+#define GPIO100_DATAOUT GPIO_OUT_ZERO
+#define GPIO100_SMT GPIO_SMT_DISABLE
+#define GPIO100_IES GPIO_IES_ENABLE
+/* Configuration for GPIO101 */
+#define GPIO101_MODE GPIO_MODE_01
+#define GPIO101_DIR GPIO_DIR_OUT
+#define GPIO101_PULLEN GPIO_PULL_DISABLE
+#define GPIO101_PULL GPIO_PULL_DOWN
+#define GPIO101_DATAOUT GPIO_OUT_ZERO
+#define GPIO101_SMT GPIO_SMT_DISABLE
+#define GPIO101_IES GPIO_IES_ENABLE
+/* Configuration for GPIO102 */
+#define GPIO102_MODE GPIO_MODE_01
+#define GPIO102_DIR GPIO_DIR_IN
+#define GPIO102_PULLEN GPIO_PULL_DISABLE
+#define GPIO102_PULL GPIO_PULL_DOWN
+#define GPIO102_DATAOUT GPIO_OUT_ZERO
+#define GPIO102_SMT GPIO_SMT_DISABLE
+#define GPIO102_IES GPIO_IES_ENABLE
+/* Configuration for GPIO103 */
+#define GPIO103_MODE GPIO_MODE_01
+#define GPIO103_DIR GPIO_DIR_IN
+#define GPIO103_PULLEN GPIO_PULL_DISABLE
+#define GPIO103_PULL GPIO_PULL_DOWN
+#define GPIO103_DATAOUT GPIO_OUT_ZERO
+#define GPIO103_SMT GPIO_SMT_DISABLE
+#define GPIO103_IES GPIO_IES_ENABLE
+/* Configuration for GPIO104 */
+#define GPIO104_MODE GPIO_MODE_01
+#define GPIO104_DIR GPIO_DIR_IN
+#define GPIO104_PULLEN GPIO_PULL_DISABLE
+#define GPIO104_PULL GPIO_PULL_DOWN
+#define GPIO104_DATAOUT GPIO_OUT_ZERO
+#define GPIO104_SMT GPIO_SMT_DISABLE
+#define GPIO104_IES GPIO_IES_ENABLE
+/* Configuration for GPIO105 */
+#define GPIO105_MODE GPIO_MODE_01
+#define GPIO105_DIR GPIO_DIR_IN
+#define GPIO105_PULLEN GPIO_PULL_DISABLE
+#define GPIO105_PULL GPIO_PULL_DOWN
+#define GPIO105_DATAOUT GPIO_OUT_ZERO
+#define GPIO105_SMT GPIO_SMT_DISABLE
+#define GPIO105_IES GPIO_IES_ENABLE
+/* Configuration for GPIO106 */
+#define GPIO106_MODE GPIO_MODE_01
+#define GPIO106_DIR GPIO_DIR_IN
+#define GPIO106_PULLEN GPIO_PULL_ENABLE
+#define GPIO106_PULL GPIO_PULL_DOWN
+#define GPIO106_DATAOUT GPIO_OUT_ZERO
+#define GPIO106_SMT GPIO_SMT_DISABLE
+#define GPIO106_IES GPIO_IES_ENABLE
+/* Configuration for GPIO107 */
+#define GPIO107_MODE GPIO_MODE_01
+#define GPIO107_DIR GPIO_DIR_IN
+#define GPIO107_PULLEN GPIO_PULL_DISABLE
+#define GPIO107_PULL GPIO_PULL_DOWN
+#define GPIO107_DATAOUT GPIO_OUT_ZERO
+#define GPIO107_SMT GPIO_SMT_DISABLE
+#define GPIO107_IES GPIO_IES_ENABLE
+/* Configuration for GPIO108 */
+#define GPIO108_MODE GPIO_MODE_01
+#define GPIO108_DIR GPIO_DIR_OUT
+#define GPIO108_PULLEN GPIO_PULL_DISABLE
+#define GPIO108_PULL GPIO_PULL_DOWN
+#define GPIO108_DATAOUT GPIO_OUT_ZERO
+#define GPIO108_SMT GPIO_SMT_DISABLE
+#define GPIO108_IES GPIO_IES_ENABLE
+/* Configuration for GPIO109 */
+#define GPIO109_MODE GPIO_MODE_01
+#define GPIO109_DIR GPIO_DIR_IN
+#define GPIO109_PULLEN GPIO_PULL_ENABLE
+#define GPIO109_PULL GPIO_PULL_DOWN
+#define GPIO109_DATAOUT GPIO_OUT_ZERO
+#define GPIO109_SMT GPIO_SMT_DISABLE
+#define GPIO109_IES GPIO_IES_ENABLE
+/* Configuration for GPIO11 */
+#define GPIO11_MODE GPIO_MODE_00
+#define GPIO11_DIR GPIO_DIR_IN
+#define GPIO11_PULLEN GPIO_PULL_ENABLE
+#define GPIO11_PULL GPIO_PULL_UP
+#define GPIO11_DATAOUT GPIO_OUT_ZERO
+#define GPIO11_SMT GPIO_SMT_DISABLE
+#define GPIO11_IES GPIO_IES_ENABLE
+/* Configuration for GPIO12 */
+#define GPIO12_MODE GPIO_MODE_00
+#define GPIO12_DIR GPIO_DIR_IN
+#define GPIO12_PULLEN GPIO_PULL_ENABLE
+#define GPIO12_PULL GPIO_PULL_DOWN
+#define GPIO12_DATAOUT GPIO_OUT_ZERO
+#define GPIO12_SMT GPIO_SMT_DISABLE
+#define GPIO12_IES GPIO_IES_ENABLE
+/* Configuration for GPIO110 */
+#define GPIO110_MODE GPIO_MODE_01
+#define GPIO110_DIR GPIO_DIR_IN
+#define GPIO110_PULLEN GPIO_PULL_DISABLE
+#define GPIO110_PULL GPIO_PULL_DOWN
+#define GPIO110_DATAOUT GPIO_OUT_ZERO
+#define GPIO110_SMT GPIO_SMT_DISABLE
+#define GPIO110_IES GPIO_IES_ENABLE
+/* Configuration for GPIO111 */
+#define GPIO111_MODE GPIO_MODE_01
+#define GPIO111_DIR GPIO_DIR_OUT
+#define GPIO111_PULLEN GPIO_PULL_DISABLE
+#define GPIO111_PULL GPIO_PULL_DOWN
+#define GPIO111_DATAOUT GPIO_OUT_ZERO
+#define GPIO111_SMT GPIO_SMT_DISABLE
+#define GPIO111_IES GPIO_IES_ENABLE
+/* Configuration for GPIO112 */
+#define GPIO112_MODE GPIO_MODE_01
+#define GPIO112_DIR GPIO_DIR_OUT
+#define GPIO112_PULLEN GPIO_PULL_DISABLE
+#define GPIO112_PULL GPIO_PULL_DOWN
+#define GPIO112_DATAOUT GPIO_OUT_ZERO
+#define GPIO112_SMT GPIO_SMT_DISABLE
+#define GPIO112_IES GPIO_IES_ENABLE
+/* Configuration for GPIO113 */
+#define GPIO113_MODE GPIO_MODE_01
+#define GPIO113_DIR GPIO_DIR_IN
+#define GPIO113_PULLEN GPIO_PULL_DISABLE
+#define GPIO113_PULL GPIO_PULL_DOWN
+#define GPIO113_DATAOUT GPIO_OUT_ZERO
+#define GPIO113_SMT GPIO_SMT_DISABLE
+#define GPIO113_IES GPIO_IES_ENABLE
+/* Configuration for GPIO114 */
+#define GPIO114_MODE GPIO_MODE_01
+#define GPIO114_DIR GPIO_DIR_OUT
+#define GPIO114_PULLEN GPIO_PULL_DISABLE
+#define GPIO114_PULL GPIO_PULL_DOWN
+#define GPIO114_DATAOUT GPIO_OUT_ZERO
+#define GPIO114_SMT GPIO_SMT_DISABLE
+#define GPIO114_IES GPIO_IES_ENABLE
+/* Configuration for GPIO115 */
+#define GPIO115_MODE GPIO_MODE_01
+#define GPIO115_DIR GPIO_DIR_OUT
+#define GPIO115_PULLEN GPIO_PULL_DISABLE
+#define GPIO115_PULL GPIO_PULL_DOWN
+#define GPIO115_DATAOUT GPIO_OUT_ZERO
+#define GPIO115_SMT GPIO_SMT_DISABLE
+#define GPIO115_IES GPIO_IES_ENABLE
+/* Configuration for GPIO146 */
+#define GPIO146_MODE GPIO_MODE_00
+#define GPIO146_DIR GPIO_DIR_IN
+#define GPIO146_PULLEN GPIO_PULL_ENABLE
+#define GPIO146_PULL GPIO_PULL_DOWN
+#define GPIO146_DATAOUT GPIO_OUT_ZERO
+#define GPIO146_SMT GPIO_SMT_DISABLE
+#define GPIO146_IES GPIO_IES_ENABLE
+/* Configuration for GPIO116 */
+#define GPIO116_MODE GPIO_MODE_01
+#define GPIO116_DIR GPIO_DIR_IN
+#define GPIO116_PULLEN GPIO_PULL_DISABLE
+#define GPIO116_PULL GPIO_PULL_DOWN
+#define GPIO116_DATAOUT GPIO_OUT_ZERO
+#define GPIO116_SMT GPIO_SMT_DISABLE
+#define GPIO116_IES GPIO_IES_ENABLE
+/* Configuration for GPIO117 */
+#define GPIO117_MODE GPIO_MODE_01
+#define GPIO117_DIR GPIO_DIR_IN
+#define GPIO117_PULLEN GPIO_PULL_DISABLE
+#define GPIO117_PULL GPIO_PULL_DOWN
+#define GPIO117_DATAOUT GPIO_OUT_ZERO
+#define GPIO117_SMT GPIO_SMT_DISABLE
+#define GPIO117_IES GPIO_IES_ENABLE
+/* Configuration for GPIO118 */
+#define GPIO118_MODE GPIO_MODE_01
+#define GPIO118_DIR GPIO_DIR_IN
+#define GPIO118_PULLEN GPIO_PULL_DISABLE
+#define GPIO118_PULL GPIO_PULL_DOWN
+#define GPIO118_DATAOUT GPIO_OUT_ZERO
+#define GPIO118_SMT GPIO_SMT_DISABLE
+#define GPIO118_IES GPIO_IES_ENABLE
+/* Configuration for GPIO119 */
+#define GPIO119_MODE GPIO_MODE_01
+#define GPIO119_DIR GPIO_DIR_IN
+#define GPIO119_PULLEN GPIO_PULL_DISABLE
+#define GPIO119_PULL GPIO_PULL_DOWN
+#define GPIO119_DATAOUT GPIO_OUT_ZERO
+#define GPIO119_SMT GPIO_SMT_DISABLE
+#define GPIO119_IES GPIO_IES_ENABLE
+/* Configuration for GPIO120 */
+#define GPIO120_MODE GPIO_MODE_01
+#define GPIO120_DIR GPIO_DIR_IN
+#define GPIO120_PULLEN GPIO_PULL_DISABLE
+#define GPIO120_PULL GPIO_PULL_DOWN
+#define GPIO120_DATAOUT GPIO_OUT_ZERO
+#define GPIO120_SMT GPIO_SMT_DISABLE
+#define GPIO120_IES GPIO_IES_ENABLE
+/* Configuration for GPIO121 */
+#define GPIO121_MODE GPIO_MODE_01
+#define GPIO121_DIR GPIO_DIR_IN
+#define GPIO121_PULLEN GPIO_PULL_DISABLE
+#define GPIO121_PULL GPIO_PULL_DOWN
+#define GPIO121_DATAOUT GPIO_OUT_ZERO
+#define GPIO121_SMT GPIO_SMT_DISABLE
+#define GPIO121_IES GPIO_IES_ENABLE
+/* Configuration for GPIO122 */
+#define GPIO122_MODE GPIO_MODE_01
+#define GPIO122_DIR GPIO_DIR_IN
+#define GPIO122_PULLEN GPIO_PULL_DISABLE
+#define GPIO122_PULL GPIO_PULL_DOWN
+#define GPIO122_DATAOUT GPIO_OUT_ZERO
+#define GPIO122_SMT GPIO_SMT_DISABLE
+#define GPIO122_IES GPIO_IES_ENABLE
+/* Configuration for GPIO123 */
+#define GPIO123_MODE GPIO_MODE_01
+#define GPIO123_DIR GPIO_DIR_IN
+#define GPIO123_PULLEN GPIO_PULL_DISABLE
+#define GPIO123_PULL GPIO_PULL_DOWN
+#define GPIO123_DATAOUT GPIO_OUT_ZERO
+#define GPIO123_SMT GPIO_SMT_DISABLE
+#define GPIO123_IES GPIO_IES_ENABLE
+/* Configuration for GPIO124 */
+#define GPIO124_MODE GPIO_MODE_01
+#define GPIO124_DIR GPIO_DIR_IN
+#define GPIO124_PULLEN GPIO_PULL_DISABLE
+#define GPIO124_PULL GPIO_PULL_DOWN
+#define GPIO124_DATAOUT GPIO_OUT_ZERO
+#define GPIO124_SMT GPIO_SMT_DISABLE
+#define GPIO124_IES GPIO_IES_ENABLE
+/* Configuration for GPIO125 */
+#define GPIO125_MODE GPIO_MODE_01
+#define GPIO125_DIR GPIO_DIR_IN
+#define GPIO125_PULLEN GPIO_PULL_DISABLE
+#define GPIO125_PULL GPIO_PULL_DOWN
+#define GPIO125_DATAOUT GPIO_OUT_ZERO
+#define GPIO125_SMT GPIO_SMT_DISABLE
+#define GPIO125_IES GPIO_IES_ENABLE
+/* Configuration for GPIO126 */
+#define GPIO126_MODE GPIO_MODE_01
+#define GPIO126_DIR GPIO_DIR_IN
+#define GPIO126_PULLEN GPIO_PULL_DISABLE
+#define GPIO126_PULL GPIO_PULL_DOWN
+#define GPIO126_DATAOUT GPIO_OUT_ZERO
+#define GPIO126_SMT GPIO_SMT_DISABLE
+#define GPIO126_IES GPIO_IES_ENABLE
+/* Configuration for GPIO127 */
+#define GPIO127_MODE GPIO_MODE_01
+#define GPIO127_DIR GPIO_DIR_IN
+#define GPIO127_PULLEN GPIO_PULL_DISABLE
+#define GPIO127_PULL GPIO_PULL_DOWN
+#define GPIO127_DATAOUT GPIO_OUT_ZERO
+#define GPIO127_SMT GPIO_SMT_DISABLE
+#define GPIO127_IES GPIO_IES_ENABLE
+/* Configuration for GPIO128 */
+#define GPIO128_MODE GPIO_MODE_01
+#define GPIO128_DIR GPIO_DIR_IN
+#define GPIO128_PULLEN GPIO_PULL_DISABLE
+#define GPIO128_PULL GPIO_PULL_DOWN
+#define GPIO128_DATAOUT GPIO_OUT_ZERO
+#define GPIO128_SMT GPIO_SMT_DISABLE
+#define GPIO128_IES GPIO_IES_ENABLE
+/* Configuration for GPIO129 */
+#define GPIO129_MODE GPIO_MODE_01
+#define GPIO129_DIR GPIO_DIR_IN
+#define GPIO129_PULLEN GPIO_PULL_DISABLE
+#define GPIO129_PULL GPIO_PULL_DOWN
+#define GPIO129_DATAOUT GPIO_OUT_ZERO
+#define GPIO129_SMT GPIO_SMT_DISABLE
+#define GPIO129_IES GPIO_IES_ENABLE
+/* Configuration for GPIO130 */
+#define GPIO130_MODE GPIO_MODE_00
+#define GPIO130_DIR GPIO_DIR_IN
+#define GPIO130_PULLEN GPIO_PULL_ENABLE
+#define GPIO130_PULL GPIO_PULL_DOWN
+#define GPIO130_DATAOUT GPIO_OUT_ZERO
+#define GPIO130_SMT GPIO_SMT_DISABLE
+#define GPIO130_IES GPIO_IES_ENABLE
+/* Configuration for GPIO131 */
+#define GPIO131_MODE GPIO_MODE_00
+#define GPIO131_DIR GPIO_DIR_IN
+#define GPIO131_PULLEN GPIO_PULL_ENABLE
+#define GPIO131_PULL GPIO_PULL_DOWN
+#define GPIO131_DATAOUT GPIO_OUT_ZERO
+#define GPIO131_SMT GPIO_SMT_DISABLE
+#define GPIO131_IES GPIO_IES_ENABLE
+/* Configuration for GPIO132 */
+#define GPIO132_MODE GPIO_MODE_01
+#define GPIO132_DIR GPIO_DIR_IN
+#define GPIO132_PULLEN GPIO_PULL_DISABLE
+#define GPIO132_PULL GPIO_PULL_DOWN
+#define GPIO132_DATAOUT GPIO_OUT_ZERO
+#define GPIO132_SMT GPIO_SMT_DISABLE
+#define GPIO132_IES GPIO_IES_ENABLE
+/* Configuration for GPIO133 */
+#define GPIO133_MODE GPIO_MODE_00
+#define GPIO133_DIR GPIO_DIR_IN
+#define GPIO133_PULLEN GPIO_PULL_ENABLE
+#define GPIO133_PULL GPIO_PULL_DOWN
+#define GPIO133_DATAOUT GPIO_OUT_ZERO
+#define GPIO133_SMT GPIO_SMT_DISABLE
+#define GPIO133_IES GPIO_IES_ENABLE
+/* Configuration for GPIO134 */
+#define GPIO134_MODE GPIO_MODE_01
+#define GPIO134_DIR GPIO_DIR_IN
+#define GPIO134_PULLEN GPIO_PULL_DISABLE
+#define GPIO134_PULL GPIO_PULL_DOWN
+#define GPIO134_DATAOUT GPIO_OUT_ZERO
+#define GPIO134_SMT GPIO_SMT_DISABLE
+#define GPIO134_IES GPIO_IES_ENABLE
+/* Configuration for GPIO135 */
+#define GPIO135_MODE GPIO_MODE_01
+#define GPIO135_DIR GPIO_DIR_IN
+#define GPIO135_PULLEN GPIO_PULL_DISABLE
+#define GPIO135_PULL GPIO_PULL_DOWN
+#define GPIO135_DATAOUT GPIO_OUT_ZERO
+#define GPIO135_SMT GPIO_SMT_DISABLE
+#define GPIO135_IES GPIO_IES_ENABLE
+/* Configuration for GPIO136 */
+#define GPIO136_MODE GPIO_MODE_01
+#define GPIO136_DIR GPIO_DIR_IN
+#define GPIO136_PULLEN GPIO_PULL_DISABLE
+#define GPIO136_PULL GPIO_PULL_DOWN
+#define GPIO136_DATAOUT GPIO_OUT_ZERO
+#define GPIO136_SMT GPIO_SMT_DISABLE
+#define GPIO136_IES GPIO_IES_ENABLE
+/* Configuration for GPIO137 */
+#define GPIO137_MODE GPIO_MODE_01
+#define GPIO137_DIR GPIO_DIR_IN
+#define GPIO137_PULLEN GPIO_PULL_DISABLE
+#define GPIO137_PULL GPIO_PULL_DOWN
+#define GPIO137_DATAOUT GPIO_OUT_ZERO
+#define GPIO137_SMT GPIO_SMT_DISABLE
+#define GPIO137_IES GPIO_IES_ENABLE
+/* Configuration for GPIO138 */
+#define GPIO138_MODE GPIO_MODE_01
+#define GPIO138_DIR GPIO_DIR_IN
+#define GPIO138_PULLEN GPIO_PULL_DISABLE
+#define GPIO138_PULL GPIO_PULL_DOWN
+#define GPIO138_DATAOUT GPIO_OUT_ZERO
+#define GPIO138_SMT GPIO_SMT_DISABLE
+#define GPIO138_IES GPIO_IES_ENABLE
+/* Configuration for GPIO139 */
+#define GPIO139_MODE GPIO_MODE_01
+#define GPIO139_DIR GPIO_DIR_IN
+#define GPIO139_PULLEN GPIO_PULL_DISABLE
+#define GPIO139_PULL GPIO_PULL_DOWN
+#define GPIO139_DATAOUT GPIO_OUT_ZERO
+#define GPIO139_SMT GPIO_SMT_DISABLE
+#define GPIO139_IES GPIO_IES_ENABLE
+/* Configuration for GPIO140 */
+#define GPIO140_MODE GPIO_MODE_01
+#define GPIO140_DIR GPIO_DIR_IN
+#define GPIO140_PULLEN GPIO_PULL_DISABLE
+#define GPIO140_PULL GPIO_PULL_DOWN
+#define GPIO140_DATAOUT GPIO_OUT_ZERO
+#define GPIO140_SMT GPIO_SMT_DISABLE
+#define GPIO140_IES GPIO_IES_ENABLE
+/* Configuration for GPIO141 */
+#define GPIO141_MODE GPIO_MODE_01
+#define GPIO141_DIR GPIO_DIR_IN
+#define GPIO141_PULLEN GPIO_PULL_DISABLE
+#define GPIO141_PULL GPIO_PULL_DOWN
+#define GPIO141_DATAOUT GPIO_OUT_ZERO
+#define GPIO141_SMT GPIO_SMT_DISABLE
+#define GPIO141_IES GPIO_IES_ENABLE
+/* Configuration for GPIO142 */
+#define GPIO142_MODE GPIO_MODE_01
+#define GPIO142_DIR GPIO_DIR_IN
+#define GPIO142_PULLEN GPIO_PULL_DISABLE
+#define GPIO142_PULL GPIO_PULL_DOWN
+#define GPIO142_DATAOUT GPIO_OUT_ZERO
+#define GPIO142_SMT GPIO_SMT_DISABLE
+#define GPIO142_IES GPIO_IES_ENABLE
+/* Configuration for GPIO143 */
+#define GPIO143_MODE GPIO_MODE_01
+#define GPIO143_DIR GPIO_DIR_IN
+#define GPIO143_PULLEN GPIO_PULL_DISABLE
+#define GPIO143_PULL GPIO_PULL_DOWN
+#define GPIO143_DATAOUT GPIO_OUT_ZERO
+#define GPIO143_SMT GPIO_SMT_DISABLE
+#define GPIO143_IES GPIO_IES_ENABLE
+/* Configuration for GPIO144 */
+#define GPIO144_MODE GPIO_MODE_01
+#define GPIO144_DIR GPIO_DIR_IN
+#define GPIO144_PULLEN GPIO_PULL_DISABLE
+#define GPIO144_PULL GPIO_PULL_DOWN
+#define GPIO144_DATAOUT GPIO_OUT_ZERO
+#define GPIO144_SMT GPIO_SMT_DISABLE
+#define GPIO144_IES GPIO_IES_ENABLE
+/* Configuration for GPIO145 */
+#define GPIO145_MODE GPIO_MODE_01
+#define GPIO145_DIR GPIO_DIR_IN
+#define GPIO145_PULLEN GPIO_PULL_DISABLE
+#define GPIO145_PULL GPIO_PULL_DOWN
+#define GPIO145_DATAOUT GPIO_OUT_ZERO
+#define GPIO145_SMT GPIO_SMT_DISABLE
+#define GPIO145_IES GPIO_IES_ENABLE
+/* Configuration for GPIO147 */
+#define GPIO147_MODE GPIO_MODE_01
+#define GPIO147_DIR GPIO_DIR_IN
+#define GPIO147_PULLEN GPIO_PULL_DISABLE
+#define GPIO147_PULL GPIO_PULL_DOWN
+#define GPIO147_DATAOUT GPIO_OUT_ZERO
+#define GPIO147_SMT GPIO_SMT_ENABLE
+#define GPIO147_IES GPIO_IES_ENABLE
+/* Configuration for GPIO148 */
+#define GPIO148_MODE GPIO_MODE_01
+#define GPIO148_DIR GPIO_DIR_IN
+#define GPIO148_PULLEN GPIO_PULL_DISABLE
+#define GPIO148_PULL GPIO_PULL_DOWN
+#define GPIO148_DATAOUT GPIO_OUT_ZERO
+#define GPIO148_SMT GPIO_SMT_ENABLE
+#define GPIO148_IES GPIO_IES_ENABLE
+/* Configuration for GPIO149 */
+#define GPIO149_MODE GPIO_MODE_01
+#define GPIO149_DIR GPIO_DIR_IN
+#define GPIO149_PULLEN GPIO_PULL_DISABLE
+#define GPIO149_PULL GPIO_PULL_DOWN
+#define GPIO149_DATAOUT GPIO_OUT_ZERO
+#define GPIO149_SMT GPIO_SMT_ENABLE
+#define GPIO149_IES GPIO_IES_ENABLE
+/* Configuration for GPIO150 */
+#define GPIO150_MODE GPIO_MODE_01
+#define GPIO150_DIR GPIO_DIR_IN
+#define GPIO150_PULLEN GPIO_PULL_DISABLE
+#define GPIO150_PULL GPIO_PULL_DOWN
+#define GPIO150_DATAOUT GPIO_OUT_ZERO
+#define GPIO150_SMT GPIO_SMT_ENABLE
+#define GPIO150_IES GPIO_IES_ENABLE
+/* Configuration for GPIO151 */
+#define GPIO151_MODE GPIO_MODE_01
+#define GPIO151_DIR GPIO_DIR_IN
+#define GPIO151_PULLEN GPIO_PULL_DISABLE
+#define GPIO151_PULL GPIO_PULL_DOWN
+#define GPIO151_DATAOUT GPIO_OUT_ZERO
+#define GPIO151_SMT GPIO_SMT_ENABLE
+#define GPIO151_IES GPIO_IES_ENABLE
+/* Configuration for GPIO152 */
+#define GPIO152_MODE GPIO_MODE_01
+#define GPIO152_DIR GPIO_DIR_IN
+#define GPIO152_PULLEN GPIO_PULL_DISABLE
+#define GPIO152_PULL GPIO_PULL_DOWN
+#define GPIO152_DATAOUT GPIO_OUT_ZERO
+#define GPIO152_SMT GPIO_SMT_ENABLE
+#define GPIO152_IES GPIO_IES_ENABLE
+/* Configuration for GPIO153 */
+#define GPIO153_MODE GPIO_MODE_01
+#define GPIO153_DIR GPIO_DIR_IN
+#define GPIO153_PULLEN GPIO_PULL_DISABLE
+#define GPIO153_PULL GPIO_PULL_DOWN
+#define GPIO153_DATAOUT GPIO_OUT_ZERO
+#define GPIO153_SMT GPIO_SMT_ENABLE
+#define GPIO153_IES GPIO_IES_ENABLE
+/* Configuration for GPIO154 */
+#define GPIO154_MODE GPIO_MODE_01
+#define GPIO154_DIR GPIO_DIR_IN
+#define GPIO154_PULLEN GPIO_PULL_DISABLE
+#define GPIO154_PULL GPIO_PULL_DOWN
+#define GPIO154_DATAOUT GPIO_OUT_ZERO
+#define GPIO154_SMT GPIO_SMT_ENABLE
+#define GPIO154_IES GPIO_IES_ENABLE
+/* Configuration for GPIO155 */
+#define GPIO155_MODE GPIO_MODE_01
+#define GPIO155_DIR GPIO_DIR_IN
+#define GPIO155_PULLEN GPIO_PULL_DISABLE
+#define GPIO155_PULL GPIO_PULL_DOWN
+#define GPIO155_DATAOUT GPIO_OUT_ZERO
+#define GPIO155_SMT GPIO_SMT_ENABLE
+#define GPIO155_IES GPIO_IES_ENABLE
+/* Configuration for GPIO156 */
+#define GPIO156_MODE GPIO_MODE_01
+#define GPIO156_DIR GPIO_DIR_IN
+#define GPIO156_PULLEN GPIO_PULL_DISABLE
+#define GPIO156_PULL GPIO_PULL_DOWN
+#define GPIO156_DATAOUT GPIO_OUT_ZERO
+#define GPIO156_SMT GPIO_SMT_ENABLE
+#define GPIO156_IES GPIO_IES_ENABLE
+/* Configuration for GPIO157 */
+#define GPIO157_MODE GPIO_MODE_01
+#define GPIO157_DIR GPIO_DIR_IN
+#define GPIO157_PULLEN GPIO_PULL_ENABLE
+#define GPIO157_PULL GPIO_PULL_UP
+#define GPIO157_DATAOUT GPIO_OUT_ZERO
+#define GPIO157_SMT GPIO_SMT_ENABLE
+#define GPIO157_IES GPIO_IES_ENABLE
+/* Configuration for GPIO158 */
+#define GPIO158_MODE GPIO_MODE_01
+#define GPIO158_DIR GPIO_DIR_IN
+#define GPIO158_PULLEN GPIO_PULL_ENABLE
+#define GPIO158_PULL GPIO_PULL_UP
+#define GPIO158_DATAOUT GPIO_OUT_ZERO
+#define GPIO158_SMT GPIO_SMT_ENABLE
+#define GPIO158_IES GPIO_IES_ENABLE
+/* Configuration for GPIO159 */
+#define GPIO159_MODE GPIO_MODE_01
+#define GPIO159_DIR GPIO_DIR_IN
+#define GPIO159_PULLEN GPIO_PULL_ENABLE
+#define GPIO159_PULL GPIO_PULL_UP
+#define GPIO159_DATAOUT GPIO_OUT_ZERO
+#define GPIO159_SMT GPIO_SMT_ENABLE
+#define GPIO159_IES GPIO_IES_ENABLE
+/* Configuration for GPIO160 */
+#define GPIO160_MODE GPIO_MODE_01
+#define GPIO160_DIR GPIO_DIR_IN
+#define GPIO160_PULLEN GPIO_PULL_ENABLE
+#define GPIO160_PULL GPIO_PULL_UP
+#define GPIO160_DATAOUT GPIO_OUT_ZERO
+#define GPIO160_SMT GPIO_SMT_ENABLE
+#define GPIO160_IES GPIO_IES_ENABLE
+/* Configuration for GPIO44 */
+#define GPIO44_MODE GPIO_MODE_00
+#define GPIO44_DIR GPIO_DIR_IN
+#define GPIO44_PULLEN GPIO_PULL_ENABLE
+#define GPIO44_PULL GPIO_PULL_UP
+#define GPIO44_DATAOUT GPIO_OUT_ZERO
+#define GPIO44_SMT GPIO_SMT_DISABLE
+#define GPIO44_IES GPIO_IES_ENABLE
+/* Configuration for GPIO45 */
+#define GPIO45_MODE GPIO_MODE_00
+#define GPIO45_DIR GPIO_DIR_IN
+#define GPIO45_PULLEN GPIO_PULL_ENABLE
+#define GPIO45_PULL GPIO_PULL_UP
+#define GPIO45_DATAOUT GPIO_OUT_ZERO
+#define GPIO45_SMT GPIO_SMT_DISABLE
+#define GPIO45_IES GPIO_IES_ENABLE
+/* Configuration for GPIO46 */
+#define GPIO46_MODE GPIO_MODE_00
+#define GPIO46_DIR GPIO_DIR_IN
+#define GPIO46_PULLEN GPIO_PULL_ENABLE
+#define GPIO46_PULL GPIO_PULL_UP
+#define GPIO46_DATAOUT GPIO_OUT_ZERO
+#define GPIO46_SMT GPIO_SMT_DISABLE
+#define GPIO46_IES GPIO_IES_ENABLE
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/dcm.h b/src/bsp/lk/platform/mt2731/include/platform/dcm.h
new file mode 100644
index 0000000..b0343d0
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/dcm.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef DCM_H
+#define DCM_H
+
+void mt_dcm_init(void);
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/emi_hw.h b/src/bsp/lk/platform/mt2731/include/platform/emi_hw.h
new file mode 100644
index 0000000..3a1f57c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/emi_hw.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __EMI_HW_H__
+#define __EMI_HW_H__
+
+#define EMI_BASE (0x10219000)
+#define EMI_MPU_BASE (0x10226000)
+#define CHN0_EMI_BASE (0x10235000)
+#define CHN1_EMI_BASE (0x10245000)
+
+typedef volatile unsigned int * P_U32;
+#define EMI_CONA ((P_U32)(EMI_BASE+0x000))
+#define EMI_CONB ((P_U32)(EMI_BASE+0x008))
+#define EMI_CONC ((P_U32)(EMI_BASE+0x010))
+#define EMI_COND ((P_U32)(EMI_BASE+0x018))
+#define EMI_CONE ((P_U32)(EMI_BASE+0x020))
+#define EMI_CONF ((P_U32)(EMI_BASE+0x028))
+#define EMI_CONG ((P_U32)(EMI_BASE+0x030))
+#define EMI_CONH ((P_U32)(EMI_BASE+0x038))
+#define EMI_CONH_2ND ((P_U32)(EMI_BASE+0x03C))
+#define EMI_CONI ((P_U32)(EMI_BASE+0x040))
+#define EMI_CONJ ((P_U32)(EMI_BASE+0x048))
+#define EMI_CONM ((P_U32)(EMI_BASE+0x060))
+#define EMI_CONN ((P_U32)(EMI_BASE+0x068))
+#define EMI_CONO ((P_U32)(EMI_BASE+0x070))
+#define EMI_MDCT ((P_U32)(EMI_BASE+0x078))
+#define EMI_MDCT_2ND ((P_U32)(EMI_BASE+0x07C))
+#define EMI_IOCL ((P_U32)(EMI_BASE+0x0D0))
+#define EMI_IOCL_2ND ((P_U32)(EMI_BASE+0x0D4))
+#define EMI_IOCM ((P_U32)(EMI_BASE+0x0D8))
+#define EMI_IOCM_2ND ((P_U32)(EMI_BASE+0x0DC))
+#define EMI_TESTB ((P_U32)(EMI_BASE+0x0E8))
+#define EMI_TESTC ((P_U32)(EMI_BASE+0x0F0))
+#define EMI_TESTD ((P_U32)(EMI_BASE+0x0F8))
+#define EMI_ARBA ((P_U32)(EMI_BASE+0x100))
+#define EMI_ARBB ((P_U32)(EMI_BASE+0x108))
+#define EMI_ARBC ((P_U32)(EMI_BASE+0x110))
+#define EMI_ARBD ((P_U32)(EMI_BASE+0x118))
+#define EMI_ARBE ((P_U32)(EMI_BASE+0x120))
+#define EMI_ARBF ((P_U32)(EMI_BASE+0x128))
+#define EMI_ARBG ((P_U32)(EMI_BASE+0x130))
+#define EMI_ARBH ((P_U32)(EMI_BASE+0x138))
+#define EMI_ARBI ((P_U32)(EMI_BASE+0x140))
+#define EMI_ARBI_2ND ((P_U32)(EMI_BASE+0x144))
+#define EMI_ARBK ((P_U32)(EMI_BASE+0x150))
+#define EMI_ARBK_2ND ((P_U32)(EMI_BASE+0x154))
+#define EMI_SLCT ((P_U32)(EMI_BASE+0x158))
+#define EMI_MPUD0_ST ((P_U32)(EMI_BASE+0x160))
+#define EMI_MPUD1_ST ((P_U32)(EMI_BASE+0x164))
+#define EMI_MPUD2_ST ((P_U32)(EMI_BASE+0x168))
+#define EMI_MPUD3_ST ((P_U32)(EMI_BASE+0x16C))
+#define EMI_MPUD4_ST ((P_U32)(EMI_BASE+0x170))
+#define EMI_MPUD5_ST ((P_U32)(EMI_BASE+0x174))
+#define EMI_MPUD6_ST ((P_U32)(EMI_BASE+0x178))
+#define EMI_MPUD7_ST ((P_U32)(EMI_BASE+0x17C))
+#define EMI_MPUD8_ST ((P_U32)(EMI_BASE+0x180))
+#define EMI_MPUD9_ST ((P_U32)(EMI_BASE+0x184))
+#define EMI_MPUD10_ST ((P_U32)(EMI_BASE+0x188))
+#define EMI_MPUD11_ST ((P_U32)(EMI_BASE+0x18C))
+#define EMI_MPUD12_ST ((P_U32)(EMI_BASE+0x190))
+#define EMI_MPUD13_ST ((P_U32)(EMI_BASE+0x194))
+#define EMI_MPUD14_ST ((P_U32)(EMI_BASE+0x198))
+#define EMI_MPUD15_ST ((P_U32)(EMI_BASE+0x19C))
+#define EMI_MPUD16_ST ((P_U32)(EMI_BASE+0x1A0))
+#define EMI_MPUD17_ST ((P_U32)(EMI_BASE+0x1A4))
+#define EMI_MPUD18_ST ((P_U32)(EMI_BASE+0x1A8))
+#define EMI_MPUD19_ST ((P_U32)(EMI_BASE+0x1AC))
+#define EMI_MPUD20_ST ((P_U32)(EMI_BASE+0x1B0))
+#define EMI_MPUD21_ST ((P_U32)(EMI_BASE+0x1B4))
+#define EMI_MPUD22_ST ((P_U32)(EMI_BASE+0x1B8))
+#define EMI_MPUD23_ST ((P_U32)(EMI_BASE+0x1BC))
+#define EMI_MPUD24_ST ((P_U32)(EMI_BASE+0x1C0))
+#define EMI_MPUD25_ST ((P_U32)(EMI_BASE+0x1C4))
+#define EMI_MPUD26_ST ((P_U32)(EMI_BASE+0x1C8))
+#define EMI_MPUD27_ST ((P_U32)(EMI_BASE+0x1CC))
+#define EMI_MPUD28_ST ((P_U32)(EMI_BASE+0x1D0))
+#define EMI_MPUD29_ST ((P_U32)(EMI_BASE+0x1D4))
+#define EMI_MPUD30_ST ((P_U32)(EMI_BASE+0x1D8))
+#define EMI_MPUD31_ST ((P_U32)(EMI_BASE+0x1DC))
+#define EMI_MPUS ((P_U32)(EMI_BASE+0x1F0))
+#define EMI_MPUT ((P_U32)(EMI_BASE+0x1F8))
+#define EMI_MPUT_2ND ((P_U32)(EMI_BASE+0x1FC))
+#define EMI_D0_ST2 ((P_U32)(EMI_BASE+0x200))
+#define EMI_D1_ST2 ((P_U32)(EMI_BASE+0x204))
+#define EMI_D2_ST2 ((P_U32)(EMI_BASE+0x208))
+#define EMI_D3_ST2 ((P_U32)(EMI_BASE+0x20C))
+#define EMI_D4_ST2 ((P_U32)(EMI_BASE+0x210))
+#define EMI_D5_ST2 ((P_U32)(EMI_BASE+0x214))
+#define EMI_D6_ST2 ((P_U32)(EMI_BASE+0x218))
+#define EMI_D7_ST2 ((P_U32)(EMI_BASE+0x21C))
+#define EMI_D8_ST2 ((P_U32)(EMI_BASE+0x220))
+#define EMI_D9_ST2 ((P_U32)(EMI_BASE+0x224))
+#define EMI_D10_ST2 ((P_U32)(EMI_BASE+0x228))
+#define EMI_D11_ST2 ((P_U32)(EMI_BASE+0x22C))
+#define EMI_D12_ST2 ((P_U32)(EMI_BASE+0x230))
+#define EMI_D13_ST2 ((P_U32)(EMI_BASE+0x234))
+#define EMI_D14_ST2 ((P_U32)(EMI_BASE+0x238))
+#define EMI_D15_ST2 ((P_U32)(EMI_BASE+0x23C))
+#define EMI_D16_ST2 ((P_U32)(EMI_BASE+0x240))
+#define EMI_D17_ST2 ((P_U32)(EMI_BASE+0x244))
+#define EMI_D18_ST2 ((P_U32)(EMI_BASE+0x248))
+#define EMI_D19_ST2 ((P_U32)(EMI_BASE+0x24C))
+#define EMI_D20_ST2 ((P_U32)(EMI_BASE+0x250))
+#define EMI_D21_ST2 ((P_U32)(EMI_BASE+0x254))
+#define EMI_D22_ST2 ((P_U32)(EMI_BASE+0x258))
+#define EMI_D23_ST2 ((P_U32)(EMI_BASE+0x25C))
+#define EMI_D24_ST2 ((P_U32)(EMI_BASE+0x260))
+#define EMI_D25_ST2 ((P_U32)(EMI_BASE+0x264))
+#define EMI_D26_ST2 ((P_U32)(EMI_BASE+0x268))
+#define EMI_D27_ST2 ((P_U32)(EMI_BASE+0x26C))
+#define EMI_D28_ST2 ((P_U32)(EMI_BASE+0x270))
+#define EMI_D29_ST2 ((P_U32)(EMI_BASE+0x274))
+#define EMI_D30_ST2 ((P_U32)(EMI_BASE+0x278))
+#define EMI_D31_ST2 ((P_U32)(EMI_BASE+0x27C))
+#define EMI_BMEN ((P_U32)(EMI_BASE+0x400))
+#define EMI_BSTP ((P_U32)(EMI_BASE+0x404))
+#define EMI_BCNT ((P_U32)(EMI_BASE+0x408))
+#define EMI_TACT ((P_U32)(EMI_BASE+0x410))
+#define EMI_TSCT ((P_U32)(EMI_BASE+0x418))
+#define EMI_WACT ((P_U32)(EMI_BASE+0x420))
+#define EMI_WSCT ((P_U32)(EMI_BASE+0x428))
+#define EMI_BACT ((P_U32)(EMI_BASE+0x430))
+#define EMI_BSCT ((P_U32)(EMI_BASE+0x438))
+#define EMI_MSEL ((P_U32)(EMI_BASE+0x440))
+#define EMI_TSCT2 ((P_U32)(EMI_BASE+0x448))
+#define EMI_TSCT3 ((P_U32)(EMI_BASE+0x450))
+#define EMI_WSCT2 ((P_U32)(EMI_BASE+0x458))
+#define EMI_WSCT3 ((P_U32)(EMI_BASE+0x460))
+#define EMI_WSCT4 ((P_U32)(EMI_BASE+0x464))
+#define EMI_MSEL2 ((P_U32)(EMI_BASE+0x468))
+#define EMI_MSEL3 ((P_U32)(EMI_BASE+0x470))
+#define EMI_MSEL4 ((P_U32)(EMI_BASE+0x478))
+#define EMI_MSEL5 ((P_U32)(EMI_BASE+0x480))
+#define EMI_MSEL6 ((P_U32)(EMI_BASE+0x488))
+#define EMI_MSEL7 ((P_U32)(EMI_BASE+0x490))
+#define EMI_MSEL8 ((P_U32)(EMI_BASE+0x498))
+#define EMI_MSEL9 ((P_U32)(EMI_BASE+0x4A0))
+#define EMI_MSEL10 ((P_U32)(EMI_BASE+0x4A8))
+#define EMI_BMID0 ((P_U32)(EMI_BASE+0x4B0))
+#define EMI_BMID1 ((P_U32)(EMI_BASE+0x4B4))
+#define EMI_BMID2 ((P_U32)(EMI_BASE+0x4B8))
+#define EMI_BMID3 ((P_U32)(EMI_BASE+0x4BC))
+#define EMI_BMID4 ((P_U32)(EMI_BASE+0x4C0))
+#define EMI_BMID5 ((P_U32)(EMI_BASE+0x4C4))
+#define EMI_BMID6 ((P_U32)(EMI_BASE+0x4C8))
+#define EMI_BMID7 ((P_U32)(EMI_BASE+0x4CC))
+#define EMI_BMID8 ((P_U32)(EMI_BASE+0x4D0))
+#define EMI_BMID9 ((P_U32)(EMI_BASE+0x4D4))
+#define EMI_BMID10 ((P_U32)(EMI_BASE+0x4D8))
+#define EMI_BMEN1 ((P_U32)(EMI_BASE+0x4E0))
+#define EMI_BMEN2 ((P_U32)(EMI_BASE+0x4E8))
+#define EMI_BMRW0 ((P_U32)(EMI_BASE+0x4F8))
+#define EMI_BMRW1 ((P_U32)(EMI_BASE+0x4FC))
+#define EMI_TTYPE1 ((P_U32)(EMI_BASE+0x500))
+#define EMI_TTYPE2 ((P_U32)(EMI_BASE+0x508))
+#define EMI_TTYPE3 ((P_U32)(EMI_BASE+0x510))
+#define EMI_TTYPE4 ((P_U32)(EMI_BASE+0x518))
+#define EMI_TTYPE5 ((P_U32)(EMI_BASE+0x520))
+#define EMI_TTYPE6 ((P_U32)(EMI_BASE+0x528))
+#define EMI_TTYPE7 ((P_U32)(EMI_BASE+0x530))
+#define EMI_TTYPE8 ((P_U32)(EMI_BASE+0x538))
+#define EMI_TTYPE9 ((P_U32)(EMI_BASE+0x540))
+#define EMI_TTYPE10 ((P_U32)(EMI_BASE+0x548))
+#define EMI_TTYPE11 ((P_U32)(EMI_BASE+0x550))
+#define EMI_TTYPE12 ((P_U32)(EMI_BASE+0x558))
+#define EMI_TTYPE13 ((P_U32)(EMI_BASE+0x560))
+#define EMI_TTYPE14 ((P_U32)(EMI_BASE+0x568))
+#define EMI_TTYPE15 ((P_U32)(EMI_BASE+0x570))
+#define EMI_TTYPE16 ((P_U32)(EMI_BASE+0x578))
+#define EMI_TTYPE17 ((P_U32)(EMI_BASE+0x580))
+#define EMI_TTYPE18 ((P_U32)(EMI_BASE+0x588))
+#define EMI_TTYPE19 ((P_U32)(EMI_BASE+0x590))
+#define EMI_TTYPE20 ((P_U32)(EMI_BASE+0x598))
+#define EMI_TTYPE21 ((P_U32)(EMI_BASE+0x5A0))
+#define EMI_BWCT0 ((P_U32)(EMI_BASE+0x5B0))
+#define EMI_BWCT1 ((P_U32)(EMI_BASE+0x5B4))
+#define EMI_BWCT2 ((P_U32)(EMI_BASE+0x5B8))
+#define EMI_BWCT3 ((P_U32)(EMI_BASE+0x5BC))
+#define EMI_BWCT4 ((P_U32)(EMI_BASE+0x5C0))
+#define EMI_BWST0 ((P_U32)(EMI_BASE+0x5C4))
+#define EMI_BWST1 ((P_U32)(EMI_BASE+0x5C8))
+#define EMI_EX_CON ((P_U32)(EMI_BASE+0x5D0))
+#define EMI_EX_ST0 ((P_U32)(EMI_BASE+0x5D4))
+#define EMI_EX_ST1 ((P_U32)(EMI_BASE+0x5D8))
+#define EMI_EX_ST2 ((P_U32)(EMI_BASE+0x5DC))
+#define EMI_WP_ADR ((P_U32)(EMI_BASE+0x5E0))
+#define EMI_WP_ADR_2ND ((P_U32)(EMI_BASE+0x5E4))
+#define EMI_WP_CTRL ((P_U32)(EMI_BASE+0x5E8))
+#define EMI_CHKER ((P_U32)(EMI_BASE+0x5F0))
+#define EMI_CHKER_TYPE ((P_U32)(EMI_BASE+0x5F4))
+#define EMI_CHKER_ADR ((P_U32)(EMI_BASE+0x5F8))
+#define EMI_CHKER_ADR_2ND ((P_U32)(EMI_BASE+0x5FC))
+#define EMI_BWCT0_2ND ((P_U32)(EMI_BASE+0x6A0))
+#define EMI_LTCT0_2ND ((P_U32)(EMI_BASE+0x750))
+#define EMI_LTCT1_2ND ((P_U32)(EMI_BASE+0x754))
+#define EMI_LTCT2_2ND ((P_U32)(EMI_BASE+0x758))
+#define EMI_LTCT3_2ND ((P_U32)(EMI_BASE+0x75C))
+#define EMI_BWCT0_3RD ((P_U32)(EMI_BASE+0x770))
+#define EMI_BWCT0_4TH ((P_U32)(EMI_BASE+0x780))
+#define EMI_BWCT0_5TH ((P_U32)(EMI_BASE+0x7B0))
+#define EMI_BWCT0_6TH ((P_U32)(EMI_BASE+0x7C8))
+#define EMI_SNST ((P_U32)(EMI_BASE+0x7F8))
+#define EMI_SLVA ((P_U32)(EMI_BASE+0x800))
+#define EMI_AXI_BIST_ADR0 ((P_U32)(EMI_BASE+0x98c))
+#define EMI_AXI_BIST_ADR1 ((P_U32)(EMI_BASE+0x990))
+#define EMI_AXI_BIST_ADR2 ((P_U32)(EMI_BASE+0x994))
+
+#define EMI_MPU_CTRL (EMI_MPU_BASE+0x000)
+#define EMI_MPU_DBG (EMI_MPU_BASE+0x004)
+#define EMI_MPU_SA0 (EMI_MPU_BASE+0x100)
+#define EMI_MPU_EA0 (EMI_MPU_BASE+0x200)
+#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4))
+#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4))
+#define EMI_MPU_APC0 (EMI_MPU_BASE+0x300)
+#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
+#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800)
+#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4))
+#define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900)
+#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4))
+
+#define CHN_EMI_CONA(base) (base + 0x000)
+#define CHN_EMI_CONB(base) (base + 0x008)
+#define CHN_EMI_CONC(base) (base + 0x010)
+
+#endif // __EMI_HW_H__
diff --git a/src/bsp/lk/platform/mt2731/include/platform/emi_info_v1.h b/src/bsp/lk/platform/mt2731/include/platform/emi_info_v1.h
new file mode 100644
index 0000000..ff93764
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/emi_info_v1.h
@@ -0,0 +1,51 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef __EMI_INFO_H__
+#define __EMI_INFO_H__
+
+#define MAX_CH 2
+#define MAX_RK 2
+
+typedef struct {
+ unsigned int dram_type;
+ unsigned int ch_num;
+ unsigned int rk_num;
+ unsigned long long rank_size[MAX_RK];
+} emi_info_t;
+
+int set_fdt_emi_info(void *fdt);
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_mt.h b/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_mt.h
new file mode 100644
index 0000000..6f00046
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_mt.h
@@ -0,0 +1,15 @@
+#ifndef __EMI_MPU_MT_H__
+#define __EMI_MPU_MT_H__
+
+#define ENABLE_MPU 1
+
+#define EMI_MPU_ALIGN_BITS 16
+#define EMI_MPU_DOMAIN_NUM 16
+#define EMI_MPU_REGION_NUM 32
+#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
+
+#define SSPM_MPU_REGION_ID 3
+
+#include "emi_mpu_v1.h"
+
+#endif /* __EMI_MPU_MT_H__ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_v1.h b/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_v1.h
new file mode 100644
index 0000000..ff8dfa4
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/emi_mpu_v1.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __EMI_MPU_H__
+#define __EMI_MPU_H__
+
+#include "emi_mpu_mt.h"
+
+#define NO_PROTECTION 0
+#define SEC_RW 1
+#define SEC_RW_NSEC_R 2
+#define SEC_RW_NSEC_W 3
+#define SEC_R_NSEC_R 4
+#define FORBIDDEN 5
+#define SEC_R_NSEC_RW 6
+
+#define LOCK 1
+#define UNLOCK 0
+
+#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
+#if (EMI_MPU_DGROUP_NUM == 1)
+#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
+do { \
+ apc_ary[0] = \
+ (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \
+ (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
+ (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \
+} while (0)
+#elif (EMI_MPU_DGROUP_NUM == 2)
+#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
+do { \
+ apc_ary[1] = \
+ (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | (((unsigned int) d13) << 15) | \
+ (((unsigned int) d12) << 12) | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \
+ (((unsigned int) d9) << 3) | ((unsigned int) d8); \
+ apc_ary[0] = \
+ (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \
+ (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
+ (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \
+} while (0)
+#endif
+
+struct emi_region_info_t {
+ unsigned long long start;
+ unsigned long long end;
+ unsigned int region;
+ unsigned int apc[EMI_MPU_DGROUP_NUM];
+};
+
+extern int emi_mpu_set_protection(struct emi_region_info_t *region_info);
+
+#endif /* __EMI_MPU_H__ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/generic_ioctl.h b/src/bsp/lk/platform/mt2731/include/platform/generic_ioctl.h
new file mode 100644
index 0000000..84c2ec8
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/generic_ioctl.h
@@ -0,0 +1,64 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ *** This header was automatically generated from a Linux kernel header
+ *** of the same name, to make information necessary for userspace to
+ *** call into the kernel available to libc. It contains only constants,
+ *** structures, and macros generated from the original header, and thus,
+ *** contains no copyrightable information.
+ ***
+ *** To edit the content of this header, modify the corresponding
+ *** source file (e.g. under external/kernel-headers/original/) then
+ *** run bionic/libc/kernel/tools/update_all.py
+ ***
+ *** Any manual change here will be lost the next time this script will
+ *** be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _UAPI_ASM_GENERIC_IOCTL_H
+#define _UAPI_ASM_GENERIC_IOCTL_H
+#define _IOC_NRBITS 8
+#define _IOC_TYPEBITS 8
+#ifndef _IOC_SIZEBITS
+#define _IOC_SIZEBITS 14
+#endif
+#ifndef _IOC_DIRBITS
+#define _IOC_DIRBITS 2
+#endif
+#define _IOC_NRMASK ((1 << _IOC_NRBITS) - 1)
+#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS) - 1)
+#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS) - 1)
+#define _IOC_DIRMASK ((1 << _IOC_DIRBITS) - 1)
+#define _IOC_NRSHIFT 0
+#define _IOC_TYPESHIFT (_IOC_NRSHIFT + _IOC_NRBITS)
+#define _IOC_SIZESHIFT (_IOC_TYPESHIFT + _IOC_TYPEBITS)
+#define _IOC_DIRSHIFT (_IOC_SIZESHIFT + _IOC_SIZEBITS)
+#ifndef _IOC_NONE
+#define _IOC_NONE 0U
+#endif
+#ifndef _IOC_WRITE
+#define _IOC_WRITE 1U
+#endif
+#ifndef _IOC_READ
+#define _IOC_READ 2U
+#endif
+#define _IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT))
+#define _IOC_TYPECHECK(t) (sizeof(t))
+#define _IO(type,nr) _IOC(_IOC_NONE, (type), (nr), 0)
+#define _IOR(type,nr,size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size) _IOC(_IOC_READ | _IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
+#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
+#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ | _IOC_WRITE, (type), (nr), sizeof(size))
+#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT ((_IOC_WRITE | _IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/gic.h b/src/bsp/lk/platform/mt2731/include/platform/gic.h
new file mode 100644
index 0000000..abd54f7
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/gic.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/mt2731.h>
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mkimg.h b/src/bsp/lk/platform/mt2731/include/platform/mkimg.h
new file mode 100644
index 0000000..8b864f6
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mkimg.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __MKIMG_H__
+#define __MKIMG_H__
+
+#define MKIMG_MAGIC (0x58881688)
+#define MKIMG_EXT_MAGIC (0x58891689)
+
+#define MKIMG_HDR_SZ (0x200)
+#define MKIMG_NAME_SZ (32)
+
+#define LEGACY_MKIMG_ALIGN_SZ (4096)
+
+/* image types */
+#define IMG_TYPE_ID_OFFSET (0)
+#define IMG_TYPE_RESERVED0_OFFSET (8)
+#define IMG_TYPE_RESERVED1_OFFSET (16)
+#define IMG_TYPE_GROUP_OFFSET (24)
+
+#define IMG_TYPE_ID_MASK (0xffU << IMG_TYPE_ID_OFFSET)
+#define IMG_TYPE_RESERVED0_MASK (0xffU << IMG_TYPE_RESERVED0_OFFSET)
+#define IMG_TYPE_RESERVED1_MASK (0xffU << IMG_TYPE_RESERVED1_OFFSET)
+#define IMG_TYPE_GROUP_MASK (0xffU << IMG_TYPE_GROUP_OFFSET)
+
+#define IMG_TYPE_GROUP_AP (0x00U << IMG_TYPE_GROUP_OFFSET)
+#define IMG_TYPE_GROUP_MD (0x01U << IMG_TYPE_GROUP_OFFSET)
+#define IMG_TYPE_GROUP_CERT (0x02U << IMG_TYPE_GROUP_OFFSET)
+
+/* AP group */
+#define IMG_TYPE_IMG_AP_BIN (0x00 | IMG_TYPE_GROUP_AP)
+#define IMG_TYPE_AND_VFY_BOOT_SIG (0x01 | IMG_TYPE_GROUP_AP)
+
+/* MD group */
+#define IMG_TYPE_IMG_MD_LTE (0x00 | IMG_TYPE_GROUP_MD)
+#define IMG_TYPE_IMG_MD_C2K (0x01 | IMG_TYPE_GROUP_MD)
+
+/* CERT group */
+#define IMG_TYPE_CERT1 (0x00 | IMG_TYPE_GROUP_CERT)
+#define IMG_TYPE_CERT1_MD (0x01 | IMG_TYPE_GROUP_CERT)
+#define IMG_TYPE_CERT2 (0x02 | IMG_TYPE_GROUP_CERT)
+
+union mkimg_hdr {
+ struct {
+ uint32_t magic;
+ uint32_t dsz;
+ char name[MKIMG_NAME_SZ];
+ uint32_t maddr;
+ uint32_t mode;
+ /* extension */
+ uint32_t ext_magic;
+ uint32_t hdr_sz;
+ uint32_t hdr_ver;
+ uint32_t img_type;
+ uint32_t img_list_end;
+ uint32_t align_sz;
+ uint32_t dsz_extend;
+ uint32_t maddr_extend;
+ uint32_t scrambled;
+ } info;
+ uint8_t data[MKIMG_HDR_SZ];
+};
+
+#endif /* __MKIMG_H__ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mmc_core.h b/src/bsp/lk/platform/mt2731/include/platform/mmc_core.h
new file mode 100644
index 0000000..1214ae1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mmc_core.h
@@ -0,0 +1,655 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <sys/types.h>
+#include <kernel/mutex.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MMC_BLOCK_BITS_SHFT (9)
+#define MMC_BLOCK_SIZE (1 << MMC_BLOCK_BITS_SHFT)
+#define MMC_MAX_BLOCK_SIZE (1 << MMC_BLOCK_BITS_SHFT)
+
+#define SDIO_MAX_FUNCS (7)
+
+#define SD_CMD_BIT (1 << 7)
+#define SD_CMD_APP_BIT (1 << 8)
+#define SD_CMD_AUTO_BIT (1 << 9)
+
+/* MMC command numbers */
+#define MMC_CMD_GO_IDLE_STATE (0) /* bc. no response */
+#define MMC_CMD_SEND_OP_COND (1) /* bcr. R3 */
+#define MMC_CMD_ALL_SEND_CID (2) /* bcr. R2 */
+#define MMC_CMD_SET_RELATIVE_ADDR (3) /* ac. R1 */
+#define MMC_CMD_SET_DSR (4) /* bc. no response */
+#define MMC_CMD_SLEEP_AWAKE (5) /* ac. R1b */
+#define MMC_CMD_SWITCH (6) /* ac. R1b */
+#define MMC_CMD_SELECT_CARD (7) /* ac. R1/R1b */
+#define MMC_CMD_SEND_EXT_CSD (8) /* adtc. R1 */
+#define MMC_CMD_SEND_CSD (9) /* ac. R2 */
+#define MMC_CMD_SEND_CID (10) /* ac. R2 */
+#define MMC_CMD_READ_DAT_UNTIL_STOP (11) /* adtc. R1 */
+#define MMC_CMD_STOP_TRANSMISSION (12) /* ac. R1/R1b */
+#define MMC_CMD_SEND_STATUS (13) /* ac. R1 */
+#define MMC_CMD_BUSTEST_R (14) /* adtc. R1 */
+#define MMC_CMD_GO_INACTIVE_STATE (15) /* ac. no response */
+#define MMC_CMD_SET_BLOCKLEN (16) /* ac. R1 */
+#define MMC_CMD_READ_SINGLE_BLOCK (17) /* adtc. R1 */
+#define MMC_CMD_READ_MULTIPLE_BLOCK (18) /* adtc. R1 */
+#define MMC_CMD_BUSTEST_W (19) /* adtc. R1 */
+#define MMC_CMD_WRITE_DAT_UNTIL_STOP (20) /* adtc. R1 */
+#define MMC_CMD21 (21) /* adtc. R1 Sandisk */
+#define MMC_CMD_SET_BLOCK_COUNT (23) /* ac. R1 */
+#define MMC_CMD_WRITE_BLOCK (24) /* adtc. R1 */
+#define MMC_CMD_WRITE_MULTIPLE_BLOCK (25) /* adtc. R1 */
+#define MMC_CMD_PROGRAM_CID (26) /* adtc. R1 */
+#define MMC_CMD_PROGRAM_CSD (27) /* adtc. R1 */
+
+#define MMC_CMD_SET_WRITE_PROT (28) /* ac. R1b */
+#define MMC_CMD_CLR_WRITE_PROT (29) /* ac. R1b */
+#define MMC_CMD_SEND_WRITE_PROT (30) /* adtc. R1 */
+#define MMC_CMD_SEND_WRITE_PROT_TYPE (31) /* adtc. R1 */
+#define MMC_CMD_ERASE_WR_BLK_START (32)
+#define MMC_CMD_ERASE_WR_BLK_END (33)
+#define MMC_CMD_ERASE_GROUP_START (35) /* ac. R1 */
+#define MMC_CMD_ERASE_GROUP_END (36) /* ac. R1 */
+#define MMC_CMD_ERASE (38) /* ac. R1b */
+#define MMC_CMD_FAST_IO (39) /* ac. R4 */
+#define MMC_CMD_GO_IRQ_STATE (40) /* bcr. R5 */
+#define MMC_CMD_LOCK_UNLOCK (42) /* adtc. R1 */
+#define MMC_CMD50 (50) /* adtc. R1 Sandisk */
+#define MMC_CMD_APP_CMD (55) /* ac. R1 */
+#define MMC_CMD_GEN_CMD (56) /* adtc. R1 */
+
+/* SD Card command numbers */
+#define SD_CMD_SEND_RELATIVE_ADDR (3 | SD_CMD_BIT)
+#define SD_CMD_SWITCH (6 | SD_CMD_BIT)
+#define SD_CMD_SEND_IF_COND (8 | SD_CMD_BIT)
+#define SD_CMD_VOL_SWITCH (11 | SD_CMD_BIT)
+#define SD_CMD_SEND_TUNING_BLOCK (19 | SD_CMD_BIT)
+#define SD_CMD_SPEED_CLASS_CTRL (20 | SD_CMD_BIT)
+
+#define SD_ACMD_SET_BUSWIDTH (6 | SD_CMD_APP_BIT)
+#define SD_ACMD_SD_STATUS (13 | SD_CMD_APP_BIT)
+#define SD_ACMD_SEND_NR_WR_BLOCKS (22 | SD_CMD_APP_BIT)
+#define SD_ACMD_SET_WR_ERASE_CNT (23 | SD_CMD_APP_BIT)
+#define SD_ACMD_SEND_OP_COND (41 | SD_CMD_APP_BIT)
+#define SD_ACMD_SET_CLR_CD (42 | SD_CMD_APP_BIT)
+#define SD_ACMD_SEND_SCR (51 | SD_CMD_APP_BIT)
+
+/* SDIO Card command numbers */
+#define SD_IO_SEND_OP_COND (5 | SD_CMD_BIT) /* bcr. R4 */
+#define SD_IO_RW_DIRECT (52 | SD_CMD_BIT)/* ac. R5 */
+#define SD_IO_RW_EXTENDED (53 | SD_CMD_BIT)/* adtc. R5 */
+
+/* platform dependent command */
+#define SD_ATOCMD_STOP_TRANSMISSION (12 | SD_CMD_AUTO_BIT)
+#define SD_ATOCMD_SET_BLOCK_COUNT (23 | SD_CMD_AUTO_BIT)
+
+#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
+#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
+#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
+#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
+#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
+#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
+#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
+#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
+#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
+#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
+#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ //Add this line by reference to include/linux/mmc/host.h in linux kernel
+#define MMC_VDD_27_36 0x00FF8000
+
+#define EMMC_VER_50 (50)
+#define EMMC_VER_45 (45)
+#define EMMC_VER_44 (44)
+#define EMMC_VER_43 (43)
+#define EMMC_VER_42 (42)
+#define SD_VER_10 (10)
+#define SD_VER_20 (20)
+#define SD_VER_30 (30)
+
+#define MMC_ERR_NONE 0
+#define MMC_ERR_TIMEOUT 1
+#define MMC_ERR_BADCRC 2
+#define MMC_ERR_FIFO 3
+#define MMC_ERR_FAILED 4
+#define MMC_ERR_INVALID 5
+#define MMC_ERR_CMDTUNEFAIL 6
+#define MMC_ERR_READTUNEFAIL 7
+#define MMC_ERR_WRITETUNEFAIL 8
+#define MMC_ERR_CMD_TIMEOUT 9
+#define MMC_ERR_CMD_RSPCRC 10
+#define MMC_ERR_ACMD_TIMEOUT 11
+#define MMC_ERR_ACMD_RSPCRC 12
+#define MMC_ERR_AXI_RSPCRC 13
+#define MMC_ERR_UNEXPECT 14
+#define MMC_ERR_RETRY 15
+
+#define MMC_POWER_OFF 0
+#define MMC_POWER_UP 1
+#define MMC_POWER_ON 2
+
+#define MMC_BUS_WIDTH_1 0
+#define MMC_BUS_WIDTH_4 2
+
+#define SD_BUS_WIDTH_1 0
+#define SD_BUS_WIDTH_4 2
+
+#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
+#define MMC_STATE_READONLY (1<<1) /* card is read-only */
+#define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */
+#define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */
+#define MMC_STATE_HIGHCAPS (1<<4)
+#define MMC_STATE_UHS1 (1<<5) /* card is in ultra high speed mode */
+#define MMC_STATE_DDR (1<<6) /* card is in ddr mode */
+#define MMC_STATE_HS200 (1<<7)
+#define MMC_STATE_HS400 (1<<8)
+#define MMC_STATE_BACKYARD (1<<9)
+
+#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */
+#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
+#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
+#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
+#define R1_ERASE_PARAM (1 << 27) /* ex, c */
+#define R1_WP_VIOLATION (1 << 26) /* erx, c */
+#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
+#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
+#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
+#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
+#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
+#define R1_CC_ERROR (1 << 20) /* erx, c */
+#define R1_ERROR (1 << 19) /* erx, c */
+#define R1_UNDERRUN (1 << 18) /* ex, c */
+#define R1_OVERRUN (1 << 17) /* ex, c */
+#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
+#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
+#define R1_ERASE_RESET (1 << 13) /* sr, c */
+#define R1_STATUS(x) (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
+#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
+#define R1_SWITCH_ERROR (1 << 7) /* ex, b */
+#define R1_URGENT_BKOPS (1 << 6) /* sr, a */
+#define R1_APP_CMD (1 << 5) /* sr, c */
+
+/*
+ * Card Command Classes (CCC)
+ */
+#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
+/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
+#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
+/* (CMD11) */
+#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
+/* (CMD16,17,18) */
+#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
+/* (CMD20) */
+#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
+/* (CMD16,24,25,26,27) */
+#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
+/* (CMD32,33,34,35,36,37,38,39) */
+#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
+/* (CMD28,29,30) */
+#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
+/* (CMD16,CMD42) */
+#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
+/* (CMD55,56,57,ACMD*) */
+#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
+/* (CMD5,39,40,52,53) */
+#define CCC_SWITCH (1<<10) /* (10) High speed switch */
+/* (CMD6,34,35,36,37,50) */
+/* (11) Reserved */
+/* (CMD?) */
+
+/*
+ * CSD field definitions
+ */
+
+#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
+#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
+#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
+#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
+
+#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
+#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
+#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
+#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
+#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
+
+/*
+ * EXT_CSD fields
+ */
+
+#define EXT_CSD_BADBLK_MGMT 134 /* R/W */
+#define EXT_CSD_ENH_START_ADDR 136 /* R/W 4 bytes */
+#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W 3 bytes */
+#define EXT_CSD_GP1_SIZE_MULT 143 /* R/W 3 bytes */
+#define EXT_CSD_GP2_SIZE_MULT 146 /* R/W 3 bytes */
+#define EXT_CSD_GP3_SIZE_MULT 149 /* R/W 3 bytes */
+#define EXT_CSD_GP4_SIZE_MULT 152 /* R/W 3 bytes */
+#define EXT_CSD_PART_SET_COMPL 155 /* R/W */
+#define EXT_CSD_PART_ATTR 156 /* R/W 3 bytes */
+#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R/W 3 bytes */
+#define EXT_CSD_PART_SUPPORT 160 /* R */
+#define EXT_CSD_HPI_MGMT 161 /* R/W/E_P (4.41) */
+#define EXT_CSD_RST_N_FUNC 162 /* R/W */
+#define EXT_CSD_BKOPS_EN 163 /* R/W (4.41) */
+#define EXT_CSD_BKOPS_START 164 /* W/E_P (4.41) */
+#define EXT_CSD_WR_REL_PARAM 166 /* R (4.41) */
+#define EXT_CSD_WR_REL_SET 167 /* R/W (4.41) */
+#define EXT_CSD_RPMB_SIZE_MULT 168 /* R */
+#define EXT_CSD_FW_CONFIG 169 /* R/W */
+#define EXT_CSD_USR_WP 171 /* R/W, R/W/C_P & R/W/E_P */
+#define EXT_CSD_BOOT_WP 173 /* R/W, R/W/C_P */
+#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W/E */
+#define EXT_CSD_BOOT_BUS_WIDTH 177 /* R/W/E */
+#define EXT_CSD_BOOT_CONFIG_PROT 178 /* R/W & R/W/C_P */
+#define EXT_CSD_PART_CFG 179 /* R/W/E & R/W/E_P */
+#define EXT_CSD_ERASED_MEM_CONT 181 /* R */
+#define EXT_CSD_BUS_WIDTH 183 /* R/W */
+#define EXT_CSD_HS_TIMING 185 /* R/W */
+#define EXT_CSD_PWR_CLASS 187 /* R/W/E_P */
+#define EXT_CSD_CMD_SET_REV 189 /* R */
+#define EXT_CSD_CMD_SET 191 /* R/W/E_P */
+#define EXT_CSD_REV 192 /* R */
+#define EXT_CSD_STRUCT 194 /* R */
+#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_OUT_OF_INTR_TIME 198 /* R (4.41) */
+#define EXT_CSD_PART_SWITCH_TIME 199 /* R (4.41) */
+#define EXT_CSD_PWR_CL_52_195 200 /* R */
+#define EXT_CSD_PWR_CL_26_195 201 /* R */
+#define EXT_CSD_PWR_CL_52_360 202 /* R */
+#define EXT_CSD_PWR_CL_26_360 203 /* R */
+#define EXT_CSD_MIN_PERF_R_4_26 205 /* R */
+#define EXT_CSD_MIN_PERF_W_4_26 206 /* R */
+#define EXT_CSD_MIN_PERF_R_8_26_4_25 207 /* R */
+#define EXT_CSD_MIN_PERF_W_8_26_4_25 208 /* R */
+#define EXT_CSD_MIN_PERF_R_8_52 209 /* R */
+#define EXT_CSD_MIN_PERF_W_8_52 210 /* R */
+#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
+#define EXT_CSD_S_A_TIMEOUT 217 /* R */
+#define EXT_CSD_S_C_VCCQ 219 /* R */
+#define EXT_CSD_S_C_VCC 220 /* R */
+#define EXT_CSD_HC_WP_GPR_SIZE 221 /* R */
+#define EXT_CSD_REL_WR_SEC_C 222 /* R */
+#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* R */
+#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* R */
+#define EXT_CSD_ACC_SIZE 225 /* R */
+#define EXT_CSD_BOOT_SIZE_MULT 226 /* R */
+#define EXT_CSD_BOOT_INFO 228 /* R */
+#define EXT_CSD_SEC_TRIM_MULT 229 /* R */
+#define EXT_CSD_SEC_ERASE_MULT 230 /* R */
+#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* R */
+#define EXT_CSD_TRIM_MULT 232 /* R */
+#define EXT_CSD_MIN_PERF_DDR_R_8_52 234 /* R */
+#define EXT_CSD_MIN_PERF_DDR_W_8_52 235 /* R */
+#define EXT_CSD_PWR_CL_DDR_52_195 238 /* R */
+#define EXT_CSD_PWR_CL_DDR_52_360 239 /* R */
+#define EXT_CSD_INI_TIMEOUT_AP 241 /* R */
+#define EXT_CSD_CORRECT_PRG_SECTS_NUM 242 /* R, 4 bytes (4.41) */
+#define EXT_CSD_BKOPS_STATUS 246 /* R (4.41) */
+#define EXT_CSD_BKOPS_SUPP 502 /* R (4.41) */
+#define EXT_CSD_HPI_FEATURE 503 /* R (4.41) */
+#define EXT_CSD_S_CMD_SET 504 /* R */
+
+/*
+ * EXT_CSD field definitions
+ */
+
+/* SEC_FEATURE_SUPPORT[231] */
+#define EXT_CSD_SEC_FEATURE_ER_EN (1<<0)
+#define EXT_CSD_SEC_FEATURE_BD_BLK_EN (1<<2)
+#define EXT_CSD_SEC_FEATURE_GB_CL_EN (1<<4)
+
+/* BOOT_INFO[228] */
+#define EXT_CSD_BOOT_INFO_ALT_BOOT (1<<0)
+#define EXT_CSD_BOOT_INFO_DDR_BOOT (1<<1)
+#define EXT_CSD_BOOT_INFO_HS_BOOT (1<<2)
+
+#define EXT_CSD_CMD_SET_NORMAL (1<<0)
+#define EXT_CSD_CMD_SET_SECURE (1<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_52 (1<<2) /* Card can run at DDR 52MHz@1.8V or 3V */
+#define EXT_CSD_CARD_TYPE_DDR_52_1_2V (1<<3) /* Card can run at DDR 52MHz@1.2V */
+#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz@ 1.8V*/
+#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz@ 1.2V*/
+#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz@ 1.8V*/
+#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz@ 1.2V*/
+
+/* BUS_WIDTH[183] */
+#define EXT_CSD_BUS_WIDTH_1 (0) /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4 (1) /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8 (2) /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_DDR (5) /* Card is in 4 bit mode + DDR */
+#define EXT_CSD_BUS_WIDTH_8_DDR (6) /* Card is in 8 bit mode + DDR */
+
+/* high speed timing */
+#define EXT_CSD_HS_TIMEING_BACKWARDS (0) /* selecting backwards compatibility interface timing */
+#define EXT_CSD_HS_TIMEING_HS (1) /* selecting high speed interface timing */
+#define EXT_CSD_HS_TIMEING_HS200 (2) /* selecting hs200 interface timing */
+#define EXT_CSD_HS_TIMEING_HS400 (3) /* selecting hs400 interface timing */
+
+/* ERASED_MEM_CONT[181] */
+#define EXT_CSD_ERASED_MEM_CONT_0 (0)
+#define EXT_CSD_ERASED_MEM_CONT_1 (1)
+
+/* PARTITION CONFIG[179] */
+#define EXT_CSD_PART_CFG_DEFT_PART (0)
+#define EXT_CSD_PART_CFG_BOOT_PART_1 (1)
+#define EXT_CSD_PART_CFG_BOOT_PART_2 (2)
+#define EXT_CSD_PART_CFG_RPMB_PART (3)
+#define EXT_CSD_PART_CFG_GP_PART_1 (4)
+#define EXT_CSD_PART_CFG_GP_PART_2 (5)
+#define EXT_CSD_PART_CFG_GP_PART_3 (6)
+#define EXT_CSD_PART_CFG_GP_PART_4 (7)
+#define EXT_CSD_PART_CFG_EN_NO_BOOT (0 << 3)
+#define EXT_CSD_PART_CFG_EN_BOOT_PART_1 (1 << 3)
+#define EXT_CSD_PART_CFG_EN_BOOT_PART_2 (2 << 3)
+#define EXT_CSD_PART_CFG_EN_USER_AREA (7 << 3)
+#define EXT_CSD_PART_CFG_EN_NO_ACK (0 << 6)
+#define EXT_CSD_PART_CFG_EN_ACK (1 << 6)
+
+/* BOOT_CONFIG_PROT[178] */
+#define EXT_CSD_EN_PWR_BOOT_CFG_PROT (1)
+#define EXT_CSD_EN_PERM_BOOT_CFG_PROT (1<<4) /* Carefully */
+
+/* BOOT_BUS_WIDTH[177] */
+#define EXT_CSD_BOOT_BUS_WIDTH_1 (0)
+#define EXT_CSD_BOOT_BUS_WIDTH_4 (1)
+#define EXT_CSD_BOOT_BUS_WIDTH_8 (2)
+#define EXT_CSD_BOOT_BUS_RESET (1 << 2)
+
+#define EXT_CSD_BOOT_BUS_MODE_DEFT (0 << 3)
+#define EXT_CSD_BOOT_BUS_MODE_HS (1 << 3)
+#define EXT_CSD_BOOT_BUS_MODE_DDR (2 << 3)
+
+/* ERASE_GROUP_DEF[175] */
+#define EXT_CSD_ERASE_GRP_DEF_EN (1)
+
+/* BOOT_WP[173] */
+#define EXT_CSD_BOOT_WP_EN_PWR_WP (1)
+#define EXT_CSD_BOOT_WP_EN_PERM_WP (1 << 2)
+#define EXT_CSD_BOOT_WP_DIS_PERM_WP (1 << 4)
+#define EXT_CSD_BOOT_WP_DIS_PWR_WP (1 << 6)
+
+/* USER_WP[171] */
+#define EXT_CSD_USR_WP_EN_PWR_WP (1)
+#define EXT_CSD_USR_WP_EN_PERM_WP (1<<2)
+#define EXT_CSD_USR_WP_DIS_PWR_WP (1<<3)
+#define EXT_CSD_USR_WP_DIS_PERM_WP (1<<4)
+#define EXT_CSD_USR_WP_DIS_CD_PERM_WP (1<<6)
+#define EXT_CSD_USR_WP_DIS_PERM_PWD (1<<7)
+
+/* RST_n_FUNCTION[162] */
+#define EXT_CSD_RST_N_TEMP_DIS (0)
+#define EXT_CSD_RST_N_PERM_EN (1) /* carefully */
+#define EXT_CSD_RST_N_PERM_DIS (2) /* carefully */
+
+/* PARTITIONING_SUPPORT[160] */
+#define EXT_CSD_PART_SUPPORT_PART_EN (1)
+#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN (1<<1)
+
+/* PARTITIONS_ATTRIBUTE[156] */
+#define EXT_CSD_PART_ATTR_ENH_USR (1<<0)
+#define EXT_CSD_PART_ATTR_ENH_1 (1<<1)
+#define EXT_CSD_PART_ATTR_ENH_2 (1<<2)
+#define EXT_CSD_PART_ATTR_ENH_3 (1<<3)
+#define EXT_CSD_PART_ATTR_ENH_4 (1<<4)
+
+/* PARTITION_SETTING_COMPLETED[156] */
+#define EXT_CSD_PART_SET_COMPL_BIT (1<<0)
+
+/*
+ * MMC_SWITCH access modes
+ */
+
+#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
+#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
+#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
+
+#define MMC_SWITCH_MODE_SDR12 0
+#define MMC_SWITCH_MODE_SDR25 1
+#define MMC_SWITCH_MODE_SDR50 2
+#define MMC_SWITCH_MODE_SDR104 3
+#define MMC_SWITCH_MODE_DDR50 4
+
+#define MMC_SWITCH_MODE_DRV_TYPE_B 0
+#define MMC_SWITCH_MODE_DRV_TYPE_A 1
+#define MMC_SWITCH_MODE_DRV_TYPE_C 2
+#define MMC_SWITCH_MODE_DRV_TYPE_D 3
+
+#define MMC_SWITCH_MODE_CL_200MA 0
+#define MMC_SWITCH_MODE_CL_400MA 1
+#define MMC_SWITCH_MODE_CL_600MA 2
+#define MMC_SWITCH_MODE_CL_800MA 3
+
+/*
+ * MMC_ERASE arguments
+ */
+#define MMC_ERASE_SECURE_REQ (1 << 31)
+#define MMC_ERASE_GC_REQ (1 << 15)
+#define MMC_ERASE_DISCARD (3 << 0)
+#define MMC_ERASE_TRIM (1 << 0)
+#define MMC_ERASE_NORMAL (0)
+
+#define HOST_BUS_WIDTH_1 (1)
+#define HOST_BUS_WIDTH_4 (4)
+#define HOST_BUS_WIDTH_8 (8)
+
+#define EMMC_BOOT_PULL_CMD_MODE (0)
+#define EMMC_BOOT_RST_CMD_MODE (1)
+
+enum {
+ EMMC_BOOT_PWR_RESET = 0,
+ EMMC_BOOT_RST_N_SIG,
+ EMMC_BOOT_PRE_IDLE_CMD
+};
+
+enum {
+ RESP_NONE = 0,
+ RESP_R1,
+ RESP_R2,
+ RESP_R3,
+ RESP_R4,
+ RESP_R5,
+ RESP_R6,
+ RESP_R7,
+ RESP_R1B
+};
+
+struct mmc_csd {
+ unsigned char csd_struct;
+ unsigned char mmca_vsn;
+ unsigned int max_dtr; /* max. data transfer rate */
+ unsigned int read_blkbits; /* max. read data block length */
+ unsigned int capacity; /* card capacity */
+};
+
+struct mmc_ext_csd {
+ unsigned int sectors;
+ unsigned int hs_max_dtr;
+ unsigned char rev;
+ unsigned char boot_info;
+ unsigned int boot_part_sz;
+ unsigned int rpmb_sz;
+ unsigned char ddr_support;
+ unsigned char hs400_support;
+ unsigned char part_cfg;
+ unsigned char sec_support;
+ unsigned char reset_en;
+};
+
+#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
+#define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */
+#define MMC_CAP_BYTEBLOCK (1 << 2) /* Can do non-log2 block sizes */
+#define MMC_CAP_MMC_HIGHSPEED (1 << 3) /* Can do MMC high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED (1 << 4) /* Can do SD high-speed timing */
+#define MMC_CAP_8_BIT_DATA (1 << 5) /* Can the host do 8 bit transfers */
+#define MMC_CAP_SD_UHS1 (1 << 6) /* Can do SD ultra-high-speed timing */
+#define MMC_CAP_DDR (1 << 7) /* The host support dual data rate */
+#define MMC_CAP_EMMC_HS200 (1 << 8) /* The host support dual data rate */
+#define MMC_CAP_EMMC_HS400 (1 << 9) /* The host support dual data rate */
+
+struct mmc_host {
+ u8 host_id;
+ struct mmc_card *card;
+ u32 max_phys_segs;
+ addr_t base; /* host base address */
+ addr_t base_top; /* top pad control base address */
+ u32 caps; /* Host capabilities */
+ u32 f_min; /* host min. frequency */
+ u32 f_max; /* host max. frequency */
+ u32 clk; /* host clock speed */
+ u32 sclk; /* SD/MS clock speed */
+ u32 blklen; /* block len */
+ u32 ocr; /* current ocr */
+ u32 ocr_avail; /* available ocr */
+ u32 timeout_ns; /* data timeout ns */
+ u32 timeout_clks; /* data timeout clks */
+ u8 clksrc; /* clock source */
+ u8 hclksrc; /* clock source */
+ u8 curr_part; /* host current working partition */
+ u32 intr_mask; /* Interrupt mask */
+ u32 time_read;
+ void *priv; /* private data */
+ mutex_t lock; /* mutex lock for multi-thread */
+ int (*blk_read)(struct mmc_host *host, u8 *dst, u32 src, u32 nblks);
+ int (*blk_write)(struct mmc_host *host, u32 dst, u8 *src, u32 nblks);
+};
+
+#define MMC_TYPE_UNKNOWN (0) /* Unknown card */
+#define MMC_TYPE_MMC (0x00000001) /* MMC card */
+#define MMC_TYPE_SD (0x00000002) /* SD card */
+#define MMC_TYPE_SDIO (0x00000004) /* SDIO card */
+
+/* MMC device */
+struct mmc_card {
+ struct mmc_host *host; /* the host this device belongs to */
+ unsigned int nblks;
+ unsigned int blklen;
+ unsigned int ocr;
+ unsigned int maxhz;
+ unsigned int uhs_mode;
+ unsigned int rca; /* relative card address of device */
+ unsigned int type; /* card type */
+ unsigned int sdio_funcs; /* number of SDIO functions */
+ unsigned short state; /* (our) card state */
+ unsigned short ready; /* card is ready or not */
+ u32 raw_csd[4]; /* raw card CSD */
+ struct mmc_csd csd; /* card specific */
+ struct mmc_ext_csd ext_csd; /* mmc v4 extended card specific */
+ u8 version; /* the SD card version, 1.0, 2.0, or 3.0*/
+};
+
+struct mmc_command {
+ u32 opcode;
+ u32 arg;
+ u32 rsptyp;
+ u32 resp[4];
+ u32 timeout;
+ u32 retries; /* max number of retries */
+ u32 error; /* command error */
+};
+
+struct mmc_data {
+ u8 *buf;
+ struct mmc_command *cmd;
+ u32 blks;
+ u32 timeout; /* ms */
+};
+
+#define mmc_card_mmc(c) ((c)->type & MMC_TYPE_MMC)
+#define mmc_card_sd(c) ((c)->type & MMC_TYPE_SD)
+
+#define mmc_card_set_host(c,h) ((c)->host = (h))
+#define mmc_card_set_unknown(c) ((c)->type = MMC_TYPE_UNKNOWN)
+#define mmc_card_set_mmc(c) ((c)->type |= MMC_TYPE_MMC)
+#define mmc_card_set_sd(c) ((c)->type |= MMC_TYPE_SD)
+
+#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT)
+#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY)
+#define mmc_card_backyard(c) ((c)->state & MMC_STATE_BACKYARD)
+#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED)
+#define mmc_card_uhs1(c) ((c)->state & MMC_STATE_UHS1)
+#define mmc_card_hs200(c) ((c)->state & MMC_STATE_HS200)
+#define mmc_card_hs400(c) ((c)->state & MMC_STATE_HS400)
+#define mmc_card_ddr(c) ((c)->state & MMC_STATE_DDR)
+#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR)
+#define mmc_card_highcaps(c) ((c)->state & MMC_STATE_HIGHCAPS)
+
+#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
+#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
+#define mmc_card_set_backyard(c) ((c)->state |= MMC_STATE_BACKYARD)
+#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED)
+#define mmc_card_set_uhs1(c) ((c)->state |= MMC_STATE_UHS1)
+#define mmc_card_set_hs200(c) ((c)->state |= MMC_STATE_HS200)
+#define mmc_card_set_hs400(c) ((c)->state |= MMC_STATE_HS400)
+#define mmc_card_set_ddr(c) ((c)->state |= MMC_STATE_DDR)
+#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
+
+#define mmc_card_clear_present(c) ((c)->state &= ~MMC_STATE_PRESENT)
+#define mmc_card_clear_readonly(c) ((c)->state &= ~MMC_STATE_READONLY)
+#define mmc_card_clear_highspeed(c) ((c)->state &= ~MMC_STATE_HIGHSPEED)
+#define mmc_card_clear_uhs1(c) ((c)->state &= ~MMC_STATE_UHS1)
+#define mmc_card_clear_hs200(c) ((c)->state &= ~MMC_STATE_HS200)
+#define mmc_card_clear_hs400(c) ((c)->state &= ~MMC_STATE_HS400)
+#define mmc_card_clear_ddr(c) ((c)->state &= ~MMC_STATE_DDR)
+#define mmc_card_clear_blockaddr(c) ((c)->state &= ~MMC_STATE_BLOCKADDR)
+
+#define mmc_card_clr_ddr(c) ((c)->state &= ~MMC_STATE_DDR)
+#define mmc_card_clr_speed_mode(c) ((c)->state &= ~(MMC_STATE_HS400 | MMC_STATE_HS200 | MMC_STATE_UHS1 | MMC_STATE_HIGHSPEED | MMC_STATE_BACKYARD))
+
+#define mmc_card_name(c) ((c)->cid.prod_name)
+
+#define mmc_op_multi(op) (((op) == MMC_CMD_READ_MULTIPLE_BLOCK) || \
+ ((op) == MMC_CMD_WRITE_MULTIPLE_BLOCK))
+
+struct mmc_card *emmc_init_stage1(bool *retry_opcond);
+int emmc_init_stage2(struct mmc_card *card, bool retry_opcond);
+int sdmmc_init(u8 host_id);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mmc_ioctl.h b/src/bsp/lk/platform/mt2731/include/platform/mmc_ioctl.h
new file mode 100644
index 0000000..6afd29b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mmc_ioctl.h
@@ -0,0 +1,76 @@
+#ifndef LINUX_MMC_IOCTL_H
+#define LINUX_MMC_IOCTL_H
+
+#include <sys/types.h>
+#include "generic_ioctl.h"
+
+struct mmc_ioc_cmd {
+ /* Implies direction of data. true = write, false = read */
+ int write_flag;
+
+ /* Application-specific command. true = precede with CMD55 */
+ int is_acmd;
+
+ u32 opcode;
+ u32 arg;
+ u32 response[4]; /* CMD response */
+ unsigned int flags;
+ unsigned int blksz;
+ unsigned int blocks;
+
+ /*
+ * Sleep at least postsleep_min_us useconds, and at most
+ * postsleep_max_us useconds *after* issuing command. Needed for
+ * some read commands for which cards have no other way of indicating
+ * they're ready for the next command (i.e. there is no equivalent of
+ * a "busy" indicator for read operations).
+ */
+ unsigned int postsleep_min_us;
+ unsigned int postsleep_max_us;
+
+ /*
+ * Override driver-computed timeouts. Note the difference in units!
+ */
+ unsigned int data_timeout_ns;
+ unsigned int cmd_timeout_ms;
+
+ /*
+ * For 64-bit machines, the next member, ``u64 data_ptr``, wants to
+ * be 8-byte aligned. Make sure this struct is the same size when
+ * built for 32-bit.
+ */
+ u32 __pad;
+
+ /* DAT buffer */
+ u64 data_ptr;
+};
+#define mmc_ioc_cmd_set_data(ic, ptr) ic.data_ptr = (u64)(unsigned long) ptr
+
+/**
+ * struct mmc_ioc_multi_cmd - multi command information
+ * @num_of_cmds: Number of commands to send. Must be equal to or less than
+ * MMC_IOC_MAX_CMDS.
+ * @cmds: Array of commands with length equal to 'num_of_cmds'
+ */
+struct mmc_ioc_multi_cmd {
+ u64 num_of_cmds;
+ struct mmc_ioc_cmd cmds[0];
+};
+
+#define MMC_BLOCK_MAJOR 179
+#define MMC_IOC_CMD _IOWR(MMC_BLOCK_MAJOR, 0, struct mmc_ioc_cmd)
+/*
+ * MMC_IOC_MULTI_CMD: Used to send an array of MMC commands described by
+ * the structure mmc_ioc_multi_cmd. The MMC driver will issue all
+ * commands in array in sequence to card.
+ */
+#define MMC_IOC_MULTI_CMD _IOWR(MMC_BLOCK_MAJOR, 1, struct mmc_ioc_multi_cmd)
+/*
+ * Since this ioctl is only meant to enhance (and not replace) normal access
+ * to the mmc bus device, an upper data transfer limit of MMC_IOC_MAX_BYTES
+ * is enforced per ioctl call. For larger data transfers, use the normal
+ * block device operations.
+ */
+#define MMC_IOC_MAX_BYTES (512L * 1024)
+#define MMC_IOC_MAX_CMDS 255
+#endif /* LINUX_MMC_IOCTL_H */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mmc_rpmb.h b/src/bsp/lk/platform/mt2731/include/platform/mmc_rpmb.h
new file mode 100644
index 0000000..237dff7
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mmc_rpmb.h
@@ -0,0 +1,59 @@
+
+
+#ifndef _MMC_RPMB_H
+#define _MMC_RPMB_H
+
+#include "mmc_core.h"
+
+/* ==================================================================================
+
+ RPMB definition
+
+====================================================================================*/
+#define RPMB_SZ_STUFF 196
+#define RPMB_SZ_MAC 32
+#define RPMB_SZ_DATA 256
+#define RPMB_SZ_NONCE 16
+
+#define RPMB_PROGRAM_KEY 1 /* Program RPMB Authentication Key */
+#define RPMB_GET_WRITE_COUNTER 2 /* Read RPMB write counter */
+#define RPMB_WRITE_DATA 3 /* Write data to RPMB partition */
+#define RPMB_READ_DATA 4 /* Read data from RPMB partition */
+#define RPMB_RESULT_READ 5 /* Read result request */
+#define RPMB_REQ 1 /* RPMB request mark */
+#define RPMB_RESP (1 << 1)/* RPMB response mark */
+#define RPMB_AVALIABLE_SECTORS 8 /* 4K page size */
+
+#define RPMB_TYPE_BEG 510
+#define RPMB_RES_BEG 508
+#define RPMB_BLKS_BEG 506
+#define RPMB_ADDR_BEG 504
+#define RPMB_WCOUNTER_BEG 500
+
+#define RPMB_NONCE_BEG 484
+#define RPMB_DATA_BEG 228
+#define RPMB_MAC_BEG 196
+
+struct mmc_rpmb_cfg {
+ u16 type; /* RPMB request type */
+ u16 result; /* response or request result */
+ u16 blk_cnt; /* Number of blocks(half sector 256B) */
+ u16 addr; /* data address */
+ u32 *wc; /* write counter */
+ u8 *nonce; /* Ramdom number */
+ u8 *data; /* Buffer of the user data */
+ u8 *mac; /* Message Authentication Code */
+};
+
+struct mmc_rpmb_req {
+ struct mmc_rpmb_cfg *rpmb_cfg;
+ u8 *data_frame;
+};
+
+extern int mmc_rpmb_set_key(u8 *key);
+extern u32 mmc_rpmb_get_size(void);
+extern u32 mmc_rpmb_get_rel_wr_sec_c(void);
+
+extern int mmc_rpmb_block_read(int blknr, unsigned char blk[256]);
+extern int mmc_rpmb_block_write(int blknr, unsigned char blk[256]);
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/msdc.h b/src/bsp/lk/platform/mt2731/include/platform/msdc.h
new file mode 100644
index 0000000..9ef29de
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/msdc.h
@@ -0,0 +1,1321 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <reg.h>
+#include <platform/msdc_cfg.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mmc_core.h>
+
+/*--------------------------------------------------------------------------*/
+/* Common Macro */
+/*--------------------------------------------------------------------------*/
+#define REG_ADDR(x) ((volatile uint32_t *)(uintptr_t)(base + OFFSET_##x))
+
+/*--------------------------------------------------------------------------*/
+/* Common Definition */
+/*--------------------------------------------------------------------------*/
+#define MSDC_FIFO_SZ (128)
+#define MSDC_FIFO_THD (128)
+//#define MSDC_MAX_NUM (2)
+
+#define MSDC_MS (0)
+#define MSDC_SDMMC (1)
+
+#define MSDC_MODE_UNKNOWN (0)
+#define MSDC_MODE_PIO (1)
+#define MSDC_MODE_DMA_BASIC (2)
+#define MSDC_MODE_DMA_DESC (3)
+#define MSDC_MODE_DMA_ENHANCED (4)
+#define MSDC_MODE_MMC_STREAM (5)
+
+#define MSDC_BUS_1BITS (0)
+#define MSDC_BUS_4BITS (1)
+#define MSDC_BUS_8BITS (2)
+
+#define MSDC_BURST_8B (3)
+#define MSDC_BURST_16B (4)
+#define MSDC_BURST_32B (5)
+#define MSDC_BURST_64B (6)
+
+#define MSDC_PIN_PULL_NONE (0)
+#define MSDC_PIN_PULL_DOWN (1)
+#define MSDC_PIN_PULL_UP (2)
+#define MSDC_PIN_KEEP (3)
+
+#ifdef FPGA_PLATFORM
+#define MSDC_OP_SCLK (10000000)
+#define MSDC_MAX_SCLK MSDC_OP_SCLK / 2
+#else
+#define MSDC_OP_SCLK (200000000)
+#define MSDC_MAX_SCLK (200000000)
+#endif
+
+#define MSDC_MIN_SCLK (260000)
+
+#define MSDC_350K_SCLK (350000)
+#define MSDC_400K_SCLK (400000)
+#define MSDC_25M_SCLK (25000000)
+#define MSDC_26M_SCLK (26000000)
+#define MSDC_50M_SCLK (50000000)
+#define MSDC_52M_SCLK (52000000)
+#define MSDC_100M_SCLK (100000000)
+#define MSDC_179M_SCLK (179000000)
+#define MSDC_200M_SCLK (200000000)
+#define MSDC_208M_SCLK (208000000)
+#define MSDC_400M_SCLK (400000000)
+#define MSDC_800M_SCLK (800000000)
+
+#define MSDC_AUTOCMD12 (0x0001)
+#define MSDC_AUTOCMD23 (0x0002)
+#define MSDC_AUTOCMD19 (0x0003)
+
+#define TYPE_CMD_RESP_EDGE (0)
+#define TYPE_WRITE_CRC_EDGE (1)
+#define TYPE_READ_DATA_EDGE (2)
+#define TYPE_WRITE_DATA_EDGE (3)
+
+#define START_AT_RISING (0x0)
+#define START_AT_FALLING (0x1)
+#define START_AT_RISING_AND_FALLING (0x2)
+#define START_AT_RISING_OR_FALLING (0x3)
+
+#define MSDC_DMA_BURST_8B (3)
+#define MSDC_DMA_BURST_16B (4)
+#define MSDC_DMA_BURST_32B (5)
+#define MSDC_DMA_BURST_64B (6)
+
+/*--------------------------------------------------------------------------*/
+/* Register Offset */
+/*--------------------------------------------------------------------------*/
+#define OFFSET_MSDC_CFG (0x00)
+#define OFFSET_MSDC_IOCON (0x04)
+#define OFFSET_MSDC_PS (0x08)
+#define OFFSET_MSDC_INT (0x0c)
+#define OFFSET_MSDC_INTEN (0x10)
+#define OFFSET_MSDC_FIFOCS (0x14)
+#define OFFSET_MSDC_TXDATA (0x18)
+#define OFFSET_MSDC_RXDATA (0x1c)
+#define OFFSET_SDC_CFG (0x30)
+#define OFFSET_SDC_CMD (0x34)
+#define OFFSET_SDC_ARG (0x38)
+#define OFFSET_SDC_STS (0x3c)
+#define OFFSET_SDC_RESP0 (0x40)
+#define OFFSET_SDC_RESP1 (0x44)
+#define OFFSET_SDC_RESP2 (0x48)
+#define OFFSET_SDC_RESP3 (0x4c)
+#define OFFSET_SDC_BLK_NUM (0x50)
+#define OFFSET_SDC_VOL_CHG (0x54)
+#define OFFSET_SDC_CSTS (0x58)
+#define OFFSET_SDC_CSTS_EN (0x5c)
+#define OFFSET_SDC_DCRC_STS (0x60)
+#define OFFSET_SDC_ADV_CFG0 (0x64)
+/* Only for EMMC Controller 4 registers below */
+#define OFFSET_EMMC_CFG0 (0x70)
+#define OFFSET_EMMC_CFG1 (0x74)
+#define OFFSET_EMMC_STS (0x78)
+#define OFFSET_EMMC_IOCON (0x7c)
+#define OFFSET_SDC_ACMD_RESP (0x80)
+#define OFFSET_SDC_ACMD19_TRG (0x84)
+#define OFFSET_SDC_ACMD19_STS (0x88)
+#define OFFSET_MSDC_DMA_SA_HIGH (0x8C)
+#define OFFSET_MSDC_DMA_SA (0x90)
+#define OFFSET_MSDC_DMA_CA (0x94)
+#define OFFSET_MSDC_DMA_CTRL (0x98)
+#define OFFSET_MSDC_DMA_CFG (0x9c)
+#define OFFSET_MSDC_DBG_SEL (0xa0)
+#define OFFSET_MSDC_DBG_OUT (0xa4)
+#define OFFSET_MSDC_DMA_LEN (0xa8)
+#define OFFSET_MSDC_PATCH_BIT0 (0xb0)
+#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
+#define OFFSET_MSDC_PATCH_BIT2 (0xb8)
+/* Only for SD/SDIO Controller 6 registers below */
+#define OFFSET_DAT0_TUNE_CRC (0xc0)
+#define OFFSET_DAT1_TUNE_CRC (0xc4)
+#define OFFSET_DAT2_TUNE_CRC (0xc8)
+#define OFFSET_DAT3_TUNE_CRC (0xcc)
+#define OFFSET_CMD_TUNE_CRC (0xd0)
+#define OFFSET_SDIO_TUNE_WIND (0xd4)
+#define OFFSET_MSDC_PAD_TUNE0 (0xf0)
+#define OFFSET_MSDC_PAD_TUNE1 (0xf4)
+#define OFFSET_MSDC_DAT_RDDLY0 (0xf8)
+#define OFFSET_MSDC_DAT_RDDLY1 (0xfc)
+#define OFFSET_MSDC_DAT_RDDLY2 (0x100)
+#define OFFSET_MSDC_DAT_RDDLY3 (0x104)
+#define OFFSET_MSDC_HW_DBG (0x110)
+#define OFFSET_MSDC_VERSION (0x114)
+#define OFFSET_MSDC_ECO_VER (0x118)
+/* Only for EMMC 5.0 Controller 4 registers below */
+#define OFFSET_EMMC50_PAD_CTL0 (0x180)
+#define OFFSET_EMMC50_PAD_DS_CTL0 (0x184)
+#define OFFSET_EMMC50_PAD_DS_TUNE (0x188)
+#define OFFSET_EMMC50_PAD_CMD_TUNE (0x18c)
+#define OFFSET_EMMC50_PAD_DAT01_TUNE (0x190)
+#define OFFSET_EMMC50_PAD_DAT23_TUNE (0x194)
+#define OFFSET_EMMC50_PAD_DAT45_TUNE (0x198)
+#define OFFSET_EMMC50_PAD_DAT67_TUNE (0x19c)
+#define OFFSET_EMMC51_CFG0 (0x204)
+#define OFFSET_EMMC50_CFG0 (0x208)
+#define OFFSET_EMMC50_CFG1 (0x20c)
+#define OFFSET_EMMC50_CFG2 (0x21c)
+#define OFFSET_EMMC50_CFG3 (0x220)
+#define OFFSET_EMMC50_CFG4 (0x224)
+#define OFFSET_SDC_FIFO_CFG (0x228)
+/*--------------------------------------------------------------------------*/
+/* Register Address */
+/*--------------------------------------------------------------------------*/
+/* common register */
+#define MSDC_CFG REG_ADDR(MSDC_CFG)
+#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
+#define MSDC_PS REG_ADDR(MSDC_PS)
+#define MSDC_INT REG_ADDR(MSDC_INT)
+#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
+#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
+#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
+#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
+
+/* sdmmc register */
+#define SDC_CFG REG_ADDR(SDC_CFG)
+#define SDC_CMD REG_ADDR(SDC_CMD)
+#define SDC_ARG REG_ADDR(SDC_ARG)
+#define SDC_STS REG_ADDR(SDC_STS)
+#define SDC_RESP0 REG_ADDR(SDC_RESP0)
+#define SDC_RESP1 REG_ADDR(SDC_RESP1)
+#define SDC_RESP2 REG_ADDR(SDC_RESP2)
+#define SDC_RESP3 REG_ADDR(SDC_RESP3)
+#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
+#define SDC_VOL_CHG REG_ADDR(SDC_VOL_CHG)
+#define SDC_CSTS REG_ADDR(SDC_CSTS)
+#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
+#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
+#define SDC_ADV_CFG0 REG_ADDR(SDC_ADV_CFG0)
+
+/* emmc register*/
+#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
+#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
+#define EMMC_STS REG_ADDR(EMMC_STS)
+#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
+
+/* auto command register */
+#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
+#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
+#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
+
+/* dma register */
+#define MSDC_DMA_SA_HIGH REG_ADDR(MSDC_DMA_SA_HIGH)
+#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
+#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
+#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
+#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
+#define MSDC_DMA_LEN REG_ADDR(MSDC_DMA_LEN)
+
+/* data read delay */
+#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
+#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
+#define MSDC_DAT_RDDLY2 REG_ADDR(MSDC_DAT_RDDLY2)
+#define MSDC_DAT_RDDLY3 REG_ADDR(MSDC_DAT_RDDLY3)
+
+/* debug register */
+#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
+#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
+
+/* misc register */
+#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT0)
+#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
+#define MSDC_PATCH_BIT2 REG_ADDR(MSDC_PATCH_BIT2)
+#define DAT0_TUNE_CRC REG_ADDR(DAT0_TUNE_CRC)
+#define DAT1_TUNE_CRC REG_ADDR(DAT1_TUNE_CRC)
+#define DAT2_TUNE_CRC REG_ADDR(DAT2_TUNE_CRC)
+#define DAT3_TUNE_CRC REG_ADDR(DAT3_TUNE_CRC)
+#define CMD_TUNE_CRC REG_ADDR(CMD_TUNE_CRC)
+#define SDIO_TUNE_WIND REG_ADDR(SDIO_TUNE_WIND)
+#define MSDC_PAD_TUNE0 REG_ADDR(MSDC_PAD_TUNE0)
+#define MSDC_PAD_TUNE1 REG_ADDR(MSDC_PAD_TUNE1)
+#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
+#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
+#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER)
+/* eMMC 5.0 register */
+#define EMMC50_PAD_CTL0 REG_ADDR(EMMC50_PAD_CTL0)
+#define EMMC50_PAD_DS_CTL0 REG_ADDR(EMMC50_PAD_DS_CTL0)
+#define EMMC50_PAD_DS_TUNE REG_ADDR(EMMC50_PAD_DS_TUNE)
+#define EMMC50_PAD_CMD_TUNE REG_ADDR(EMMC50_PAD_CMD_TUNE)
+#define EMMC50_PAD_DAT01_TUNE REG_ADDR(EMMC50_PAD_DAT01_TUNE)
+#define EMMC50_PAD_DAT23_TUNE REG_ADDR(EMMC50_PAD_DAT23_TUNE)
+#define EMMC50_PAD_DAT45_TUNE REG_ADDR(EMMC50_PAD_DAT45_TUNE)
+#define EMMC50_PAD_DAT67_TUNE REG_ADDR(EMMC50_PAD_DAT67_TUNE)
+#define EMMC51_CFG0 REG_ADDR(EMMC51_CFG0)
+#define EMMC50_CFG0 REG_ADDR(EMMC50_CFG0)
+#define EMMC50_CFG1 REG_ADDR(EMMC50_CFG1)
+#define EMMC50_CFG2 REG_ADDR(EMMC50_CFG2)
+#define EMMC50_CFG3 REG_ADDR(EMMC50_CFG3)
+#define EMMC50_CFG4 REG_ADDR(EMMC50_CFG4)
+#define SDC_FIFO_CFG REG_ADDR(SDC_FIFO_CFG)
+#define MSDC_AES_SEL REG_ADDR(MSDC_AES_SEL)
+
+/* HW CMDQ registger */
+#define MTKCQ_CFG0 REG_ADDR(MTKCQ_CFG0)
+#define MTKCQ_CFG1 REG_ADDR(MTKCQ_CFG1)
+#define MTKCQ_CFG2 REG_ADDR(MTKCQ_CFG2)
+#define MTKCQ_ERR_ST REG_ADDR(MTKCQ_ERR_ST)
+#define MTKCQ_CMD45_READY REG_ADDR(MTKCQ_CMD45_READY)
+#define MTKCQ_TASK_READY_ST REG_ADDR(MTKCQ_TASK_READY_ST)
+#define MTKCQ_TASK_DONE_ST REG_ADDR(MTKCQ_TASK_DONE_ST)
+#define MTKCQ_ERR_ST_CLR REG_ADDR(MTKCQ_ERR_ST_CLR)
+#define MTKCQ_CMD_DONE_CLR REG_ADDR(MTKCQ_CMD_DONE_CLR)
+#define MTKCQ_SW_CTL_CQ REG_ADDR(MTKCQ_SW_CTL_CQ)
+#define MTKCQ_CMD44_RESP REG_ADDR(MTKCQ_CMD44_RESP)
+#define MTKCQ_CMD45_RESP REG_ADDR(MTKCQ_CMD45_RESP)
+#define MTKCQ_CMD13_RCA REG_ADDR(MTKCQ_CMD13_RCA)
+#define EMMC51_CQCB_CFG3 REG_ADDR(EMMC51_CQCB_CFG3)
+#define EMMC51_CQCB_CMD44 REG_ADDR(EMMC51_CQCB_CMD44)
+#define EMMC51_CQCB_CMD45 REG_ADDR(EMMC51_CQCB_CMD45)
+#define EMMC51_CQCB_TIDMAP REG_ADDR(EMMC51_CQCB_TIDMAP)
+#define EMMC51_CQCB_TIDMAPCLR REG_ADDR(EMMC51_CQCB_TIDMAPCLR)
+#define EMMC51_CQCB_CURCMD REG_ADDR(EMMC51_CQCB_CURCMD)
+
+/*--------------------------------------------------------------------------*/
+/* Register Mask */
+/*--------------------------------------------------------------------------*/
+
+/* MSDC_CFG mask */
+#define MSDC_CFG_MODE (0x1 << 0) /* RW */
+#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
+#define MSDC_CFG_RST (0x1 << 2) /* A0 */
+#define MSDC_CFG_PIO (0x1 << 3) /* RW */
+#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
+#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
+#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
+#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
+#define MSDC_CFG_CKDIV (0xfff << 8) /* RW */
+#define MSDC_CFG_CKDIV_BITS (12)
+#define MSDC_CFG_CKMOD (0x3 << 20) /* W1C */
+#define MSDC_CFG_CKMOD_BITS (2)
+#define MSDC_CFG_CKMOD_HS400 (0x1 << 22) /* RW */
+#define MSDC_CFG_START_BIT (0x3 << 23) /* RW */
+#define MSDC_CFG_SCLK_STOP_DDR (0x1 << 25) /* RW */
+#define MSDC_CFG_DVFS_EN (0x1 << 30) /* RW */
+
+/* MSDC_IOCON mask */
+#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
+#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
+#define MSDC_IOCON_R_D_SMPL (0x1 << 2) /* RW */
+#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
+#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
+#define MSDC_IOCON_R_D_SMPL_SEL (0x1 << 5) /* RW */
+#define MSDC_IOCON_W_D_SMPL (0x1 << 8) /* RW */
+#define MSDC_IOCON_W_D_SMPL_SEL (0x1 << 9) /* RW */
+#define MSDC_IOCON_W_D0SPL (0x1 << 10) /* RW */
+#define MSDC_IOCON_W_D1SPL (0x1 << 11) /* RW */
+#define MSDC_IOCON_W_D2SPL (0x1 << 12) /* RW */
+#define MSDC_IOCON_W_D3SPL (0x1 << 13) /* RW */
+#define MSDC_IOCON_R_D0SPL (0x1 << 16) /* RW */
+#define MSDC_IOCON_R_D1SPL (0x1 << 17) /* RW */
+#define MSDC_IOCON_R_D2SPL (0x1 << 18) /* RW */
+#define MSDC_IOCON_R_D3SPL (0x1 << 19) /* RW */
+#define MSDC_IOCON_R_D4SPL (0x1 << 20) /* RW */
+#define MSDC_IOCON_R_D5SPL (0x1 << 21) /* RW */
+#define MSDC_IOCON_R_D6SPL (0x1 << 22) /* RW */
+#define MSDC_IOCON_R_D7SPL (0x1 << 23) /* RW */
+
+/* MSDC_PS mask */
+#define MSDC_PS_CDEN (0x1 << 0) /* RW */
+#define MSDC_PS_CDSTS (0x1 << 1) /* R */
+#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
+#define MSDC_PS_DAT (0xff << 16) /* R */
+#define MSDC_PS_DAT8PIN (0xFF << 16) /* RU */
+#define MSDC_PS_DAT4PIN (0xF << 16) /* RU */
+#define MSDC_PS_DAT0 (0x1 << 16) /* RU */
+
+#define MSDC_PS_CMD (0x1 << 24) /* RU */
+
+#define MSDC_PS_WP (0x1 << 31) /* RU */
+
+/* MSDC_INT mask */
+#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
+#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
+
+#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
+#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
+#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
+#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
+#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C Only for SD/SDIO */
+#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
+#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
+#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
+#define MSDC_INT_CSTA (0x1 << 11) /* R */
+#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
+#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
+#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
+#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
+#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
+#define MSDC_INT_BDCSERR (0x1 << 17) /* W1C */
+#define MSDC_INT_GPDCSERR (0x1 << 18) /* W1C */
+#define MSDC_INT_DMAPRO (0x1 << 19) /* W1C */
+#define MSDC_INT_GEAR_OUT_BOUND (0x1 << 20) /* W1C */
+#define MSDC_INT_ACMD53_DONE (0x1 << 21) /* W1C */
+#define MSDC_INT_ACMD53_FAIL (0x1 << 22) /* W1C */
+#define MSDC_INT_AXI_RESP_ERR (0x1 << 23) /* W1C */
+
+/* MSDC_INTEN mask */
+#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
+#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
+
+#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
+#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
+#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
+#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
+#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW Only for SDIO*/
+#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
+#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
+#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
+#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
+#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
+#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
+#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
+#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
+#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
+#define MSDC_INTEN_BDCSERR (0x1 << 17) /* RW */
+#define MSDC_INTEN_GPDCSERR (0x1 << 18) /* RW */
+#define MSDC_INTEN_DMAPRO (0x1 << 19) /* RW */
+#define MSDC_INTEN_GOBOUND (0x1 << 20) /* RW Only for SD/SDIO ACMD 53*/
+#define MSDC_INTEN_ACMD53_DONE (0x1 << 21) /* RW Only for SD/SDIO ACMD 53*/
+#define MSDC_INTEN_ACMD53_FAIL (0x1 << 22) /* RW Only for SD/SDIO ACMD 53*/
+#define MSDC_INTEN_AXI_RESP_ERR (0x1 << 23) /* RW Only for eMMC 5.0*/
+
+#define MSDC_INTEN_DFT ( MSDC_INTEN_MMCIRQ |MSDC_INTEN_CDSC | MSDC_INTEN_ACMDRDY\
+ |MSDC_INTEN_ACMDTMO |MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_DMAQ_EMPTY /*|MSDC_INTEN_SDIOIRQ*/\
+ |MSDC_INTEN_CMDRDY |MSDC_INTEN_CMDTMO | MSDC_INTEN_RSPCRCERR |MSDC_INTEN_CSTA\
+ |MSDC_INTEN_XFER_COMPL |MSDC_INTEN_DXFER_DONE | MSDC_INTEN_DATTMO |MSDC_INTEN_DATCRCERR\
+ |MSDC_INTEN_BDCSERR |MSDC_INTEN_ACMD19_DONE | MSDC_INTEN_GPDCSERR /*|MSDC_INTEN_DMAPRO*/\
+ /*|MSDC_INTEN_GOBOUND |MSDC_INTEN_ACMD53_DONE |MSDC_INTEN_ACMD53_FAIL |MSDC_INTEN_AXI_RESP_ERR*/)
+
+
+/* MSDC_FIFOCS mask */
+#define MSDC_FIFOCS_RXCNT (0xFF << 0) /* R */
+#define MSDC_FIFOCS_TXCNT (0xFF << 16) /* R */
+#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
+
+/* SDC_CFG mask */
+#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
+#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
+#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
+#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
+#define SDC_CFG_SDIO (0x1 << 19) /* RW */
+#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
+#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
+#define SDC_CFG_DTOC (0xFF << 24) /* RW */
+
+/* SDC_CMD mask */
+#define SDC_CMD_OPC (0x3F << 0) /* RW */
+#define SDC_CMD_BRK (0x1 << 6) /* RW */
+#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
+#define SDC_CMD_DTYP (0x3 << 11) /* RW */
+#define SDC_CMD_RW (0x1 << 13) /* RW */
+#define SDC_CMD_STOP (0x1 << 14) /* RW */
+#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
+#define SDC_CMD_BLKLEN (0xFFF << 16) /* RW */
+#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
+#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
+#define SDC_CMD_ACMD53 (0x1 << 31) /* RW Only for SD/SDIO ACMD 53*/
+
+/* SDC_STS mask */
+#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
+#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
+#define SDC_STS_START_BIT_CRCERR (0x1 << 2)
+#define SDC_STS_CMD_WR_BUSY (0x1 << 16) /* RW !!! MT2701 Add*/
+#define SDC_STS_DATA_TIMEOUT_TYPE (0x3 << 17) /* RU */
+#define SDC_STS_CMD_TIMEOUT_TYPE (0x3 << 19) /* RU */
+#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
+
+/* SDC_VOL_CHG mask */
+#define SDC_VOL_CHG_CNT (0xffff << 0) /* RW */
+/* SDC_DCRC_STS mask */
+#define SDC_DCRC_STS_POS (0xFF << 0) /* RO */
+#define SDC_DCRC_STS_NEG (0xFF << 8) /* RO */
+
+/* SDC_ADV_CFG0 mask */
+#define SDC_ADV_CFG0_RESP_CRC (0x7f << 0) /* RU */
+#define SDC_ADV_CFG0_RESP_INDEX (0x3f << 7) /* RU */
+#define SDC_ADV_CFG0_RESP_ENDBIT (0x1 << 13) /* RU */
+#define SDC_ADV_CFG0_ENDBIT_CHECK (0x1 << 14) /* RW */
+#define SDC_ADV_CFG0_INDEX_CHECK (0x1 << 15) /* RW */
+#define SDC_ADV_CFG0_DAT_BUF_CLK_DIV (0x3 << 16) /* RW */
+#define SDC_ADV_CFG0_DAT_BUF_FREQ_CTL_EN (0x1 << 18) /* RW */
+#define SDC_ADV_CFG0_SDIO_IRQ_ENHANCE_EN (0x1 << 19) /* RW */
+#define SDC_ADV_CFG0_SDC_RX_ENH_EN (0x1 << 20) /* RW */
+
+/* EMMC_CFG0 mask */
+#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* WO Only for eMMC */
+#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* WO Only for eMMC */
+#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW Only for eMMC */
+#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW Only for eMMC */
+
+#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW Only for eMMC */
+#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW Only for eMMC */
+
+/* EMMC_CFG1 mask */
+#define EMMC_CFG1_BOOTDATTMC (0xFFFFF<< 0) /* RW Only for eMMC */
+#define EMMC_CFG1_BOOTACKTMC (0xFFF << 20) /* RW Only for eMMC */
+
+/* EMMC_STS mask */
+#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C Only for eMMC */
+#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C Only for eMMC */
+#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C Only for eMMC */
+#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C Only for eMMC */
+#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* RU Only for eMMC */
+#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C Only for eMMC */
+#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* RU Only for eMMC */
+
+/* EMMC_IOCON mask */
+#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW Only for eMMC */
+
+/* SDC_ACMD19_TRG mask */
+#define SDC_ACMD19_TRG_TUNESEL (0xF << 0) /* RW */
+
+/* MSDC_DMA_SA_HIGH */
+#define MSDC_DMA_SURR_ADDR_HIGH4BIT (0xf << 0) /* RW */
+
+/* MSDC_DMA_CTRL mask */
+#define MSDC_DMA_CTRL_START (0x1 << 0) /* WO */
+#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
+#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
+#define MSDC_DMA_CTRL_REDAYM (0x1 << 3) /* RO */
+#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
+#define MSDC_DMA_CTRL_ALIGN (0x1 << 9) /* RW */
+#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
+#define MSDC_DMA_CTRL_SPLIT1K (0x1 << 11) /* RW */
+#define MSDC_DMA_CTRL_BURSTSZ (0x7 << 12) /* RW */
+
+/* MSDC_DMA_CFG mask */
+#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
+#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
+#define MSDC_DMA_CFG_LOCKDISABLE (0x1 << 2) /* RW */
+#define MSDC_DMA_CFG_AHBEN (0x3 << 8) /* RW */
+#define MSDC_DMA_CFG_ACTEN (0x3 << 12) /* RW */
+#define MSDC_DMA_CFG_CS12B (0x1 << 16) /* RW */
+
+/* MSDC_PATCH_BIT0 mask */
+#define MSDC_PB0_EN_START_BIT_CHK_SUP (0x1 << 0)
+#define MSDC_PB0_EN_8BITSUP (0x1 << 1)
+#define MSDC_PB0_DIS_RECMDWR (0x1 << 2)
+#define MSDC_PB0_RD_DAT_SEL (0x1 << 3)
+#define MSDC_PB0_RESV2 (0x3 << 4)
+#define MSDC_PB0_DESCUP (0x1 << 6)
+#define MSDC_PB0_INT_DAT_LATCH_CK_SEL (0x7 << 7)
+#define MSDC_PB0_CKGEN_MSDC_DLY_SEL (0x1F<<10)
+#define MSDC_PB0_FIFORD_DIS (0x1 << 15)
+#define MSDC_PB0_BLKNUM_SEL (0x1 << 16)
+#define MSDC_PB0_SDIO_INTCSEL (0x1 << 17)
+#define MSDC_PB0_SDC_BSYDLY (0xf << 18)
+#define MSDC_PB0_SDC_WDOD (0xf << 22)
+#define MSDC_PB0_CMDIDRTSEL (0x1 << 26)
+#define MSDC_PB0_CMDFAILSEL (0x1 << 27)
+#define MSDC_PB0_SDIO_INTDLYSEL (0x1 << 28)
+#define MSDC_PB0_SPCPUSH (0x1 << 29)
+#define MSDC_PB0_DETWR_CRCTMO (0x1 << 30)
+#define MSDC_PB0_EN_DRVRSP (0x1 << 31) /* RW */
+
+/* MSDC_PATCH_BIT1 mask */
+#define MSDC_PB1_WRDAT_CRCS_TA_CNTR (0x7 << 0)
+#define MSDC_PB1_CMD_RSP_TA_CNTR (0x7 << 3)
+#define MSDC_PB1_GET_BUSY_MA (0x1 << 6)
+#define MSDC_PB1_CHECK_BUSY_SEL (0x1 << 7)
+#define MSDC_PB1_STOP_DLY_SEL (0xf << 8)
+#define MSDC_PB1_BIAS_EN18IO_28NM (0x1 << 12)
+#define MSDC_PB1_BIAS_EXT_28NM (0x1 << 13)
+#define MSDC_PB1_DDR_CMD_FIX_SEL (0x1 << 14)
+#define MSDC_PB1_RESET_GDMA (0x1 << 15)
+#define MSDC_PB1_SINGLE_BURST (0x1 << 16)
+#define MSDC_PB1_FROCE_STOP (0x1 << 17)
+#define MSDC_PB1_STATE_CLR (0x1 << 19)
+#define MSDC_PB1_POP_MARK_WATER (0x1 << 20)
+#define MSDC_PB1_DCM_EN (0x1 << 21)
+#define MSDC_PB1_AXI_WRAP_CKEN (0x1 << 22)
+#define MSDC_PB1_CKCLK_GDMA_EN (0x1 << 23)
+#define MSDC_PB1_CKSPCEN (0x1 << 24)
+#define MSDC_PB1_CKPSCEN (0x1 << 25)
+#define MSDC_PB1_CKVOLDETEN (0x1 << 26)
+#define MSDC_PB1_CKACMDEN (0x1 << 27)
+#define MSDC_PB1_CKSDEN (0x1 << 28) /* RW */
+#define MSDC_PB1_CKWCTLEN (0x1 << 29) /* RW */
+#define MSDC_PB1_CKRCTLEN (0x1 << 30) /* RW */
+#define MSDC_PB1_CKSHBFFEN (0x1 << 31) /* RW */
+
+/* MSDC_PATCH_BIT2 mask */
+#define MSDC_PB2_ENHANCEGPD (0x1 << 0) /* RW !!! MT2701 Add */
+#define MSDC_PB2_SUPPORT64G (0x1 << 1) /* RW !!! MT2701 Add */
+#define MSDC_PB2_RESPWAITCNT (0x3 << 2)
+#define MSDC_PB2_CFGRDATCNT (0x1f << 4)
+#define MSDC_PB2_CFGRDAT (0x1 << 9)
+#define MSDC_PB2_INTCRESPSEL (0x1 << 11)
+#define MSDC_PB2_CFGRESPCNT (0x7 << 12)
+#define MSDC_PB2_CFGRESP (0x1 << 15)
+#define MSDC_PB2_RESPSTENSEL (0x7 << 16)
+#define MSDC_PB2_DDR50_SEL (0x1 << 19)
+#define MSDC_PB2_POPENCNT (0xf << 20)
+#define MSDC_PB2_CFG_CRCSTS_SEL (0x1 << 24)
+#define MSDC_PB2_CFGCRCSTSEDGE (0x1 << 25)
+#define MSDC_PB2_CFGCRCSTSCNT (0x3 << 26)
+#define MSDC_PB2_CFGCRCSTS (0x1 << 28)
+#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW !!! MT2701 Add */
+
+#define MSDC_MASK_ACMD53_CRC_ERR_INTR (0x1<<4)
+#define MSDC_ACMD53_FAIL_ONE_SHOT (0X1<<5)
+
+/* MSDC_PAD_TUNE mask */
+#define MSDC_PAD_TUNE0_DATWRDLY (0x1F << 0) /* RW */
+#define MSDC_PAD_TUNE0_DELAYEN (0x1 << 7) /* RW */
+#define MSDC_PAD_TUNE0_DATRRDLY (0x1F << 8) /* RW */
+#define MSDC_PAD_TUNE0_DATRRDLYSEL (0x1 << 13) /* RW */
+#define MSDC_PAD_TUNE0_RXDLYSEL (0x1 << 15) /* RW */
+#define MSDC_PAD_TUNE0_CMDRDLY (0x1F << 16) /* RW */
+#define MSDC_PAD_TUNE0_CMDRRDLYSEL (0x1 << 21) /* RW */
+#define MSDC_PAD_TUNE0_CMDRRDLY (0x1F << 22) /* RW */
+#define MSDC_PAD_TUNE0_CLKTXDLY (0x1F << 27) /* RW */
+
+/* MSDC_PAD_TUNE1 mask */
+#define MSDC_PAD_TUNE1_DATRRDLY2 (0x1F << 8) /* RW */
+#define MSDC_PAD_TUNE1_DATRRDLY2SEL (0x1 << 13) /* RW */
+#define MSDC_PAD_TUNE1_CMDRDLY2 (0x1F << 16) /* RW */
+#define MSDC_PAD_TUNE1_CMDRRDLY2SEL (0x1 << 21) /* RW */
+
+/* MSDC_DAT_RDDLY0 mask */
+#define MSDC_DAT_RDDLY0_D3 (0x1F << 0) /* RW */
+#define MSDC_DAT_RDDLY0_D2 (0x1F << 8) /* RW */
+#define MSDC_DAT_RDDLY0_D1 (0x1F << 16) /* RW */
+#define MSDC_DAT_RDDLY0_D0 (0x1F << 24) /* RW */
+
+/* MSDC_DAT_RDDLY1 mask */
+#define MSDC_DAT_RDDLY1_D7 (0x1F << 0) /* RW */
+
+#define MSDC_DAT_RDDLY1_D6 (0x1F << 8) /* RW */
+
+#define MSDC_DAT_RDDLY1_D5 (0x1F << 16) /* RW */
+
+#define MSDC_DAT_RDDLY1_D4 (0x1F << 24) /* RW */
+
+/* MSDC_DAT_RDDLY2 mask */
+#define MSDC_DAT_RDDLY2_D3 (0x1F << 0) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY2_D2 (0x1F << 8) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY2_D1 (0x1F << 16) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY2_D0 (0x1F << 24) /* RW !!! MT2701 Add*/
+
+/* MSDC_DAT_RDDLY3 mask */
+#define MSDC_DAT_RDDLY3_D7 (0x1F << 0) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY3_D6 (0x1F << 8) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY3_D5 (0x1F << 16) /* RW !!! MT2701 Add*/
+
+#define MSDC_DAT_RDDLY3_D4 (0x1F << 24) /* RW !!! MT2701 Add*/
+
+/* MSDC_HW_DBG_SEL mask */
+#define MSDC_HW_DBG0_SEL (0xFF << 0) /* RW DBG3->DBG0 !!! MT2701 Change*/
+#define MSDC_HW_DBG1_SEL (0x3F << 8) /* RW DBG2->DBG1 !!! MT2701 Add*/
+
+#define MSDC_HW_DBG2_SEL (0xFF << 16) /* RW DBG1->DBG2 !!! MT2701 Add*/
+#define MSDC_HW_DBG3_SEL (0x3F << 24) /* RW DBG0->DBG3 !!! MT2701 Add*/
+#define MSDC_HW_DBG_WRAPTYPE_SEL (0x1 << 30)
+
+/* MSDC_EMMC50_PAD_CTL0 mask*/
+#define MSDC_EMMC50_PAD_CTL0_DCCSEL (0x1 << 0)
+#define MSDC_EMMC50_PAD_CTL0_HLSEL (0x1 << 1) /* RW */
+#define MSDC_EMMC50_PAD_CTL0_DLP0 (0x3 << 2) /* RW */
+#define MSDC_EMMC50_PAD_CTL0_DLN0 (0x3 << 4) /* RW */
+#define MSDC_EMMC50_PAD_CTL0_DLP1 (0x3 << 6) /* RW */
+#define MSDC_EMMC50_PAD_CTL0_DLN1 (0x3 << 8) /* RW */
+
+/* MSDC_EMMC50_PAD_DS_CTL0 mask */
+#define MSDC_EMMC50_PAD_DS_CTL0_SR (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_R0 (0x1 << 1) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_R1 (0x1 << 2) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_PUPD (0x1 << 3) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_IES (0x1 << 4) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_SMT (0x1 << 5) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_RDSEL (0x3F << 6) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_TDSEL (0xF << 12) /* RW */
+#define MSDC_EMMC50_PAD_DS_CTL0_DRV (0x7 << 16) /* RW */
+
+
+/* EMMC50_PAD_DS_TUNE mask */
+#define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1) /* RW */
+#define MSDC_EMMC50_PAD_DS_TUNE_DLY1 (0x1F << 2) /* RW */
+#define MSDC_EMMC50_PAD_DS_TUNE_DLY2 (0x1F << 7) /* RW */
+#define MSDC_EMMC50_PAD_DS_TUNE_DLY3 (0x1F << 12) /* RW */
+
+/* EMMC50_PAD_CMD_TUNE mask */
+#define MSDC_EMMC50_PAD_CMD_TUNE_DLY3SEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_CMD_TUNE_RXDLY3 (0x1F << 1) /* RW */
+#define MSDC_EMMC50_PAD_CMD_TUNE_TXDLY (0x1F << 6) /* RW */
+
+/* EMMC50_PAD_DAT01_TUNE mask */
+#define MSDC_EMMC50_PAD_DAT0_RXDLY3SEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DAT0_RXDLY3 (0x1F << 1) /* RW */
+#define MSDC_EMMC50_PAD_DAT0_TXDLY (0x1F << 6) /* RW */
+#define MSDC_EMMC50_PAD_DAT1_RXDLY3SEL (0x1 << 16) /* RW */
+#define MSDC_EMMC50_PAD_DAT1_RXDLY3 (0x1F << 17) /* RW */
+#define MSDC_EMMC50_PAD_DAT1_TXDLY (0x1F << 22) /* RW */
+
+/* EMMC50_PAD_DAT23_TUNE mask */
+#define MSDC_EMMC50_PAD_DAT2_RXDLY3SEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DAT2_RXDLY3 (0x1F << 1) /* RW */
+#define MSDC_EMMC50_PAD_DAT2_TXDLY (0x1F << 6) /* RW */
+#define MSDC_EMMC50_PAD_DAT3_RXDLY3SEL (0x1 << 16) /* RW */
+#define MSDC_EMMC50_PAD_DAT3_RXDLY3 (0x1F << 17) /* RW */
+#define MSDC_EMMC50_PAD_DAT3_TXDLY (0x1F << 22) /* RW */
+
+/* EMMC50_PAD_DAT45_TUNE mask */
+#define MSDC_EMMC50_PAD_DAT4_RXDLY3SEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DAT4_RXDLY3 (0x1F << 1) /* RW */
+#define MSDC_EMMC50_PAD_DAT4_TXDLY (0x1F << 6) /* RW */
+#define MSDC_EMMC50_PAD_DAT5_RXDLY3SEL (0x1 << 16) /* RW */
+#define MSDC_EMMC50_PAD_DAT5_RXDLY3 (0x1F << 17) /* RW */
+#define MSDC_EMMC50_PAD_DAT5_TXDLY (0x1F << 22) /* RW */
+
+/* EMMC50_PAD_DAT67_TUNE mask */
+#define MSDC_EMMC50_PAD_DAT6_RXDLY3SEL (0x1 << 0) /* RW */
+#define MSDC_EMMC50_PAD_DAT6_RXDLY3 (0x1F << 1) /* RW */
+#define MSDC_EMMC50_PAD_DAT6_TXDLY (0x1F << 6) /* RW */
+#define MSDC_EMMC50_PAD_DAT7_RXDLY3SEL (0x1 << 16) /* RW */
+#define MSDC_EMMC50_PAD_DAT7_RXDLY3 (0x1F << 17) /* RW */
+#define MSDC_EMMC50_PAD_DAT7_TXDLY (0x1F << 22) /* RW */
+
+/* EMMC51_CFG0 mask */
+#define MSDC_EMMC51_CFG_CMDQEN (0x1 << 0)
+#define MSDC_EMMC51_CFG_NUM (0x3F << 1)
+#define MSDC_EMMC51_CFG_RSPTYPE (0x7 << 7)
+#define MSDC_EMMC51_CFG_DTYPE (0x3 << 10)
+#define MSDC_EMMC51_CFG_RDATCNT (0x3FF << 12)
+#define MSDC_EMMC51_CFG_WDATCNT (0x3FF << 22)
+
+/* EMMC50_CFG0 mask */
+#define MSDC_EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)
+#define MSDC_EMMC50_CFG_CRC_STS_CNT (0x3 << 1)
+#define MSDC_EMMC50_CFG_CRC_STS_EDGE (0x1 << 3)
+#define MSDC_EMMC50_CFG_CRC_STS_SEL (0x1 << 4)
+#define MSDC_EMMC50_CFG_END_BIT_CHK_CNT (0xf << 5)
+#define MSDC_EMMC50_CFG_CMD_RESP_SEL (0x1 << 9)
+#define MSDC_EMMC50_CFG_CMD_EDGE_SEL (0x1 << 10)
+#define MSDC_EMMC50_CFG_ENDBIT_CNT (0x3FF << 11)
+#define MSDC_EMMC50_CFG_READ_DAT_CNT (0x7 << 21)
+#define MSDC_EMMC50_CFG_EMMC50_MON_SEL (0x1 << 24)
+#define MSDC_EMMC50_CFG_TXSKEW_SEL (0x1 << 29)
+
+/* EMMC50_CFG1 mask */
+#define MSDC_EMMC50_CFG1_CKSWITCH_CNT (0x7 << 8)
+#define MSDC_EMMC50_CFG1_RDDAT_STOP (0x1 << 11)
+#define MSDC_EMMC50_CFG1_WAITCLK_CNT (0xF << 12)
+#define MSDC_EMMC50_CFG1_DBG_SEL (0xFF << 16)
+#define MSDC_EMMC50_CFG1_PSHCNT (0x7 << 24)
+#define MSDC_EMMC50_CFG1_PSHPSSEL (0x1 << 27)
+#define MSDC_EMMC50_CFG1_DSCFG (0x1 << 28)
+#define MSDC_EMMC50_CFG1_SPARE1 (0x7UL << 29)
+
+/* EMMC50_CFG2_mask */
+/*#define MSDC_EMMC50_CFG2_AXI_GPD_UP (0x1 << 0)*/
+#define MSDC_EMMC50_CFG2_AXI_IOMMU_WR_EMI (0x1 << 1)
+#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_WR_EMI (0x1 << 2)
+#define MSDC_EMMC50_CFG2_AXI_IOMMU_RD_EMI (0x1 << 7)
+#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_RD_EMI (0x1 << 8)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_128B (0x1 << 13)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_256B (0x1 << 14)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_512B (0x1 << 15)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_1K (0x1 << 16)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_2K (0x1 << 17)
+#define MSDC_EMMC50_CFG2_AXI_BOUND_4K (0x1 << 18)
+#define MSDC_EMMC50_CFG2_AXI_RD_OUTS_NUM (0x1F << 19)
+#define MSDC_EMMC50_CFG2_AXI_SET_LEN (0xf << 24)
+#define MSDC_EMMC50_CFG2_AXI_RESP_ERR_TYPE (0x3 << 28)
+#define MSDC_EMMC50_CFG2_AXI_BUSY (0x1 << 30)
+
+/* EMMC50_CFG3_mask */
+#define MSDC_EMMC50_CFG3_OUTS_WR (0x1F << 0)
+#define MSDC_EMMC50_CFG3_ULTRA_SET_WR (0x3F << 5)
+#define MSDC_EMMC50_CFG3_PREULTRA_SET_WR (0x3F << 11)
+#define MSDC_EMMC50_CFG3_ULTRA_SET_RD (0x3F << 17)
+#define MSDC_EMMC50_CFG3_PREULTRA_SET_RD (0x3F << 23)
+
+/* EMMC50_CFG4_mask */
+#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_WR (0xFF << 0)
+#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_RD (0xFF << 8)
+#define MSDC_EMMC50_CFG4_ULTRA_EN (0x3 << 16)
+#define MSDC_EMMC50_CFG4_AXI_WRAP_DBG_SEL (0x1F << 18)
+
+/* SDC_FIFO_CFG mask */
+#define SDC_FIFO_CFG_EMMC50_BLOCK_LENGTH (0x1FF << 0)
+#define SDC_FIFO_CFG_WR_PTR_MARGIN (0xFF << 16)
+#define SDC_FIFO_CFG_WR_VALID_SEL (0x1 << 24)
+#define SDC_FIFO_CFG_RD_VALID_SEL (0x1 << 25)
+#define SDC_FIFO_CFG_WR_VALID (0x1 << 26)
+#define SDC_FIFO_CFG_RD_VALID (0x1 << 27)
+
+/* SDIO_TUNE_WIND mask*/
+#define MSDC_SDIO_TUNE_WIND (0x1F << 0)
+
+/* MSDC_AES_SEL mask*/
+#define MSDC_AES_SEL_SEL (0x3F << 0)
+#define MSDC_AES_SEL_EN (0xF << 8)
+
+/* MTKCQ_CFG0 mask*/
+#define MTKCQ_CFG0_ACMD13_BLK_CNT (0xFFFF << 0)
+
+/* MTKCQ_CFG1 mask*/
+#define MTKCQ_CFG1_ACMD13_IDLE_TIME (0xFFFF << 0)
+
+/* MTKCQ_CFG2 mask*/
+#define MTKCQ_CFG2_CQ_EN (0x1 << 0)
+#define MTKCQ_CFG2_CQ_BUSY (0x1 << 1)
+#define MTKCQ_CFG2_CMD13_FLAG (0x1 << 4)
+
+/* MTKCQ_ERR_ST mask*/
+#define MTKCQ_ERR_ST_CMD44_RESP_CRCERR (0x1 << 0) /* RO */
+#define MTKCQ_ERR_ST_CMD44_RESP_TO (0x1 << 1) /* RO */
+#define MTKCQ_ERR_ST_CMD45_RESP_CRCERR (0x1 << 4) /* RO */
+#define MTKCQ_ERR_ST_CMD45_RESP_TO (0x1 << 5) /* RO */
+#define MTKCQ_ERR_ST_CMD13_RESP_CRCERR (0x1 << 8) /* RO */
+#define MTKCQ_ERR_ST_CMD13_RESP_TO (0x1 << 9) /* RO */
+#define MTKCQ_ERR_ST_OTHER_CMD_RESP_CRCERR (0x1 << 12) /* RO */
+#define MTKCQ_ERR_ST_OTHER_CMD_RESP_TO (0x1 << 13) /* RO */
+#define MTKCQ_ERR_ST_RESP_ERR_ST (0x1 << 16) /* RO */
+#define MTKCQ_ERR_ST_CQ_R1_RESP_ERR (0x1 << 17) /* RO */
+
+/* MTKCQ_CMD45_READY mask*/
+#define MTKCQ_CMD45_READY_ST (0xFFFFFFFF << 0) /* RW */
+
+/* MTKCQ_TASK_READY_ST mask*/
+#define MTKCQ_TASK_READY_ST_MA (0xFFFFFFFF << 0) /* RO */
+
+/* MTKCQ_TASK_DONE_ST mask*/
+#define MTKCQ_TASK_DONE_ST_CMD13_UPDATE_ST (0x1 << 0) /* RO */
+#define MTKCQ_TASK_DONE_ST_CMD45_DONE_ST (0x1 << 1) /* RO */
+#define MTKCQ_TASK_DONE_ST_OTHER_CMD_DONE_ST (0x1 << 2) /* RO */
+#define MTKCQ_TASK_DONE_ST_CMD_DONE_ST (0x1 << 3) /* RO */
+#define MTKCQ_TASK_DONE_ST_CMD13_DONE_ST (0x1 << 4) /* RO */
+#define MTKCQ_TASK_DONE_ST_CQ_SWCMD_MISS (0x1 << 5) /* RO */
+#define MTKCQ_TASK_DONE_ST_CMD45_DONE_ST_MASK (0x1 << 6) /* RW */
+
+/* MTKCQ_ERR_ST_CLR mask*/
+#define MTKCQ_ERR_ST_CLR_CMD44_RESP_CRCERR_CLR (0x1 << 0) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CMD44_RESP_TO_CLR (0x1 << 1) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CMD45_RESP_CRCERR_CLR (0x1 << 4) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CMD45_RESP_TO_CLR (0x1 << 5) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CMD13_RESP_CRCERR_CLR (0x1 << 8) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CMD13_RESP_TO_CLR (0x1 << 9) /* W1 */
+#define MTKCQ_ERR_ST_CLR_OTHER_CMD_RESP_CRCERR_CLR (0x1 << 12) /* W1 */
+#define MTKCQ_ERR_ST_CLR_CQ_R1_RESP_ERR_CLR (0x1 << 17) /* W1 */
+
+/* MTKCQ_CMD_DONE_CLR mask*/
+#define MTKCQ_CMD_DONE_CLR_CMD13_UPDATE_ST_CLR (0x1 << 0) /* W1 */
+#define MTKCQ_CMD_DONE_CLR_CMD45_DONE_ST_CLR (0x1 << 1) /* W1 */
+#define MTKCQ_CMD_DONE_CLR_OTHER_CMD_DONE_ST_CLR (0x1 << 2) /* W1 */
+#define MTKCQ_CMD_DONE_CLR_CMD13_DONE_ST_CLR (0x1 << 4) /* W1 */
+
+/* MTKCQ_SW_CTL_CQ mask*/
+#define MTKCQ_SW_CTL_CQ_SW_RESTART_CQ (0x1 << 0) /* RW */
+#define MTKCQ_SW_CTL_CQ_GO_IDLE (0x1 << 4) /* RW */
+#define MTKCQ_SW_CTL_CQ_GO_ACTIVE (0x1 << 5) /* A0 */
+
+/* MTKCQ_CMD44_RESP mask*/
+#define MTKCQ_CMD44_RESP_MASK (0xFFFFFFFF << 0) /* RO */
+
+/* MTKCQ_CMD45_RESP mask*/
+#define MTKCQ_CMD45_RESP_MASK (0xFFFFFFFF << 0) /* RO */
+
+/* MTKCQ_CMD13_RCA mask*/
+#define MTKCQ_CMD13_RCA_MASK (0xFFFF << 0) /* RW */
+
+/* EMMC51_CQCB_CFG3 mask*/
+#define EMMC51_CQCB_CFG3_MSDC_CQCB_CLR (0x1 << 0) /* A0 */
+#define EMMC51_CQCB_CFG3_CQCB_FIFO_FULL (0x1 << 4) /* RU */
+
+/* EMMC51_CQCB_CMD44 mask*/
+#define EMMC51_CQCB_CMD44_MASK (0xFFFFFFFF << 0) /* RW */
+
+/* EMMC51_CQCB_CMD45 mask*/
+#define EMMC51_CQCB_CMD45_MASK (0xFFFFFFFF << 0) /* RW */
+
+/* EMMC51_CQCB_TIDMAP mask*/
+#define EMMC51_CQCB_TIDMAP_TASKIDMAP (0xFFFFFFFF << 0) /* RW */
+
+/* EMMC51_CQCB_TIDMAPCLR mask*/
+#define EMMC51_CQCB_TIDMAPCLR_MASK (0xFFFFFFFF << 0) /* WO */
+
+/* EMMC51_CQCB_CURCMD mask*/
+#define EMMC51_CQCB_CURCMD_ID (0x3F << 0) /* RW */
+
+#if defined(FEATURE_MULTI_HOST)
+#include "msdc_reg_mh.h"
+#endif
+
+/*
+ *MSDC TOP REG
+ */
+#define REG_OP(x) ((volatile uint32_t *)((uintptr_t)host->base_top + OFFSET_##x))
+
+/* TOP REGISTER */
+#define OFFSET_EMMC_TOP_CONTROL (0x00)
+#define OFFSET_EMMC_TOP_CMD (0x04)
+#define OFFSET_TOP_EMMC50_PAD_CTL0 (0x08)
+#define OFFSET_TOP_EMMC50_PAD_DS_TUNE (0x0c)
+#define OFFSET_TOP_EMMC50_PAD_DAT0_TUNE (0x10)
+#define OFFSET_TOP_EMMC50_PAD_DAT1_TUNE (0x14)
+#define OFFSET_TOP_EMMC50_PAD_DAT2_TUNE (0x18)
+#define OFFSET_TOP_EMMC50_PAD_DAT3_TUNE (0x1c)
+#define OFFSET_TOP_EMMC50_PAD_DAT4_TUNE (0x20)
+#define OFFSET_TOP_EMMC50_PAD_DAT5_TUNE (0x24)
+#define OFFSET_TOP_EMMC50_PAD_DAT6_TUNE (0x28)
+#define OFFSET_TOP_EMMC50_PAD_DAT7_TUNE (0x2c)
+
+#define EMMC_TOP_CONTROL REG_OP(EMMC_TOP_CONTROL)
+#define EMMC_TOP_CMD REG_OP(EMMC_TOP_CMD)
+#define TOP_EMMC50_PAD_CTL0 REG_OP(TOP_EMMC50_PAD_CTL0)
+#define TOP_EMMC50_PAD_DS_TUNE REG_OP(TOP_EMMC50_PAD_DS_TUNE)
+#define TOP_EMMC50_PAD_DAT0_TUNE REG_OP(TOP_EMMC50_PAD_DAT0_TUNE)
+#define TOP_EMMC50_PAD_DAT1_TUNE REG_OP(TOP_EMMC50_PAD_DAT1_TUNE)
+#define TOP_EMMC50_PAD_DAT2_TUNE REG_OP(TOP_EMMC50_PAD_DAT2_TUNE)
+#define TOP_EMMC50_PAD_DAT3_TUNE REG_OP(TOP_EMMC50_PAD_DAT3_TUNE)
+#define TOP_EMMC50_PAD_DAT4_TUNE REG_OP(TOP_EMMC50_PAD_DAT4_TUNE)
+#define TOP_EMMC50_PAD_DAT5_TUNE REG_OP(TOP_EMMC50_PAD_DAT5_TUNE)
+#define TOP_EMMC50_PAD_DAT6_TUNE REG_OP(TOP_EMMC50_PAD_DAT6_TUNE)
+#define TOP_EMMC50_PAD_DAT7_TUNE REG_OP(TOP_EMMC50_PAD_DAT7_TUNE)
+
+
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
+#define DELAY_EN (0x1 << 1) /* RW */
+#define PAD_DAT_RD_RXDLY2 (0x1F << 2) /* RW */
+#define PAD_DAT_RD_RXDLY (0x1F << 7) /* RW */
+#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
+#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
+#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
+#define SDC_RX_ENH_EN (0x1 << 15) /* TW */
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1F << 0) /* RW */
+#define PAD_CMD_RXDLY (0x1F << 5) /* RW */
+#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
+#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
+#define PAD_CMD_TX_DLY (0x1F << 12) /* RW */
+
+/* TOP_EMMC50_PAD_CTL0 mask */
+#define HL_SEL (0x1 << 0) /* RW */
+#define DCC_SEL (0x1 << 1) /* RW */
+#define DLN1 (0x3 << 2) /* RW */
+#define DLN0 (0x3 << 4) /* RW */
+#define DLP1 (0x3 << 6) /* RW */
+#define DLP0 (0x3 << 8) /* RW */
+#define PAD_CLK_TXDLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DS_TUNE mask */
+#define PAD_DS_DLY3 (0x1F << 0) /* RW */
+#define PAD_DS_DLY2 (0x1F << 5) /* RW */
+#define PAD_DS_DLY1 (0x1F << 10) /* RW */
+#define PAD_DS_DLY2_SEL (0x1 << 15) /* RW */
+#define PAD_DS_DLY_SEL (0x1 << 16) /* RW */
+
+/* TOP_EMMC50_PAD_DAT0_TUNE mask */
+#define DAT0_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT0_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT0_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT1_TUNE mask */
+#define DAT1_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT1_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT1_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT2_TUNE mask */
+#define DAT2_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT2_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT2_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT3_TUNE mask */
+#define DAT3_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT3_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT3_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT4_TUNE mask */
+#define DAT4_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT4_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT4_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT5_TUNE mask */
+#define DAT5_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT5_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT5_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT6_TUNE mask */
+#define DAT6_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT6_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT6_TX_DLY (0x1F << 10) /* RW */
+
+/* TOP_EMMC50_PAD_DAT7_TUNE mask */
+#define DAT7_RD_DLY2 (0x1F << 0) /* RW */
+#define DAT7_RD_DLY1 (0x1F << 5) /* RW */
+#define PAD_DAT7_TX_DLY (0x1F << 10) /* RW */
+
+/*******************************************************************************
+ * Power Definition
+ ******************************************************************************/
+#define MSDC_PB0_DEFAULT 0x403C0006
+#define MSDC_PB1_DEFAULT 0xFFE20349
+#define MSDC_PB2_DEFAULT 0x14801803
+
+#define CMD_RSP_TA_CNTR_DEFAULT 0
+#define WRDAT_CRCS_TA_CNTR_DEFAULT 0
+#define BUSY_MA_DEFAULT 1
+
+#define CRCSTSENSEL_HS400_DEFAULT 3
+#define RESPSTENSEL_HS400_DEFAULT 3
+#define CRCSTSENSEL_HS_DEFAULT 1
+#define RESPSTENSEL_HS_DEFAULT 1
+#define CRCSTSENSEL_FPGA_DEFAULT 0
+
+#if 1
+/* Chaotian Add GPIO top layer */
+#define MSDC_DRVN_GEAR0 0
+#define MSDC_DRVN_GEAR1 1
+#define MSDC_DRVN_GEAR2 2
+#define MSDC_DRVN_GEAR3 3
+#define MSDC_DRVN_GEAR4 4
+#define MSDC_DRVN_GEAR5 5
+#define MSDC_DRVN_GEAR6 6
+#define MSDC_DRVN_GEAR7 7
+#define MSDC_DRVN_DONT_CARE MSDC_DRVN_GEAR0
+
+/*--------------------------------------------------------------------------*/
+/* MSDC GPIO Related Register */
+/*--------------------------------------------------------------------------*/
+/* for MT2731 */
+#define MSDC0_GPIO_MODE16 (GPIO_BASE + 0x400)
+#define MSDC0_GPIO_MODE17 (GPIO_BASE + 0x410)
+#define MSDC0_GPIO_MODE18 (GPIO_BASE + 0x420)
+#define MSDC0_DRV_CFG0 (IO_CFG_TR_BASE + 0x00)
+#define MSDC0_DRV_CFG1 (IO_CFG_TR_BASE + 0x10)
+#define MSDC0_GPIO_IES_ADDR (IO_CFG_TR_BASE + 0x20)
+#define MSDC0_GPIO_PUPD0_ADDR (IO_CFG_TR_BASE + 0x30)
+#define MSDC0_GPIO_R0_ADDR (IO_CFG_TR_BASE + 0x40)
+#define MSDC0_GPIO_R1_ADDR (IO_CFG_TR_BASE + 0x50)
+#define MSDC0_GPIO_RDSEL0_ADDR (IO_CFG_TR_BASE + 0x60)
+#define MSDC0_GPIO_RDSEL1_ADDR (IO_CFG_TR_BASE + 0x70)
+#define MSDC0_GPIO_SMT_ADDR (IO_CFG_TR_BASE + 0x80)
+#define MSDC0_GPIO_TDSEL0_ADDR (IO_CFG_TR_BASE + 0x90)
+#define MSDC0_GPIO_TDSEL1_ADDR (IO_CFG_TR_BASE + 0xa0)
+
+/* MSDC0 IES mask */
+#define MSDC0_IES_RSTB_MASK (0x1 << 11)
+#define MSDC0_IES_DSL_MASK (0x1 << 10)
+#define MSDC0_IES_DAT_MASK (0xFF << 2)
+#define MSDC0_IES_CMD_MASK (0x1 << 1)
+#define MSDC0_IES_CLK_MASK (0x1 << 0)
+#define MSDC0_IES_ALL_MASK (0xFFF << 0)
+/* MSDC0 SMT mask */
+#define MSDC0_SMT_RSTB_MASK (0x1 << 11)
+#define MSDC0_SMT_DSL_MASK (0x1 << 10)
+#define MSDC0_SMT_DAT_MASK (0xFF << 2)
+#define MSDC0_SMT_CMD_MASK (0x1 << 1)
+#define MSDC0_SMT_CLK_MASK (0x1 << 0)
+#define MSDC0_SMT_ALL_MASK (0xFFF << 0)
+/* MSDC0 TDSEL0 mask */
+#define MSDC0_TDSEL0_DAT_MASK (0xFFFFFF << 8)
+#define MSDC0_TDSEL0_CMD_MASK (0xF << 4)
+#define MSDC0_TDSEL0_CLK_MASK (0xF << 0)
+#define MSDC0_TDSEL0_ALL_MASK (0xFFFFFFFF << 0)
+/* MSDC0 TDSEL1 mask */
+#define MSDC0_TDSEL1_RSTB_MASK (0xF << 4)
+#define MSDC0_TDSEL1_DSL_MASK (0xF << 0)
+#define MSDC0_TDSEL1_ALL_MASK (0xFF << 0)
+/* MSDC0 RDSEL0 mask */
+#define MSDC0_RDSEL0_DAT5_MASK (0x3F << 24)
+#define MSDC0_RDSEL0_DAT4_MASK (0x3F << 18)
+#define MSDC0_RDSEL0_DAT0_MASK (0x3F << 12)
+#define MSDC0_RDSEL0_CMD_MASK (0x3F << 6)
+#define MSDC0_RDSEL0_CLK_MASK (0x3F << 0)
+#define MSDC0_RDSEL0_ALL_MASK (0x3FFFFFFF << 0)
+/* MSDC0 RDSEL1 mask */
+#define MSDC0_RDSEL1_RSTB_MASK (0x3F << 24)
+#define MSDC0_RDSEL1_DSL_MASK (0x3F << 18)
+#define MSDC0_RDSEL1_DAT123_MASK (0x3F << 12)
+#define MSDC0_RDSEL1_DAT7_MASK (0x3F << 6)
+#define MSDC0_RDSEL1_DAT6_MASK (0x3F << 0)
+#define MSDC0_RDSEL1_ALL_MASK (0x3FFFFFFF << 0)
+
+/* MSDC0 DRV0 mask */
+#define MSDC0_DRV_CLK_MASK (0x7 << 0)
+#define MSDC0_DRV_CMD_MASK (0x7 << 3)
+#define MSDC0_DRV_DAT0_MASK (0x7 << 6)
+#define MSDC0_DRV_DAT1_MASK (0x7 << 9)
+#define MSDC0_DRV_DAT2_MASK (0x7 << 12)
+#define MSDC0_DRV_DAT3_MASK (0x7 << 15)
+#define MSDC0_DRV_DAT4_MASK (0x7 << 18)
+#define MSDC0_DRV_DAT5_MASK (0x7 << 21)
+#define MSDC0_DRV_DAT6_MASK (0x7 << 24)
+#define MSDC0_DRV_DAT7_MASK (0x7 << 27)
+#define MSDC0_DRV_DS_MASK (0x7 << 0)
+#define MSDC0_DRV_RST_MASK (0x7 << 3)
+/* MSDC0 PUPD mask*/
+#define MSDC0_PUPD_RSTB_MASK (0x1 << 11)
+#define MSDC0_PUPD_DSL_MASK (0x1 << 10)
+#define MSDC0_PUPD_DAT7_MASK (0x1 << 9)
+#define MSDC0_PUPD_DAT6_MASK (0x1 << 8)
+#define MSDC0_PUPD_DAT5_MASK (0x1 << 7)
+#define MSDC0_PUPD_DAT4_MASK (0x1 << 6)
+#define MSDC0_PUPD_DAT3_MASK (0x1 << 5)
+#define MSDC0_PUPD_DAT2_MASK (0x1 << 4)
+#define MSDC0_PUPD_DAT1_MASK (0x1 << 3)
+#define MSDC0_PUPD_DAT0_MASK (0x1 << 2)
+#define MSDC0_PUPD_CMD_MASK (0x1 << 1)
+#define MSDC0_PUPD_CLK_MASK (0x1 << 0)
+#define MSDC0_PUPD_DAT_MASK (0xFF << 2)
+#define MSDC0_PUPD_ALL_MASK (0x7FF << 0)
+/* MSDC0 R0 mask*/
+#define MSDC0_R0_RSTB_MASK (0x1 << 11)
+#define MSDC0_R0_DSL_MASK (0x1 << 10)
+#define MSDC0_R0_DAT7_MASK (0x1 << 9)
+#define MSDC0_R0_DAT6_MASK (0x1 << 8)
+#define MSDC0_R0_DAT5_MASK (0x1 << 7)
+#define MSDC0_R0_DAT4_MASK (0x1 << 6)
+#define MSDC0_R0_DAT3_MASK (0x1 << 5)
+#define MSDC0_R0_DAT2_MASK (0x1 << 4)
+#define MSDC0_R0_DAT1_MASK (0x1 << 3)
+#define MSDC0_R0_DAT0_MASK (0x1 << 2)
+#define MSDC0_R0_CMD_MASK (0x1 << 1)
+#define MSDC0_R0_CLK_MASK (0x1 << 0)
+#define MSDC0_R0_DAT_MASK (0xFF << 2)
+#define MSDC0_R0_ALL_MASK (0x7FF << 0)
+/* MSDC0 R1 mask*/
+#define MSDC0_R1_RSTB_MASK (0x1 << 11)
+#define MSDC0_R1_DSL_MASK (0x1 << 10)
+#define MSDC0_R1_DAT7_MASK (0x1 << 9)
+#define MSDC0_R1_DAT6_MASK (0x1 << 8)
+#define MSDC0_R1_DAT5_MASK (0x1 << 7)
+#define MSDC0_R1_DAT4_MASK (0x1 << 6)
+#define MSDC0_R1_DAT3_MASK (0x1 << 5)
+#define MSDC0_R1_DAT2_MASK (0x1 << 4)
+#define MSDC0_R1_DAT1_MASK (0x1 << 3)
+#define MSDC0_R1_DAT0_MASK (0x1 << 2)
+#define MSDC0_R1_CMD_MASK (0x1 << 1)
+#define MSDC0_R1_CLK_MASK (0x1 << 0)
+#define MSDC0_R1_DAT_MASK (0xFF << 2)
+#define MSDC0_R1_ALL_MASK (0x7FF << 0)
+
+
+#endif
+
+typedef enum __MSDC_PIN_STATE {
+ MSDC_HIGHZ = 0,
+ MSDC_10KOHM,
+ MSDC_50KOHM,
+ MSDC_8KOHM,
+ MSDC_PST_MAX
+} MSDC_PIN_STATE;
+
+
+/* each PLL have different gears for select
+ * software can used mux interface from clock management module to select */
+enum {
+ MSDC50_CLKSRC4HCLK_26MHZ = 0,
+ MSDC50_CLKSRC4HCLK_273MHZ,
+ MSDC50_CLKSRC4HCLK_156MHZ,
+ MSDC50_CLKSRC4HCLK_182MHZ,
+ MSDC_DONOTCARE_HCLK,
+ MSDC50_CLKSRC4HCLK_MAX
+};
+
+enum {
+ MSDC50_CLKSRC_26MHZ = 0,
+ MSDC50_CLKSRC_400MHZ, /* MSDCPLL_CK */
+ MSDC50_CLKSRC_182MHZ, /*MSDCPLL_D2 */
+ MSDC50_CLKSRC_78MHZ,
+ MSDC50_CLKSRC_312MHZ,
+ MSDC50_CLKSRC_273MHZ, /*MSDCPLL_D4 */
+ MSDC50_CLKSRC_249MHZ,
+ MSDC50_CLKSRC_156MHZ,
+ MSDC50_CLKSRC_MAX
+};
+
+/* MSDC0/1/2
+ PLL MUX SEL List */
+enum {
+ MSDC30_CLKSRC_26MHZ = 0,
+ MSDC30_CLKSRC_200MHZ,
+ MSDC30_CLKSRC_182MHZ,
+ MSDC30_CLKSRC_91MHZ,
+ MSDC30_CLKSRC_156MHZ,
+ MSDC30_CLKSRC_104MHZ,
+ MSDC30_CLKSRC_MAX
+};
+
+#define MSDC50_CLKSRC_DEFAULT MSDC50_CLKSRC_400MHZ
+#define MSDC30_CLKSRC_DEFAULT MSDC30_CLKSRC_200MHZ
+
+typedef enum MT65XX_POWER_VOL_TAG {
+ VOL_DEFAULT,
+ VOL_0900 = 900,
+ VOL_1000 = 1000,
+ VOL_1100 = 1100,
+ VOL_1200 = 1200,
+ VOL_1300 = 1300,
+ VOL_1350 = 1350,
+ VOL_1500 = 1500,
+ VOL_1800 = 1800,
+ VOL_2000 = 2000,
+ VOL_2100 = 2100,
+ VOL_2500 = 2500,
+ VOL_2800 = 2800,
+ VOL_3000 = 3000,
+ VOL_3300 = 3300,
+ VOL_3400 = 3400,
+ VOL_3500 = 3500,
+ VOL_3600 = 3600
+} MT65XX_POWER_VOLTAGE;
+
+/*--------------------------------------------------------------------------*/
+/* Descriptor Structure */
+/*--------------------------------------------------------------------------*/
+#define DMA_FLAG_NONE (0x00000000)
+#define DMA_FLAG_EN_CHKSUM (0x00000001)
+#define DMA_FLAG_PAD_BLOCK (0x00000002)
+#define DMA_FLAG_PAD_DWORD (0x00000004)
+
+#define MSDC_WRITE32(addr, data) writel(data, addr)
+#define MSDC_READ32(addr) readl(addr)
+#define MSDC_WRITE8(addr, data) writeb(data, addr)
+#define MSDC_READ8(addr) readb(addr)
+
+#define MSDC_SET_BIT32(addr,mask) \
+ do { \
+ unsigned int tv = MSDC_READ32(addr); \
+ tv |=((u32)(mask)); \
+ MSDC_WRITE32(addr,tv); \
+ } while (0)
+#define MSDC_CLR_BIT32(addr,mask) \
+ do { \
+ unsigned int tv = MSDC_READ32(addr); \
+ tv &= ~((u32)(mask)); \
+ MSDC_WRITE32(addr,tv); \
+ } while (0)
+
+#define MSDC_SET_FIELD(reg,field,val) \
+ do { \
+ u32 tv = MSDC_READ32(reg); \
+ tv &= ~((u32)(field)); \
+ tv |= ((val) << (__builtin_ffs((u32)(field)) - 1)); \
+ MSDC_WRITE32(reg, tv); \
+ } while (0)
+
+#define MSDC_GET_FIELD(reg,field,val) \
+ do { \
+ u32 tv = MSDC_READ32(reg); \
+ val = ((tv & (field)) >> (__builtin_ffs((u32)(field)) - 1)); \
+ } while (0)
+
+#define MSDC_RETRY(expr,retry,cnt) \
+ do { \
+ uint32_t t = cnt; \
+ uint32_t r = retry; \
+ uint32_t c = cnt; \
+ while (r) { \
+ if (!(expr)) break; \
+ if (c-- == 0) { \
+ r--; spin(200); c = t; \
+ } \
+ } \
+ if (r == 0) \
+ dprintf(CRITICAL, "%s->%d: retry %d times failed!\n", __func__, \
+ __LINE__, retry); \
+ } while (0)
+
+#define MSDC_RESET() \
+ do { \
+ MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_RST); \
+ MSDC_RETRY(MSDC_READ32(MSDC_CFG) & MSDC_CFG_RST, 5, 1000); \
+ } while (0)
+
+#define MSDC_CLR_INT() \
+ do { \
+ volatile uint32_t val = MSDC_READ32(MSDC_INT); \
+ MSDC_WRITE32(MSDC_INT, val); \
+ } while (0)
+
+#define MSDC_CLR_FIFO() \
+ do { \
+ MSDC_SET_BIT32(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
+ MSDC_RETRY(MSDC_READ32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, 5, 1000); \
+ } while (0)
+
+#define MSDC_FIFO_WRITE32(val) MSDC_WRITE32(MSDC_TXDATA, val)
+#define MSDC_FIFO_READ32() MSDC_READ32(MSDC_RXDATA)
+#define MSDC_FIFO_WRITE8(val) MSDC_WRITE8(MSDC_TXDATA, val)
+#define MSDC_FIFO_READ8() MSDC_READ8(MSDC_RXDATA)
+
+#define MSDC_TXFIFOCNT() \
+ ((MSDC_READ32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
+#define MSDC_RXFIFOCNT() \
+ ((MSDC_READ32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
+
+#define SDC_IS_BUSY() (MSDC_READ32(SDC_STS) & SDC_STS_SDCBUSY)
+#define SDC_IS_CMD_BUSY() (MSDC_READ32(SDC_STS) & SDC_STS_CMDBUSY)
+
+#define SDC_SEND_CMD(cmd,arg) \
+ do { \
+ MSDC_WRITE32(SDC_ARG, (arg)); \
+ MSDC_WRITE32(SDC_CMD, (cmd)); \
+ } while (0)
+
+#define MSDC_DMA_ON MSDC_CLR_BIT32(MSDC_CFG, MSDC_CFG_PIO);
+#define MSDC_DMA_OFF MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_PIO);
+
+#define MSDC_RELIABLE_WRITE (0x1 << 0)
+#define MSDC_PACKED (0x1 << 1)
+#define MSDC_TAG_REQUEST (0x1 << 2)
+#define MSDC_CONTEXT_ID (0x1 << 3)
+#define MSDC_FORCED_PROG (0x1 << 4)
+
+#ifdef FPGA_PLATFORM
+#define msdc_dump_padctl_by_id(...)
+#define msdc_pin_set(...)
+#define msdc_set_smt(...)
+#define msdc_set_driving(...)
+#define msdc_set_pin_mode(...)
+#define msdc_set_rdsel_wrap(...)
+#define msdc_set_tdsel_wrap(...)
+#define msdc_gpio_and_pad_init(...)
+#endif
+
+int msdc_init(struct mmc_host *host);
+void msdc_config_bus(struct mmc_host *host, u32 width);
+int msdc_dma_transfer(struct mmc_host *host, struct mmc_data *data);
+int msdc_tune_bwrite(struct mmc_host *host, u32 dst, u8 *src, u32 nblks);
+int msdc_tune_bread(struct mmc_host *host, u8 *dst, u32 src, u32 nblks);
+void msdc_reset_tune_counter(struct mmc_host *host);
+int msdc_abort_handler(struct mmc_host *host, int abort_card);
+int msdc_tune_read(struct mmc_host *host);
+void msdc_config_clock(struct mmc_host *host, int state, u32 hz);
+int msdc_cmd(struct mmc_host *host, struct mmc_command *cmd);
+void msdc_set_timeout(struct mmc_host *host, u32 ns, u32 clks);
+void msdc_set_autocmd(struct mmc_host *host, int cmd);
+int msdc_get_autocmd(struct mmc_host *host);
diff --git a/src/bsp/lk/platform/mt2731/include/platform/msdc_cfg.h b/src/bsp/lk/platform/mt2731/include/platform/msdc_cfg.h
new file mode 100644
index 0000000..436c456
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/msdc_cfg.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+/*--------------------------------------------------------------------------*/
+/* Common Definition */
+/*--------------------------------------------------------------------------*/
+#ifdef CFG_FPGA_PLATFORM
+#define FPGA_PLATFORM
+#endif
+
+/* HW deal with the 2K DMA boundary limitation, SW do nothing with it */
+/* Most of eMMC request in lk are sequential access, so it's no need to
+ * use descript DMA mode, I just remove relevant codes. JieWu@20160607 */
+#define MSDC_USE_DMA_MODE
+
+#define FEATURE_MMC_WR_TUNING
+#define FEATURE_MMC_RD_TUNING
+#define FEATURE_MMC_CM_TUNING
+//#define FEATURE_MMC_TUNING_EDGE_ONLY_WHEN_HIGH_SPEED
+
+/* Maybe we discard these macro definition */
+//#define MSDC_USE_PATCH_BIT2_TURNING_WITH_ASYNC
+
+/*--------------------------------------------------------------------------*/
+/* Debug Definition */
+/*--------------------------------------------------------------------------*/
+//#define KEEP_SLIENT_BUILD
+//#define ___MSDC_DEBUG___
+#define MSDC_TUNE_LOG (1)
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt2731.h b/src/bsp/lk/platform/mt2731/include/platform/mt2731.h
new file mode 100644
index 0000000..04c1940
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt2731.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+#include <compiler.h>
+#include <debug.h>
+
+/* RAM_CONSOLE should over SRAM */
+#define RAM_CONSOLE_SRAM_ADDR (0x0011D000)
+#define RAM_CONSOLE_SRAM_SIZE (0x800)
+
+/* SRAM used for store GCE instructions */
+#define GCE_INS_SRAM_SIZE (0x400)
+#define GCE_INS_SRAM_ADDR (RAM_CONSOLE_SRAM_ADDR - GCE_INS_SRAM_SIZE)
+
+#if LK_AS_BL33 == 0 /* LK as BL2 */
+/* program memory: L2C for BL2 */
+#define MEMORY_BASE_PHYS (0x200000)
+#define MEMORY_APERTURE_SIZE (0x40000UL)
+
+/* internal SRAM */
+#define SRAM_BASE_PHYS (0x100000)
+#define SRAM_BASE_SIZE (0x30000UL)
+
+#else /* LK as BL33 */
+
+/* program memory and memory before mempool */
+#define MEMORY_BASE_PHYS (0x40000000)
+#define MEMORY_APERTURE_SIZE (0xC300000UL)
+
+/* non-secure accessible internal SRAM region */
+#define SRAM_BASE_PHYS (0x118000)
+#define SRAM_BASE_SIZE (0x18000UL)
+#endif
+
+/* peripheral */
+#define PERIPHERAL_BASE_PHYS (0x10000000)
+#define PERIPHERAL_BASE_SIZE (0x10000000UL)
+
+/* gic+peripheral */
+#define GIC_PERIPHERAL_BASE_PHYS (0xC000000)
+#define GIC_PERIPHERAL_BASE_SIZE (0x10000000UL)
+
+#define MD1_BASE_PHYS (0x20000000)
+#define MD1_BASE_SIZE (0x2000000UL) /* 32 MB size*/
+
+/* dram */
+#define DRAM_BASE_PHY (0x40000000UL)
+
+#if WITH_KERNEL_VM
+
+#if ARCH_ARM64
+#define MEMORY_BASE_VIRT (KERNEL_ASPACE_BASE + MEMORY_BASE_PHYS)
+#define SRAM_BASE_VIRT (KERNEL_ASPACE_BASE + SRAM_BASE_PHYS)
+#define PERIPHERAL_BASE_VIRT (KERNEL_ASPACE_BASE + PERIPHERAL_BASE_PHYS)
+#define GIC_PERIPHERAL_BASE_VIRT (KERNEL_ASPACE_BASE + GIC_PERIPHERAL_BASE_PHYS)
+#define MD1_BASE_VIRT (KERNEL_ASPACE_BASE + MD1_BASE_PHYS)
+#define DRAM_BASE_VIRT (KERNEL_ASPACE_BASE + DRAM_BASE_PHY)
+#endif
+
+#if ARCH_ARM
+#define MEMORY_BASE_VIRT (MEMORY_BASE_PHYS)
+#define SRAM_BASE_VIRT (SRAM_BASE_PHYS)
+#define PERIPHERAL_BASE_VIRT (PERIPHERAL_BASE_PHYS)
+#define GIC_PERIPHERAL_BASE_VIRT (GIC_PERIPHERAL_BASE_PHYS)
+#define MD1_BASE_VIRT (MD1_BASE_PHYS)
+#define DRAM_BASE_VIRT (DRAM_BASE_PHY)
+#endif
+
+#else
+#define MEMORY_BASE_VIRT MEMORY_BASE_PHYS
+#define SRAM_BASE_VIRT SRAM_BASE_PHYS
+#define PERIPHERAL_BASE_VIRT PERIPHERAL_BASE_PHYS
+#define GIC_PERIPHERAL_BASE_VIRT GIC_PERIPHERAL_BASE_PHYS
+#define MD1_BASE_VIRT MD1_BASE_PHYS
+#define DRAM_BASE_VIRT DRAM_BASE_PHY
+#endif
+
+/* reserve 8KB sram for mrdump(last 8KB) */
+#define MRDUMP_CB_SIZE 0x2000
+#define MRDUMP_CB_ADDR (SRAM_BASE_PHYS + SRAM_BASE_SIZE - MRDUMP_CB_SIZE) //end -8K
+
+#define SRAM_ARENA_BASE SRAM_BASE_PHYS
+#define SRAM_ARENA_SIZE (SRAM_BASE_SIZE - MRDUMP_CB_SIZE)
+
+/* temp modify for 32 bit kernel */
+#define DRAM_ARENA_BASE (DRAM_BASE_PHY+0x2008000UL)
+#define DRAM_ARENA_SIZE SRAM_BASE_SIZE
+
+/* 64KB use for LK2.0 transfer bootargs to BL33 */
+#define DRAM_BOOTARG_OFFSET 0x2038000
+#define DRAM_BOOTARG_BASE (DRAM_BASE_PHY + DRAM_BOOTARG_OFFSET)
+#define DRAM_BOOTARG_SIZE 0x10000
+
+/* interrupts */
+#define ARM_GENERIC_TIMER_VIRTUAL_INT 27
+#define ARM_GENERIC_TIMER_PHYSICAL_INT 30
+
+#define MAX_INT 256
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_gpio.h b/src/bsp/lk/platform/mt2731/include/platform/mt_gpio.h
new file mode 100644
index 0000000..d94a442
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_gpio.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+/******************************************************************************
+* Enumeration for GPIO pin
+******************************************************************************/
+/* GPIO MODE CONTROL VALUE*/
+enum GPIO_MODE {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01 = 1,
+ GPIO_MODE_02 = 2,
+ GPIO_MODE_03 = 3,
+ GPIO_MODE_04 = 4,
+ GPIO_MODE_05 = 5,
+ GPIO_MODE_06 = 6,
+ GPIO_MODE_07 = 7,
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_01,
+};
+/* GPIO DIRECTION */
+enum GPIO_DIR {
+ GPIO_DIR_UNSUPPORTED = -1,
+ GPIO_DIR_IN = 0,
+ GPIO_DIR_OUT = 1,
+ GPIO_DIR_MAX,
+ GPIO_DIR_DEFAULT = GPIO_DIR_IN,
+};
+/* GPIO PULL ENABLE*/
+enum GPIO_PULL_EN {
+ GPIO_PULL_EN_UNSUPPORTED = -1,
+ GPIO_PULL_DISABLE = 0,
+ GPIO_PULL_ENABLE = 1,
+ GPIO_PULL_EN_MAX,
+ GPIO_PULL_EN_DEFAULT = GPIO_PULL_ENABLE,
+};
+/* GPIO IES ENABLE*/
+enum GPIO_IES_EN {
+ GPIO_IES_EN_UNSUPPORTED = -1,
+ GPIO_IES_DISABLE = 0,
+ GPIO_IES_ENABLE = 1,
+ GPIO_IES_EN_MAX,
+ GPIO_IES_EN_DEFAULT = GPIO_IES_ENABLE,
+};
+/* GPIO SMT ENABLE*/
+enum GPIO_SMT_EN {
+ GPIO_SMT_EN_UNSUPPORTED = -1,
+ GPIO_SMT_DISABLE = 0,
+ GPIO_SMT_ENABLE = 1,
+ GPIO_SMT_EN_MAX,
+ GPIO_SMT_EN_DEFAULT = GPIO_SMT_DISABLE,
+};
+/* GPIO SAFETY ENABLE*/
+enum GPIO_SAFETY_EN {
+ GPIO_SAFETY_EN_UNSUPPORTED = -1,
+ GPIO_SAFETY_DISABLE = 0,
+ GPIO_SAFETY_ENABLE = 1,
+ GPIO_SAFETY_EN_MAX,
+ GPIO_SAFETY_EN_DEFAULT = GPIO_SAFETY_DISABLE,
+};
+/* GPIO PULL-UP/PULL-DOWN*/
+enum GPIO_PULL {
+ GPIO_PULL_UNSUPPORTED = -1,
+ GPIO_PULL_DOWN = 0,
+ GPIO_PULL_UP = 1,
+ GPIO_PULL_MAX,
+ GPIO_PULL_DEFAULT = GPIO_PULL_DOWN
+};
+/* GPIO OUTPUT */
+enum GPIO_OUT {
+ GPIO_OUT_UNSUPPORTED = -1,
+ GPIO_OUT_ZERO = 0,
+ GPIO_OUT_ONE = 1,
+ GPIO_OUT_MAX,
+ GPIO_OUT_DEFAULT = GPIO_OUT_ZERO,
+ GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO,
+};
+
+typedef struct {
+ addr_t reg_addr;
+ u32 val;
+ u32 mask;
+} gpio_reg_init;
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+void mt_gpio_init(void);
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_gpt_v4.h b/src/bsp/lk/platform/mt2731/include/platform/mt_gpt_v4.h
new file mode 100644
index 0000000..c19ad05
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_gpt_v4.h
@@ -0,0 +1,90 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ */
+
+#ifndef __MT_GPT_H__
+#define __MT_GPT_H__
+#include <platform/mt_typedefs.h>
+#include <sys/types.h>
+
+#define GPT_IRQEN_REG ((volatile unsigned int*)(APXGPT_BASE))
+#define GPT_IRQSTA_REG ((volatile unsigned int*)(APXGPT_BASE+0x04))
+#define GPT_IRQACK_REG ((volatile unsigned int*)(APXGPT_BASE+0x08))
+
+#define GPT5_CON_REG ((volatile unsigned int*)(APXGPT_BASE+0x50))
+#define GPT5_CLK_REG ((volatile unsigned int*)(APXGPT_BASE+0x54))
+#define GPT5_COUNT_REG ((volatile unsigned int*)(APXGPT_BASE+0x58))
+#define GPT5_COMPARE_REG ((volatile unsigned int*)(APXGPT_BASE+0x5C))
+
+#define GPT_MODE4_ONE_SHOT (0x00 << 4)
+#define GPT_MODE4_REPEAT (0x01 << 4)
+#define GPT_MODE4_KEEP_GO (0x02 << 4)
+#define GPT_MODE4_FREERUN (0x03 << 4)
+
+#define GPT_CLEAR 2
+
+#define GPT_ENABLE 1
+#define GPT_DISABLE 0
+
+#define GPT_CLK_SYS (0x0 << 4)
+#define GPT_CLK_RTC (0x1 << 4)
+
+#define GPT_DIV_BY_1 0
+#define GPT_DIV_BY_2 1
+
+#define CNTPCT_BIT_MASK_L 0x00000000FFFFFFFF
+#define CNTPCT_1US_TICK ((U32)13) // 1000 / 76.92ns = 13.000
+#define CNTPCT_1MS_TICK ((U32)13000) // 1000000 / 76.92ns = 13000.520
+
+static inline U64 arch_counter_get_cntpct(void)
+{
+ U64 cval = 0;
+
+ //__asm__ __volatile__("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+ return cval;
+}
+
+extern void gpt_busy_wait_us(unsigned int timeout_us);
+extern void gpt_busy_wait_ms(unsigned int timeout_ms);
+
+extern unsigned long get_timer(unsigned long base);
+//extern void mdelay(unsigned long msec);
+//extern void udelay(unsigned long usec);
+extern void mtk_timer_init(void);
+
+void gpt_one_shot_irq(unsigned int ms);
+int gpt_irq_init(void);
+void gpt_irq_ack(void);
+extern unsigned int gpt4_tick2time_us (unsigned int tick);
+extern unsigned int gpt4_get_current_tick (void);
+extern bool gpt4_timeout_tick (U32 start_tick, U32 timeout_tick);
+extern U32 gpt4_time2tick_us (U32 time_us);
+
+#endif /* !__MT_GPT_H__ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_infracfg.h b/src/bsp/lk/platform/mt2731/include/platform/mt_infracfg.h
new file mode 100644
index 0000000..0879d10
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_infracfg.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#pragma once
+
+#include <platform/mt2731.h>
+
+#define INFRA_MISC (INFRACFG_BASE + 0xf00)
+#define DDR_4GB_SUPPORT_EN (0x1 << 13)
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_irq.h b/src/bsp/lk/platform/mt2731/include/platform/mt_irq.h
new file mode 100644
index 0000000..21f63fd
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_irq.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#define GIC_DIST_PENDING_SET 0x200
+#define GIC_DIST_ENABLE_SET 0x100
+#define GIC_DIST_ENABLE_CLEAR 0x180
+#define GIC_DIST_PENDING_CLEAR 0x280
+#define GIC_DIST_CTR 0x004
+#define GIC_DIST_CTRL 0x000
+#define GIC_DIST_TARGET 0x800
+#define GIC_DIST_ACTIVE_BIT 0x300
+#define GIC_DIST_PRI 0x400
+#define GIC_DIST_ICDISR 0x80
+#define GIC_DIST_CONFIG 0xc00
+#define GIC_DIST_SOFTINT 0xf00
+
+#define GIC_CPU_HIGHPRI 0x18
+#define GIC_CPU_EOI 0x10
+#define GIC_CPU_RUNNINGPRI 0x14
+#define GIC_CPU_BINPOINT 0x08
+#define GIC_CPU_INTACK 0x0c
+#define GIC_CPU_CTRL 0x00
+#define GIC_CPU_PRIMASK 0x04
+
+/*
+ * Define IRQ code.
+ */
+#define GIC_PRIVATE_SIGNALS (32)
+
+#define GIC_PPI_OFFSET (27)
+#define GIC_PPI_GLOBAL_TIMER (GIC_PPI_OFFSET + 0)
+#define GIC_PPI_LEGACY_FIQ (GIC_PPI_OFFSET + 1)
+#define GIC_PPI_PRIVATE_TIMER (GIC_PPI_OFFSET + 2)
+#define GIC_PPI_WATCHDOG_TIMER (GIC_PPI_OFFSET + 3)
+#define GIC_PPI_LEGACY_IRQ (GIC_PPI_OFFSET + 4)
+
+#define USB_MCU_IRQ_BIT1_ID 105
+#define MSDC0_IRQ_BIT_ID 111
+#define NFI_IRQ_BIT_ID 166
+#define NFIECC_IRQ_BIT_ID 167
+#define MT_GPT_IRQ_ID 202
+
+#define MT_NR_PPI (5)
+#define MT_NR_SPI (292)
+#define NR_IRQ_LINE (GIC_PPI_OFFSET + MT_NR_PPI + MT_NR_SPI)
+
+#define EDGE_SENSITIVE 0
+#define LEVEL_SENSITIVE 1
+
+#define MT65xx_POLARITY_LOW 0
+#define MT65xx_POLARITY_HIGH 1
+
+void mt_irq_set_sens(unsigned int irq, unsigned int sens);
+void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_reg_base.h b/src/bsp/lk/platform/mt2731/include/platform/mt_reg_base.h
new file mode 100644
index 0000000..9630305
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_reg_base.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#pragma once
+
+#include <platform/mt2731.h>
+
+/* I/O mapping */
+#define IO_PHYS PERIPHERAL_BASE_VIRT
+#define IO_SIZE PERIPHERAL_BASE_SIZE
+
+/* GIC */
+#if ARCH_ARM64
+#define GIC_DIST_BASE (KERNEL_ASPACE_BASE + 0x0C000000)
+#define GIC_REDIS_BASE (KERNEL_ASPACE_BASE + 0x0C080000)
+#endif
+
+#if ARCH_ARM
+#define GIC_DIST_BASE (0x0C000000)
+#define GIC_REDIS_BASE (0x0C080000)
+#endif
+
+#define GIC_REDIS_BASE_PHY (0x0C080000)
+
+#define CKSYS_BASE IO_PHYS /* TODO: TOPCKGEN_BASE*/
+#define INFRACFG_BASE (IO_PHYS + 0x00001000) /* TODO: INFRACFG_AO_BASE*/
+#define PERICFG_BASE (IO_PHYS + 0x00003000)
+/* IO register definitions */
+#define SPM_BASE (IO_PHYS + 0x00006000) /* TODO: SLEEP_BASE*/
+#define TOP_RGU_BASE (IO_PHYS + 0x00007000)
+#define APXGPT_BASE (IO_PHYS + 0x00008000)
+#define SEJ_BASE (IO_PHYS + 0x0000A000)
+#define APMIXED_BASE (IO_PHYS + 0x0000C000)
+#define PWRAP_BASE (IO_PHYS + 0x0000D000) /* PWRAP */
+#define bcrm_INFRA_AO_wrapper_base (IO_PHYS + 0x00015000)
+#define MCUSYS_CFGREG_BASE (IO_PHYS + 0x00200000) /* TODO: MCUCFG_BASE*/
+#define MP0_MISC_CONFIG2 (MCUSYS_CFGREG_BASE + 0x038) /* Resets vector base address bit 31~2 in 64-bit mode for CPU0 */
+#define INT_POL_CTL0 (MCUSYS_CFGREG_BASE + 0xA80) /* TODO: check */
+#define INT_POL_SECCTL0 (MCUSYS_CFGREG_BASE + 0xA00)
+#define SEC_POL_CTL_EN0 INT_POL_SECCTL0
+
+/* GPIO register definitions */
+#define GPIO_BASE (IO_PHYS + 0x00005000)
+#define IO_CFG_LM_BASE (IO_PHYS + 0x00002000)
+#define IO_CFG_LB_BASE (IO_PHYS + 0x00002200)
+#define IO_CFG_BL_BASE (IO_PHYS + 0x00002400)
+#define IO_CFG_BR_BASE (IO_PHYS + 0x00002600)
+#define IO_CFG_RB_BASE (IO_PHYS + 0x00002800)
+#define IO_CFG_RM_BASE (IO_PHYS + 0x00002A00)
+#define IO_CFG_TR_BASE (IO_PHYS + 0x00002C00)
+#define IO_CFG_TL_BASE (IO_PHYS + 0x00002E00)
+
+/*MD1*/
+#define MD1_BASE MD1_BASE_VIRT
+
+#define write_r(a, v) writel(v, a) /* need to fix it */
+
+#define UART1_BASE (IO_PHYS + 0x01002000)
+#define UART2_BASE (IO_PHYS + 0x01003000)
+#define UART3_BASE (IO_PHYS + 0x01004000)
+#define UART4_BASE (IO_PHYS + 0x01005000)
+#define I2C0_BASE (IO_PHYS + 0x01007000)
+#define I2C1_BASE (IO_PHYS + 0x01008000)
+#define I2C2_BASE (IO_PHYS + 0x01009000)
+#define I2C3_BASE (IO_PHYS + 0x0100F000)
+#define I2C4_BASE (IO_PHYS + 0x01011000)
+#define I2C0_APDMA_BASE (IO_PHYS + 0x01000080)
+#define I2C1_APDMA_BASE (IO_PHYS + 0x01000100)
+#define I2C2_APDMA_BASE (IO_PHYS + 0x01000180)
+#define I2C3_APDMA_BASE (IO_PHYS + 0x01000280)
+#define I2C4_APDMA_BASE (IO_PHYS + 0x01000300)
+
+#define NOR_BASE (IO_PHYS + 0x0100D000) /* TODO: removed? */
+#define NFI_BASE (IO_PHYS + 0x01018000) /* TODO: correct? */
+#define NFIECC_BASE (IO_PHYS + 0x01019000) /* TODO: correct? */
+#define EFUSE_BASE (IO_PHYS + 0x01c10000)
+#define MSDC0_BASE (IO_PHYS + 0x01230000)
+#define MSDC1_BASE (IO_PHYS + 0x01240000)
+#define MSDC0_TOP_BASE (IO_PHYS + 0x01C00000)
+#define MSDC1_TOP_BASE (IO_PHYS + 0x01C90000)
+#define TRNG_BASE (IO_PHYS + 0x00206000)
+
+/* USB */
+#define USB_BASE (IO_PHYS + 0x01200000)
+#define USBSIF_BASE (IO_PHYS + 0x01CC0000)
+#define USB_I2C_BASE (I2C2_BASE)
+
+/* BGR: Bandgap */
+#define BGR_BASE (IO_PHYS + 0x0000C600)
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_spm_reg.h b/src/bsp/lk/platform/mt2731/include/platform/mt_spm_reg.h
new file mode 100644
index 0000000..6316e06
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_spm_reg.h
@@ -0,0 +1,1931 @@
+/****************************************************************
+* Auto generated by DE, please DO NOT modify this file directly.
+*****************************************************************/
+
+#ifndef _MT_SPM_REG_
+#define _MT_SPM_REG_
+
+#include <platform/mt_reg_base.h>
+
+/**************************************
+ * Define and Declare
+ **************************************/
+
+#define POWERON_CONFIG_EN (SPM_BASE + 0x0000)
+#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x0004)
+#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x0008)
+#define SPM_CLK_CON (SPM_BASE + 0x000C)
+#define SPM_CLK_SETTLE (SPM_BASE + 0x0010)
+#define SPM_AP_STANDBY_CON (SPM_BASE + 0x0014)
+#define PCM_CON0 (SPM_BASE + 0x0018)
+#define PCM_CON1 (SPM_BASE + 0x001C)
+#define PCM_TIMER_VAL (SPM_BASE + 0x0020)
+#define PCM_WDT_VAL (SPM_BASE + 0x0024)
+#define PCM_REG_DATA_INI (SPM_BASE + 0x0028)
+#define PCM_PWR_IO_EN (SPM_BASE + 0x002C)
+#define PCM_TIMER_2_EN (SPM_BASE + 0x0030)
+#define PCM_TIMER_2_VAL (SPM_BASE + 0x0034)
+#define PCM_TIMER_2_SETTLE (SPM_BASE + 0x0038)
+#define PCM_TIMER_2_CLEAR (SPM_BASE + 0x003C)
+#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x00B0)
+#define SPM_IRQ_MASK (SPM_BASE + 0x00B4)
+#define SPM_SRC_REQ (SPM_BASE + 0x00B8)
+#define SPM_SRC_MASK (SPM_BASE + 0x00BC)
+#define SPM_SRC2_MASK (SPM_BASE + 0x00C0)
+#define SPM_SRC3_MASK (SPM_BASE + 0x00C4)
+#define SPM_SRC4_MASK (SPM_BASE + 0x00C8)
+#define SPM_SRC5_MASK (SPM_BASE + 0x00CC)
+#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x00D0)
+#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x00D4)
+#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x00D8)
+#define SPM_SRC6_MASK (SPM_BASE + 0x00DC)
+#define PCM_DEBUG_CON (SPM_BASE + 0x00E0)
+#define AHB_BUS_CON (SPM_BASE + 0x00E4)
+#define DDR_EN_DBC_CON0 (SPM_BASE + 0x00E8)
+#define DDR_EN_DBC_CON1 (SPM_BASE + 0x00EC)
+#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x00F0)
+#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x00F4)
+#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x00F8)
+#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x00FC)
+#define PCM_REG0_DATA (SPM_BASE + 0x0100)
+#define PCM_REG2_DATA (SPM_BASE + 0x0104)
+#define PCM_REG6_DATA (SPM_BASE + 0x0108)
+#define PCM_REG7_DATA (SPM_BASE + 0x010C)
+#define PCM_REG13_DATA (SPM_BASE + 0x0110)
+#define SRC_REQ_STA_0 (SPM_BASE + 0x0114)
+#define SRC_REQ_STA_1 (SPM_BASE + 0x0118)
+#define SRC_REQ_STA_2 (SPM_BASE + 0x011C)
+#define SRC_REQ_STA_3 (SPM_BASE + 0x0120)
+#define SRC_REQ_STA_4 (SPM_BASE + 0x0124)
+#define PCM_TIMER_OUT (SPM_BASE + 0x0128)
+#define PCM_WDT_OUT (SPM_BASE + 0x012C)
+#define SPM_IRQ_STA (SPM_BASE + 0x0130)
+#define SUBSYS_IDLE_STA (SPM_BASE + 0x0134)
+#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x0138)
+#define MD32PCM_EVENT_STA (SPM_BASE + 0x013C)
+#define SPM_WAKEUP_STA (SPM_BASE + 0x0140)
+#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x0144)
+#define SPM_WAKEUP_MISC (SPM_BASE + 0x0148)
+#define BUS_PROTECT_RDY (SPM_BASE + 0x014C)
+#define BUS_PROTECT2_RDY (SPM_BASE + 0x0150)
+#define BUS_PROTECT3_RDY (SPM_BASE + 0x0154)
+#define BUS_PROTECT4_RDY (SPM_BASE + 0x0158)
+#define PCM_STA (SPM_BASE + 0x015C)
+#define PWR_STATUS (SPM_BASE + 0x0160)
+#define PWR_STATUS_2ND (SPM_BASE + 0x0164)
+#define CPU_PWR_STATUS (SPM_BASE + 0x0168)
+#define SPM_SRC_RDY_STA (SPM_BASE + 0x016C)
+#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x0170)
+#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x0174)
+#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x0178)
+#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x017C)
+#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x0180)
+#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x0184)
+#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x0188)
+#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x018C)
+#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x0190)
+#define SPM_TWAM_CON (SPM_BASE + 0x0194)
+#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0198)
+#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x019C)
+#define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x01A0)
+#define SPM_PC_STA (SPM_BASE + 0x01A4)
+#define DVFSRC_EVENT_STA (SPM_BASE + 0x01A8)
+#define GIC_WAKEUP_STA (SPM_BASE + 0x01B0)
+#define SYS_TIMER_OUT_L (SPM_BASE + 0x01B4)
+#define SYS_TIMER_OUT_H (SPM_BASE + 0x01B8)
+#define SPM_CG_CHECK_STA (SPM_BASE + 0x01BC)
+#define SPM_DVFS_HISTORY_STA0 (SPM_BASE + 0x01C0)
+#define SPM_DVFS_HISTORY_STA1 (SPM_BASE + 0x01C4)
+#define SPM_DDREN_SLEEP_COUNT (SPM_BASE + 0x01C8)
+#define SPM_DDREN_WAKE_COUNT (SPM_BASE + 0x01CC)
+#define SPM_APSRC_COUNT (SPM_BASE + 0x01D0)
+#define SPM_VRF18_COUNT (SPM_BASE + 0x01D4)
+#define SPM_INFRA_COUNT (SPM_BASE + 0x01D8)
+#define SPM_26M_COUNT (SPM_BASE + 0x01DC)
+#define ECC_CORRECTABLE_ERR_COUNTER (SPM_BASE + 0x01E0)
+#define ECC_SECOND_ERR_COUNTER (SPM_BASE + 0x01E4)
+#define ECC_SECOND_ERR_FLAG_MASK (SPM_BASE + 0x01E8)
+#define ECC_PARITY_STA (SPM_BASE + 0x01EC)
+#define PCM_TIMER_2_OUT (SPM_BASE + 0x01F0)
+#define SPMC_STATUS (SPM_BASE + 0x01F4)
+#define ECC_SECOND_ERR_STA (SPM_BASE + 0x01F8)
+#define MCUSYS_PWR_CON (SPM_BASE + 0x0200)
+#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x0204)
+#define MP0_CPU0_PWR_CON (SPM_BASE + 0x0208)
+#define MP0_CPU1_PWR_CON (SPM_BASE + 0x020C)
+#define ARMPLL_CLK_CON (SPM_BASE + 0x022C)
+#define MCUSYS_IDLE_STA (SPM_BASE + 0x0230)
+#define MCUSYS_WAKE_STA (SPM_BASE + 0x0234)
+#define CPU_SPARE_CON (SPM_BASE + 0x0238)
+#define CPU_SPARE_CON_SET (SPM_BASE + 0x023C)
+#define CPU_SPARE_CON_CLR (SPM_BASE + 0x0240)
+#define AMRPLL_CLK_SEL (SPM_BASE + 0x0244)
+#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x0248)
+#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x024C)
+#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x0250)
+#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x0268)
+#define ROOT_CORE_ADDR (SPM_BASE + 0x026C)
+#define SYS_TIMER_CON (SPM_BASE + 0x0274)
+#define MP0_L2CFLUSH (SPM_BASE + 0x0278)
+#define CPU_MCDI_WFI_EN (SPM_BASE + 0x027C)
+#define CPU_MCDI_WFI_EN_SET (SPM_BASE + 0x0280)
+#define CPU_MCDI_WFI_EN_CLR (SPM_BASE + 0x0284)
+#define CPU_MCDI_WAKE_EN (SPM_BASE + 0x0288)
+#define IFR_PWR_CON (SPM_BASE + 0x0310)
+#define DPY_PWR_CON (SPM_BASE + 0x0314)
+#define MD1_PWR_CON (SPM_BASE + 0x0318)
+#define MD1_SRAM_ISOINT_B (SPM_BASE + 0x0320)
+#define SYSRAM_CON (SPM_BASE + 0x0354)
+#define SYSROM_CON (SPM_BASE + 0x0358)
+#define DPY_SHU_SRAM_CON (SPM_BASE + 0x036C)
+#define DUMMY_SRAM_CON (SPM_BASE + 0x03AC)
+#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x03B0)
+#define GCPU_SRAM_CON (SPM_BASE + 0x03CC)
+#define GCPU_EXTEND_SRAM_CON (SPM_BASE + 0x03D0)
+#define DCCM_E_SRAM_CON (SPM_BASE + 0x03D4)
+#define DCCM_O_SRAM_CON (SPM_BASE + 0x03D8)
+#define ICCM_S1_SRAM_CON (SPM_BASE + 0x03DC)
+#define ICCM_S2_SRAM_CON (SPM_BASE + 0x03E0)
+#define HSM_SRAM_CON (SPM_BASE + 0x03E4)
+#define ETHERNET_SRAM_CON (SPM_BASE + 0x03E8)
+#define PCIE_SRAM_CON (SPM_BASE + 0x03EC)
+#define MD_EXTRA_PWR_CON (SPM_BASE + 0x03F0)
+#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x0400)
+#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x0404)
+#define SPM_MAS_PAUSE3_MASK_B (SPM_BASE + 0x0408)
+#define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x040C)
+#define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x0410)
+#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x0414)
+#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x0418)
+#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x041C)
+#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x0420)
+#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x0424)
+#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x0428)
+#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x042C)
+#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x0430)
+#define AP_MDSRC_REQ (SPM_BASE + 0x0434)
+#define SPM2MD_DVFS_CON (SPM_BASE + 0x0438)
+#define MD2SPM_DVFS_CON (SPM_BASE + 0x043C)
+#define ULPOSC_CON (SPM_BASE + 0x0440)
+#define SPM_SWINT (SPM_BASE + 0x0448)
+#define SPM_SWINT_SET (SPM_BASE + 0x044C)
+#define SPM_SWINT_CLR (SPM_BASE + 0x0450)
+#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x0454)
+#define SPM_PLL_CON (SPM_BASE + 0x0458)
+#define SPM_S1_MODE_CH (SPM_BASE + 0x045C)
+#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x0460)
+#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x0464)
+#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x0468)
+#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x046C)
+#define DRAMC_DPY_CLK_SW_CON_SEL3 (SPM_BASE + 0x0470)
+#define DRAMC_DPY_CLK_SW_CON3 (SPM_BASE + 0x0474)
+#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x0478)
+#define SPM_MEM_CK_SEL (SPM_BASE + 0x047C)
+#define SPM_SEMA_M0 (SPM_BASE + 0x0480)
+#define SPM_SEMA_M1 (SPM_BASE + 0x0484)
+#define SPM_SEMA_M2 (SPM_BASE + 0x0488)
+#define SPM_SEMA_M3 (SPM_BASE + 0x048C)
+#define SPM_SEMA_M4 (SPM_BASE + 0x0490)
+#define SPM_SEMA_M5 (SPM_BASE + 0x0494)
+#define SPM_SEMA_M6 (SPM_BASE + 0x0498)
+#define SPM_SEMA_M7 (SPM_BASE + 0x049C)
+#define SPM_AP_SEMA (SPM_BASE + 0x04A0)
+#define SPM_SPM_SEMA (SPM_BASE + 0x04A4)
+#define SPM_SSPM_CON (SPM_BASE + 0x04A8)
+#define SPM_SCP_CON (SPM_BASE + 0x04AC)
+#define SPM_ADSP_CON (SPM_BASE + 0x04B0)
+#define SPM2ADSP_MAILBOX (SPM_BASE + 0x04B4)
+#define ADSP2SPM_MAILBOX (SPM_BASE + 0x04B8)
+#define SPM_SCP_MAILBOX (SPM_BASE + 0x04BC)
+#define SCP_SPM_MAILBOX (SPM_BASE + 0x04C0)
+#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x04C4)
+#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x04C8)
+#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x04CC)
+#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x04D0)
+#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x04D4)
+#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x04D8)
+#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x04DC)
+#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x04E0)
+#define SPM_CIRQ_CON (SPM_BASE + 0x04E4)
+#define SW2SPM_INT (SPM_BASE + 0x04E8)
+#define SW2SPM_INT_SET (SPM_BASE + 0x04EC)
+#define SW2SPM_INT_CLR (SPM_BASE + 0x04F0)
+#define SPM_DVFS_MISC (SPM_BASE + 0x04F4)
+#define SCP_VCORE_LEVEL (SPM_BASE + 0x04F8)
+#define SRCLKEN_RC_CFG (SPM_BASE + 0x0500)
+#define RC_CENTRAL_CFG1 (SPM_BASE + 0x0504)
+#define RC_CENTRAL_CFG2 (SPM_BASE + 0x0508)
+#define RC_CMD_ARB_CFG (SPM_BASE + 0x050C)
+#define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x0510)
+#define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x0514)
+#define RC_DCXO_FPM_CFG (SPM_BASE + 0x0518)
+#define RC_CENTRAL_CFG3 (SPM_BASE + 0x051C)
+#define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x0520)
+#define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x0524)
+#define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x0528)
+#define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x052C)
+#define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x0530)
+#define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x0534)
+#define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x0538)
+#define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x053C)
+#define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x0540)
+#define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x0544)
+#define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x0548)
+#define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x054C)
+#define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x0550)
+#define RC_SPM_CTRL (SPM_BASE + 0x05B8)
+#define SUBSYS_INTF_CFG (SPM_BASE + 0x05BC)
+#define SPM_SW_FLAG_0 (SPM_BASE + 0x0600)
+#define SPM_SW_FLAG_1 (SPM_BASE + 0x0604)
+#define SPM_SW_RSV_0 (SPM_BASE + 0x0608)
+#define SPM_SW_RSV_1 (SPM_BASE + 0x060C)
+#define SPM_SW_RSV_2 (SPM_BASE + 0x0610)
+#define SPM_SW_RSV_3 (SPM_BASE + 0x0614)
+#define SPM_SW_RSV_4 (SPM_BASE + 0x0618)
+#define SPM_SW_RSV_5 (SPM_BASE + 0x061C)
+#define SPM_SW_RSV_6 (SPM_BASE + 0x0620)
+#define SPM_SW_RSV_7 (SPM_BASE + 0x0624)
+#define SPM_SW_RSV_8 (SPM_BASE + 0x0628)
+#define SPM_SW_RSV_9 (SPM_BASE + 0x062C)
+#define SPM_SW_RSV_10 (SPM_BASE + 0x0630)
+#define SPM_SW_RSV_11 (SPM_BASE + 0x0634)
+#define SPM_SW_RSV_18 (SPM_BASE + 0x0638)
+#define SPM_SW_RSV_19 (SPM_BASE + 0x063C)
+#define SPM_RSV_CON_0 (SPM_BASE + 0x0640)
+#define SPM_RSV_CON_1 (SPM_BASE + 0x0644)
+#define SPM_RSV_STA_0 (SPM_BASE + 0x0648)
+#define SPM_RSV_STA_1 (SPM_BASE + 0x064C)
+#define SPM_SPARE_CON (SPM_BASE + 0x0650)
+#define SPM_SPARE_CON_SET (SPM_BASE + 0x0654)
+#define SPM_SPARE_CON_CLR (SPM_BASE + 0x0658)
+#define SPM_DV_CON_0 (SPM_BASE + 0x065C)
+#define SPM_DV_CON_1 (SPM_BASE + 0x0660)
+#define SPM_FORCE_DVFS (SPM_BASE + 0x0664)
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_0_MASK (SPM_BASE + 0x0668)
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_1_MASK (SPM_BASE + 0x066C)
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_2_MASK (SPM_BASE + 0x0670)
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_3_MASK (SPM_BASE + 0x0674)
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_4_MASK (SPM_BASE + 0x0678)
+#define INFRA2SPM_SODI_CG_CHECK_0_MASK (SPM_BASE + 0x067C)
+#define INFRA2SPM_SODI_CG_CHECK_1_MASK (SPM_BASE + 0x0680)
+#define INFRA2SPM_SODI_CG_CHECK_2_MASK (SPM_BASE + 0x0684)
+#define INFRA2SPM_SODI_CG_CHECK_3_MASK (SPM_BASE + 0x0688)
+#define INFRA2SPM_SODI_CG_CHECK_4_MASK (SPM_BASE + 0x068C)
+#define INFRA2SPM_SODI3_CG_CHECK_0_MASK (SPM_BASE + 0x0690)
+#define INFRA2SPM_SODI3_CG_CHECK_1_MASK (SPM_BASE + 0x0694)
+#define INFRA2SPM_SODI3_CG_CHECK_2_MASK (SPM_BASE + 0x0698)
+#define INFRA2SPM_SODI3_CG_CHECK_3_MASK (SPM_BASE + 0x069C)
+#define INFRA2SPM_SODI3_CG_CHECK_4_MASK (SPM_BASE + 0x06A0)
+#define INFRA2SPM_MCDSR_CG_CHECK_0_MASK (SPM_BASE + 0x06A4)
+#define INFRA2SPM_MCDSR_CG_CHECK_1_MASK (SPM_BASE + 0x06A8)
+#define INFRA2SPM_MCDSR_CG_CHECK_2_MASK (SPM_BASE + 0x06AC)
+#define INFRA2SPM_MCDSR_CG_CHECK_3_MASK (SPM_BASE + 0x06B0)
+#define INFRA2SPM_MCDSR_CG_CHECK_4_MASK (SPM_BASE + 0x06B4)
+#define OTHER2SPM_CG_CHECK_MASK (SPM_BASE + 0x06B8)
+#define SPM_TIMER_0 (SPM_BASE + 0x06BC)
+#define SPM_TIMER_1 (SPM_BASE + 0x06C0)
+#define SPM_TIMER_2 (SPM_BASE + 0x06C4)
+#define UFS_PSRI_SW (SPM_BASE + 0x06D0)
+#define UFS_PSRI_SW_SET (SPM_BASE + 0x06D4)
+#define UFS_PSRI_SW_CLR (SPM_BASE + 0x06D8)
+#define SPM_DVFS_CON (SPM_BASE + 0x0700)
+#define SPM_DVFS_CON_STA (SPM_BASE + 0x0704)
+#define SPM_DVFS_LEVEL (SPM_BASE + 0x0708)
+#define SPM_DVFS_STA (SPM_BASE + 0x070C)
+#define SPM_DVFS_CMD0 (SPM_BASE + 0x0710)
+#define SPM_DVFS_CMD1 (SPM_BASE + 0x0714)
+#define SPM_DVFS_CMD2 (SPM_BASE + 0x0718)
+#define SPM_DVFS_CMD3 (SPM_BASE + 0x071C)
+#define SPM_DVFS_CMD4 (SPM_BASE + 0x0720)
+#define SPM_DVFS_CMD5 (SPM_BASE + 0x0724)
+#define SPM_DVFS_CMD6 (SPM_BASE + 0x0728)
+#define SPM_DVFS_CMD7 (SPM_BASE + 0x072C)
+#define SPM_DVFS_CMD8 (SPM_BASE + 0x0730)
+#define SPM_DVFS_CMD9 (SPM_BASE + 0x0734)
+#define SPM_DVFS_CMD10 (SPM_BASE + 0x0738)
+#define SPM_DVFS_CMD11 (SPM_BASE + 0x073C)
+#define SPM_DVFS_CMD12 (SPM_BASE + 0x0740)
+#define SPM_DVFS_CMD13 (SPM_BASE + 0x0744)
+#define SPM_DVFS_CMD14 (SPM_BASE + 0x0748)
+#define SPM_DVFS_CMD15 (SPM_BASE + 0x074C)
+#define SPM_DVFS_CMD16 (SPM_BASE + 0x0750)
+#define SPM_DVFS_CMD17 (SPM_BASE + 0x0754)
+#define SPM_DVFS_CMD18 (SPM_BASE + 0x0758)
+#define SPM_DVFS_CMD19 (SPM_BASE + 0x075C)
+#define SPM_DVFS_CMD20 (SPM_BASE + 0x0760)
+#define SPM_DVFS_CMD21 (SPM_BASE + 0x0764)
+#define SPM_DVFS_CMD22 (SPM_BASE + 0x0768)
+#define SPM_DVFS_CMD23 (SPM_BASE + 0x076C)
+#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x07BC)
+#define PCM_WDT_LATCH_0 (SPM_BASE + 0x0800)
+#define PCM_WDT_LATCH_1 (SPM_BASE + 0x0804)
+#define PCM_WDT_LATCH_2 (SPM_BASE + 0x0808)
+#define PCM_WDT_LATCH_3 (SPM_BASE + 0x080C)
+#define PCM_WDT_LATCH_4 (SPM_BASE + 0x0810)
+#define PCM_WDT_LATCH_5 (SPM_BASE + 0x0814)
+#define PCM_WDT_LATCH_6 (SPM_BASE + 0x0818)
+#define PCM_WDT_LATCH_7 (SPM_BASE + 0x081C)
+#define PCM_WDT_LATCH_8 (SPM_BASE + 0x0820)
+#define PCM_WDT_LATCH_9 (SPM_BASE + 0x0824)
+#define PCM_WDT_LATCH_10 (SPM_BASE + 0x0828)
+#define PCM_WDT_LATCH_11 (SPM_BASE + 0x082C)
+#define PCM_WDT_LATCH_12 (SPM_BASE + 0x0830)
+#define PCM_WDT_LATCH_13 (SPM_BASE + 0x0834)
+#define PCM_WDT_LATCH_14 (SPM_BASE + 0x0838)
+#define PCM_WDT_LATCH_15 (SPM_BASE + 0x083C)
+#define PCM_WDT_LATCH_16 (SPM_BASE + 0x0840)
+#define PCM_WDT_LATCH_17 (SPM_BASE + 0x0844)
+#define PCM_WDT_LATCH_18 (SPM_BASE + 0x0848)
+#define DVFSRC_IRQ_LATCH_0 (SPM_BASE + 0x084C)
+#define DVFSRC_IRQ_LATCH_1 (SPM_BASE + 0x0850)
+#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x0854)
+#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x0858)
+#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x085C)
+#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x0860)
+#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x0864)
+#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x0868)
+#define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x086C)
+#define DRAMC_GATING_ERR_LATCH_CH0_7 (SPM_BASE + 0x0870)
+#define DRAMC_GATING_ERR_LATCH_CH0_8 (SPM_BASE + 0x0874)
+#define DRAMC_GATING_ERR_LATCH_CH1_0 (SPM_BASE + 0x0878)
+#define DRAMC_GATING_ERR_LATCH_CH1_1 (SPM_BASE + 0x087C)
+#define DRAMC_GATING_ERR_LATCH_CH1_2 (SPM_BASE + 0x0880)
+#define DRAMC_GATING_ERR_LATCH_CH1_3 (SPM_BASE + 0x0884)
+#define DRAMC_GATING_ERR_LATCH_CH1_4 (SPM_BASE + 0x0888)
+#define DRAMC_GATING_ERR_LATCH_CH1_5 (SPM_BASE + 0x088C)
+#define DRAMC_GATING_ERR_LATCH_CH1_6 (SPM_BASE + 0x0890)
+#define DRAMC_GATING_ERR_LATCH_CH1_7 (SPM_BASE + 0x0894)
+#define DRAMC_GATING_ERR_LATCH_CH1_8 (SPM_BASE + 0x0898)
+#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x089C)
+#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x08A0)
+#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x08A4)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x08A8)
+#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x0900)
+#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x0904)
+#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x0908)
+#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x090C)
+#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x0910)
+#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x0914)
+#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x0918)
+#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x091C)
+#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x0920)
+#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x0924)
+#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x0928)
+#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x092C)
+#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x0930)
+#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x0934)
+#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x0938)
+#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x093C)
+#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x0940)
+#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x0944)
+#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x0948)
+#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x094C)
+#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x0950)
+#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x0954)
+#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x0958)
+#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x095C)
+#define SPM_ACK_CHK_CON_4 (SPM_BASE + 0x0960)
+#define SPM_ACK_CHK_PC_4 (SPM_BASE + 0x0964)
+#define SPM_ACK_CHK_SEL_4 (SPM_BASE + 0x0968)
+#define SPM_ACK_CHK_TIMER_4 (SPM_BASE + 0x096C)
+#define SPM_ACK_CHK_STA_4 (SPM_BASE + 0x0970)
+#define SPM_ACK_CHK_SWINT_4 (SPM_BASE + 0x0974)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 4) /* 1b */
+#define REG_SRCCLKEN_MASK_LSB (1U << 5) /* 3b */
+#define REG_MD1_C32RM_EN_LSB (1U << 8) /* 1b */
+#define REG_MD2_C32RM_EN_LSB (1U << 9) /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 10) /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define REG_SRCCLKEN0_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN1_EN_LSB (1U << 13) /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 14) /* 9b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 9b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB (1U << 0) /* 1b */
+#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define RG_EN_IM_ECC_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
+#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 2) /* 1b */
+#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
+#define RG_IM_PDN_LSB (1U << 4) /* 1b */
+#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define RG_SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
+#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_TIMER_VAL (0x10006000+0x020) */
+#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x024) */
+#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_2_EN (0x10006000+0x030) */
+#define REG_PCM_TIMER_2_EN_LSB (1U << 0) /* 1b */
+/* PCM_TIMER_2_VAL (0x10006000+0x034) */
+#define REG_PCM_TIMER_2_VAL_LSB (1U << 0) /* 32b */
+/* PCM_TIMER_2_SETTLE (0x10006000+0x038) */
+#define REG_PCM_TIMER_2_SETTLE_LSB (1U << 0) /* 1b */
+/* PCM_TIMER_2_CLEAR (0x10006000+0x03C) */
+#define REG_PCM_TIMER_2_CLEAR_LSB (1U << 0) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
+#define REG_SPM_DDR_EN2_REQ_LSB (1U << 8) /* 1b */
+#define REG_SPM_DVFS_REQ_LSB (1U << 9) /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 10) /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 11) /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_PCIE_LOCK_MAILBOX_REQ_LSB (1U << 13) /* 1b */
+#define REG_SPM_MCUSYS_PWR_EVENT_REQ_LSB (1U << 14) /* 1b */
+#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 15) /* 1b */
+#define FORCE_INFRA_PCIE_LOCK_MAILBOX_WAKE_LSB (1U << 16) /* 1b */
+#define INFRA_PCIE_PWR_LOCK_SPM_MODE_LSB (1U << 17) /* 1b */
+#define SC_INFRA_PCIE_PWR_LOCK_LSB (1U << 18) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MD_DDR_EN2_0_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_MD_DDR_EN2_1_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_INFRASYS_DDR_EN2_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_CONN_VFE28_REQ_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_PCIE_DDR_EN2_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_DPMAIF_DDR_EN2_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_UFS_DDR_EN2_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_DISP0_DDR_EN2_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_DISP1_DDR_EN2_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_GCE_DDR_EN2_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_EMI_CH0_DDR_EN_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_EMI_CH1_DDR_EN_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_EMI_CH0_DDR_EN2_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_EMI_CH1_DDR_EN2_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
+#define REG_SC_INFRA_PCIE_LOCK_2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_SPM_DDR_EN2_RESERVED_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_CLDMA_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_CLDMA_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_CLDMA_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_CLDMA_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_CLDMA_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_CLDMA_DDR_EN2_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_MCUSYS_PWR_EVENT_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MSDC0_DDR_EN2_MASK_B_LSB (1U << 30) /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN2_MASK_B_LSB (1U << 18) /* 9b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_CG_CHECK_DDR_EN2_MASK_B_LSB (1U << 30) /* 1b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SPM_SRC6_MASK (0x10006000+0x0DC) */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MSDC1_DDR_EN2_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MSDC2_DDR_EN2_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_MSDC1_DDR_EN2_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_MSDC2_DDR_EN2_ACK_MASK_LSB (1U << 27) /* 1b */
+/* PCM_DEBUG_CON (0x10006000+0x0E0) */
+#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */
+/* AHB_BUS_CON (0x10006000+0x0E4) */
+#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */
+#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */
+/* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */
+#define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */
+#define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */
+/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */
+#define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN2_ACK_0_MASK_LSB (1U << 5) /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 6) /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 7) /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 8) /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 9) /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 10) /* 1b */
+#define REG_MD_DDR_EN2_ACK_1_MASK_LSB (1U << 11) /* 1b */
+#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_PCIE_DDR_EN2_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_DPMAIF_DDR_EN2_ACK_MASK_LSB (1U << 29) /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_CLDMA_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
+#define REG_CLDMA_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
+#define REG_CLDMA_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
+#define REG_CLDMA_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
+#define REG_CLDMA_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
+#define REG_CLDMA_DDR_EN2_ACK_MASK_LSB (1U << 5) /* 1b */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 6) /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 7) /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_UFS_DDR_EN2_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_DISP0_DDR_EN2_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_DISP1_DDR_EN2_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_GCE_DDR_EN2_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_MSDC0_DDR_EN2_ACK_MASK_LSB (1U << 28) /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_RESOURCE_ACK_CON2_RSV_LSB (1U << 0) /* 1b */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_DDR_EN2_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
+#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
+#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
+#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
+#define MD_DDR_EN2_0_LSB (1U << 6) /* 1b */
+#define MD_SRCCLKENA_1_LSB (1U << 7) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 8) /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB (1U << 9) /* 1b */
+#define MD_APSRC_REQ_1_LSB (1U << 10) /* 1b */
+#define MD_VRF18_REQ_1_LSB (1U << 11) /* 1b */
+#define MD_DDR_EN_1_LSB (1U << 12) /* 1b */
+#define MD_DDR_EN2_1_LSB (1U << 13) /* 1b */
+#define SRCCLKENI_LSB (1U << 20) /* 3b */
+#define PCIE_SRCCLKENA_LSB (1U << 23) /* 1b */
+#define PCIE_INFRA_REQ_LSB (1U << 24) /* 1b */
+#define PCIE_APSRC_REQ_LSB (1U << 25) /* 1b */
+#define PCIE_VRF18_REQ_LSB (1U << 26) /* 1b */
+#define PCIE_DDR_EN_LSB (1U << 27) /* 1b */
+#define PCIE_DDR_EN2_LSB (1U << 28) /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB (1U << 29) /* 1b */
+#define MCUSYS_PWR_ON_ACK_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define DPMAIF_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define DPMAIF_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define DPMAIF_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define DPMAIF_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define DPMAIF_DDR_EN_LSB (1U << 4) /* 1b */
+#define DPMAIF_DDR_EN2_LSB (1U << 5) /* 1b */
+#define CLDMA_SRCCLKENA_LSB (1U << 6) /* 1b */
+#define CLDMA_INFRA_REQ_LSB (1U << 7) /* 1b */
+#define CLDMA_APSRC_REQ_LSB (1U << 8) /* 1b */
+#define CLDMA_VRF18_REQ_LSB (1U << 9) /* 1b */
+#define CLDMA_DDR_EN_LSB (1U << 10) /* 1b */
+#define CLDMA_DDR_EN2_LSB (1U << 11) /* 1b */
+#define UFS_SRCCLKENA_LSB (1U << 12) /* 1b */
+#define UFS_INFRA_REQ_LSB (1U << 13) /* 1b */
+#define UFS_APSRC_REQ_LSB (1U << 14) /* 1b */
+#define UFS_VRF18_REQ_LSB (1U << 15) /* 1b */
+#define UFS_DDR_EN_LSB (1U << 16) /* 1b */
+#define UFS_DDR_EN2_LSB (1U << 17) /* 1b */
+#define DISP0_APSRC_REQ_LSB (1U << 18) /* 1b */
+#define DISP0_DDR_EN_LSB (1U << 19) /* 1b */
+#define DISP0_DDR_EN2_LSB (1U << 20) /* 1b */
+#define DISP1_APSRC_REQ_LSB (1U << 21) /* 1b */
+#define DISP1_DDR_EN_LSB (1U << 22) /* 1b */
+#define DISP1_DDR_EN2_LSB (1U << 23) /* 1b */
+#define GCE_INFRA_REQ_LSB (1U << 24) /* 1b */
+#define GCE_APSRC_REQ_LSB (1U << 25) /* 1b */
+#define GCE_VRF18_REQ_LSB (1U << 26) /* 1b */
+#define GCE_DDR_EN_LSB (1U << 27) /* 1b */
+#define GCE_DDR_EN2_LSB (1U << 28) /* 1b */
+#define INFRASYS_APSRC_REQ_LSB (1U << 29) /* 1b */
+#define INFRASYS_DDR_EN_LSB (1U << 30) /* 1b */
+#define INFRASYS_DDR_EN2_LSB (1U << 31) /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
+#define SW2SPM_INT_LSB (1U << 11) /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
+#define SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
+#define SPM_DDR_EN2_RESERVED_LSB (1U << 26) /* 1b */
+/* SRC_REQ_STA_3 (0x10006000+0x120) */
+#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
+#define F26M_STATE_LSB (1U << 16) /* 1b */
+#define INFRA_STATE_LSB (1U << 17) /* 1b */
+#define APSRC_STATE_LSB (1U << 18) /* 1b */
+#define VRF18_STATE_LSB (1U << 19) /* 1b */
+#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
+#define DDR_EN2_STATE_LSB (1U << 21) /* 1b */
+#define DVFS_STATE_LSB (1U << 22) /* 1b */
+#define SW_MAILBOX_STATE_LSB (1U << 23) /* 1b */
+#define SSPM_MAILBOX_STATE_LSB (1U << 24) /* 1b */
+#define ADSP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
+#define INFRA_PCIE_LOCK_MAILBOX_STATE_LSB (1U << 26) /* 1b */
+#define MCUSYS_PWR_EVENT_STATE_LSB (1U << 27) /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x124) */
+#define MSDC0_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define MSDC0_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define MSDC0_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define MSDC0_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define MSDC0_DDR_EN_LSB (1U << 4) /* 1b */
+#define MSDC0_DDR_EN2_LSB (1U << 5) /* 1b */
+#define CG_CHECK_DDR_EN_LSB (1U << 24) /* 1b */
+#define CG_CHECK_DDR_EN2_LSB (1U << 25) /* 1b */
+#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
+#define MSDC1_DDR_EN2_LSB (1U << 31) /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x128) */
+#define PCM_TIMER_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x12C) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x130) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* SUBSYS_IDLE_STA (0x10006000+0x134) */
+#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x138) */
+#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x13C) */
+#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x140) */
+#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x144) */
+#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x148) */
+#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
+#define PCM_TIMER_2_EVENT_LSB (1U << 15) /* 1b */
+#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
+#define PCM_TIMER_EVENT_LSB (1U << 17) /* 1b */
+#define PMIC_EINT_OUT_B_LSB (1U << 18) /* 2b */
+#define TWAM_IRQ_B_LSB (1U << 20) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 24) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 25) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 26) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 27) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_4_LSB (1U << 28) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
+#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
+/* BUS_PROTECT_RDY (0x10006000+0x14C) */
+#define PROTECT_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x150) */
+#define PROTECT2_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x154) */
+#define PROTECT3_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x158) */
+#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */
+#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */
+/* PCM_STA (0x10006000+0x15C) */
+#define PCM_CK_SEL_O_LSB (1U << 0) /* 3b */
+#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
+#define RAM_SEQ_ATPG_EN_LSB (1U << 7) /* 1b */
+#define WDT_GPU_EXT_BUCK_ISO_LSB (1U << 8) /* 1b */
+/* PWR_STATUS (0x10006000+0x160) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x164) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x168) */
+#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_SRC_RDY_STA (0x10006000+0x16C) */
+#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
+#define SPM_DDR_EN2_INTERNAL_ACK_LSB (1U << 2) /* 1b */
+#define SPM_DDR_EN2_INTERNAL_ACK_SEL_LSB (1U << 3) /* 1b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x170) */
+#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x174) */
+#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x178) */
+#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x17C) */
+#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x180) */
+#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x184) */
+#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x188) */
+#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x18C) */
+#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x190) */
+#define TWAM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x194) */
+#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
+#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x198) */
+#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x19C) */
+#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
+/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x1A0) */
+#define MFG_EFUSE_S2P_RX_DONE_LSB (1U << 0) /* 1b */
+#define CAM_EFUSE_S2P_RX_DONE_LSB (1U << 1) /* 1b */
+#define INFRA_PWR_EFUSE_S2P_RX_DONE_LSB (1U << 2) /* 1b */
+#define INFRA_AO_EFUSE_S2P_RX_DONE_LSB (1U << 3) /* 1b */
+/* SPM_PC_STA (0x10006000+0x1A4) */
+#define MON_PC_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A8) */
+#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
+/* GIC_WAKEUP_STA (0x10006000+0x1B0) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
+/* SYS_TIMER_OUT_L (0x10006000+0x1B4) */
+#define SYS_TIMER_OUT_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_OUT_H (0x10006000+0x1B8) */
+#define SYS_TIMER_OUT_H_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1BC) */
+#define SPM_DEEPIDLE_CG_CHECK_RESULT_LSB (1U << 0) /* 1b */
+#define SPM_SODI_CG_CHECK_RESULT_LSB (1U << 1) /* 1b */
+#define SPM_SODI3_CG_CHECK_RESULT_LSB (1U << 2) /* 1b */
+#define SPM_MCDSR_CG_CHECK_RESULT_LSB (1U << 3) /* 1b */
+/* SPM_DVFS_HISTORY_STA0 (0x10006000+0x1C0) */
+#define SPM_DVFS_HISTORY_STA0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_HISTORY_STA1 (0x10006000+0x1C4) */
+#define SPM_DVFS_HISTORY_STA1_LSB (1U << 0) /* 32b */
+/* SPM_DDREN_SLEEP_COUNT (0x10006000+0x1C8) */
+#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 32b */
+/* SPM_DDREN_WAKE_COUNT (0x10006000+0x1CC) */
+#define SPM_DDREN_WAKE_COUNT_LSB (1U << 0) /* 32b */
+/* SPM_APSRC_COUNT (0x10006000+0x1D0) */
+#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_VRF18_COUNT (0x10006000+0x1D4) */
+#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_INFRA_COUNT (0x10006000+0x1D8) */
+#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_26M_COUNT (0x10006000+0x1DC) */
+#define SPM_26M_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_26M_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* ECC_CORRECTABLE_ERR_COUNTER (0x10006000+0x1E0) */
+#define ECC_CORRECTABLE_ERR_COUNTER_0_LSB (1U << 0) /* 16b */
+#define ECC_CORRECTABLE_ERR_COUNTER_1_LSB (1U << 16) /* 16b */
+/* ECC_SECOND_ERR_COUNTER (0x10006000+0x1E4) */
+#define ECC_SECOND_ERR_COUNTER_0_LSB (1U << 0) /* 16b */
+#define ECC_SECOND_ERR_COUNTER_1_LSB (1U << 16) /* 16b */
+/* ECC_SECOND_ERR_FLAG_MASK (0x10006000+0x1E8) */
+#define REG_ECC_SECOND_ERR_FLAG_MASK_LSB (1U << 0) /* 1b */
+/* ECC_PARITY_STA (0x10006000+0x1EC) */
+#define PARITY_BLOCK0_LSB (1U << 0) /* 7b */
+#define PARITY_BLOCK1_LSB (1U << 7) /* 7b */
+#define M_RDATA_0_CPO_LSB (1U << 14) /* 7b */
+#define M_RDATA_1_CPO_LSB (1U << 21) /* 7b */
+/* PCM_TIMER_2_OUT (0x10006000+0x1F0) */
+#define PCM_TIMER_2_LSB (1U << 0) /* 32b */
+/* SPMC_STATUS (0x10006000+0x1F4) */
+#define SC_SPMC_STATUS_LSB (1U << 0) /* 8b */
+/* ECC_SECOND_ERR_STA (0x10006000+0x1F8) */
+#define ECC_SECOND_ERR_FLAG_AFTMSK_LSB (1U << 0) /* 1b */
+/* MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUSYS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MCUSYS_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUSYS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MCUSYS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUSYS_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MCUSYS_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MCUSYS_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MCUSYS_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 10) /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 11) /* 1b */
+#define MCUSYS_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define BYPASS_CPU_SPMC_MODE_LSB (1U << 13) /* 1b */
+#define MCUSYS_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define MCUSYS_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+#define MCUSYS_PWR_ON_2ND_ACK_LSB (1U << 30) /* 1b */
+#define MCUSYS_PWR_CON_MCUSYS_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPUTOP_SPMC_DORMANT_EN_LSB (1U << 10) /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB (1U << 11) /* 1b */
+#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+#define MP0_CPUTOP_PWR_ON_2ND_ACK_LSB (1U << 30) /* 1b */
+#define MP0_CPUTOP_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* MP0_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+#define MP0_CPU0_PWR_ON_2ND_ACK_LSB (1U << 30) /* 1b */
+#define MP0_CPU0_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+#define MP0_CPU1_PWR_ON_2ND_ACK_LSB (1U << 30) /* 1b */
+#define MP0_CPU1_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 4b */
+#define SC_ARM_CK_OFF_LSB (1U << 4) /* 4b */
+#define SC_ARMPLL_OFF_LSB (1U << 8) /* 1b */
+#define SC_ARMBPLL_OFF_LSB (1U << 9) /* 1b */
+#define SC_ARMBBPLL_OFF_LSB (1U << 10) /* 1b */
+#define SC_CCIPLL_CKOFF_LSB (1U << 11) /* 1b */
+#define SC_ARMDDS_OFF_LSB (1U << 12) /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB (1U << 13) /* 1b */
+#define SC_ARMBBPLL_S_OFF_LSB (1U << 14) /* 1b */
+#define SC_CCIPLL_PWROFF_LSB (1U << 15) /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB (1U << 17) /* 1b */
+#define SC_ARMBBPLLOUT_OFF_LSB (1U << 18) /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB (1U << 19) /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
+#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
+#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
+#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
+#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
+#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
+#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
+#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
+#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
+#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
+/* MCUSYS_WAKE_STA (0x10006000+0x234) */
+#define NIRQOUT_LSB (1U << 0) /* 8b */
+#define SPM_INTERRUPT_WAKEUP_LSB (1U << 8) /* 1b */
+#define NIRQOUT_SPM_AFTEN_LSB (1U << 9) /* 8b */
+#define SPM_INTERRUPT_WAKEUP_AFTEN_LSB (1U << 17) /* 1b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* AMRPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 4b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x268) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x26C) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_CON (0x10006000+0x274) */
+#define SYS_TIMER_START_LSB (1U << 0) /* 1b */
+#define SYS_TIMER_UPDATE_LSB (1U << 1) /* 1b */
+#define SYS_TIMER_START_DONE_LSB (1U << 2) /* 1b */
+#define SYS_TIMER_UPDATE_DONE_LSB (1U << 3) /* 1b */
+#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
+/* MP0_L2CFLUSH (0x10006000+0x278) */
+#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */
+#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */
+/* CPU_MCDI_WFI_EN (0x10006000+0x27C) */
+#define CPU_MCDI_WFI_EN_LSB (1U << 0) /* 8b */
+/* CPU_MCDI_WFI_EN_SET (0x10006000+0x280) */
+#define CPU_MCDI_WFI_EN_SET_LSB (1U << 0) /* 8b */
+/* CPU_MCDI_WFI_EN_CLR (0x10006000+0x284) */
+#define CPU_MCDI_WFI_EN_CLR_LSB (1U << 0) /* 8b */
+/* CPU_MCDI_WAKE_EN (0x10006000+0x288) */
+#define CPU_MCDI_WAKE_EN_LSB (1U << 0) /* 8b */
+#define CPU_MCDI_WAKE_EN_1OFN_LSB (1U << 8) /* 1b */
+/* IFR_PWR_CON (0x10006000+0x310) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* DPY_PWR_CON (0x10006000+0x314) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x318) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 4b */
+/* MD1_SRAM_ISOINT_B (0x10006000+0x320) */
+#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */
+/* SYSRAM_CON (0x10006000+0x354) */
+#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 8b */
+#define SYSRAM_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+/* SYSROM_CON (0x10006000+0x358) */
+#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
+#define SYSROM_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x36C) */
+#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* DUMMY_SRAM_CON (0x10006000+0x3AC) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x3B0) */
+#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define VNR_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */
+#define VHVNR_EXT_BUCK_ISO_LSB (1U << 3) /* 1b */
+/* GCPU_SRAM_CON (0x10006000+0x3CC) */
+#define GCPU_SRAM_CKISO_LSB (1U << 0) /* 8b */
+#define GCPU_SRAM_ISOINT_B_LSB (1U << 8) /* 11b */
+#define GCPU_SRAM_SLEEP_B_LSB (1U << 19) /* 11b */
+/* GCPU_EXTEND_SRAM_CON (0x10006000+0x3D0) */
+#define GCPU_SRAM_PDN_LSB (1U << 0) /* 17b */
+#define GCPU_SRAM_PDN_ACK_LSB (1U << 17) /* 1b */
+/* DCCM_E_SRAM_CON (0x10006000+0x3D4) */
+#define DCCM_E_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DCCM_E_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DCCM_E_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DCCM_E_SRAM_PDN_LSB (1U << 16) /* 4b */
+#define DCCM_E_SRAM_PDN_ACK_LSB (1U << 20) /* 1b */
+/* DCCM_O_SRAM_CON (0x10006000+0x3D8) */
+#define DCCM_O_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DCCM_O_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DCCM_O_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DCCM_O_SRAM_PDN_LSB (1U << 16) /* 4b */
+#define DCCM_O_SRAM_PDN_ACK_LSB (1U << 20) /* 1b */
+/* ICCM_S1_SRAM_CON (0x10006000+0x3DC) */
+#define ICCM_S1_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define ICCM_S1_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define ICCM_S1_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define ICCM_S1_SRAM_PDN_LSB (1U << 16) /* 8b */
+#define ICCM_S1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+/* ICCM_S2_SRAM_CON (0x10006000+0x3E0) */
+#define ICCM_S2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define ICCM_S2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define ICCM_S2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define ICCM_S2_SRAM_PDN_LSB (1U << 16) /* 8b */
+#define ICCM_S2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+/* HSM_SRAM_CON (0x10006000+0x3E4) */
+#define HSM_SRAM_CKISO_LSB (1U << 0) /* 2b */
+#define HSM_SRAM_ISOINT_B_LSB (1U << 2) /* 2b */
+#define HSM_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define HSM_SRAM_PDN_LSB (1U << 16) /* 1b */
+#define HSM_SRAM_PDN_ACK_LSB (1U << 17) /* 1b */
+/* ETHERNET_SRAM_CON (0x10006000+0x3E8) */
+#define ETHERNET_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define ETHERNET_SRAM_ISOINT_B_LSB (1U << 1) /* 8b */
+#define ETHERNET_SRAM_SLEEP_B_LSB (1U << 9) /* 8b */
+#define ETHERNET_SRAM_PDN_LSB (1U << 17) /* 8b */
+/* PCIE_SRAM_CON (0x10006000+0x3EC) */
+#define PCIE_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define PCIE_SRAM_ISOINT_B_LSB (1U << 1) /* 5b */
+#define PCIE_SRAM_SLEEP_B_LSB (1U << 6) /* 5b */
+#define PCIE_SRAM_PDN_LSB (1U << 16) /* 5b */
+#define PCIE_SRAM_PDN_ACK_LSB (1U << 21) /* 1b */
+/* MD_EXTRA_PWR_CON (0x10006000+0x3F0) */
+#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */
+/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x400) */
+#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x404) */
+#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_MAS_PAUSE3_MASK_B (0x10006000+0x408) */
+#define SPM_MAS_PAUSE3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x40C) */
+#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */
+/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x410) */
+#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x414) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x418) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x41C) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x420) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x424) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x428) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x42C) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x430) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* AP_MDSRC_REQ (0x10006000+0x434) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* ULPOSC_CON (0x10006000+0x440) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM_SWINT (0x10006000+0x448) */
+#define SPM_SWINT_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x44C) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x450) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_PLL_CON (0x10006000+0x458) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
+/* SPM_S1_MODE_CH (0x10006000+0x45C) */
+#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */
+#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */
+#define SPM_S1_MODE_CH_EMI_SELF_REFRESH_CH_LSB (1U << 16) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */
+#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */
+#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */
+#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x468) */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_SEL_LSB (1U << 8) /* 1b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_SEL_LSB (1U << 12) /* 1b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 16) /* 2b */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 18) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 22) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 24) /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB (1U << 26) /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB (1U << 28) /* 2b */
+#define SW_DMYRD_EN_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x46C) */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 8) /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 12) /* 4b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 16) /* 2b */
+#define SW_SHU_RESTORE_LSB (1U << 18) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 20) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 22) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 24) /* 2b */
+#define SW_DMYRD_MOD_LSB (1U << 26) /* 2b */
+#define SW_DMYRD_INTV_LSB (1U << 28) /* 2b */
+#define SW_DMYRD_EN_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_SEL3 (0x10006000+0x470) */
+#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 0) /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 2) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 4) /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB (1U << 6) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 8) /* 2b */
+#define SW_DR_RESERVED_0_SEL_LSB (1U << 10) /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB (1U << 12) /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB (1U << 14) /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB (1U << 16) /* 2b */
+#define SW_DR_RESERVED_4_SEL_LSB (1U << 18) /* 2b */
+#define SW_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 2b */
+#define SW_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 22) /* 2b */
+#define SW_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 24) /* 2b */
+#define SW_DRS_DIS_ACK_SEL_LSB (1U << 26) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON3 (0x10006000+0x474) */
+#define SW_DR_SRAM_LOAD_LSB (1U << 0) /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB (1U << 2) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 4) /* 2b */
+#define SW_DRS_DIS_REQ_LSB (1U << 6) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB (1U << 8) /* 2b */
+#define SW_DR_RESERVED_0_LSB (1U << 10) /* 2b */
+#define SW_DR_RESERVED_1_LSB (1U << 12) /* 2b */
+#define SW_DR_RESERVED_2_LSB (1U << 14) /* 2b */
+#define SW_DR_RESERVED_3_LSB (1U << 16) /* 2b */
+#define SW_DR_RESERVED_4_LSB (1U << 18) /* 2b */
+#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 2b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 22) /* 2b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 24) /* 2b */
+#define SC_DRS_DIS_ACK_LSB (1U << 26) /* 2b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x478) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
+#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 4) /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_CH0_PCM_LSB (1U << 5) /* 4b */
+#define SC_DR_SHU_LEVEL_SRAM_CH1_PCM_LSB (1U << 9) /* 4b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 13) /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB (1U << 14) /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB (1U << 15) /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB (1U << 16) /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB (1U << 17) /* 1b */
+#define SC_DR_RESERVED_4_PCM_LSB (1U << 18) /* 1b */
+#define SC_DR_RESERVED_5_PCM_LSB (1U << 19) /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 20) /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 21) /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 22) /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB (1U << 23) /* 1b */
+#define DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 24) /* 1b */
+#define DRAMC_SPCMD_APSRC_REQ_LSB (1U << 25) /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x47C) */
+#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x480) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x484) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x488) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x48C) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x490) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x494) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x498) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x49C) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM_AP_SEMA (0x10006000+0x4A0) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x4A4) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SSPM_CON (0x10006000+0x4A8) */
+#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
+#define SPM_SSPM_CON_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
+#define REG_MD32_26M_CK_SEL_LSB (1U << 8) /* 1b */
+#define REG_MD32_DCM_EN_LSB (1U << 9) /* 1b */
+/* SPM_SCP_CON (0x10006000+0x4AC) */
+#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_SCP_CON_SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+#define REG_SCP_26M_CK_SEL_LSB (1U << 5) /* 1b */
+#define REG_SCP_DCM_EN_LSB (1U << 6) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 7) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 8) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 9) /* 1b */
+/* SPM_ADSP_CON (0x10006000+0x4B0) */
+#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_ADSP_CON_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+#define ADSP_CLK_ON_LSB (1U << 5) /* 1b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x4B4) */
+#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x4B8) */
+#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x4BC) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x4C0) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4C4) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4C8) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4CC) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4D0) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4D4) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4D8) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4DC) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4E0) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4E4) */
+#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
+/* SW2SPM_INT (0x10006000+0x4E8) */
+#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x4EC) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x4F0) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SPM_DVFS_MISC (0x10006000+0x4F4) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
+#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_HISTORY_EN_LSB (1U << 5) /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
+#define MD2AP_CENTRAL_BUCK_GEAR_REQ_LSB (1U << 8) /* 1b */
+#define MD2AP_CENTRAL_BUCK_GEAR_RDY_LSB (1U << 9) /* 1b */
+#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
+#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
+#define SC_MM_CK_SEL_LSB (1U << 16) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 20) /* 1b */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 21) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 22) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 23) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 24) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 25) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 26) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 27) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 28) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 29) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 30) /* 1b */
+/* SCP_VCORE_LEVEL (0x10006000+0x4F8) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_SPM_CTRL (0x10006000+0x5B8) */
+#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
+#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x604) */
+#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x608) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x60C) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x610) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x614) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x618) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x61C) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x620) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x624) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x628) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_9 (0x10006000+0x62C) */
+#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_10 (0x10006000+0x630) */
+#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_11 (0x10006000+0x634) */
+#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_18 (0x10006000+0x638) */
+#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_19 (0x10006000+0x63C) */
+#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x640) */
+#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x644) */
+#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x648) */
+#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x64C) */
+#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x650) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x654) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x658) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_0 (0x10006000+0x65C) */
+#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x660) */
+#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_FORCE_DVFS (0x10006000+0x664) */
+#define SPM_FORCE_DVFS_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_DEEPIDLE_CG_CHECK_0_MASK (0x10006000+0x668) */
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_0_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_DEEPIDLE_CG_CHECK_1_MASK (0x10006000+0x66C) */
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_1_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_DEEPIDLE_CG_CHECK_2_MASK (0x10006000+0x670) */
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_2_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_DEEPIDLE_CG_CHECK_3_MASK (0x10006000+0x674) */
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_3_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_DEEPIDLE_CG_CHECK_4_MASK (0x10006000+0x678) */
+#define INFRA2SPM_DEEPIDLE_CG_CHECK_4_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI_CG_CHECK_0_MASK (0x10006000+0x67C) */
+#define INFRA2SPM_SODI_CG_CHECK_0_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI_CG_CHECK_1_MASK (0x10006000+0x680) */
+#define INFRA2SPM_SODI_CG_CHECK_1_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI_CG_CHECK_2_MASK (0x10006000+0x684) */
+#define INFRA2SPM_SODI_CG_CHECK_2_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI_CG_CHECK_3_MASK (0x10006000+0x688) */
+#define INFRA2SPM_SODI_CG_CHECK_3_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI_CG_CHECK_4_MASK (0x10006000+0x68C) */
+#define INFRA2SPM_SODI_CG_CHECK_4_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI3_CG_CHECK_0_MASK (0x10006000+0x690) */
+#define INFRA2SPM_SODI3_CG_CHECK_0_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI3_CG_CHECK_1_MASK (0x10006000+0x694) */
+#define INFRA2SPM_SODI3_CG_CHECK_1_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI3_CG_CHECK_2_MASK (0x10006000+0x698) */
+#define INFRA2SPM_SODI3_CG_CHECK_2_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI3_CG_CHECK_3_MASK (0x10006000+0x69C) */
+#define INFRA2SPM_SODI3_CG_CHECK_3_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_SODI3_CG_CHECK_4_MASK (0x10006000+0x6A0) */
+#define INFRA2SPM_SODI3_CG_CHECK_4_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_MCDSR_CG_CHECK_0_MASK (0x10006000+0x6A4) */
+#define INFRA2SPM_MCDSR_CG_CHECK_0_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_MCDSR_CG_CHECK_1_MASK (0x10006000+0x6A8) */
+#define INFRA2SPM_MCDSR_CG_CHECK_1_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_MCDSR_CG_CHECK_2_MASK (0x10006000+0x6AC) */
+#define INFRA2SPM_MCDSR_CG_CHECK_2_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_MCDSR_CG_CHECK_3_MASK (0x10006000+0x6B0) */
+#define INFRA2SPM_MCDSR_CG_CHECK_3_MASK_LSB (1U << 0) /* 32b */
+/* INFRA2SPM_MCDSR_CG_CHECK_4_MASK (0x10006000+0x6B4) */
+#define INFRA2SPM_MCDSR_CG_CHECK_4_MASK_LSB (1U << 0) /* 32b */
+/* OTHER2SPM_CG_CHECK_MASK (0x10006000+0x6B8) */
+#define APMIXEDSYS2SPM_SODI3_CG_CHECK_MASK_LSB (1U << 0) /* 5b */
+#define AUDIO2SPM_MCDSR_CG_CHECK_MASK_LSB (1U << 5) /* 1b */
+#define USB2SPM_MCDSR_CG_CHECK_MASK_LSB (1U << 6) /* 1b */
+#define AUDIO2SPM_SODI_CG_CHECK_MASK_LSB (1U << 7) /* 1b */
+#define USB2SPM_SODI_CG_CHECK_MASK_LSB (1U << 8) /* 1b */
+#define AUDIO2SPM_SODI3_CG_CHECK_MASK_LSB (1U << 9) /* 1b */
+#define USB2SPM_SODI3_CG_CHECK_MASK_LSB (1U << 10) /* 1b */
+#define AUDIO2SPM_DEEPIDLE_CG_CHECK_MASK_LSB (1U << 11) /* 1b */
+#define USB2SPM_DEEPIDLE_CG_CHECK_MASK_LSB (1U << 12) /* 1b */
+/* SPM_TIMER_0 (0x10006000+0x6BC) */
+#define SPM_TIMER_VAL_0_LSB (1U << 0) /* 14b */
+#define SPM_TIMER_0_LSB (1U << 14) /* 14b */
+#define SPM_TIMER_EN_0_LSB (1U << 28) /* 1b */
+#define SPM_TIMER_CLR_0_LSB (1U << 29) /* 1b */
+#define SPM_TIMEOUT_WAKEUP_EN_0_LSB (1U << 30) /* 1b */
+#define SPM_TIMEOUT_0_LSB (1U << 31) /* 1b */
+/* SPM_TIMER_1 (0x10006000+0x6C0) */
+#define SPM_TIMER_VAL_1_LSB (1U << 0) /* 14b */
+#define SPM_TIMER_1_LSB (1U << 14) /* 14b */
+#define SPM_TIMER_EN_1_LSB (1U << 28) /* 1b */
+#define SPM_TIMER_CLR_1_LSB (1U << 29) /* 1b */
+#define SPM_TIMEOUT_WAKEUP_EN_1_LSB (1U << 30) /* 1b */
+#define SPM_TIMEOUT_1_LSB (1U << 31) /* 1b */
+/* SPM_TIMER_2 (0x10006000+0x6C4) */
+#define SPM_TIMER_VAL_2_LSB (1U << 0) /* 14b */
+#define SPM_TIMER_2_LSB (1U << 14) /* 14b */
+#define SPM_TIMER_EN_2_LSB (1U << 28) /* 1b */
+#define SPM_TIMER_CLR_2_LSB (1U << 29) /* 1b */
+#define SPM_TIMEOUT_WAKEUP_EN_2_LSB (1U << 30) /* 1b */
+#define SPM_TIMEOUT_2_LSB (1U << 31) /* 1b */
+/* UFS_PSRI_SW (0x10006000+0x6D0) */
+#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6D4) */
+#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6D8) */
+#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_LEVEL (0x10006000+0x708) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_STA (0x10006000+0x70C) */
+#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x7BC) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
+#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
+/* DVFSRC_IRQ_LATCH_0 (0x10006000+0x84C) */
+#define DVFSRC_IRQ_LATCH_0_LSB (1U << 0) /* 32b */
+/* DVFSRC_IRQ_LATCH_1 (0x10006000+0x850) */
+#define DVFSRC_IRQ_LATCH_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x854) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x858) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x85C) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x860) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x864) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x868) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x86C) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_7 (0x10006000+0x870) */
+#define DRAMC_GATING_ERR_LATCH_CH0_7_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_8 (0x10006000+0x874) */
+#define DRAMC_GATING_ERR_LATCH_CH0_8_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_0 (0x10006000+0x878) */
+#define DRAMC_GATING_ERR_LATCH_CH1_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_1 (0x10006000+0x87C) */
+#define DRAMC_GATING_ERR_LATCH_CH1_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_2 (0x10006000+0x880) */
+#define DRAMC_GATING_ERR_LATCH_CH1_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_3 (0x10006000+0x884) */
+#define DRAMC_GATING_ERR_LATCH_CH1_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_4 (0x10006000+0x888) */
+#define DRAMC_GATING_ERR_LATCH_CH1_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_5 (0x10006000+0x88C) */
+#define DRAMC_GATING_ERR_LATCH_CH1_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_6 (0x10006000+0x890) */
+#define DRAMC_GATING_ERR_LATCH_CH1_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_7 (0x10006000+0x894) */
+#define DRAMC_GATING_ERR_LATCH_CH1_7_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH1_8 (0x10006000+0x898) */
+#define DRAMC_GATING_ERR_LATCH_CH1_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x89C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x8A0) */
+#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x8A4) */
+#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x918) */
+#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x91C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x930) */
+#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x934) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x938) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x93C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x948) */
+#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x950) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x954) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x958) */
+#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x95C) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_4 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_4_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_4_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_4_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_4_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_4_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_4_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_4_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_4_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_4_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_4_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_4_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_4 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_4_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_4_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_4 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_4_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_4_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_4_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_4_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_4 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_4_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_4_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_4 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_4_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_4 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_4_LSB (1U << 0) /* 32b */
+
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+/**************************************
+ * Macro and Inline
+ **************************************/
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_typedefs.h b/src/bsp/lk/platform/mt2731/include/platform/mt_typedefs.h
new file mode 100644
index 0000000..29c2b95
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_typedefs.h
@@ -0,0 +1,159 @@
+/* ------------
+ * Type definition.
+ */
+
+#ifndef _MTK_DVC_TEST_TYPEDEFS_H
+#define _MTK_DVC_TEST_TYPEDEFS_H
+
+
+/*==== CONSTANTS ==================================================*/
+
+#define IMPORT EXTERN
+#ifndef __cplusplus
+#define EXTERN extern
+#else
+#define EXTERN extern "C"
+#endif
+#define LOCAL static
+#define GLOBAL
+#define EXPORT GLOBAL
+
+
+#define EQ ==
+#define NEQ !=
+#define AND &&
+#define OR ||
+#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B)))
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifndef BOOL
+typedef unsigned char BOOL;
+#endif
+
+typedef volatile unsigned char *UINT8P;
+typedef volatile unsigned short *UINT16P;
+typedef volatile unsigned int *UINT32P;
+
+
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+typedef unsigned long long u64;
+
+typedef unsigned long long U64;
+typedef unsigned int U32;
+typedef unsigned short U16;
+typedef unsigned char U8;
+
+typedef signed char s8;
+typedef signed short s16;
+typedef signed int s32;
+typedef signed long long s64;
+
+typedef signed char S8;
+typedef signed short S16;
+typedef signed int S32;
+typedef signed long long S64;
+
+typedef unsigned int kal_uint32;
+typedef unsigned short kal_uint16;
+typedef unsigned char kal_uint8;
+
+typedef signed int kal_int32;
+typedef signed short kal_int16;
+typedef signed char kal_int8;
+
+typedef enum {
+ KAL_FALSE = 0,
+ KAL_TRUE = 1,
+} kal_bool;
+
+/*==== EXPORT =====================================================*/
+
+#define MAXIMUM(A,B) (((A)>(B))?(A):(B))
+#define MINIMUM(A,B) (((A)<(B))?(A):(B))
+
+#define READ_REGISTER_UINT32(reg) \
+ (*(volatile unsigned int * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+ (*(volatile unsigned int * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+ (*(volatile unsigned short * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+ (*(volatile unsigned short * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+ (*(volatile unsigned char * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+ (*(volatile unsigned char * const)(reg)) = (val)
+
+#define INREG8(x) READ_REGISTER_UINT8((unsigned char *)(x))
+#define OUTREG8(x, y) WRITE_REGISTER_UINT8((unsigned char *)(x), (unsigned char)(y))
+#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x) READ_REGISTER_UINT16((unsigned short *)(x))
+#define OUTREG16(x, y) WRITE_REGISTER_UINT16((unsigned short *)(x),(unsigned short)(y))
+#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x) READ_REGISTER_UINT32((unsigned int *)(x))
+#define OUTREG32(x, y) WRITE_REGISTER_UINT32((unsigned int *)(x), (unsigned int )(y))
+#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+
+#define DRV_Reg8(addr) INREG8(addr)
+#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data) SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
+
+#define DRV_Reg16(addr) INREG16(addr)
+#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data) SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
+
+#define DRV_Reg32(addr) INREG32(addr)
+#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data) SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
+
+// !!! DEPRECATED, WILL BE REMOVED LATER !!!
+#define DRV_Reg(addr) DRV_Reg16(addr)
+#define DRV_WriteReg(addr, data) DRV_WriteReg16(addr, data)
+#define DRV_SetReg(addr, data) DRV_SetReg16(addr, data)
+#define DRV_ClrReg(addr, data) DRV_ClrReg16(addr, data)
+
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_uart.h b/src/bsp/lk/platform/mt2731/include/platform/mt_uart.h
new file mode 100644
index 0000000..fa9dd26
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_uart.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#pragma once
+
+bool check_uart_enter(void);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mt_usbphy.h b/src/bsp/lk/platform/mt2731/include/platform/mt_usbphy.h
new file mode 100644
index 0000000..d685b37
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mt_usbphy.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <platform/mt_typedefs.h>
+
+void mt_usb_phy_poweron(void);
+void mt_usb_phy_poweroff(void);
+
+void charger_detect_init(void);
+void charger_detect_release(void);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_bio_ioctl.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_bio_ioctl.h
new file mode 100644
index 0000000..8b03edf
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_bio_ioctl.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef __MTK_BIO_IOCTL_H__
+#define __MTK_BIO_IOCTL_H__
+
+#include <lib/bio.h>
+
+enum bio_ioctl_custom_num {
+ BIO_IOCTL_QUERY_CAP_REWRITABLE = BIO_IOCTL_CUSTOM_START + 1, /* query the capability of directly write without erase */
+};
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_drm.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_drm.h
new file mode 100644
index 0000000..731fc4b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_drm.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef __MTK_DRM_H__
+#define __MTK_DRM_H__
+
+#include <platform/mt_reg_base.h>
+
+#if ARCH_ARM64
+#define MTK_DRM_BASE (KERNEL_ASPACE_BASE+0x0D01B000ULL)
+#else
+#define MTK_DRM_BASE (0x0D01B000)
+#endif
+
+#define MTK_DRM_MODE (MTK_DRM_BASE+0x0000)
+#define MTK_DRM_NONRST_REG (MTK_DRM_BASE+0x0020)
+#define MTK_DRM_NONRST_REG2 (MTK_DRM_BASE+0x0024)
+#define MTK_DRM_DEBUG_CTL (MTK_DRM_BASE+0x0040)
+#define MTK_DRM_LATCH_CTL (MTK_DRM_BASE+0x0044)
+#define MTK_DRM_LATCH_CTL2 (MTK_DRM_BASE+0x0048)
+#define MTK_DRM_LATCH_CTL3 (MTK_DRM_BASE+0x004C)
+#define MTK_DRM_MFG_REG (MTK_DRM_BASE+0x0068)
+#define MTK_DRM_LATCH_CTL4 (MTK_DRM_BASE+0x006C)
+#define MTK_DRM_DEBUG_CTL2 (MTK_DRM_BASE+0x00A0)
+#define MTK_DRM_DEBUG_0_REG (MTK_DRM_BASE+0x0500)
+#define MTK_DRM_DEBUG_2_REG (MTK_DRM_BASE+0x0508)
+
+/* MTK_DRM_MODE */
+#define MTK_DRM_MODE_KEY (0x22000000)
+#define MTK_DRM_MODE_DDR_RESERVE (0x00000080)
+
+/* MTK_DRM_DEBUG_CTL */
+#define MTK_DRM_DEBUG_CTL_KEY (0x59000000)
+#define MTK_DRM_DRAMC_SREF (0x00001000)
+#define MTK_DRM_DRAMC_ISO (0x00002000)
+#define MTK_DRM_DRAMC_CONF_ISO (0x00004000)
+#define MTK_DRM_EMI_DCS_PAUSE (0x00040000)
+#define MTK_DRM_DVFSRC_PAUSE (0x00080000)
+#define MTK_DRM_DDR_RESERVE_STA (0x00100000)
+#define MTK_DRM_DDR_SREF_STA (0x00200000)
+#define MTK_DRM_DVFSRC_SUCCESS (0x01000000)
+
+/* MTK_DRM_DEBUG_CTL2 */
+#define MTK_DRM_DEBUG_CTL2_KEY (0x55000000)
+#define MTK_DRM_DVFSRC_EN (0x00000200)
+#define MTK_DRM_EMI_DCS_EN (0x00000100)
+
+/* MTK_DRM_LATCH_CTL */
+#define MTK_DRM_LATCH_CTL_KEY (0x95000000)
+#define MTK_DRM_LATCH_EN (0x00000001)
+#define MTK_DRM_MCU_LATCH_SELECT (0x00000002)
+#define MTK_DRM_SPM_LATCH_SELECT (0x00000004)
+#define MTK_DRM_MCU_LATCH_EN (0x00000010)
+#define MTK_DRM_SPM_LATCH_EN (0x00000020)
+#define MTK_DRM_DRAMC_LATCH_EN (0x00000040)
+#define MTK_DRM_MP0_EXT_OFF_EN (0x00000100)
+#define MTK_DRM_GPU_EXT_OFF_EN (0x00000200)
+#define MTK_DRM_MD_EXT_OFF_EN (0x00000400)
+#define MTK_DRM_DRAMC_RD_TEST_EN (0x00000800)
+#define MTK_DRM_DRAMC_RDWT_TEST_EN (0x00001000)
+#define MTK_DRM_DVFSRC_LATCH_EN (0x00002000)
+#define MTK_DRM_EMI_LATCH_EN (0x00004000)
+#define MTK_DRM_DEBUGSYS_LATCH_EN (0x00020000)
+
+/* MTK_DRM_LATCH_CTL2 */
+#define MTK_DRM_LATCH_CTL2_KEY (0x95000000)
+#define MTK_DRM_MCU_DFD_EN (0x00020000)
+#define MTK_DRM_MCU_DFD_TIMEOUT_MASK (0x0001FFFF)
+#define MTK_DRM_MCU_DFD_TIMEOUT_OFS (0)
+#define MTK_DRM_MCU_DFD_TIMEOUT_VALUE (0x30)
+
+enum {
+ DRM_REG_CLR = 0,
+ DRM_REG_SET = 1
+};
+
+extern void check_ddr_reserve_status(void);
+extern void mtk_drm_init(void);
+int drm_dram_reserved(int enable);
+int drm_is_dram_slf(void);
+int drm_is_dvfsrc_enable(void);
+int drm_is_dvfsrc_success(void);
+int drm_is_reserve_ddr_enabled(void);
+int drm_is_reserve_ddr_mode_success(void);
+int drm_release_rg_dram_setting(void);
+int drm_release_rg_dramc_conf_iso(void);
+int drm_release_rg_dramc_iso(void);
+int drm_release_rg_dramc_sref(void);
+
+#endif /*__MTK_DRM_H__*/
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_gce.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_gce.h
new file mode 100644
index 0000000..54a3d54
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_gce.h
@@ -0,0 +1,84 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef __MTK_GCE_H__
+#define __MTK_GCE_H__
+
+#include <platform/mt_reg_base.h>
+
+#define CMDQ_THREAD_PRIO_LOWEST 0
+#define CMDQ_THREAD_PRIO_HIGHEST 1
+
+#if ARCH_ARM64
+#define GCE_CMDQ_BASE (KERNEL_ASPACE_BASE + 0x10238000ULL)
+#else
+#define GCE_CMDQ_BASE 0x10238000
+#endif
+
+#define BIT(x) (1u << (x))
+
+#define CMDQ_THREAD_BASE 0x100
+#define CMDQ_THREAD_SIZE 0x80
+#define CMDQ_THR_WARM_RESET 0x00
+#define CMDQ_THREAD_ENABLE_TASK 0x04
+#define CMDQ_THREAD_SUSPEND_TASK 0x08
+#define CMDQ_CURR_IRQ_STA 0x10
+#define CMDQ_THREAD_EXEC_CNT_PA 0x28
+#define CMDQ_THRAD_INS_CYCLES 0x50
+#define CMDQ_THREAD_PRIORITY 0x7
+#define CMDQ_THREAD_IRQ_DONE 0x1
+#define CMDQ_THREAD_IRQ_ERROR 0x12
+#define CMDQ_THREAD_IRQ_EN (CMDQ_THREAD_IRQ_ERROR | CMDQ_THREAD_IRQ_DONE)
+#define CMDQ_THREAD_CURR_ADDR 0x20
+#define CMDQ_THREAD_END_ADDR 0x24
+#define CMDQ_THREAD_CNT 0x28
+#define CMDQ_THREAD_CFG 0x40
+#define CMDQ_THREAD_IRQ_ENABLE 0x14
+
+#define CMDQ_THREAD_ENABLED 0x1
+#define CMDQ_THREAD_IRQ_DONE 0x1
+#define CMDQ_THREAD_IRQ_ERROR 0x12
+#define CMDQ_THREAD_SUSPEND 0x1
+#define CMDQ_THREAD_RESUME 0x0
+#define CMDQ_THREAD_DO_WARM_RESET BIT(0)
+#define CMDQ_THREAD_WARM_RESET 0x00
+#define CMDQ_THREAD_ACTIVE_SLOT_CYCLES 0x3200
+#define CMDQ_THREAD_DISABLED 0x0
+#define CMDQ_INS_CYCLE_TIMEOUT 0x0
+#define CMDQ_THR_DO_WARM_RESET BIT(0)
+
+int mtk_gce_start(void);
+
+#endif /*__MTK_GCE_H__*/
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_i2c.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_i2c.h
new file mode 100644
index 0000000..c89fe9b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_i2c.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __MTK_I2C_H__
+#define __MTK_I2C_H__
+#include <platform/mt_typedefs.h>
+#include <platform/mt_reg_base.h>
+#include <reg.h>
+#include <debug.h>
+/***sync_write is sync writel£¬wrapper is ordinary***/
+#include <sys/types.h>
+
+#define I2C_NR 5 /* Number of I2C controllers */
+
+#define I2CTAG "[I2C-LK] "
+#define I2CLOG(fmt, arg...) dprintf(INFO,I2CTAG fmt, ##arg)
+#define I2CMSG(fmt, arg...) dprintf(SPEW,I2CTAG fmt, ##arg)
+#define I2CERR(fmt, arg...) dprintf(ALWAYS,I2CTAG "%d: "fmt, __LINE__, ##arg)
+#define I2CFUC() dprintf(ALWAYS,I2CTAG "%s\n", __FUNCTION__)
+
+#ifdef MACH_FPGA
+#define CONFIG_MTK_I2C_FPGA_ENABLE
+#endif
+
+
+#ifdef CONFIG_MTK_I2C_FPGA_ENABLE
+#define FPGA_CLOCK 273000 /* FPGA crystal frequency (KHz) */
+#define I2C_CLK_DIV (4) /* frequency divisor */
+#define I2C_CLK_RATE (FPGA_CLOCK / I2C_CLK_DIV) /* I2C base clock (KHz) */
+#else
+#define I2C_CLK_RATE 124800 / I2C_CLK_DIV/* TODO: Calculate from bus clock */
+#define I2C_CLK_DIV (5) /* frequency divisor */
+#define SCP_I2C_CLK (26000 / 2) /* TODO: Check the correct frequency */
+#endif
+
+#define I2C_MB()
+#define I2C_BUG_ON(a)
+#define I2C_M_RD 0x0001
+
+/***********i2c register************/
+/*
+#define I2C0_BASE (0x11007000)
+#define I2C1_BASE (0x11008000)
+//for i2c multi channel
+//I2C2 HAS CH0 CH1 CH2
+#define I2C2_BASE (0x11009000)
+#define I2C3_BASE (0x1100F000)
+#define I2C4_BASE (0x11011000)
+*/
+/***********i2c DMA reg************/
+//DMA has multi CH for different i2c CH
+/*
+#define I2C0_APDMA_BASE (0x11000080)
+#define I2C1_APDMA_BASE (0x11000100)
+#define I2C2_APDMA_BASE (0x11000180)
+#define I2C3_APDMA_BASE (0x11000280)
+#define I2C4_APDMA_BASE (0x11000300)
+*/
+#define I2C_OK 0x0000
+#define EAGAIN_I2C 11 /* Try again */
+#define EINVAL_I2C 22 /* Invalid argument */
+#define EOPNOTSUPP_I2C 95 /* Operation not supported on transport endpoint */
+#define ETIMEDOUT_I2C 110 /* Connection timed out */
+#define EREMOTEIO_I2C 121 /* Remote I/O error */
+#define ENOTSUPP_I2C 524 /* Remote I/O error */
+#define I2C_WRITE_FAIL_HS_NACKERR 0xA013
+#define I2C_WRITE_FAIL_ACKERR 0xA014
+#define I2C_WRITE_FAIL_TIMEOUT 0xA015
+#define DUTY_CYCLE 45
+
+
+/******************************************register operation***********************************/
+enum I2C_REGS_OFFSET {
+ OFFSET_DATA_PORT = 0x0,
+ OFFSET_SLAVE_ADDR = 0x04,
+ OFFSET_INTR_MASK = 0x08,
+ OFFSET_INTR_STAT = 0x0C,
+ OFFSET_CONTROL = 0x10,
+ OFFSET_TRANSFER_LEN = 0x14,
+ OFFSET_TRANSAC_LEN = 0x18,
+ OFFSET_DELAY_LEN = 0x1C,
+ OFFSET_HTIMING = 0x20,
+ OFFSET_START = 0x24,
+ OFFSET_EXT_CONF = 0x28,
+ OFFSET_LTIMING = 0x2C,
+ OFFSET_HS = 0x30,
+ OFFSET_IO_CONFIG = 0x34,
+ OFFSET_FIFO_ADDR_CLR = 0x38,
+ OFFSET_TRANSFER_LEN_AUX = 0x44,
+ OFFSET_CLOCK_DIV = 0x48,
+ OFFSET_SOFTRESET = 0x50,
+ OFFSET_DEBUGSTAT = 0xe4,
+ OFFSET_DEBUGCTRL = 0xe8,
+ OFFSET_FIFO_STAT = 0xf4,
+ OFFSET_FIFO_THRESH = 0xf8,
+ OFFSET_DCM_EN = 0xf88,
+ OFFSET_MULTI_DMA = 0xf8c,
+};
+
+enum DMA_REGS_OFFSET {
+ OFFSET_INT_FLAG = 0x0,
+ OFFSET_INT_EN = 0x04,
+ OFFSET_EN = 0x08,
+ OFFSET_RST = 0x0C,
+ OFFSET_CON = 0x18,
+ OFFSET_TX_MEM_ADDR = 0x1C,
+ OFFSET_RX_MEM_ADDR = 0x20,
+ OFFSET_TX_LEN = 0x24,
+ OFFSET_RX_LEN = 0x28,
+};
+
+typedef enum {
+ ST_MODE,
+ FS_MODE,
+ HS_MODE,
+} I2C_SPEED_MODE;
+
+enum mt_trans_op {
+ I2C_MASTER_NONE = 0,
+ I2C_MASTER_WR = 1,
+ I2C_MASTER_RD,
+ I2C_MASTER_WRRD,
+};
+
+#define I2C_HS_NACKERR (1 << 2)
+#define I2C_ACKERR (1 << 1)
+#define I2C_TRANSAC_COMP (1 << 0)
+
+#define I2C_FIFO_SIZE 8
+
+#define MAX_ST_MODE_SPEED 100 /* khz */
+#define MAX_FS_MODE_SPEED 400 /* khz */
+#define MAX_HS_MODE_SPEED 3400 /* khz */
+
+#define MAX_DMA_TRANS_SIZE 65532 /* Max(65535) aligned to 4 bytes = 65532 */
+#define MAX_DMA_TRANS_NUM 256
+
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV 8
+
+#define DMA_ADDRESS_HIGH (0xC0000000)
+
+
+
+enum i2c_trans_st_rs {
+ I2C_TRANS_STOP = 0,
+ I2C_TRANS_REPEATED_START,
+};
+
+
+
+//CONTROL
+#define I2C_CONTROL_RS (0x1 << 1)
+#define I2C_CONTROL_DMA_EN (0x1 << 2)
+#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
+#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
+#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
+#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
+#define I2C_CONTROL_WRAPPER (0x1 << 0)
+/***********************************end of register operation****************************************/
+/***********************************I2C Param********************************************************/
+struct mt_trans_data {
+ U16 trans_num;
+ U16 data_size;
+ U16 trans_len;
+ U16 trans_auxlen;
+};
+
+typedef struct mt_i2c_t {
+ //==========set in i2c probe============//
+ addr_t base; /* i2c base addr */
+ U16 id;
+ U16 irqnr; /* i2c interrupt number */
+ U16 irq_stat; /* i2c interrupt status */
+ U32 clk; /* host clock speed in khz */
+ U32 pdn; /*clock number*/
+ //==========common data define============//
+ enum i2c_trans_st_rs st_rs;
+ enum mt_trans_op op;
+ addr_t pdmabase;
+ U32 speed; //The speed (khz)
+ U16 delay_len; //number of half pulse between transfers in a trasaction
+ U32 msg_len; //number of half pulse between transfers in a trasaction
+ U8 *msg_buf; /* pointer to msg data */
+ U8 addr; //The address of the slave device, 7bit,the value include read/write bit.
+ U8 master_code;/* master code in HS mode */
+ U8 mode; /* ST/FS/HS mode */
+ //==========reserved funtion============//
+ U8 is_push_pull_enable; //IO push-pull or open-drain
+ U8 is_clk_ext_disable; //clk entend default enable
+ U8 is_dma_enabled; //Transaction via DMA instead of 8-byte FIFO
+ U8 read_flag;//read,write,read_write
+ BOOL dma_en;
+ BOOL poll_en;
+ BOOL pushpull;//open drain
+ BOOL filter_msg;//filter msg error log
+ BOOL i2c_3dcamera_flag;//flag for 3dcamera
+
+ //==========define reg============//
+ U16 htiming_reg;
+ U16 ltiming_reg;
+ U16 high_speed_reg;
+ U16 control_reg;
+ struct mt_trans_data trans_data;
+} mt_i2c;
+
+//===========================i2c old driver===================================================//
+enum {
+ I2C0 = 0,
+ I2C1 = 1,
+ I2C2 = 2,
+ I2C3 = 3,
+ I2C4 = 4,
+};
+
+//==============================================================================
+// I2C Exported Function
+//==============================================================================
+extern S32 i2c_read(mt_i2c *i2c,U8 *buffer, U32 len);
+extern S32 i2c_write(mt_i2c *i2c,U8 *buffer, U32 len);
+extern S32 i2c_write_read(mt_i2c *i2c,U8 *buffer, U32 write_len, U32 read_len);
+extern S32 i2c_set_speed(mt_i2c *i2c);
+extern int i2c_hw_init(void);
+
+//#define I2C_EARLY_PORTING
+#ifdef I2C_EARLY_PORTING
+int mt_i2c_test(void);
+#endif
+#endif /* __MT_I2C_H__ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_key.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_key.h
new file mode 100644
index 0000000..b2acf0d
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_key.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#pragma once
+
+bool check_download_key(void);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_mrdump.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_mrdump.h
new file mode 100644
index 0000000..71b15fa
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_mrdump.h
@@ -0,0 +1,48 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _LK_MTK_MRDUMP_H_
+#define _LK_MTK_MRDUMP_H_
+
+#include <platform/mt2731.h>
+
+#define MRDUMP_OUTPUT_PARTITION "log"
+
+/* USB DUMP */
+//#define MRDUMP_DEFAULT_USB_DUMP
+//#define MRDUMP_ZIP_NO_COMPRESSION
+
+#endif /* _LK_MTK_MRDUMP_H_ */
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_serial_key.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_serial_key.h
new file mode 100644
index 0000000..6a8916a
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_serial_key.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+/* serial key */
+#if WITH_KERNEL_VM
+#define SERIAL_KEY_HI (18446744005287936324UL)
+#define SERIAL_KEY_LO (18446744005287936320UL)
+#define SERIAL_KEY_2_HI (18446744005287936332UL)
+#define SERIAL_KEY_2_LO (18446744005287936328UL)
+#else
+#define SERIAL_KEY_HI (297861444U)
+#define SERIAL_KEY_LO (297861440U)
+#define SERIAL_KEY_2_HI (297861452U)
+#define SERIAL_KEY_2_LO (297861448U)
+#endif
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_trng.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_trng.h
new file mode 100644
index 0000000..0281c79
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_trng.h
@@ -0,0 +1,41 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2018. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef __MTK_TRNG_H__
+#define __MTK_TRNG_H__
+s32 trng_drv_get_random_data(u8 *buf, u32 len);
+
+#endif /* !defined __MTK_TRNG_H__ */
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/mtk_wdt.h b/src/bsp/lk/platform/mt2731/include/platform/mtk_wdt.h
new file mode 100644
index 0000000..25be780
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/mtk_wdt.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/mt_reg_base.h>
+#include <stdbool.h>
+
+#define ENABLE_WDT_MODULE (1) /* Module switch */
+#define LK_WDT_DISABLE (0)
+
+#define MTK_WDT_BASE TOP_RGU_BASE
+
+#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000)
+#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004)
+#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008)
+#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C)
+#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010)
+#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014)
+#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018)
+#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020)
+#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024)
+#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030)
+#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034)
+#define MTK_WDT_DRAMC_CTL (MTK_WDT_BASE+0x0040)
+#define MTK_WDT_DEBUG_CTL3 (MTK_WDT_BASE+0x00a8)
+#define MTK_WDT_DEBUG_2_REG (MTK_WDT_BASE+0x0508)
+
+/*WDT_MODE*/
+#define MTK_WDT_MODE_KEYMASK (0xff00)
+#define MTK_WDT_MODE_KEY (0x22000000)
+#define MTK_WDT_MODE_DDR_RESERVE (0x0080)
+
+#define MTK_WDT_MODE_DUAL_MODE (0x0040)
+#define MTK_WDT_MODE_IN_DIS (0x0020) /* Reserved */
+#define MTK_WDT_MODE_AUTO_RESTART (0x0010) /* Reserved */
+#define MTK_WDT_MODE_IRQ (0x0008)
+#define MTK_WDT_MODE_EXTEN (0x0004)
+#define MTK_WDT_MODE_EXT_POL (0x0002)
+#define MTK_WDT_MODE_ENABLE (0x0001)
+
+/*WDT_LENGTH*/
+#define MTK_WDT_LENGTH_TIME_OUT (0xffe0)
+#define MTK_WDT_LENGTH_KEYMASK (0x001f)
+#define MTK_WDT_LENGTH_KEY (0x0008)
+
+/*WDT_RESTART*/
+#define MTK_WDT_RESTART_KEY (0x1971)
+
+/*WDT_STATUS*/
+#define MTK_WDT_STATUS_HWWDT_RST_WITH_IRQ (0xA0000000)
+#define MTK_WDT_STATUS_HWWDT_RST (0x80000000)
+#define MTK_WDT_STATUS_SWWDT_RST (0x40000000)
+#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000)
+#define MTK_WDT_STATUS_SECURITY_RST (1<<28)
+#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000)
+#define MTK_WDT_STATUS_SPMWDT_RST (0x0001)
+#define MTK_WDT_STATUS_THERMAL_CTL_RST (1<<18)
+
+/* Reboot reason */
+#define RE_BOOT_REASON_UNKNOW (0x00)
+#define RE_BOOT_BY_WDT_HW (0x01)
+#define RE_BOOT_BY_WDT_SW (0x02)
+#define RE_BOOT_WITH_INTTERUPT (0x04)
+#define RE_BOOT_BY_SPM_THERMAL (0x08)
+#define RE_BOOT_BY_SPM (0x10)
+#define RE_BOOT_BY_THERMAL_DIRECT (0x20)
+#define RE_BOOT_BY_DEBUG (0x40)
+#define RE_BOOT_BY_SECURITY (0x80)
+#define RE_BOOT_BY_PMIC_FULL_RST (0x800) /* PMIC full (cold) reset */
+#define RE_BOOT_ABNORMAL (0xF0)
+
+#define WDT_NORMAL_REBOOT (0x100)
+#define WDT_BY_PASS_PWK_REBOOT (0x200)
+#define WDT_NOT_WDT_REBOOT (0x400)
+
+//MTK_WDT_DEBUG_CTL
+#define MTK_DEBUG_CTL_KEY (0x59000000)
+#define MTK_RG_DDR_PROTECT_EN (0x00001)
+#define MTK_RG_MCU_LATH_EN (0x00002)
+#define MTK_RG_DRAMC_SREF (0x00100)
+#define MTK_RG_DRAMC_ISO (0x00200)
+#define MTK_RG_CONF_ISO (0x00400)
+#define MTK_DDR_RESERVE_RTA (0x10000) //sta
+#define MTK_DDR_SREF_STA (0x20000) //sta
+
+
+/*WDT_INTERVAL*/
+#define MTK_WDT_INTERVAL_MASK (0x0fff)
+
+/*WDT_SWRST*/
+#define MTK_WDT_SWRST_KEY (0x1209)
+
+/*WDT_SWSYSRST*/
+#define MTK_WDT_SWSYS_RST_PWRAP_SPI_CTL_RST (0x0800)
+#define MTK_WDT_SWSYS_RST_APMIXED_RST (0x0400)
+#define MTK_WDT_SWSYS_RST_MD_LITE_RST (0x0200)
+#define MTK_WDT_SWSYS_RST_INFRA_AO_RST (0x0100)
+#define MTK_WDT_SWSYS_RST_MD_RST (0x0080)
+#define MTK_WDT_SWSYS_RST_DDRPHY_RST (0x0040)
+#define MTK_WDT_SWSYS_RST_IMG_RST (0x0020)
+#define MTK_WDT_SWSYS_RST_VDEC_RST (0x0010)
+#define MTK_WDT_SWSYS_RST_VENC_RST (0x0008)
+#define MTK_WDT_SWSYS_RST_MFG_RST (0x0004)
+#define MTK_WDT_SWSYS_RST_DISP_RST (0x0002)
+#define MTK_WDT_SWSYS_RST_INFRA_RST (0x0001)
+
+#define MTK_WDT_SWSYS_RST_KEY (0x88000000)
+
+#define MTK_WDT_DEBUG_CTL3_KEY (0x51000000)
+#define MTK_WDT_DEBUG_CTL3_DIS_DDR_RSV (1 << 15)
+
+typedef enum wd_swsys_reset_type {
+ WD_MD_RST,
+} WD_SYS_RST_TYPE;
+
+int mtk_wdt_is_pmic_full_reset(void);
+void set_clr_fastboot_mode(bool flag);
+void set_clr_recovery_mode(bool flag);
+bool check_fastboot_mode(void);
+bool check_recovery_mode(void);
+unsigned int mtk_wdt_check_status(void);
+void mtk_wdt_init(void);
+void mtk_wdt_disable(void);
+void mtk_wdt_restart(void);
+unsigned int mtk_wdt_check_status(void);
+int rgu_dram_reserved(int enable);
+int rgu_is_reserve_ddr_enabled(void);
+
+int rgu_is_dram_slf(void);
+
+void rgu_release_rg_dramc_conf_iso(void);
+
+void rgu_release_rg_dramc_iso(void);
+
+void rgu_release_rg_dramc_sref(void);
+int rgu_is_reserve_ddr_mode_success(void);
+void mtk_arch_reset(char mode);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_ecc_hal.h b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_ecc_hal.h
new file mode 100644
index 0000000..a891078
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_ecc_hal.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <kernel/event.h>
+#include <kernel/mutex.h>
+#include <sys/types.h>
+
+#define ECC_IDLE_MASK NAND_BIT(0)
+#define ECC_IRQ_EN NAND_BIT(0)
+#define ECC_OP_ENABLE (1)
+#define ECC_OP_DISABLE (0)
+
+#define ECC_ENCCON (0x00)
+#define ECC_ENCCNFG (0x04)
+#define ECC_CNFG_4BIT (0)
+#define ECC_CNFG_6BIT (1)
+#define ECC_CNFG_8BIT (2)
+#define ECC_CNFG_10BIT (3)
+#define ECC_CNFG_12BIT (4)
+#define ECC_CNFG_14BIT (5)
+#define ECC_CNFG_16BIT (6)
+#define ECC_CNFG_18BIT (7)
+#define ECC_CNFG_20BIT (8)
+#define ECC_CNFG_22BIT (9)
+#define ECC_CNFG_24BIT (0xa)
+#define ECC_CNFG_28BIT (0xb)
+#define ECC_CNFG_32BIT (0xc)
+#define ECC_CNFG_36BIT (0xd)
+#define ECC_CNFG_40BIT (0xe)
+#define ECC_CNFG_44BIT (0xf)
+#define ECC_CNFG_48BIT (0x10)
+#define ECC_CNFG_52BIT (0x11)
+#define ECC_CNFG_56BIT (0x12)
+#define ECC_CNFG_60BIT (0x13)
+#define ECC_CNFG_68BIT (0x14)
+#define ECC_CNFG_72BIT (0x15)
+#define ECC_CNFG_80BIT (0x16)
+#define ECC_MODE_SHIFT (5)
+#define ECC_MS_SHIFT (16)
+#define ECC_ENCDIADDR (0x08)
+#define ECC_ENCIDLE (0x0c)
+#define ECC_ENCSTA (0x7c)
+#define ENC_IDLE NAND_BIT(0)
+#define ECC_ENCIRQ_EN (0x80)
+#define ECC_ENCIRQ_STA (0x84)
+#define PG_IRQ_SEL NAND_BIT(1)
+#define ECC_PIO_DIRDY (0x90)
+#define PIO_DI_RDY (0x01)
+#define ECC_PIO_DI (0x94)
+#define ECC_DECCON (0x100)
+#define ECC_DECCNFG (0x104)
+#define DEC_EMPTY_EN NAND_BIT(31)
+#define DEC_CON_SHIFT (12)
+#define ECC_DECDIADDR (0x108)
+#define ECC_DECIDLE (0x10c)
+#define ECC_DECFER (0x110)
+#define ECC_DECENUM(x) (0x114 + (x) * sizeof(u32))
+#define ERR_MASK (0x1f)
+#define ECC_DECDONE (0x124)
+#define ECC_DECIRQ_EN (0x200)
+#define ECC_DECIRQ_STA (0x204)
+#define ECC_DECFSM (0x208)
+#define FSM_MASK (0x3f3fff0f)
+#define FSM_IDLE (0x01011101)
+
+#define ECC_ENCPAR(x) (0x300 + (x) * sizeof(u32))
+#define ECC_DECEL(x) (0x500 + (x) * sizeof(u32))
+#define DECEL_MASK (0x3fff)
+#define ECC_TIMEOUT (500000)
+
+#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
+#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
+#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
+#define ECC_PARITY_BITS (14)
+#define MAX_ECC_STRENGTH (80)
+
+#define writew(v, a) (*REG16(a) = (v))
+#define readw(a) (*REG16(a))
+
+struct mtk_ecc {
+ mutex_t lock;
+ event_t irq_event;
+ uintptr_t regs;
+ u32 sectors;
+};
+
+enum mtk_ecc_mode {
+ ECC_DMA_MODE = 0,
+ ECC_NFI_MODE = 1,
+ ECC_PIO_MODE = 2
+};
+
+enum mtk_ecc_operation {
+ ECC_ENCODE,
+ ECC_DECODE
+};
+
+enum mtk_ecc_deccon {
+ ECC_DEC_FER = 1,
+ ECC_DEC_LOCATE = 2,
+ ECC_DEC_CORRECT = 3
+};
+
+struct mtk_ecc_stats {
+ u32 corrected;
+ u32 bitflips;
+ u32 failed;
+};
+
+struct mtk_ecc_config {
+ enum mtk_ecc_operation op;
+ enum mtk_ecc_mode mode;
+ enum mtk_ecc_deccon deccon;
+ u32 addr;
+ u32 strength;
+ u32 sectors;
+ u32 len;
+};
+
+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
+ u8 *data, u32 bytes, int polling);
+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config, int polling);
+void mtk_ecc_disable(struct mtk_ecc *ecc);
+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, u32 sectors);
+int mtk_ecc_cpu_correct(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, u8 *data, u32 sector, int polling);
+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op, int polling);
+int mtk_ecc_hw_init(struct mtk_ecc **ext_ecc);
+int mtk_ecc_wait_decode_fsm_idle(struct mtk_ecc *ecc);
+int mtk_ecc_decode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, u8 *data, u32 len, int polling);
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_bbt.h b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_bbt.h
new file mode 100644
index 0000000..873259c
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_bbt.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/nand/mtk_nand_nal.h>
+
+int mtk_nand_isbad_bbt(struct mtk_nand_chip *chip, u32 page);
+int mtk_nand_scan_bbt(struct mtk_nand_chip *chip);
+int mtk_nand_markbad_bbt(struct mtk_nand_chip *chip, u32 page);
+int mtk_nand_unmarkbad_bbt(struct mtk_nand_chip *chip, u32 page);
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_common.h b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_common.h
new file mode 100644
index 0000000..3f9d51b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_common.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform.h>
+
+#define NAND_BIT(nr) (1UL << (nr))
+#define NAND_GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> ((sizeof(unsigned long) * 8) - 1 - (h))))
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define clamp(val, lo, hi) MIN((typeof(val))MAX(val, lo), hi)
+
+#define MTK_TIMEOUT (500000)
+
+#define KB(x) ((x) * 1024UL)
+#define MB(x) (KB(x) * 1024UL)
+
+#define swap(a, b) \
+ do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while(0)
+
+/*
+ * wait until cond gets true or timeout.
+ *
+ * cond : C expression to wait
+ * timeout : usecs
+ *
+ * Returns:
+ * 0 : if cond = false after timeout elapsed.
+ * 1 : if cond = true after timeout elapsed,
+ * or the remain usecs if cond = true before timeout elapsed.
+ */
+#define check_with_timeout(cond, timeout) \
+({ \
+ lk_bigtime_t __ret; \
+ if (cond) { \
+ __ret = timeout; \
+ } else { \
+ lk_bigtime_t __end = current_time_hires() + timeout; \
+ \
+ for (;;) { \
+ lk_bigtime_t __now = current_time_hires(); \
+ \
+ if (cond) { \
+ __ret = (__end > __now) ? (__end - __now) : 1; \
+ break; \
+ } \
+ \
+ if (__end <= __now) { \
+ __ret = 0; \
+ break; \
+ } \
+ } \
+ } \
+ __ret; \
+})
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_nal.h b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_nal.h
new file mode 100644
index 0000000..90757a7
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nand_nal.h
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/nand/mtk_ecc_hal.h>
+#include <stdbool.h>
+#include <sys/types.h>
+
+#define MT2731_SUPPORT_SPI_NAND 1
+#define MT2731_DISABLE_RANDOMIZER 0
+
+/* Select the chip by setting nCE to low */
+#define NAND_NCE 0x01
+/* Select the command latch by setting CLE to high */
+#define NAND_CLE 0x02
+/* Select the address latch by setting ALE to high */
+#define NAND_ALE 0x04
+
+#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
+#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
+#define NAND_CTRL_CHANGE 0x80
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READ1 1
+#define NAND_CMD_RNDOUT 5
+#define NAND_CMD_PAGEPROG 0x10
+#define NAND_CMD_READOOB 0x50
+#define NAND_CMD_ERASE1 0x60
+#define NAND_CMD_STATUS 0x70
+#define NAND_CMD_SEQIN 0x80
+#define NAND_CMD_RNDIN 0x85
+#define NAND_CMD_READID 0x90
+#define NAND_CMD_ERASE2 0xd0
+#define NAND_CMD_PARAM 0xec
+#define NAND_CMD_GET_FEATURES 0xee
+#define NAND_CMD_SET_FEATURES 0xef
+#define NAND_CMD_RESET 0xff
+#define NAND_CMD_LOCK 0x2a
+#define NAND_CMD_UNLOCK1 0x23
+#define NAND_CMD_UNLOCK2 0x24
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART 0x30
+#define NAND_CMD_READCACHESEQ 0x31
+#define NAND_CMD_READCACHELAST 0x3f
+#define NAND_CMD_RNDOUTSTART 0xE0
+#define NAND_CMD_CACHEDPROG 0x15
+#define NAND_CMD_NONE -1
+
+/* Status bits */
+#define NAND_STATUS_FAIL 0x01
+#define NAND_STATUS_FAIL_N1 0x02
+#define NAND_STATUS_TRUE_READY 0x20
+#define NAND_STATUS_READY 0x40
+#define NAND_STATUS_WP 0x80
+
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE 0x00008000
+/* Search good / bad pattern on the last page of the eraseblock */
+#define NAND_BBT_SCANLASTPAGE 0x00010000
+
+/* Chip has cache read function */
+#define NAND_CACHEREAD 0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG 0x00000008
+
+#if MT2731_SUPPORT_SPI_NAND
+#define NAND_SINGLE_PLANE 0x00010000
+#define NAND_MULTI_PLANE 0x00020000
+#define NAND_SINGLE_PLANE_TWO_DIE 0x00040000
+#endif
+/*
+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
+ * patterns.
+ */
+#define NAND_NEED_SCRAMBLING 0x00002000
+
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_CACHEREAD(chip) ((chip->options & NAND_CACHEREAD))
+
+/* Max NAND ID length */
+#define NAND_MAX_ID_LEN 8
+
+struct mtk_nand_flash_dev {
+ const char *name;
+ u8 id[NAND_MAX_ID_LEN];
+ u8 id_len;
+
+ /* unit: KByte */
+ u32 chipsize;
+ u32 erasesize;
+ u32 pagesize;
+ u16 oobsize;
+ u32 fdmeccsize;
+ u8 bits_per_cell;
+
+ /* customized setting if need */
+ u8 freq_map; // bit[7:4]:lk clock freq, bit[3:0]:kernel clock freq
+ u32 acctiming;
+ u32 ecc_size; // sector size
+ u32 ecc_strength;
+ u32 bbt_options;
+ u32 options;
+};
+
+enum {
+ NAND_OPS_RAW_DMA_POLL = 0,
+ NAND_OPS_RAW_DMA_IRQ,
+ NAND_OPS_RAW_PIO_POLL,
+ NAND_OPS_RAW_PIO_IRQ,
+ NAND_OPS_ECC_DMA_POLL,
+ NAND_OPS_ECC_DMA_IRQ,
+ NAND_OPS_ECC_PIO_POLL,
+ NAND_OPS_ECC_PIO_IRQ,
+ NAND_OPS_ERASE_POLL,
+ NAND_OPS_ERASE_IRQ,
+};
+
+enum mtk_randomizer_operation {RAND_ENCODE, RAND_DECODE};
+
+struct mtk_nand_ops {
+ u32 mode;
+ u64 offset;
+ u64 len;
+ const u8 *writebuf;
+ u8 *readbuf;
+ /* ecc protected oob data */
+ u8 *oobeccbuf;
+ u32 oobeccoffs;
+ u32 oobecclen;
+ /* ecc unprotected oob data */
+ u8 *oobrawbuf;
+ u32 oobrawoffs;
+ u32 oobrawlen;
+ /* ecc parity data */
+ u8 *oobparitybuf;
+ u32 oobparityoffs;
+ u32 oobparitylen;
+};
+
+#if MT2731_SUPPORT_SPI_NAND
+
+typedef enum {
+ SF_UNDEF = 0,
+ SPI,
+ SPIQ,
+ QPI,
+} snand_mode;
+
+/*
+ * Standard SPI NAND flash commands
+ */
+#define SNAND_CMD_BLOCK_ERASE (0xD8)
+#define SNAND_CMD_GET_FEATURES (0x0F)
+#define SNAND_CMD_FEATURES_BLOCK_LOCK (0xA0)
+#define SNAND_CMD_FEATURES_OTP (0xB0)
+#define SNAND_CMD_FEATURES_STATUS (0xC0)
+#define SNAND_CMD_PAGE_READ (0x13)
+#define SNAND_CMD_PROGRAM_EXECUTE (0x10)
+#define SNAND_CMD_PROGRAM_LOAD (0x02)
+#define SNAND_CMD_PROGRAM_LOAD_X4 (0x32)
+#define SNAND_CMD_PROGRAM_RANDOM_LOAD (0x84)
+#define SNAND_CMD_PROGRAM_RANDOM_LOAD_X4 (0xC4)
+#define SNAND_CMD_READ_ID (0x9F)
+#define SNAND_CMD_RANDOM_READ (0x03)
+#define SNAND_CMD_RANDOM_READ_SPIQ (0x6B)
+#define SNAND_CMD_SET_FEATURES (0x1F)
+
+#define SNAND_CMD_SW_RESET (0xFF)
+#define SNAND_CMD_WRITE_ENABLE (0x06)
+#define SNAND_FLASH_ID_LENGTH (2) // The number of bytes for JEDEC ID
+
+/*
+ * SPI NAND - Status register
+ */
+#define SNAND_STATUS_OIP (0x01)
+#define SNAND_STATUS_WEL (0x02)
+#define SNAND_STATUS_ERASE_FAIL (0x04)
+#define SNAND_STATUS_PROGRAM_FAIL (0x08)
+#define SNAND_STATUS_TOO_MANY_ERROR_BITS (0x20)
+#define SNAND_STATUS_ECC_STATUS_MASK (0x30)
+#define SNAND_STATUS_ERROR_BITS_CORRECTED (0x10)
+
+/*
+ * SPI NAND - OTP register
+ */
+#define SNAND_OTP_ECC_ENABLE (0x10)
+#define SNAND_OTP_QE (0x01)
+
+/*
+ * SPI NAND - Block lock register
+ */
+#define SNAND_BLOCK_LOCK_BITS (0x7E)
+
+#endif
+
+struct mtk_nand_chip {
+ u8 (*read_byte)(struct mtk_nand_chip *nand);
+ void (*write_byte)(struct mtk_nand_chip *nand, u8 byte);
+ void (*write_buf)(struct mtk_nand_chip *nand, const u8 *buf, int len);
+ void (*read_buf)(struct mtk_nand_chip *nand, u8 *buf, int len);
+ void (*select_chip)(struct mtk_nand_chip *nand, int chip);
+ void (*cmd_ctrl)(struct mtk_nand_chip *nand, int dat, unsigned int ctrl);
+ int (*dev_ready)(struct mtk_nand_chip *nand);
+ int (*wait_busy_irq)(struct mtk_nand_chip *nand);
+ void (*cmdfunc)(struct mtk_nand_chip *nand, unsigned command, int column,
+ int page_addr);
+ int(*waitfunc)(struct mtk_nand_chip *this, int polling);
+
+ int (*block_bad)(struct mtk_nand_chip *nand, u64 ofs);
+ int (*block_markbad)(struct mtk_nand_chip *nand, u64 ofs);
+
+ int (*write_page_ecc_dma_polling)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_ecc_dma_irq)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_ecc_pio_polling)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_ecc_pio_irq)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_raw_dma_polling)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_raw_dma_irq)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_raw_pio_polling)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_page_raw_pio_irq)(struct mtk_nand_chip *chip, const u8 *buf,
+ int page);
+ int (*write_subpage_ecc_dma_polling)(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page);
+ int (*write_subpage_ecc_dma_irq)(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page);
+ int (*write_subpage_ecc_pio_polling)(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page);
+ int (*write_subpage_ecc_pio_irq)(struct mtk_nand_chip *chip, u32 offset,
+ u32 data_len, const u8 *buf, int page);
+
+ int (*read_subpage_ecc_dma_polling)(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg);
+ int (*read_subpage_ecc_dma_irq)(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg);
+ int (*read_subpage_ecc_pio_polling)(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg);
+ int (*read_subpage_ecc_pio_irq)(struct mtk_nand_chip *chip, u32 off,
+ u32 len, u8 *p, int pg);
+ int (*read_page_ecc_dma_polling)(struct mtk_nand_chip *chip, u8 *p, int pg);
+ int (*read_page_ecc_dma_irq)(struct mtk_nand_chip *chip, u8 *p, int pg);
+ int (*read_page_ecc_pio_polling)(struct mtk_nand_chip *chip, u8 *p, int pg);
+ int (*read_page_ecc_pio_irq)(struct mtk_nand_chip *chip, u8 *p, int pg);
+ int (*read_page_raw_dma_polling)(struct mtk_nand_chip *chip, u8 *buf, int page);
+ int (*read_page_raw_dma_irq)(struct mtk_nand_chip *chip, u8 *buf, int page);
+ int (*read_page_raw_pio_polling)(struct mtk_nand_chip *chip, u8 *buf, int page);
+ int (*read_page_raw_pio_irq)(struct mtk_nand_chip *chip, u8 *buf, int page);
+#if MT2731_DISABLE_RANDOMIZER
+ void (*enable_randomizer)(struct mtk_nand_chip *chip, int page,
+ enum mtk_randomizer_operation rand, int repage);
+ void (*disable_randomizer)(struct mtk_nand_chip *chip);
+#endif
+ int (*fill_oob_ecc)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+ int (*fill_oob_raw)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+ int (*fill_oob_parity)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+ int (*transfer_oob_ecc)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+ int (*transfer_oob_raw)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+ int (*transfer_oob_parity)(struct mtk_nand_chip *chip, u8* buf, u32 offset, u32 len);
+
+ /* nand device information */
+ u64 totalsize;
+ /* unit: Byte */
+ u64 chipsize;
+ u32 pagesize;
+ u32 oobsize;
+ u32 blocksize;
+ u32 ecc_size;
+ u32 ecc_strength;
+ u32 ecc_steps;
+ u32 subpagesize;
+ u32 fdm_ecc_size;
+ u32 oob_free_ecc_size;
+ u32 oob_free_raw_size;
+ u8 bits_per_cell;
+ u32 page_per_chip;
+ u32 page_per_block;
+ int chip_delay;
+ u32 options;
+ u8 numchips;
+ int activechip;
+ u32 acctiming;
+ u8 freq_map;
+
+ u8 *databuf;
+ u8 *oob_poi;
+
+ u8 *bbt;
+ u32 bbt_options;
+ int bbt_block;
+ int badblockpos;
+ int badblockbits;
+
+ bool bIsPNAND;
+
+#if MT2731_SUPPORT_SPI_NAND
+ snand_mode s_mode;
+
+ int (*snand_cmd)(struct mtk_nand_chip *nand, u32 cmd, u8 outlen);
+ int (*snand_cmd_ext)(struct mtk_nand_chip *nand, u8 *cmd, u8 *data, u32 outlen, u32 inlen);
+ int (*snand_wait_idel)(struct mtk_nand_chip *nand, u8 *dev_status);
+
+
+ int (*snand_pre_read)(struct mtk_nand_chip *nand, u32 off, u32 len, int pg);
+ int (*snand_pre_write)(struct mtk_nand_chip *nand, u32 off, u32 len, int pg);
+ int (*snand_post_write)(struct mtk_nand_chip *nand, int pg);
+ int (*snand_auto_erase)(struct mtk_nand_chip *nand, int pg);
+
+ int (*snand_get_feature)(struct mtk_nand_chip *nand, u8 Address, u8 *OutValue);
+ int (*snand_set_feature)(struct mtk_nand_chip *nand, u8 Address, u8 InValue);
+
+#endif
+
+ struct mtk_ecc_stats stats;
+
+ void *priv;
+};
+
+static inline void *nand_get_controller_data(struct mtk_nand_chip *chip)
+{
+ return chip->priv;
+}
+
+static inline void nand_set_controller_data(struct mtk_nand_chip *chip, void *priv)
+{
+ chip->priv = priv;
+}
+
+static inline bool nand_is_slc(struct mtk_nand_chip *chip)
+{
+ return chip->bits_per_cell == 1;
+}
+
+extern struct mtk_nand_flash_dev nand_flash_devs[];
+int mtk_nand_erase(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops);
+int mtk_nand_force_erase(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops);
+int mtk_nand_write(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops);
+int mtk_nand_read(struct mtk_nand_chip *chip, struct mtk_nand_ops *ops);
+int mtk_nand_block_isbad(struct mtk_nand_chip *chip, u32 page);
+int mtk_nand_block_markbad(struct mtk_nand_chip *chip, u32 page);
+int mtk_nand_block_unmarkbad(struct mtk_nand_chip *chip, u32 page);
+int mtk_nand_init(void);
+void mtk_nand_deinit(void);
+int mtk_nand_scan(struct mtk_nand_chip *chip, int maxchips);
+int mtk_nand_scan_tail(struct mtk_nand_chip *chip);
+int nand_reset(struct mtk_nand_chip *chip, int chipnr);
+struct mtk_nand_chip *mtk_get_nand_chip(void);
+int mtk_nand_block_checkbad(struct mtk_nand_chip *chip, u32 page);
+int nand_get_device_id(u8 *id, u32 len);
+
+#if MT2731_SUPPORT_SPI_NAND
+extern struct mtk_nand_flash_dev snand_flash_devs[];
+int mtk_snand_init(void);
+int mtk_snand_scan(struct mtk_nand_chip *chip, int maxchips);
+int snand_reset(struct mtk_nand_chip *chip, int chipnr);
+struct mtk_nand_chip *mtk_get_snand_chip(void);
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nfi_hal.h b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nfi_hal.h
new file mode 100644
index 0000000..bf2a6a5
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/mtk_nfi_hal.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/nand/mtk_nand_nal.h>
+#include <kernel/mutex.h>
+#include <kernel/event.h>
+
+#define NFI_CNFG (0x00)
+#define CNFG_AHB NAND_BIT(0)
+#define CNFG_READ_EN NAND_BIT(1)
+#define CNFG_DMA_BURST_EN NAND_BIT(2)
+#define CNFG_RESEED_SEC_EN NAND_BIT(4)
+#define CNFG_RAND_SEL NAND_BIT(5)
+#define CNFG_RAND_MASK (3 << 4)
+#define CNFG_BYTE_RW NAND_BIT(6)
+#define CNFG_HW_ECC_EN NAND_BIT(8)
+#define CNFG_AUTO_FMT_EN NAND_BIT(9)
+#define CNFG_OP_SINGLE_READ (2 << 12)
+#define CNFG_OP_PRGM (3 << 12)
+#define CNFG_OP_RESET (5 << 12)
+#define CNFG_OP_CUST (6 << 12)
+#define CNFG_OP_MASK (7 << 12)
+#define NFI_PAGEFMT (0x04)
+#define PAGEFMT_FDM_ECC_SHIFT (12)
+#define PAGEFMT_FDM_SHIFT (8)
+#define PAGEFMT_SPARE_16 (0)
+#define PAGEFMT_SPARE_26 (1)
+#define PAGEFMT_SPARE_27 (2)
+#define PAGEFMT_SPARE_28 (3)
+#define PAGEFMT_SPARE_32 (4)
+#define PAGEFMT_SPARE_36 (5)
+#define PAGEFMT_SPARE_40 (6)
+#define PAGEFMT_SPARE_44 (7)
+#define PAGEFMT_SPARE_48 (8)
+#define PAGEFMT_SPARE_49 (9)
+#define PAGEFMT_SPARE_50 (0xa)
+#define PAGEFMT_SPARE_51 (0xb)
+#define PAGEFMT_SPARE_52 (0xc)
+#define PAGEFMT_SPARE_62 (0xd)
+#define PAGEFMT_SPARE_61 (0xe)
+#define PAGEFMT_SPARE_63 (0xf)
+#define PAGEFMT_SPARE_64 (0x10)
+#define PAGEFMT_SPARE_67 (0x11)
+#define PAGEFMT_SPARE_74 (0x12)
+#define PAGEFMT_SPARE_SHIFT (16)
+#define PAGEFMT_SEC_SEL_512 NAND_BIT(2)
+#define PAGEFMT_512_2K (0)
+#define PAGEFMT_2K_4K (1)
+#define PAGEFMT_4K_8K (2)
+#define PAGEFMT_8K_16K (3)
+#define NFI_CON (0x08)
+#define CON_FIFO_FLUSH NAND_BIT(0)
+#define CON_NFI_RST NAND_BIT(1)
+#define CON_SRD NAND_BIT(4)
+#define CON_NOB_SHIFT (5)
+#define CON_BRD NAND_BIT(8) /* burst read */
+#define CON_BWR NAND_BIT(9) /* burst write */
+#define CON_SEC_SHIFT (12)
+#define NFI_ACCCON (0x0c)
+#define NFI_INTR_EN (0x10)
+#define INTR_RESET_DONE_EN NAND_BIT(2)
+#define INTR_BUSY_RETURN_EN NAND_BIT(4)
+#define INTR_AHB_DONE_EN NAND_BIT(6)
+#define INTR_EN NAND_BIT(31)
+#define NFI_INTR_STA (0x14)
+#define NFI_CMD (0x20)
+#define NFI_ADDRNOB (0x30)
+#define NFI_COLADDR (0x34)
+#define NFI_ROWADDR (0x38)
+#define NFI_STRDATA (0x40)
+#define STAR_EN (1)
+#define STAR_DE (0)
+#define NFI_CNRNB (0x44)
+#define NFI_DATAW (0x50)
+#define NFI_DATAR (0x54)
+#define NFI_PIO_DIRDY (0x58)
+#define PIO_DI_RDY (0x01)
+#define NFI_STA (0x60)
+#define STA_CMD NAND_BIT(0)
+#define STA_ADDR NAND_BIT(1)
+#define STA_BUSY NAND_BIT(8)
+#define STA_EMP_PAGE NAND_BIT(12)
+#define NFI_FSM_CUSTDATA (0xe << 16)
+#define NFI_FSM_MASK (0xf << 16)
+#define NAND_FSM_MASK (0x3f8 << 20)
+#define NFI_ADDRCNTR (0x70)
+#define CNTR_MASK NAND_GENMASK(16, 12)
+#define ADDRCNTR_ADDR_MASK (0xFFF)
+#define ADDRCNTR_CNTR_MASK (0x1F000)
+#define ADDRCNTR_SEC_SHIFT (12)
+#define ADDRCNTR_SEC(val) (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
+#define NFI_STRADDR (0x80)
+#define NFI_BYTELEN (0x84)
+#define NFI_CSEL (0x90)
+#define NFI_FDML(x) (0xa0 + (x) * sizeof(u32) * 2)
+#define NFI_FDMM(x) (0xa4 + (x) * sizeof(u32) * 2)
+#define NFI_FDM_MAX_SIZE (8)
+#define NFI_FDM_MIN_SIZE (1)
+#define NFI_MASTER_STA (0x224)
+#define MASTER_STA_MASK (0x0FFF)
+#define MASTER_BUS_BUSY (0x3)
+#define NFI_RANDOM_CNFG (0x238)
+#define RAN_ENCODE_EN NAND_BIT(0)
+#define ENCODE_SEED_SHIFT (1)
+#define RAN_DECODE_EN NAND_BIT(16)
+#define DECODE_SEED_SHIFT (17)
+#define RAN_SEED_MASK (0x7fff)
+#define RAND_SEED_SHIFT(op) \
+ ((op) == RAND_ENCODE ? ENCODE_SEED_SHIFT : DECODE_SEED_SHIFT)
+#define RAND_EN(op) \
+ ((op) == RAND_ENCODE ? RAN_ENCODE_EN : RAN_DECODE_EN)
+#define NFI_EMPTY_THRESH (0x23c)
+
+#define MTK_RESET_TIMEOUT (1000000)
+#define MTK_MAX_SECTOR (16)
+#define MTK_NAND_MAX_NSELS (2)
+
+#if MT2731_SUPPORT_SPI_NAND
+
+#define SNF_MAC_CTL (0x500)
+//SNF_MAC_CTL
+#define WIP (0x00000001)
+#define WIP_READY (0x00000002)
+#define TRIG (0x00000004)
+#define MAC_EN (0x00000008)
+#define MAC_SIO_SEL (0x00000010)
+
+#define SNF_MAC_OUTL (0x504)
+#define SNF_MAC_INL (0x508)
+
+#define SNF_RD_CTL1 (0x50C)
+#define SNF_RD_CTL2 (0x510)
+// SNF_RD_CTL2
+#define DATA_READ_DUMMY_OFFSET (8)
+#define DATA_READ_CMD_MASK (0x000000FF)
+
+#define SNF_RD_CTL3 (0x514)
+// SNF_RD_CTL3
+#define DATA_READ_ADDRESS_MASK (0x0000FFFF)
+
+#define SNF_GF_CTL1 (0x518)
+#define SNF_GF_CTL3 (0x520)
+// SNF_GF_CTL3
+#define GF_LOOP_LIMIT_OFFSET (16)
+#define GF_LOOP_LIMIT_MASK (0x000F0000)
+#define GF_LOOP_LIMIT_NO_LIMIT (0xF)
+#define GF_POLLING_CYCLE_MASK (0x0000FFFF)
+
+
+#define SNF_PG_CTL1 (0x524)
+// SNF_PG_CTL1
+#define PG_EXE_CMD_OFFSET (16)
+#define PG_LOAD_CMD_OFFSET (8)
+#define PG_WRITE_EN_CMD_OFFSET (0)
+
+#define SNF_PG_CTL2 (0x528)
+// SNF_PG_CTL2
+#define PG_LOAD_CMD_DUMMY_OUT_OFFSET (12)
+#define PG_LOAD_ADDR_MASK (0x0000FFFF)
+
+#define SNF_PG_CTL3 (0x52C)
+
+#define SNF_ER_CTL (0x530)
+// SNF_ER_CTL
+#define ER_CMD_OFFSET (8)
+#define ER_CMD_MASK (0x0000FF00)
+#define AUTO_ERASE_TRIGGER (0x00000001)
+
+#define SNF_ER_CTL2 (0x534)
+
+#define SNF_MISC_CTL (0x538)
+// SNF_MISC_CTL
+#define SNF_DATA_READ_MODE_X1 (0x0)
+#define SNF_DATA_READ_MODE_X4 (0x2)
+#define SNF_DATA_READ_MODE_OFFSET (16)
+#define SNF_DATA_READ_MODE_MASK (0x00070000)
+
+#define SNF_PG_LOAD_X4_EN (0x00100000)
+#define SNF_DATARD_CUSTOM_EN (0x00000040)
+#define SNF_PG_LOAD_CUSTOM_EN (0x00000080)
+#define SNF_SW_RST (0x10000000)
+#define SNF_DUAL_MASK (0x00007000)
+
+
+#define SNF_MISC_CTL2 (0x53C)
+// SNF_MISC_CTL
+#define PG_LOAD_BYTE_LEN_OFFSET (16)
+#define RD_DATA_BYTE_LEN_OFFSET (0)
+
+
+#define SNF_DLY_CTL1 (0x540)
+#define SNF_DLY_CTL2 (0x544)
+#define SNF_DLY_CTL3 (0x548)
+#define SNF_DLY_CTL4 (0x54C)
+
+#define SNF_STA_CTL1 (0x550)
+// SNF_STA_CTL1
+#define AUTO_BLKER (0x01000000)
+#define AUTO_READ (0x02000000)
+#define AUTO_PROGRAM (0x04000000)
+#define CUSTOM_READ (0x08000000)
+#define CUSTOM_PROGRAM (0x10000000)
+
+#define SNF_STA_CTL2 (0x554)
+#define SNF_STA_CTL3 (0x558)
+
+#define SNF_SNF_CNFG (0x55C)
+#define SNF_DEBUG_SEL (0x560)
+
+#define SNF_GPRAM_ADDR (0x800)
+
+#endif
+
+struct mtk_nfc_bad_mark_ctl {
+ void (*bm_swap)(struct mtk_nand_chip *chip, u8 *buf, int raw);
+ u32 sec;
+ u32 pos;
+};
+
+/*
+ * FDM: region used to store free OOB data
+ */
+struct mtk_nfc_fdm {
+ u32 reg_size;
+ u32 ecc_size;
+};
+
+struct mtk_nfc {
+ mutex_t lock;
+ event_t irq_event;
+ struct mtk_ecc_config ecc_cfg;
+ struct mtk_ecc *ecc;
+ uintptr_t regs;
+ u8 *buffer;
+};
+
+struct mtk_nfc_nand_chip {
+ struct mtk_nand_chip chip;
+ struct mtk_nfc_bad_mark_ctl bad_mark;
+ struct mtk_nfc_fdm fdm;
+ u32 spare_per_sector;
+};
+
+int mtk_nfc_nand_chip_init(struct mtk_nand_chip **ext_nand);
+
+#if MT2731_SUPPORT_SPI_NAND
+int mtk_snfc_nand_chip_init(struct mtk_nand_chip **ext_nand);
+void mtk_snfc_hw_reset(struct mtk_nfc *nfc);
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/nand/nand.h b/src/bsp/lk/platform/mt2731/include/platform/nand/nand.h
new file mode 100644
index 0000000..4487705
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/nand/nand.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+int nand_init_device(void);
+void nand_dump_device_info(void);
+void nand_prepare_goto_kernel(void);
diff --git a/src/bsp/lk/platform/mt2731/include/platform/plat_dbg_info.h b/src/bsp/lk/platform/mt2731/include/platform/plat_dbg_info.h
new file mode 100644
index 0000000..a063e63
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/plat_dbg_info.h
@@ -0,0 +1,100 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("Media Tek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef MT_PLAT_DBG_INFO_H
+#define MT_PLAT_DBG_INFO_H
+
+/* here include the header declaring users' data structure */
+#define PLAT_DBG_INFO_BASE 0x0011D800
+#define PLAT_DBG_INFO_SIZE 512
+#define INFO_TYPE_MAX 3
+
+#define INFO_TAIL_MAGIC 0x72590000
+
+#define INIT_DBG_HEAD(X) \
+ dbg_info->head[TYPE_##X]=((KEY_##X<<16)|(sizeof(DEF_##X)&0xFFFF));
+#define INFO_ALIGN_CHECK(X) \
+ _Static_assert(sizeof(X)%4==0,#X" alignment is violated");
+
+typedef enum {
+ TYPE_LAST_DRAMC,
+ TYPE_LAST_EMI,
+ TYPE_PLAT_SRAM_FLAG,
+ TYPE_END
+} DBG_INFO_TYPE;
+_Static_assert(TYPE_END <= INFO_TYPE_MAX, "TYPE_END is violated");
+
+typedef struct {
+ unsigned int head[INFO_TYPE_MAX];
+#ifdef DEF_LAST_DRAMC
+ DEF_LAST_DRAMC last_dramc;
+#endif
+#ifdef DEF_LAST_EMI
+ DEF_LAST_EMI last_emi;
+#endif
+#ifdef DEF_PLAT_SRAM_FLAG
+ DEF_PLAT_SRAM_FLAG plat_sram_flag;
+#endif
+ unsigned int tail;
+} top_dbg_info;
+_Static_assert(sizeof(top_dbg_info) <= PLAT_DBG_INFO_SIZE, "PLAT_DBG_INFO_SIZE is violated");
+
+#ifdef DEF_LAST_DRAMC
+#define KEY_LAST_DRAMC 0xD8A3
+INFO_ALIGN_CHECK(DEF_LAST_DRAMC)
+#endif
+#ifdef DEF_LAST_EMI
+#define KEY_LAST_EMI 0xE31C
+INFO_ALIGN_CHECK(DEF_LAST_EMI)
+#endif
+#ifdef DEF_PLAT_SRAM_FLAG
+#define KEY_PLAT_SRAM_FLAG 0xDB45
+INFO_ALIGN_CHECK(DEF_PLAT_SRAM_FLAG)
+#endif
+
+typedef struct {
+ unsigned int key;
+ unsigned int base;
+ unsigned int size;
+} dbg_info_in_bootargs;
+
+unsigned int get_dbg_info_key(DBG_INFO_TYPE info_type);
+unsigned int get_dbg_info_base(unsigned int key);
+unsigned int get_dbg_info_size(unsigned int key);
+
+#endif //MT_PLAT_DBG_INFO_H
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/platform_blx.h b/src/bsp/lk/platform/mt2731/include/platform/platform_blx.h
new file mode 100644
index 0000000..0a32b7e
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/platform_blx.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+#include <compiler.h>
+#include <debug.h>
+
+typedef enum {
+ BR_POWER_KEY = 0,
+ BR_USB,
+ BR_RTC,
+ BR_WDT,
+ BR_WDT_BY_PASS_PWK,
+ BR_TOOL_BY_PASS_PWK,
+ BR_2SEC_REBOOT,
+ BR_UNKNOWN,
+ BR_KERNEL_PANIC,
+ BR_WDT_SW,
+ BR_WST_HW,
+} boot_reason_t;
+
+void platform_memory_init(void);
+void platform_early_init_blx(void);
+void platform_set_aarch64_reset_vector(ulong vector);
+boot_reason_t platform_boot_status(void);
diff --git a/src/bsp/lk/platform/mt2731/include/platform/pll.h b/src/bsp/lk/platform/mt2731/include/platform/pll.h
new file mode 100644
index 0000000..af24e24
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/pll.h
@@ -0,0 +1,168 @@
+#ifndef PLL_H
+#define PLL_H
+
+/* Register */
+#define AP_PLL_CON0 (APMIXED_BASE + 0x00)
+#define AP_PLL_CON1 (APMIXED_BASE + 0x04)
+#define AP_PLL_CON2 (APMIXED_BASE + 0x08)
+#define AP_PLL_CON3 (APMIXED_BASE + 0x0C)
+#define AP_PLL_CON4 (APMIXED_BASE + 0x10)
+#define AP_PLL_CON5 (APMIXED_BASE + 0x14)
+#define CLKSQ_STB_CON0 (APMIXED_BASE + 0x18)
+#define PLL_PWR_CON0 (APMIXED_BASE + 0x1C)
+#define PLL_PWR_CON1 (APMIXED_BASE + 0x20)
+#define PLL_ISO_CON0 (APMIXED_BASE + 0x24)
+#define PLL_ISO_CON1 (APMIXED_BASE + 0x28)
+#define PLL_STB_CON0 (APMIXED_BASE + 0x2C)
+#define DIV_STB_CON0 (APMIXED_BASE + 0x30)
+#define PLL_CHG_CON0 (APMIXED_BASE + 0x34)
+#define PLL_TEST_CON0 (APMIXED_BASE + 0x38)
+#define PLL_TEST_CON1 (APMIXED_BASE + 0x3C)
+#define APLL1_TUNER_CON0 (APMIXED_BASE + 0x40)
+#define PLLON_CON0 (APMIXED_BASE + 0x44)
+#define PLLON_CON1 (APMIXED_BASE + 0x48)
+
+#define ARMPLL_CON0 (APMIXED_BASE + 0x204)
+#define ARMPLL_CON1 (APMIXED_BASE + 0x208)
+#define ARMPLL_CON2 (APMIXED_BASE + 0x20c)
+#define ARMPLL_CON3 (APMIXED_BASE + 0x210)
+
+#define MAINPLL_CON0 (APMIXED_BASE + 0x214)
+#define MAINPLL_CON1 (APMIXED_BASE + 0x218)
+#define MAINPLL_CON2 (APMIXED_BASE + 0x21C)
+#define MAINPLL_CON3 (APMIXED_BASE + 0x220)
+
+#define UNIVPLL_CON0 (APMIXED_BASE + 0x224)
+#define UNIVPLL_CON1 (APMIXED_BASE + 0x228)
+#define UNIVPLL_CON2 (APMIXED_BASE + 0x22C)
+#define UNIVPLL_CON3 (APMIXED_BASE + 0x230)
+
+#define MSDCPLL_CON0 (APMIXED_BASE + 0x234)
+#define MSDCPLL_CON1 (APMIXED_BASE + 0x238)
+#define MSDCPLL_CON2 (APMIXED_BASE + 0x23C)
+#define MSDCPLL_CON3 (APMIXED_BASE + 0x240)
+
+#define APLL1_CON0 (APMIXED_BASE + 0x244)
+#define APLL1_CON1 (APMIXED_BASE + 0x248)
+#define APLL1_CON2 (APMIXED_BASE + 0x24C)
+#define APLL1_CON3 (APMIXED_BASE + 0x250)
+#define APLL1_CON4 (APMIXED_BASE + 0x254)
+
+#define APLL2_CON0 (APMIXED_BASE + 0x258)
+#define APLL2_CON1 (APMIXED_BASE + 0x25C)
+#define APLL2_CON2 (APMIXED_BASE + 0x260)
+#define APLL2_CON3 (APMIXED_BASE + 0x264)
+#define APLL2_CON4 (APMIXED_BASE + 0x268)
+
+#define MPLL_CON0 (APMIXED_BASE + 0x26C)
+#define MPLL_CON1 (APMIXED_BASE + 0x270)
+#define MPLL_CON2 (APMIXED_BASE + 0x274)
+#define MPLL_CON3 (APMIXED_BASE + 0x278)
+
+#define ETHERPLL_CON0 (APMIXED_BASE + 0x27C)
+#define ETHERPLL_CON1 (APMIXED_BASE + 0x280)
+#define ETHERPLL_CON2 (APMIXED_BASE + 0x284)
+#define ETHERPLL_CON3 (APMIXED_BASE + 0x288)
+
+/* MCUCFG Register */
+
+/* TOPCKGEN Register */
+#define CLK_MODE (CKSYS_BASE + 0x000)
+#define CLK_CFG_UPDATE (CKSYS_BASE + 0x004)
+#define CLK_CFG_0 (CKSYS_BASE + 0x040)
+#define CLK_CFG_0_SET (CKSYS_BASE + 0x044)
+#define CLK_CFG_0_CLR (CKSYS_BASE + 0x048)
+#define CLK_CFG_1 (CKSYS_BASE + 0x050)
+#define CLK_CFG_1_SET (CKSYS_BASE + 0x054)
+#define CLK_CFG_1_CLR (CKSYS_BASE + 0x058)
+#define CLK_CFG_2 (CKSYS_BASE + 0x060)
+#define CLK_CFG_2_SET (CKSYS_BASE + 0x064)
+#define CLK_CFG_2_CLR (CKSYS_BASE + 0x068)
+#define CLK_CFG_3 (CKSYS_BASE + 0x070)
+#define CLK_CFG_3_SET (CKSYS_BASE + 0x074)
+#define CLK_CFG_3_CLR (CKSYS_BASE + 0x078)
+#define CLK_CFG_4 (CKSYS_BASE + 0x080)
+#define CLK_CFG_4_SET (CKSYS_BASE + 0x084)
+#define CLK_CFG_4_CLR (CKSYS_BASE + 0x088)
+#define CLK_CFG_5 (CKSYS_BASE + 0x090)
+#define CLK_CFG_5_SET (CKSYS_BASE + 0x094)
+#define CLK_CFG_5_CLR (CKSYS_BASE + 0x098)
+#define CLK_CFG_6 (CKSYS_BASE + 0x0A0)
+#define CLK_CFG_6_SET (CKSYS_BASE + 0x0A4)
+#define CLK_CFG_6_CLR (CKSYS_BASE + 0x0A8)
+#define CLK_CFG_7 (CKSYS_BASE + 0x0B0)
+#define CLK_CFG_7_SET (CKSYS_BASE + 0x0B4)
+#define CLK_CFG_7_CLR (CKSYS_BASE + 0x0B8)
+
+#define CLK_MISC_CFG_0 (CKSYS_BASE + 0x104)
+#define CLK_DBG_CFG (CKSYS_BASE + 0x10C)
+#define CLK_SCP_CFG_0 (CKSYS_BASE + 0x200)
+#define CLK_SCP_CFG_1 (CKSYS_BASE + 0x204)
+#define CLK26CALI_0 (CKSYS_BASE + 0x220)
+#define CLK26CALI_1 (CKSYS_BASE + 0x224)
+#define CKSTA_REG (CKSYS_BASE + 0x230)
+#define CLKMON_CLK_SEL_REG (CKSYS_BASE + 0x300)
+#define CLKMON_K1_REG (CKSYS_BASE + 0x304)
+#define CLK_AUDDIV_0 (CKSYS_BASE + 0x320)
+#define AUD_TOP_CFG (CKSYS_BASE + 0x32C)
+#define AUD_TOP_MON (CKSYS_BASE + 0x330)
+#define CLK_PDN_REG (CKSYS_BASE + 0x400)
+#define CLK_EXTCK_REG (CKSYS_BASE + 0x500)
+
+/* INFRASYS Register, Infra DCM */
+#define INFRA_GLOBALCON_DCMCTL (INFRACFG_BASE + 0x50)
+#define INFRA_BUS_DCM_CTRL (INFRACFG_BASE + 0x70)
+#define PERI_BUS_DCM_CTRL (INFRACFG_BASE + 0x74)
+#define MODULE_SW_CG_0_SET (INFRACFG_BASE + 0x80)
+#define MODULE_SW_CG_0_CLR (INFRACFG_BASE + 0x84)
+#define MODULE_SW_CG_1_SET (INFRACFG_BASE + 0x88)
+#define MODULE_SW_CG_1_CLR (INFRACFG_BASE + 0x8C)
+#define MODULE_SW_CG_0_STA (INFRACFG_BASE + 0x90)
+#define MODULE_SW_CG_1_STA (INFRACFG_BASE + 0x94)
+#define MODULE_CLK_SEL (INFRACFG_BASE + 0x98)
+#define MODULE_SW_CG_2_SET (INFRACFG_BASE + 0xA4)
+#define MODULE_SW_CG_2_CLR (INFRACFG_BASE + 0xA8)
+#define MODULE_SW_CG_2_STA (INFRACFG_BASE + 0xAC)
+#define MODULE_SW_CG_3_SET (INFRACFG_BASE + 0xC0)
+#define MODULE_SW_CG_3_CLR (INFRACFG_BASE + 0xC4)
+#define MODULE_SW_CG_3_STA (INFRACFG_BASE + 0xC8)
+#define INFRA_TOPAXI_SI0_CTL (INFRACFG_BASE + 0x0200)
+#define INFRA_TOPAXI_PROTECTEN (INFRACFG_BASE + 0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA1 (INFRACFG_BASE + 0x0228)
+#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_BASE + 0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_BASE + 0x0258)
+#define INFRA_TOPAXI_PROTECTEN_SET (INFRACFG_BASE + 0x02A0)
+#define INFRA_TOPAXI_PROTECTEN_CLR (INFRACFG_BASE + 0x02A4)
+#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_BASE + 0x02A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_BASE + 0x02AC)
+#define INFRA_PLL_ULPOSC_CON0 (INFRACFG_BASE + 0x0B00)
+#define INFRA_PLL_ULPOSC_CON1 (INFRACFG_BASE + 0x0B04)
+#define VDNR_CON (INFRACFG_BASE + 0x71C)
+/* MCUCFG CLKMUX */
+
+/* SUBSYS_CG */
+#define TRNG_PDN_SET (INFRACFG_BASE + 0x0088)
+#define TRNG_PDN_CLR (INFRACFG_BASE + 0x008C)
+
+/* Pericfg Register */
+//#define PERIAXI_SI0_CTL (PERICFG_BASE+0x20C)
+
+#define GCE_BASE (IO_PHYS + 0x238000)
+#define GCE_CTL_INT0 (GCE_BASE + 0xf0)
+
+#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0 \
+ (bcrm_INFRA_AO_wrapper_base + 0x7C)
+
+/* mcusys part has been in BROM. test here only. */
+#define ACLKEN_DIV (MCUSYS_CFGREG_BASE + 0x640)
+ #define ACLKEN_DIV_SEL_MASK (0x1f << 0)
+ #define ACLKEN_DIV_SEL_HALF (0x12 << 0)
+#define BUS_PLL_DIVIDER_CFG (MCUSYS_CFGREG_BASE + 0x7c0)
+ #define BUS_PLLDIV_MUX1SEL_MASK (0x3 << 9)
+ #define BUS_PLLDIV_MUX1SEL_ARMPLL (0x1 << 9)
+ #define BUS_PLLDIV_MUX1SEL_26M (0x0 << 9)
+
+void mt_pll_init(void);
+void mt_pll_post_init(void);
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/pmic.h b/src/bsp/lk/platform/mt2731/include/platform/pmic.h
new file mode 100644
index 0000000..1dab7fe
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/pmic.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#if defined(PMIC_CHIP_MT6389)
+#include <platform/MT6389/pmic.h>
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/pmic_wrap_init.h b/src/bsp/lk/platform/mt2731/include/platform/pmic_wrap_init.h
new file mode 100644
index 0000000..97626f1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/pmic_wrap_init.h
@@ -0,0 +1,338 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __PMIC_WRAP_INIT_H__
+#define __PMIC_WRAP_INIT_H__
+
+/****** SW ENV define *************************************/
+#define PMIC_WRAP_PRELOADER 0
+#define PMIC_WRAP_LK 1
+#define PMIC_WRAP_KERNEL 0
+#define PMIC_WRAP_SCP 0
+#define PMIC_WRAP_CTP 0
+
+/* #define PMIC_WRAP_DEBUG */
+#define PMIC_WRAP_SUPPORT
+#define PMIC_WRAP_CRC_SUPPORT
+/* #define PMIC_WRAP_RESET_UT */
+
+#define MTK_PLATFORM_MT2731 1
+#define MTK_PLATFORM_MT6763 0
+
+#if defined PMIC_CHIP_MT6356
+#define MTK_PLATFORM_MT6356 1
+#endif
+#if defined PMIC_CHIP_MT6389
+#define MTK_PLATFORM_MT6389 1
+#endif
+/****** For BringUp. if BringUp doesn't had PMIC, need open this ***********/
+#if (PMIC_WRAP_PRELOADER)
+ #if CFG_FPGA_PLATFORM
+ #define PMIC_WRAP_NO_PMIC
+ #else
+ /* #define PWRAP_TIMEOUT */
+ #endif
+#elif (PMIC_WRAP_LK)
+ #if CFG_FPGA_PLATFORM
+ #define PMIC_WRAP_NO_PMIC
+ #else
+ #define PWRAP_TIMEOUT
+ #endif
+#elif (PMIC_WRAP_KERNEL)
+ #if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
+ #define PMIC_WRAP_NO_PMIC
+ #else
+ /* #define PWRAP_TIMEOUT */
+ #endif
+#elif (PMIC_WRAP_CTP)
+ #if defined(CONFIG_MTK_FPGA)
+ #define PMIC_WRAP_NO_PMIC
+ #else
+ /* #define PWRAP_TIMEOUT */
+ #endif
+#else
+ #define PWRAP_TIMEOUT
+#endif
+
+/****** SW ENV header define *****************************/
+#if (PMIC_WRAP_PRELOADER)
+ #include <sync_write.h>
+ #include <typedefs.h>
+ #include <gpio.h>
+ #include <mt2731.h>
+#elif (PMIC_WRAP_LK)
+ #include <debug.h>
+ #include <platform/mt_typedefs.h>
+ #include <platform/mt_reg_base.h>
+ /* #include <platform/mt_gpt.h> */
+ #include <platform/mt_irq.h>
+ #include <sys/types.h>
+ /* #include <platform/sync_write.h> */
+ #include <platform/upmu_hw.h>
+#elif (PMIC_WRAP_KERNEL)
+#elif (PMIC_WRAP_SCP)
+ #include "stdio.h"
+ #include <string.h>
+ #include "FreeRTOS.h"
+#elif (PMIC_WRAP_CTP)
+ #include <sync_write.h>
+ #include <typedefs.h>
+ #include <reg_base.H>
+#else
+ ### Compile error, check SW ENV define
+#endif
+
+/*****************************************************************/
+#include <platform/reg_PMIC_WRAP.h>
+#include <platform/reg_PMIC_WRAP_mac.h>
+/*******************macro for regsister@PMIC *******************************/
+
+/*******************start ---external API********************************/
+extern signed int pwrap_read(unsigned int adr, unsigned int *rdata);
+extern signed int pwrap_write(unsigned int adr, unsigned int wdata);
+extern signed int pwrap_write_nochk(unsigned int adr, unsigned int wdata);
+extern signed int pwrap_read_nochk(unsigned int adr, unsigned int *rdata);
+extern signed int pwrap_wacs2(unsigned int write, unsigned int adr, unsigned int wdata, unsigned int *rdata);
+extern void pwrap_dump_all_register(void);
+extern signed int pwrap_init_preloader(void);
+extern signed int pwrap_init_lk(void);
+extern signed int pwrap_init_scp(void);
+extern signed int pwrap_init(void);
+
+/****** DEBUG marco define *******************************/
+#define PWRAPTAG "[PWRAP] "
+#if (PMIC_WRAP_PRELOADER)
+ #ifdef PMIC_WRAP_DEBUG
+ #define PWRAPFUC(fmt, arg...) print(PWRAPTAG "%s\n", __func__)
+ #define PWRAPLOG(fmt, arg...) print(PWRAPTAG fmt, ##arg)
+ #else
+ #define PWRAPFUC(fmt, arg...)
+ #define PWRAPLOG(fmt, arg...)
+ #endif /* end of #ifdef PMIC_WRAP_DEBUG */
+ #define PWRAPCRI(fmt, arg...) print(PWRAPTAG fmt, ##arg)
+ #define PWRAPERR(fmt, arg...) print(PWRAPTAG "ERR " fmt, ##arg)
+#elif (PMIC_WRAP_LK)
+ #ifdef PMIC_WRAP_DEBUG
+ #define PWRAPFUC(fmt, arg...) \
+ dprintf(CRITICAL, PWRAPTAG "%s\n", __func__)
+ #define PWRAPLOG(fmt, arg...) \
+ dprintf(CRITICAL, PWRAPTAG fmt, ##arg)
+ #else
+ #define PWRAPFUC(fmt, arg...)
+ #define PWRAPLOG(fmt, arg...)
+ #endif /* end of #ifdef PMIC_WRAP_DEBUG */
+ #define PWRAPERR(fmt, arg...) \
+ dprintf(INFO, PWRAPTAG "ERR,line=%d " fmt, __LINE__, ##arg)
+ #define PWRAPCRI(fmt, arg...) \
+ dprintf(CRITICAL, PWRAPTAG "CRI,line=%d " fmt, __LINE__, ##arg)
+#elif (PMIC_WRAP_KERNEL)
+ #ifdef PMIC_WRAP_DEBUG
+ #define PWRAPDEB(fmt, arg...)
+ #define PWRAPLOG(fmt, arg...) pr_err(PWRAPTAG fmt, ##arg)
+ #define PWRAPFUC(fmt, arg...)
+ #define PWRAPREG(fmt, arg...) pr_err(PWRAPTAG fmt, ##arg)
+ #else
+ #define PWRAPDEB(fmt, arg...)
+ #define PWRAPLOG(fmt, arg...)
+ #define PWRAPFUC(fmt, arg...)
+ #define PWRAPREG(fmt, arg...)
+ #endif /* end of #ifdef PMIC_WRAP_DEBUG */
+ #define PWRAP_PR_ERR(fmt, arg...) \
+ pr_err(PWRAPTAG "ERROR,line=%d " fmt, __LINE__, ##arg)
+#elif (PMIC_WRAP_SCP)
+ #ifdef PMIC_WRAP_DEBUG
+ #define PWRAPFUC(fmt, arg...) \
+ PRINTF_D(PWRAPTAG "%s\n", __func__)
+ #define PWRAPLOG(fmt, arg...) \
+ PRINTF_D(PWRAPTAG fmt, ##arg)
+ #else
+ #define PWRAPFUC(fmt, arg...)
+ #define PWRAPLOG(fmt, arg...)
+ #endif /* end of #ifdef PMIC_WRAP_DEBUG */
+ #define PWRAPERR(fmt, arg...) \
+ PRINTF_E(PWRAPTAG "ERR, line=%d " fmt, __LINE__, ##arg)
+#elif (PMIC_WRAP_CTP)
+ #ifdef PMIC_WRAP_DEBUG
+ #define PWRAPFUC(fmt, arg...) \
+ dbg_print(PWRAPTAG "%s\n", __func__)
+ #define PWRAPLOG(fmt, arg...) \
+ dbg_print(PWRAPTAG fmt, ##arg)
+ #else
+ #define PWRAPFUC(fmt, arg...) \
+ dbg_print(PWRAPTAG "%s\n", __func__)
+ #define PWRAPLOG(fmt, arg...) \
+ dbg_print(PWRAPTAG fmt, ##arg)
+ #endif /* end of #ifdef PMIC_WRAP_DEBUG */
+ #define PWRAPERR(fmt, arg...) \
+ dbg_print(PWRAPTAG "ERR,line=%d " fmt, __LINE__, ##arg)
+ #define PWRAPCRI(fmt, arg...) \
+ dbg_print(PWRAPTAG "line=%d " fmt, __LINE__, ##arg)
+#else
+ ### Compile error, check SW ENV define
+#endif
+/**********************************************************/
+
+/*********** platform info, PMIC info ********************/
+#define PMIC_WRAP_REG_RANGE (354)
+#define CLK_26M_PRD (3846)
+#define CLK_ULPOSC_PRD (6400)
+
+#define DEFAULT_VALUE_READ_TEST (0x5aa5)
+#define DEFAULT_VALUE_WRITE_TEST (0xa55a)
+#define PWRAP_WRITE_TEST_VALUE (0x1234)
+#define PWRAP_EXT_WRITE_TEST_VALUE (0x4321)
+
+/**********************************************************/
+
+#define ENABLE (1)
+#define DISABLE (0)
+#define DISABLE_ALL (0)
+
+/* HIPRIS_ARB */
+/*
+ * #define MDINF (1 << 0)
+ * #define WACS0 (1 << 1)
+ * #define WACS1 (1 << 2)
+ * #define WACS2 (1 << 4)
+ * #define DVFSINF (1 << 3)
+ * #define STAUPD (1 << 5)
+ * #define GPSINF (1 << 6)
+*/
+
+/* MUX SEL */
+#define WRAPPER_MODE (0)
+#define MANUAL_MODE (1)
+
+/* macro for MAN_RDATA FSM */
+#define MAN_FSM_NO_REQ (0x00)
+#define MAN_FSM_IDLE (0x00)
+#define MAN_FSM_REQ (0x02)
+#define MAN_FSM_WFDLE (0x04)
+#define MAN_FSM_WFVLDCLR (0x06)
+
+/* macro for WACS_FSM */
+#define WACS_FSM_IDLE (0x00)
+#define WACS_FSM_REQ (0x02) /* request in process */
+#define WACS_FSM_WFDLE (0x04)
+#define WACS_FSM_WFVLDCLR (0x06)
+#define WACS_INIT_DONE (0x01)
+#define WACS_SYNC_IDLE (0x01)
+#define WACS_SYNC_BUSY (0x00)
+
+/**** timeout time, unit :us ***********/
+#define TIMEOUT_RESET (0x2710) /* 10000us */
+#define TIMEOUT_READ (0x2710) /* 10000us */
+#define TIMEOUT_WAIT_IDLE (0x2710) /* 10000us */
+
+/*-----macro for manual commnd ---------------------------------*/
+#define OP_WR (0x1)
+#define OP_RD (0x0)
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_OUTQ (0xA)
+#define OP_INS (0xC)
+#define OP_INS0 (0xD)
+#define OP_IND (0xE)
+#define OP_INQ (0xF)
+#define OP_OS2IS (0x10)
+#define OP_OS2ID (0x11)
+#define OP_OS2IQ (0x12)
+#define OP_OD2IS (0x13)
+#define OP_OD2ID (0x14)
+#define OP_OD2IQ (0x15)
+#define OP_OQ2IS (0x16)
+#define OP_OQ2ID (0x17)
+#define OP_OQ2IQ (0x18)
+#define OP_OSNIS (0x19)
+#define OP_ODNID (0x1A)
+
+/******************Error handle *****************************/
+#define E_PWR_INVALID_ARG (1)
+#define E_PWR_INVALID_RW (2)
+#define E_PWR_INVALID_ADDR (3)
+#define E_PWR_INVALID_WDAT (4)
+#define E_PWR_INVALID_OP_MANUAL (5)
+#define E_PWR_NOT_IDLE_STATE (6)
+#define E_PWR_NOT_INIT_DONE (7)
+#define E_PWR_NOT_INIT_DONE_READ (8)
+#define E_PWR_WAIT_IDLE_TIMEOUT (9)
+#define E_PWR_WAIT_IDLE_TIMEOUT_READ (10)
+#define E_PWR_INIT_SIDLY_FAIL (11)
+#define E_PWR_RESET_TIMEOUT (12)
+#define E_PWR_TIMEOUT (13)
+#define E_PWR_INIT_RESET_SPI (20)
+#define E_PWR_INIT_SIDLY (21)
+#define E_PWR_INIT_REG_CLOCK (22)
+#define E_PWR_INIT_ENABLE_PMIC (23)
+#define E_PWR_INIT_DIO (24)
+#define E_PWR_INIT_CIPHER (25)
+#define E_PWR_INIT_WRITE_TEST (26)
+#define E_PWR_INIT_ENABLE_CRC (27)
+#define E_PWR_INIT_ENABLE_DEWRAP (28)
+#define E_PWR_READ_TEST_FAIL (30)
+#define E_PWR_WRITE_TEST_FAIL (31)
+#define E_PWR_SWITCH_DIO (32)
+
+
+/*-----macro for read/write register -------------------------------------*/
+
+#define WRAP_RD32(addr) (*(volatile unsigned int *)(addr))
+#define WRAP_WR32(addr,data) ((*(volatile unsigned int *)(addr)) = (unsigned int)data)
+#define WRAP_SET_BIT(BS,REG) ((*(volatile unsigned int*)(REG)) |= (unsigned int)(BS))
+#define WRAP_CLR_BIT(BS,REG) ((*(volatile unsigned int*)(REG)) &= ~((unsigned int)(BS)))
+
+/**************** end ---external API***********************************/
+
+/************* macro for spi clock config ******************************/
+
+#define CLK_SPI_CK_26M 0x1
+#define PMIC_CLOCK_DCM (INFRACFG_BASE+0x074)
+#define PMICW_CLOCK_CTRL (INFRACFG_BASE+0x108)
+#define INFRA_GLOBALCON_RST2_SET (INFRACFG_BASE+0x140)
+#define INFRA_GLOBALCON_RST2_CLR (INFRACFG_BASE+0x144)
+#define APB_CLOCK_GATING (INFRACFG_BASE+0xF0C)
+
+#define IOCFG_RB_DRV_CFG1_SET (IO_CFG_RB_BASE+0x014)
+#define IOCFG_RB_DRV_CFG1_CLR (IO_CFG_RB_BASE+0x018)
+#define IOCFG_RB_PD_CFG0_SET (IO_CFG_RB_BASE+0x044)
+#define IOCFG_RB_PD_CFG0_CLR (IO_CFG_RB_BASE+0x048)
+#define IOCFG_RB_PU_CFG0_SET (IO_CFG_RB_BASE+0x054)
+#define IOCFG_RB_PU_CFG0_CLR (IO_CFG_RB_BASE+0x058)
+
+#endif /*__PMIC_WRAP_INIT_H__*/
diff --git a/src/bsp/lk/platform/mt2731/include/platform/ram_console_def.h b/src/bsp/lk/platform/mt2731/include/platform/ram_console_def.h
new file mode 100644
index 0000000..f78c81f
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/ram_console_def.h
@@ -0,0 +1,61 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __RAM_CONSOLE_DEF_H__
+#define __RAM_CONSOLE_DEF_H__
+
+#include <platform/mt2731.h>
+
+// ram_console over sram for mt2731
+#define RAM_CONSOLE_OVER_SRAM
+
+#ifdef RAM_CONSOLE_OVER_SRAM // sram
+#define RAM_CONSOLE_DEF_ADDR RAM_CONSOLE_SRAM_ADDR
+#define RAM_CONSOLE_DEF_SIZE RAM_CONSOLE_SRAM_SIZE
+
+#else // dram
+#define RAM_CONSOLE_DEF_ADDR RAM_CONSOLE_DRAM_ADDR
+#define RAM_CONSOLE_DEF_SIZE RAM_CONSOLE_DRAM_SIZE
+#endif
+
+// align minirdump-reserved-memory in dts
+#define KE_RESERVED_MEM_ADDR (DRAM_BASE_PHY + 0x3ff0000)
+#define PSTORE_ADDR (DRAM_BASE_PHY + 0x3f10000)
+#define PSTORE_SIZE 0xe0000
+
+#endif // #ifndef __RAM_CONSOLE_H__
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP.h b/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP.h
new file mode 100644
index 0000000..6799bf1
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP.h
@@ -0,0 +1,333 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __PMIC_WRAP_REGS_H__
+#define __PMIC_WRAP_REGS_H__
+
+#define PMIC_WRAP_MUX_SEL ((UINT32P)(PWRAP_BASE+0x0))
+#define PMIC_WRAP_WRAP_EN ((UINT32P)(PWRAP_BASE+0x4))
+#define PMIC_WRAP_DIO_EN ((UINT32P)(PWRAP_BASE+0x8))
+#define PMIC_WRAP_SI_SAMPLE_CTRL ((UINT32P)(PWRAP_BASE+0xC))
+#define PMIC_WRAP_SI_SAMPLE_CTRL_1 ((UINT32P)(PWRAP_BASE+0x10))
+#define PMIC_WRAP_SI_SAMPLE_CTRL_2 ((UINT32P)(PWRAP_BASE+0x14))
+#define PMIC_WRAP_SI_SAMPLE_CTRL_3 ((UINT32P)(PWRAP_BASE+0x18))
+#define PMIC_WRAP_SI_SAMPLE_CTRL_ULPOSC ((UINT32P)(PWRAP_BASE+0x1C))
+#define PMIC_WRAP_RDDMY ((UINT32P)(PWRAP_BASE+0x20))
+#define PMIC_WRAP_CSHEXT_WRITE ((UINT32P)(PWRAP_BASE+0x24))
+#define PMIC_WRAP_CSHEXT_READ ((UINT32P)(PWRAP_BASE+0x28))
+#define PMIC_WRAP_CSLEXT_WRITE ((UINT32P)(PWRAP_BASE+0x2C))
+#define PMIC_WRAP_CSLEXT_READ ((UINT32P)(PWRAP_BASE+0x30))
+#define PMIC_WRAP_EXT_CK_WRITE ((UINT32P)(PWRAP_BASE+0x34))
+#define PMIC_WRAP_EXT_CK_READ ((UINT32P)(PWRAP_BASE+0x38))
+#define PMIC_WRAP_STAUPD_CTRL ((UINT32P)(PWRAP_BASE+0x3C))
+#define PMIC_WRAP_STAUPD_GRPEN ((UINT32P)(PWRAP_BASE+0x40))
+#define PMIC_WRAP_EINT_STA0_ADR ((UINT32P)(PWRAP_BASE+0x44))
+#define PMIC_WRAP_EINT_STA1_ADR ((UINT32P)(PWRAP_BASE+0x48))
+#define PMIC_WRAP_EINT_STA ((UINT32P)(PWRAP_BASE+0x4C))
+#define PMIC_WRAP_EINT_CLR ((UINT32P)(PWRAP_BASE+0x50))
+#define PMIC_WRAP_EINT_CTRL ((UINT32P)(PWRAP_BASE+0x54))
+#define PMIC_WRAP_STAUPD_MAN_TRIG ((UINT32P)(PWRAP_BASE+0x58))
+#define PMIC_WRAP_STAUPD_STA ((UINT32P)(PWRAP_BASE+0x5C))
+#define PMIC_WRAP_WRAP_STA ((UINT32P)(PWRAP_BASE+0x60))
+#define PMIC_WRAP_HARB_INIT ((UINT32P)(PWRAP_BASE+0x64))
+#define PMIC_WRAP_HARB_HPRIO ((UINT32P)(PWRAP_BASE+0x68))
+#define PMIC_WRAP_HPRIO_ARB_EN ((UINT32P)(PWRAP_BASE+0x6C))
+#define PMIC_WRAP_HARB_STA0 ((UINT32P)(PWRAP_BASE+0x70))
+#define PMIC_WRAP_HARB_STA1 ((UINT32P)(PWRAP_BASE+0x74))
+#define PMIC_WRAP_HARB_STA2 ((UINT32P)(PWRAP_BASE+0x78))
+#define PMIC_WRAP_MAN_EN ((UINT32P)(PWRAP_BASE+0x7C))
+#define PMIC_WRAP_MAN_CMD ((UINT32P)(PWRAP_BASE+0x80))
+#define PMIC_WRAP_MAN_RDATA ((UINT32P)(PWRAP_BASE+0x84))
+#define PMIC_WRAP_MAN_VLDCLR ((UINT32P)(PWRAP_BASE+0x88))
+#define PMIC_WRAP_WACS0_EN ((UINT32P)(PWRAP_BASE+0x8C))
+#define PMIC_WRAP_INIT_DONE0 ((UINT32P)(PWRAP_BASE+0x90))
+#define PMIC_WRAP_WACS1_EN ((UINT32P)(PWRAP_BASE+0x94))
+#define PMIC_WRAP_INIT_DONE1 ((UINT32P)(PWRAP_BASE+0x98))
+#define PMIC_WRAP_WACS2_EN ((UINT32P)(PWRAP_BASE+0x9C))
+#define PMIC_WRAP_INIT_DONE2 ((UINT32P)(PWRAP_BASE+0xA0))
+#define PMIC_WRAP_WACS_P2P_EN ((UINT32P)(PWRAP_BASE+0xA4))
+#define PMIC_WRAP_INIT_DONE_P2P ((UINT32P)(PWRAP_BASE+0xA8))
+#define PMIC_WRAP_WACS_MD32_EN ((UINT32P)(PWRAP_BASE+0xAC))
+#define PMIC_WRAP_INIT_DONE_MD32 ((UINT32P)(PWRAP_BASE+0xB0))
+#define PMIC_WRAP_INT0_EN ((UINT32P)(PWRAP_BASE+0xB4))
+#define PMIC_WRAP_INT0_FLG_RAW ((UINT32P)(PWRAP_BASE+0xB8))
+#define PMIC_WRAP_INT0_FLG ((UINT32P)(PWRAP_BASE+0xBC))
+#define PMIC_WRAP_INT0_CLR ((UINT32P)(PWRAP_BASE+0xC0))
+#define PMIC_WRAP_INT1_EN ((UINT32P)(PWRAP_BASE+0xC4))
+#define PMIC_WRAP_INT1_FLG_RAW ((UINT32P)(PWRAP_BASE+0xC8))
+#define PMIC_WRAP_INT1_FLG ((UINT32P)(PWRAP_BASE+0xCC))
+#define PMIC_WRAP_INT1_CLR ((UINT32P)(PWRAP_BASE+0xD0))
+#define PMIC_WRAP_SIG_ADR ((UINT32P)(PWRAP_BASE+0xD4))
+#define PMIC_WRAP_SIG_MODE ((UINT32P)(PWRAP_BASE+0xD8))
+#define PMIC_WRAP_SIG_VALUE ((UINT32P)(PWRAP_BASE+0xDC))
+#define PMIC_WRAP_SIG_ERRVAL ((UINT32P)(PWRAP_BASE+0xE0))
+#define PMIC_WRAP_CRC_EN ((UINT32P)(PWRAP_BASE+0xE4))
+#define PMIC_WRAP_TIMER_CTRL ((UINT32P)(PWRAP_BASE+0xE8))
+#define PMIC_WRAP_TIMER_STA ((UINT32P)(PWRAP_BASE+0xEC))
+#define PMIC_WRAP_WDT_UNIT ((UINT32P)(PWRAP_BASE+0xF0))
+#define PMIC_WRAP_WDT_SRC_EN_0 ((UINT32P)(PWRAP_BASE+0xF4))
+#define PMIC_WRAP_WDT_SRC_EN_1 ((UINT32P)(PWRAP_BASE+0xF8))
+#define PMIC_WRAP_WDT_FLG_0 ((UINT32P)(PWRAP_BASE+0xFC))
+#define PMIC_WRAP_WDT_FLG_1 ((UINT32P)(PWRAP_BASE+0x100))
+#define PMIC_WRAP_DEBUG_INT_SEL ((UINT32P)(PWRAP_BASE+0x104))
+#define PMIC_WRAP_DVFS_ADR0 ((UINT32P)(PWRAP_BASE+0x108))
+#define PMIC_WRAP_DVFS_WDATA0 ((UINT32P)(PWRAP_BASE+0x10C))
+#define PMIC_WRAP_DVFS_ADR1 ((UINT32P)(PWRAP_BASE+0x110))
+#define PMIC_WRAP_DVFS_WDATA1 ((UINT32P)(PWRAP_BASE+0x114))
+#define PMIC_WRAP_DVFS_ADR2 ((UINT32P)(PWRAP_BASE+0x118))
+#define PMIC_WRAP_DVFS_WDATA2 ((UINT32P)(PWRAP_BASE+0x11C))
+#define PMIC_WRAP_DVFS_ADR3 ((UINT32P)(PWRAP_BASE+0x120))
+#define PMIC_WRAP_DVFS_WDATA3 ((UINT32P)(PWRAP_BASE+0x124))
+#define PMIC_WRAP_DVFS_ADR4 ((UINT32P)(PWRAP_BASE+0x128))
+#define PMIC_WRAP_DVFS_WDATA4 ((UINT32P)(PWRAP_BASE+0x12C))
+#define PMIC_WRAP_DVFS_ADR5 ((UINT32P)(PWRAP_BASE+0x130))
+#define PMIC_WRAP_DVFS_WDATA5 ((UINT32P)(PWRAP_BASE+0x134))
+#define PMIC_WRAP_DVFS_ADR6 ((UINT32P)(PWRAP_BASE+0x138))
+#define PMIC_WRAP_DVFS_WDATA6 ((UINT32P)(PWRAP_BASE+0x13C))
+#define PMIC_WRAP_DVFS_ADR7 ((UINT32P)(PWRAP_BASE+0x140))
+#define PMIC_WRAP_DVFS_WDATA7 ((UINT32P)(PWRAP_BASE+0x144))
+#define PMIC_WRAP_DVFS_ADR8 ((UINT32P)(PWRAP_BASE+0x148))
+#define PMIC_WRAP_DVFS_WDATA8 ((UINT32P)(PWRAP_BASE+0x14C))
+#define PMIC_WRAP_DVFS_ADR9 ((UINT32P)(PWRAP_BASE+0x150))
+#define PMIC_WRAP_DVFS_WDATA9 ((UINT32P)(PWRAP_BASE+0x154))
+#define PMIC_WRAP_DVFS_ADR10 ((UINT32P)(PWRAP_BASE+0x158))
+#define PMIC_WRAP_DVFS_WDATA10 ((UINT32P)(PWRAP_BASE+0x15C))
+#define PMIC_WRAP_DVFS_ADR11 ((UINT32P)(PWRAP_BASE+0x160))
+#define PMIC_WRAP_DVFS_WDATA11 ((UINT32P)(PWRAP_BASE+0x164))
+#define PMIC_WRAP_DVFS_ADR12 ((UINT32P)(PWRAP_BASE+0x168))
+#define PMIC_WRAP_DVFS_WDATA12 ((UINT32P)(PWRAP_BASE+0x16C))
+#define PMIC_WRAP_DVFS_ADR13 ((UINT32P)(PWRAP_BASE+0x170))
+#define PMIC_WRAP_DVFS_WDATA13 ((UINT32P)(PWRAP_BASE+0x174))
+#define PMIC_WRAP_DVFS_ADR14 ((UINT32P)(PWRAP_BASE+0x178))
+#define PMIC_WRAP_DVFS_WDATA14 ((UINT32P)(PWRAP_BASE+0x17C))
+#define PMIC_WRAP_DVFS_ADR15 ((UINT32P)(PWRAP_BASE+0x180))
+#define PMIC_WRAP_DVFS_WDATA15 ((UINT32P)(PWRAP_BASE+0x184))
+#define PMIC_WRAP_DCXO_ENABLE ((UINT32P)(PWRAP_BASE+0x188))
+#define PMIC_WRAP_DCXO_CONN_ADR0 ((UINT32P)(PWRAP_BASE+0x18C))
+#define PMIC_WRAP_DCXO_CONN_WDATA0 ((UINT32P)(PWRAP_BASE+0x190))
+#define PMIC_WRAP_DCXO_CONN_ADR1 ((UINT32P)(PWRAP_BASE+0x194))
+#define PMIC_WRAP_DCXO_CONN_WDATA1 ((UINT32P)(PWRAP_BASE+0x198))
+#define PMIC_WRAP_DCXO_NFC_ADR0 ((UINT32P)(PWRAP_BASE+0x19C))
+#define PMIC_WRAP_DCXO_NFC_WDATA0 ((UINT32P)(PWRAP_BASE+0x1A0))
+#define PMIC_WRAP_DCXO_NFC_ADR1 ((UINT32P)(PWRAP_BASE+0x1A4))
+#define PMIC_WRAP_DCXO_NFC_WDATA1 ((UINT32P)(PWRAP_BASE+0x1A8))
+#define PMIC_WRAP_SPMINF_STA_0 ((UINT32P)(PWRAP_BASE+0x1AC))
+#define PMIC_WRAP_SPMINF_STA_1 ((UINT32P)(PWRAP_BASE+0x1B0))
+#define PMIC_WRAP_SPMINF_BACKUP_STA ((UINT32P)(PWRAP_BASE+0x1B4))
+#define PMIC_WRAP_MCU_PMINF_STA_0 ((UINT32P)(PWRAP_BASE+0x1B8))
+#define PMIC_WRAP_MCU_PMINF_STA_1 ((UINT32P)(PWRAP_BASE+0x1BC))
+#define PMIC_WRAP_SCPINF_STA ((UINT32P)(PWRAP_BASE+0x1C0))
+#define PMIC_WRAP_CIPHER_KEY_SEL ((UINT32P)(PWRAP_BASE+0x1C4))
+#define PMIC_WRAP_CIPHER_IV_SEL ((UINT32P)(PWRAP_BASE+0x1C8))
+#define PMIC_WRAP_CIPHER_EN ((UINT32P)(PWRAP_BASE+0x1CC))
+#define PMIC_WRAP_CIPHER_RDY ((UINT32P)(PWRAP_BASE+0x1D0))
+#define PMIC_WRAP_CIPHER_MODE ((UINT32P)(PWRAP_BASE+0x1D4))
+#define PMIC_WRAP_CIPHER_SWRST ((UINT32P)(PWRAP_BASE+0x1D8))
+#define PMIC_WRAP_DCM_EN ((UINT32P)(PWRAP_BASE+0x1DC))
+#define PMIC_WRAP_DCM_DBC_PRD ((UINT32P)(PWRAP_BASE+0x1E0))
+#define PMIC_WRAP_INT_GPS_AUXADC_CMD_ADDR ((UINT32P)(PWRAP_BASE+0x1E4))
+#define PMIC_WRAP_INT_GPS_AUXADC_CMD ((UINT32P)(PWRAP_BASE+0x1E8))
+#define PMIC_WRAP_INT_GPS_AUXADC_RDATA_ADDR ((UINT32P)(PWRAP_BASE+0x1EC))
+#define PMIC_WRAP_EXT_GPS_AUXADC_RDATA_ADDR ((UINT32P)(PWRAP_BASE+0x1F0))
+#define PMIC_WRAP_GPSINF_0_STA ((UINT32P)(PWRAP_BASE+0x1F4))
+#define PMIC_WRAP_GPSINF_1_STA ((UINT32P)(PWRAP_BASE+0x1F8))
+#define PMIC_WRAP_MD_ADCINF_CTRL ((UINT32P)(PWRAP_BASE+0x1FC))
+#define PMIC_WRAP_MD_AUXADC_RDATA_LATEST_ADDR ((UINT32P)(PWRAP_BASE+0x200))
+#define PMIC_WRAP_MD_AUXADC_RDATA_WP_ADDR ((UINT32P)(PWRAP_BASE+0x204))
+#define PMIC_WRAP_MD_AUXADC_RDATA_0_ADDR ((UINT32P)(PWRAP_BASE+0x208))
+#define PMIC_WRAP_MD_AUXADC_RDATA_1_ADDR ((UINT32P)(PWRAP_BASE+0x20C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_2_ADDR ((UINT32P)(PWRAP_BASE+0x210))
+#define PMIC_WRAP_MD_AUXADC_RDATA_3_ADDR ((UINT32P)(PWRAP_BASE+0x214))
+#define PMIC_WRAP_MD_AUXADC_RDATA_4_ADDR ((UINT32P)(PWRAP_BASE+0x218))
+#define PMIC_WRAP_MD_AUXADC_RDATA_5_ADDR ((UINT32P)(PWRAP_BASE+0x21C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_6_ADDR ((UINT32P)(PWRAP_BASE+0x220))
+#define PMIC_WRAP_MD_AUXADC_RDATA_7_ADDR ((UINT32P)(PWRAP_BASE+0x224))
+#define PMIC_WRAP_MD_AUXADC_RDATA_8_ADDR ((UINT32P)(PWRAP_BASE+0x228))
+#define PMIC_WRAP_MD_AUXADC_RDATA_9_ADDR ((UINT32P)(PWRAP_BASE+0x22C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_10_ADDR ((UINT32P)(PWRAP_BASE+0x230))
+#define PMIC_WRAP_MD_AUXADC_RDATA_11_ADDR ((UINT32P)(PWRAP_BASE+0x234))
+#define PMIC_WRAP_MD_AUXADC_RDATA_12_ADDR ((UINT32P)(PWRAP_BASE+0x238))
+#define PMIC_WRAP_MD_AUXADC_RDATA_13_ADDR ((UINT32P)(PWRAP_BASE+0x23C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_14_ADDR ((UINT32P)(PWRAP_BASE+0x240))
+#define PMIC_WRAP_MD_AUXADC_RDATA_15_ADDR ((UINT32P)(PWRAP_BASE+0x244))
+#define PMIC_WRAP_MD_AUXADC_RDATA_16_ADDR ((UINT32P)(PWRAP_BASE+0x248))
+#define PMIC_WRAP_MD_AUXADC_RDATA_17_ADDR ((UINT32P)(PWRAP_BASE+0x24C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_18_ADDR ((UINT32P)(PWRAP_BASE+0x250))
+#define PMIC_WRAP_MD_AUXADC_RDATA_19_ADDR ((UINT32P)(PWRAP_BASE+0x254))
+#define PMIC_WRAP_MD_AUXADC_RDATA_20_ADDR ((UINT32P)(PWRAP_BASE+0x258))
+#define PMIC_WRAP_MD_AUXADC_RDATA_21_ADDR ((UINT32P)(PWRAP_BASE+0x25C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_22_ADDR ((UINT32P)(PWRAP_BASE+0x260))
+#define PMIC_WRAP_MD_AUXADC_RDATA_23_ADDR ((UINT32P)(PWRAP_BASE+0x264))
+#define PMIC_WRAP_MD_AUXADC_RDATA_24_ADDR ((UINT32P)(PWRAP_BASE+0x268))
+#define PMIC_WRAP_MD_AUXADC_RDATA_25_ADDR ((UINT32P)(PWRAP_BASE+0x26C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_26_ADDR ((UINT32P)(PWRAP_BASE+0x270))
+#define PMIC_WRAP_MD_AUXADC_RDATA_27_ADDR ((UINT32P)(PWRAP_BASE+0x274))
+#define PMIC_WRAP_MD_AUXADC_RDATA_28_ADDR ((UINT32P)(PWRAP_BASE+0x278))
+#define PMIC_WRAP_MD_AUXADC_RDATA_29_ADDR ((UINT32P)(PWRAP_BASE+0x27C))
+#define PMIC_WRAP_MD_AUXADC_RDATA_30_ADDR ((UINT32P)(PWRAP_BASE+0x280))
+#define PMIC_WRAP_MD_AUXADC_RDATA_31_ADDR ((UINT32P)(PWRAP_BASE+0x284))
+#define PMIC_WRAP_MD_ADCINF_0_STA_0 ((UINT32P)(PWRAP_BASE+0x288))
+#define PMIC_WRAP_MD_ADCINF_0_STA_1 ((UINT32P)(PWRAP_BASE+0x28C))
+#define PMIC_WRAP_MD_ADCINF_1_STA_0 ((UINT32P)(PWRAP_BASE+0x290))
+#define PMIC_WRAP_MD_ADCINF_1_STA_1 ((UINT32P)(PWRAP_BASE+0x294))
+#define PMIC_WRAP_SWRST ((UINT32P)(PWRAP_BASE+0x298))
+#define PMIC_WRAP_SLEEP_PROTECTION_CTRL ((UINT32P)(PWRAP_BASE+0x29C))
+#define PMIC_WRAP_SPM_SLEEP_GATING_CTRL ((UINT32P)(PWRAP_BASE+0x2A0))
+#define PMIC_WRAP_SCP_SLEEP_GATING_CTRL ((UINT32P)(PWRAP_BASE+0x2A4))
+#define PMIC_WRAP_PRIORITY_USER_SEL_0 ((UINT32P)(PWRAP_BASE+0x2A8))
+#define PMIC_WRAP_PRIORITY_USER_SEL_1 ((UINT32P)(PWRAP_BASE+0x2AC))
+#define PMIC_WRAP_PRIORITY_USER_SEL_2 ((UINT32P)(PWRAP_BASE+0x2B0))
+#define PMIC_WRAP_PRIORITY_USER_SEL_3 ((UINT32P)(PWRAP_BASE+0x2B4))
+#define PMIC_WRAP_PRIORITY_USER_SEL_4 ((UINT32P)(PWRAP_BASE+0x2B8))
+#define PMIC_WRAP_ARBITER_OUT_SEL_0 ((UINT32P)(PWRAP_BASE+0x2BC))
+#define PMIC_WRAP_ARBITER_OUT_SEL_1 ((UINT32P)(PWRAP_BASE+0x2C0))
+#define PMIC_WRAP_ARBITER_OUT_SEL_2 ((UINT32P)(PWRAP_BASE+0x2C4))
+#define PMIC_WRAP_ARBITER_OUT_SEL_3 ((UINT32P)(PWRAP_BASE+0x2C8))
+#define PMIC_WRAP_ARBITER_OUT_SEL_4 ((UINT32P)(PWRAP_BASE+0x2CC))
+#define PMIC_WRAP_STARV_COUNTER_0 ((UINT32P)(PWRAP_BASE+0x2D0))
+#define PMIC_WRAP_STARV_COUNTER_1 ((UINT32P)(PWRAP_BASE+0x2D4))
+#define PMIC_WRAP_STARV_COUNTER_2 ((UINT32P)(PWRAP_BASE+0x2D8))
+#define PMIC_WRAP_STARV_COUNTER_3 ((UINT32P)(PWRAP_BASE+0x2DC))
+#define PMIC_WRAP_STARV_COUNTER_4 ((UINT32P)(PWRAP_BASE+0x2E0))
+#define PMIC_WRAP_STARV_COUNTER_5 ((UINT32P)(PWRAP_BASE+0x2E4))
+#define PMIC_WRAP_STARV_COUNTER_6 ((UINT32P)(PWRAP_BASE+0x2E8))
+#define PMIC_WRAP_STARV_COUNTER_7 ((UINT32P)(PWRAP_BASE+0x2EC))
+#define PMIC_WRAP_STARV_COUNTER_8 ((UINT32P)(PWRAP_BASE+0x2F0))
+#define PMIC_WRAP_STARV_COUNTER_9 ((UINT32P)(PWRAP_BASE+0x2F4))
+#define PMIC_WRAP_STARV_COUNTER_10 ((UINT32P)(PWRAP_BASE+0x2F8))
+#define PMIC_WRAP_STARV_COUNTER_11 ((UINT32P)(PWRAP_BASE+0x2FC))
+#define PMIC_WRAP_STARV_COUNTER_12 ((UINT32P)(PWRAP_BASE+0x300))
+#define PMIC_WRAP_STARV_COUNTER_13 ((UINT32P)(PWRAP_BASE+0x304))
+#define PMIC_WRAP_STARV_COUNTER_14 ((UINT32P)(PWRAP_BASE+0x308))
+#define PMIC_WRAP_STARV_COUNTER_15 ((UINT32P)(PWRAP_BASE+0x30C))
+#define PMIC_WRAP_STARV_COUNTER_16 ((UINT32P)(PWRAP_BASE+0x310))
+#define PMIC_WRAP_STARV_INT_EN ((UINT32P)(PWRAP_BASE+0x314))
+#define PMIC_WRAP_STARV_COUNTER_0_STATUS ((UINT32P)(PWRAP_BASE+0x318))
+#define PMIC_WRAP_STARV_COUNTER_1_STATUS ((UINT32P)(PWRAP_BASE+0x31C))
+#define PMIC_WRAP_STARV_COUNTER_2_STATUS ((UINT32P)(PWRAP_BASE+0x320))
+#define PMIC_WRAP_STARV_COUNTER_3_STATUS ((UINT32P)(PWRAP_BASE+0x324))
+#define PMIC_WRAP_STARV_COUNTER_4_STATUS ((UINT32P)(PWRAP_BASE+0x328))
+#define PMIC_WRAP_STARV_COUNTER_5_STATUS ((UINT32P)(PWRAP_BASE+0x32C))
+#define PMIC_WRAP_STARV_COUNTER_6_STATUS ((UINT32P)(PWRAP_BASE+0x330))
+#define PMIC_WRAP_STARV_COUNTER_7_STATUS ((UINT32P)(PWRAP_BASE+0x334))
+#define PMIC_WRAP_STARV_COUNTER_8_STATUS ((UINT32P)(PWRAP_BASE+0x338))
+#define PMIC_WRAP_STARV_COUNTER_9_STATUS ((UINT32P)(PWRAP_BASE+0x33C))
+#define PMIC_WRAP_STARV_COUNTER_10_STATUS ((UINT32P)(PWRAP_BASE+0x340))
+#define PMIC_WRAP_STARV_COUNTER_11_STATUS ((UINT32P)(PWRAP_BASE+0x344))
+#define PMIC_WRAP_STARV_COUNTER_12_STATUS ((UINT32P)(PWRAP_BASE+0x348))
+#define PMIC_WRAP_STARV_COUNTER_13_STATUS ((UINT32P)(PWRAP_BASE+0x34C))
+#define PMIC_WRAP_STARV_COUNTER_14_STATUS ((UINT32P)(PWRAP_BASE+0x350))
+#define PMIC_WRAP_STARV_COUNTER_15_STATUS ((UINT32P)(PWRAP_BASE+0x354))
+#define PMIC_WRAP_STARV_COUNTER_16_STATUS ((UINT32P)(PWRAP_BASE+0x358))
+#define PMIC_WRAP_STARV_COUNTER_CLR ((UINT32P)(PWRAP_BASE+0x35C))
+#define PMIC_WRAP_STARV_PRIO_STATUS ((UINT32P)(PWRAP_BASE+0x360))
+#define PMIC_WRAP_MONITOR_CTRL_0 ((UINT32P)(PWRAP_BASE+0x364))
+#define PMIC_WRAP_MONITOR_CTRL_1 ((UINT32P)(PWRAP_BASE+0x368))
+#define PMIC_WRAP_MONITOR_CTRL_2 ((UINT32P)(PWRAP_BASE+0x36C))
+#define PMIC_WRAP_MONITOR_CTRL_3 ((UINT32P)(PWRAP_BASE+0x370))
+#define PMIC_WRAP_CHANNEL_SEQUENCE_0 ((UINT32P)(PWRAP_BASE+0x374))
+#define PMIC_WRAP_CHANNEL_SEQUENCE_1 ((UINT32P)(PWRAP_BASE+0x378))
+#define PMIC_WRAP_CHANNEL_SEQUENCE_2 ((UINT32P)(PWRAP_BASE+0x37C))
+#define PMIC_WRAP_CHANNEL_SEQUENCE_3 ((UINT32P)(PWRAP_BASE+0x380))
+#define PMIC_WRAP_CMD_SEQUENCE_0 ((UINT32P)(PWRAP_BASE+0x384))
+#define PMIC_WRAP_CMD_SEQUENCE_1 ((UINT32P)(PWRAP_BASE+0x388))
+#define PMIC_WRAP_CMD_SEQUENCE_2 ((UINT32P)(PWRAP_BASE+0x38C))
+#define PMIC_WRAP_CMD_SEQUENCE_3 ((UINT32P)(PWRAP_BASE+0x390))
+#define PMIC_WRAP_CMD_SEQUENCE_4 ((UINT32P)(PWRAP_BASE+0x394))
+#define PMIC_WRAP_CMD_SEQUENCE_5 ((UINT32P)(PWRAP_BASE+0x398))
+#define PMIC_WRAP_CMD_SEQUENCE_6 ((UINT32P)(PWRAP_BASE+0x39C))
+#define PMIC_WRAP_CMD_SEQUENCE_7 ((UINT32P)(PWRAP_BASE+0x3A0))
+#define PMIC_WRAP_WDATA_SEQUENCE_0 ((UINT32P)(PWRAP_BASE+0x3A4))
+#define PMIC_WRAP_WDATA_SEQUENCE_1 ((UINT32P)(PWRAP_BASE+0x3A8))
+#define PMIC_WRAP_WDATA_SEQUENCE_2 ((UINT32P)(PWRAP_BASE+0x3AC))
+#define PMIC_WRAP_WDATA_SEQUENCE_3 ((UINT32P)(PWRAP_BASE+0x3B0))
+#define PMIC_WRAP_WDATA_SEQUENCE_4 ((UINT32P)(PWRAP_BASE+0x3B4))
+#define PMIC_WRAP_WDATA_SEQUENCE_5 ((UINT32P)(PWRAP_BASE+0x3B8))
+#define PMIC_WRAP_WDATA_SEQUENCE_6 ((UINT32P)(PWRAP_BASE+0x3BC))
+#define PMIC_WRAP_WDATA_SEQUENCE_7 ((UINT32P)(PWRAP_BASE+0x3C0))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_0 ((UINT32P)(PWRAP_BASE+0x3C4))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_1 ((UINT32P)(PWRAP_BASE+0x3C8))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_2 ((UINT32P)(PWRAP_BASE+0x3CC))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_3 ((UINT32P)(PWRAP_BASE+0x3D0))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_4 ((UINT32P)(PWRAP_BASE+0x3D4))
+#define PMIC_WRAP_DEBUG_REG_FOR_SW_5 ((UINT32P)(PWRAP_BASE+0x3D8))
+#define PMIC_WRAP_BWC_OPTIONS ((UINT32P)(PWRAP_BASE+0x3DC))
+#define PMIC_WRAP_RESERVED ((UINT32P)(PWRAP_BASE+0x3E0))
+#define PMIC_WRAP_WACS0_CMD ((UINT32P)(PWRAP_BASE+0xC00))
+#define PMIC_WRAP_WACS0_RDATA ((UINT32P)(PWRAP_BASE+0xC04))
+#define PMIC_WRAP_WACS0_VLDCLR ((UINT32P)(PWRAP_BASE+0xC08))
+#define PMIC_WRAP_WACS1_CMD ((UINT32P)(PWRAP_BASE+0xC10))
+#define PMIC_WRAP_WACS1_RDATA ((UINT32P)(PWRAP_BASE+0xC14))
+#define PMIC_WRAP_WACS1_VLDCLR ((UINT32P)(PWRAP_BASE+0xC18))
+#define PMIC_WRAP_WACS2_CMD ((UINT32P)(PWRAP_BASE+0xC20))
+#define PMIC_WRAP_WACS2_RDATA ((UINT32P)(PWRAP_BASE+0xC24))
+#define PMIC_WRAP_WACS2_VLDCLR ((UINT32P)(PWRAP_BASE+0xC28))
+#define PMIC_WRAP_WACS3_CMD ((UINT32P)(PWRAP_BASE+0xC30))
+#define PMIC_WRAP_WACS3_RDATA ((UINT32P)(PWRAP_BASE+0xC34))
+#define PMIC_WRAP_WACS3_VLDCLR ((UINT32P)(PWRAP_BASE+0xC38))
+#define PMIC_WRAP_MD_AUXADC_READY_CHECK ((UINT32P)(PWRAP_BASE+0xC40))
+#define PMIC_WRAP_WACS3_EN ((UINT32P)(PWRAP_BASE+0xC44))
+#define PMIC_WRAP_INIT_DONE3 ((UINT32P)(PWRAP_BASE+0xC48))
+
+/* APB Module pmic_wrap_mpu */
+#define PMIC_WRAP_MPU_CON0 ((UINT32P)(PWRAP_BASE+0xF00))
+#define PMIC_WRAP_MPU_CON1 ((UINT32P)(PWRAP_BASE+0xF04))
+#define PMIC_WRAP_MPU_PMIC_RGN_EN ((UINT32P)(PWRAP_BASE+0xF08))
+#define PMIC_WRAP_MPU_PMIC_RGN0 ((UINT32P)(PWRAP_BASE+0xF0C))
+#define PMIC_WRAP_MPU_PMIC_RGN1 ((UINT32P)(PWRAP_BASE+0xF10))
+#define PMIC_WRAP_MPU_PMIC_RGN2 ((UINT32P)(PWRAP_BASE+0xF14))
+#define PMIC_WRAP_MPU_PMIC_RGN3 ((UINT32P)(PWRAP_BASE+0xF18))
+#define PMIC_WRAP_MPU_PMIC_RGN0_PER ((UINT32P)(PWRAP_BASE+0xF1C))
+#define PMIC_WRAP_MPU_PMIC_RGN1_PER ((UINT32P)(PWRAP_BASE+0xF20))
+#define PMIC_WRAP_MPU_PMIC_RGN2_PER ((UINT32P)(PWRAP_BASE+0xF24))
+#define PMIC_WRAP_MPU_PMIC_RGN3_PER ((UINT32P)(PWRAP_BASE+0xF28))
+#define PMIC_WRAP_MPU_PMIC_OTHERS_PER ((UINT32P)(PWRAP_BASE+0xF2C))
+#define PMIC_WRAP_MPU_PWRAP_WACS0_PER ((UINT32P)(PWRAP_BASE+0xF30))
+#define PMIC_WRAP_MPU_PWRAP_WACS1_PER ((UINT32P)(PWRAP_BASE+0xF34))
+#define PMIC_WRAP_MPU_PWRAP_WACS2_PER ((UINT32P)(PWRAP_BASE+0xF38))
+#define PMIC_WRAP_MPU_PWRAP_WACS3_PER ((UINT32P)(PWRAP_BASE+0xF3C))
+#define PMIC_WRAP_MPU_PWRAP_OTHERS_PER ((UINT32P)(PWRAP_BASE+0xF40))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_INFO_0 ((UINT32P)(PWRAP_BASE+0xF44))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_INFO_1 ((UINT32P)(PWRAP_BASE+0xF48))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_INFO_2 ((UINT32P)(PWRAP_BASE+0xF4C))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0 ((UINT32P)(PWRAP_BASE+0xF50))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1 ((UINT32P)(PWRAP_BASE+0xF54))
+#define PMIC_WRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2 ((UINT32P)(PWRAP_BASE+0xF58))
+#define PMIC_WRAP_MPU_PWRAP_ACC_VIO_INFO_0 ((UINT32P)(PWRAP_BASE+0xF5C))
+#define PMIC_WRAP_MPU_PWRAP_ACC_VIO_INFO_1 ((UINT32P)(PWRAP_BASE+0xF60))
+
+#endif /*__PMIC_WRAP_REGS_H__*/
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP_mac.h b/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP_mac.h
new file mode 100644
index 0000000..2e9e7c9
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/reg_PMIC_WRAP_mac.h
@@ -0,0 +1,713 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __PMIC_WRAP_REGS_HMAC__
+#define __PMIC_WRAP_REGS_HMAC__
+
+#define GET_MUX_SEL(x) ((x>>0) & 0x00000001)
+#define GET_WRAP_EN(x) ((x>>0) & 0x00000001)
+#define GET_DIO_EN0(x) ((x>>0) & 0x00000001)
+#define GET_DIO_EN1(x) ((x>>1) & 0x00000001)
+#define GET_PMIC_0_SI_DLY_SEL(x) ((x>>0) & 0x0000001f)
+#define GET_PMIC_0_SI_CK_SEL(x) ((x>>5) & 0x00000001)
+#define GET_PMIC_0_SI_EN_SEL(x) ((x>>6) & 0x00000007)
+#define GET_PMIC_1_SI_DLY_SEL(x) ((x>>9) & 0x0000001f)
+#define GET_PMIC_1_SI_CK_SEL(x) ((x>>14) & 0x00000001)
+#define GET_PMIC_1_SI_EN_SEL(x) ((x>>15) & 0x00000007)
+#define GET_DUAL_PMIC_SI_SAMPLE_CTRL_EN(x) ((x>>18) & 0x00000001)
+#define GET_SI_SAMPLING_USING_LOCAL_SI_CK(x) ((x>>19) & 0x00000001)
+#define GET_PMIC_0_SI_DLY_SEL_1(x) ((x>>0) & 0x0000001f)
+#define GET_PMIC_0_SI_CK_SEL_1(x) ((x>>5) & 0x00000001)
+#define GET_PMIC_0_SI_EN_SEL_1(x) ((x>>6) & 0x00000007)
+#define GET_PMIC_1_SI_DLY_SEL_1(x) ((x>>9) & 0x0000001f)
+#define GET_PMIC_1_SI_CK_SEL_1(x) ((x>>14) & 0x00000001)
+#define GET_PMIC_1_SI_EN_SEL_1(x) ((x>>15) & 0x00000007)
+#define GET_DUAL_PMIC_SI_SAMPLE_CTRL_1_EN(x) ((x>>18) & 0x00000001)
+#define GET_SI_SAMPLE_CTRL_1_EN(x) ((x>>19) & 0x00000001)
+#define GET_PMIC_0_SI_DLY_SEL_2(x) ((x>>0) & 0x0000001f)
+#define GET_PMIC_0_SI_CK_SEL_2(x) ((x>>5) & 0x00000001)
+#define GET_PMIC_0_SI_EN_SEL_2(x) ((x>>6) & 0x00000007)
+#define GET_PMIC_1_SI_DLY_SEL_2(x) ((x>>9) & 0x0000001f)
+#define GET_PMIC_1_SI_CK_SEL_2(x) ((x>>14) & 0x00000001)
+#define GET_PMIC_1_SI_EN_SEL_2(x) ((x>>15) & 0x00000007)
+#define GET_DUAL_PMIC_SI_SAMPLE_CTRL_2_EN(x) ((x>>18) & 0x00000001)
+#define GET_SI_SAMPLE_CTRL_2_EN(x) ((x>>19) & 0x00000001)
+#define GET_PMIC_0_SI_DLY_SEL_3(x) ((x>>0) & 0x0000001f)
+#define GET_PMIC_0_SI_CK_SEL_3(x) ((x>>5) & 0x00000001)
+#define GET_PMIC_0_SI_EN_SEL_3(x) ((x>>6) & 0x00000007)
+#define GET_PMIC_1_SI_DLY_SEL_3(x) ((x>>9) & 0x0000001f)
+#define GET_PMIC_1_SI_CK_SEL_3(x) ((x>>14) & 0x00000001)
+#define GET_PMIC_1_SI_EN_SEL_3(x) ((x>>15) & 0x00000007)
+#define GET_DUAL_PMIC_SI_SAMPLE_CTRL_3_EN(x) ((x>>18) & 0x00000001)
+#define GET_SI_SAMPLE_CTRL_3_EN(x) ((x>>19) & 0x00000001)
+#define GET_PMIC_0_SI_DLY_SEL_ULPOSC(x) ((x>>0) & 0x0000001f)
+#define GET_PMIC_0_SI_CK_SEL_ULPOSC(x) ((x>>5) & 0x00000001)
+#define GET_PMIC_0_SI_EN_SEL_ULPOSC(x) ((x>>6) & 0x00000007)
+#define GET_PMIC_1_SI_DLY_SEL_ULPOSC(x) ((x>>9) & 0x0000001f)
+#define GET_PMIC_1_SI_CK_SEL_ULPOSC(x) ((x>>14) & 0x00000001)
+#define GET_PMIC_1_SI_EN_SEL_ULPOSC(x) ((x>>15) & 0x00000007)
+#define GET_DUAL_PMIC_SI_SAMPLE_CTRL_ULPOSC_EN(x) ((x>>18) & 0x00000001)
+#define GET_SI_SAMPLE_CTRL_ULPOSC_EN(x) ((x>>19) & 0x00000001)
+#define GET_RDDMY0(x) ((x>>0) & 0x000000ff)
+#define GET_RDDMY1(x) ((x>>8) & 0x000000ff)
+#define GET_CSHEXT_WRITE_START(x) ((x>>0) & 0x000000ff)
+#define GET_CSHEXT_WRITE_END(x) ((x>>8) & 0x000000ff)
+#define GET_CSHEXT_READ_START(x) ((x>>0) & 0x000000ff)
+#define GET_CSHEXT_READ_END(x) ((x>>8) & 0x000000ff)
+#define GET_CSLEXT_WRITE_START(x) ((x>>0) & 0x000000ff)
+#define GET_CSLEXT_WRITE_END(x) ((x>>8) & 0x000000ff)
+#define GET_CSLEXT_READ_START(x) ((x>>0) & 0x000000ff)
+#define GET_CSLEXT_READ_END(x) ((x>>8) & 0x000000ff)
+#define GET_EXT_CK_WRITE(x) ((x>>0) & 0x000000ff)
+#define GET_EXT_CK_READ(x) ((x>>0) & 0x000000ff)
+#define GET_STAUPD_PRD(x) ((x>>0) & 0x0000000f)
+#define GET_STAUPD_FETCH_ALL(x) ((x>>4) & 0x00000001)
+#define GET_STAUPD_GRPEN(x) ((x>>0) & 0x000001ff)
+#define GET_EINT_STA0_ADR(x) ((x>>0) & 0x0000ffff)
+#define GET_EINT_STA1_ADR(x) ((x>>0) & 0x0000ffff)
+#define GET_EINT_STA(x) ((x>>0) & 0x0000000f)
+#define GET_EINT_CLR(x) ((x>>0) & 0x0000000f)
+#define GET_VALID_SRCLK_EN_CTRL(x) ((x>>0) & 0x00000001)
+#define GET_VALID_SRVOL_EN_CTRL(x) ((x>>1) & 0x00000001)
+#define GET_SPI_IO_MODE_CTRL(x) ((x>>2) & 0x0000000f)
+#define GET_HARB_SPI_EINT_MODE_GATING(x) ((x>>6) & 0x00000001)
+#define GET_PMIC_EINT_OUT_0_SRC_SEL_NORMAL(x) ((x>>7) & 0x00000003)
+#define GET_PMIC_EINT_OUT_0_SRC_SEL_SLEEP(x) ((x>>9) & 0x00000001)
+#define GET_PMIC_EINT_OUT_1_SRC_SEL_NORMAL(x) ((x>>10) & 0x00000003)
+#define GET_PMIC_EINT_OUT_1_SRC_SEL_SLEEP(x) ((x>>12) & 0x00000001)
+#define GET_PMIC_EINT_SCP_SRC_SEL_NORMAL(x) ((x>>13) & 0x00000003)
+#define GET_PMIC_EINT_SCP_SRC_SEL_SLEEP(x) ((x>>15) & 0x00000001)
+#define GET_SPM_PMIC_EINT_ACK_STAUPD_NO_SEL(x) ((x>>16) & 0x0000000f)
+#define GET_STAUPD_MAN_TRIG(x) ((x>>0) & 0x00000001)
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x0000000f)
+#define GET_STAUPD_ALE_CNT(x) ((x>>4) & 0x0000000f)
+#define GET_GRP_REQ_PENDING(x) ((x>>8) & 0x000001ff)
+#define GET_GRP_DATA_PENDING(x) ((x>>17) & 0x000001ff)
+#define GET_STAUPD_FSM(x) ((x>>26) & 0x00000007)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_INIT(x) ((x>>0) & 0x00000001)
+#define GET_HARB_HPRIO(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_HARB_EN(x) ((x>>0) & 0x00000001)
+#define GET_WACS1_HARB_EN(x) ((x>>1) & 0x00000001)
+#define GET_WACS2_HARB_EN(x) ((x>>2) & 0x00000001)
+#define GET_WACS_P2P_HARB_EN(x) ((x>>3) & 0x00000001)
+#define GET_WACS_MD32_HARB_EN(x) ((x>>4) & 0x00000001)
+#define GET_MDINF_HARB_EN(x) ((x>>5) & 0x00000001)
+#define GET_C2KINF_HARB_EN(x) ((x>>6) & 0x00000001)
+#define GET_MD_DVFSINF_HARB_EN(x) ((x>>7) & 0x00000001)
+#define GET_SPMINF_HARB_EN(x) ((x>>8) & 0x00000001)
+#define GET_SPMINF_BACKUP_HARB_EN(x) ((x>>9) & 0x00000001)
+#define GET_DCXO_CONNINF_HARB_EN(x) ((x>>10) & 0x00000001)
+#define GET_DCXO_NFCINF_HARB_EN(x) ((x>>11) & 0x00000001)
+#define GET_MCU_PMINF_HARB_EN(x) ((x>>12) & 0x00000001)
+#define GET_MD_ADCINF_0_HARB_EN(x) ((x>>13) & 0x00000001)
+#define GET_MD_ADCINF_1_HARB_EN(x) ((x>>14) & 0x00000001)
+#define GET_GPSINF_0_HARB_EN(x) ((x>>15) & 0x00000001)
+#define GET_GPSINF_1_HARB_EN(x) ((x>>16) & 0x00000001)
+#define GET_STAUPD_HARB_EN(x) ((x>>17) & 0x00000001)
+#define GET_WACS3_HARB_EN(x) ((x>>18) & 0x00000001)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_W(x) ((x>>31) & 0x00000001)
+#define GET_AG_HARB_REQ(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x0000000f)
+#define GET_HARB_OWN(x) ((x>>7) & 0x0000000f)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>11) & 0x0000000f)
+#define GET_MAN_EN(x) ((x>>0) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_MAN_VLDCLR(x) ((x>>0) & 0x00000001)
+#define GET_WACS0_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>0) & 0x00000001)
+#define GET_WACS1_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>0) & 0x00000001)
+#define GET_WACS2_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>0) & 0x00000001)
+#define GET_WACS3_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE3(x) ((x>>0) & 0x00000001)
+#define GET_WACS_P2P_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE_P2P(x) ((x>>0) & 0x00000001)
+#define GET_WACS_MD32_EN(x) ((x>>0) & 0x00000001)
+#define GET_INIT_DONE_MD32(x) ((x>>0) & 0x00000001)
+#define GET_INT0_EN(x) ((x>>0) & 0x00000000)
+#define GET_INT0_FLG_RAW(x) ((x>>0) & 0x00000000)
+#define GET_INT0_FLG(x) ((x>>0) & 0x00000000)
+#define GET_INT0_CLR(x) ((x>>0) & 0x00000000)
+#define GET_INT1_EN(x) ((x>>0) & 0x00000000)
+#define GET_INT1_FLG_RAW(x) ((x>>0) & 0x00000000)
+#define GET_INT1_FLG(x) ((x>>0) & 0x00000000)
+#define GET_INT1_CLR(x) ((x>>0) & 0x00000000)
+#define GET_SIG_ADR0(x) ((x>>0) & 0x0000ffff)
+#define GET_SIG_ADR1(x) ((x>>16) & 0x0000ffff)
+#define GET_SIG_MODE0(x) ((x>>0) & 0x00000001)
+#define GET_SIG_MODE1(x) ((x>>1) & 0x00000001)
+#define GET_SIG_VALUE0(x) ((x>>0) & 0x0000ffff)
+#define GET_SIG_VALUE1(x) ((x>>16) & 0x0000ffff)
+#define GET_SIG_ERRVAL0(x) ((x>>0) & 0x0000ffff)
+#define GET_SIG_ERRVAL1(x) ((x>>16) & 0x0000ffff)
+#define GET_CRC_EN(x) ((x>>0) & 0x00000001)
+#define GET_TIMER_CLK_EN(x) ((x>>0) & 0x00000001)
+#define GET_TIMER_CLK_AUTO_GATING_EN(x) ((x>>1) & 0x00000001)
+#define GET_TIMER_CLK_AUTO_GATING_CTRL(x) ((x>>2) & 0x00000003)
+#define GET_STAUPD_TIMER_RESET(x) ((x>>4) & 0x00000001)
+#define GET_WDT_TIMER_RESET(x) ((x>>5) & 0x00000001)
+#define GET_STAUPD_TIMER(x) ((x>>0) & 0x00001fff)
+#define GET_WDT_TIMER(x) ((x>>16) & 0x0000ffff)
+#define GET_WDT_UNIT(x) ((x>>0) & 0x0000000f)
+#define GET_WDT_SRC_EN_0(x) ((x>>0) & 0x00000000)
+#define GET_WDT_SRC_EN_1(x) ((x>>0) & 0x00000000)
+#define GET_WDT_FLG_0(x) ((x>>0) & 0x00000000)
+#define GET_WDT_FLG_1(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_INT_SEL(x) ((x>>0) & 0x00000007)
+#define GET_DVFS_ADR0(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA0(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR1(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA1(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR2(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA2(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR3(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA3(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR4(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA4(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR5(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA5(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR6(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA6(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR7(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA7(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR8(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA8(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR9(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA9(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR10(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA10(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR11(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA11(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR12(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA12(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR13(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA13(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR14(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA14(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_ADR15(x) ((x>>0) & 0x0000ffff)
+#define GET_DVFS_WDATA15(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_NFC_ENABLE(x) ((x>>0) & 0x00000001)
+#define GET_DCXO_CONN_ENABLE(x) ((x>>1) & 0x00000001)
+#define GET_DCXO_CONN_ADR0(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_CONN_WDATA0(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_CONN_ADR1(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_CONN_WDATA1(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_NFC_ADR0(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_NFC_WDATA0(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_NFC_ADR1(x) ((x>>0) & 0x0000ffff)
+#define GET_DCXO_NFC_WDATA1(x) ((x>>0) & 0x0000ffff)
+#define GET_SPM_PWRAP_REQ(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_SPM_ACK(x) ((x>>1) & 0x00000001)
+#define GET_SPM_PMIC_EINT_REQ(x) ((x>>2) & 0x00000001)
+#define GET_SPM_PMIC_EINT_ACK(x) ((x>>3) & 0x00000001)
+#define GET_SPM_SLEEP_REQ(x) ((x>>4) & 0x00000001)
+#define GET_SPM_SLEEP_ACK(x) ((x>>5) & 0x00000001)
+#define GET_SPMINF_BUSY(x) ((x>>6) & 0x00000001)
+#define GET_SPM_PWRAP_ADR(x) ((x>>0) & 0x0000ffff)
+#define GET_SPM_PWRAP_WDATA(x) ((x>>16) & 0x0000ffff)
+#define GET_SPM_PWRAP_DVFS_CTRL_RDY(x) ((x>>0) & 0x00000001)
+#define GET_SPM_PWRAP_DVFS_CTRL(x) ((x>>1) & 0x0000000f)
+#define GET_PWRAP_SPM_DVFS_CTRL_ACK(x) ((x>>5) & 0x00000001)
+#define GET_SPMINF_BACKUP_BUSY(x) ((x>>6) & 0x00000001)
+#define GET_MCU_PM_PWRAP_REQ(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_MCU_PM_ACK(x) ((x>>1) & 0x00000001)
+#define GET_MCU_PMINF_BUSY(x) ((x>>2) & 0x00000001)
+#define GET_MCU_PM_PWRAP_ADR(x) ((x>>0) & 0x0000ffff)
+#define GET_MCU_PM_PWRAP_WDATA(x) ((x>>16) & 0x0000ffff)
+#define GET_SCP_SLEEP_REQ(x) ((x>>0) & 0x00000001)
+#define GET_SCP_SLEEP_ACK(x) ((x>>1) & 0x00000001)
+#define GET_PMIC_EINT_SCP(x) ((x>>2) & 0x00000001)
+#define GET_CIPHER_KEY_SEL(x) ((x>>0) & 0x00000003)
+#define GET_CIPHER_IV_SEL(x) ((x>>0) & 0x00000003)
+#define GET_CIPHER_EN(x) ((x>>0) & 0x00000001)
+#define GET_CIPHER_RDY(x) ((x>>0) & 0x00000003)
+#define GET_CIPHER_MODE(x) ((x>>0) & 0x00000001)
+#define GET_CIPHER_SWRST(x) ((x>>0) & 0x00000001)
+#define GET_SYS_CK_DCM_EN(x) ((x>>0) & 0x00000001)
+#define GET_SPI_CK_DCM_EN(x) ((x>>1) & 0x00000001)
+#define GET_PCLK_MPU_EXCEPT_DCM_EN(x) ((x>>2) & 0x00000001)
+#define GET_WACS_CK_DCM_EN(x) ((x>>3) & 0x00000001)
+#define GET_MDINF_CK_DCM_EN(x) ((x>>4) & 0x00000001)
+#define GET_C2KINF_CK_DCM_EN(x) ((x>>5) & 0x00000001)
+#define GET_MD_DVFSINF_CK_DCM_EN(x) ((x>>6) & 0x00000001)
+#define GET_SPMINF_CK_DCM_EN(x) ((x>>7) & 0x00000001)
+#define GET_SPMINF_BACKUP_CK_DCM_EN(x) ((x>>8) & 0x00000001)
+#define GET_DCXOINF_CK_DCM_EN(x) ((x>>9) & 0x00000001)
+#define GET_MCU_PMINF_CK_DCM_EN(x) ((x>>10) & 0x00000001)
+#define GET_MD_ADCINF_0_CK_DCM_EN(x) ((x>>11) & 0x00000001)
+#define GET_MD_ADCINF_1_CK_DCM_EN(x) ((x>>12) & 0x00000001)
+#define GET_GPSINF_0_CK_DCM_EN(x) ((x>>13) & 0x00000001)
+#define GET_GPSINF_1_CK_DCM_EN(x) ((x>>14) & 0x00000001)
+#define GET_MD32INF_CK_DCM_EN(x) ((x>>15) & 0x00000001)
+#define GET_STAUPD_CK_DCM_EN(x) ((x>>16) & 0x00000001)
+#define GET_ARBITER_CK_DCM_EN(x) ((x>>17) & 0x00000001)
+#define GET_CRC_CK_DCM_EN(x) ((x>>18) & 0x00000001)
+#define GET_INTCTL_CK_DCM_EN(x) ((x>>19) & 0x00000001)
+#define GET_WDTCTL_CK_DCM_EN(x) ((x>>20) & 0x00000001)
+#define GET_SPICTL_CK_DCM_EN(x) ((x>>21) & 0x00000001)
+#define GET_SYS_CK_DCM_DBC_PRD(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_CK_DCM_DBC_PRD(x) ((x>>8) & 0x000000ff)
+#define GET_INT_GPS_AUXADC_CMD_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_INT_GPS_AUXADC_CMD_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_INT_GPS_AUXADC_CMD_0(x) ((x>>0) & 0x0000ffff)
+#define GET_INT_GPS_AUXADC_CMD_1(x) ((x>>16) & 0x0000ffff)
+#define GET_INT_GPS_AUXADC_RDATA_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_INT_GPS_AUXADC_RDATA_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_EXT_GPS_AUXADC_RDATA_ADDR(x) ((x>>0) & 0x0000ffff)
+#define GET_GPS_PWRAP_REQ_0(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_GPS_ACK_0(x) ((x>>1) & 0x00000001)
+#define GET_PWRAP_GPS_RDATA_0(x) ((x>>2) & 0x00007fff)
+#define GET_PWRAP_GPS_RDATA_VALID_0(x) ((x>>17) & 0x00000001)
+#define GET_GPSINF_0_FSM(x) ((x>>18) & 0x00000007)
+#define GET_GPSINF_0_BUSY(x) ((x>>21) & 0x00000001)
+#define GET_GPS_PWRAP_REQ_1(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_GPS_ACK_1(x) ((x>>1) & 0x00000001)
+#define GET_PWRAP_GPS_RDATA_1(x) ((x>>2) & 0x00007fff)
+#define GET_PWRAP_GPS_RDATA_VALID_1(x) ((x>>17) & 0x00000001)
+#define GET_GPSINF_1_FSM(x) ((x>>18) & 0x00000007)
+#define GET_GPSINF_1_BUSY(x) ((x>>21) & 0x00000001)
+#define GET_MD_AUXADC_MODE_LATCH_SEL_0(x) ((x>>0) & 0x00000001)
+#define GET_MD_AUXADC_MODE_LATCH_SEL_1(x) ((x>>1) & 0x00000001)
+#define GET_MD_AUXADC_RDATA_LATEST_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_LATEST_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_WP_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_WP_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_0_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_0_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_1_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_1_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_2_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_2_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_3_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_3_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_4_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_4_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_5_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_5_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_6_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_6_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_7_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_7_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_8_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_8_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_9_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_9_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_10_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_10_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_11_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_11_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_12_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_12_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_13_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_13_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_14_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_14_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_15_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_15_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_16_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_16_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_17_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_17_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_18_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_18_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_19_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_19_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_20_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_20_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_21_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_21_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_22_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_22_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_23_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_23_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_24_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_24_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_25_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_25_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_26_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_26_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_27_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_27_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_28_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_28_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_29_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_29_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_30_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_30_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_31_ADDR_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MD_AUXADC_RDATA_31_ADDR_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MTS_PWRAP_REQ_0(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_MTS_ACK_0(x) ((x>>1) & 0x00000001)
+#define GET_PWRAP_MTS_RDATA_0(x) ((x>>2) & 0x0000ffff)
+#define GET_PWRAP_MTS_RDATA_VALID_0(x) ((x>>18) & 0x00000001)
+#define GET_MD_ADCINF_0_FSM(x) ((x>>19) & 0x00000007)
+#define GET_MD_ADCINF_0_BUSY(x) ((x>>22) & 0x00000001)
+#define GET_MD_ADCINF_0_ALE_CNT(x) ((x>>0) & 0x0000003f)
+#define GET_MD_ADCINF_0_DLE_CNT_REAL(x) ((x>>6) & 0x0000003f)
+#define GET_MD_ADCINF_0_ALE_CNT_FULL(x) ((x>>12) & 0x00000001)
+#define GET_MD_ADCINF_0_DLE_CNT_FULL(x) ((x>>13) & 0x00000001)
+#define GET_MTS_PWRAP_REQ_1(x) ((x>>0) & 0x00000001)
+#define GET_PWRAP_MTS_ACK_1(x) ((x>>1) & 0x00000001)
+#define GET_PWRAP_MTS_RDATA_1(x) ((x>>2) & 0x0000ffff)
+#define GET_PWRAP_MTS_RDATA_VALID_1(x) ((x>>18) & 0x00000001)
+#define GET_MD_ADCINF_1_FSM(x) ((x>>19) & 0x00000007)
+#define GET_MD_ADCINF_1_BUSY(x) ((x>>22) & 0x00000001)
+#define GET_MD_ADCINF_1_ALE_CNT(x) ((x>>0) & 0x0000003f)
+#define GET_MD_ADCINF_1_DLE_CNT_REAL(x) ((x>>6) & 0x0000003f)
+#define GET_MD_ADCINF_1_ALE_CNT_FULL(x) ((x>>12) & 0x00000001)
+#define GET_MD_ADCINF_1_DLE_CNT_FULL(x) ((x>>13) & 0x00000001)
+#define GET_SWRST(x) ((x>>0) & 0x00000001)
+#define GET_VALID_SPM_SLEEP_PROTECTION_CTRL(x) ((x>>0) & 0x00000003)
+#define GET_VALID_SCP_SLEEP_PROTECTION_CTRL(x) ((x>>2) & 0x00000003)
+#define GET_SPM_SLEEP_ACK_CONDITION(x) ((x>>4) & 0x00000003)
+#define GET_SCP_SLEEP_ACK_CONDITION(x) ((x>>6) & 0x00000003)
+#define GET_SPM_SLEEP_ACK_AFTER_TIMER_CLK_GATED(x) ((x>>8) & 0x00000001)
+#define GET_SCP_SLEEP_ACK_AFTER_TIMER_CLK_GATED(x) ((x>>9) & 0x00000001)
+#define GET_SPM_SLEEP_ACK_ON_OTHER_GATING(x) ((x>>10) & 0x00000001)
+#define GET_SCP_SLEEP_ACK_ON_OTHER_GATING(x) ((x>>11) & 0x00000001)
+#define GET_SPM_SLEEP_GATING_CONDITION(x) ((x>>0) & 0x00000001)
+#define GET_HARB_SPM_SLEEP_GATING(x) ((x>>1) & 0x00000001)
+#define GET_WACS0_REQ_SPM_SLEEP_GATING(x) ((x>>2) & 0x00000001)
+#define GET_WACS1_REQ_SPM_SLEEP_GATING(x) ((x>>3) & 0x00000001)
+#define GET_WACS2_REQ_SPM_SLEEP_GATING(x) ((x>>4) & 0x00000001)
+#define GET_WACS_P2P_REQ_SPM_SLEEP_GATING(x) ((x>>5) & 0x00000001)
+#define GET_WACS_MD32_REQ_SPM_SLEEP_GATING(x) ((x>>6) & 0x00000001)
+#define GET_MDINF_REQ_SPM_SLEEP_GATING(x) ((x>>7) & 0x00000001)
+#define GET_C2KINF_REQ_SPM_SLEEP_GATING(x) ((x>>8) & 0x00000001)
+#define GET_MD_DVFSINF_REQ_SPM_SLEEP_GATING(x) ((x>>9) & 0x00000001)
+#define GET_SPMINF_REQ_SPM_SLEEP_GATING(x) ((x>>10) & 0x00000001)
+#define GET_SPMINF_BACKUP_REQ_SPM_SLEEP_GATING(x) ((x>>11) & 0x00000001)
+#define GET_DCXO_CONNINF_REQ_SPM_SLEEP_GATING(x) ((x>>12) & 0x00000001)
+#define GET_DCXO_NFCINF_REQ_SPM_SLEEP_GATING(x) ((x>>13) & 0x00000001)
+#define GET_MCU_PMINF_REQ_SPM_SLEEP_GATING(x) ((x>>14) & 0x00000001)
+#define GET_MD_ADCINF_0_REQ_SPM_SLEEP_GATING(x) ((x>>15) & 0x00000001)
+#define GET_MD_ADCINF_1_REQ_SPM_SLEEP_GATING(x) ((x>>16) & 0x00000001)
+#define GET_GPSINF_0_REQ_SPM_SLEEP_GATING(x) ((x>>17) & 0x00000001)
+#define GET_GPSINF_1_REQ_SPM_SLEEP_GATING(x) ((x>>18) & 0x00000001)
+#define GET_STAUPD_REQ_SPM_SLEEP_GATING(x) ((x>>19) & 0x00000001)
+#define GET_WACS3_REQ_SPM_SLEEP_GATING(x) ((x>>20) & 0x00000001) //jinghao
+#define GET_SCP_SLEEP_GATING_CONDITION(x) ((x>>0) & 0x00000001)
+#define GET_HARB_SCP_SLEEP_GATING(x) ((x>>1) & 0x00000001)
+#define GET_WACS0_REQ_SCP_SLEEP_GATING(x) ((x>>2) & 0x00000001)
+#define GET_WACS1_REQ_SCP_SLEEP_GATING(x) ((x>>3) & 0x00000001)
+#define GET_WACS2_REQ_SCP_SLEEP_GATING(x) ((x>>4) & 0x00000001)
+#define GET_WACS_P2P_REQ_SCP_SLEEP_GATING(x) ((x>>5) & 0x00000001)
+#define GET_WACS_MD32_REQ_SCP_SLEEP_GATING(x) ((x>>6) & 0x00000001)
+#define GET_MDINF_REQ_SCP_SLEEP_GATING(x) ((x>>7) & 0x00000001)
+#define GET_C2KINF_REQ_SCP_SLEEP_GATING(x) ((x>>8) & 0x00000001)
+#define GET_MD_DVFSINF_REQ_SCP_SLEEP_GATING(x) ((x>>9) & 0x00000001)
+#define GET_SPMINF_REQ_SCP_SLEEP_GATING(x) ((x>>10) & 0x00000001)
+#define GET_SPMINF_BACKUP_REQ_SCP_SLEEP_GATING(x) ((x>>11) & 0x00000001)
+#define GET_DCXO_CONNINF_REQ_SCP_SLEEP_GATING(x) ((x>>12) & 0x00000001)
+#define GET_DCXO_NFCINF_REQ_SCP_SLEEP_GATING(x) ((x>>13) & 0x00000001)
+#define GET_MCU_PMINF_REQ_SCP_SLEEP_GATING(x) ((x>>14) & 0x00000001)
+#define GET_MD_ADCINF_0_REQ_SCP_SLEEP_GATING(x) ((x>>15) & 0x00000001)
+#define GET_MD_ADCINF_1_REQ_SCP_SLEEP_GATING(x) ((x>>16) & 0x00000001)
+#define GET_GPSINF_0_REQ_SCP_SLEEP_GATING(x) ((x>>17) & 0x00000001)
+#define GET_GPSINF_1_REQ_SCP_SLEEP_GATING(x) ((x>>18) & 0x00000001)
+#define GET_STAUPD_REQ_SCP_SLEEP_GATING(x) ((x>>19) & 0x00000001)
+#define GET_WACS3_REQ_SCP_SLEEP_GATING(x) ((x>>20) & 0x00000001) //jinghao
+#define GET_ARBITER_SEL_CH0(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_SEL_CH1(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_SEL_CH2(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_SEL_CH3(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_SEL_CH4(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_SEL_CH5(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_SEL_CH6(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_SEL_CH7(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_SEL_CH8(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_SEL_CH9(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_SEL_CH10(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_SEL_CH11(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_SEL_CH12(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_SEL_CH13(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_SEL_CH14(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_SEL_CH15(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_SEL_CH16(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_MDINF_SEL(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_SPMINF_SEL(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_OUT_SPMINF_BACKUP_SEL(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS0_SEL(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS_MD32_SEL(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_DCXO_CONNINF_SEL(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_OUT_DCXO_NFCINF_SEL(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_OUT_MCU_PMINF_SEL(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_OUT_STAUPD_SEL(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_MD_ADCINF_0_SEL(x) ((x>>8) & 0x000000ff)
+#define GET_ARBITER_OUT_MD_ADCINF_1_SEL(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_OUT_GPSINF_0_SEL(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_OUT_GPSINF_1_SEL(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS2_SEL(x) ((x>>8) & 0x000000ff)
+//#define GET_ARBITER_OUT_MD_DVFSINF_SEL(x) ((x>>16) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS1_SEL(x) ((x>>24) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS_P2P_SEL(x) ((x>>0) & 0x000000ff)
+#define GET_ARBITER_OUT_WACS3_SEL(x) ((x>>8) & 0x000000ff) //jinghao
+#define GET_STARV_COUNTER0_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER0_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER1_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER1_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER2_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER2_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER3_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER3_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER4_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER4_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER5_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER5_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER6_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER6_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER7_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER7_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER8_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER8_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER9_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER9_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER10_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER10_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER11_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER11_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER12_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER12_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER13_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER13_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER14_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER14_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER15_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER15_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER16_TARGET(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER16_ENABLE(x) ((x>>10) & 0x00000001)
+#define GET_STARV_INT_EN(x) ((x>>0) & 0x00000001)
+#define GET_STARV_COUNTER0_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER0(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER1_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER1(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER2_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER2(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER3_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER3(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER4_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER4(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER5_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER5(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER6_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER6(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER7_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER7(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER8_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER8(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER9_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER9(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER10_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER10(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER11_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER11(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER12_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER12(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER13_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER13(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER14_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER14(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER15_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER15(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER16_GATED(x) ((x>>0) & 0x000003ff)
+#define GET_STARV_COUNTER16(x) ((x>>10) & 0x000003ff)
+#define GET_STARV_COUNTER0_CLR(x) ((x>>0) & 0x00000001)
+#define GET_STARV_COUNTER1_CLR(x) ((x>>1) & 0x00000001)
+#define GET_STARV_COUNTER2_CLR(x) ((x>>2) & 0x00000001)
+#define GET_STARV_COUNTER3_CLR(x) ((x>>3) & 0x00000001)
+#define GET_STARV_COUNTER4_CLR(x) ((x>>4) & 0x00000001)
+#define GET_STARV_COUNTER5_CLR(x) ((x>>5) & 0x00000001)
+#define GET_STARV_COUNTER6_CLR(x) ((x>>6) & 0x00000001)
+#define GET_STARV_COUNTER7_CLR(x) ((x>>7) & 0x00000001)
+#define GET_STARV_COUNTER8_CLR(x) ((x>>8) & 0x00000001)
+#define GET_STARV_COUNTER9_CLR(x) ((x>>9) & 0x00000001)
+#define GET_STARV_COUNTER10_CLR(x) ((x>>10) & 0x00000001)
+#define GET_STARV_COUNTER11_CLR(x) ((x>>11) & 0x00000001)
+#define GET_STARV_COUNTER12_CLR(x) ((x>>12) & 0x00000001)
+#define GET_STARV_COUNTER13_CLR(x) ((x>>13) & 0x00000001)
+#define GET_STARV_COUNTER14_CLR(x) ((x>>14) & 0x00000001)
+#define GET_STARV_COUNTER15_CLR(x) ((x>>15) & 0x00000001)
+#define GET_STARV_COUNTER16_CLR(x) ((x>>16) & 0x00000001)
+#define GET_AG_ARB_HPRIO_STARV(x) ((x>>0) & 0x0000ffff) //jinghao
+#define GET_MONITOR_MODE(x) ((x>>0) & 0x00000003)
+#define GET_MONITOR_STOP_AFTER_INT(x) ((x>>2) & 0x00000001)
+#define GET_MONITOR_CLR(x) ((x>>3) & 0x00000001)
+#define GET_MONITOR_RECORD_CNT(x) ((x>>4) & 0x0000001f)
+#define GET_MONITOR_TARGET_CHANNEL(x) ((x>>0) & 0x00000000)
+#define GET_MONITOR_TARGET_CMD(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_TARGET_CMD_MASK(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_TARGET_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_TARGET_WDATA_MASK(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CHANNEL_0(x) ((x>>0) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_1(x) ((x>>8) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_2(x) ((x>>16) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_3(x) ((x>>24) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_4(x) ((x>>0) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_5(x) ((x>>8) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_6(x) ((x>>16) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_7(x) ((x>>24) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_8(x) ((x>>0) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_9(x) ((x>>8) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_10(x) ((x>>16) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_11(x) ((x>>24) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_12(x) ((x>>0) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_13(x) ((x>>8) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_14(x) ((x>>16) & 0x000000ff)
+#define GET_MONITOR_CHANNEL_15(x) ((x>>24) & 0x000000ff)
+#define GET_MONITOR_CMD_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_2(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_3(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_4(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_5(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_6(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_7(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_8(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_9(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_10(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_11(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_12(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_13(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_CMD_14(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_CMD_15(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_0(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_1(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_2(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_3(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_4(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_5(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_6(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_7(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_8(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_9(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_10(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_11(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_12(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_13(x) ((x>>16) & 0x0000ffff)
+#define GET_MONITOR_WDATA_14(x) ((x>>0) & 0x0000ffff)
+#define GET_MONITOR_WDATA_15(x) ((x>>16) & 0x0000ffff)
+#define GET_DEBUG_REG_FOR_SW_0(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_REG_FOR_SW_1(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_REG_FOR_SW_2(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_REG_FOR_SW_3(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_REG_FOR_SW_4(x) ((x>>0) & 0x00000000)
+#define GET_DEBUG_REG_FOR_SW_5(x) ((x>>0) & 0x00000000)
+#define GET_SYS_IDLE_WITH_PSEL_M(x) ((x>>0) & 0x00000001)
+#define GET_SYS_IDLE_FOR_SLEEP_ACK_WITHOUT_PSEL(x) ((x>>1) & 0x00000001)
+#define GET_GPSINF_BUSY_WITHOUT_SPM_SLEEP_REQ(x) ((x>>2) & 0x00000001)
+#define GET_GPSINF_BUSY_WITHOUT_SCP_SLEEP_REQ(x) ((x>>3) & 0x00000001)
+#define GET_CIPHER_FIFO_RD_RX_MUST_BE_BEFORE_TX(x) ((x>>4) & 0x00000001)
+#define GET_BWC_OPTIONS_RESERVED(x) ((x>>5) & 0x07ffffff)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_WACS0_EN0(x) ((x>>21) & 0x00000001)
+#define GET_WACS0_INIT_DONE0(x) ((x>>22) & 0x00000001)
+#define GET_SYS_IDLE0(x) ((x>>23) & 0x00000001)
+#define GET_WACS0_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS0_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS0_VLDCLR(x) ((x>>0) & 0x00000001)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_WACS2_EN0(x) ((x>>21) & 0x00000001)
+#define GET_WACS2_INIT_DONE2(x) ((x>>22) & 0x00000001)
+#define GET_SYS_IDLE2(x) ((x>>23) & 0x00000001)
+#define GET_WACS2_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS2_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS2_VLDCLR(x) ((x>>0) & 0x00000001)
+
+//jinghao add for wacs1/3
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_WACS1_EN0(x) ((x>>21) & 0x00000001)
+#define GET_WACS1_INIT_DONE1(x) ((x>>22) & 0x00000001)
+#define GET_SYS_IDLE1(x) ((x>>23) & 0x00000001)
+#define GET_WACS1_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS1_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS1_VLDCLR(x) ((x>>0) & 0x00000001)
+#define GET_WACS3_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS3_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS3_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS3_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS3_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS3_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE3(x) ((x>>20) & 0x00000001)
+#define GET_WACS3_EN0(x) ((x>>21) & 0x00000001)
+#define GET_WACS3_INIT_DONE3(x) ((x>>22) & 0x00000001)
+#define GET_SYS_IDLE3(x) ((x>>23) & 0x00000001)
+#define GET_WACS3_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS3_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS3_VLDCLR(x) ((x>>0) & 0x00000001)
+#define GET_MD_AUXADC_READY_CHECK_0(x) ((x>>0) & 0x00000001)
+#define GET_MD_AUXADC_READY_CHECK_1(x) ((x>>1) & 0x00000001)
+
+
+#endif //__PMIC_WRAP_REGS_HMAC__
+
diff --git a/src/bsp/lk/platform/mt2731/include/platform/regulator/mtk_regulator.h b/src/bsp/lk/platform/mt2731/include/platform/regulator/mtk_regulator.h
new file mode 100644
index 0000000..4b45cab
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/regulator/mtk_regulator.h
@@ -0,0 +1,30 @@
+#ifndef __SSPM_MTK_REGULATOR_H
+#define __SSPM_MTK_REGULATOR_H
+
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+struct mtk_regulator {
+ const char *name;
+ unsigned char id;
+ struct regulator_ctrl *reg_ops;
+};
+
+enum {
+ REGULATOR_MODE_FAST,
+ REGULATOR_MODE_NORMAL,
+};
+
+extern int mtk_regulator_get(const char *id, struct mtk_regulator *mreg);
+extern int mtk_regulator_enable(struct mtk_regulator *mreg, unsigned char enable);
+extern int mtk_regulator_is_enabled(struct mtk_regulator *mreg);
+extern int mtk_regulator_set_voltage(struct mtk_regulator *mreg, int min_uv, int max_uv);
+extern int mtk_regulator_get_voltage(struct mtk_regulator *mreg);
+extern int mtk_regulator_set_mode(struct mtk_regulator *mreg, unsigned char mode);
+extern int mtk_regulator_get_mode(struct mtk_regulator *mreg);
+#ifdef LDO_VOTRIM_SUPPORT
+extern int mtk_regulator_set_votrim(struct mtk_regulator *mreg, int trim_uv);
+extern int mtk_regulator_get_votrim(struct mtk_regulator *mreg);
+#endif
+
+#endif /* __SSPM_MTK_REGULATOR_H */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/rt5738.h b/src/bsp/lk/platform/mt2731/include/platform/rt5738.h
new file mode 100644
index 0000000..34bac4d
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/rt5738.h
@@ -0,0 +1,61 @@
+#ifndef _rt5738_SW_H_
+#define _rt5738_SW_H_
+
+#define CFG_RT5738_DDQ
+#define CFG_PRELOADER
+
+#ifdef CFG_PRELOADER
+#include <sys/types.h>
+#endif
+
+#define RT5738_VDD2_ID 0x0000
+#ifdef CFG_RT5738_DDQ
+#define RT5738_VDDQ_ID 0x0000
+#endif /* CFG_RT5738_DDQ */
+
+/* Voltage setting */
+#define RT5738_VSEL0 0x00
+#define RT5738_VSEL1 0x01
+/* Control register */
+#define RT5738_CONTROL 0x02
+/* IC Type */
+#define RT5738_ID1 0x03
+/* IC mask version */
+#define RT5738_ID2 0x04
+/* Monitor register */
+#define RT5738_MONITOR 0x05
+#define RT5738_CTRL2 0x06
+#define RT5738_CTRL3 0x07
+#define RT5738_CTRL4 0x08
+
+enum {
+ RT5738_VDD2,
+#ifdef CFG_RT5738_DDQ
+ RT5738_VDDQ,
+#endif /* CFG_RT5738_DDQ */
+ RT5738_MAX,
+};
+
+struct rt5738_chip {
+ kal_uint8 id;
+ char *name;
+ kal_uint16 i2c_channel;
+ kal_uint8 slave_addr;
+ kal_uint8 buck_ctrl;
+ kal_uint8 mode_shift;
+ kal_uint8 en_shift;
+ kal_uint32 chip_id;
+};
+
+extern void rt5738_dump_register(int id);
+extern void rt5738_driver_probe(void);
+/*extern int rt5738_vosel(unsigned long val);*/
+extern int rt5738_set_voltage(int id, unsigned long val);
+extern unsigned long rt5738_get_voltage(int id); // if return 0 --> get fail
+extern int rt5738_enable(int id, unsigned char en);
+extern int rt5738_is_enabled(int id); // if return -1 --> get fail
+extern int rt5738_set_mode(int id, unsigned char mode);
+extern unsigned char rt5738_get_mode(int id);
+extern int is_rt5738_exist(int id);
+extern int g_rt5738_hw_exist[RT5738_MAX];
+#endif /* _rt5738_SW_H_ */
diff --git a/src/bsp/lk/platform/mt2731/include/platform/sip.h b/src/bsp/lk/platform/mt2731/include/platform/sip.h
new file mode 100644
index 0000000..1f676d2
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/sip.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <sys/types.h>
+
+#if ARCH_ARM64
+#define MTK_SIP_SMC_AARCH_BIT (0x40000000)
+#else
+#define MTK_SIP_SMC_AARCH_BIT (0x00000000)
+#endif
+
+#define MTK_SIP_KERNEL_BOOT_AARCH32 (0x82000200)
+#define MTK_SIP_KERNEL_BOOT_AARCH64 (0xC2000200)
+
+#define MTK_SIP_KERNEL_EMIMPU_SET (0x82000262 | MTK_SIP_SMC_AARCH_BIT)
+#define MTK_SIP_KERNEL_EMIMPU_CLEAR (0x82000263 | MTK_SIP_SMC_AARCH_BIT)
+
+#define MTK_SIP_KERNEL_MDHW_REMAP_SET (0x82000266 | MTK_SIP_SMC_AARCH_BIT)
+#define MTK_SIP_KERNEL_MDHW_REMAP_GET (0x82000267 | MTK_SIP_SMC_AARCH_BIT)
+
+#define MTK_SIP_LK_AMMS_MD_BASE_ADDR_AARCH32 0x82000112
+#define MTK_SIP_LK_AMMS_MD_BASE_ADDR_AARCH64 0xC2000112
+#define MTK_SIP_LK_AMMS_GET_MD_BASE_ADDR_AARCH32 0x82000113
+#define MTK_SIP_LK_AMMS_GET_MD_BASE_ADDR_AARCH64 0xC2000113
+#define MTK_SIP_LK_AMMS_MD_POS_ADDR_AARCH32 0x82000121
+#define MTK_SIP_LK_AMMS_MD_POS_ADDR_AARCH64 0xC2000121
+#define MTK_SIP_LK_AMMS_MD_POS_LENGTH_AARCH32 0x82000122
+#define MTK_SIP_LK_AMMS_MD_POS_LENGTH_AARCH64 0xC2000122
+#define MTK_SIP_LK_AMMS_GET_MD_POS_ADDR_AARCH32 0x82000123
+#define MTK_SIP_LK_AMMS_GET_MD_POS_ADDR_AARCH64 0xC2000123
+#define MTK_SIP_LK_AMMS_GET_MD_POS_LENGTH_AARCH32 0x82000124
+#define MTK_SIP_LK_AMMS_GET_MD_POS_LENGTH_AARCH64 0xC2000124
+#define MTK_SIP_LK_AMMS_MD_POS_MD_VIEW_ADDR_AARCH32 0x82000125
+#define MTK_SIP_LK_AMMS_MD_POS_MD_VIEW_ADDR_AARCH64 0xC2000125
+#define MTK_SIP_LK_AMMS_GET_MD_POS_MD_VIEW_ADDR_AARCH32 0x82000126
+#define MTK_SIP_LK_AMMS_GET_MD_POS_MD_VIEW_ADDR_AARCH64 0xC2000126
diff --git a/src/bsp/lk/platform/mt2731/include/platform/spm.h b/src/bsp/lk/platform/mt2731/include/platform/spm.h
new file mode 100644
index 0000000..d69d28b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/spm.h
@@ -0,0 +1,11 @@
+#ifndef _SPM_
+#define _SPM_
+
+#include <platform/mt_spm_reg.h>
+#include <platform/mt_typedefs.h>
+
+/* Macro and Inline */
+#define spm_read(addr) DRV_Reg32(addr)
+#define spm_write(addr, val) DRV_WriteReg32(addr, val)
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos.h b/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos.h
new file mode 100644
index 0000000..cb2d0fd
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos.h
@@ -0,0 +1,54 @@
+#ifndef _SPM_MTCMOS_
+#define _SPM_MTCMOS_
+
+#define STA_POWER_DOWN 0
+#define STA_POWER_ON 1
+
+/* INFRASYS Register */
+#define TOPAXI_PROT_EN (INFRACFG_BASE + 0x220)
+#define TOPAXI_PROT_STA1 (INFRACFG_BASE + 0x228)
+#define TOPAXI_PROT_EN1 (INFRACFG_BASE + 0x250)
+#define TOPAXI_PROT_STA3 (INFRACFG_BASE + 0x258)
+#define TOPAXI_PROT_EN_SET (INFRACFG_BASE + 0x260)
+#define TOPAXI_PROT_EN_CLR (INFRACFG_BASE + 0x264)
+
+typedef enum {
+ E1_LITTLE_STAGE_1 = 0,
+ E1_BIG_STAGE_1,
+ E1_BIG_STAGE_2,
+ E1_BIG_STAGE_3,
+ E2_STAGE_1,
+ E2_STAGE_2,
+} CPUSYS_INIT_STAGE;
+
+/*
+ * 1. for CPU MTCMOS: CPU0, CPU1, CPU2, CPU3, DBG0, CPU4, CPU5, CPU6, CPU7, DBG1, CPUSYS1
+ * 2. call spm_mtcmos_cpu_lock/unlock() before/after any operations
+ */
+extern void spm_mtcmos_cpu_lock(unsigned long *flags);
+extern void spm_mtcmos_cpu_unlock(unsigned long *flags);
+extern void spm_mtcmos_ctrl_cpusys_init(CPUSYS_INIT_STAGE stage);
+
+extern int spm_mtcmos_ctrl_cpu(unsigned int cpu, int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu0(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu1(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu2(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu3(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu4(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu5(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu6(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpu7(int state, int chkWfiBeforePdn);
+
+extern int spm_mtcmos_ctrl_dbg0(int state);
+extern int spm_mtcmos_ctrl_cpusys0(int state, int chkWfiBeforePdn);
+extern int spm_mtcmos_ctrl_cpusys1(int state, int chkWfiBeforePdn);
+
+extern unsigned char spm_cpusys0_can_power_down(void);
+extern unsigned char spm_cpusys1_can_power_down(void);
+
+/*
+ * 1. for non-CPU, infra, DPY MTCMOS: DISP, MFG, ISP, VDEC, USB2, VEN, AUDIO, USB
+ * 2. call spm_mtcmos_noncpu_lock/unlock() before/after any operations
+ */
+extern int spm_mtcmos_ctrl_md1(int state);
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos_internal.h b/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos_internal.h
new file mode 100644
index 0000000..e1a96d6
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/spm_mtcmos_internal.h
@@ -0,0 +1,102 @@
+#ifndef _SPM_MTCMOS_INTERNAL_
+#define _SPM_MTCMOS_INTERNAL_
+
+
+/**************************************
+ * for CPU MTCMOS
+ **************************************/
+/*
+ * regiser bit difinition
+ */
+/* SPM_CA7_CPU0_PWR_CON */
+/* SPM_CA7_CPU1_PWR_CON */
+/* SPM_CA7_CPU2_PWR_CON */
+/* SPM_CA7_CPU3_PWR_CON */
+/* SPM_CA7_DBG_PWR_CON */
+/* SPM_CA7_CPUTOP_PWR_CON */
+/* SPM_CA15_CPU0_PWR_CON */
+/* SPM_CA15_CPU1_PWR_CON */
+/* SPM_CA15_CPU2_PWR_CON */
+/* SPM_CA15_CPU3_PWR_CON */
+/* SPM_CA15_CPUTOP_PWR_CON */
+#define SRAM_ISOINT_B (1U << 6)
+#define SRAM_CKISO (1U << 5)
+#define PWR_CLK_DIS (1U << 4)
+#define PWR_ON_2ND (1U << 3)
+#define PWR_ON (1U << 2)
+#define PWR_ISO (1U << 1)
+#define PWR_RST_B (1U << 0)
+#define CA15_CPU_PWR_CON_DEF_OFF (0x00000032)
+
+/* SPM_CA7_CPU0_L1_PDN */
+/* SPM_CA7_CPU1_L1_PDN */
+/* SPM_CA7_CPU2_L1_PDN */
+/* SPM_CA7_CPU3_L1_PDN */
+#define L1_PDN_ACK (1U << 8)
+#define L1_PDN (1U << 0)
+/* SPM_CA7_CPUTOP_L2_PDN */
+#define L2_SRAM_PDN_ACK (1U << 8)
+#define L2_SRAM_PDN (1U << 0)
+/* SPM_CA7_CPUTOP_L2_SLEEP */
+#define L2_SRAM_SLEEP_B_ACK (1U << 8)
+#define L2_SRAM_SLEEP_B (1U << 0)
+
+/* SPM_CA15_L1_PWR_CON */
+#define CPU3_CA15_L1_PDN_ACK (1U << 11)
+#define CPU2_CA15_L1_PDN_ACK (1U << 10)
+#define CPU1_CA15_L1_PDN_ACK (1U << 9)
+#define CPU0_CA15_L1_PDN_ACK (1U << 8)
+#define CPU3_CA15_L1_PDN_ISO (1U << 7)
+#define CPU2_CA15_L1_PDN_ISO (1U << 6)
+#define CPU1_CA15_L1_PDN_ISO (1U << 5)
+#define CPU0_CA15_L1_PDN_ISO (1U << 4)
+#define CPU3_CA15_L1_PDN (1U << 3)
+#define CPU2_CA15_L1_PDN (1U << 2)
+#define CPU1_CA15_L1_PDN (1U << 1)
+#define CPU0_CA15_L1_PDN (1U << 0)
+#define CA15_L1_PWR_CON_DEF_OFF (0x00000fff)
+/* SPM_CA15_L2_PWR_CON */
+#define CA15_L2_SLEEPB_ACK (1U << 10)
+#define CA15_L2_PDN_ACK (1U << 8)
+#define CA15_L2_SLEEPB_ISO (1U << 6)
+#define CA15_L2_SLEEPB (1U << 4)
+#define CA15_L2_PDN_ISO (1U << 2)
+#define CA15_L2_PDN (1U << 0)
+#define CA15_L2_PWR_CON_DEF_OFF (0x00000515)
+
+/* SPM_PWR_STATUS */
+/* SPM_PWR_STATUS_2ND */
+#define CA15_CPU3 (1U << 19)
+#define CA15_CPU2 (1U << 18)
+#define CA15_CPU1 (1U << 17)
+#define CA15_CPU0 (1U << 16)
+#define CA15_CPUTOP (1U << 15)
+#define CA7_DBG (1U << 13)
+#define CA7_CPU3 (1U << 12)
+#define CA7_CPU2 (1U << 11)
+#define CA7_CPU1 (1U << 10)
+#define CA7_CPU0 (1U << 9)
+#define CA7_CPUTOP (1U << 8)
+
+/* SPM_SLEEP_TIMER_STA */
+#define CA15_CPUTOP_STANDBYWFI (1U << 25)
+#define CA7_CPUTOP_STANDBYWFI (1U << 24)
+#define CA15_CPU3_STANDBYWFI (1U << 23)
+#define CA15_CPU2_STANDBYWFI (1U << 22)
+#define CA15_CPU1_STANDBYWFI (1U << 21)
+#define CA15_CPU0_STANDBYWFI (1U << 20)
+#define CA7_CPU3_STANDBYWFI (1U << 19)
+#define CA7_CPU2_STANDBYWFI (1U << 18)
+#define CA7_CPU1_STANDBYWFI (1U << 17)
+#define CA7_CPU0_STANDBYWFI (1U << 16)
+
+/* SPM_SLEEP_DUAL_VCORE_PWR_CON */
+#define VCA15_PWR_ISO (1U << 13)
+#define VCA7_PWR_ISO (1U << 12)
+
+/* INFRA_TOPAXI_PROTECTEN */
+#define CA15_PDN_REQ (30)
+#define CA7_PDN_REQ (29)
+#define L2_PDN_REQ (2)
+
+#endif
diff --git a/src/bsp/lk/platform/mt2731/include/platform/udc-common.h b/src/bsp/lk/platform/mt2731/include/platform/udc-common.h
new file mode 100644
index 0000000..bee93e9
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/udc-common.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+extern int txn_status;
+
+#define GET_STATUS 0
+#define CLEAR_FEATURE 1
+#define SET_FEATURE 3
+#define SET_ADDRESS 5
+#define GET_DESCRIPTOR 6
+#define SET_DESCRIPTOR 7
+#define GET_CONFIGURATION 8
+#define SET_CONFIGURATION 9
+#define GET_INTERFACE 10
+#define SET_INTERFACE 11
+#define SYNCH_FRAME 12
+#define SET_SEL 48
+
+#define TYPE_DEVICE 1
+#define TYPE_CONFIGURATION 2
+#define TYPE_STRING 3
+#define TYPE_INTERFACE 4
+#define TYPE_ENDPOINT 5
+#define TYPE_DEV_QUALIFIER 6
+#define TYPE_OTHER_SPEEDCONF 7
+#define TYPE_IFACE_POWER 8
+#define TYPE_OTG 9
+#define TYPE_DEBUG 10
+#define TYPE_IFACE_ASSOC 11
+#define TYPE_BOS 15
+#define TYPE_DEVICE_CAP 16
+#define TYPE_SS_EP_COMP 48
+
+#define DEVICE_READ 0x80
+#define DEVICE_WRITE 0x00
+#define INTERFACE_READ 0x81
+#define INTERFACE_WRITE 0x01
+#define ENDPOINT_READ 0x82
+#define ENDPOINT_WRITE 0x02
+
+#define TEST_SE0_NAK 0x0300
+#define TEST_PACKET 0x0400
+#define PORTSC_PTC (0xF << 16)
+#define PORTSC_PTC_SE0_NAK (0x03 << 16)
+#define PORTSC_PTC_TST_PKT (0x4 << 16)
+
+#define USB3_U1_ENABLE 48
+#define USB3_U2_ENABLE 49
+
+#define UDC_TYPE_BULK_IN 1
+#define UDC_TYPE_BULK_OUT 2
+
+struct setup_packet {
+ unsigned char type;
+ unsigned char request;
+ unsigned short value;
+ unsigned short index;
+ unsigned short length;
+} __attribute__ ((packed));
diff --git a/src/bsp/lk/platform/mt2731/include/platform/upmu_hw.h b/src/bsp/lk/platform/mt2731/include/platform/upmu_hw.h
new file mode 100644
index 0000000..8c5bbfe
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/include/platform/upmu_hw.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#if defined(PMIC_CHIP_MT6389)
+#include <platform/MT6389/upmu_hw.h>
+#endif
diff --git a/src/bsp/lk/platform/mt2731/interrupts.c b/src/bsp/lk/platform/mt2731/interrupts.c
new file mode 100644
index 0000000..c542f57
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/interrupts.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <kernel/thread.h>
+#include <platform/interrupts.h>
+#include <platform/mt_reg_base.h>
+#include <platform/mt_irq.h>
+#include <debug.h>
+
+/* set for mt_gic */
+void mt_irq_set_polarity(unsigned int irq, unsigned int polarity)
+{
+ unsigned int offset;
+ unsigned int reg_index;
+ unsigned int value;
+
+ /* peripheral device's IRQ line is using GIC's SPI, and line ID >= GIC_PRIVATE_SIGNALS */
+ if (irq < GIC_PRIVATE_SIGNALS) {
+ dprintf(SPEW, "The Interrupt ID < 32, please check!\n");
+ return;
+ }
+
+ offset = (irq - GIC_PRIVATE_SIGNALS) & 0x1F;
+ reg_index = (irq - GIC_PRIVATE_SIGNALS) >> 5;
+ if (polarity == 0) {
+ value = readl(INT_POL_CTL0 + (reg_index * 4));
+ value |= (1 << offset); /* always invert the incoming IRQ's polarity */
+ write_r((INT_POL_CTL0 + (reg_index * 4)), value);
+ } else {
+ value = readl(INT_POL_CTL0 + (reg_index * 4));
+ value &= ~(0x1 << offset);
+ write_r(INT_POL_CTL0 + (reg_index * 4), value);
+ }
+}
+
+/* set for arm gic */
+void mt_irq_set_sens(unsigned int irq, unsigned int sens)
+{
+ unsigned int config;
+
+ if (sens == EDGE_SENSITIVE) {
+ config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
+ config |= (0x2 << (irq % 16) * 2);
+ write_r(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
+ } else {
+ config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
+ config &= ~(0x2 << (irq % 16) * 2);
+ write_r( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
+ }
+ DSB;
+}
diff --git a/src/bsp/lk/platform/mt2731/plat_dbg_info.c b/src/bsp/lk/platform/mt2731/plat_dbg_info.c
new file mode 100644
index 0000000..ba4f48f
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/plat_dbg_info.c
@@ -0,0 +1,136 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include <platform/plat_dbg_info.h>
+
+static top_dbg_info *dbg_info;
+static int init = 0;
+
+static void init_dbg_info(void)
+{
+ unsigned int i;
+ unsigned int offset, size;
+
+ dbg_info = (top_dbg_info *) PLAT_DBG_INFO_BASE;
+
+ for (i = 0; i < INFO_TYPE_MAX; i++)
+ *((unsigned int *)dbg_info + i) = 0;
+
+#ifdef KEY_LAST_DRAMC
+ INIT_DBG_HEAD(LAST_DRAMC)
+#endif
+#ifdef KEY_LAST_EMI
+ INIT_DBG_HEAD(LAST_EMI)
+#endif
+#ifdef KEY_PLAT_SRAM_FLAG
+ INIT_DBG_HEAD(PLAT_SRAM_FLAG)
+#endif
+
+
+ offset = 4 * INFO_TYPE_MAX;
+ for (i = 0; i < TYPE_END; i++) {
+ size = dbg_info->head[i];
+ if ((size >> 16) == 0)
+ continue;
+ dbg_info->head[i] = (dbg_info->head[i] & 0xffff0000) | offset;
+ offset += (size & 0xffff);
+ }
+
+ dbg_info->tail = INFO_TAIL_MAGIC | sizeof(top_dbg_info);
+
+ init = 1;
+}
+
+unsigned int get_dbg_info_key(DBG_INFO_TYPE info_type)
+{
+ if (init == 0)
+ init_dbg_info();
+
+ return (*((unsigned int *)dbg_info + info_type) >> 16);
+}
+
+unsigned int get_dbg_info_base(unsigned int key)
+{
+ unsigned int i;
+ unsigned int offset;
+
+ if (key == 0)
+ return 0;
+
+ if (init == 0)
+ init_dbg_info();
+
+ for (i = 0; i < TYPE_END; i++) {
+ offset = *((unsigned int *)dbg_info + i);
+ if ((offset >> 16) == key)
+ return ((unsigned int)dbg_info + (offset & 0xffff));
+ }
+
+ return 0;
+}
+
+unsigned int get_dbg_info_size(unsigned int key)
+{
+ unsigned int offset_start, offset_end;
+ unsigned int i;
+
+ if (key == 0)
+ return 0;
+
+ if (init == 0)
+ init_dbg_info();
+
+ for (i = 0; i < TYPE_END; i++) {
+ offset_start = *((unsigned int *)dbg_info + i);
+ if ((offset_start >> 16) == key)
+ break;
+ }
+ offset_start &= 0xffff;
+
+ offset_end = dbg_info->tail - 4;
+ for (i++; i < TYPE_END; i++) {
+ if ((*((unsigned int *)dbg_info + i) >> 16) != 0) {
+ offset_end = *((unsigned int *)dbg_info + i);
+ break;
+ }
+ }
+
+ offset_end &= 0xffff;
+
+ return (offset_end - offset_start);
+}
+
diff --git a/src/bsp/lk/platform/mt2731/platform.c b/src/bsp/lk/platform/mt2731/platform.c
new file mode 100644
index 0000000..f3901a6
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/platform.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#include <debug.h>
+#include <dev/interrupt/arm_gic.h>
+#include <dev/timer/arm_generic.h>
+#include <dev/uart.h>
+#include <err.h>
+#include <errno.h>
+#include <lib/mempool.h>
+#include <platform.h>
+#include <platform/platform_blx.h>
+#include <platform/gic.h>
+#include <platform/mtk_wdt.h>
+#include <platform/mtk_drm.h>
+#include <platform/pmic_wrap_init.h>
+#include <platform/pmic.h>
+
+void platform_early_init(void)
+{
+ uart_init_early();
+
+ /* initialize the interrupt controller */
+ arm_gic_init();
+
+ arm_generic_timer_init(ARM_GENERIC_TIMER_PHYSICAL_INT, 13000000);
+
+ /* init debugtop DRM */
+ mtk_drm_init();
+
+ /* init AP watchdog and set timeout to 10 secs */
+ mtk_wdt_init();
+
+ /* bl2 or bl33 specific platform early init */
+ platform_early_init_blx();
+
+ extern void mtk_wdt_early_init(void) __attribute__((weak));
+ if (mtk_wdt_early_init)
+ mtk_wdt_early_init();
+}
+
+void platform_init(void)
+{
+ int cache_ret, uncache_ret;
+
+ cache_ret = NO_ERROR;
+ if (CACHED_MEMPOOL_ADDR && CACHED_MEMPOOL_SIZE)
+ cache_ret = mempool_init((void *)CACHED_MEMPOOL_ADDR,
+ CACHED_MEMPOOL_SIZE, MEMPOOL_CACHE);
+
+ uncache_ret = NO_ERROR;
+ if (UNCACHED_MEMPOOL_ADDR && UNCACHED_MEMPOOL_SIZE)
+ uncache_ret = mempool_init((void *)UNCACHED_MEMPOOL_ADDR,
+ UNCACHED_MEMPOOL_SIZE, MEMPOOL_UNCACHE);
+
+ if ((cache_ret != NO_ERROR) || (uncache_ret != NO_ERROR))
+ platform_halt(HALT_ACTION_REBOOT, HALT_REASON_SW_PANIC);
+}
+
+/* Initialization context in start.S before switching from EL3 to EL1.
+ * Note data/bss segment NOT initialized, i.e. No assumption on global variable initialization.*/
+void platform_el3_init(void)
+{
+ gic_setup();
+}
+
+
+/*
+ * target_ab_set_active_bootdev() - set active boot device in ab boot flow
+ *
+ * this function is used to set the active boot device, aka slot in ab boot
+ * concept. For mt2731, the slot concept should be defined by the actual
+ * target. For targets that support ab boot concept should override this
+ * function.
+ *
+ * @slot: the slot # to be set as active boot device
+ *
+ * returns:
+ * -ENOTSUP: function not supported
+ */
+__WEAK int target_ab_set_active_bootdev(int slot)
+{
+ return -ENOTSUP;
+}
+
+/*
+ * override the common plat_ab_set_active_bootdev() impl.
+ */
+int plat_ab_set_active_bootdev(int slot)
+{
+ return target_ab_set_active_bootdev(slot);
+}
diff --git a/src/bsp/lk/platform/mt2731/platform_bl2.c b/src/bsp/lk/platform/mt2731/platform_bl2.c
new file mode 100644
index 0000000..a09179b
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/platform_bl2.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#include <arch/ops.h>
+#include <debug.h>
+#include <err.h>
+#if WITH_KERNEL_VM
+#include <kernel/vm.h>
+#else
+#include <kernel/novm.h>
+#endif
+#include <memory.h>
+#include <platform.h>
+#include <platform/audio_clk_enable.h>
+#include <platform/bgr.h>
+#include <platform/clkbuf_ctl.h>
+#include <platform/dcm.h>
+#include <platform/mt_infracfg.h>
+#include <platform/pll.h>
+#include <platform/pmic_wrap_init.h>
+#include <platform/pmic.h>
+#include <platform/mt_gpt_v4.h>
+#include <platform/mtk_drm.h>
+#include <platform/nand/mtk_nand_nal.h>
+#include <platform/mtk_wdt.h>
+#include <boot_args.h>
+#include <string.h>
+
+static uint32_t g_boot_reason = 0;
+static uint32_t g_rgu_mode = 0;
+
+extern u32 g_ddr_reserve_ready;
+extern u32 g_ddr_reserve_ta_err;
+extern u32 g_ddr_reserve_enable;
+extern u32 g_ddr_reserve_success;
+
+#if WITH_KERNEL_VM
+#define PROG_MEM_MAPPING_IDX 0
+#define GIC_PERIPHERAL_MAPPING_IDX 1
+#define DRAM_MAPPING_IDX 2
+
+#define MMU_LEVEL_2_ENTRY_MAP_SIZE (0x200000) /* 2MB for 4K page size */
+
+/* initial memory mappings. parsed by start.S */
+struct mmu_initial_mapping mmu_initial_mappings[] = {
+ {
+ /*
+ * internal sram : 0x10_0000 ~ 0x12_ffff ==> 1st 2MB range in L2 table
+ * l2c shared sram: 0x20_0000 ~ 0x23_ffff ==> 2nd 2MB range in L2 table
+ * For 4K page size, an entry in level 2 mmu table can map to 2MB range.
+ *
+ * We use internal sram as arena memory to map dram to mmu, the internal
+ * sram should be mapped before dram mmu mmapping. Add internal sram
+ * to mmu initial mappings, so we don't need to carefully map the
+ * internal sram on existing mmu table (new page table is not available
+ * since the arena memory is not set yet).
+ */
+ .phys = ROUNDDOWN(SRAM_BASE_PHYS, MMU_LEVEL_2_ENTRY_MAP_SIZE),
+ .virt = ROUNDDOWN(SRAM_BASE_VIRT, MMU_LEVEL_2_ENTRY_MAP_SIZE),
+ .size = (MMU_LEVEL_2_ENTRY_MAP_SIZE * 2),
+ .flags = 0,
+ .name = "prog"
+ },
+ {
+ .phys = GIC_PERIPHERAL_BASE_PHYS,
+ .virt = GIC_PERIPHERAL_BASE_VIRT,
+ .size = GIC_PERIPHERAL_BASE_SIZE,
+ .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE
+ },
+
+ /* reserved for dram */
+ { 0 },
+ /* null entry to terminate the list */
+ { 0 }
+};
+
+static pmm_arena_t arena = {
+ .name = "sram",
+ .base = SRAM_ARENA_BASE,
+ .size = SRAM_ARENA_SIZE,
+ .flags = PMM_ARENA_FLAG_KMAP,
+ .priority = 1,
+};
+
+static pmm_arena_t dram_arena = {
+ .name = "dram",
+ .base = DRAM_ARENA_BASE,
+ .size = DRAM_ARENA_SIZE,
+ .flags = PMM_ARENA_FLAG_KMAP,
+ .priority = 0,
+};
+#endif /* WITH_KERNEL_VM */
+
+static inline size_t query_plat_dram_sz(void)
+{
+ return mt_mem_size();
+}
+
+static void setup_plat_mem(void)
+{
+#if WITH_KERNEL_VM
+ size_t dram_sz, mem_sz;
+ size_t unmap_dram_start_pa, unmap_dram_start_va;
+
+ /* map dram may need new page tables, add internal sram to arena memory */
+ pmm_add_arena(&arena);
+
+ /*
+ * Except the dram range for uncached memory pool, all other dram ranges
+ * are all mapped as cacheable memory.
+ */
+ unmap_dram_start_pa = DRAM_BASE_PHY;
+ unmap_dram_start_va = DRAM_BASE_VIRT;
+
+ dram_sz = query_plat_dram_sz();
+ mem_sz = UNCACHED_MEMPOOL_ADDR - unmap_dram_start_va;
+ arch_mmu_map(unmap_dram_start_va, unmap_dram_start_pa,
+ mem_sz >> PAGE_SIZE_SHIFT, ARCH_MMU_FLAG_CACHED);
+ arch_mmu_map(UNCACHED_MEMPOOL_ADDR, unmap_dram_start_pa + mem_sz,
+ UNCACHED_MEMPOOL_SIZE >> PAGE_SIZE_SHIFT,
+ ARCH_MMU_FLAG_UNCACHED);
+
+ mem_sz += UNCACHED_MEMPOOL_SIZE;
+ arch_mmu_map(UNCACHED_MEMPOOL_ADDR + UNCACHED_MEMPOOL_SIZE,
+ unmap_dram_start_pa + mem_sz,
+ (dram_sz - mem_sz) >> PAGE_SIZE_SHIFT, ARCH_MMU_FLAG_CACHED);
+
+ /* add dram to mmu_initial_mappings for pa to va lookup */
+ mmu_initial_mappings[DRAM_MAPPING_IDX].phys = DRAM_BASE_PHY;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].virt = DRAM_BASE_VIRT;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].size = dram_sz;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].flags = 0;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].name = "dram";
+
+ pmm_add_arena(&dram_arena);
+
+#else
+ novm_add_arena("sram", SRAM_BASE_PHYS, SRAM_BASE_SIZE);
+#endif /* WITH_KERNEL_VM */
+}
+
+void *init_bootarg_buffer(void)
+{
+ void *bootarg = (void *)paddr_to_kvaddr(DRAM_BOOTARG_BASE);
+ memset((void *)bootarg, 0, DRAM_BOOTARG_SIZE);
+
+ return bootarg;
+}
+
+void *bl2_set_boot_args(uint32_t boot_mode)
+{
+ BOOT_ARGUMENT *bl2_bootarg = (BOOT_ARGUMENT *)init_bootarg_buffer();
+
+ bl2_bootarg->maggic_number = BOOT_ARGUMENT_MAGIC;
+ bl2_bootarg->boot_mode = boot_mode;
+ bl2_bootarg->boot_reason = g_boot_reason;
+ bl2_bootarg->rgu_mode = g_rgu_mode;
+ bl2_bootarg->ddr_reserve_enable = g_ddr_reserve_enable;
+ bl2_bootarg->ddr_reserve_success = (g_ddr_reserve_ta_err == 0) ? 1 : 0;
+ bl2_bootarg->ddr_reserve_ready = g_ddr_reserve_ready;
+ bl2_bootarg->dram_size = (u64)mt_mem_size();
+ bl2_bootarg->cold_reset = is_pmic_cold_reset();
+
+ dprintf(ALWAYS, "boot mode:%d boot_reason:%d rgu_mode:%d, cold_reset:%d\n",
+ bl2_bootarg->boot_mode, bl2_bootarg->boot_reason,
+ bl2_bootarg->rgu_mode, bl2_bootarg->cold_reset);
+
+ dprintf(ALWAYS, "DDR reserve mode: enable = %d, success = %d, ready = %d\n",
+ bl2_bootarg->ddr_reserve_enable,
+ bl2_bootarg->ddr_reserve_success, bl2_bootarg->ddr_reserve_ready);
+ return (void *)bl2_bootarg;
+}
+
+void platform_memory_init(void)
+{
+ mt_mem_init();
+ setup_plat_mem();
+}
+
+void platform_early_init_blx(void)
+{
+#if !CFG_FPGA_PLATFORM
+ mt_pll_init();
+
+ /* retry 3 times for pmic wrapper init */
+ pwrap_init_preloader();
+
+ /* init PMIC */
+ pmic_init();
+
+ pmic_init_setting();
+
+ mt_pll_post_init();
+
+ mt_clkbuf_init();
+
+ /* TODO: confirm audio clk enable in BL2 or BL33 */
+ mt_audio_clk_enable();
+
+ mt_dcm_init();
+#endif
+
+ mtk_timer_init();
+
+ bgr_init();
+
+ dprintf(CRITICAL, "BL2 Build Time: %s %s\n", __DATE__, __TIME__);
+}
+
+void platform_set_aarch64_reset_vector(ulong vector)
+{
+ writel(vector, MP0_MISC_CONFIG2);
+}
+
+void mtk_wdt_early_init(void)
+{
+ /* now the dram not init done, can not use dram to cache g_bootarg */
+ check_ddr_reserve_status();
+ g_boot_reason = mtk_wdt_check_status();
+ g_rgu_mode = readl(MTK_WDT_MODE);
+ dprintf(INFO, "g_boot_reason:0x%x g_rgu_mode:0x%x\n", g_boot_reason, g_rgu_mode);
+}
+
+#ifdef PMIC_CHIP_MT6389
+int platform_get_mcp_id(u8 *id, u32 len, u32 *fw_id_len)
+{
+ int ret = -1;
+
+ if(len == 0)
+ return -1;
+
+ memset(id, 0, len);
+
+#ifdef BOOT_DEV_NAND
+ ret = nand_get_device_id(id, len);
+#endif
+
+ return ret;
+}
+#endif
diff --git a/src/bsp/lk/platform/mt2731/platform_bl33.c b/src/bsp/lk/platform/mt2731/platform_bl33.c
new file mode 100644
index 0000000..b910776
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/platform_bl33.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#include <arch/ops.h>
+#include <debug.h>
+#include <err.h>
+#if WITH_KERNEL_VM
+#include <kernel/vm.h>
+#else
+#include <kernel/novm.h>
+#endif
+#include <lib/kcmdline.h>
+#include <platform.h>
+#include <platform/mt2731.h>
+#include <platform/mt_gpio.h>
+#include <trace.h>
+#include <boot_args.h>
+#include <platform/mtk_wdt.h>
+#include <platform/platform_blx.h>
+#include <platform/mtk_gce.h>
+
+#define LOCAL_TRACE 0
+
+#if WITH_KERNEL_VM
+#define PROG_MEM_MAPPING_IDX 0
+#define GIC_PERIPHERAL_MAPPING_IDX 1
+#define SRAM_MAPPING_IDX 2
+#define DRAM_MAPPING_IDX 3
+
+BOOT_ARGUMENT *g_boot_arg;
+extern ulong lk_boot_args[4];
+
+/* initial memory mappings. parsed by start.S */
+struct mmu_initial_mapping mmu_initial_mappings[] = {
+ {
+ .phys = MEMORY_BASE_PHYS,
+ .virt = MEMORY_BASE_VIRT,
+ .size = MEMORY_APERTURE_SIZE,
+ .flags = 0,
+ .name = "prog"
+ },
+ {
+ .phys = GIC_PERIPHERAL_BASE_PHYS,
+ .virt = GIC_PERIPHERAL_BASE_VIRT,
+ .size = GIC_PERIPHERAL_BASE_SIZE,
+ .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE
+ },
+ {
+ .phys = MD1_BASE_PHYS,
+ .virt = MD1_BASE_VIRT,
+ .size = MD1_BASE_SIZE,
+ .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE
+ },
+ /* reserved for internal sram */
+ { 0 },
+ /* reserved for dram */
+ { 0 },
+ /* null entry to terminate the list */
+ { 0 }
+};
+
+static pmm_arena_t dram_arena = {
+ .name = "dram",
+ .base = DRAM_ARENA_BASE,
+ .size = DRAM_ARENA_SIZE,
+ .flags = PMM_ARENA_FLAG_KMAP,
+ .priority = 0,
+};
+#endif /* WITH_KERNEL_VM */
+
+static inline size_t query_plat_dram_sz(void)
+{
+ return BL33_DRAM_SZ_MB * 0x100000UL;
+}
+
+static void setup_plat_mem(void)
+{
+#if WITH_KERNEL_VM
+ size_t unmap_dram_sz, mapped_mem_sz;
+ size_t unmap_dram_start_pa, unmap_dram_start_va;
+
+ /* dram arena memory are already mapped in mmu initial mappings */
+ pmm_add_arena(&dram_arena);
+
+ arch_mmu_map(SRAM_BASE_VIRT, SRAM_BASE_PHYS,
+ SRAM_BASE_SIZE >> PAGE_SIZE_SHIFT, ARCH_MMU_FLAG_CACHED);
+
+ /* add internal sram to mmu_initial_mappings for pa to va lookup */
+ mmu_initial_mappings[SRAM_MAPPING_IDX].phys = SRAM_BASE_PHYS;
+ mmu_initial_mappings[SRAM_MAPPING_IDX].virt = SRAM_BASE_VIRT;
+ mmu_initial_mappings[SRAM_MAPPING_IDX].size = SRAM_BASE_SIZE;
+ mmu_initial_mappings[SRAM_MAPPING_IDX].flags = 0;
+ mmu_initial_mappings[SRAM_MAPPING_IDX].name = "sram";
+
+ /*
+ * Except the dram range for uncached memory pool, all other dram ranges
+ * are all mapped as cacheable memory.
+ */
+
+ /* BL33 initial mapping already maps a portion of dram, map the rest here */
+ unmap_dram_start_pa = MEMORY_BASE_PHYS + MEMORY_APERTURE_SIZE;
+ unmap_dram_start_va = MEMORY_BASE_VIRT + MEMORY_APERTURE_SIZE;
+
+ mapped_mem_sz = UNCACHED_MEMPOOL_ADDR - unmap_dram_start_va;
+ arch_mmu_map(unmap_dram_start_va, unmap_dram_start_pa,
+ mapped_mem_sz >> PAGE_SIZE_SHIFT, ARCH_MMU_FLAG_CACHED);
+ arch_mmu_map(UNCACHED_MEMPOOL_ADDR, unmap_dram_start_pa + mapped_mem_sz,
+ UNCACHED_MEMPOOL_SIZE >> PAGE_SIZE_SHIFT,
+ ARCH_MMU_FLAG_UNCACHED);
+
+ unmap_dram_sz = query_plat_dram_sz() - MEMORY_APERTURE_SIZE;
+ mapped_mem_sz += UNCACHED_MEMPOOL_SIZE;
+ arch_mmu_map(UNCACHED_MEMPOOL_ADDR + UNCACHED_MEMPOOL_SIZE,
+ unmap_dram_start_pa + mapped_mem_sz,
+ (unmap_dram_sz - mapped_mem_sz) >> PAGE_SIZE_SHIFT,
+ ARCH_MMU_FLAG_CACHED);
+
+ /* add dram to mmu_initial_mappings for pa to va lookup */
+ mmu_initial_mappings[DRAM_MAPPING_IDX].phys = unmap_dram_start_pa;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].virt = unmap_dram_start_va;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].size = unmap_dram_sz;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].flags = 0;
+ mmu_initial_mappings[DRAM_MAPPING_IDX].name = "dram";
+#else
+ novm_add_arena("sram", SRAM_BASE_PHYS, SRAM_BASE_SIZE);
+#endif /* WITH_KERNEL_VM */
+}
+
+void platform_get_bootargs(void)
+{
+ g_boot_arg = (BOOT_ARGUMENT *)paddr_to_kvaddr(lk_boot_args[0]);
+ if (!g_boot_arg) {
+ dprintf(CRITICAL, "%s g_boot_arg failed lk_boot_args[0]: 0x%lx, force map DRAM_BOOTARG_BASE: 0x%lx\n",
+ __func__, lk_boot_args[0], DRAM_BOOTARG_BASE);
+ g_boot_arg = (BOOT_ARGUMENT *)paddr_to_kvaddr(DRAM_BOOTARG_BASE);
+ }
+ if((g_boot_arg == NULL) ||
+ (*(unsigned int *)g_boot_arg != BOOT_ARGUMENT_MAGIC)) {
+ dprintf(CRITICAL, "%s failed (g_boot_arg:%p)\n", __func__, g_boot_arg);
+ g_boot_arg = NULL;
+ return;
+ }
+
+ dprintf(ALWAYS, "%s pa:0x%lx va:%p dram size:0x%llx\n",
+ __func__, lk_boot_args[0], g_boot_arg, g_boot_arg->dram_size);
+}
+
+void platform_memory_init(void)
+{
+ setup_plat_mem();
+ platform_get_bootargs();
+ /* Load gce instructions to sram and enable GCE thread */
+ mtk_gce_start();
+}
+
+void platform_early_init_blx(void)
+{
+ /* init gpio */
+ mt_gpio_init();
+
+ dprintf(CRITICAL, "BL33 Build Time: %s %s\n", __DATE__, __TIME__);
+}
+
+int platform_wdt_boot_check(void)
+{
+ unsigned int wdt_sta = g_boot_arg->boot_reason;
+ unsigned int rgu_mode = g_boot_arg->rgu_mode;
+
+ if (wdt_sta & (MTK_WDT_STATUS_HWWDT_RST|MTK_WDT_STATUS_SWWDT_RST|MTK_WDT_STATUS_SPMWDT_RST)) {
+ if (rgu_mode & MTK_WDT_MODE_AUTO_RESTART)
+ {
+ /* HW/SW reboot, and auto restart is set, means bypass power key */
+ dprintf (INFO, "SW reset with bypass power key flag\n");
+ return WDT_BY_PASS_PWK_REBOOT;
+ } else {
+ dprintf (INFO, "SW reset without bypass power key flag\n");
+ return WDT_NORMAL_REBOOT;
+ }
+ }
+ return WDT_NOT_WDT_REBOOT;
+}
+
+boot_reason_t platform_boot_status(void)
+{
+ if (platform_wdt_boot_check() == WDT_NORMAL_REBOOT) {
+ dprintf(INFO, "WDT normal boot!\n");
+ return BR_WDT;
+ } else if(platform_wdt_boot_check() == WDT_BY_PASS_PWK_REBOOT) {
+ dprintf(INFO, "WDT reboot bypass power key!\n");
+ return BR_WDT_BY_PASS_PWK;
+ }
+ dprintf(CRITICAL, "BL33 check Boot status-WDT\n");
+
+ /*TODO implement rtc_boot_check*/
+ /*TODO implement mtk_detect_key*/
+ /*TODO implement usb_accessory_in*/
+ return BR_UNKNOWN;
+}
+
diff --git a/src/bsp/lk/platform/mt2731/rules.mk b/src/bsp/lk/platform/mt2731/rules.mk
new file mode 100644
index 0000000..5916693
--- /dev/null
+++ b/src/bsp/lk/platform/mt2731/rules.mk
@@ -0,0 +1,151 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE := $(LOCAL_DIR)
+COMMON_PLAT := $(LOCAL_DIR)/../mediatek/common
+
+ARCH ?= arm64
+ARM_CPU ?= cortex-a53
+WITH_SMP ?= 0
+WITH_KERNEL_VM ?= 1
+
+LK_HEAP_IMPLEMENTATION ?= miniheap
+
+GLOBAL_INCLUDES += -I$(LK_TOP_DIR)/include \
+
+MODULE_SRCS += \
+ $(COMMON_PLAT)/boot_mode.c \
+ $(LOCAL_DIR)/fixup/plat_fixup.c \
+ $(LOCAL_DIR)/platform.c \
+ $(LOCAL_DIR)/debug.c \
+ $(LOCAL_DIR)/interrupts.c \
+ $(LOCAL_DIR)/plat_dbg_info.c \
+ $(LOCAL_DIR)/../mediatek/common/fastboot_oem_cmd/oem_ab_cmd.c \
+ $(LOCAL_DIR)/../mediatek/common/fastboot_oem_cmd/oem_efuse_cmd.c \
+ $(LOCAL_DIR)/../mediatek/common/fastboot_oem_cmd/oem_mac_cmd.c \
+
+ifeq ($(NAND_DEBUG),1)
+MODULE_SRCS += $(LOCAL_DIR)/../mediatek/common/fastboot_oem_cmd/oem_nand_cmd.c
+endif
+
+MACH_TYPE := 2731
+
+ifeq ($(WITH_KERNEL_VM),1)
+ifeq ($(ARCH),arm64)
+KERNEL_ASPACE_BASE ?= 0xfffffff000000000
+KERNEL_ASPACE_SIZE ?= 0x0000000180000000
+MMU_IDENT_SIZE_SHIFT ?= 32
+endif
+endif
+
+# mempool configuration
+ifeq ($(WITH_KERNEL_VM),1)
+
+ifeq ($(ARCH),arm64)
+CACHED_MEMPOOL_ADDR ?= 0xfffffff044800000
+CACHED_MEMPOOL_SIZE ?= 0x03800000 # 56MB
+UNCACHED_MEMPOOL_ADDR ?= 0xfffffff04FE00000
+UNCACHED_MEMPOOL_SIZE ?= 0x200000 # 2MB
+BL33_ADDR ?= 0xfffffff042110000
+MD_ADDR ?= 0xfffffff048000000
+HSM_OS_ADDR ?= 0xfffffff042080000
+AP_MD_SHARE_NC ?= 0xfffffff044000000
+AP_MD_SHARE_C ?= 0xfffffff046000000
+endif
+
+ifeq ($(ARCH),arm)
+CACHED_MEMPOOL_ADDR ?= 0x48000000
+CACHED_MEMPOOL_SIZE ?= 0x03800000 # 56MB
+UNCACHED_MEMPOOL_ADDR ?= 0x4B800000
+UNCACHED_MEMPOOL_SIZE ?= 0x200000 # 2MB
+BL33_ADDR ?= 0x42110000
+MD_ADDR ?= 0x48000000
+HSM_OS_ADDR ?= 0x42080000
+AP_MD_SHARE_NC ?= 0x44000000
+AP_MD_SHARE_C ?= 0x46000000
+endif
+
+else
+CACHED_MEMPOOL_ADDR ?= 0 # don't care this when mmu is off
+CACHED_MEMPOOL_SIZE ?= 0
+UNCACHED_MEMPOOL_ADDR ?= 0x4FE00000
+UNCACHED_MEMPOOL_SIZE ?= 0x200000 # 2MB
+BL33_ADDR ?= 0x42110000
+MD_ADDR ?= 0x48000000
+HSM_OS_ADDR ?= 0x42080000
+AP_MD_SHARE_NC ?= 0x44000000
+AP_MD_SHARE_C ?= 0x46000000
+endif
+
+# LK build as BL2 or BL33 setting
+LK_AS_BL33 ?= 0
+
+# CPU FREQ: CA35_FREQ_806MHZ (0.8G), CA35_FREQ_1196MHZ (1.2G)
+CA35_FREQ ?= CA35_FREQ_1196MHZ
+
+MODULE_DEPS += \
+ dev/interrupt/arm_gic_v3 \
+ dev/timer/arm_generic \
+ lib/bio \
+ lib/fastboot \
+ lib/fdt \
+ lib/fit \
+ lib/kcmdline \
+ lib/mempool \
+ lib/partition \
+
+# if BOOTAPP is not specified elsewhere, and AVB is required, choose 'avbboot'
+ifeq ($(strip $(SECURE_BOOT_ENABLE)),yes)
+ifeq ($(strip $(SECURE_BOOT_TYPE)),avb)
+BOOTAPP ?= avbboot
+endif
+endif
+
+# otherwise, choose 'fitboot'
+BOOTAPP ?= fitboot
+
+MODULES += app/$(BOOTAPP)
+
+ifeq ($(WITH_KERNEL_VM),1)
+GLOBAL_DEFINES += MMU_IDENT_SIZE_SHIFT=$(MMU_IDENT_SIZE_SHIFT)
+else
+GLOBAL_DEFINES += NOVM_MAX_ARENAS=2
+endif
+
+ifeq ($(SECURE_BOOT_ENABLE),yes)
+GLOBAL_DEFINES += CUSTOM_DEFAULT_STACK_SIZE=8192
+ifeq ($(MD_VERIFY),yes)
+GLOBAL_DEFINES += MTK_SECURITY_SW_SUPPORT
+endif
+endif
+
+# for AEE
+GLOBAL_DEFINES += MTK_PMIC_FULL_RESET
+
+# for user load
+ifeq ($(BUILD_LOAD_TYPE),user)
+GLOBAL_DEFINES += MTK_BUILD_USER_LOAD
+endif
+
+GLOBAL_DEFINES += \
+ RAMBASE=$(RAMBASE) \
+ MACH_TYPE=$(MACH_TYPE) \
+ PLATFORM_SUPPORTS_PANIC_SHELL=1 \
+ WITH_NO_FP=1 \
+ CACHED_MEMPOOL_ADDR=$(CACHED_MEMPOOL_ADDR) \
+ CACHED_MEMPOOL_SIZE=$(CACHED_MEMPOOL_SIZE) \
+ UNCACHED_MEMPOOL_ADDR=$(UNCACHED_MEMPOOL_ADDR) \
+ UNCACHED_MEMPOOL_SIZE=$(UNCACHED_MEMPOOL_SIZE) \
+ BL33_ADDR=$(BL33_ADDR) \
+ MD_ADDR=$(MD_ADDR) \
+ HSM_OS_ADDR=$(HSM_OS_ADDR) \
+ AP_MD_SHARE_NC=$(AP_MD_SHARE_NC) \
+ AP_MD_SHARE_C=$(AP_MD_SHARE_C) \
+ $(CA35_FREQ) \
+ NAND_DEBUG=$(NAND_DEBUG) \
+ LK_AS_BL33=$(LK_AS_BL33)
+
+LINKER_SCRIPT += \
+ $(BUILDDIR)/system-onesegment.ld
+
+include $(LOCAL_DIR)/bl2_bl33_options.mk
+include make/module.mk $(LOCAL_DIR)/drivers/rules.mk