[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/lk/target/aud8516m3v5-emmc-32b-avs-test/custom_emi.c b/src/bsp/lk/target/aud8516m3v5-emmc-32b-avs-test/custom_emi.c
new file mode 100644
index 0000000..daa433f
--- /dev/null
+++ b/src/bsp/lk/target/aud8516m3v5-emmc-32b-avs-test/custom_emi.c
@@ -0,0 +1,172 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2008
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_emi.c
+ *
+ * Project:
+ * --------
+ * Android
+ *
+ * Description:
+ * ------------
+ * This Module defines the EMI (external memory interface) related setting.
+ *
+ * Author:
+ * -------
+ * EMI auto generator V0.01
+ *
+ * Memory Device database last modified on 2015/6/26
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ *------------------------------------------------------------------------------
+ * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * This file is generated by EMI Auto-gen Tool.
+ * Please do not modify the content directly!
+ * It could be overwritten!
+ *============================================================================
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include <platform/emi.h>
+
+#define NUM_EMI_RECORD (1)
+int num_of_emi_records = NUM_EMI_RECORD;
+
+EMI_SETTINGS emi_settings[NUM_EMI_RECORD] = {
+#if defined (COMMON_DDR3_16BIT)
+ {
+ 0x1, /* sub_version */
+ 0x0004, /* TYPE */
+ 0, /* EMMC ID/FW ID checking length */
+ 0, /* FW length */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
+ 0x00002010, /* EMI_CONA_VAL */
+ 0x00000003, /* EMI_CONH_VAL */
+ { {
+ 0x09090640, /* U 00 */
+ 0x19491401, /* U 01 */
+ 0x0B090201, /* U 02 */
+ 0x550C0306, /* U 03 */
+ 0x23566560, /* U 04 */
+ 0x00000908, /* U 05 */
+ 0x14140000, /* U 06 */
+ 0x00000000 /* U 07 */
+ }
+ },
+ {0x20000000,0,0,0}, /* DRAM RANK SIZE */
+ 0x04210000, /* EMI_CONF_VAL */
+ 0x00000000, /* CHN0_EMI_CONA_VAL */
+ 0x00000000, /* CHN1_EMI_CONA_VAL */
+ 0x0, /* dram_cbt_mode */
+ {0,0,0,0,0,0}, /* reserved 6 */
+ 0x40000000, /* PCDDR3_MODE_REG5 */
+ 0, /* PIN_MUX_TYPE for tablet */
+ } ,
+#else
+ {
+ 0x1, /* sub_version */
+ 0x0003, /* TYPE */
+ 0, /* EMMC ID/FW ID checking length */
+ 0, /* FW length */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
+ 0x0002a052, /* EMI_CONA_VAL */
+ 0x00000003, /* EMI_CONH_VAL */
+ {
+ {
+ 0x09090640, /* U 00 */
+ 0x19491401, /* U 01 */
+ 0x0B090201, /* U 02 */
+ 0x550C0306, /* U 03 */
+ 0x23566560, /* U 04 */
+ 0x00000908, /* U 05 */
+ 0x14140000, /* U 06 */
+ 0x00000000 /* U 07 */
+ }
+ },
+ {0x40000000,0x40000000,0,0}, /* DRAM RANK SIZE */
+ 0x04210000, /* EMI_CONF_VAL */
+ 0x00000000, /* CHN0_EMI_CONA_VAL */
+ 0x00000000, /* CHN1_EMI_CONA_VAL */
+ 0x0, /* dram_cbt_mode */
+ {0,0,0,0,0,0}, /* reserved 6 */
+ 0x00000006, /* LPDDR3_MODE_REG5 */
+ 2, /* PIN_MUX_TYPE for tablet */
+ } ,
+#endif
+};
+
+EMI_SETTINGS default_emi_setting = {
+ 0x1, /* sub_version */
+ 0x0004, /* TYPE */
+ 0, /* EMMC ID/FW ID checking length */
+ 0, /* FW length */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
+ 0x00002010, /* EMI_CONA_VAL */
+ 0x00000003, /* EMI_CONH_VAL */
+ { {
+ 0x09090640, /* U 00 */
+ 0x19491401, /* U 01 */
+ 0x0B090201, /* U 02 */
+ 0x550C0306, /* U 03 */
+ 0x23566560, /* U 04 */
+ 0x00000908, /* U 05 */
+ 0x14140000, /* U 06 */
+ 0x00000000
+ }
+ }, /* U 07 */
+ {0x20000000,0,0,0}, /* DRAM RANK SIZE */
+ 0x04210000, /* EMI_CONF_VAL */
+ 0x00000000, /* CHN0_EMI_CONA_VAL */
+ 0x00000000, /* CHN1_EMI_CONA_VAL */
+ 0x0, /* dram_cbt_mode */
+ {0,0,0,0,0,0}, /* reserved 6 */
+ 0x40000000, /* PCDDR3_MODE_REG5 */
+ 0, /* PIN_MUX_TYPE for tablet */
+};
+