[Feature]add MT2731_MP2_MR2_SVN388 baseline version

Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/trustzone/teeloader/LICENSE b/src/bsp/trustzone/teeloader/LICENSE
new file mode 100644
index 0000000..6e16090
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/LICENSE
@@ -0,0 +1,31 @@
+Copyright Statement:
+
+This software/firmware and related documentation ("MediaTek Software") are
+protected under relevant copyright laws. The information contained herein is
+confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+the prior written permission of MediaTek inc. and/or its licensors, any
+reproduction, modification, use or disclosure of MediaTek Software, and
+information contained herein, in whole or in part, shall be strictly
+prohibited.
+
+MediaTek Inc. (C) 2017. All rights reserved.
+
+BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
diff --git a/src/bsp/trustzone/teeloader/README b/src/bsp/trustzone/teeloader/README
new file mode 100644
index 0000000..78f8430
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/README
@@ -0,0 +1,2 @@
+The "tz" directory is intended for Mediatek solution TrustZone.
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/Makefile b/src/bsp/trustzone/teeloader/mt2635/Makefile
new file mode 100644
index 0000000..9a10e2c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/Makefile
@@ -0,0 +1,71 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/device_apc.c \
+	$(DIR_SRC)/security/tz_emi_mpu.c \
+	$(DIR_SRC)/security/tz_init.c \
+	$(DIR_SRC)/security/tz_sec_cfg.c \
+	$(DIR_SRC)/security/seclib_dummy.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+	$(DIR_SRC)/security/tz_tbase.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt/cust_tee.mak
new file mode 100644
index 0000000..3818332
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt/cust_tee.mak
@@ -0,0 +1,7 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
diff --git a/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt_tee/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt_tee/cust_tee.mak
new file mode 100644
index 0000000..5bf9327
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/custom/auto2635evb2_ivt_tee/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0xE00000
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2635/default.mak b/src/bsp/trustzone/teeloader/mt2635/default.mak
new file mode 100644
index 0000000..b9543d1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/default.mak
@@ -0,0 +1,11 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT6735
+CFG_ATF_LOG_SUPPORT := 1
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x4FFC0000
+CFG_TEE_SECMEM_SIZE = 0xE00000
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2635/feature.mak b/src/bsp/trustzone/teeloader/mt2635/feature.mak
new file mode 100644
index 0000000..83fbf8d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/feature.mak
@@ -0,0 +1,43 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2635/include/device_apc.h
new file mode 100644
index 0000000..d9563f4
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/device_apc.h
@@ -0,0 +1,217 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __DEVICE_APC_H__
+#define __DEVICE_APC_H__
+
+#include "typedefs.h"
+
+#define DEVAPC0_AO_BASE         0x10007000      // for AP
+#define DEVAPC0_PD_BASE         0x10207000      // for AP
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define DEVAPC0_D0_APC_0            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0000))
+#define DEVAPC0_D0_APC_1            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0004))
+#define DEVAPC0_D0_APC_2            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0008))
+#define DEVAPC0_D0_APC_3            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x000C))
+#define DEVAPC0_D0_APC_4            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0010))
+#define DEVAPC0_D0_APC_5            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0014))
+#define DEVAPC0_D0_APC_6            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0018))
+#define DEVAPC0_D0_APC_7            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x001C))
+#define DEVAPC0_D0_APC_8            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+
+#define DEVAPC0_D1_APC_0            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0100))
+#define DEVAPC0_D1_APC_1            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0104))
+#define DEVAPC0_D1_APC_2            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0108))
+#define DEVAPC0_D1_APC_3            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x010C))
+#define DEVAPC0_D1_APC_4            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0110))
+#define DEVAPC0_D1_APC_5            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0114))
+#define DEVAPC0_D1_APC_6            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0118))
+#define DEVAPC0_D1_APC_7            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x011C))
+#define DEVAPC0_D1_APC_8            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+
+#define DEVAPC0_D2_APC_0            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0200))
+#define DEVAPC0_D2_APC_1            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0204))
+#define DEVAPC0_D2_APC_2            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0208))
+#define DEVAPC0_D2_APC_3            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x020C))
+#define DEVAPC0_D2_APC_4            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0210))
+#define DEVAPC0_D2_APC_5            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0214))
+#define DEVAPC0_D2_APC_6            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0218))
+#define DEVAPC0_D2_APC_7            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x021C))
+#define DEVAPC0_D2_APC_8            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+
+#define DEVAPC0_D3_APC_0            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0300))
+#define DEVAPC0_D3_APC_1            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0304))
+#define DEVAPC0_D3_APC_2            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0308))
+#define DEVAPC0_D3_APC_3            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x030C))
+#define DEVAPC0_D3_APC_4            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0310))
+#define DEVAPC0_D3_APC_5            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0314))
+#define DEVAPC0_D3_APC_6            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0318))
+#define DEVAPC0_D3_APC_7            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x031C))
+#define DEVAPC0_D3_APC_8            ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+
+#if defined(MACH_TYPE_MT6735)
+
+#define DEVAPC0_MAS_DOM_0           ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0A00))
+#define DEVAPC0_MAS_DOM_1           ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0A04))
+#define DEVAPC0_MAS_DOM_2           ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0A08))
+#define DEVAPC0_MAS_SEC             ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0B00))
+
+#else
+
+#error "Wrong MACH type"
+
+#endif
+
+#define DEVAPC0_APC_CON             ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F00))
+#define DEVAPC0_APC_LOCK_0          ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F04))
+#define DEVAPC0_APC_LOCK_1          ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F08))
+#define DEVAPC0_APC_LOCK_2          ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F0C))
+#define DEVAPC0_APC_LOCK_3          ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F10))
+#define DEVAPC0_APC_LOCK_4          ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F14))
+
+#define DEVAPC0_PD_APC_CON          ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F00))
+#define DEVAPC0_D0_VIO_MASK_0       ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0000))
+#define DEVAPC0_D0_VIO_MASK_1       ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0004))
+#define DEVAPC0_D0_VIO_MASK_2       ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0008))
+#define DEVAPC0_D0_VIO_MASK_3       ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x000C))
+#define DEVAPC0_D0_VIO_MASK_4       ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0010))
+#define DEVAPC0_D0_VIO_STA_0        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0400))
+#define DEVAPC0_D0_VIO_STA_1        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0404))
+#define DEVAPC0_D0_VIO_STA_2        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0408))
+#define DEVAPC0_D0_VIO_STA_3        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x040C))
+#define DEVAPC0_D0_VIO_STA_4        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0410))
+#define DEVAPC0_VIO_DBG0            ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0900))
+#define DEVAPC0_VIO_DBG1            ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0904))
+
+#define DEVAPC0_DEC_ERR_CON         ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F80))
+#define DEVAPC0_DEC_ERR_ADDR        ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F84))
+#define DEVAPC0_DEC_ERR_ID          ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F88))
+
+
+#define DEVAPC_APC_CON_CTRL         (0x1 << 0)
+#define DEVAPC_APC_CON_EN           0x1
+#define MASTER_MSDC0                4
+#define MASTER_SPI0                 7
+
+typedef enum {
+    NON_SECURE_TRAN = 0,
+    SECURE_TRAN,
+} E_TRANSACTION;
+
+
+///* DOMAIN_SETUP */
+
+
+#define DOMAIN_0                      0
+#define DOMAIN_1                      1
+#define DOMAIN_2                      2
+#define DOMAIN_3                      3
+
+#if defined(MACH_TYPE_MT6735)
+
+#define DOMAIN_4                      4
+#define DOMAIN_5                      5
+#define DOMAIN_6                      6
+
+#define CONN2AP                      (0xf << 16)//index12   DEVAPC0_MAS_DOM_1
+#define MD1_DOMAIN                   (0xf << 24)//index14   DEVAPC0_MAS_DOM_1
+#define MD3_DOMAIN                   (0xf <<  8)//index18   DEVAPC0_MAS_DOM_2
+#define GPU                          (0xf << 20)//index21   DEVAPC0_MAS_DOM_2
+
+#else
+
+#error "Wrong MACH type"
+
+#endif
+
+static inline unsigned int uffs(unsigned int x)
+{
+    unsigned int r = 1;
+
+    if (!x)
+        return 0;
+    if (!(x & 0xffff)) {
+        x >>= 16;
+        r += 16;
+    }
+    if (!(x & 0xff)) {
+        x >>= 8;
+        r += 8;
+    }
+    if (!(x & 0xf)) {
+        x >>= 4;
+        r += 4;
+    }
+    if (!(x & 3)) {
+        x >>= 2;
+        r += 2;
+    }
+    if (!(x & 1)) {
+        x >>= 1;
+        r += 1;
+    }
+    return r;
+}
+
+#define reg_read16(reg)          __raw_readw(reg)
+#define reg_read32(reg)          __raw_readl(reg)
+#define reg_write16(reg,val)     __raw_writew(val,reg)
+#define reg_write32(reg,val)     __raw_writel(val,reg)
+
+#define reg_set_bits(reg,bs)     ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs)     ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+     do {    \
+         volatile unsigned int tv = reg_read32(reg); \
+         tv &= ~(field); \
+         tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+         reg_write32(reg,tv); \
+     } while(0)
+
+#define reg_get_field(reg,field,val) \
+     do {    \
+         volatile unsigned int tv = reg_read32(reg); \
+         val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+     } while(0)
+
+extern void device_APC_dom_setup(void);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/platform.h b/src/bsp/trustzone/teeloader/mt2635/include/platform.h
new file mode 100644
index 0000000..96b232b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/platform.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR	(0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE	(0x10000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE               (0x500000 + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE               (0x500000)
+#endif
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE           (0x600000)
+#define CFG_MAX_TEE_DRAM_SIZE           (160 * 1024 * 1024) /* TEE max DRAM size is 160MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE           (0)
+#define CFG_MAX_TEE_DRAM_SIZE           (0) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/print.h b/src/bsp/trustzone/teeloader/mt2635/include/print.h
new file mode 100644
index 0000000..6f7f93a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+extern void print(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/string.h b/src/bsp/trustzone/teeloader/mt2635/include/string.h
new file mode 100644
index 0000000..d211265
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2635/include/typedefs.h
new file mode 100644
index 0000000..a78ef5c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/typedefs.h
@@ -0,0 +1,178 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE                       0
+#endif
+#ifndef TRUE
+#define TRUE                        1
+#endif
+
+#ifndef NULL
+#define NULL    0
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define printf	print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_mpu.h
new file mode 100644
index 0000000..557b8ee
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+
+#define SECURE_OS_MPU_REGION_ID    0
+#define ATF_MPU_REGION_ID          1
+
+#define LOCK                1
+#define UNLOCK              0
+
+#if defined(MACH_TYPE_MT6735) || defined(MACH_TYPE_MT6753) || defined(MACH_TYPE_MT6737T)
+#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | ((((d7) << 9) | ((d6) << 6) | ((d5) << 3) | (d4)) << 16) | (lock << 15))
+#else
+#define SET_ACCESS_PERMISSON(lock, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))  | (lock << 15))
+#endif
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_reg.h
new file mode 100644
index 0000000..a1f0cfb
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/tz_emi_reg.h
@@ -0,0 +1,276 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define IO_PHYS            	    0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00203000)
+
+/*EMI PSRAM (NOR) and DRAM control registers*/
+#define EMI_CONA                 ((P_U32)(EMI_BASE+0x0000))  /* EMI control register for bank 0 */
+#define EMI_CONB                 ((P_U32)(EMI_BASE+0x0008))  /* EMI control register for bank 1 */
+#define EMI_CONC                 ((P_U32)(EMI_BASE+0x0010))  /* EMI control register for bank 2 */
+#define EMI_COND                 ((P_U32)(EMI_BASE+0x0018))  /* EMI control register for bank 3 */
+#define EMI_CONE                 ((P_U32)(EMI_BASE+0x0020))  /* EMI control register for bank 0 */
+#define EMI_CONF                 ((P_U32)(EMI_BASE+0x0028))  /* EMI control register for bank 1 */
+#define EMI_CONG                 ((P_U32)(EMI_BASE+0x0030))  /* EMI control register for bank 0 */
+#define EMI_CONH                 ((P_U32)(EMI_BASE+0x0038))  /* EMI control register for bank 1 */
+#define EMI_CONI                 ((P_U32)(EMI_BASE+0x0040))  /* EMI control register 0 for Mobile-RAM */
+#define EMI_CONJ                 ((P_U32)(EMI_BASE+0x0048))  /* EMI control register 1 for Mobile-RAM */
+#define EMI_CONK                 ((P_U32)(EMI_BASE+0x0050))  /* EMI control register 2 for Mobile-RAM */
+#define EMI_CONL                 ((P_U32)(EMI_BASE+0x0058))  /* EMI control register 3 for Mobile-RAM */
+#define EMI_CONM                 ((P_U32)(EMI_BASE+0x0060))
+#define EMI_CONN                 ((P_U32)(EMI_BASE+0x0068))
+#define CAL_EN                   (1 << 8)
+#define EMI_GENA                 ((P_U32)(EMI_BASE+0x0070))
+#define EMI_REMAP                 EMI_GENA
+#define EMI_DRCT                 ((P_U32)(EMI_BASE+0x0078))
+#define EMI_DDRV                 ((P_U32)(EMI_BASE+0x0080))
+#define EMI_GEND                 ((P_U32)(EMI_BASE+0x0088))
+#define EMI_PPCT                 ((P_U32)(EMI_BASE+0x0090)) /* EMI Performance and Power Control Register */
+
+#define EMI_DLLV                 ((P_U32)(EMI_BASE+0x00A0))
+
+#define EMI_DFTC                 ((P_U32)(EMI_BASE+0x00F0))
+#define EMI_DFTD                 ((P_U32)(EMI_BASE+0x00F8))
+
+/* EMI bandwith filter and MPU control registers */
+#define EMI_ARBA                 ((P_U32)(EMI_BASE+0x0100))
+#define EMI_ARBB                 ((P_U32)(EMI_BASE+0x0108))
+#define EMI_ARBC                 ((P_U32)(EMI_BASE+0x0110))
+#define EMI_ARBD                 ((P_U32)(EMI_BASE+0x0118))
+#define EMI_ARBE                 ((P_U32)(EMI_BASE+0x0120))
+#define EMI_ARBF                 ((P_U32)(EMI_BASE+0x0128))
+#define EMI_ARBG                 ((P_U32)(EMI_BASE+0x0130))
+
+#define EMI_SLCT                 ((P_U32)(EMI_BASE+0x0150))
+#define EMI_ABCT	             ((P_U32)(EMI_BASE+0x0158))
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA                 ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB                 ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC                 ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD                 ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE                ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF	        ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG	        ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH	        ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI	        ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUI_2ND	    ((P_U32)(EMI_BASE+0x01A4))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUJ_2ND	    ((P_U32)(EMI_BASE+0x01AC))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUK_2ND        ((P_U32)(EMI_BASE+0x01B4))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUL_2ND        ((P_U32)(EMI_BASE+0x01BC))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#define EMI_MPUA2		((P_U32)(EMI_BASE+0x0260))
+#define EMI_MPUB2		((P_U32)(EMI_BASE+0x0268))
+#define EMI_MPUC2		((P_U32)(EMI_BASE+0x0270))
+#define EMI_MPUD2		((P_U32)(EMI_BASE+0x0278))
+#define EMI_MPUE2		((P_U32)(EMI_BASE+0x0280))
+#define EMI_MPUF2		((P_U32)(EMI_BASE+0x0288))
+#define EMI_MPUG2		((P_U32)(EMI_BASE+0x0290))
+#define EMI_MPUH2		((P_U32)(EMI_BASE+0x0298))
+#define EMI_MPUI2		((P_U32)(EMI_BASE+0x02A0))
+#define EMI_MPUI2_2ND	((P_U32)(EMI_BASE+0x02A4))
+#define EMI_MPUJ2		((P_U32)(EMI_BASE+0x02A8))
+#define EMI_MPUJ2_2ND	((P_U32)(EMI_BASE+0x02AC))
+#define EMI_MPUK2		((P_U32)(EMI_BASE+0x02B0))
+#define EMI_MPUK2_2ND	((P_U32)(EMI_BASE+0x02B4))
+#define EMI_MPUL2		((P_U32)(EMI_BASE+0x02B8))
+#define EMI_MPUL2_2ND	((P_U32)(EMI_BASE+0x02BC))
+#define EMI_MPUM2		((P_U32)(EMI_BASE+0x02C0))
+#define EMI_MPUN2		((P_U32)(EMI_BASE+0x02C8))
+#define EMI_MPUO2		((P_U32)(EMI_BASE+0x02D0))
+#define EMI_MPUP2		((P_U32)(EMI_BASE+0x02D8))
+#define EMI_MPUQ2		((P_U32)(EMI_BASE+0x02E0))
+#define EMI_MPUR2		((P_U32)(EMI_BASE+0x02E8))
+#define EMI_MPUU2		((P_U32)(EMI_BASE+0x0300))
+#define EMI_MPUY2		((P_U32)(EMI_BASE+0x0320))
+
+/* EMI IO delay, driving and MISC control registers */
+#define EMI_IDLA            ((P_U32)(EMI_BASE+0x0200))
+#define EMI_IDLB            ((P_U32)(EMI_BASE+0x0208))
+#define EMI_IDLC            ((P_U32)(EMI_BASE+0x0210))
+#define EMI_IDLD            ((P_U32)(EMI_BASE+0x0218))
+#define EMI_IDLE            ((P_U32)(EMI_BASE+0x0220))
+#define EMI_IDLF            ((P_U32)(EMI_BASE+0x0228))
+#define EMI_IDLG            ((P_U32)(EMI_BASE+0x0230))
+#define EMI_IDLH            ((P_U32)(EMI_BASE+0x0238))
+#define EMI_IDLI            ((P_U32)(EMI_BASE+0x0240)) // IO input delay (DQS0 ~ DQS4)
+#define EMI_IDLJ            ((P_U32)(EMI_BASE+0x0248))
+#define EMI_IDLK            ((P_U32)(EMI_BASE+0x0250))
+
+#define EMI_ODLA           ((P_U32)(EMI_BASE+0x0258))
+#define EMI_ODLB           ((P_U32)(EMI_BASE+0x0260))
+#define EMI_ODLC           ((P_U32)(EMI_BASE+0x0268))
+#define EMI_ODLD           ((P_U32)(EMI_BASE+0x0270))
+#define EMI_ODLE           ((P_U32)(EMI_BASE+0x0278))
+#define EMI_ODLF           ((P_U32)(EMI_BASE+0x0280))
+#define EMI_ODLG           ((P_U32)(EMI_BASE+0x0288))
+
+#define EMI_DUTA           ((P_U32)(EMI_BASE+0x0290))
+#define EMI_DUTB           ((P_U32)(EMI_BASE+0x0298))
+#define EMI_DUTC           ((P_U32)(EMI_BASE+0x02A0))
+
+#define EMI_DRVA           ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_DRVB           ((P_U32)(EMI_BASE+0x02B0))
+
+#define EMI_IOCL           ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_IOCM           ((P_U32)(EMI_BASE+0x02C0)) //IvanTseng, for 4T mode
+#define EMI_IODC           ((P_U32)(EMI_BASE+0x02C8))
+
+#define EMI_ODTA           ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_ODTB           ((P_U32)(EMI_BASE+0x02D8))
+
+/* EMI auto-tracking control registers */
+#define EMI_DQSA           ((P_U32)(EMI_BASE+0x0300))
+#define EMI_DQSB           ((P_U32)(EMI_BASE+0x0308))
+#define EMI_DQSC           ((P_U32)(EMI_BASE+0x0310))
+#define EMI_DQSD           ((P_U32)(EMI_BASE+0x0318))
+
+
+#define EMI_DQSE           ((P_U32)(EMI_BASE+0x0320))
+#define EMI_DQSV           ((P_U32)(EMI_BASE+0x0328))
+
+#define EMI_CALA           ((P_U32)(EMI_BASE+0x0330))
+#define EMI_CALB           ((P_U32)(EMI_BASE+0x0338))
+#define EMI_CALC           ((P_U32)(EMI_BASE+0x0340))
+#define EMI_CALD           ((P_U32)(EMI_BASE+0x0348))
+
+
+#define EMI_CALE           ((P_U32)(EMI_BASE+0x0350)) //DDR data auto tracking control
+#define EMI_CALF           ((P_U32)(EMI_BASE+0x0358))
+#define EMI_CALG           ((P_U32)(EMI_BASE+0x0360)) //DDR data auto tracking control
+#define EMI_CALH           ((P_U32)(EMI_BASE+0x0368))
+
+#define EMI_CALI           ((P_U32)(EMI_BASE+0x0370))
+#define EMI_CALJ           ((P_U32)(EMI_BASE+0x0378))
+#define EMI_CALK           ((P_U32)(EMI_BASE+0x0380))
+#define EMI_CALL           ((P_U32)(EMI_BASE+0x0388))
+
+
+#define EMI_CALM           ((P_U32)(EMI_BASE+0x0390))
+#define EMI_CALN           ((P_U32)(EMI_BASE+0x0398))
+
+#define EMI_CALO           ((P_U32)(EMI_BASE+0x03A0))
+#define EMI_CALP           ((P_U32)(EMI_BASE+0x03A8))
+
+#define EMI_DUCA           ((P_U32)(EMI_BASE+0x03B0))
+#define EMI_DUCB           ((P_U32)(EMI_BASE+0x03B8))
+#define EMI_DUCC           ((P_U32)(EMI_BASE+0x03C0))
+#define EMI_DUCD           ((P_U32)(EMI_BASE+0x03C8))
+#define EMI_DUCE           ((P_U32)(EMI_BASE+0x03D0))
+
+/* EMI bus monitor control registers */
+#define EMI_BMEN           ((P_U32)(EMI_BASE+0x0400))
+#define EMI_BCNT           ((P_U32)(EMI_BASE+0x0408))
+#define EMI_TACT           ((P_U32)(EMI_BASE+0x0410))
+#define EMI_TSCT           ((P_U32)(EMI_BASE+0x0418))
+#define EMI_WACT           ((P_U32)(EMI_BASE+0x0420))
+#define EMI_WSCT           ((P_U32)(EMI_BASE+0x0428))
+#define EMI_BACT           ((P_U32)(EMI_BASE+0x0430))
+#define EMI_BSCT           ((P_U32)(EMI_BASE+0x0438))
+#define EMI_MSEL           ((P_U32)(EMI_BASE+0x0440))
+#define EMI_TSCT2           ((P_U32)(EMI_BASE+0x0448))
+#define EMI_TSCT3           ((P_U32)(EMI_BASE+0x0450))
+#define EMI_WSCT2           ((P_U32)(EMI_BASE+0x0458))
+#define EMI_WSCT3           ((P_U32)(EMI_BASE+0x0460))
+#define EMI_MSEL2           ((P_U32)(EMI_BASE+0x0468))
+#define EMI_MSEL3           ((P_U32)(EMI_BASE+0x0470))
+#define EMI_MSEL4           ((P_U32)(EMI_BASE+0x0478))
+#define EMI_MSEL5           ((P_U32)(EMI_BASE+0x0480))
+#define EMI_MSEL6           ((P_U32)(EMI_BASE+0x0488))
+#define EMI_MSEL7           ((P_U32)(EMI_BASE+0x0490))
+#define EMI_MSEL8           ((P_U32)(EMI_BASE+0x0498))
+#define EMI_MSEL9           ((P_U32)(EMI_BASE+0x04A0))
+#define EMI_MSEL10           ((P_U32)(EMI_BASE+0x04A8))
+#define EMI_BMID0            ((P_U32)(EMI_BASE+0x04B0))
+#define EMI_BMID1            ((P_U32)(EMI_BASE+0x04B8))
+#define EMI_BMID2            ((P_U32)(EMI_BASE+0x04C0))
+#define EMI_BMID3            ((P_U32)(EMI_BASE+0x04C8))
+#define EMI_BMID4            ((P_U32)(EMI_BASE+0x04D0))
+#define EMI_BMID5            ((P_U32)(EMI_BASE+0x04D8))
+
+#define EMI_TTYPE1            ((P_U32)(EMI_BASE+0x0500))
+#define EMI_TTYPE2            ((P_U32)(EMI_BASE+0x0508))
+#define EMI_TTYPE3            ((P_U32)(EMI_BASE+0x0510))
+#define EMI_TTYPE4            ((P_U32)(EMI_BASE+0x0518))
+#define EMI_TTYPE5            ((P_U32)(EMI_BASE+0x0520))
+#define EMI_TTYPE6            ((P_U32)(EMI_BASE+0x0528))
+#define EMI_TTYPE7            ((P_U32)(EMI_BASE+0x0530))
+#define EMI_TTYPE8            ((P_U32)(EMI_BASE+0x0538))
+#define EMI_TTYPE9            ((P_U32)(EMI_BASE+0x0540))
+#define EMI_TTYPE10            ((P_U32)(EMI_BASE+0x0548))
+#define EMI_TTYPE11            ((P_U32)(EMI_BASE+0x0550))
+#define EMI_TTYPE12            ((P_U32)(EMI_BASE+0x0558))
+#define EMI_TTYPE13            ((P_U32)(EMI_BASE+0x0560))
+#define EMI_TTYPE14            ((P_U32)(EMI_BASE+0x0568))
+#define EMI_TTYPE15            ((P_U32)(EMI_BASE+0x0570))
+#define EMI_TTYPE16            ((P_U32)(EMI_BASE+0x0578))
+#define EMI_TTYPE17            ((P_U32)(EMI_BASE+0x0580))
+#define EMI_TTYPE18            ((P_U32)(EMI_BASE+0x0588))
+#define EMI_TTYPE19            ((P_U32)(EMI_BASE+0x0590))
+#define EMI_TTYPE20            ((P_U32)(EMI_BASE+0x0598))
+#define EMI_TTYPE21            ((P_U32)(EMI_BASE+0x05A0))
+
+/* EMI MBIST control registers*/
+#define EMI_MBISTA            ((P_U32)(EMI_BASE+0x0600))
+#define EMI_MBISTB            ((P_U32)(EMI_BASE+0x0608))
+#define EMI_MBISTC            ((P_U32)(EMI_BASE+0x0610))
+#define EMI_MBISTD            ((P_U32)(EMI_BASE+0x0618))
+#define EMI_MBISTE            ((P_U32)(EMI_BASE+0x0620)) /* EMI MBIST status register */
+
+
+/* EMI Flow control register A */
+#define EMI_RFCA            ((P_U32)(EMI_BASE+0x0630))
+#define EMI_RFCB            ((P_U32)(EMI_BASE+0x0638))
+#define EMI_RFCC            ((P_U32)(EMI_BASE+0x0640))
+#define EMI_RFCD            ((P_U32)(EMI_BASE+0x0648))
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2635/include/tz_init.h
new file mode 100755
index 0000000..2e6cc13
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/tz_init.h
@@ -0,0 +1,84 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+#define DEVINFO_SIZE 4
+
+#define TEE_BOOT_ARG_ADDR (ATF_BOOT_ARG_ADDR + 0x100)
+
+#define TEE_PARAMETER_BASE (ATF_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000)//256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000)//16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0)//don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0)//don't support ATF log
+#endif
+
+typedef struct {
+	unsigned int atf_magic;
+	unsigned int tee_support;
+	unsigned int tee_entry;
+	unsigned int tee_boot_arg_addr;
+	unsigned int hwuid[4];     // HW Unique id for t-base used
+	unsigned int HRID[2];      // HW random id for t-base used
+	unsigned int atf_log_port;
+	unsigned int atf_log_baudrate;
+	unsigned int atf_log_buf_start;
+	unsigned int atf_log_buf_size;
+	unsigned int atf_irq_num;
+	unsigned int devinfo[DEVINFO_SIZE];
+	unsigned int atf_aee_debug_buf_start;
+	unsigned int atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+	unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(unsigned char *id, unsigned int size);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2635/include/tz_mem.h
new file mode 100755
index 0000000..df71b23
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/tz_mem.h
@@ -0,0 +1,102 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS   0x00100000
+#define SRAM_START_ADDR     0x00102140
+#define VECTOR_START        (SRAM_START_ADDR + 0xBAC0)
+
+typedef struct tz_memory_t {
+    short next, previous;
+} tz_memory_t;
+
+#define FREE            ((short)(0x0001))
+#define IS_FREE(x)      ((x)->next & FREE)
+#define CLEAR_FREE(x)   ((x)->next &= ~FREE)
+#define SET_FREE(x)     ((x)->next |= FREE)
+#define FROM_ADDR(x)    ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x)      ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC                   (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION                 (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE        (0x1000)//4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE       (0x200000)//2MB by default
+
+#define BL31                            (0x43001000UL)
+#define BL31_SIZE                       (0x30000) //192KB by default
+#define BL33                            (0x41E00000UL)
+
+#define ATF_BOOT_ARG_ADDR               (0x00101000)
+
+#define TEE_SECURE_ISRAM_ADDR           (0x0)
+#define TEE_SECURE_ISRAM_SIZE           (0x0)
+
+#define TEE_BOOT_ARG_ADDR (ATF_BOOT_ARG_ADDR + 0x100)
+
+#define TEE_PARAMETER_BASE (ATF_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000)//256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000)//16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0)//don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0)//don't support ATF log
+#endif
+
+typedef struct {
+    unsigned int magic;           // Magic number
+    unsigned int version;         // version
+    unsigned int svp_mem_start;   // MM sec mem pool start addr.
+    unsigned int svp_mem_end;     // MM sec mem pool end addr.
+    unsigned int tplay_table_start; //tplay handle-to-physical table start
+    unsigned int tplay_table_size;  //tplay handle-to-physical table size
+    unsigned int tplay_mem_start;   //tplay physcial memory start address for crypto operation
+    unsigned int tplay_mem_size;    //tplay phsycial memory size for crypto operation
+    unsigned int secmem_obfuscation;//MM sec mem obfuscation or not
+    unsigned int msg_auth_key[8]; /* size of message auth key is 32bytes(256 bits) */
+    unsigned int rpmb_size;       /* size of rpmb partition */
+    unsigned int emmc_rel_wr_sec_c;  //emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2635/include/tz_tbase.h
new file mode 100644
index 0000000..67f8078
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION            (0x00010000U)
+
+typedef struct {
+    u32 magic;        // magic value from information
+    u32 length;       // size of struct in bytes.
+    u64 version;      // Version of structure
+    u64 dRamBase;     // NonSecure DRAM start address
+    u64 dRamSize;     // NonSecure DRAM size
+    u64 secDRamBase;  // Secure DRAM start address
+    u64 secDRamSize;  // Secure DRAM size
+    u64 secIRamBase;  // Secure IRAM base
+    u64 secIRamSize;  // Secure IRam size
+    u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+    u32 RFU1;
+    u32 MSMPteCount;  // Number of MMU entries for MSM
+    u64 MSMBase;      // MMU entries for MSM
+    u64 gic_distributor_base;
+    u64 gic_cpuinterface_base;
+    u32 gic_version;
+    u32 total_number_spi;
+    u32 ssiq_number;
+    u32 RFU2;
+    u64 flags;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2635/include/uart.h b/src/bsp/trustzone/teeloader/mt2635/include/uart.h
new file mode 100644
index 0000000..1647749
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART1_BASE         (IO_PHYS + 0x01002000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/prebuild/librpmbkey.a b/src/bsp/trustzone/teeloader/mt2635/prebuild/librpmbkey.a
new file mode 100644
index 0000000..d462128
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/prebuild/librpmbkey.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2635/src/drivers/device_apc.c
new file mode 100644
index 0000000..8a3dfdd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/drivers/device_apc.c
@@ -0,0 +1,123 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES                                                          */
+/*=======================================================================*/
+#include "device_apc.h"
+#include "print.h"
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE        0x00000000      /* No event */
+#define DBG_EVT_ERR         0x00000001      /* ERR related event */
+#define DBG_EVT_DOM         0x00000002      /* DOM related event */
+
+#define DBG_EVT_ALL         0xffffffff
+
+#define DBG_EVT_MASK       (DBG_EVT_DOM )
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+    do {    \
+    if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+    print(fmt, ##args); \
+    } \
+    } while(0)
+
+#define MSG_FUNC_ENTRY(f)   MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{}while(0)
+#define MSG_FUNC_ENTRY(f)      do{}while(0)
+#endif
+
+void tz_dapc_set_master_transaction(unsigned int  master_index , E_TRANSACTION permisssion_control);
+
+void tz_dapc_sec_init()
+{
+    tz_dapc_set_master_transaction(MASTER_MSDC0 , SECURE_TRAN);
+
+#if defined(CFG_TRUSTONIC_TEE_SUPPORT)
+    tz_dapc_set_master_transaction(MASTER_SPI0 , SECURE_TRAN);
+#endif
+}
+void tz_dapc_sec_postinit()
+{
+    tz_dapc_set_master_transaction(MASTER_MSDC0 , NON_SECURE_TRAN);
+
+    /* DO NOT SET SPI0 back to Non-secure transaction. It should always keep in secure. */
+}
+void tz_dapc_set_master_transaction(unsigned int  master_index , E_TRANSACTION permisssion_control)
+{
+    reg_set_field(DEVAPC0_MAS_SEC , (0x1 << master_index), permisssion_control);
+}
+
+void device_APC_dom_setup(void)
+{
+    MSG(DOM, "\nDevice APC domain init setup:\n\n");
+    reg_write32(DEVAPC0_APC_CON, 0x0);
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+
+#if defined(MACH_TYPE_MT6735)
+    /*Set modem0 master to DOMAIN1*/
+    reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_DOMAIN, DOMAIN_1);
+    /*Set connsys master to DOMAIN2*/
+    reg_set_field(DEVAPC0_MAS_DOM_1 , CONN2AP,    DOMAIN_2);
+    /*Set modem1 master to DOMAIN5*/
+    reg_set_field(DEVAPC0_MAS_DOM_2 , MD3_DOMAIN, DOMAIN_5);
+    /*Set gpu master to DOMAIN6*/
+    reg_set_field(DEVAPC0_MAS_DOM_2 , GPU,        DOMAIN_6);
+
+#else
+
+#error "Wrong MACH type"
+
+#endif
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Device APC domain after setup:\n");
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/main.c b/src/bsp/trustzone/teeloader/mt2635/src/main.c
new file mode 100644
index 0000000..08b641a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/main.c
@@ -0,0 +1,63 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+
+int teeloader_main(void)
+{
+    u32 tee_addr = 0;
+    u32 hwuid[4] = {0x2824DB45, 0x42C4C820, 0xB36304A7, 0xCD8B4307};
+    device_APC_dom_setup();
+
+    trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+    tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+    /* set tee entry address */
+    tee_set_entry(tee_addr);
+    tee_set_hwuid((u8*)&hwuid[0], sizeof(hwuid));
+
+    trustzone_post_init();
+    trustzone_jump(BL31, BL33, tee_addr);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/print.c b/src/bsp/trustzone/teeloader/mt2635/src/print.c
new file mode 100644
index 0000000..027f211
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..f605315
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_emi_mpu.c
@@ -0,0 +1,333 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp, tmp2;
+    unsigned int ax_pm, ax_pm2;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end <= start)
+        {
+            return -1;
+        }
+    }
+
+    ax_pm  = (access_permission << 16) >> 16;
+    ax_pm2 = (access_permission >> 16);
+
+    switch (region) {
+    case 0:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp2 | ax_pm2, EMI_MPUI_2ND);
+        writel(tmp | ax_pm, EMI_MPUI);
+        break;
+
+    case 1:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUC); 
+        writel(tmp2 | ax_pm2, EMI_MPUJ_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ);
+        break; 
+
+    case 3:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp2 | ax_pm2, EMI_MPUK_2ND);
+        writel(tmp | ax_pm, EMI_MPUK);
+        break;
+
+    case 5:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK);
+        break;  
+
+    case 6:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp2 | ax_pm2, EMI_MPUL_2ND);
+        writel(tmp | ax_pm, EMI_MPUL);
+        break;
+
+    case 7:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL);
+        break;
+
+#if defined(MACH_TYPE_MT6735) || defined(MACH_TYPE_MT6753) || defined(MACH_TYPE_MT6737T)
+    case 8:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUA2);
+        writel(tmp2 | ax_pm2, EMI_MPUI2_2ND);
+        writel(tmp | ax_pm, EMI_MPUI2);
+        break;
+
+    case 9:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUB2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI2);
+        break;
+
+    case 10:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUC2);
+        writel(tmp2 | ax_pm2, EMI_MPUJ2_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ2);
+        break;
+
+    case 11:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUD2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ2);
+        break;
+
+    case 12:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUE2);
+        writel(tmp2 | ax_pm2, EMI_MPUK2_2ND);
+        writel(tmp | ax_pm, EMI_MPUK2);
+        break;
+
+    case 13:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUF2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK2);
+        break;
+
+    case 14:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUG2);
+        writel(tmp2 | ax_pm2, EMI_MPUL2_2ND);
+        writel(tmp | ax_pm, EMI_MPUL2);
+        break;
+
+    case 15:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUH2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL2);
+        break;
+#endif
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    // For MT6589
+    //==================================================================================================================
+    //            | Region |  D0(AP)  |  D1(MD0)  |  D2(Conn) |  D3(MD32) |  D4(MM)  |  D5(MD1)  |  D6(MFG)  |  D7(N/A)
+    //------------+---------------------------------------------------------------------------------------------------
+    // Secure OS  |    0   |RW(S)     |Forbidden  |Forbidden  |Forbidden  |RW(S)     |Forbidden  |Forbidden  |Forbidden
+    //------------+---------------------------------------------------------------------------------------------------
+    // MD0 ROM    |    1   |RO(S/NS)  |RO(S/NS)   |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 R/W+   |    2   |Forbidden |No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 ROM    |    3   |RO(S/NS)  |Forbidden  |RO(S/NS)   |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 R/W+   |    4   |Forbidden |Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 Share  |    5   |No protect|No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 Share  |    6   |No protect|Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // AP         |    7   |No protect|Forbidden  |Forbidden  |No protect
+    //===================================================================
+
+    switch(mpu_region)
+    {
+        case SECURE_OS_MPU_REGION_ID:
+        #if defined(MACH_TYPE_MT6735) || defined(MACH_TYPE_MT6753) || defined(MACH_TYPE_MT6737T)
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+		#else  //MT6735M
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, SEC_RW, FORBIDDEN, FORBIDDEN, SEC_RW);
+	#endif
+            break;
+
+        case ATF_MPU_REGION_ID:
+        #if defined(MACH_TYPE_MT6735) || defined(MACH_TYPE_MT6753) || defined(MACH_TYPE_MT6737T)
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+		#else  //MT6735M
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+	#endif
+            break;
+
+        default:
+            print("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+            return;
+    }
+
+    print("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,  /*START_ADDR*/
+                                        sec_mem_phy_end,    /*END_ADDR*/
+                                        mpu_region,         /*region*/
+                                        sec_mem_mpu_attr);
+
+    if(ret)
+    {
+        print("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_init.c
new file mode 100644
index 0000000..ee9a019
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_init.c
@@ -0,0 +1,232 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "sec_devinfo.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+/**************************************************************************
+ *  MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000)  //4K Alignment
+#define TEE_ENABLE_VERIFY (1)
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ *  INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+
+/**************************************************************************
+ *  INTERNAL FUNCTIONS
+ **************************************************************************/
+static u32 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+void tee_set_entry(u32 addr)
+{
+    tee_entry_addr = addr;
+
+    DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(u8 *id, u32 size)
+{
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_boot_param_addr();
+
+    memcpy(teearg->hwuid, id, size);
+    memcpy(g_hwuid, id, size);
+    g_hwuid_initialized = 1;
+
+    DBG_MSG("%s MEID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, id[0], id[1], id[2], id[3]);
+    DBG_MSG("%s MEID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, id[4], id[5], id[6], id[7]);
+    DBG_MSG("%s MEID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, id[8], id[9], id[10], id[11]);
+    DBG_MSG("%s MEID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, id[12], id[13], id[14], id[15]);
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+    int ret = 0;
+
+    if (!g_hwuid_initialized)
+        return -1;
+
+    memcpy(id, g_hwuid, size);
+
+    return ret;
+}
+
+static void tee_sec_config(void)
+{
+    u32 atf_entry_addr = BL31;
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+
+    tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+    DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+        secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+    atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+
+    DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+    tz_sec_mem_init(atf_entry_addr, atf_entry_addr + BL31_SIZE - 1, ATF_MPU_REGION_ID);
+    DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+        atf_entry_addr + BL31_SIZE - 1, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+    tz_dapc_sec_init();
+#if CFG_ATF_LOG_SUPPORT
+    atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#if CFG_TEE_SUPPORT
+    tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+#endif
+}
+
+void trustzone_post_init(void)
+{
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_boot_param_addr();
+
+    teearg->atf_magic = ATF_BOOTCFG_MAGIC;
+    teearg->tee_entry = tee_entry_addr;
+    teearg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+    teearg->HRID[0] = seclib_get_devinfo_with_index(E_AREA12);
+    teearg->HRID[1] = seclib_get_devinfo_with_index(E_AREA13);
+    teearg->atf_log_port = 0x11002000;
+    teearg->atf_log_baudrate = 0xE1000;
+    teearg->atf_irq_num = (32 + 249); /* reserve SPI ID 249 for ATF log, which is ID 281 */
+
+    //DBG_MSG("%s hwuid[0] : 0x%x\n", MOD, teearg->hwuid[0]);
+    //DBG_MSG("%s hwuid[1] : 0x%x\n", MOD, teearg->hwuid[1]);
+    //DBG_MSG("%s hwuid[2] : 0x%x\n", MOD, teearg->hwuid[2]);
+    //DBG_MSG("%s hwuid[3] : 0x%x\n", MOD, teearg->hwuid[3]);
+    DBG_MSG("%s HRID[0] : 0x%x\n", MOD, teearg->HRID[0]);
+    DBG_MSG("%s HRID[1] : 0x%x\n", MOD, teearg->HRID[1]);
+    DBG_MSG("%s atf_log_port : 0x%x\n", MOD, teearg->atf_log_port);
+    DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, teearg->atf_log_baudrate);
+    DBG_MSG("%s atf_irq_num : %d\n", MOD, teearg->atf_irq_num);
+
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+    tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        tee_secmem_size);
+    tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+    teearg->tee_support = 1;
+#else
+    teearg->tee_support = 0;
+#endif
+    tz_dapc_sec_postinit();
+
+#if CFG_ATF_LOG_SUPPORT
+    teearg->atf_log_buf_start = atf_log_buf_start;
+    teearg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+    teearg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+    teearg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+    teearg->atf_log_buf_start = 0;
+    teearg->atf_log_buf_size = 0;
+    teearg->atf_aee_debug_buf_start = 0;
+    teearg->atf_aee_debug_buf_size = 0;
+#endif
+    DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, teearg->atf_log_buf_start);
+    DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, teearg->atf_log_buf_size);
+    DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, teearg->atf_aee_debug_buf_start);
+    DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, teearg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u32 addr ,u32 arg1, u32 arg2, u32 arg3,
+                         u32 arg4, u32 arg5, u32 arg6, u32 arg7) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+    jump_atf atf_entry = (void *)addr;
+
+    tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+    DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+    DBG_MSG("%s Jump to ATF, then jump 0x%x\n", MOD, arg1);
+#endif
+
+    DBG_MSG("[teeloader] tl jump to atf!\n");
+    (*atf_entry)(0xC0000000, 0x10200038, 0x170,
+        trustzone_get_atf_boot_param_addr(),
+        0x4219C480, 0x170, arg1,
+        trustzone_get_atf_boot_param_addr());
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..4bb1598
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_sec_cfg.c
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+    tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_tbase.c
new file mode 100644
index 0000000..b9484f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/security/tz_tbase.c
@@ -0,0 +1,146 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#if 0 /* to do, RPMB usage*/
+#include "mmc_rpmb.h"
+#endif
+
+#define MOD "[TZ_TBASE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern u32 seclib_get_rpmb_size(void);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+    u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+    int ret = 0;
+    sec_mem_arg_t sec_mem_arg;
+    u8 hwuid[16];
+    unsigned char i, tmpbuf;
+
+    ret = tee_get_hwuid(hwuid, 16); 
+    if (ret)
+        DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+    /* Prepare secure memory configuration parameters */
+    sec_mem_arg.magic = SEC_MEM_MAGIC;
+    sec_mem_arg.version = SEC_MEM_VERSION;
+    sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+    sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+    sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+    sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+    seclib_get_msg_auth_key((unsigned char *)sec_mem_arg.msg_auth_key, 32);
+    sec_mem_arg.rpmb_size = seclib_get_rpmb_size();
+    sec_mem_arg.emmc_rel_wr_sec_c = 1; /* mmc_rpmb_get_rel_wr_sec_c(); */
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    sec_mem_arg.secmem_obfuscation = 1;
+#else
+    sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+    DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+    DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+    DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+    DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+    DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+    DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+    DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+    DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+    DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+    DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+
+    memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+    u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+    /* Prepare TEE boot parameters */
+    teearg->magic                 = TBASE_BOOTCFG_MAGIC;             /* Trustonic's TEE magic number */
+    teearg->length                = sizeof(tee_arg_t);               /* Trustonic's TEE argument block size */
+    //teearg->version               = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+    teearg->dRamBase              = dram_base;                       /* DRAM base address */
+    teearg->dRamSize              = dram_size;                       /* Full DRAM size */
+    teearg->secDRamBase           = tee_entry;                       /* Secure DRAM base address */
+    teearg->secDRamSize           = tbase_sec_dram_size;             /* Secure DRAM size */
+    teearg->secIRamBase           = TEE_SECURE_ISRAM_ADDR;           /* Secure SRAM base address */
+    teearg->secIRamSize           = TEE_SECURE_ISRAM_SIZE;           /* Secure SRAM size */
+    //teearg->conf_mair_el3         = read_mair_el3();
+    //teearg->MSMPteCount           = totalPages;
+    //teearg->MSMBase               = (u64)registerFileL2;
+    //teearg->gic_distributor_base  = TBASE_GIC_DIST_BASE;
+    //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+    //teearg->gic_version           = TBASE_GIC_VERSION;
+    teearg->total_number_spi      = 256;                             /* Support total 256 SPIs and 32 PPIs */
+    teearg->ssiq_number           = (32 + 248);                      /* reserve SPI ID 248 for <t-base, which is ID 280 */
+    //teearg->flags                 = TBASE_MONITOR_FLAGS;
+
+    DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+    DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+    DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+    DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+    DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+    DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+    DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+    DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+    DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+    DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/start.s b/src/bsp/trustzone/teeloader/mt2635/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/string.c b/src/bsp/trustzone/teeloader/mt2635/src/string.c
new file mode 100644
index 0000000..08b3f0e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+    const char *sc;
+
+    for (sc = s; *sc != '\0'; ++sc)
+    {
+    }
+    return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+    signed char __res;
+
+    while (1)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+    signed char __res = 0;
+
+    while (count)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+        count--;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+    char *xs = s;
+
+    while (count--)
+        *xs++ = c;
+    return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+    char *tmp = dest;
+    const char *s = src;
+
+    while (count--)
+        *tmp++ = *s++;
+    return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+    const unsigned char *su1, *su2;
+    int res = 0;
+
+    for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+        if ((res = *su1 - *su2) != 0)
+            break;
+    return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+	char *_dst = dst;
+	const char *_src = src;
+
+	if (dst == src)
+		return dst;
+
+	if (dst < src)
+		return memcpy(dst, src, count);
+
+	_dst += count;
+	_src += count;
+	while(count--)
+		*--_dst = *--_src;
+
+	return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2635/src/uart.c b/src/bsp/trustzone/teeloader/mt2635/src/uart.c
new file mode 100644
index 0000000..111b31c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2635/tllink.lds b/src/bsp/trustzone/teeloader/mt2635/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2635/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2635/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2635/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt2701/Makefile b/src/bsp/trustzone/teeloader/mt2701/Makefile
new file mode 100644
index 0000000..8c0efe0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/Makefile
@@ -0,0 +1,49 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: $(DIR_SRC)/%.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DTL_VERIFY_ENABLE=${TL_VERIFY_ENABLE} -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -c $^ -o $@ 
+
+$(DIR_OBJ)/%.o: $(DIR_SRC)/%.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_dec_key.py b/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_dec_key.py
new file mode 100755
index 0000000..213c87e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_dec_key.py
@@ -0,0 +1,149 @@
+# This script modfiy teeloader tz_keys.h MTEE_IMG_VFY_PUBK item when customer set they own keys
+
+import os
+import struct
+import sys
+import binascii
+
+IMG_KEY_PATH = "./teeloader/include"
+IMG_KEY_NAME = "mtee_key.pem"
+
+TARGET_H_FILE_PATH = "./teeloader/include"
+TARGET_H_FILE_NAME = "tz_keys.h"
+
+def parse_key(keyfile):
+	temp_key_file = "%s.temp" % keyfile
+	if os.path.exists(temp_key_file):
+		os.remove(temp_key_file)
+
+	cmdline = "openssl rsa -text -in %s -pubout > %s" % (keyfile, temp_key_file)
+	os.system(cmdline)
+	#check if keyfile generated success
+	if not os.path.exists(temp_key_file):
+		print "[error] command line excute failed: %s , please check you linux environment" % cmdline
+		exit(-1)
+
+	#parse keys
+	#read keyfile
+	lines = ""
+	for line in open(temp_key_file):
+		lines += line
+
+	#replace \r \next
+	lines = lines.replace("\n", "")
+	lines = lines.replace(" ", "")
+
+	#get public key
+	#from modulus to publicExponent
+	start_idx = lines.find("modulus:") + len("modulus:")
+	end_idx = lines.find("publicExponent")
+	public_key = lines[start_idx:end_idx]
+	if public_key[:2] == "00":
+		public_key = public_key[2:]
+	public_key = public_key.replace(":", "")
+	print "public_key :" + public_key
+
+	#get private key
+	#from privateExponent to prime1
+	start_idx = lines.find("privateExponent:") + len("privateExponent:")
+	end_idx = lines.find("prime1")
+	private_key = lines[start_idx:end_idx]
+	if private_key[:2] == "00":
+		private_key = private_key[2:]
+	private_key = private_key.replace(":", "")
+	print "\nprivate_key:" + private_key
+
+	os.remove(temp_key_file)
+
+	return (public_key, private_key)
+
+def string_to_bin(string,output_file):
+	if os.path.exists(output_file):
+		os.remove(output_file)
+
+	if (len(string) != 256*2):
+		print "[error] key length is not 256, please check"
+		exit(-1)
+
+	of = open(output_file, 'wb')
+
+	for i in range(0,len(string),2):
+		num=(int(string[i],16)<<4) + int(string[i+1],16)
+		byte=struct.pack('B',num)
+		of.write(byte)
+
+	of.close
+
+def bin_file_to_h_file(in_bin_file,out_h_file):
+	if not os.path.exists(in_bin_file):
+		print "[error] File %s not exist, please check" % in_bin_file
+		exit(-2)
+
+	if os.path.exists(out_h_file):
+		os.remove(out_h_file)
+
+	of = open(out_h_file, 'w')
+
+	j = 0
+	with open(in_bin_file, 'rb') as f:
+		content = f.read()
+		for i in range(len(content)):
+			if j % 8 == 0:
+				of.write("\n    ")
+			j += 1
+
+			of.write("0x%s," % binascii.hexlify(content[i])),
+		of.write("\n")
+
+	f.close()
+	of.close()
+
+def gen_final_h_file(in_h_file,out_h_file):
+	if not os.path.exists(in_h_file):
+		print "[error] File %s not exist, please check" % in_h_file
+		exit(-2)
+
+	if os.path.exists(out_h_file):
+		os.remove(out_h_file)
+
+	inf = open(in_h_file, 'r')
+	of = open(out_h_file, 'w')
+
+	of.write("u8 MTEE_IMG_VFY_PUBK[256] = {")
+	of.write(inf.read())
+	of.write("};\n")
+
+	inf.close()
+	of.close()
+
+if __name__ == "__main__":
+	key_file_path = IMG_KEY_PATH + "/" + IMG_KEY_NAME
+	if not os.path.exists(key_file_path):
+		print "[error] File %s not exist, please check" % key_file_path
+		exit(-1)
+
+	(img_auth_public_key, img_auth_private_key) = parse_key(key_file_path)
+
+	public_key_out_file = "%s.pub_out" % key_file_path
+	private_key_out_file = "%s.pri_out" % key_file_path
+
+	string_to_bin(img_auth_public_key,public_key_out_file)
+	string_to_bin(img_auth_private_key,private_key_out_file)
+
+	h_file = "%s.temp" % public_key_out_file 
+	bin_file_to_h_file(public_key_out_file,h_file);
+
+	final_h_file = "%s.h" % h_file
+	gen_final_h_file(h_file,final_h_file)
+
+	target_h_file = TARGET_H_FILE_PATH + "/" + TARGET_H_FILE_NAME
+	cmd="cp -f %s %s" %(final_h_file , target_h_file)
+	os.system(cmd)
+
+	temp_file = "./teeloader/include/mtee_key.pem.temp"
+	if os.path.exists(temp_file):
+		os.remove(temp_file)
+	os.remove(h_file)
+	os.remove(final_h_file)
+	os.remove(public_key_out_file)
+	os.remove(private_key_out_file)
diff --git a/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_enc_key.py b/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_enc_key.py
new file mode 100755
index 0000000..b39aa05
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/cus_tzimg_enc_key.py
@@ -0,0 +1,80 @@
+# This script modfiy TRUSTZONE_IMG_PROTECT_CFG.ini AUTH_PARAM_N and AUTH_PARAM_D items when customer set they own keys
+
+import os
+import sys
+
+TARGET_PLATFORM = sys.argv[1]
+MTEE_IMG_KEY_FILE = "./teeloader/include/mtee_key.pem"
+TRUSTZONE_IMG_PROTECT_CFG_FILE = "./mtee/build/cfg/" + TARGET_PLATFORM + "/TRUSTZONE_IMG_PROTECT_CFG.ini"
+TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP = "./mtee/build/cfg/" + TARGET_PLATFORM + "/TRUSTZONE_IMG_PROTECT_CFG_TEMP.ini"
+
+def parse_key(keyfile):
+	temp_key_file = "%s.temp" % keyfile
+	cmdline = "openssl rsa -text -in %s -pubout > %s" % (keyfile, temp_key_file)
+	os.system(cmdline)
+	#check if keyfile generated success
+	if not os.path.exists(temp_key_file):
+		print "[error] command line excute failed: %s , please check you linux environment" % cmdline
+		exit(-1)
+
+	#parse keys
+	#read keyfile
+	lines = ""
+	for line in open(temp_key_file):
+		lines += line
+
+	#replace \r \next
+	lines = lines.replace("\n", "")
+	lines = lines.replace(" ", "")
+
+	#get public key
+	#from modulus to publicExponent
+	start_idx = lines.find("modulus:") + len("modulus:")
+	end_idx = lines.find("publicExponent")
+	public_key = lines[start_idx:end_idx]
+	if public_key[:2] == "00":
+		public_key = public_key[2:]
+	public_key = public_key.replace(":", "")
+	#print "public_key :" + public_key
+
+	#get private key
+	#from privateExponent to prime1
+	start_idx = lines.find("privateExponent:") + len("privateExponent:")
+	end_idx = lines.find("prime1")
+	private_key = lines[start_idx:end_idx]
+	if private_key[:2] == "00":
+		private_key = private_key[2:]
+	private_key = private_key.replace(":", "")
+	#print "private_key:" + private_key
+
+	os.remove(temp_key_file)
+
+	return (public_key, private_key)
+
+#check paramters
+if len(sys.argv) < 2:
+	print "miss parameter"
+	print "usage: python cus_mtee_enc_key.py platform(ex: mt2701)\n"
+
+#generate temp file used to modify original config
+if os.path.exists(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP):
+	os.remove(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP)
+cmd = "cp -f " + TRUSTZONE_IMG_PROTECT_CFG_FILE + " " + TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP
+os.system(cmd)
+
+#modify AUTH_PARAM_N and AUTH_PARAM_D
+(img_auth_public_key, img_auth_private_key) = parse_key(MTEE_IMG_KEY_FILE)
+img_auth_key_list = open(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP).readlines()
+tmp = open(TRUSTZONE_IMG_PROTECT_CFG_FILE, "w+")
+for i in range(0, len(img_auth_key_list)):
+	if img_auth_key_list[i].startswith("AUTH_PARAM_N"):
+		img_auth_key_list[i] = "AUTH_PARAM_N = 0x" + img_auth_public_key + "\n"
+		tmp.write(img_auth_key_list[i])
+	elif img_auth_key_list[i].startswith("AUTH_PARAM_D"):
+		img_auth_key_list[i] = "AUTH_PARAM_D = 0x" + img_auth_private_key + "\n"
+		tmp.write(img_auth_key_list[i])
+	else:
+		tmp.write(img_auth_key_list[i])
+
+#job done, remove temp file
+os.remove(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP)
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/blkdev.h b/src/bsp/trustzone/teeloader/mt2701/include/blkdev.h
new file mode 100644
index 0000000..64077dd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/blkdev.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef BLKDEV_H
+#define BLKDEV_H
+
+#include "typedefs.h"
+
+typedef struct blkdev blkdev_t;
+
+struct blkdev {
+	u32 type;       /* block device type */
+	u32 blksz;      /* block size. (read/write unit) */
+	u32 erasesz;    /* erase size */
+	u32 blks;       /* number of blocks in the device */
+	u32 offset;     /* user area offset in blksz unit */
+	u8 *blkbuf;     /* block size buffer */
+	void *priv;     /* device private data */    
+	blkdev_t *next; /* next block device */
+	int (*bread)(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+	int (*bwrite)(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+};
+
+extern int blkdev_register(blkdev_t *bdev);
+extern int blkdev_read(blkdev_t *bdev, u64 src, u32 size, u8 *dst, u32 part_id);
+extern int blkdev_write(blkdev_t *bdev, u64 dst, u32 size, u8 *src, u32 part_id);
+extern int blkdev_bread(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+extern int blkdev_bwrite(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+extern blkdev_t *blkdev_get(u32 type);
+
+#endif /* BLKDEV_H */
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/buffer.h b/src/bsp/trustzone/teeloader/mt2701/include/buffer.h
new file mode 100644
index 0000000..05c8568
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/buffer.h
@@ -0,0 +1,75 @@
+/*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2016. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver's
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef BUFFER_ADDR_H
+#define BUFFER_ADDR_H
+
+#include "dram_buffer.h"
+
+#define SEC_SECRO_BUFFER_START      sec_secro_buf
+#define SEC_SECRO_BUFFER_LENGTH     DRAM_SEC_SECRO_BUFFER_LENGTH
+
+#define SEC_WORKING_BUFFER_START    sec_working_buf
+#define SEC_WORKING_BUFFER_LENGTH   DRAM_SEC_WORKING_BUFFER_LENGTH
+
+#define SEC_UTIL_BUFFER_START       sec_util_buf
+#define SEC_UTIL_BUFFER_LENGTH      DRAM_SEC_UTIL_BUFFER_LENGTH
+
+/*SecLib.a use DRAM*/
+#define SEC_LIB_HEAP_START          sec_lib_heap_buf
+#define SEC_LIB_HEAP_LENGTH         DRAM_SEC_LIB_HEAP_LENGTH
+
+/*For v3 verify check buffer */
+#define SEC_IMG_BUFFER_START        sec_img_buf
+#define SEC_IMG_BUFFER_LENGTH       DRAM_SEC_IMG_BUFFER_LENGTH
+
+#define SEC_CHUNK_BUFFER_START      sec_chunk_buf
+#define SEC_CHUNK_BUFFER_LENGTH     DRAM_SEC_CHUNK_BUFFER_LENGTH
+
+#define DA_RAM_ADDR                 (CFG_DA_RAM_ADDR)
+#define DA_RAM_LENGTH               (0x30000)
+
+#define DA_RAM_RELOCATE_ADDR        (CFG_DA_RAM_ADDR + DA_RAM_LENGTH)
+#define DA_RAM_RELOCATE_LENGTH      (DA_RAM_LENGTH)
+
+#define  sec_secro_buf    g_dram_buf->sec_secro_buf 
+#define  sec_working_buf  g_sec_buf.sram_sec_working_buf
+#define  sec_util_buf     g_dram_buf->sec_util_buf
+#define  sec_lib_heap_buf g_dram_buf->sec_lib_heap_buf
+#define  sec_img_buf      g_sec_buf.sram_sec_img_buf
+#define  sec_chunk_buf    g_dram_buf->sec_chunk_buf
+#endif
+
+
+
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/dram_buffer.h b/src/bsp/trustzone/teeloader/mt2701/include/dram_buffer.h
new file mode 100644
index 0000000..df86f38
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/dram_buffer.h
@@ -0,0 +1,142 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+ 
+#ifndef DRAM_BUFFER_H 
+#define DRAM_BUFFER_H
+
+#include "partition.h"
+
+#define BMT_BUFFER_SIZE     0x10000
+#define PART_HDR_BUF_SIZE 512
+#define GPT_BUFFER_SIZE    (0x4000)
+#define STORAGE_BUFFER_SIZE 0x10000
+#define IMG_HDR_BUF_SIZE 512
+#define LOG_BUFFER_MAX_SIZE             (0x10000)
+#define DRAM_SEC_SECRO_BUFFER_LENGTH     (0x3000)
+#define DRAM_SEC_WORKING_BUFFER_LENGTH   0x2000  
+#define DRAM_SEC_UTIL_BUFFER_LENGTH      0x1000   
+#define DRAM_SEC_LIB_HEAP_LENGTH         0x4000   
+#define DRAM_SEC_IMG_BUFFER_LENGTH       0x3000    
+#define DRAM_SEC_CHUNK_BUFFER_LENGTH     0x100000 
+#define CFG_DRAM_ADDR                   (0x00240000)
+#define MAX_MAIN_SIZE                (0x1000)
+#define MAX_SPAR_SIZE                (0x80)
+#define BMT_DAT_BUFFER_SIZE         (MAX_MAIN_SIZE + MAX_SPAR_SIZE) 
+#define PMT_DAT_BUFFER_SIZE         (MAX_MAIN_SIZE + MAX_SPAR_SIZE)
+#define PMT_READ_BUFFER_SIZE        (MAX_MAIN_SIZE)
+#define NAND_NFI_BUFFER_SIZE          0x1000
+#define PART_MAX_NUM   20
+
+#if CFG_BYPASS_EMI
+typedef struct {
+	u8 bmt_buf[0x1000];
+	u8 bmt_dat_buf[BMT_DAT_BUFFER_SIZE];
+	u8 nand_nfi_buf[0x1000];
+	part_hdr_t part_hdr_buf[1];
+	u32 crc32_table[256];
+	u8 pgpt_header_buf[512];
+	u8 sgpt_header_buf[512];
+	u8 pgpt_entries_buf[GPT_BUFFER_SIZE];
+	u8 sgpt_entries_buf[GPT_BUFFER_SIZE];
+	unsigned char storage_buffer[16];
+	u8 img_hdr_buf[IMG_HDR_BUF_SIZE];
+	unsigned int part_num;
+	part_hdr_t   part_info[2];
+	part_t  partition_info[2];
+#ifdef MTK_EMMC_SUPPORT
+	struct part_meta_info meta_info[1];
+#endif
+	u32 bootarg;
+	u8 log_dram_buf[0x1000];
+	u8  sec_secro_buf[DRAM_SEC_SECRO_BUFFER_LENGTH];
+	u8  sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];/*This dram Buffer not used for security concern*/
+	u8  sec_util_buf[DRAM_SEC_UTIL_BUFFER_LENGTH];
+	u8  sec_lib_heap_buf[DRAM_SEC_LIB_HEAP_LENGTH];
+	u8  sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];        /*This dram Buffer not used for security concern*/
+	u8  sec_chunk_buf[0x4000];
+	u32 *boottag; 
+} dram_buf_t;
+#else
+typedef struct {
+	/*bmt.c*/
+	u8 bmt_buf[BMT_BUFFER_SIZE];
+	u8 bmt_dat_buf[BMT_DAT_BUFFER_SIZE];
+	/*nand.c*/
+	u8 nand_nfi_buf[NAND_NFI_BUFFER_SIZE];
+	
+	/*download.c*/
+	part_hdr_t part_hdr_buf[PART_HDR_BUF_SIZE];  
+	/*efi.c*/
+	u32 crc32_table[256];
+	u8 pgpt_header_buf[512];
+	u8 sgpt_header_buf[512];
+	u8 pgpt_entries_buf[GPT_BUFFER_SIZE];
+	u8 sgpt_entries_buf[GPT_BUFFER_SIZE];
+	/*mmc_common_inter.c*/
+	unsigned char storage_buffer[STORAGE_BUFFER_SIZE];
+	/*partition.c*/
+	u8 img_hdr_buf[IMG_HDR_BUF_SIZE];
+	unsigned int part_num;
+	part_hdr_t   part_info[PART_MAX_NUM];
+	part_t  partition_info[128];
+	
+#ifdef MTK_EMMC_SUPPORT
+	struct part_meta_info meta_info[128];
+#endif
+	u32 bootarg;
+	u8 log_dram_buf[LOG_BUFFER_MAX_SIZE];
+	u8  sec_secro_buf[DRAM_SEC_SECRO_BUFFER_LENGTH];
+	u8  sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];/*This dram Buffer not used for security concern*/
+	u8  sec_util_buf[DRAM_SEC_UTIL_BUFFER_LENGTH];
+	u8  sec_lib_heap_buf[DRAM_SEC_LIB_HEAP_LENGTH];
+	u8  sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];        /*This dram Buffer not used for security concern*/
+	u8  sec_chunk_buf[DRAM_SEC_CHUNK_BUFFER_LENGTH]; 
+	u32 *boottag;
+} dram_buf_t;
+#endif
+
+typedef struct {
+	u8 sram_sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];
+	u8 sram_sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];
+} sec_buf_t;
+
+void init_dram_buffer();
+u64 platform_memory_size(void);
+dram_buf_t *g_dram_buf;
+sec_buf_t  g_sec_buf;
+
+#endif /*DRAM_BUFFER_H*/
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/partition.h b/src/bsp/trustzone/teeloader/mt2701/include/partition.h
new file mode 100644
index 0000000..7c0fb8f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/partition.h
@@ -0,0 +1,94 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PARTITION_H
+#define PARTITION_H
+
+#include "typedefs.h"
+#include "blkdev.h"
+
+#define PART_HEADER_DEFAULT_ADDR    (0xFFFFFFFF)
+#define LOAD_ADDR_MODE_BACKWARD     (0x00000000)
+#define PART_MAGIC          0x58881688
+
+typedef union {
+	struct {
+		unsigned int magic;     /* partition magic */
+		unsigned int dsize;     /* partition data size */
+		char name[32];          /* partition name */
+		unsigned int maddr;     /* partition memory address */
+		unsigned int mode;      /* memory addressing mode */
+	} info;
+	unsigned char data[512];
+} part_hdr_t;
+
+#if 1
+#define PART_META_INFO_NAMELEN  64
+#define PART_META_INFO_UUIDLEN  16
+
+struct part_meta_info {
+	u8 name[PART_META_INFO_NAMELEN];
+	u8 uuid[PART_META_INFO_UUIDLEN];
+};
+
+typedef struct {
+	unsigned long start_sect;
+	unsigned long nr_sects;
+	unsigned int part_id;
+	struct part_meta_info *info;
+} part_t;
+#else
+typedef struct {
+	unsigned char *name;        /* partition name */
+	unsigned long startblk;     /* partition start blk */
+	unsigned long size;         /* partition size */
+	unsigned long blks;         /* partition blks */
+	unsigned long flags;        /* partition flags */
+	unsigned int part_id;
+} part_t;
+#endif
+
+extern int part_init(void);
+extern part_t *part_get(char *name);
+extern int part_load(blkdev_t *bdev, part_t *part, u32 *addr, u32 offset, u32 *size);
+extern void part_dump(void);
+
+extern part_t *get_part(char *name);
+extern void put_part(part_t *part);
+extern int part_load_raw_part(blkdev_t *bdev, part_t *part, u32 *addr, u32 offset, u32 *size);
+
+#endif /* PARTITION_H */
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/print.h b/src/bsp/trustzone/teeloader/mt2701/include/print.h
new file mode 100644
index 0000000..50e2385
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/print.h
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void dbg_print(char *sz, ...);
+extern void print(char *sz, ...);
+extern void log_buf_ctrl(int drambuf);
+extern void log_ctrl(int enable);
+extern int  log_status(void);
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/stdlib.h b/src/bsp/trustzone/teeloader/mt2701/include/stdlib.h
new file mode 100644
index 0000000..91eb793
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/stdlib.h
@@ -0,0 +1,44 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __STDLIB_H__
+#define __STDLIB_H__
+
+int atoi(const char *s);
+long long atoll(const char *num);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/string.h b/src/bsp/trustzone/teeloader/mt2701/include/string.h
new file mode 100644
index 0000000..5436663
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/string.h
@@ -0,0 +1,48 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#endif /* STRING_H */
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2701/include/typedefs.h
new file mode 100644
index 0000000..dcf93d1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/typedefs.h
@@ -0,0 +1,303 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#define __NOBITS_SECTION__(x) __attribute__((section(#x ", \"aw\", %nobits@")))
+#define __SRAM__  __NOBITS_SECTION__(.secbuf)
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+//------------------------------------------------------------------
+
+typedef volatile unsigned char *P_kal_uint8;
+typedef volatile unsigned short *P_kal_uint16;
+typedef volatile unsigned int *P_kal_uint32;
+
+typedef long LONG;
+typedef unsigned char UBYTE;
+typedef short SHORT;
+
+typedef signed char kal_int8;
+typedef signed short kal_int16;
+typedef signed int kal_int32;
+typedef long long kal_int64;
+typedef unsigned char kal_uint8;
+typedef unsigned short kal_uint16;
+typedef unsigned int kal_uint32;
+typedef unsigned long long kal_uint64;
+typedef char kal_char;
+
+typedef unsigned int *UINT32P;
+typedef volatile unsigned short *UINT16P;
+typedef volatile unsigned char *UINT8P;
+typedef unsigned char *U8P;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char U8;
+typedef signed char S8;
+typedef unsigned short U16;
+typedef signed short S16;
+typedef unsigned int U32;
+typedef signed int S32;
+typedef unsigned long long U64;
+typedef signed long long S64;
+typedef unsigned char bool;
+
+//------------------------------------------------------------------
+
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+#define BITS_PER_LONG               32
+/* Dma addresses are 32-bits wide.  */
+typedef u32 dma_addr_t;
+
+//------------------------------------------------------------------
+
+#define FALSE                       0
+#define TRUE                        1
+
+#define IMPORT  EXTERN
+#ifndef __cplusplus
+#define EXTERN  extern
+#else
+#define EXTERN  extern "C"
+#endif
+#define LOCAL     static
+#define GLOBAL
+#define EXPORT    GLOBAL
+
+#define EQ        ==
+#define NEQ       !=
+#define AND       &&
+#define OR        ||
+#define XOR(A,B)  ((!(A) AND (B)) OR ((A) AND !(B)))
+
+#ifndef FALSE
+#define FALSE   0
+#endif
+
+#ifndef TRUE
+#define TRUE    1
+#endif
+
+#ifndef NULL
+#define NULL    0
+#endif
+
+enum boolean {
+	false,
+	true
+};
+
+enum {
+	RX,
+	TX,
+	NONE
+};
+
+#ifndef BOOL
+typedef unsigned char BOOL;
+#endif
+
+typedef enum {
+	KAL_FALSE = 0,
+	KAL_TRUE = 1,
+} kal_bool;
+
+/*==== EXPORTED MACRO ===================================================*/
+
+#define MAXIMUM(A,B)                (((A)>(B))?(A):(B))
+#define MINIMUM(A,B)                (((A)<(B))?(A):(B))
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+// !!! DEPRECATED, WILL BE REMOVED LATER !!!
+#define DRV_Reg(addr)               DRV_Reg16(addr)
+#define DRV_WriteReg(addr, data)    DRV_WriteReg16(addr, data)
+#define DRV_SetReg(addr, data)      DRV_SetReg16(addr, data)
+#define DRV_ClrReg(addr, data)      DRV_ClrReg16(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define dsb()	\
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
+
+#if 0
+extern void platform_assert(char *file, int line, char *expr);
+
+#define ASSERT(expr) \
+    do{ if(!(expr)){platform_assert(__FILE__, __LINE__, #expr);} }while(0)
+#endif
+
+// compile time assert 
+//#define COMPILE_ASSERT(condition) ((void)sizeof(char[1 - 2*!!!(condition)]))
+
+#define printf          print
+#define tl_printf       tl_print
+//#define BUG_ON(expr)    ASSERT(!(expr))
+
+#if defined(MACH_TYPE_MT6735M)
+#define printf(fmt, args...)          do{}while(0)
+#endif
+
+//------------------------------------------------------------------
+
+#if 0
+typedef char *va_list;
+#define _INTSIZEOF(n) ( (sizeof(n) + sizeof(int) - 1) & ~(sizeof(int) - 1) )
+#define va_start(ap,v) ( ap = (va_list)&v + _INTSIZEOF(v) )
+#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+#else
+#include <stdarg.h>
+#endif
+
+#define READ_REG(REG)           __raw_readl(REG)
+#define WRITE_REG(VAL, REG)     __raw_writel(VAL, REG)
+
+#ifndef min
+#define min(x, y)   (x < y ? x : y)
+#endif
+#ifndef max
+#define max(x, y)   (x > y ? x : y)
+#endif
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2701/include/tz_init.h
new file mode 100644
index 0000000..948103e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/tz_init.h
@@ -0,0 +1,89 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "tz_keys.h"
+#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+#define DEVINFO_SIZE 4
+
+#define MCUSYS_CFGREG_BASE  (0x10000000 + 0x00200000)
+#define RVBADDRESS_CPU0     (MCUSYS_CFGREG_BASE + 0x38)
+
+/* 
+    RSA2048 public key for verifying mtee image
+    It should be the same as AUTH_PARAM_N in alps\mediatek\custom\mt6752_evb\trustzone\TRUSTZONE_IMG_PROTECT_CFG.ini
+*/
+#define MTEE_IMG_VFY_PUBK_SZ 256
+
+typedef struct {
+	u32 atf_magic;
+	u32 tee_support;
+	u32 tee_entry;
+	u32 tee_boot_arg_addr;
+	u32 hwuid[4];     // HW Unique id for t-base used
+	u32 HRID[2];      // HW random id for t-base used
+	u32 atf_log_port;
+	u32 atf_log_baudrate;
+	u32 atf_log_buf_start;
+	u32 atf_log_buf_size;
+	u32 atf_irq_num;
+	u32 devinfo[DEVINFO_SIZE];
+	u32 atf_aee_debug_buf_start;
+	u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+	u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tee_get_secmem_start(u32 *addr);
+void tee_get_secmem_size(u32 *size);
+void tee_set_entry(u32 addr);
+void tee_set_hwuid(u8 *id, u32 size);
+int  tee_verify_image(u32 *addr, u32 size);
+u32 tee_get_load_addr(u32 maddr);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2);
+
+#endif /* TRUSTZONE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/tz_keys.h b/src/bsp/trustzone/teeloader/mt2701/include/tz_keys.h
new file mode 100644
index 0000000..c412839
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/tz_keys.h
@@ -0,0 +1,55 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+u8 MTEE_IMG_VFY_PUBK[256] = {
+	0xDA, 0xCD, 0x8B, 0x5F, 0xDA, 0x8A, 0x76, 0x6F, 0xB7, 0xBC, 0xAA, 0x43, 0xF0, 0xB1, 0x69, 0x15,
+	0xCE, 0x7B, 0x47, 0x71, 0x4F, 0x13, 0x95, 0xFD, 0xEB, 0xCF, 0x12, 0xA2, 0xD4, 0x11, 0x55, 0xB0,
+	0xFB, 0x58, 0x7A, 0x51, 0xFE, 0xCC, 0xCB, 0x4D, 0xDA, 0x1C, 0x8E, 0x5E, 0xB9, 0xEB, 0x69, 0xB8,
+	0x6D, 0xAF, 0x2C, 0x62, 0x0F, 0x6C, 0x27, 0x35, 0x21, 0x5A, 0x5F, 0x22, 0xC0, 0xB6, 0xCE, 0x37,
+	0x7A, 0xA0, 0xD0, 0x7E, 0xB3, 0x8E, 0xD3, 0x40, 0xB5, 0x62, 0x9F, 0xC2, 0x89, 0x04, 0x94, 0xB0,
+	0x78, 0xA6, 0x3D, 0x6D, 0x07, 0xFD, 0xEA, 0xCD, 0xBE, 0x3E, 0x7F, 0x27, 0xFD, 0xE4, 0xB1, 0x43,
+	0xF4, 0x9D, 0xB4, 0x97, 0x14, 0x37, 0xE6, 0xD0, 0x0D, 0x9E, 0x18, 0xB5, 0x6F, 0x02, 0xDA, 0xBE,
+	0xB0, 0x00, 0x0B, 0x6E, 0x79, 0x51, 0x6D, 0x0C, 0x80, 0x74, 0xB5, 0xA4, 0x25, 0x69, 0xFD, 0x0D,
+	0x91, 0x96, 0x65, 0x5D, 0x2A, 0x40, 0x30, 0xD4, 0x2D, 0xFE, 0x05, 0xE9, 0xF6, 0x48, 0x83, 0xE6,
+	0xD5, 0xF7, 0x9A, 0x5B, 0xFA, 0x3E, 0x70, 0x14, 0xC9, 0xA6, 0x28, 0x53, 0xDC, 0x1F, 0x21, 0xD5,
+	0xD6, 0x26, 0xF4, 0xD0, 0x84, 0x6D, 0xB1, 0x64, 0x52, 0x18, 0x7D, 0xD7, 0x76, 0xE8, 0x88, 0x6B,
+	0x48, 0xC2, 0x10, 0xC9, 0xE2, 0x08, 0x05, 0x9E, 0x7C, 0xAF, 0xC9, 0x97, 0xFD, 0x2C, 0xA2, 0x10,
+	0x77, 0x5C, 0x1A, 0x5D, 0x9A, 0xA2, 0x61, 0x25, 0x2F, 0xB9, 0x75, 0x26, 0x8D, 0x97, 0x0C, 0x62,
+	0x73, 0x38, 0x71, 0xD5, 0x78, 0x14, 0x09, 0x8A, 0x45, 0x3D, 0xF9, 0x2B, 0xC6, 0xCA, 0x19, 0x02,
+	0x5C, 0xD9, 0xD4, 0x30, 0xF0, 0x2E, 0xE4, 0x6F, 0x80, 0xDE, 0x6C, 0x63, 0xEA, 0x80, 0x2B, 0xEF,
+	0x90, 0x67, 0x3A, 0xAC, 0x4C, 0x66, 0x67, 0xF2, 0x88, 0x3F, 0xB4, 0x50, 0x1F, 0xA7, 0x74, 0x55
+};
diff --git a/src/bsp/trustzone/teeloader/mt2701/include/uart.h b/src/bsp/trustzone/teeloader/mt2701/include/uart.h
new file mode 100644
index 0000000..717090f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+ 
+#ifndef UART_H
+#define UART_H
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART1_BASE         (IO_PHYS + 0x01002000)
+
+int uart_putc(char c);
+
+#endif
+
diff --git a/src/bsp/trustzone/teeloader/mt2701/prebuild/DaVerifyLib.a b/src/bsp/trustzone/teeloader/mt2701/prebuild/DaVerifyLib.a
new file mode 100644
index 0000000..d78aa04
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/prebuild/DaVerifyLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2701/prebuild/HwCryptoLib.a b/src/bsp/trustzone/teeloader/mt2701/prebuild/HwCryptoLib.a
new file mode 100644
index 0000000..be64f3e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/prebuild/HwCryptoLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2701/prebuild/SecLib.a b/src/bsp/trustzone/teeloader/mt2701/prebuild/SecLib.a
new file mode 100644
index 0000000..65e5e52
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/prebuild/SecLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2701/prebuild/SecPlat.a b/src/bsp/trustzone/teeloader/mt2701/prebuild/SecPlat.a
new file mode 100644
index 0000000..c75240e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/prebuild/SecPlat.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/crt.s b/src/bsp/trustzone/teeloader/mt2701/src/crt.s
new file mode 100644
index 0000000..9e54b46
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/crt.s
@@ -0,0 +1,69 @@
+/* Runtime ABI for the ARM Cortex-M0
+ * crt.S: C runtime environment
+ *
+ * Copyright (c) 2012 Jörg Mische <bobbl@gmx.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+	.syntax unified
+	.text
+	.thumb
+	@.cpu cortex-m0
+
+
+
+
+
+@ void exit(int status)
+@
+@ Exit from program: breakpoint 0
+@
+	.thumb_func
+        .global exit
+exit:
+	bkpt	#0
+
+
+
+@ void abort(void)
+@
+@ Abnormal program termination: breakpoint 1
+@
+	.thumb_func
+        .global abort
+abort:
+	bkpt	#1
+
+
+
+@ int __aeabi_idiv0(int r)
+@
+@ Handler for 32 bit division by zero
+@
+	.thumb_func
+        .global __aeabi_idiv0
+__aeabi_idiv0:
+
+
+
+@ long long __aeabi_ldiv0(long long r)
+@
+@ Handler for 64 bit division by zero
+@
+	.thumb_func
+        .global __aeabi_ldiv0
+__aeabi_ldiv0:
+	bx	lr
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/div0.c b/src/bsp/trustzone/teeloader/mt2701/src/div0.c
new file mode 100644
index 0000000..278cf23
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/div0.c
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#include <typedefs.h>
+
+void __div0(void)
+{
+	//ASSERT(0);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/dram_buffer.c b/src/bsp/trustzone/teeloader/mt2701/src/dram_buffer.c
new file mode 100644
index 0000000..4547fd6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/dram_buffer.c
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "dram_buffer.h"
+#include "typedefs.h"
+
+#define MOD "[Dram_Buffer]"
+
+dram_buf_t *g_dram_buf = 0;
+
+u64 platform_memory_size(void)
+{
+	/* now use hard code */
+	u64 mem_size = 99;
+	return mem_size;
+}
+
+void init_dram_buffer()
+{
+	u32 structure_size = sizeof(dram_buf_t);
+
+	/*allocate dram_buf */
+	g_dram_buf = BASE_ADDR - 0x200000;
+	memset((void *)&(g_dram_buf->bootarg), 0, sizeof(u32));
+}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/dummy.s b/src/bsp/trustzone/teeloader/mt2701/src/dummy.s
new file mode 100644
index 0000000..cd4d98c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/dummy.s
@@ -0,0 +1,15 @@
+.globl get_timer
+.type  get_timer, function
+
+.globl part_load
+.type  part_load, function
+
+.globl part_get
+.type  part_get, function
+
+get_timer:
+part_load:
+part_get:
+	mov	pc, lr
+
+
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/idiv.s b/src/bsp/trustzone/teeloader/mt2701/src/idiv.s
new file mode 100644
index 0000000..701ac7c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/idiv.s
@@ -0,0 +1,66 @@
+/* Runtime ABI for the ARM Cortex-M0
+ * idiv.S: signed 32 bit division (only quotient)
+ *
+ * Copyright (c) 2012-2017 Jörg Mische <bobbl@gmx.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+	.syntax unified
+	.text
+	.thumb
+	@.cpu cortex-m0
+
+
+
+@ int __divsi3(int num, int denom)
+@
+@ libgcc wrapper: just an alias for __aeabi_idivmod(), the remainder is ignored
+@
+	.thumb_func
+        .global __divsi3
+__divsi3:
+
+
+
+@ int __aeabi_idiv(int num:r0, int denom:r1)
+@
+@ Divide r0 by r1 and return quotient in r0 (all signed).
+@ Use __aeabi_uidivmod() but check signs before and change signs afterwards.
+@
+	.thumb_func
+        .global __aeabi_idiv
+__aeabi_idiv:
+
+	cmp	r0, #0
+	bge	.Lnumerator_pos
+	rsbs	r0, r0, #0		@ num = -num
+	cmp	r1, #0
+	bge	.Lneg_result
+	rsbs	r1, r1, #0		@ den = -den
+
+.Luidivmod:
+	b	__aeabi_uidivmod
+
+.Lnumerator_pos:
+	cmp	r1, #0
+	bge	.Luidivmod
+	rsbs	r1, r1, #0		@ den = -den
+
+.Lneg_result:
+	push	{lr}
+	bl	__aeabi_uidivmod
+	rsbs	r0, r0, #0		@ quot = -quot
+	pop	{pc}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/idivmod.s b/src/bsp/trustzone/teeloader/mt2701/src/idivmod.s
new file mode 100644
index 0000000..5fcbc1b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/idivmod.s
@@ -0,0 +1,136 @@
+/* Runtime ABI for the ARM Cortex-M0
+ * idivmod.S: signed 32 bit division (quotient and remainder)
+ *
+ * Copyright (c) 2012 Jörg Mische <bobbl@gmx.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+	.syntax unified
+	.text
+	.thumb
+	@.cpu cortex-m0
+
+
+
+@ {int quotient:r0, int remainder:r1}
+@ __aeabi_idivmod(int numerator:r0, int denominator:r1)
+@
+@ Divide r0 by r1 and return the quotient in r0 and the remainder in r1
+@
+	.thumb_func
+        .global __aeabi_idivmod
+__aeabi_idivmod:
+
+	cmp	r0, #0
+	bge	.Lnumerator_pos
+	rsbs	r0, r0, #0		@ num = -num
+	cmp	r1, #0
+	bge	.Lboth_neg
+
+	rsbs	r1, r1, #0		@ den = -den
+	push	{lr}
+	bl	__aeabi_uidivmod
+	rsbs	r1, r1, #0		@ rem = -rem
+	pop	{pc}
+
+.Lboth_neg:
+	push	{lr}
+	bl	__aeabi_uidivmod
+	rsbs	r0, r0, #0		@ quot = -quot
+	rsbs	r1, r1, #0		@ rem = -rem
+	pop	{pc}
+
+.Lnumerator_pos:
+	cmp	r1, #0
+	bge	.Luidivmod
+
+	rsbs	r1, r1, #0		@ den = -den
+	push	{lr}
+	bl	__aeabi_uidivmod
+	rsbs	r0, r0, #0		@ quot = -quot
+	pop	{pc}
+
+
+
+
+
+@ unsigned __udivsi3(unsigned num, unsigned denom)
+@
+@ libgcc wrapper: just an alias for __aeabi_uidivmod(), the remainder is ignored
+@
+	.thumb_func
+        .global __udivsi3
+__udivsi3:
+
+
+
+@ unsigned __aeabi_uidiv(unsigned num, unsigned denom)
+@
+@ Just an alias for __aeabi_uidivmod(), the remainder is ignored
+@
+	.thumb_func
+        .global __aeabi_uidiv
+__aeabi_uidiv:
+
+
+
+@ {unsigned quotient:r0, unsigned remainder:r1}
+@  __aeabi_uidivmod(unsigned numerator:r0, unsigned denominator:r1)
+@
+@ Divide r0 by r1 and return the quotient in r0 and the remainder in r1
+@
+	.thumb_func
+        .global __aeabi_uidivmod
+__aeabi_uidivmod:
+
+
+
+.Luidivmod:
+	cmp	r1, #0
+	bne	1f
+	b	__aeabi_idiv0
+1:
+
+	@ Shift left the denominator until it is greater than the numerator
+	movs	r2, #1		@ counter
+	movs	r3, #0		@ result
+	cmp	r0, r1
+	bls	.Lsub_loop
+	adds	r1, #0		@ dont shift if denominator would overflow
+	bmi	.Lsub_loop
+
+.Ldenom_shift_loop:
+	lsls	r2, #1
+	lsls	r1, #1
+	bmi	.Lsub_loop
+	cmp	r0, r1
+	bhi	.Ldenom_shift_loop
+
+.Lsub_loop:
+	cmp	r0, r1
+	bcc	.Ldont_sub	@ if (num>denom)
+
+	subs	r0, r1		@ numerator -= denom
+	orrs	r3, r2		@ result(r3) |= bitmask(r2)
+.Ldont_sub:
+
+	lsrs	r1, #1		@ denom(r1) >>= 1
+	lsrs	r2, #1		@ bitmask(r2) >>= 1
+	bne	.Lsub_loop
+
+	mov	r1, r0		@ remainder(r1) = numerator(r0)
+	mov	r0, r3		@ quotient(r0) = result(r3)
+	bx	lr
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/init.s b/src/bsp/trustzone/teeloader/mt2701/src/init.s
new file mode 100644
index 0000000..3da06a1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/init.s
@@ -0,0 +1,230 @@
+.section .text.start
+
+.equ MODE_USR       ,0x10
+.equ MODE_FIQ       ,0x11
+.equ MODE_IRQ       ,0x12
+.equ MODE_SVC       ,0x13
+.equ MODE_MON       ,0x16
+.equ MODE_ABT       ,0x17
+.equ MODE_UNDEF     ,0x1B
+.equ MODE_SYS       ,0x1F
+.equ I_BIT          ,0x80
+.equ F_BIT          ,0x40
+.equ INT_BIT        ,0xC0
+
+/* .equ RVBADDRESS_CPU0 ,0x10200038 */
+@.extern sys_stack
+@.extern sys_stack_sz
+@.extern bl31_base_addr
+@.extern rst_vector_base_addr
+/* wenmin: use this hard code to build pass, need check right number */
+sys_stack = 0xBFBF0000
+sys_stack_sz = 0x1000
+bl31_base_addr = 0x31
+rst_vector_base_addr = 0x0
+
+.globl _start
+.type  _start, function
+_start:
+	b resethandler
+bss_start:
+	.word _bss_start
+bss_end:
+	.word _bss_end
+stack:
+	.long sys_stack
+stacksz:
+	.long sys_stack_sz
+tee_entry:
+	.word 0x0
+
+resethandler:
+	ldr r5, =tee_entry
+	str r0, [r5]
+	MOV r0, #0
+	MOV r1, #0
+	MOV r2, #0
+	MOV r3, #0
+	MOV r4, #0
+	MOV r5, #0
+	MOV r6, #0
+	MOV r7, #0
+	MOV r8, #0
+	MOV r9, #0
+	MOV r10, #0
+	MOV r11, #0
+	MOV r12, #0
+	MOV sp, #0
+	MOV lr, #0
+
+	/* CONFIG_ARM_ERRATA_826319 */
+	mrc p15, 0, r8, c1, c0, 0    @ Read System Control Register into Rt
+	bic r8, r8, #0x4             @ disable D-Cache
+	bic r8, r8, #0x1000          @ clear I-Cache
+	mcr p15, 0, r8, c1, c0, 0    @ Write Rt to System Control Register
+
+	/* set the cpu to SVC32 mode */
+	MRS	r0,cpsr
+	BIC	r0,r0,#0x1f
+	ORR	r0,r0,#0xd3
+	MSR	cpsr,r0
+
+	/* disable interrupt */
+	MRS r0, cpsr
+	MOV r1, #INT_BIT
+	ORR r0, r0, r1
+	MSR cpsr_cxsf, r0
+
+	/* enable I+Z+SMP bits and disable D bit */
+	MRC p15, 0, ip, c1, c0, 0
+	ORR ip, ip, #0x1840   /* I+Z+SMP bits */
+	BIC ip, ip, #0x4      /* C bit */
+	MCR p15, 0, ip, c1, c0, 0
+
+clear_bss :
+	LDR r0, bss_start  /* find start of bss segment */
+	LDR r1, bss_end    /* stop here */
+	MOV r2, #0x00000000 /* clear */
+
+	CMP r0, r1
+	BEQ setup_stk
+
+	/*  clear loop... */
+clbss_l :
+	STR r2, [r0]
+	ADD r0, r0, #4
+	CMP r0, r1
+	BNE clbss_l
+
+setup_stk :
+	/* setup stack */
+	LDR r0, stack
+	LDR r1, =stacksz
+
+	/* buffer overflow detect pattern */
+	LDR r2, =0xDEADBEFF
+	STR r2, [r0]
+
+	LDR r1, [r1]
+	SUB r1, r1, #0x04
+	ADD r1, r0, r1
+
+	MOV sp, r1
+
+entry :
+	LDR r0, =tee_entry
+	LDR r0, [r0]
+	B   teeloader_main
+
+.globl jump
+.type  jump, function
+jump:
+	MOV r4, r1   /* r4 argument */
+	MOV r5, r2   /* r5 argument */
+	MOV pc, r0    /* jump to addr */
+
+.globl apmcu_icache_invalidate
+.type  apmcu_icache_invalidate, function
+apmcu_icache_invalidate:
+	MOV r0, #0
+	MCR p15, 0, r0, c7, c5, 0  /* CHECKME: c5 or c1 */
+	BX  lr
+
+.globl apmcu_isb
+.type  apmcu_isb, function
+apmcu_isb:
+	ISB
+	BX  lr
+
+.globl apmcu_disable_icache
+.type  apmcu_disable_icache, function
+apmcu_disable_icache:
+	MOV r0,#0
+	MCR p15,0,r0,c7,c5,6   /* Flush entire branch target cache */
+	MRC p15,0,r0,c1,c0,0
+	BIC r0,r0,#0x1800      /* I+Z bits */
+	MCR p15,0,r0,c1,c0,0
+	BX  lr
+
+.globl apmcu_disable_smp
+.type  apmcu_disable_smp, function
+apmcu_disable_smp:
+	MRC p15,0,r0,c1,c0,1
+	BIC r0,r0,#0x040       /* SMP bit */
+	MCR p15,0,r0,c1,c0,1
+	BX  lr
+
+.section .text.arch64
+.globl jumparch64
+.type  jumparch64, function
+jumparch64:
+	MOV r4, r1   /* r4 argument */
+	MOV r5, r2   /* r5 argument */
+	MOV r6, r0   /* keep LK jump addr */
+	
+	MOV r7, r3   /* r3 = TEE boot entry, relocate to r7 */
+
+	/* setup the reset vector base address after warm reset to Aarch64 */
+	LDR r0, =bl31_base_addr
+	LDR r0,[r0]
+
+	LDR r1, =rst_vector_base_addr
+	LDR r1,[r1]
+	str r0,[r1]
+
+	/* setup the excution state after warm reset: 1:Aarch64, 0:Aarch32 */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #1
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* do warm reset:reset request */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #2
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* set r0 as 0xC000_0000 for ATF OP code check */
+	MOV r0, #0xC0000000
+
+.globl WFI_LOOP
+.type  WFI_LOOP, function
+WFI_LOOP:
+	/* enter WFI to request a warm reset */
+	WFI
+	B WFI_LOOP
+
+.globl jumparch64_slt
+.type  jumparch64_slt, function
+jumparch64_slt:
+	/* setup the reset vector base address after warm reset to Aarch64 */
+	/* ldr r1,=RVBADDRESS_CPU0 */
+	/* ldr r1,[r1] */
+	/* LDR r0, =0x40000000 */
+	LDR r0, =0x40000000
+	LDR r1, =0x10200038
+	str r0,[r1]
+
+	/* setup the excution state after warm reset: 1:Aarch64, 0:Aarch32 */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #1
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* do warm reset:reset request */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #2
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* set r0 as 0x40000300 for dtb */
+	ldr r0, =0x40000300
+
+1:
+	/* enter WFI to request a warm reset */
+	WFI
+	B 1b
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/ldivmod.s b/src/bsp/trustzone/teeloader/mt2701/src/ldivmod.s
new file mode 100644
index 0000000..fc1f239
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/ldivmod.s
@@ -0,0 +1,252 @@
+/* Runtime ABI for the ARM Cortex-M0
+ * ldivmod.S: 64 bit division (quotient and remainder)
+ *
+ * Copyright (c) 2012-2017 Jörg Mische <bobbl@gmx.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+	.syntax unified
+	.text
+	.thumb
+	@.cpu cortex-m0
+
+
+
+@ {long long quotient, long long remainder}
+@ __aeabi_ldivmod(long long numerator, long long denominator)
+@
+@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder in
+@ r3:r2 (all signed)
+@
+	.thumb_func
+        .global __aeabi_ldivmod
+__aeabi_ldivmod:
+
+	cmp	r1, #0
+	bge	.Lnumerator_pos
+
+	push	{r4, lr}
+	movs	r4, #0			@ num = -num
+	rsbs	r0, r0, #0
+	sbcs	r4, r1
+	mov	r1, r4
+
+	cmp	r3, #0
+	bge	.Lboth_neg
+
+	movs	r4, #0			@ den = -den
+	rsbs	r2, r2, #0
+	sbcs	r4, r3
+	mov	r3, r4
+	bl	__aeabi_uldivmod
+	movs	r4, #0			@ rem = -rem
+	rsbs	r2, r2, #0
+	sbcs	r4, r3
+	mov	r3, r4
+	pop	{r4, pc}
+
+.Lboth_neg:
+	bl	__aeabi_uldivmod
+	movs	r4, #0			@ quot = -quot
+	rsbs	r0, r0, #0
+	sbcs	r4, r1
+	mov	r1, r4
+	movs	r4, #0			@ rem = -rem
+	rsbs	r2, r2, #0
+	sbcs	r4, r3
+	mov	r3, r4
+	pop	{r4, pc}
+
+.Lnumerator_pos:
+	cmp	r3, #0
+	bge	.Luldivmod
+
+	push	{r4, lr}
+	movs	r4, #0			@ den = -den
+	rsbs	r2, r2, #0
+	sbcs	r4, r3
+	mov	r3, r4
+	bl	__aeabi_uldivmod
+	movs	r4, #0			@ quot = -quot
+	rsbs	r0, r0, #0
+	sbcs	r4, r1
+	mov	r1, r4
+	pop	{r4, pc}
+
+
+
+
+@ unsigned long long __udivdi3(unsigned long long num, unsigned long long denom)
+@
+@ libgcc wrapper: just an alias for __aeabi_uldivmod(), the remainder is ignored
+@
+	.thumb_func
+        .global __udivdi3
+__udivdi3:
+
+
+
+@ {unsigned long long quotient, unsigned long long remainder}
+@ __aeabi_uldivmod(unsigned long long numerator, unsigned long long denominator)
+@
+@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder
+@ in r3:r2 (all unsigned)
+@
+	.thumb_func
+        .global __aeabi_uldivmod
+__aeabi_uldivmod:
+
+
+
+.Luldivmod:
+	cmp	r3, #0
+	bne	.L_large_denom
+	cmp	r2, #0
+	beq	.L_divison_by_0
+	cmp	r1, #0
+	beq	.L_fallback_32bits
+
+
+
+	@ case 1: num >= 2^32 and denom < 2^32
+	@ Result might be > 2^32, therefore we first calculate the upper 32
+	@ bits of the result. It is done similar to the calculation of the
+	@ lower 32 bits, but with a denominator that is shifted by 32.
+	@ Hence the lower 32 bits of the denominator are always 0 and the
+	@ costly 64 bit shift and sub operations can be replaced by cheap 32
+	@ bit operations.
+
+	push	{r4, r5, r6, r7, lr}
+
+	@ shift left the denominator until it is greater than the numerator
+	@ denom(r7:r6) = r3:r2 << 32
+
+	movs	r5, #1		@ bitmask
+	adds	r7, r2, #0	@ dont shift if denominator would overflow
+	bmi	.L_upper_result
+	cmp	r1, r7
+	blo	.L_upper_result
+
+.L_denom_shift_loop1:
+	lsls	r5, #1
+	lsls	r7, #1
+	bmi	.L_upper_result	@ dont shift if overflow
+	cmp	r1, r7
+	bhs	.L_denom_shift_loop1
+
+.L_upper_result:
+	mov	r3, r1
+	mov	r2, r0
+	movs	r1, #0		@ upper result = 0
+	b	.L_sub_entry1
+
+.L_sub_loop1:
+	lsrs	r7, #1		@ denom(r7:r6) >>= 1
+
+.L_sub_entry1:
+	cmp	r3, r7
+	bcc	.L_dont_sub1	@ if (num>denom)
+
+	subs	r3, r7		@ num -= denom
+	orrs	r1, r5		@ result(r7:r6) |= bitmask(r5)
+.L_dont_sub1:
+
+	lsrs	r5, #1		@ bitmask(r5) >>= 1
+	bne	.L_sub_loop1
+
+	movs	r5, #1
+	lsls	r5, #31
+	lsls	r6, r7, #31	@ denom(r7:r6) = (r7:0) >> 1
+	lsrs	r7, #1		@ dont forget least significant bit!
+	b	.L_lower_result
+
+
+
+	@ case 2: division by 0
+	@ call __aeabi_ldiv0
+
+.L_divison_by_0:
+	b	__aeabi_ldiv0
+
+
+
+	@ case 3: num < 2^32 and denom < 2^32
+	@ fallback to 32 bit division
+
+.L_fallback_32bits:
+	mov	r1, r2
+	push	{lr}
+	bl	__aeabi_uidivmod
+	mov	r2, r1
+	movs	r1, #0
+	movs	r3, #0
+	pop	{pc}
+
+
+
+	@ case 4: denom >= 2^32
+	@ result is smaller than 2^32
+
+.L_large_denom:
+	push	{r4, r5, r6, r7, lr}
+
+	mov	r7, r3
+	mov	r6, r2
+	mov	r3, r1
+	mov	r2, r0
+
+	@ Shift left the denominator until it is greater than the numerator
+
+	movs	r1, #0		@ high word of result is 0
+	movs	r5, #1		@ bitmask
+	adds	r7, #0		@ dont shift if denominator would overflow
+	bmi	.L_lower_result
+	cmp	r3, r7
+	blo	.L_lower_result
+
+.L_denom_shift_loop4:
+	lsls	r5, #1
+	lsls	r7, #1
+	lsls	r6, #1
+	adcs	r7, r1		@ r1=0
+	bmi	.L_lower_result	@ dont shift if overflow
+	cmp	r3, r7
+	bhs	.L_denom_shift_loop4
+
+
+
+.L_lower_result:
+	eors	r0, r0
+
+.L_sub_loop4:
+	mov	r4, r3
+	cmp	r2, r6
+	sbcs	r4, r7
+	bcc	.L_dont_sub4	@ if (num>denom)
+
+	subs	r2, r6		@ numerator -= denom
+	sbcs	r3, r7
+	orrs	r0, r5		@ result(r1:r0) |= bitmask(r5)
+.L_dont_sub4:
+
+	lsls	r4, r7, #31	@ denom(r7:r6) >>= 1
+	lsrs	r6, #1
+	lsrs	r7, #1
+	orrs	r6, r4
+	lsrs	r5, #1		@ bitmask(r5) >>= 1
+	bne	.L_sub_loop4
+
+	pop	{r4, r5, r6, r7, pc}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/main.c b/src/bsp/trustzone/teeloader/mt2701/src/main.c
new file mode 100644
index 0000000..4f5cb14
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/main.c
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/print.c b/src/bsp/trustzone/teeloader/mt2701/src/print.c
new file mode 100644
index 0000000..4c8140a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/print.c
@@ -0,0 +1,287 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "dram_buffer.h"
+#include "uart.h"
+
+#define C_LOG_SRAM_BUF_SIZE (20480)
+static char log_sram_buf[C_LOG_SRAM_BUF_SIZE];
+
+#define LOG_BUFFER_MAX_SIZE (0x10000)
+#define log_dram_buf g_dram_buf->log_dram_buf
+
+char *log_ptr;
+char *log_hdr;
+char *log_end;
+static int g_log_drambuf = 1;
+static int g_log_disable = 0;
+
+static int g_log_miss_chrs = 0;
+
+static void outchar(const char c)
+{
+	if (g_log_disable) {
+		if (log_ptr < log_end)
+			*log_ptr++ = (char)c;
+		else
+			g_log_miss_chrs++;
+	} else {
+		uart_putc(c);
+	}
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void log_buf_ctrl(int drambuf)
+{
+	if (drambuf) {
+		if ((g_log_disable) && (!g_log_drambuf)) {
+			char *buf_ptr = log_hdr;
+			U32 buf_len = log_ptr - log_hdr;
+
+			log_hdr = (char *)log_dram_buf;
+			log_end = log_hdr + LOG_BUFFER_MAX_SIZE;
+			log_ptr = log_hdr;
+			if (buf_len) {
+				memcpy(log_hdr, buf_ptr, buf_len);
+				log_ptr = log_hdr + buf_len;
+			}
+			if (g_log_miss_chrs) {
+				outstr("\n{MISS: ");
+				outdec(g_log_miss_chrs);
+				outstr(" chars}\n");
+				g_log_miss_chrs = 0;
+			}
+		} else if (!g_log_disable) {
+			log_hdr = (char *)log_dram_buf;
+			log_end = log_hdr + LOG_BUFFER_MAX_SIZE;
+			log_ptr = log_hdr;
+		}
+	} else {
+		log_hdr = (char *)log_sram_buf;
+		log_end = log_hdr + C_LOG_SRAM_BUF_SIZE;
+		log_ptr = log_hdr;
+	}
+
+	g_log_drambuf = drambuf ? 1 : 0;
+}
+
+void log_ctrl(int enable)
+{
+	u32 len;
+	char *ptr;
+
+	g_log_disable = enable ? 0 : 1;
+
+	/* flush log and reset log buf ptr */
+	if (enable) {
+		ptr = (char *)log_hdr;
+		len = (u32) log_ptr - (u32) ptr;
+		for (; len; len--) {
+			//outchar(*ptr++);
+		}
+		log_ptr = log_hdr;
+	}
+}
+
+int log_status(void)
+{
+	return g_log_disable == 0 ? 1 : 0;
+}
+
+void dbg_print(char *fmt, ...)
+{
+	print(fmt);
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+#ifdef __ARM_EABI__
+					/* Normally, compiler uses r0 to r6 to pass 32-bit or 64-bit 
+					 * arguments. But with EABI, 64-bit arguments will be aligned 
+					 * to an _even_ numbered register. for example:
+					 *
+					 *   int foo(int a, long long b, int c)
+					 *
+					 *   EABI: r0: a, r1: unused, r2-r3: b, r4: c
+					 *   Normal: r0: a, r1-r2: b, r3:c
+					 * 
+					 * For this reason, need to align to even numbered register
+					 * to retrieve 64-bit argument.
+					 */
+
+					/* odd and unused argument */
+					if (reg & 0x1) {
+						/* 64-bit argument starts from next 32-bit register */
+						reg++;
+						/* ignore this 32-bit register */
+						ltmp = va_arg(vl, unsigned int);
+					}
+					reg++;	/* 64-bit argument uses one more 32-bit register */
+#endif
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+
+	va_end(args);
+}
+
+void tl_print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/stdlib.c b/src/bsp/trustzone/teeloader/mt2701/src/stdlib.c
new file mode 100644
index 0000000..73c7d1f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/stdlib.c
@@ -0,0 +1,164 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+char *strchr(const char *p, int ch)
+{
+	for (;; ++p) {
+		if (*p == ch)
+			return ((char *)p);
+		if (!*p)
+			return ((char *)NULL);
+	}
+	/* NOTREACHED */
+}
+
+int atoi(const char *s)
+{
+	/* make digits[] size 4 bytes align */
+	static const char digits[12] = "0123456789";	/* legal digits in order */
+	unsigned val = 0;	/* value we're accumulating */
+	int neg = 0;		/* set to true if we see a minus sign */
+
+	/* skip whitespace */
+	while (*s == ' ' || *s == '\t') {
+		s++;
+	}
+
+	/* check for sign */
+	if (*s == '-') {
+		neg = 1;
+		s++;
+	} else if (*s == '+') {
+		s++;
+	}
+
+	/* process each digit */
+	while (*s) {
+		const char *where;
+		unsigned digit;
+
+		/* look for the digit in the list of digits */
+		where = strchr(digits, *s);
+		if (where == 0) {
+			/* not found; not a digit, so stop */
+			break;
+		}
+
+		/* get the index into the digit list, which is the value */
+		digit = (where - digits);
+
+		/* could (should?) check for overflow here */
+
+		/* shift the number over and add in the new digit */
+		val = val * 10 + digit;
+
+		/* look at the next character */
+		s++;
+	}
+
+	/* handle negative numbers */
+	if (neg) {
+		return -val;
+	}
+
+	/* done */
+	return val;
+}
+
+int isdigit(char c)
+{
+	return ((c >= '0') && (c <= '9'));
+}
+
+int isxdigit(char c)
+{
+	return isdigit(c) || ((c >= 'a') && (c <= 'f'))
+	    || ((c >= 'A') && (c <= 'F'));
+}
+
+int hexval(char c)
+{
+	if ((c >= '0') && (c <= '9')) {
+		return c - '0';
+	}
+
+	if ((c >= 'a') && (c <= 'f')) {
+		return c - 'a' + 10;
+	}
+
+	if ((c >= 'A') && (c <= 'F')) {
+		return c - 'A' + 10;
+	}
+}
+
+long long atoll(const char *num)
+{
+	long long value = 0;
+	unsigned long long max;
+	int neg = 0;
+
+	if (num[0] == '0' && num[1] == 'x') {
+		// hex
+		num += 2;
+		while (*num && isxdigit(*num)) {
+			value = value * 16 + hexval(*num++);
+		}
+	} else {
+		// decimal
+		if (num[0] == '-') {
+			neg = 1;
+			num++;
+		}
+		while (*num && isdigit(*num))
+			value = value * 10 + *num++ - '0';
+	}
+
+	if (neg)
+		value = -value;
+
+	max = value;
+	return value;
+}
+
+void longjmperror(void)
+{
+	//ASSERT(0);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/string.c b/src/bsp/trustzone/teeloader/mt2701/src/string.c
new file mode 100644
index 0000000..aa455ad
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/string.c
@@ -0,0 +1,119 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+	const char *sc;
+
+	for (sc = s; *sc != '\0'; ++sc) {
+	}
+	return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+	signed char __res;
+
+	while (1) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+	}
+	return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+	signed char __res = 0;
+
+	while (count) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+		count--;
+	}
+	return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void *memset(void *s, int c, int count)
+{
+	char *xs = s;
+
+	while (count--)
+		*xs++ = c;
+
+	return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void *memcpy(void *dest, const void *src, int count)
+{
+	char *tmp = dest;
+	const char *s = src;
+
+	while (count--)
+		*tmp++ = *s++;
+
+	return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+	const unsigned char *su1, *su2;
+	int res = 0;
+
+	for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+		if ((res = *su1 - *su2) != 0)
+			break;
+
+	return res;
+}
+
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2701/src/uart.c b/src/bsp/trustzone/teeloader/mt2701/src/uart.c
new file mode 100644
index 0000000..c42cb04
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+	
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+	
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+	
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2701/tllink.lds b/src/bsp/trustzone/teeloader/mt2701/tllink.lds
new file mode 100644
index 0000000..d55d335
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/tllink.lds
@@ -0,0 +1,51 @@
+OUTPUT_ARCH(arm)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {	
+		*(.text.start)
+	} 
+
+	. = . + 0x01FC;
+	.rom_info ALIGN(4) : {	    	    	    	     
+		*(.data.rom_info)
+	} 
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)        
+	} 
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)        
+	} 
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)        
+	} 
+	.got ALIGN(4) : {
+		*(.got)
+		*(.got.*)        
+	} 
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+	.secbuf ALIGN(4) : {
+		_secbuf_start = .;
+		*(.secbuf)
+		_secbuf_end = .;
+	} 
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2701/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2701/zero_padding.sh
new file mode 100755
index 0000000..79b2c5b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2701/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	#rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt2712/Makefile b/src/bsp/trustzone/teeloader/mt2712/Makefile
new file mode 100644
index 0000000..d4e10e6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/Makefile
@@ -0,0 +1,76 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/device_apc.c \
+	$(DIR_SRC)/security/tz_init.c \
+	$(DIR_SRC)/security/tz_emi_mpu.c \
+	$(DIR_SRC)/security/tz_sec_cfg.c \
+	$(DIR_SRC)/security/seclib.c \
+	$(DIR_SRC)/drivers/tz_apc.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+	$(DIR_SRC)/security/tz_tbase.c
+endif
+ifeq ($(CFG_TRUSTKERNEL_TEE_SUPPORT),1)
+CSRCS += \
+	$(DIR_SRC)/security/tz_tkcore.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin -fno-stack-protector ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak
new file mode 100644
index 0000000..01ad308
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak
@@ -0,0 +1,12 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+# CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+# For Trustonic TEE default
+# CFG_TEE_SECMEM_SIZE = 0x3000000
+# For OPTEE default
+CFG_TEE_SECMEM_SIZE = 0x1000000
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak
new file mode 100644
index 0000000..e2b275d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x1000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak
new file mode 100644
index 0000000..30f2492
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak
new file mode 100644
index 0000000..67a218f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak
@@ -0,0 +1,9 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+#CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TRUSTKERNEL_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x1000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/default.mak b/src/bsp/trustzone/teeloader/mt2712/default.mak
new file mode 100644
index 0000000..6b85857
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/default.mak
@@ -0,0 +1,14 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT2712
+CFG_ATF_LOG_SUPPORT := 1
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+CFG_TZ_SRAMROM_SUPPORT := 1
+CFG_TZ_UART_APDMA_SUPPORT := 1
+CFG_TINYSYS_SCP_SUPPORT := 1
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x77e00000
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/feature.mak b/src/bsp/trustzone/teeloader/mt2712/feature.mak
new file mode 100644
index 0000000..e033ece
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/feature.mak
@@ -0,0 +1,68 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTKERNEL_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTKERNEL_TEE_SUPPORT=${CFG_TRUSTKERNEL_TEE_SUPPORT}
+export CFG_TRUSTKERNEL_TEE_SUPPORT
+endif
+
+ifdef CFG_OPTEE_TEE_SUPPORT
+C_OPTION += -DCFG_OPTEE_TEE_SUPPORT=${CFG_OPTEE_TEE_SUPPORT}
+export CFG_OPTEE_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
+
+ifdef CFG_TZ_SRAMROM_SUPPORT
+C_OPTION += -DCFG_TZ_SRAMROM_SUPPORT=${CFG_TZ_SRAMROM_SUPPORT}
+export CFG_TZ_SRAMROM_SUPPORT
+endif
+
+ifdef CFG_TZ_UART_APDMA_SUPPORT
+C_OPTION += -DCFG_TZ_UART_APDMA_SUPPORT=${CFG_TZ_UART_APDMA_SUPPORT}
+export CFG_TZ_UART_APDMA_SUPPORT
+endif
+
+ifdef CFG_TINYSYS_SCP_SUPPORT
+C_OPTION += -DCFG_TINYSYS_SCP_SUPPORT=${CFG_TINYSYS_SCP_SUPPORT}
+export CFG_TINYSYS_SCP_SUPPORT
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
new file mode 100644
index 0000000..7d5b170
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
@@ -0,0 +1,427 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+#define DEVAPC0_AO_BASE         (0x1000E000U)
+#define DEVAPC0_PD_BASE         (0x10207000U)
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define DEVAPC0_D0_APC_0        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0000))
+#define DEVAPC0_D0_APC_1        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0004))
+#define DEVAPC0_D0_APC_2        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0008))
+#define DEVAPC0_D0_APC_3        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x000C))
+#define DEVAPC0_D0_APC_4        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0010))
+#define DEVAPC0_D0_APC_5        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0014))
+#define DEVAPC0_D0_APC_6        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0018))
+#define DEVAPC0_D0_APC_7        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x001C))
+#define DEVAPC0_D0_APC_8        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_9        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_10       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0024))
+#define DEVAPC0_D0_APC_11       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0028))
+#define DEVAPC0_D0_APC_12       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0030))
+#define DEVAPC0_D1_APC_0        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0100))
+#define DEVAPC0_D1_APC_1        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0104))
+#define DEVAPC0_D1_APC_2        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0108))
+#define DEVAPC0_D1_APC_3        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x010C))
+#define DEVAPC0_D1_APC_4        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0110))
+#define DEVAPC0_D1_APC_5        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0114))
+#define DEVAPC0_D1_APC_6        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0118))
+#define DEVAPC0_D1_APC_7        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x011C))
+#define DEVAPC0_D1_APC_8        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_9        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_10       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0124))
+#define DEVAPC0_D1_APC_11       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0128))
+#define DEVAPC0_D1_APC_12       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0130))
+#define DEVAPC0_D2_APC_0        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0200))
+#define DEVAPC0_D2_APC_1        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0204))
+#define DEVAPC0_D2_APC_2        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0208))
+#define DEVAPC0_D2_APC_3        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x020C))
+#define DEVAPC0_D2_APC_4        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0210))
+#define DEVAPC0_D2_APC_5        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0214))
+#define DEVAPC0_D2_APC_6        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0218))
+#define DEVAPC0_D2_APC_7        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x021C))
+#define DEVAPC0_D2_APC_8        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_9        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_10       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0224))
+#define DEVAPC0_D2_APC_11       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0228))
+#define DEVAPC0_D2_APC_12       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0230))
+#define DEVAPC0_D3_APC_0        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0300))
+#define DEVAPC0_D3_APC_1        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0304))
+#define DEVAPC0_D3_APC_2        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0308))
+#define DEVAPC0_D3_APC_3        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x030C))
+#define DEVAPC0_D3_APC_4        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0310))
+#define DEVAPC0_D3_APC_5        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0314))
+#define DEVAPC0_D3_APC_6        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0318))
+#define DEVAPC0_D3_APC_7        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x031C))
+#define DEVAPC0_D3_APC_8        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_9        ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_10       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0324))
+#define DEVAPC0_D3_APC_11       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0328))
+#define DEVAPC0_D3_APC_12       ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0330))
+#define DEVAPC0_MAS_DOM_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0400))
+#define DEVAPC0_MAS_DOM_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0404))
+#define DEVAPC0_MAS_DOM_GROUP_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0408))
+#define DEVAPC0_MAS_SEC_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0500))
+#define DEVAPC0_MAS_SEC_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0504))
+#define DEVAPC0_APC_CON         ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F00))
+#define DEVAPC0_PD_APC_CON      ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F00))
+#define DEVAPC_APC_CON_CTRL     (0x1U)
+#define DEVAPC_APC_CON_EN       (0x1U)
+#define MASTER_MSDC0            4U
+
+typedef enum {
+    NON_SECURE_TRAN = 0,
+    SECURE_TRAN,
+} E_TRANSACTION;
+
+
+///* DOMAIN_SETUP */
+#define DOMAIN_0  0U
+#define DOMAIN_1  1U
+#define DOMAIN_2  2U
+#define DOMAIN_3  3U
+#define CONN2AP  (0xf << 16)//index12   DEVAPC0_MAS_DOM_1
+#define GPU      (0xf << 20)//index21   DEVAPC0_MAS_DOM_2
+
+static inline unsigned int uffs(unsigned int x)
+{
+    unsigned int r = 1;
+
+    if (!x)
+        return 0;
+    if (!(x & 0xffff)) {
+        x >>= 16;
+        r += 16;
+    }
+    if (!(x & 0xff)) {
+        x >>= 8;
+        r += 8;
+    }
+    if (!(x & 0xf)) {
+        x >>= 4;
+        r += 4;
+    }
+    if (!(x & 3)) {
+        x >>= 2;
+        r += 2;
+    }
+    if (!(x & 1)) {
+        x >>= 1;
+        r += 1;
+    }
+    return r;
+}
+
+#define reg_read16(reg)        __raw_readw(reg)
+#define reg_read32(reg)        __raw_readl(reg)
+#define reg_write16(reg,val)   __raw_writew(val,reg)
+#define reg_write32(reg,val)   __raw_writel(val,reg)
+
+#define reg_set_bits(reg,bs)   ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs)   ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        tv &= ~(field); \
+        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+        reg_write32(reg,tv); \
+    } while(0)
+
+#define reg_get_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+    } while(0)
+
+#define DAPC_SEC_RW_NSEC_RW     0U /* read and write for both secure and non-secure access */
+#define DAPC_SEC_RW             1U /* read and write for secure access */
+#define DAPC_NSEC_RW            2U /* read and write for non-secure access */
+#define DAPC_SEC_DENY_NSEC_DENY 3U /* Any access is prohibited */
+
+#define DAPC_NS_TRANSACTION 0U /* Emit non-secure signal sideband */
+#define DAPC_S_TRANSACTION  1U /* Emit secure signal sideband */
+
+#define MASTER_NFI           0U
+#define MASTER_PWM           2U
+#define MASTER_THERMAL_CTRL  3U
+#define MASTER_MSDC0         4U
+#define MASTER_MSDC1         5U
+#define MASTER_MSDC2         6U
+#define MASTER_MSDC3         7U
+#define MASTER_SPI0          8U
+#define MASTER_SPM           9U
+#define MASTER_DEBUG_SYSTEM 11U
+#define MASTER_AUDIO_AFE    12U
+#define MASTER_APMCU        13U
+#define MASTER_MFG_M0       19U
+#define MASTER_USB30        20U
+#define MASTER_SPI1         22U
+#define MASTER_SPI2         23U
+#define MASTER_SPI3         24U
+#define MASTER_SPI4         25U
+#define MASTER_SPI5         26U
+#define MASTER_SCP          27U
+#define MASTER_USB30_2      28U
+#define MASTER_SFLASH       29U
+#define MASTER_GMAC         30U
+#define MASTER_PCIE0        31U
+#define MASTER_PCIE1        32U
+
+#define MODULE_TRANSACTION(index, is_secure) (is_secure << (index % 32))
+#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)
+
+#define MODULE_DOMAIN(index, domain) (domain << (2 * (index % 16)))
+#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)
+
+#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(devapc_register, permission) reg_write32(devapc_register, permission)
+
+#define INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR         0U
+#define INFRA_AO_INFRASYS_CONFIG_REGS              1U
+/* #define Reserved                                   2U */
+#define INFRA_AO_PERISYS_CONFIG_REGS               3U
+/* #define Reserved                                   4U */
+#define INFRA_AO_GPIO_CONTROLLER                   5U
+#define INFRA_AO_TOP_LEVEL_SLP_MANAGER             6U
+#define INFRA_AO_TOP_LEVEL_RESET_GENERATOR         7U
+#define INFRA_AO_GPT                               8U
+/* #define Reserved                                   9U */
+#define INFRA_AO_SEJ                               10U
+#define INFRA_AO_APMCU_EINT_CONTROLLER             11U
+#define SYS_TIMER_CONTROL_REG                      12U
+#define IRRX_CONTROL_REG                           13U
+#define INFRA_AO_DEVICE_APC_AO                     14U
+#define UART5_REG                                  15U
+#define INFRA_AO_KPAD_CONTROL_REG                  16U
+#define TOP_RTC_REG                                17U
+#define SPI4_REG                                   18U
+#define SPI1_REG                                   19U
+#define INFRA_AO_GPT2                              20U
+#define DRAMC_CH0_REG                              21U
+#define DRAMC_CH1_REG                              22U
+#define DRAMC_CH2_REG                              23U
+#define DRAMC_CH3_REG                              24U
+#define INFRASYS_MCUSYS_CONFIG_REG                 25U
+#define INFRASYS_CONTROL_REG                       26U
+#define INFRASYS_BOOTROM_SRAM                      27U
+#define INFRASYS_EMI_BUS_INTERFACE                 28U
+#define INFRASYS_SYSTEM_CIRQ                       29U
+#define INFRASYS_M4U_CONFIGURATION                 30U
+#define INFRASYS_EFUSEC                            31U
+#define INFRASYS_DEVICE_APC_MONITOR                32U
+#define BUS_DEBUG_TRAKER                           33U
+#define INFRASYS_AP_MIXED_CONTROL_REG              34U
+#define INFRASYS_M4U_2_CONFIGURATION               35U
+#define ANA_MIPI_DSI3                              36U
+/* #define Reserved                                   37U */
+#define INFRASYS_MBIST_CONTROL_REG                 38U
+#define INFRASYS_EMI_MPU_CONTROL_REG               39U
+#define INFRASYS_TRNG                              40U
+#define INFRASYS_GCPU                              41U
+#define INFRASYS_GCPU_NS                           42U
+#define INFRASYS_CQ_DMA                            43U
+#define INFRASYS_GCPU_M4U                          44U
+#define ANA_MIPI_DSI2                              45U
+#define ANA_MIPI_DSI0                              46U
+#define ANA_MIPI_DSI1                              47U
+#define ANA_MIPI_CSI0                              48U
+#define ANA_MIPI_CSI1                              49U
+/* #define Reserved                                   50U */
+#define DEGBUG_CORESIGHT                           51U
+#define DMA                                        52U
+#define AUXADC                                     53U
+#define UART0                                      54U
+#define UART1                                      55U
+#define UART2                                      56U
+#define UART3                                      57U
+#define PWM                                        58U
+#define I2C0                                       59U
+#define I2C1                                       60U
+#define I2C2                                       61U
+#define SPI0                                       62U
+#define THERM_CTRL                                 63U
+/* #define Reserved                                   64U */
+#define SPI_NOR                                    65U
+#define NFI                                        66U
+#define NFI_ECC                                    67U
+#define I2C3                                       68U
+#define I2C4                                       69U
+/* #define Reserved                                   70U */
+#define I2C5                                       71U
+/* #define Reserved                                   72U */
+#define SPI2                                       73U
+#define SPI3                                       74U
+/* #define Reserved                                   75U */
+/* #define Reserved                                   76U */
+#define UART4                                      77U
+/* #define Reserved                                   78U */
+#define GMAC                                       79U
+/* #define Reserved                                   80U */
+/* #define Reserved                                   81U */
+#define AUDIO                                      82U
+#define MSDC0                                      83U
+#define MSDC1                                      84U
+#define MSDC2                                      85U
+#define MSDC3                                      86U
+#define USB3_0                                     87U
+#define USB3_0SIF                                  88U
+#define USB3_0SIF2                                 89U
+#define USB3_0_2                                   90U
+#define USB3_0SIF_2                                91U
+#define USB3_0SIF2_2                               92U
+#define SCPSYS_SRAM                                93U
+#define PCIe0                                      94U
+#define PCIe1                                      95U
+#define G3D_CONFIG                                 96U
+#define MMSYS_CONFIG                               97U
+#define MDP_RDMA0                                  98U
+#define MDP_RDMA1                                  99U
+#define MDP_RSZ0                                   100U
+#define MDP_RSZ1                                   101U
+#define MDP_RSZ2                                   102U
+#define MDP_WDMA                                   103U
+#define MDP_WROT0                                  104U
+#define MDP_WROT1                                  105U
+#define MDP_TDSHP0                                 106U
+#define MDP_TDSHP1                                 107U
+/* #define Reserved                                   108U */
+#define DISP_OVL0                                  109U
+#define DISP_OVL1                                  110U
+#define DISP_RDMA0                                 111U
+#define DISP_RDMA1                                 112U
+#define DISP_RDMA2                                 113U
+#define DISP_WDMA0                                 114U
+#define DISP_WDMA1                                 115U
+#define DISP_COLOR0                                116U
+#define DISP_COLOR1                                117U
+#define DISP_AAL                                   118U
+#define DISP_GAMMA                                 119U
+/* #define Reserved                                   120U */
+#define DISP_SPLIT0                                121U
+/* #define Reserved                                   122U */
+#define DISP_UFOE                                  123U
+#define DSI0                                       124U
+#define DSI1                                       125U
+#define DPI                                        126U
+#define DISP_PWM0                                  127U
+#define DISP_PWM1                                  128U
+#define MM_MUTEX                                   129U
+#define SMI_LARB0                                  130U
+#define SMI_COMMON                                 131U
+#define DISP_OD                                    132U
+#define DPI1                                       133U
+/* #define Reserved                                   134U */
+#define LVDS                                       135U
+#define SMI_LARB4                                  136U
+#define MDP_RDMA2                                  137U
+#define DISP_COLOR2                                138U
+#define DISP_AAL1                                  139U
+#define DISP_OD1                                   140U
+#define DISP_OVL2                                  141U
+#define DISP_WDMA2                                 142U
+#define LVDS1                                      143U
+#define MDP_TDSHP2                                 144U
+#define SMI_LARB5                                  145U
+#define SMI_COMMON1                                146U
+#define SMI_LARB7                                  147U
+#define MDP_RDMA3                                  148U
+#define MDP_WROT2                                  149U
+#define DSI2                                       150U
+#define DSI3                                       151U
+/* #define Reserved                                   152U */
+#define DISP_MONITOR0                              153U
+#define DISP_MONITOR1                              154U
+#define DISP_MONITOR2                              155U
+#define DISP_MONITOR3                              156U
+#define DISP_PWM2                                  157U
+#define IMGSYS_CONFIG                              158U
+#define SMI_LARB2                                  159U
+#define SENINF_TOP0                                160U
+#define SENINF_TOP1                                161U
+#define CAMSV_TOP0                                 162U
+#define CAMSV_TOP1                                 163U
+#define CAMSV_TOP2                                 164U
+#define CAMSV_TOP3                                 165U
+#define CAMSV_TOP4                                 166U
+#define CAMSV_TOP5                                 167U
+/* #define Reserved                                   168U */
+/* #define Reserved                                   169U */
+/* #define Reserved                                   170U */
+/* #define Reserved                                   171U */
+/* #define Reserved                                   172U */
+/* #define Reserved                                   173U */
+#define BDP_DISPSYS_CONFIG                         174U
+#define BDP_DISPFMT                                175U
+#define BDP_VDO                                    176U
+#define BDP_NR                                     177U
+#define BDP_NR2                                    178U
+#define BDP_TVD                                    179U
+#define BDP_WR_CHANNEL_DI                          180U
+#define BDP_WR_CHANNEL_VDI                         181U
+#define BDP_LARB                                   182U
+#define BDP_LARB_RT                                183U
+#define BDP_DRAM2AXI_BRIDGE                        184U
+#define VDECSYS_CONFIGURATION                      185U
+#define VDECSYS_SMI_LARB1                          186U
+#define VDEC_FULL_TOP                              187U
+#define IMGRZ                                      188U
+#define VDEC_MBIST                                 189U
+#define JPGDEC_CONFIGURATION                       190U
+#define JPDEC                                      191U
+#define JPDGDEC1                                   192U
+/* #define Reserved                                   193U */
+#define VENC_CONFIGURATION                         194U
+#define VENC_SMI_LARB3                             195U
+#define VENC_SMI_LARB6                             196U
+#define SMI_COMMON_2                               197U
+#define VENC                                       198U
+/*  #define Reserved                                   199U */
+#define SFLASH                                     200U
+
+extern void device_APC_dom_setup(void);
+extern void tz_dapc_sec_setting(void);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
new file mode 100644
index 0000000..926bc1f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
@@ -0,0 +1,53 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+				unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/platform.h b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
new file mode 100644
index 0000000..51dca91
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR	(0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE	(0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE               (0x800000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE               (0x800000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE           (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0xA000000UL) /* TEE max DRAM size is 160MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE           (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/print.h b/src/bsp/trustzone/teeloader/mt2712/include/print.h
new file mode 100644
index 0000000..732dc0e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/print.h
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define REL_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/seclib.h b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
new file mode 100644
index 0000000..abb4c8e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX          (0xFFFFFFFFUL)    /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/string.h b/src/bsp/trustzone/teeloader/mt2712/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
new file mode 100644
index 0000000..e49da76
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
@@ -0,0 +1,178 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE   (0U)
+#endif
+#ifndef TRUE
+#define TRUE    (1U)
+#endif
+
+#ifndef NULL
+#define NULL    (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define printf	print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
new file mode 100644
index 0000000..c593c94
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
@@ -0,0 +1,155 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2018 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_APC_H
+#define TZ_APC_H
+
+#include "typedefs.h"
+
+/*****************************************************************************
+ * Register base address definition
+ *****************************************************************************/
+
+#define SRAMROM_SEC_CTRL                ((volatile unsigned int*)(0x10001804U))
+#define SRAMROM_SEC_ADDR                ((volatile unsigned int*)(0x10001808U))
+
+/* APDMA */
+#define APDMA_GLOBAL_GSEC_CTRL          ((volatile unsigned int*)(0x11000014U))
+#define APDMA_UART_TX0_SEC_CTRL         ((volatile unsigned int*)(0x11000038U))
+#define APDMA_UART_RX0_SEC_CTRL         ((volatile unsigned int*)(0x1100003CU))
+#define APDMA_UART_TX1_SEC_CTRL         ((volatile unsigned int*)(0x11000040U))
+#define APDMA_UART_RX1_SEC_CTRL         ((volatile unsigned int*)(0x11000044U))
+#define APDMA_UART_TX2_SEC_CTRL         ((volatile unsigned int*)(0x11000048U))
+#define APDMA_UART_RX2_SEC_CTRL         ((volatile unsigned int*)(0x1100004CU))
+#define APDMA_UART_TX3_SEC_CTRL         ((volatile unsigned int*)(0x11000050U))
+#define APDMA_UART_RX3_SEC_CTRL         ((volatile unsigned int*)(0x11000054U))
+#define APDMA_UART_TX4_SEC_CTRL         ((volatile unsigned int*)(0x11000058U))
+#define APDMA_UART_RX4_SEC_CTRL         ((volatile unsigned int*)(0x1100005CU))
+#define APDMA_UART_TX5_SEC_CTRL         ((volatile unsigned int*)(0x11000060U))
+#define APDMA_UART_RX5_SEC_CTRL         ((volatile unsigned int*)(0x11000064U))
+#define APDMA_GLOBAL_GSEC_EN            0x1
+
+/* CQDMA */
+#define CQDMA_SEC_CTRL                  ((volatile unsigned int*)(0x10212C58U))
+
+/* SMI BDPSYS (larb8 and larb9) */
+#define SMI_BDPSYS_LARB8_BASE           ((volatile unsigned int*)(0x1501a000U))
+#define SMI_BDPSYS_LARB9_BASE           ((volatile unsigned int*)(0x1501a008U))
+#define SMI_BDPSYS_DOMAIN_MASK          (0xf0000)
+#define SMI_BDPSYS_AR_DOMAIN(dom)       (((dom) & 0x3) << 16)
+#define SMI_BDPSYS_AW_DOMAIN(dom)       (((dom) & 0x3) << 18)
+
+/*****************************************************************************
+ * Enum
+ *****************************************************************************/
+typedef enum
+{
+    TZ_APC_SEC_RW_NSEC_RW = 0,  /* read and write for both secure and non-secure access */
+    TZ_APC_SEC_RW_NSEC_DENY,    /* read and write for secure access */
+    TZ_APC_SEC_DENY_NSEC_RW,    /* read and write for non-secure access */
+    TZ_APC_SEC_DENY_NSEC_DENY   /* Any access is prohibited */
+} tz_apc_permission;
+
+typedef enum
+{
+    TZ_APC_DOMAIN_IVI = 0,      /* The domain is for in-vehicle infotainment system (normally Linux OS).  */
+    TZ_APC_DOMAIN_CLUSTER = 1,  /* The domain is for cluster system. */
+    TZ_APC_DOMAIN_DSP = 2,      /* The domain is for Audio DSP system. */
+    TZ_APC_DOMAIN_MCU = 3,      /* AP MCU will access the bus throgh the domain ID. The MCU used by any of the sub-system,
+                                   including IVI, cluster, and DSP will access the bus with this domain.
+                                   This domain can access almost all the slave devices in secure and non-secure mode and
+                                   hence we must apply the MMU and MPU to protect the device access and memory access in
+                                   the system. */
+} tz_apc_domain_partition;
+
+typedef enum
+{
+    TZ_SRAMROM_SEC_RW_NSEC_RW = 0,      /* read and write for both secure and non-secure access */
+    TZ_SRAMROM_SEC_RW_NSEC_DENY = 1,    /* read and write for secure access */
+    TZ_SRAMROM_SEC_RW_NSEC_RO = 2,      /* read and write for secure access and read only for non-secure access */
+    TZ_SRAMROM_SEC_RW_NSEC_WO = 3,      /* read and write for secure access and write only for non-secure access */
+    TZ_SRAMROM_SEC_RO_NSEC_RO = 4,      /* read only for both secure access and non-secure access */
+    TZ_SRAMROM_SEC_DENY_NSEC_DENY = 7  /* Any access is prohibited */
+} tz_sramrom_permission;
+
+typedef enum
+{
+    TZ_UART_APDMA_NSEC = 0,    /* Read and write with non-secure sideband AXI signal. */
+    TZ_UART_APDMA_SEC = 1,    /* Read and write with secure sideband AXI signal. */
+} tz_uart_apdma_permission;
+
+typedef enum
+{
+    TZ_CQDMA_NSEC = 0,    /* Read and write with non-secure sideband AXI signal. */
+    TZ_CQDMA_SEC = 1,    /* Read and write with secure sideband AXI signal. */
+} tz_cpdma_permission;
+
+typedef enum
+{
+    TZ_SRAMROM_REGION_0 = 0,        /* Region 0 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+    TZ_SRAMROM_REGION_1 = 1         /* Region 1 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+} tz_sramrom_region;
+
+/*****************************************************************************
+ * Functions
+ *****************************************************************************/
+
+#define reg_read16(reg)        __raw_readw(reg)
+#define reg_read32(reg)        __raw_readl(reg)
+#define reg_write16(reg,val)   __raw_writew(val,reg)
+#define reg_write32(reg,val)   __raw_writel(val,reg)
+
+static inline u32 tz_sramrom_set_bitwise_domain_permision(tz_sramrom_region region,
+    tz_apc_domain_partition domain, tz_sramrom_permission permission)
+{
+    return (permission & 0x7) << ((domain * 3) + (region == TZ_SRAMROM_REGION_1 ? 16: 0));
+}
+
+/* Enabling this bit to protect all multimedia secure related registers, including SMI,
+   accessing in non-secure world. */
+#define TZ_SRAMROM_ENABLE_MULTIMEDIA_SECURE_ACCESS (u32)(0x1 << 30)
+
+/* Enabling this bit to protect sramrom region 1 by region 1's security setting */
+#define TZ_SRAMROM_ENABLE_REGION_1_PROTECTION (u32)(0x1 << 28)
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0). */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size) (reg_write32(SRAMROM_SEC_ADDR, ((size & 0xff) << 10)))
+
+extern void tz_apc_common_init();
+extern void tz_apc_common_postinit();
+
+#endif /* TZ_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET      (0x40000000UL)
+#define EMI_MPU_ALIGNMENT   (0x10000UL)
+#define PERIAXI_BUS_CTL3    (0x10003208UL)
+#define PERISYS_4G_SUPPORT  (0x1 << 11)
+
+
+typedef enum
+{
+    TZ_MPU_SEC_RW_NSEC_RW = 0,      /* read and write for both secure and non-secure access */
+    TZ_MPU_SEC_RW_NSEC_DENY = 1,    /* read and write for secure access */
+    TZ_MPU_SEC_RW_NSEC_RO = 2,      /* read and write for secure access and read only for non-secure access */
+    TZ_MPU_SEC_RW_NSEC_WO = 3,      /* read and write for secure access and write only for non-secure access */
+    TZ_MPU_SEC_RO_NSEC_RO = 4,      /* read only for both secure access and non-secure access */
+    TZ_MPU_SEC_DENY_NSEC_DENY = 5,  /* Any access is prohibited */
+    TZ_MPU_SEC_RO_NSEC_RW = 6       /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID    (0)
+#define ATF_MPU_REGION_ID          (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE                (0x1020E000U)
+
+#define EMI_MPU_SA0                 ((P_U32)(EMI_MPU_BASE+0x100))  /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1                 ((P_U32)(EMI_MPU_BASE+0x104))  /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2                 ((P_U32)(EMI_MPU_BASE+0x108))  /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3                 ((P_U32)(EMI_MPU_BASE+0x10C))  /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4                 ((P_U32)(EMI_MPU_BASE+0x110))  /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5                 ((P_U32)(EMI_MPU_BASE+0x114))  /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6                 ((P_U32)(EMI_MPU_BASE+0x118))  /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7                 ((P_U32)(EMI_MPU_BASE+0x11C))  /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0                 ((P_U32)(EMI_MPU_BASE+0x200))  /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1                 ((P_U32)(EMI_MPU_BASE+0x204))  /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2                 ((P_U32)(EMI_MPU_BASE+0x208))  /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3                 ((P_U32)(EMI_MPU_BASE+0x20C))  /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4                 ((P_U32)(EMI_MPU_BASE+0x210))  /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5                 ((P_U32)(EMI_MPU_BASE+0x214))  /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6                 ((P_U32)(EMI_MPU_BASE+0x218))  /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7                 ((P_U32)(EMI_MPU_BASE+0x21C))  /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0                ((P_U32)(EMI_MPU_BASE+0x300))  /* EMI MPU APC 0 */
+#define EMI_MPU_APC1                ((P_U32)(EMI_MPU_BASE+0x304))  /* EMI MPU APC 1 */
+#define EMI_MPU_APC2                ((P_U32)(EMI_MPU_BASE+0x308))  /* EMI MPU APC 2 */
+#define EMI_MPU_APC3                ((P_U32)(EMI_MPU_BASE+0x30C))  /* EMI MPU APC 3 */
+#define EMI_MPU_APC4                ((P_U32)(EMI_MPU_BASE+0x310))  /* EMI MPU APC 4 */
+#define EMI_MPU_APC5                ((P_U32)(EMI_MPU_BASE+0x314))  /* EMI MPU APC 5 */
+#define EMI_MPU_APC6                ((P_U32)(EMI_MPU_BASE+0x318))  /* EMI MPU APC 6 */
+#define EMI_MPU_APC7                ((P_U32)(EMI_MPU_BASE+0x31C))  /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0             ((P_U32)(EMI_MPU_BASE+0x900))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1             ((P_U32)(EMI_MPU_BASE+0x904))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2             ((P_U32)(EMI_MPU_BASE+0x908))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3             ((P_U32)(EMI_MPU_BASE+0x90C))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4             ((P_U32)(EMI_MPU_BASE+0x910))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5             ((P_U32)(EMI_MPU_BASE+0x914))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6             ((P_U32)(EMI_MPU_BASE+0x918))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7             ((P_U32)(EMI_MPU_BASE+0x91C))  /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
new file mode 100644
index 0000000..6778589
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+
+#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+    u64 boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+	unsigned int atf_magic;
+	unsigned int tee_support;
+	unsigned int tee_boot_arg_addr;
+	unsigned int tee_entry;
+	unsigned int hwuid[4];     // HW Unique id for t-base used
+	unsigned int HRID[2];      // HW random id for t-base used
+	unsigned int atf_log_port;
+	unsigned int atf_log_baudrate;
+	unsigned int atf_log_buf_start;
+	unsigned int atf_log_buf_size;
+	unsigned int atf_aee_debug_buf_start;
+	unsigned int atf_aee_debug_buf_size;
+	unsigned int devinfo[DEVINFO_SIZE];
+	unsigned int atf_irq_num;
+	unsigned int msg_auth_key[8]; /* size of message auth key is 256 bits */
+#if CFG_TEE_SUPPORT
+	unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
new file mode 100644
index 0000000..c330423
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
@@ -0,0 +1,102 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS   (0x00100000UL)
+#define SRAM_START_ADDR     (0x00102140UL)
+#define VECTOR_START        (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+    short next, previous;
+} tz_memory_t;
+
+#define FREE            ((short)(0x0001U))
+#define IS_FREE(x)      ((x)->next & FREE)
+#define CLEAR_FREE(x)   ((x)->next &= ~FREE)
+#define SET_FREE(x)     ((x)->next |= FREE)
+#define FROM_ADDR(x)    ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x)      ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC                   (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION                 (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE        (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE       (0x200000UL) //2MB by default
+
+#define BL31                            (0x44e01000UL)
+#define BL31_SIZE                       (0x40000UL) //change to 256KB (192KB by default)
+#define BL33                            (0x73500000UL)
+
+#define ATF_BOOT_ARG_ADDR				(0x40000000UL)
+#define ATF_INIT_ARG_ADDR				(0x40000100UL)
+#define TEE_BOOT_ARG_ADDR				(0x44e00100UL)
+
+#define TEE_PARAMETER_BASE (TEE_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR           (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE           (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+    unsigned int magic;              // Magic number
+    unsigned int version;            // version
+    unsigned int svp_mem_start;      // MM sec mem pool start addr.
+    unsigned int svp_mem_end;        // MM sec mem pool end addr.
+    unsigned int tplay_table_start;  // tplay handle-to-physical table start
+    unsigned int tplay_table_size;   // tplay handle-to-physical table size
+    unsigned int tplay_mem_start;    // tplay physcial memory start address for crypto operation
+    unsigned int tplay_mem_size;     // tplay phsycial memory size for crypto operation
+    unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+    unsigned int rpmb_size;          /* size of rpmb partition */
+    unsigned int msg_auth_key[8];    /* size of message auth key is 32bytes(256 bits) */
+    unsigned int emmc_rel_wr_sec_c;  // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+    u32 magic;        // magic value from information
+    u32 length;       // size of struct in bytes.
+    u64 version;      // Version of structure
+    u64 dRamBase;     // NonSecure DRAM start address
+    u64 dRamSize;     // NonSecure DRAM size
+    u64 secDRamBase;  // Secure DRAM start address
+    u64 secDRamSize;  // Secure DRAM size
+    u64 secIRamBase;  // Secure IRAM base
+    u64 secIRamSize;  // Secure IRam size
+    u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+    u32 RFU1;
+    u32 MSMPteCount;  // Number of MMU entries for MSM
+    u64 MSMBase;      // MMU entries for MSM
+    u64 gic_distributor_base;
+    u64 gic_cpuinterface_base;
+    u32 gic_version;
+    u32 RFU2;
+    u64 flags;
+    u32 total_number_spi;
+    u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
new file mode 100644
index 0000000..57efd71
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
@@ -0,0 +1,80 @@
+#ifndef TZ_TKCORE_H
+#define TZ_TKCORE_H
+
+#include "typedefs.h"
+
+#define TKCORE_BOOTCFG_MAGIC    (0x54534958)
+
+#define TEE_ARGUMENT_VERSION_LEGACY (0x00010000U)
+#define TEE_ARGUMENT_VERSION_V1_0   (0x00010001U)
+#define TEE_ARGUMENT_VERSION_V1_1   (0x00010002U)
+#define TEE_ARGUMENT_VERSION_V1_2   (0x00010003U)
+
+#define TEE_ARGUMENT_VERSION        TEE_ARGUMENT_VERSION_V1_2
+
+#define TKCORE_SHM_SIZE_LIMIT   (0x400000U)
+
+#define RPMB_KEY_SIZE    32
+
+#define SDRPMB_FAILURE_MAGIC    (0xCDCDCDCDU)
+/* effective data size */
+#define SDRPMB_DATA_SIZE        (1U << 20)
+/* size of two write protected regions */
+#define SDRPMB_REGION_SIZE      (16U << 20)
+/* granu of sdrpmb region */
+#define SDRPMB_REGION_ALIGNMENT (8U << 20)
+
+typedef struct {
+    u32 magic;        // magic value from information
+    u32 length;       // size of struct in bytes.
+    u64 version;      // Version of structure
+    u64 dRamBase;     // NonSecure DRAM start address
+    u64 dRamSize;     // NonSecure DRAM size
+    u64 secDRamBase;  // Secure DRAM start address
+    u64 secDRamSize;  // Secure DRAM size
+    u64 secIRamBase;  // Secure IRAM base
+    u64 secIRamSize;  // Secure IRam size
+    u64 gic_distributor_base;
+    u64 gic_cpuinterface_base;
+    u32 gic_version;
+    u32    uart_base;
+    u32 total_number_spi;
+    u32 ssiq_number;
+    u64 flags;
+    u8  rpmb_key[RPMB_KEY_SIZE];
+
+    /* for TEE_ARGUMENT_VERSION_1 */
+    u8 rpmb_key_programmed;
+
+    /* for TEE_ARGUMENT_VERSION_2 (mt6580 specific) */
+    u32 nw_bootargs;
+    u32 nw_bootargs_size;
+
+    /* for TEE_ARGUMENT_VERSION_3 */
+    u32 sdrpmb_partaddr;
+    u32 sdrpmb_partsize;
+    u32 sdrpmb_starting_sector;
+    u32 sdrpmb_nr_sectors;
+
+    u8 resv[7];
+} __attribute__((packed)) tee_arg_t, *tee_arg_t_ptr;
+
+void tkcore_boot_param_prepare(u64 param_addr, u64 tee_entry,
+    u64 sec_dram_size, u64 dram_base, u64 dram_size, u32 uart_base);
+
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+void tkcore_boot_param_prepare_sdrpmb_region(part_t *part);
+
+void tkcore_boot_param_prepare_sdrpmb_data(mblock_info_t *mblock, blkdev_t *bootdev);
+
+void tkcore_boot_sdrpmb_init_finish(u32 param_addr);
+#endif
+
+void tkcore_boot_param_prepare_rpmbkey(u32 param_addr);
+
+void tkcore_boot_param_prepare_nwbootargs(u32 param_addr,
+    u32 addr, u32 size);
+
+void tkcore_dump_param(u32 param_addr);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/uart.h b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
new file mode 100644
index 0000000..9db4093
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE      (1U << 5U)
+#define UART_THR(uart)     (UART_BASE(uart) + 0x0U)  /* Write only */
+
+#define IO_PHYS            (0x10000000UL)
+#define UART1_BASE         (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a b/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a
new file mode 100644
index 0000000..8504221
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c
new file mode 100644
index 0000000..bee32c4
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c
@@ -0,0 +1,1199 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES                                                          */
+/*=======================================================================*/
+#include "device_apc.h"
+#include "print.h"
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE       (0x00000000U)      /* No event */
+#define DBG_EVT_ERR        (0x00000001U)      /* ERR related event */
+#define DBG_EVT_DOM        (0x00000002U)      /* DOM related event */
+
+#define DBG_EVT_ALL        (0xffffffffU)
+
+#define DBG_EVT_MASK       (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+    do {    \
+    if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+    print(fmt, ##args); \
+    } \
+    } while(0)
+
+#define MSG_FUNC_ENTRY(f)   MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{} while(0)
+#define MSG_FUNC_ENTRY(f)      do{} while(0)
+#endif
+
+void tz_dapc_set_master_transaction(unsigned int  master_index , E_TRANSACTION permisssion_control)
+{
+    reg_set_field(DEVAPC0_MAS_SEC_GROUP_0 , (0x1 << master_index), permisssion_control);
+}
+
+void tz_dapc_sec_init(void)
+{
+    /* lock dapc to security access only */
+    reg_write32(DEVAPC0_APC_CON, 0x1);
+
+    /* tz_dapc_set_master_transaction(MASTER_MSDC0 , SECURE_TRAN); */
+}
+
+void tz_dapc_sec_postinit(void)
+{
+    /* tz_dapc_set_master_transaction(MASTER_MSDC0 , NON_SECURE_TRAN); */
+}
+
+void device_APC_dom_setup(void)
+{
+    MSG(DOM, "\nDevice APC domain init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_2));
+#endif
+    /*Set masters to DOMAINX here if needed*/
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Device APC domain after setup:\n");
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_2));
+#endif
+}
+
+void tz_dapc_sec_setting(void)
+{
+    /* Set domain of masters */
+    DAPC_SET_MASTER_DOMAIN(
+        DEVAPC0_MAS_DOM_GROUP_0,
+        MODULE_DOMAIN(MASTER_NFI,          DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_PWM,          DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_THERMAL_CTRL, DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_MSDC0,        DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_MSDC1,        DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_MSDC2,        DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_MSDC3,        DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI0,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPM,          DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_DEBUG_SYSTEM, DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_AUDIO_AFE,    DOMAIN_2) |
+        MODULE_DOMAIN(MASTER_APMCU,        DOMAIN_3)
+    );
+
+    DAPC_SET_MASTER_DOMAIN(
+        DEVAPC0_MAS_DOM_GROUP_1,
+        MODULE_DOMAIN(MASTER_MFG_M0,       DOMAIN_1) |
+        MODULE_DOMAIN(MASTER_USB30,        DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI1,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI2,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI3,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI4,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SPI5,         DOMAIN_0) |
+#ifdef CFG_TINYSYS_SCP_SUPPORT
+        MODULE_DOMAIN(MASTER_SCP,          DOMAIN_3) |
+#else
+        MODULE_DOMAIN(MASTER_SCP,          DOMAIN_1) |
+#endif
+        MODULE_DOMAIN(MASTER_USB30_2,      DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_SFLASH,       DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_GMAC,         DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_PCIE0,        DOMAIN_0)
+    );
+
+    DAPC_SET_MASTER_DOMAIN(
+        DEVAPC0_MAS_DOM_GROUP_2,
+        MODULE_DOMAIN(MASTER_PCIE1,       DOMAIN_0)
+    );
+
+    /* Set the transaction type of masters*/
+    DAPC_SET_MASTER_TRANSACTION(
+        DEVAPC0_MAS_SEC_GROUP_0,
+        MODULE_TRANSACTION(MASTER_NFI,          DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_PWM,          DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_THERMAL_CTRL, DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_MSDC0,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_MSDC1,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_MSDC2,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_MSDC3,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI0,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPM,          DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_DEBUG_SYSTEM, DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_AUDIO_AFE,    DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_APMCU,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_MFG_M0,       DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_USB30,        DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI1,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI2,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI3,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI4,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SPI5,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SCP,           DAPC_S_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_USB30_2,      DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SFLASH,       DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_GMAC,         DAPC_NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_PCIE0,        DAPC_NS_TRANSACTION)
+    );
+
+    DAPC_SET_MASTER_TRANSACTION(
+        DEVAPC0_MAS_SEC_GROUP_1,
+        MODULE_TRANSACTION(MASTER_PCIE1,        DAPC_NS_TRANSACTION)
+    );
+
+   /* Set the access permission of slaves in domain 0*/
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_0,
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS        ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_GPT                        ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_SEJ                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SYS_TIMER_CONTROL_REG               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IRRX_CONTROL_REG                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO              ,DAPC_SEC_RW) |
+        MODULE_PERMISSION(UART5_REG                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_1,
+        MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(TOP_RTC_REG                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI4_REG                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI1_REG                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_GPT2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH0_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH1_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH2_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH3_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_CONTROL_REG                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EFUSEC                     ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_2,
+        MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BUS_DEBUG_TRAKER                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI3                       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_TRNG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU_NS                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_CQ_DMA                     ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU_M4U                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI1                       ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_3,
+        MODULE_PERMISSION(ANA_MIPI_CSI0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_CSI1                       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DEGBUG_CORESIGHT                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DMA                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(AUXADC                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART1                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART2                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART3                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(PWM                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C1                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(THERM_CTRL                          ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_4,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SPI_NOR                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(NFI                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(NFI_ECC                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C3                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C4                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(I2C5                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SPI2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI3                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(UART4                               ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(GMAC                                ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_5,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(AUDIO                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC1                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC2                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC3                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0_2                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF_2                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF2_2                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SCPSYS_SRAM                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PCIe0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(PCIe1                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_6,
+        MODULE_PERMISSION(G3D_CONFIG                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MMSYS_CONFIG                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ0                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ2                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WDMA                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_TDSHP0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_TDSHP1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_OVL0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OVL1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_RDMA0                          ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_7,
+        MODULE_PERMISSION(DISP_RDMA1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_RDMA2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_AAL                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_GAMMA                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_SPLIT0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_UFOE                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DPI                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_PWM0                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_8,
+        MODULE_PERMISSION(DISP_PWM1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MM_MUTEX                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OD                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DPI1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(LVDS                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB4                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR2                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_AAL1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OD1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OVL2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(LVDS1                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_9,
+        MODULE_PERMISSION(MDP_TDSHP2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB5                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB7                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA3                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_MONITOR0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR1                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR3                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_PWM2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IMGSYS_CONFIG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB2                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_10,
+        MODULE_PERMISSION(SENINF_TOP0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SENINF_TOP1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP3                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP4                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP5                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(BDP_DISPSYS_CONFIG                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_DISPFMT                         ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_11,
+        MODULE_PERMISSION(BDP_VDO                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_NR                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_NR2                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_TVD                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_DI                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_VDI                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_LARB                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_LARB_RT                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDECSYS_CONFIGURATION               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDECSYS_SMI_LARB1                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDEC_FULL_TOP                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IMGRZ                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDEC_MBIST                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(JPGDEC_CONFIGURATION                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(JPDEC                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+        DEVAPC0_D0_APC_12,
+        MODULE_PERMISSION(JPDGDEC1                            ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(VENC_CONFIGURATION                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC_SMI_LARB3                      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC_SMI_LARB6                      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON_2                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SFLASH                              ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    /* Set the access permission of slaves in domain 1*/
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_0,
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS       ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS        ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_GPT                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_SEJ                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SYS_TIMER_CONTROL_REG               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IRRX_CONTROL_REG                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART5_REG                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_1,
+        MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(TOP_RTC_REG                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI4_REG                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI1_REG                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_GPT2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH0_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH1_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH2_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH3_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_CONTROL_REG                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EFUSEC                     ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_2,
+        MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BUS_DEBUG_TRAKER                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI3                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_TRNG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU_NS                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_CQ_DMA                     ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU_M4U                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI1                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_CSI0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_CSI1                       ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_3,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DEGBUG_CORESIGHT                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DMA                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(AUXADC                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART1                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART2                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART3                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PWM                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(THERM_CTRL                          ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_4,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SPI_NOR                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(NFI                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(NFI_ECC                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C4                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(I2C5                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SPI2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(UART4                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(GMAC                                ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_5,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(AUDIO                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC1                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC2                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC3                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0_2                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF_2                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF2_2                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SCPSYS_SRAM                         ,DAPC_SEC_RW) |
+        MODULE_PERMISSION(PCIe0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PCIe1                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_6,
+        MODULE_PERMISSION(G3D_CONFIG                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MMSYS_CONFIG                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ0                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ1                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ2                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WDMA                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_TDSHP0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_TDSHP1                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_OVL0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OVL1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_RDMA0                          ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_7,
+        MODULE_PERMISSION(DISP_RDMA1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_RDMA2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR0                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_AAL                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_GAMMA                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_SPLIT0                         ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_UFOE                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI1                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DPI                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_PWM0                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_8,
+        MODULE_PERMISSION(DISP_PWM1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MM_MUTEX                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OD                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DPI1                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(LVDS                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB4                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR2                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_AAL1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OD1                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OVL2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(LVDS1                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_9,
+        MODULE_PERMISSION(MDP_TDSHP2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB5                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB7                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA3                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI3                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_MONITOR0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR1                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR3                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_PWM2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IMGSYS_CONFIG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB2                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_10,
+        MODULE_PERMISSION(SENINF_TOP0                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SENINF_TOP1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP3                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP4                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP5                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(BDP_DISPSYS_CONFIG                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_DISPFMT                         ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_11,
+        MODULE_PERMISSION(BDP_VDO                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_NR                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_NR2                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_TVD                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_DI                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_VDI                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_LARB                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_LARB_RT                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDECSYS_CONFIGURATION               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDECSYS_SMI_LARB1                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDEC_FULL_TOP                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IMGRZ                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDEC_MBIST                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(JPGDEC_CONFIGURATION                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(JPDEC                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+        DEVAPC0_D1_APC_12,
+        MODULE_PERMISSION(JPDGDEC1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(VENC_CONFIGURATION                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC_SMI_LARB3                      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC_SMI_LARB6                      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON_2                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SFLASH                              ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    /* Set the access permission of slaves in domain 2*/
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_0,
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS       ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS        ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_GPT                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRA_AO_SEJ                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SYS_TIMER_CONTROL_REG               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IRRX_CONTROL_REG                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART5_REG                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_1,
+        MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(TOP_RTC_REG                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI4_REG                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI1_REG                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRA_AO_GPT2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH0_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH1_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH2_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DRAMC_CH3_REG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_CONTROL_REG                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EFUSEC                     ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_2,
+        MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BUS_DEBUG_TRAKER                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI3                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_TRNG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU_NS                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_CQ_DMA                     ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(INFRASYS_GCPU_M4U                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_DSI1                       ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_3,
+        MODULE_PERMISSION(ANA_MIPI_CSI0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(ANA_MIPI_CSI1                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DEGBUG_CORESIGHT                    ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DMA                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(AUXADC                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART1                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART2                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(UART3                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PWM                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(THERM_CTRL                          ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_4,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SPI_NOR                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(NFI                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(NFI_ECC                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(I2C4                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(I2C5                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SPI2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SPI3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(UART4                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(GMAC                                ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_5,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(AUDIO                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC1                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC2                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MSDC3                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0_2                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF_2                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(USB3_0SIF2_2                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SCPSYS_SRAM                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PCIe0                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PCIe1                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_6,
+        MODULE_PERMISSION(G3D_CONFIG                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MMSYS_CONFIG                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ0                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RSZ2                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WDMA                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_TDSHP0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_TDSHP1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_OVL0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OVL1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_RDMA0                          ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_7,
+        MODULE_PERMISSION(DISP_RDMA1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_RDMA2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_AAL                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_GAMMA                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_SPLIT0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_UFOE                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI0                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DPI                                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_PWM0                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_8,
+        MODULE_PERMISSION(DISP_PWM1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MM_MUTEX                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB0                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OD                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DPI1                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(LVDS                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB4                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_COLOR2                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_AAL1                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OD1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_OVL2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_WDMA2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(LVDS1                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_9,
+        MODULE_PERMISSION(MDP_TDSHP2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB5                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB7                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_RDMA3                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(MDP_WROT2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI2                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DSI3                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(DISP_MONITOR0                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR1                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR2                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_MONITOR3                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(DISP_PWM2                           ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IMGSYS_CONFIG                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_LARB2                           ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_10,
+        MODULE_PERMISSION(SENINF_TOP0                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SENINF_TOP1                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP0                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP1                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP2                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP3                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP4                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(CAMSV_TOP5                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(BDP_DISPSYS_CONFIG                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_DISPFMT                         ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_11,
+        MODULE_PERMISSION(BDP_VDO                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_NR                              ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_NR2                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_TVD                             ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_DI                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_VDI                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_LARB                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_LARB_RT                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE                 ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDECSYS_CONFIGURATION               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDECSYS_SMI_LARB1                   ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDEC_FULL_TOP                       ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(IMGRZ                               ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VDEC_MBIST                          ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(JPGDEC_CONFIGURATION                ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(JPDEC                               ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+        DEVAPC0_D2_APC_12,
+        MODULE_PERMISSION(JPDGDEC1                            ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(VENC_CONFIGURATION                  ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC_SMI_LARB3                      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC_SMI_LARB6                      ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(SMI_COMMON_2                        ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(VENC                                ,DAPC_SEC_DENY_NSEC_DENY) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_DENY_NSEC_DENY) | */
+        MODULE_PERMISSION(SFLASH                              ,DAPC_SEC_DENY_NSEC_DENY)
+    );
+
+    /* Set the access permission of slaves in domain 3*/
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_0,
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS        ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_GPT                        ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRA_AO_SEJ                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SYS_TIMER_CONTROL_REG               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IRRX_CONTROL_REG                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO              ,DAPC_SEC_RW) |
+        MODULE_PERMISSION(UART5_REG                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_1,
+        MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(TOP_RTC_REG                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI4_REG                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI1_REG                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRA_AO_GPT2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH0_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH1_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH2_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DRAMC_CH3_REG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_CONTROL_REG                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EFUSEC                     ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_2,
+        MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BUS_DEBUG_TRAKER                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI3                       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_TRNG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU_NS                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_CQ_DMA                     ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(INFRASYS_GCPU_M4U                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_DSI1                       ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_3,
+        MODULE_PERMISSION(ANA_MIPI_CSI0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(ANA_MIPI_CSI1                       ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DEGBUG_CORESIGHT                    ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DMA                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(AUXADC                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART1                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART2                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(UART3                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(PWM                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C1                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(THERM_CTRL                          ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_4,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SPI_NOR                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(NFI                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(NFI_ECC                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C3                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(I2C4                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(I2C5                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SPI2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SPI3                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(UART4                               ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(GMAC                                ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_5,
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(AUDIO                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC1                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC2                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MSDC3                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0_2                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF_2                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(USB3_0SIF2_2                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SCPSYS_SRAM                         ,DAPC_SEC_DENY_NSEC_DENY) |
+        MODULE_PERMISSION(PCIe0                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(PCIe1                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_6,
+        MODULE_PERMISSION(G3D_CONFIG                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MMSYS_CONFIG                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ0                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ1                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RSZ2                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WDMA                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_TDSHP0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_TDSHP1                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_OVL0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OVL1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_RDMA0                          ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_7,
+        MODULE_PERMISSION(DISP_RDMA1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_RDMA2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR0                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_AAL                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_GAMMA                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_SPLIT0                         ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_UFOE                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI0                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI1                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DPI                                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_PWM0                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_8,
+        MODULE_PERMISSION(DISP_PWM1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MM_MUTEX                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB0                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OD                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DPI1                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(LVDS                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB4                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_COLOR2                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_AAL1                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OD1                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_OVL2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_WDMA2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(LVDS1                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_9,
+        MODULE_PERMISSION(MDP_TDSHP2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB5                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB7                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_RDMA3                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(MDP_WROT2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI2                                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DSI3                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(DISP_MONITOR0                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR1                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR2                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_MONITOR3                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(DISP_PWM2                           ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IMGSYS_CONFIG                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_LARB2                           ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_10,
+        MODULE_PERMISSION(SENINF_TOP0                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SENINF_TOP1                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP0                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP1                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP2                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP3                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP4                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(CAMSV_TOP5                          ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(BDP_DISPSYS_CONFIG                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_DISPFMT                         ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_11,
+        MODULE_PERMISSION(BDP_VDO                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_NR                              ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_NR2                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_TVD                             ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_DI                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_WR_CHANNEL_VDI                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_LARB                            ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_LARB_RT                         ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE                 ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDECSYS_CONFIGURATION               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDECSYS_SMI_LARB1                   ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDEC_FULL_TOP                       ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(IMGRZ                               ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VDEC_MBIST                          ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(JPGDEC_CONFIGURATION                ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(JPDEC                               ,DAPC_SEC_RW_NSEC_RW)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+        DEVAPC0_D3_APC_12,
+        MODULE_PERMISSION(JPDGDEC1                            ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(VENC_CONFIGURATION                  ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC_SMI_LARB3                      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC_SMI_LARB6                      ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(SMI_COMMON_2                        ,DAPC_SEC_RW_NSEC_RW) |
+        MODULE_PERMISSION(VENC                                ,DAPC_SEC_RW_NSEC_RW) |
+        /* MODULE_PERMISSION(Reserved                            ,DAPC_SEC_RW_NSEC_RW) | */
+        MODULE_PERMISSION(SFLASH                              ,DAPC_SEC_RW_NSEC_RW)
+    );
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c b/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c
new file mode 100644
index 0000000..80bbcc0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c
@@ -0,0 +1,211 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES                                                          */
+/*=======================================================================*/
+#include "tz_apc.h"
+#include "device_apc.h"
+#include "print.h"
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE       (0x00000000U)      /* No event */
+#define DBG_EVT_ERR        (0x00000001U)      /* ERR related event */
+#define DBG_EVT_DOM        (0x00000002U)      /* DOM related event */
+
+#define DBG_EVT_ALL        (0xffffffffU)
+
+#define DBG_EVT_MASK       (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+    do {    \
+        if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+            print(fmt, ##args); \
+        } \
+    } while(0)
+
+#define MSG_FUNC_ENTRY(f)   MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{}while(0)
+#define MSG_FUNC_ENTRY(f)      do{}while(0)
+#endif
+
+/* MTK SMI bdpsys larb domain setting (larb8 and larb9) */
+static void tz_apc_smi_bdpsys_sec_init()
+{
+    u32 reg, domain = 0;/* always be domain 0.*/
+
+    /* Larb8 */
+    reg = reg_read32(SMI_BDPSYS_LARB8_BASE);
+    reg &= ~SMI_BDPSYS_DOMAIN_MASK;
+    reg |= SMI_BDPSYS_AR_DOMAIN(domain) | SMI_BDPSYS_AW_DOMAIN(domain);
+    reg_write32(SMI_BDPSYS_LARB8_BASE, reg);
+
+    /* Larb9 */
+    reg = reg_read32(SMI_BDPSYS_LARB9_BASE);
+    reg &= ~SMI_BDPSYS_DOMAIN_MASK;
+    reg |= SMI_BDPSYS_AR_DOMAIN(domain) | SMI_BDPSYS_AW_DOMAIN(domain);
+    reg_write32(SMI_BDPSYS_LARB9_BASE, reg);
+}
+
+void tz_apc_common_init()
+{
+#ifdef CFG_TZ_SRAMROM_SUPPORT
+    u32 domain_permission = 0U;
+#endif /* CFG_TZ_SRAMROM_SUPPORT */
+
+#ifdef CFG_TZ_SRAMROM_SUPPORT
+    /* Enabling this bit to protect all multimedia secure related registers,
+       including SMI, accessing in non-secure world. */
+    domain_permission |= TZ_SRAMROM_ENABLE_MULTIMEDIA_SECURE_ACCESS;
+    /* Enable this bit to protect sramrom region 1 by its security setting */
+    domain_permission |= TZ_SRAMROM_ENABLE_REGION_1_PROTECTION;
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+        TZ_APC_DOMAIN_IVI, TZ_SRAMROM_SEC_RW_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+        TZ_APC_DOMAIN_CLUSTER, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+        TZ_APC_DOMAIN_DSP, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+        TZ_APC_DOMAIN_MCU, TZ_SRAMROM_SEC_RW_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+        TZ_APC_DOMAIN_IVI, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+        TZ_APC_DOMAIN_CLUSTER, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+        TZ_APC_DOMAIN_DSP, TZ_SRAMROM_SEC_RW_NSEC_RW);
+    domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+        TZ_APC_DOMAIN_MCU, TZ_SRAMROM_SEC_RW_NSEC_RW);
+    reg_write32(SRAMROM_SEC_CTRL, domain_permission);
+    TZ_SRAMROM_SET_REGION_0_SIZE_KB(96);
+#endif /* CFG_TZ_SRAMROM_SUPPORT */
+
+#ifdef CFG_TZ_UART_APDMA_SUPPORT
+
+    /* GLOBAL GSEC_EN */
+    reg_write32(APDMA_GLOBAL_GSEC_CTRL, reg_read32(APDMA_GLOBAL_GSEC_CTRL) | APDMA_GLOBAL_GSEC_EN);
+
+#if 0
+    /* Setting TX0/RX0 */
+    domain_permission = reg_read32(APDMA_UART_TX0_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX0_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX0_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX0_SEC_CTRL, domain_permission);
+
+    /* Setting TX1/RX1 */
+    domain_permission = reg_read32(APDMA_UART_TX1_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX1_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX1_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX1_SEC_CTRL, domain_permission);
+
+    /* Setting TX2/RX2 */
+    domain_permission = reg_read32(APDMA_UART_TX2_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX2_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX2_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX2_SEC_CTRL, domain_permission);
+
+    /* Setting TX3/RX3 */
+    domain_permission = reg_read32(APDMA_UART_TX3_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX3_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX3_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX3_SEC_CTRL, domain_permission);
+#endif
+
+    /* Setting TX4/RX4 */
+    domain_permission = reg_read32(APDMA_UART_TX4_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_IVI<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX4_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX4_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_IVI<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX4_SEC_CTRL, domain_permission);
+
+#if 0
+    /* Setting TX5/RX5 */
+    domain_permission = reg_read32(APDMA_UART_TX5_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_TX5_SEC_CTRL, domain_permission);
+
+    domain_permission = reg_read32(APDMA_UART_RX5_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_UART_APDMA_NSEC;
+    reg_write32(APDMA_UART_RX5_SEC_CTRL, domain_permission);
+
+    /* Setting CQDMA */
+    domain_permission = reg_read32(CQDMA_SEC_CTRL);
+    domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+    domain_permission |= TZ_CQDMA_NSEC;
+    reg_write32(CQDMA_SEC_CTRL, domain_permission);
+#endif
+#endif
+
+    /* Set domain of masters and their transaction type.
+       Set access permission of slaves in each domain. */
+    tz_dapc_sec_setting();
+}
+
+void tz_apc_common_postinit()
+{
+    tz_apc_smi_bdpsys_sec_init();
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/main.c b/src/bsp/trustzone/teeloader/mt2712/src/main.c
new file mode 100644
index 0000000..c3ea768
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/main.c
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#include "platform.h"
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg, unsigned long boot_reason)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = ATF_INIT_ARG_ADDR;
+    atf_arg->boot_reason = boot_reason;
+}
+
+int teeloader_main(unsigned long bl33_addr, unsigned long boot_reason)
+{
+    u32 tee_addr = 0;
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+
+    set_atf_parameters(atf_arg, boot_reason);
+
+    /* marked because no device APC support */
+	//device_APC_dom_setup();
+    trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+    tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+    /* set tee entry address */
+    tee_set_entry(tee_addr);
+    tee_set_hwuid();
+    tee_set_msg_auth_key();
+
+    trustzone_post_init();
+    trustzone_jump(BL31, BL33, tee_addr);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/print.c b/src/bsp/trustzone/teeloader/mt2712/src/print.c
new file mode 100644
index 0000000..34622c7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c b/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c
new file mode 100644
index 0000000..b70f923
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c
@@ -0,0 +1,88 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "hacc_export.h"
+#include "string.h"
+#include "print.h"
+
+#define HRID                            (0x10206140UL)
+#define SOC_DATA                        (0x08000000UL)
+#define HW_DATA_SIZE                    (0x4UL)
+
+#define MOD "[SECLIB]"
+
+int seclib_get_key(u32 hwaddr, u8 *key, u32 key_size, int index)
+{
+    u32 hwdata[HW_DATA_SIZE] = {0};
+    int i = 0;
+
+    if (key_size != sizeof(hwdata))
+    {
+        return -1;
+    }
+    for (i = 0; i < HW_DATA_SIZE; i++)
+    {
+        hwdata[i] = READ_REGISTER_UINT32(hwaddr + (i * sizeof(u32)));
+    }
+    if (0 != seclib_get_data_key((u8 *)hwdata, key_size, (u8 *)key, index))
+    {
+        return -1;
+    }
+    DBG_MSG("%s HWDATA : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, hwdata[0], hwdata[1], hwdata[2], hwdata[3]);
+
+    return 0;
+}
+
+int seclib_get_hrid_key(u32 *key, u32 key_size)
+{
+    u32 hrkey[HW_DATA_SIZE] = {0};
+
+    if (0 != seclib_get_key(HRID, (u8 *)hrkey, sizeof(hrkey), 1))
+    {
+        return -1;
+    }
+    key[0]=hrkey[0];
+    key[1]=hrkey[1];
+
+    return 0;
+}
+
+int seclib_get_hwid_key(u8 *key, u32 key_size)
+{
+    return seclib_get_key(SOC_DATA, key, key_size, 2);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..cbeb21a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c
@@ -0,0 +1,258 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+
+    if (end <= start)
+    {
+        DBG_MSG("%s, Invalid address! End address should larger than start address.\n", MOD);
+        return -1;
+    }
+
+
+    if((end >> 31) && !(start >> 31))
+    {
+        DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n", MOD);
+        return -1;
+    }
+
+    if ((readl(PERIAXI_BUS_CTL3) & PERISYS_4G_SUPPORT) == 0)
+    {
+        start = start - EMI_PHY_OFFSET;
+        end = end - EMI_PHY_OFFSET;
+        DBG_MSG("%s, MPU 2GB mode.\n", MOD);
+    }
+    else
+        DBG_MSG("%s, MPU 4GB mode.\n", MOD);
+
+    /*Address 64KB alignment*/
+    start = start >> 16;
+    end = end >> 16;
+
+    switch (region) {
+    case 0:
+        writel(0, EMI_MPU_APC0);
+        writel(start, EMI_MPU_SA0);
+        writel(end, EMI_MPU_EA0);
+        writel(access_permission, EMI_MPU_APC0);
+        break;
+
+    case 1:
+        writel(0, EMI_MPU_APC1);
+        writel(start, EMI_MPU_SA1);
+        writel(end, EMI_MPU_EA1);
+        writel(access_permission, EMI_MPU_APC1);
+        break;
+
+    case 2:
+        writel(0, EMI_MPU_APC2);
+        writel(start, EMI_MPU_SA2);
+        writel(end, EMI_MPU_EA2);
+        writel(access_permission, EMI_MPU_APC2);
+        break;
+
+    case 3:
+        writel(0, EMI_MPU_APC3);
+        writel(start, EMI_MPU_SA3);
+        writel(end, EMI_MPU_EA3);
+        writel(access_permission, EMI_MPU_APC3);
+        break;
+
+    case 4:
+        writel(0, EMI_MPU_APC4);
+        writel(start, EMI_MPU_SA4);
+        writel(end, EMI_MPU_EA4);
+        writel(access_permission, EMI_MPU_APC4);
+        break;
+
+    case 5:
+        writel(0, EMI_MPU_APC5);
+        writel(start, EMI_MPU_SA5);
+        writel(end, EMI_MPU_EA5);
+        writel(access_permission, EMI_MPU_APC5);
+        break;
+
+    case 6:
+        writel(0, EMI_MPU_APC6);
+        writel(start, EMI_MPU_SA6);
+        writel(end, EMI_MPU_EA6);
+        writel(access_permission, EMI_MPU_APC6);
+        break;
+
+    case 7:
+        writel(0, EMI_MPU_APC7);
+        writel(start, EMI_MPU_SA7);
+        writel(end, EMI_MPU_EA7);
+        writel(access_permission, EMI_MPU_APC7);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+/* sample code for scenario as below: */
+/* mpu region2: 0x40000000 - 0xe0000000 (2.5GB) is secure RW and non-secure RW for domain 0, 3.*/
+/* mpu region3: 0xe0000000 - 0xe0080000 (512K) is secure RW and non-secure RW for domain 0, 2, 3.*/
+/* mpu region4: 0xe0080000 - 0xe0880000 (8M) is secure and non-secure RW for domain 2, 3.*/
+/* mpu region5: 0xe0880000 - 0xec880000 (384M) is secure RW and non-secure RW for domain 1, 2, 3.*/
+/* mpu region6: 0xec880000 - 0xec8e0000 (384K) is secure RW and non-secure RW for domain 0, 1, 3.*/
+/* mpu region7: 0xec8e0000 - 0xf48e0000 (128M) is secure RW for domain 0, 3.*/
+
+void tz_emi_mpu_init_2(void)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+
+    /*region2 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0x40000000,               /*START_ADDR*/
+                                            0xe0000000,           /*END_ADDR*/
+                                            2,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region3 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xe0000000,               /*START_ADDR*/
+                                            0xe0080000,           /*END_ADDR*/
+                                            3,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region4 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0080000,               /*START_ADDR*/
+                                            0xe0880000,           /*END_ADDR*/
+                                            4,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region5 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0880000,               /*START_ADDR*/
+                                            0xec880000,           /*END_ADDR*/
+                                            5,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region6 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xec880000,               /*START_ADDR*/
+                                            0xec8e0000,           /*END_ADDR*/
+                                            6,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region7 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xec8e0000,               /*START_ADDR*/
+                                            0xf48e0000,           /*END_ADDR*/
+                                            7,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    if(ret)
+        DBG_MSG("%s MPU error!!\n", MOD);
+
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch(mpu_region)
+    {
+        case SECURE_OS_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        case ATF_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        default:
+            DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+            return;
+    }
+
+    DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,  /*START_ADDR*/
+                                        sec_mem_phy_end,    /*END_ADDR*/
+                                        mpu_region,         /*region*/
+                                        sec_mem_mpu_attr);
+
+    if(ret)
+    {
+        DBG_MSG("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c
new file mode 100644
index 0000000..7d05e99
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c
@@ -0,0 +1,268 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "seclib.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "tz_apc.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+#if CFG_TRUSTKERNEL_TEE_SUPPORT
+#include "tz_tkcore.h"
+#endif
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+/**************************************************************************
+ *  MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000U)  //4K Alignment
+#define TEE_ENABLE_VERIFY (1U)
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ *  INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+static u32 msg_auth_key[8];
+
+/**************************************************************************
+ *  INTERNAL FUNCTIONS
+ **************************************************************************/
+
+static u64 trustzone_get_atf_init_param_addr(void)
+{
+    return ATF_INIT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+
+void tee_set_entry(u32 addr)
+{
+    tee_entry_addr = addr;
+
+    DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(void)
+{
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[0], g_hwuid[1], g_hwuid[2], g_hwuid[3]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[4], g_hwuid[5], g_hwuid[6], g_hwuid[7]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[8], g_hwuid[9], g_hwuid[10], g_hwuid[11]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[12], g_hwuid[13], g_hwuid[14], g_hwuid[15]);
+    memcpy(teearg->hwuid, g_hwuid, sizeof(g_hwuid));
+    g_hwuid_initialized = 1;
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+    int ret = 0;
+
+    if (!g_hwuid_initialized)
+    {
+        ret = seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+        if(ret != 0)
+            return ret;
+    }
+    memcpy(id, g_hwuid, size);
+    return ret;
+}
+
+void tee_set_msg_auth_key(void)
+{
+    int i;
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    seclib_get_msg_auth_key((unsigned char *) msg_auth_key, 32);
+
+    DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[0], msg_auth_key[1], msg_auth_key[2], msg_auth_key[3]);
+    DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[4], msg_auth_key[5], msg_auth_key[6], msg_auth_key[7]);
+
+    memcpy(teearg->msg_auth_key, msg_auth_key, sizeof(msg_auth_key));
+}
+
+static void tee_sec_config(void)
+{
+    u32 atf_entry_addr = BL31;
+
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    /* memory protection for TEE */
+#if CFG_TRUSTKERNEL_TEE_SUPPORT
+    u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - TKCORE_SHM_SIZE_LIMIT - 1;
+#else
+    u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+#endif
+
+    tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+    DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+        secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+
+    /* memory protection for ATF */
+    atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+    u32 atf_end_addr = atf_entry_addr + BL31_SIZE - 1;
+
+    DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+    tz_sec_mem_init(atf_entry_addr, atf_end_addr, ATF_MPU_REGION_ID);
+    DBG_MSG("%s set ATF memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+        atf_end_addr, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+    tz_dapc_sec_init();
+
+#if CFG_ATF_LOG_SUPPORT
+    atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#endif
+
+#if CFG_TEE_SUPPORT
+    tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+    tz_apc_common_init();
+}
+
+void trustzone_post_init(void)
+{
+    atf_arg_t_ptr atf_init_arg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    atf_init_arg->atf_magic = ATF_BOOTCFG_MAGIC;
+    atf_init_arg->tee_entry = tee_entry_addr;
+    atf_init_arg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+    seclib_get_hrid_key(atf_init_arg->HRID, sizeof(atf_init_arg->HRID));
+    atf_init_arg->atf_log_port = 0x11002000;
+    atf_init_arg->atf_log_baudrate = 0xE1000;
+    atf_init_arg->atf_irq_num = 267; /* reserve SPI ID for ATF log */
+    atf_init_arg->devinfo[0] = 0;
+    atf_init_arg->devinfo[1] = 0;
+    atf_init_arg->devinfo[2] = 0xFFFFFFFF;
+    atf_init_arg->devinfo[3] = 0xFFFFFFFF;
+
+    DBG_MSG("%s HRID[0] : 0x%x\n", MOD, atf_init_arg->HRID[0]);
+    DBG_MSG("%s HRID[1] : 0x%x\n", MOD, atf_init_arg->HRID[1]);
+    DBG_MSG("%s atf_log_port : 0x%x\n", MOD, atf_init_arg->atf_log_port);
+    DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, atf_init_arg->atf_log_baudrate);
+    DBG_MSG("%s atf_irq_num : %d\n", MOD, atf_init_arg->atf_irq_num);
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+    tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        tee_secmem_size);
+    tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+    atf_init_arg->tee_support = 1;
+#elif CFG_TRUSTKERNEL_TEE_SUPPORT
+    tkcore_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, tee_secmem_size,
+            CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE,
+            atf_init_arg->atf_log_port);
+    tkcore_boot_param_prepare_rpmbkey(TEE_BOOT_ARG_ADDR);
+    /* only useful for non-ATF platform */
+    tkcore_boot_param_prepare_nwbootargs(TEE_BOOT_ARG_ADDR, 0U, 0U);
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+    tkcore_boot_sdrpmb_init_finish(TEE_BOOT_ARG_ADDR);
+#endif
+    //prepare the parameter for secure driver here
+    atf_init_arg->tee_support = 1;
+#elif CFG_OPTEE_TEE_SUPPORT
+    atf_init_arg->tee_support = 1;
+#else
+    atf_init_arg->tee_support = 0;
+#endif
+    tz_dapc_sec_postinit();
+    tz_apc_common_postinit();
+
+#if CFG_ATF_LOG_SUPPORT
+    atf_init_arg->atf_log_buf_start = atf_log_buf_start;
+    atf_init_arg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+    atf_init_arg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+    atf_init_arg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+    atf_init_arg->atf_log_buf_start = 0;
+    atf_init_arg->atf_log_buf_size = 0;
+    atf_init_arg->atf_aee_debug_buf_start = 0;
+    atf_init_arg->atf_aee_debug_buf_size = 0;
+#endif
+    DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, atf_init_arg->atf_log_buf_start);
+    DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, atf_init_arg->atf_log_buf_size);
+    DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_start);
+    DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry = (void *)addr;
+
+    /* EMI MPU support */
+    tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+    DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+    DBG_MSG("%s Jump to ATF, then jump 0x%x\n", MOD, arg1);
+#endif
+
+    atf_entry = (jump_atf)BL31;
+    REL_MSG("[teeloader] tl jump to atf!\n");
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..e60d671
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+    tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c
new file mode 100644
index 0000000..e5da33a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+
+#define MOD "[TZ_TBASE]"
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+    u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+    int ret = 0;
+    sec_mem_arg_t sec_mem_arg;
+    u8 hwuid[16];
+    unsigned char i, *ptmp, tmpbuf;
+
+    ret = tee_get_hwuid(hwuid, 16);
+    if (ret)
+        DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+    /* Prepare secure memory configuration parameters */
+    sec_mem_arg.magic = SEC_MEM_MAGIC;
+    sec_mem_arg.version = SEC_MEM_VERSION;
+    sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+    sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+    sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+    sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+    /* set msg auth key by seclib support */
+    seclib_get_msg_auth_key((unsigned char *) sec_mem_arg.msg_auth_key, 32);
+
+    sec_mem_arg.rpmb_size = 128*1024; /* 128kx1: minimum size */
+    sec_mem_arg.emmc_rel_wr_sec_c = 1;
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    sec_mem_arg.secmem_obfuscation = 1;
+#else
+    sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+    DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+    DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+    DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+    DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+    DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+    DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+    DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+    DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+    DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+    DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+    DBG_MSG("%s emmc_rel_wr_sec_c: 0x%x\n", MOD, sec_mem_arg.emmc_rel_wr_sec_c);
+
+    memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+    u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+    /* Prepare TEE boot parameters */
+    teearg->magic                 = TBASE_BOOTCFG_MAGIC;             /* Trustonic's TEE magic number */
+    teearg->length                = sizeof(tee_arg_t);               /* Trustonic's TEE argument block size */
+    //teearg->version               = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+    teearg->dRamBase              = dram_base;                       /* DRAM base address */
+    teearg->dRamSize              = dram_size;                       /* Full DRAM size */
+    teearg->secDRamBase           = tee_entry;                       /* Secure DRAM base address */
+    teearg->secDRamSize           = tbase_sec_dram_size;             /* Secure DRAM size */
+    teearg->secIRamBase           = TEE_SECURE_ISRAM_ADDR;           /* Secure SRAM base address */
+    teearg->secIRamSize           = TEE_SECURE_ISRAM_SIZE;           /* Secure SRAM size */
+    //teearg->conf_mair_el3         = read_mair_el3();
+    //teearg->MSMPteCount           = totalPages;
+    //teearg->MSMBase               = (u64)registerFileL2;
+    //teearg->gic_distributor_base  = TBASE_GIC_DIST_BASE;
+    //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+    //teearg->gic_version           = TBASE_GIC_VERSION;
+    teearg->total_number_spi      = 256;                      /* Support total 256 SPIs */
+    teearg->ssiq_number           = 266;                      /* reserve SPI ID 266 for <t-base */
+    //teearg->flags                 = TBASE_MONITOR_FLAGS;
+
+    DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+    DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+    DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+    DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+    DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+    DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+    DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+    DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+    DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+    DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c
new file mode 100644
index 0000000..15aeddf
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c
@@ -0,0 +1,396 @@
+/* Include header files */
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "uart.h"
+#include "platform.h"
+
+#include "tz_tkcore.h"
+
+#define MOD "[TZ_TKCORE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+#if CFG_BOOT_ARGUMENT_BY_ATAG
+extern unsigned int g_uart;
+#elif CFG_BOOT_ARGUMENT && !CFG_BOOT_ARGUMENT_BY_ATAG
+#define bootarg g_dram_buf->bootarg
+#endif
+
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+
+struct sdrpmb_info {
+    int failed; int part_id;
+    u32 sdrpmb_part_start;
+
+    u32 sdrpmb_partaddr;
+    u32 sdrpmb_partsize;
+    u32 sdrpmb_starting_sector;
+    u32 sdrpmb_nr_sectors;
+} sdrpmb_info = { 0, -1, 0U, 0U, 0U, 0U, 0U };
+
+int tz_mmc_clr_write_prot(struct mmc_card *card, u32 addr);
+
+void clr_wp(u32 wp_sector, u32 nr_sects)
+{
+    u32 i;
+    int err = 0;
+    struct mmc_card *card;
+
+    u32 grpsector = SDRPMB_REGION_ALIGNMENT / 512;
+
+    print("Clear WP 0x%x 0x%x\n", wp_sector, nr_sects);
+
+    if (!(card = mmc_get_card(0))) {
+        print("invalid card\n");
+        return;
+    }
+
+    if (!mmc_card_mmc(card)) {
+        print("not mmc card!!!\n");
+        return;
+    }
+
+    if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+        print("invalid mmc spec: 0x%x", card->csd.mmca_vsn);
+        return;
+    }
+
+    for (i = 0; i < nr_sects; i += grpsector) {
+        err = tz_mmc_clr_write_prot(card, wp_sector + i);
+        if (err) {
+            print("clear wp 0x%x failed with %d\n",
+                wp_sector + i, err);
+        }
+    }
+
+    return;
+}
+
+static u64 mblock_reserve_dryrun(mblock_info_t *mblock_info, u64 reserved_size)
+{
+    int i, max_rank, target = -1;
+    u64 start, end, sz, max_addr = 0;
+    u64 reserved_addr = 0, align, limit;
+    mblock_t mblock;
+
+    align = 1ULL << 20;
+    /* address cannot go beyond 64bit */
+    limit = 0x100000000ULL;
+    /* always allocate from the larger rank */
+    max_rank = mblock_info->mblock_num - 1;
+
+    for (i = 0; i < mblock_info->mblock_num; i++) {
+        start = mblock_info->mblock[i].start;
+        sz = mblock_info->mblock[i].size;
+        end = limit < (start + sz)? limit: (start + sz);
+        reserved_addr = (end - reserved_size);
+        reserved_addr &= ~(align - 1);
+        if ((reserved_addr + reserved_size <= start + sz) &&
+                (reserved_addr >= start) &&
+                (mblock_info->mblock[i].rank <= max_rank) &&
+                (start + sz > max_addr) &&
+                (reserved_addr + reserved_size <= limit)) {
+            max_addr = start + sz;
+            target = i;
+        }
+    }
+
+    if (target < 0) {
+        printf("mblock_reserve error\n");
+        return 0;
+    }
+
+    start = mblock_info->mblock[target].start;
+    sz = mblock_info->mblock[target].size;
+    end = limit < (start + sz)? limit: (start + sz);
+    reserved_addr = (end - reserved_size);
+    reserved_addr &= ~(align - 1);
+
+    return reserved_addr;
+}
+
+/* note that memory is not really reserved */
+static int reserve_tmpmem(mblock_info_t *mblock_info, u32 *addr, u32 size)
+{
+    u64 _addr = mblock_reserve_dryrun(mblock_info, size);
+    if (_addr == 0ULL) {
+        return -1;
+    }
+
+    /* we only reserve memory lower than 32-bit address, thus
+       we can safely convert variable to u32 */
+    *addr = (u32) _addr;
+    return 0;
+}
+
+void sdrpmb_init_set_failed(void)
+{
+    sdrpmb_info.failed = 1;
+    sdrpmb_info.sdrpmb_partaddr = SDRPMB_FAILURE_MAGIC;
+    sdrpmb_info.sdrpmb_partsize = 0;
+}
+
+void tkcore_boot_param_prepare_sdrpmb_region(part_t *part)
+{
+    if (sdrpmb_info.failed || part == NULL) {
+        return;
+    }
+
+    sdrpmb_info.part_id = part->part_id;
+
+    u32 sect = part->start_sect + part->nr_sects;
+
+    if (sect < SDRPMB_REGION_SIZE / 512) {
+        printf("%s: unexpected MMC size: %u sectors\n", MOD, sect);
+        goto err;
+    }
+    sect -= SDRPMB_REGION_SIZE / 512;
+    /* sect % N must be smaller than sect */
+    sect -= sect % (SDRPMB_REGION_ALIGNMENT / 512);
+
+    if (sect < part->start_sect) {
+        printf("%s: unexpected sdrpmb partition start: %u size: %u\n", MOD, part->start_sect, part->nr_sects);
+        goto err;
+    }
+
+    sdrpmb_info.sdrpmb_part_start = part->start_sect;
+
+    sdrpmb_info.sdrpmb_starting_sector = sect;
+    sdrpmb_info.sdrpmb_nr_sectors = SDRPMB_REGION_SIZE / 512;
+
+    return;
+
+err:
+    sdrpmb_init_set_failed();
+}
+
+#define TKCORE_MAGIC    0xdeadbeef
+
+void check_for_sdrpmb_flag(u64 start_byte ,blkdev_t *bootdev)
+{
+    int ret;
+    u32 magic;
+
+    if (sdrpmb_info.failed)
+        return;
+
+    /* check if sdrpmb region is not reserved */
+    if (sdrpmb_info.part_id < 0)
+        return;
+
+    if ((ret = blkdev_read(bootdev, start_byte, 4, (u8 *) &magic, sdrpmb_info.part_id))) {
+        print("%s: read magic failed with %d", MOD, ret);
+        return;
+    }
+
+    if (magic == TKCORE_MAGIC)
+        return;
+
+    magic = TKCORE_MAGIC;
+
+    if ((ret = blkdev_write(bootdev, start_byte, 4, (u8 *) &magic, sdrpmb_info.part_id))) {
+        print("%s: write magic failed with %d", MOD, ret);
+    }
+
+    clr_wp(sdrpmb_info.sdrpmb_starting_sector, sdrpmb_info.sdrpmb_nr_sectors);
+}
+
+void tkcore_boot_param_prepare_sdrpmb_data(mblock_info_t *mblock, blkdev_t *bootdev)
+{
+    int ret = 0;
+    u64 start_byte;
+
+    if (sdrpmb_info.failed)
+        return;
+
+    /* check if sdrpmb region is not reserved */
+    if (sdrpmb_info.part_id < 0)
+        return;
+
+    if (mblock == NULL || bootdev == NULL) {
+        ret = -1;
+        goto out;
+    }
+
+    sdrpmb_info.sdrpmb_partsize = SDRPMB_DATA_SIZE << 1;
+    ret = reserve_tmpmem(mblock, &(sdrpmb_info.sdrpmb_partaddr), SDRPMB_DATA_SIZE << 1);
+    if (ret) {
+        printf("%s: reserve memory failed\n", MOD);
+        goto out;
+    }
+
+    check_for_sdrpmb_flag(((u64) sdrpmb_info.sdrpmb_part_start) * 512,
+        bootdev);
+
+    /* TODO use sector size instead of the hard coded 512 */
+    start_byte = ((u64) sdrpmb_info.sdrpmb_starting_sector) * 512;
+
+    if ((ret = blkdev_read(bootdev, start_byte, SDRPMB_DATA_SIZE,
+        (u8 *) (sdrpmb_info.sdrpmb_partaddr), sdrpmb_info.part_id))) {
+        printf("%s: read SDRPMB.0 failed", MOD);
+        goto out;
+    }
+
+    if ((ret = blkdev_read(bootdev, start_byte + SDRPMB_REGION_ALIGNMENT,
+        SDRPMB_DATA_SIZE, (u8 *) (sdrpmb_info.sdrpmb_partaddr + SDRPMB_DATA_SIZE),
+        sdrpmb_info.part_id))) {
+        printf("%s: read SDRPMB.1 failed", MOD);
+        goto out;
+    }
+
+out:
+    if (ret)
+        sdrpmb_init_set_failed();
+    return;
+}
+
+static void get_wp_status(u32 wp_addr)
+{
+    int err;
+    struct mmc_card *card;
+    u32 wp_status;
+
+    if (!(card = mmc_get_card(0))) {
+        print("invalid card\n");
+        return;
+    }
+
+    if (!mmc_card_mmc(card)) {
+        print("not mmc card!!!\n");
+        return;
+    }
+
+    if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+        print("invalid mmc spec: 0x%x", card->csd.mmca_vsn);
+        return;
+    }
+
+    err = mmc_send_write_prot(card, wp_addr, &wp_status);
+    if (err) {
+        print("bad send_write prot failed with %d\n", err);
+        return;
+    }
+
+    print("addr: 0x%x wp_status: 0x%x\n", wp_addr, wp_status);
+}
+
+void tkcore_boot_sdrpmb_init_finish(u32 param_addr)
+{
+    int ret = 0;
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+    if (teearg == NULL)
+        return;
+
+    if (sdrpmb_info.failed || sdrpmb_info.part_id < 0)
+        return;
+
+    get_wp_status(sdrpmb_info.sdrpmb_starting_sector);
+
+    teearg->sdrpmb_partaddr = sdrpmb_info.sdrpmb_partaddr;
+    teearg->sdrpmb_partsize = sdrpmb_info.sdrpmb_partsize;
+    teearg->sdrpmb_starting_sector = sdrpmb_info.sdrpmb_starting_sector - sdrpmb_info.sdrpmb_part_start;
+    teearg->sdrpmb_nr_sectors = sdrpmb_info.sdrpmb_nr_sectors;
+
+    return;
+}
+#endif
+
+void tkcore_boot_param_prepare(u64 param_addr, u64 tee_entry,
+    u64 sec_dram_size, u64 dram_base, u64 dram_size, u32 uart_base)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+    if (teearg == NULL) {
+        return;
+    }
+
+    /* Prepare TEE boot parameters */
+    teearg->magic = TKCORE_BOOTCFG_MAGIC;
+    teearg->length = sizeof(tee_arg_t);
+    teearg->version = (u64) TEE_ARGUMENT_VERSION;
+    teearg->dRamBase = dram_base;
+    teearg->dRamSize = dram_size;
+    teearg->secDRamBase = tee_entry;
+    teearg->secDRamSize = sec_dram_size;
+    teearg->secIRamBase = TEE_SECURE_ISRAM_ADDR;
+    teearg->secIRamSize = TEE_SECURE_ISRAM_SIZE;
+
+    /* GIC parameters */
+    teearg->total_number_spi = 352;
+    /* SSI Reserve */
+    teearg->ssiq_number = 32 + 296;
+
+    teearg->flags = 0;
+
+    teearg->uart_base = uart_base;
+}
+
+void tkcore_dump_param(u32 param_addr)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+#if 0
+    DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+    DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+    DBG_MSG("%s teearg.version: 0x%x\n", MOD, teearg->version);
+    DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+    DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+    DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+    DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+    DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+    DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+    DBG_MSG("%s teearg.gic_dist_base: 0x%x\n", MOD, teearg->gic_distributor_base);
+    DBG_MSG("%s teearg.gic_cpu_base: 0x%x\n", MOD, teearg->gic_cpuinterface_base);
+    DBG_MSG("%s teearg.gic_version: 0x%x\n", MOD, teearg->gic_version);
+    DBG_MSG("%s teearg.uart_base: 0x%x\n", MOD, teearg->uart_base);
+    DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+    DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+    DBG_MSG("%s teearg.flags: %x\n", MOD, teearg->flags);
+#endif
+    if (teearg->version >= TEE_ARGUMENT_VERSION_V1_0) {
+      //  DBG_MSG("%s teearg.rpmb_key_programmed : %d\n",
+        //    MOD, teearg->rpmb_key_programmed);
+    }
+
+    if (teearg->version >= TEE_ARGUMENT_VERSION_V1_1) {
+      //  DBG_MSG("%s teearg.nw_bootargs: 0x%x\n", MOD, teearg->nw_bootargs);
+      //  DBG_MSG("%s teearg.nw_bootargs_size: 0x%x\n", MOD, teearg->nw_bootargs_size);
+    }
+
+    if (teearg->version >= TEE_ARGUMENT_VERSION_V1_2) {
+        DBG_MSG("%s teearg.sdrpmb_partaddr: 0x%x\n", MOD, teearg->sdrpmb_partaddr);
+        DBG_MSG("%s teearg.sdrpmb_partsize: 0x%x\n", MOD, teearg->sdrpmb_partsize);
+        DBG_MSG("%s teearg.sdrpmb_starting_sector: 0x%x\n", MOD, teearg->sdrpmb_starting_sector);
+        DBG_MSG("%s teearg.sdrpmb_nr_sectors: 0x%x\n", MOD, teearg->sdrpmb_nr_sectors);
+    }
+}
+
+void tkcore_boot_param_prepare_nwbootargs(u32 param_addr, u32 addr, u32 size)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+    if (teearg == NULL)
+        return;
+    //fix unalign problem with memory copy.
+    memcpy(&teearg->nw_bootargs, &addr, sizeof(addr));
+    memcpy(&teearg->nw_bootargs_size, &size, sizeof(size));
+}
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+void tkcore_boot_param_prepare_rpmbkey(u32 param_addr)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+    if (teearg == NULL) {
+        return ;
+    }
+
+    seclib_get_msg_auth_key(teearg->rpmb_key, RPMB_KEY_SIZE);
+	print("I'm OK!\n");
+    teearg->rpmb_key_programmed = 1;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/start.s b/src/bsp/trustzone/teeloader/mt2712/src/start.s
new file mode 100644
index 0000000..47d2284
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/string.c b/src/bsp/trustzone/teeloader/mt2712/src/string.c
new file mode 100644
index 0000000..d916f3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+    const char *sc;
+
+    for (sc = s; *sc != '\0'; ++sc)
+    {
+    }
+    return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+    signed char __res;
+
+    while (1)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+    signed char __res = 0;
+
+    while (count)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+        count--;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+    char *xs = s;
+
+    while (count--)
+        *xs++ = c;
+    return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+    char *tmp = dest;
+    const char *s = src;
+
+    while (count--)
+        *tmp++ = *s++;
+    return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+    const unsigned char *su1, *su2;
+    int res = 0;
+
+    for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+        if ((res = *su1 - *su2) != 0)
+            break;
+    return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+	char *_dst = dst;
+	const char *_src = src;
+
+	if (dst == src)
+		return dst;
+
+	if (dst < src)
+		return memcpy(dst, src, count);
+
+	_dst += count;
+	_src += count;
+	while(count--)
+		*--_dst = *--_src;
+
+	return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/uart.c b/src/bsp/trustzone/teeloader/mt2712/src/uart.c
new file mode 100644
index 0000000..e93d4dc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/tllink.lds b/src/bsp/trustzone/teeloader/mt2712/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt2731/Makefile b/src/bsp/trustzone/teeloader/mt2731/Makefile
new file mode 100644
index 0000000..7ae84be
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/Makefile
@@ -0,0 +1,71 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/device_apc.c \
+	$(DIR_SRC)/security/tz_init.c \
+	$(DIR_SRC)/security/tz_emi_mpu.c \
+	$(DIR_SRC)/security/tz_sec_cfg.c \
+	$(DIR_SRC)/security/seclib.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+	$(DIR_SRC)/security/tz_tbase.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin -fno-stack-protector ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak
new file mode 100644
index 0000000..3818332
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak
@@ -0,0 +1,7 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak
new file mode 100644
index 0000000..36e0ddd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x900000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak
new file mode 100644
index 0000000..a7a488a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0xA00000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2731/default.mak b/src/bsp/trustzone/teeloader/mt2731/default.mak
new file mode 100644
index 0000000..1b0035b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/default.mak
@@ -0,0 +1,14 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT2731
+CFG_ATF_LOG_SUPPORT := 0
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+CFG_TZ_SRAMROM_SUPPORT := 1
+CFG_TZ_UART_APDMA_SUPPORT := 1
+CFG_DEVAPC_SET_PROTECT := 1
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x4FFC0000
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2731/feature.mak b/src/bsp/trustzone/teeloader/mt2731/feature.mak
new file mode 100644
index 0000000..3ba5fe6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/feature.mak
@@ -0,0 +1,58 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
+
+ifdef CFG_TZ_SRAMROM_SUPPORT
+C_OPTION += -DCFG_TZ_SRAMROM_SUPPORT=${CFG_TZ_SRAMROM_SUPPORT}
+export CFG_TZ_SRAMROM_SUPPORT
+endif
+
+ifdef CFG_DEVAPC_SET_PROTECT
+C_OPTION += -DCFG_DEVAPC_SET_PROTECT=${CFG_DEVAPC_SET_PROTECT}
+export CFG_DEVAPC_SET_PROTECT
+endif
+
+ifdef CFG_TZ_UART_APDMA_SUPPORT
+C_OPTION += -DCFG_TZ_UART_APDMA_SUPPORT=${CFG_TZ_UART_APDMA_SUPPORT}
+export CFG_TZ_UART_APDMA_SUPPORT
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h
new file mode 100644
index 0000000..263d492
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h
@@ -0,0 +1,409 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+/* #define DEVAPC_UT */
+
+/******************************************************************************
+ * SIP CMD DEFINITION
+ ******************************************************************************/
+#define SIP_APC_MODULE_SET	0x1
+#define SIP_APC_MM2ND_SET	0x2
+#define SIP_APC_MASTER_SET	0x3
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void tz_apc_common_init(void);
+void tz_apc_common_postinit(void);
+void devapc_init(void);
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr);
+unsigned int devapc_perm_get(int, int, int);
+uint64_t sip_tee_apc_request(uint32_t cmd, uint32_t x1, uint32_t x2, uint32_t x3);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum E_TRANSACTION {
+	NON_SECURE_TRANSACTION = 0,
+	SECURE_TRANSACTION,
+	E_TRANSACTION_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum APC_ATTR {
+	E_NO_PROTECTION = 0,
+	E_SEC_RW_ONLY,
+	E_SEC_RW_NS_R,
+	E_FORBIDDEN,
+	E_APC_ATTR_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum E_MASK_DOM {
+	E_DOMAIN_0 = 0,
+	E_DOMAIN_1,
+	E_DOMAIN_2,
+	E_DOMAIN_3,
+	E_DOMAIN_4,
+	E_DOMAIN_5,
+	E_DOMAIN_6,
+	E_DOMAIN_7,
+	E_DOMAIN_8,
+	E_DOMAIN_9,
+	E_DOMAIN_10,
+	E_DOMAIN_11,
+	E_DOMAIN_12,
+	E_DOMAIN_13,
+	E_DOMAIN_14,
+	E_DOMAIN_15,
+	E_MASK_DOM_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_MASTER_TYPE {
+	E_DAPC_MASTER = 0,
+	E_DAPC_INFRACFG_AO_MASTER,
+	E_DAPC_MASTER_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_SLAVE_TYPE {
+	E_DAPC_INFRA_SLAVE = 0,
+	E_DAPC_SRAMROM_SLAVE,
+	E_DAPC_MD_SLAVE,
+	E_DAPC_OTHERS_SLAVE,
+	E_DAPC_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_PD_SLAVE_TYPE {
+	E_DAPC_PD_INFRA_MM_MD_SLAVE = 0,
+	E_DAPC_PD_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+struct INFRA_PERI_DEVICE_INFO {
+	unsigned char       d0_permission;
+	unsigned char       d1_permission;
+	unsigned char       d9_permission;
+	unsigned char       d11_permission;
+};
+
+#define DAPC_INFRA_ATTR(DEV_NAME, PERM_ATTR1, PERM_ATTR2, PERM_ATTR3, PERM_ATTR4) \
+{(unsigned char)PERM_ATTR1, (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, (unsigned char)PERM_ATTR4}
+
+struct MD_DEVICE_INFO {
+	unsigned char       d0_permission;
+};
+
+#define DAPC_MD_ATTR(DEV_NAME, PERM_ATTR1) {(unsigned char)PERM_ATTR1}
+
+enum DEVAPC_ERR_STATUS {
+	DEVAPC_OK = 0x0,
+
+	DEVAPC_ERR_GENERIC = 0x1000,
+	DEVAPC_ERR_INVALID_CMD = 0x1001,
+	DEVAPC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+	DEVAPC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+	DEVAPC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+	DEVAPC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+	DEVAPC_ERR_OUT_OF_BOUNDARY = 0x1006,
+};
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+
+#define devapc_writel(VAL, REG)		__raw_writel(VAL, REG)
+#define devapc_readl(REG)		__raw_readl(REG)
+
+static void tz_set_field(volatile u32 *reg, u32 field, u32 val)
+{
+	u32 tv = (u32)*reg;
+	tv &= ~(field);
+	tv |= val;
+	*reg = tv;
+}
+
+#define reg_set_field(r, f, v)	tz_set_field((volatile u32 *)r, f, v)
+
+/******************************************************************************
+ *
+ * REGISTER ADDRESS DEFINITION
+ *
+ ******************************************************************************/
+#define DEVAPC_AO_INFRA_BASE        0x1001C000
+#define DEVAPC_PD_INFRA_BASE        0x10207000
+
+#define SRAMROM_BASE                0x10214000
+#define INFRACFG_AO_BASE            0x10001000
+#define SECURITY_AO_BASE            0x1001A000
+
+/* #define BLOCKED_REG_BASE            0x10400000 */
+
+/*******************************************************************************************/
+/* Device APC AO */
+#define DEVAPC_SYS0_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0000))
+#define DEVAPC_SYS1_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x1000))
+#define DEVAPC_SYS2_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x2000))
+
+#define DEVAPC_INFRA_MAS_DOM_0         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0900))
+#define DEVAPC_INFRA_MAS_DOM_1         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0904))
+#define DEVAPC_INFRA_MAS_DOM_2         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0908))
+#define DEVAPC_INFRA_MAS_DOM_3         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x090C))
+#define DEVAPC_INFRA_MAS_DOM_4         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0910))
+
+#define DEVAPC_INFRA_MAS_SEC_0         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0A00))
+
+#define DEVAPC_INFRA_APC_CON           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0F00))
+
+#define DEVAPC_SRAMROM_DOM_REMAP_0_0   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0800))
+#define DEVAPC_SRAMROM_DOM_REMAP_0_1   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0804))
+#define DEVAPC_SRAMROM_DOM_REMAP_1_0   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0810))
+
+/* MD is combined into DEVAPC_AO SYS2 */
+
+/*******************************************************************************************/
+/* Device APC PD */
+#define DEVAPC_PD_INFRA_VIO_MASK(index) \
+	((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_STA(index) \
+	((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x400 + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_DBG0       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0900))
+#define DEVAPC_PD_INFRA_VIO_DBG1       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0904))
+#define DEVAPC_PD_INFRA_VIO_DBG2       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0908))
+
+#define DEVAPC_PD_INFRA_APC_CON        ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F00))
+
+#define DEVAPC_PD_INFRA_VIO_SHIFT_STA  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F10))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_SEL  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F14))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_CON  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F20))
+
+/*******************************************************************************************/
+
+#define INFRA_AO_SEC_CON		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F80))
+
+/* INFRACFG AO */
+#define INFRA_AO_SEC_CG_CON0		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F84))
+#define INFRA_AO_SEC_CG_CON1		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F88))
+#define INFRA_AO_SEC_CG_CON2		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F9C))
+#define INFRA_AO_SEC_CG_CON3		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0FA4))
+
+#define INFRACFG_AO_DEVAPC_CON		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0710))
+#define INFRACFG_AO_DEVAPC_MAS_DOM	((volatile unsigned int *)(INFRACFG_AO_BASE+0x0714))
+#define INFRACFG_AO_DEVAPC_MAS_SEC	((volatile unsigned int *)(INFRACFG_AO_BASE+0x0718))
+
+/* PMS(MD devapc) */
+/* #define AP2MD1_PMS_CTRL_EN             ((unsigned int *)0x100018AC) */
+/* #define AP2MD1_PMS_CTRL_EN_LOCK        ((unsigned int *)0x100018A8) */
+
+/*******************************************************************************************/
+
+#define SRAMROM_SEC_VIO_STA            ((volatile unsigned int *)(SRAMROM_BASE+0x010))
+#define SRAMROM_SEC_VIO_ADDR           ((volatile unsigned int *)(SRAMROM_BASE+0x014))
+#define SRAMROM_SEC_VIO_CLR            ((volatile unsigned int *)(SRAMROM_BASE+0x018))
+
+#define SRAMROM_ROM_SEC_VIO_STA        ((volatile unsigned int *)(SRAMROM_BASE+0x110))
+#define SRAMROM_ROM_SEC_VIO_ADDR       ((volatile unsigned int *)(SRAMROM_BASE+0x114))
+#define SRAMROM_ROM_SEC_VIO_CLR        ((volatile unsigned int *)(SRAMROM_BASE+0x118))
+
+
+#define SRAMROM_SEC_CTRL               ((volatile unsigned int *)(SECURITY_AO_BASE+0x010))
+#define SRAMROM_SEC_CTRL2              ((volatile unsigned int *)(SECURITY_AO_BASE+0x018))
+#define SRAMROM_SEC_CTRL5              ((volatile unsigned int *)(SECURITY_AO_BASE+0x024))
+#define SRAMROM_SEC_CTRL6              ((volatile unsigned int *)(SECURITY_AO_BASE+0x028))
+#define SRAMROM_SEC_ADDR               ((volatile unsigned int *)(SECURITY_AO_BASE+0x050))
+#define SRAMROM_SEC_ADDR1              ((volatile unsigned int *)(SECURITY_AO_BASE+0x054))
+#define SRAMROM_SEC_ADDR2              ((volatile unsigned int *)(SECURITY_AO_BASE+0x058))
+
+#define SRAMROM_SEC_ADDR_SEC0_SEC_EN       (28)
+#define SRAMROM_SEC_ADDR_SEC1_SEC_EN       (29)
+#define SRAMROM_SEC_ADDR_SEC2_SEC_EN       (30)
+#define SRAMROM_SEC_ADDR_SEC3_SEC_EN       (31)
+
+/* SEC means region (0~3) */
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT   (0)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT   (3)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT   (6)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT   (9)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT   (16)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT   (19)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT   (22)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT   (25)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT  (0)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT  (3)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT  (6)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT  (9)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT  (16)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT  (19)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT  (22)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT  (25)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT  (0)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT  (3)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT  (6)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT  (9)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT  (16)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT  (19)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT  (22)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT  (25)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT  (0)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT  (3)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT  (6)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT  (9)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT  (16)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT  (19)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT  (22)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT  (25)
+
+
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT)
+
+#define PERMIT_S_RW_NS_RW       (0x0)
+#define PERMIT_S_RW_NS_BLOCK    (0x1)
+#define PERMIT_S_RW_NS_RO       (0x2)
+#define PERMIT_S_RW_NS_WO       (0x3)
+#define PERMIT_S_RO_NS_RO       (0x4)
+#define PERMIT_S_BLOCK_NS_BLOCK (0x7)
+
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0) */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size)	(devapc_writel(((size & 0xff) << 10), SRAMROM_SEC_ADDR))
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+/* If you config register INFRA_AO_SEC_CON(address 0x10000F80) bit[4] = 1,
+ * the domain comes from device_apc. By default this register is 0,
+ * the domain comes form MD1
+ */
+#define FORCE_MD1_SIGNAL_FROM_DAPC      ((0x1) << 4)
+
+/* PROTECT BIT FOR INFRACFG AO */
+#define SEJ_CG_PROTECT_BIT              ((0x1) << 5)
+#define TRNG_CG_PROTECT_BIT             ((0x1) << 9)
+#define DEVAPC_CG_PROTECT_BIT           ((0x1) << 20)
+
+#define SRAM_SEC_VIO_BIT                (0x1)
+#define ROM_SEC_VIO_BIT                 (0x1)
+
+/*******************************************************************************************/
+/* Master domain/secure bit definition */
+#define MASTER_SPM_DOM_INDEX		(18)
+#define MASTER_SPM_SEC_INDEX		(19)
+#define MASTER_INFRA_MAX_INDEX		(19)
+
+/* Below master should be set in INFRACFG_AO */
+#define MASTER_INFRACFG_AO_MAX_INDEX	5
+#define MASTER_APMCU_INDEX		0
+#define MASTER_MD_INDEX			1
+#define MASTER_HSM_INDEX		2
+#define MASTER_USB_INDEX		3
+#define MASTER_SSUSB_INDEX		4
+#define MASTER_MSDC0_INDEX		5
+
+/*******************************************************************************************/
+/* Master domain remap */
+#define MASTER_DOM_RMP_INIT		(0xFFFFFFFF)
+#define SRAMROM_RMP_AP			(0x7 << 0)	// Infra domain 0
+
+#define MD_RMP_AP			(0x3 << 0)	// Infra domain 0
+
+/*******************************************************************************************/
+#define MOD_NO_IN_1_DEVAPC              16
+#define MAS_DOM_NO_IN_1_DEVAPC		4
+
+/* infra/sramrom/MD support maximum domain num */
+#define DEVAPC_INFRA_DOM_MAX		16
+#define DEVAPC_SRAMROM_DOM_MAX		8
+#define DEVAPC_MD_DOM_MAX		4
+
+/* infra/sramrom/MD APC number per domain */
+#define DEVAPC_INFRA_APC_NUM		10
+#define DEVAPC_SRAMROM_APC_NUM		1
+#define DEVAPC_MD_APC_NUM		3
+
+/* infra/sramrom/MD support maximum ctrl index */
+#define SLAVE_INFRA_MAX_INDEX		146
+#define SLAVE_SRAMROM_MAX_INDEX		0
+#define SLAVE_MD_MAX_INDEX		35
+
+#define VIO_MASK_STA_NUM		13
+#define SRAMROM_VIO_INDEX		355
+#define DEVAPC_CTRL_SRAMROM_INDEX	0
+/* devapc can only handle vio index 0 ~ sramrom */
+#define VIOLATION_MAX_INDEX		SRAMROM_VIO_INDEX
+#define VIOLATION_TRIGGERED		1
+
+#endif /* DEVICE_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h
new file mode 100644
index 0000000..fc3e2d6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+				unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/platform.h b/src/bsp/trustzone/teeloader/mt2731/include/platform.h
new file mode 100644
index 0000000..4f9c524
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR	(0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE	(0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE               (0x500000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE               (0x500000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE           (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0xE00000UL) /* TEE max DRAM size is 14MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE           (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/print.h b/src/bsp/trustzone/teeloader/mt2731/include/print.h
new file mode 100644
index 0000000..176ca38
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/seclib.h b/src/bsp/trustzone/teeloader/mt2731/include/seclib.h
new file mode 100644
index 0000000..fab3935
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/seclib.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX          (0xFFFFFFFFUL)    /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/string.h b/src/bsp/trustzone/teeloader/mt2731/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h
new file mode 100644
index 0000000..5305aef
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h
@@ -0,0 +1,184 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+typedef unsigned long uintptr_t;
+typedef u64 uint64_t;
+typedef u32 uint32_t;
+typedef u32 size_t;
+typedef u8 uint8_t;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE   (0U)
+#endif
+#ifndef TRUE
+#define TRUE    (1U)
+#endif
+
+#ifndef NULL
+#define NULL    (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define printf	print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET      (0x40000000UL)
+#define EMI_MPU_ALIGNMENT   (0x10000UL)
+#define PERIAXI_BUS_CTL3    (0x10003208UL)
+#define PERISYS_4G_SUPPORT  (0x1 << 11)
+
+
+typedef enum
+{
+    TZ_MPU_SEC_RW_NSEC_RW = 0,      /* read and write for both secure and non-secure access */
+    TZ_MPU_SEC_RW_NSEC_DENY = 1,    /* read and write for secure access */
+    TZ_MPU_SEC_RW_NSEC_RO = 2,      /* read and write for secure access and read only for non-secure access */
+    TZ_MPU_SEC_RW_NSEC_WO = 3,      /* read and write for secure access and write only for non-secure access */
+    TZ_MPU_SEC_RO_NSEC_RO = 4,      /* read only for both secure access and non-secure access */
+    TZ_MPU_SEC_DENY_NSEC_DENY = 5,  /* Any access is prohibited */
+    TZ_MPU_SEC_RO_NSEC_RW = 6       /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID    (0)
+#define ATF_MPU_REGION_ID          (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE                (0x1020E000U)
+
+#define EMI_MPU_SA0                 ((P_U32)(EMI_MPU_BASE+0x100))  /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1                 ((P_U32)(EMI_MPU_BASE+0x104))  /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2                 ((P_U32)(EMI_MPU_BASE+0x108))  /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3                 ((P_U32)(EMI_MPU_BASE+0x10C))  /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4                 ((P_U32)(EMI_MPU_BASE+0x110))  /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5                 ((P_U32)(EMI_MPU_BASE+0x114))  /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6                 ((P_U32)(EMI_MPU_BASE+0x118))  /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7                 ((P_U32)(EMI_MPU_BASE+0x11C))  /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0                 ((P_U32)(EMI_MPU_BASE+0x200))  /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1                 ((P_U32)(EMI_MPU_BASE+0x204))  /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2                 ((P_U32)(EMI_MPU_BASE+0x208))  /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3                 ((P_U32)(EMI_MPU_BASE+0x20C))  /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4                 ((P_U32)(EMI_MPU_BASE+0x210))  /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5                 ((P_U32)(EMI_MPU_BASE+0x214))  /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6                 ((P_U32)(EMI_MPU_BASE+0x218))  /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7                 ((P_U32)(EMI_MPU_BASE+0x21C))  /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0                ((P_U32)(EMI_MPU_BASE+0x300))  /* EMI MPU APC 0 */
+#define EMI_MPU_APC1                ((P_U32)(EMI_MPU_BASE+0x304))  /* EMI MPU APC 1 */
+#define EMI_MPU_APC2                ((P_U32)(EMI_MPU_BASE+0x308))  /* EMI MPU APC 2 */
+#define EMI_MPU_APC3                ((P_U32)(EMI_MPU_BASE+0x30C))  /* EMI MPU APC 3 */
+#define EMI_MPU_APC4                ((P_U32)(EMI_MPU_BASE+0x310))  /* EMI MPU APC 4 */
+#define EMI_MPU_APC5                ((P_U32)(EMI_MPU_BASE+0x314))  /* EMI MPU APC 5 */
+#define EMI_MPU_APC6                ((P_U32)(EMI_MPU_BASE+0x318))  /* EMI MPU APC 6 */
+#define EMI_MPU_APC7                ((P_U32)(EMI_MPU_BASE+0x31C))  /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0             ((P_U32)(EMI_MPU_BASE+0x900))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1             ((P_U32)(EMI_MPU_BASE+0x904))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2             ((P_U32)(EMI_MPU_BASE+0x908))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3             ((P_U32)(EMI_MPU_BASE+0x90C))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4             ((P_U32)(EMI_MPU_BASE+0x910))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5             ((P_U32)(EMI_MPU_BASE+0x914))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6             ((P_U32)(EMI_MPU_BASE+0x918))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7             ((P_U32)(EMI_MPU_BASE+0x91C))  /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h
new file mode 100644
index 0000000..63d22bd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+//Don't used the typedef of teeloader, as this file will be included in Trustonic tee.
+//Which MUST use specific gcc version compiler, and the compiler have some conflict define
+//with the typedef here.
+//#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+#define HRID_SIZE 2
+/* bootarg for ATF */
+typedef struct {
+    unsigned long long bootarg_loc;
+    unsigned long long bootarg_size;
+    unsigned long long bl33_start_addr;
+    unsigned long long tee_info_addr;
+    unsigned long long boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+    unsigned int atf_magic;
+    unsigned int tee_support;
+    unsigned int tee_boot_arg_addr;
+    unsigned int tee_entry;
+    unsigned int hwuid[4];     // HW Unique id for t-base used
+    unsigned int HRID[HRID_SIZE];      // HW random id for t-base used
+    unsigned int atf_log_port;
+    unsigned int atf_log_baudrate;
+    unsigned int atf_log_buf_start;
+    unsigned int atf_log_buf_size;
+    unsigned int atf_aee_debug_buf_start;
+    unsigned int atf_aee_debug_buf_size;
+    unsigned int devinfo[DEVINFO_SIZE];
+    unsigned int atf_irq_num;
+    unsigned int msg_auth_key[8]; /* size of message auth key is 256 bits */
+#if CFG_TEE_SUPPORT
+    unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h
new file mode 100644
index 0000000..6d157c6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h
@@ -0,0 +1,103 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS   (0x00100000UL)
+#define SRAM_START_ADDR     (0x00102140UL)
+#define VECTOR_START        (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+    short next, previous;
+} tz_memory_t;
+
+#define FREE            ((short)(0x0001U))
+#define IS_FREE(x)      ((x)->next & FREE)
+#define CLEAR_FREE(x)   ((x)->next &= ~FREE)
+#define SET_FREE(x)     ((x)->next |= FREE)
+#define FROM_ADDR(x)    ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x)      ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC                   (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION                 (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE        (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE       (0x80000UL) //0.5MB by default
+
+#define BL31                            (0x43001000UL)
+#define BL31_SIZE                       (0x40000UL) //change to 256KB (192KB by default)
+#define BL33                            (0x42110000UL)
+
+
+#define ATF_BOOT_ARG_ADDR				(0x40000000UL)
+#define ATF_INIT_ARG_ADDR				(0x40000100UL)
+#define TEE_BOOT_ARG_ADDR				(0x43000100UL)
+
+#define TEE_PARAMETER_BASE (TEE_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR           (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE           (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+    unsigned int magic;              // Magic number
+    unsigned int version;            // version
+    unsigned int svp_mem_start;      // MM sec mem pool start addr.
+    unsigned int svp_mem_end;        // MM sec mem pool end addr.
+    unsigned int tplay_table_start;  // tplay handle-to-physical table start
+    unsigned int tplay_table_size;   // tplay handle-to-physical table size
+    unsigned int tplay_mem_start;    // tplay physcial memory start address for crypto operation
+    unsigned int tplay_mem_size;     // tplay phsycial memory size for crypto operation
+    unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+    unsigned int rpmb_size;          /* size of rpmb partition */
+    unsigned int msg_auth_key[8];    /* size of message auth key is 32bytes(256 bits) */
+    unsigned int emmc_rel_wr_sec_c;  // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+    u32 magic;        // magic value from information
+    u32 length;       // size of struct in bytes.
+    u64 version;      // Version of structure
+    u64 dRamBase;     // NonSecure DRAM start address
+    u64 dRamSize;     // NonSecure DRAM size
+    u64 secDRamBase;  // Secure DRAM start address
+    u64 secDRamSize;  // Secure DRAM size
+    u64 secIRamBase;  // Secure IRAM base
+    u64 secIRamSize;  // Secure IRam size
+    u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+    u32 RFU1;
+    u32 MSMPteCount;  // Number of MMU entries for MSM
+    u64 MSMBase;      // MMU entries for MSM
+    u64 gic_distributor_base;
+    u64 gic_cpuinterface_base;
+    u32 gic_version;
+    u32 RFU2;
+    u64 flags;
+    u32 total_number_spi;
+    u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/uart.h b/src/bsp/trustzone/teeloader/mt2731/include/uart.h
new file mode 100644
index 0000000..9a6ba92
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/uart.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include "typedefs.h"
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE      (1U << 5U)
+#define UART_THR(uart)     (UART_BASE(uart) + 0x0U)  /* Write only */
+
+#define IO_PHYS            (0x10000000UL)
+#define UART1_BASE         (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a b/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a
new file mode 100644
index 0000000..f524098
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c
new file mode 100644
index 0000000..6e5e942
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c
@@ -0,0 +1,984 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include <stdbool.h>
+#include "device_apc.h"
+#include "print.h"
+
+#define MTAG	"[DEVAPC]"
+#define DAPC_DEBUG
+
+#ifdef DAPC_DEBUG
+#define DBG(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG(str, ...) do {} while(0)
+#endif
+
+#define INFO(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#define ERROR(str, ...) do {print(MTAG "[ERROR]" str, ##__VA_ARGS__);} while(0)
+
+
+static const struct INFRA_PERI_DEVICE_INFO D_APC_INFRA_Devices[] = {
+	/*		module,					AP permission,   MD permission,   SPM permission,
+	 */
+
+	/* 0 */
+	DAPC_INFRA_ATTR("SPM_APB_S",                            E_NO_PROTECTION, E_SEC_RW_ONLY,   E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPM_APB_S-1",                          E_SEC_RW_ONLY,   E_SEC_RW_ONLY,   E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPM_APB_S-2",                          E_SEC_RW_ONLY,   E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOPCKGEN_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRACFG_AO_APB_S",                    E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("IOCFG_APB_S",                          E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PERICFG_AO_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EFUSE_DEBUG_AO_APB_S",                 E_SEC_RW_NS_R,   E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GPIO_APB_S",                           E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOPRGU_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 10 */
+	DAPC_INFRA_ATTR("APXGPT_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_RSV0_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SEJ_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AP_CIRQ_EINT_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("APMIXEDSYS_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PMIC_WRAP_APB_S",                      E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_RSV2_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("KP_APB_S",                             E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOP_MISC_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DVFSRC_APB_S",                         E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 20 */
+	DAPC_INFRA_ATTR("MBIST_AO_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_AO_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_BCRM_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AES_TOP0_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SYS_TIMER_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MODEM_TEMP_SHARE_APB_S",               E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEBUG_CTRL_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SECURITY_AO_APB_S",                    E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("TOPCKGEN_INFRA_CFG_APB_S",             E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEVICE_APC_AO_APB_S",                  E_SEC_RW_ONLY,   E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 30 */
+	DAPC_INFRA_ATTR("PWM_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("HSM_AXI_S",                            E_SEC_RW_ONLY,   E_FORBIDDEN,     E_FORBIDDEN,     E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("PCIE_BR_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PCIE_PCI0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S-1",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S-2",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S",                                E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S-1",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S-2",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 40 */
+	DAPC_INFRA_ATTR("MCUPM_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUPM_APB_S-1",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUPM_APB_S-2",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AUDIO_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC0_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC1_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC2_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB1_S",                          E_NO_PROTECTION, E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB2_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 50 */
+	DAPC_INFRA_ATTR("EAST_APB3_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB0_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("SOUTH_APB1_S",                         E_NO_PROTECTION, E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB2_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB3_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB1_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB2_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB3_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB0_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 60 */
+	DAPC_INFRA_ATTR("NORTH_APB1_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB2_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB3_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUCFG_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SYS_CIRQ_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TRNG_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEVICE_APC_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEBUG_TRACKER_APB_S",                  E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF0_AP_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF0_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 70 */
+	DAPC_INFRA_ATTR("CCIF1_AP_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF1_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MBIST_PDN_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRACFG_PDN_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_NS_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_MMU_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CQ_DMA_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRA_RSV0_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SRAMROM_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+
+	/* 80 */
+	DAPC_INFRA_ATTR("INFRA_BCRM_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EMI_APB_S",                            E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("INFRA_RSV2_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_APB_S",                          E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EMI_MPU_APB_S",                        E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRA_RSV3_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP0_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP1_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP2_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 90 */
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP3_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP4_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP0_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP1_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP2_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP3_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP4_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCE_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF2_AP_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF2_MD_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 100 */
+	DAPC_INFRA_ATTR("CCIF3_AP_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF3_MD_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC2_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC3_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC4_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC5_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC6_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC7_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC8_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 110 */
+	DAPC_INFRA_ATTR("GCPU_ECC9_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC10_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC11_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC12_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC13_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC14_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC15_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC16_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("FAKE_ENG_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TRFG_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 120 */
+	DAPC_INFRA_ATTR("DEBUG_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("APDMA_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AUXADC_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART0_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("UART1_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("UART2_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART3_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C0_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C1_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C2_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 130 */
+	DAPC_INFRA_ATTR("SPI0_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PTP_THERM_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("BTIF_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PERI_RSV0_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DISP_PWM_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C3_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI1_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C4_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI2_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI_SLV_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 140 */
+	DAPC_INFRA_ATTR("UART4_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART5_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART6_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("IMP_IIC_WRAP_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NFI_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NFIECC_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("ETHER_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+};
+
+static const struct MD_DEVICE_INFO D_APC_MD_Devices[] = {
+	/*              module,                     AP permission */
+
+	 /* 0 */
+	DAPC_MD_ATTR("MDPERISYS_1",                 E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDPERISYS_2/MDTOP",           E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDMCUAPB",                    E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDCORESYS",                   E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDINFRA_APB_1",               E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDINFRA_APB_2",               E_NO_PROTECTION),
+	DAPC_MD_ATTR("MML2",                        E_NO_PROTECTION),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+
+	 /* 10 */
+	DAPC_MD_ATTR("MD_INFRA",                    E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("uSIP Peripheral",             E_FORBIDDEN),
+	DAPC_MD_ATTR("modeml1_ao_top_pwr_wrap",     E_NO_PROTECTION),
+	DAPC_MD_ATTR("md2gsys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rxdfesys_pwr_wrap",           E_FORBIDDEN),
+
+	 /* 20 */
+	DAPC_MD_ATTR("cssys_pwr_wrap",              E_FORBIDDEN),
+	DAPC_MD_ATTR("txsys_pwr_wrap",              E_FORBIDDEN),
+	DAPC_MD_ATTR("bigramsys (mem)",             E_FORBIDDEN),
+	DAPC_MD_ATTR("md32scq share (mem)",         E_FORBIDDEN),
+	DAPC_MD_ATTR("md32scq_vu01 (mem)",          E_FORBIDDEN),
+	DAPC_MD_ATTR("peripheral (reg)",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rakesys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rakesys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("brpsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("brpsys_pwr_wrap",             E_FORBIDDEN),
+
+	 /* 30 */
+	DAPC_MD_ATTR("dmcsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("dmcsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+
+};
+
+static uint32_t set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module,
+	enum E_MASK_DOM domain_num, enum APC_ATTR permission)
+{
+	uint32_t *base = NULL;
+	uint32_t apc_index;
+	uint32_t apc_set_index;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if (permission != E_NO_PROTECTION &&
+		permission != E_SEC_RW_ONLY &&
+		permission != E_SEC_RW_NS_R &&
+		permission != E_FORBIDDEN) {
+
+		ERROR("permission=0x%x is not supported!\n",
+			permission);
+		return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+	}
+
+	apc_index = module / MOD_NO_IN_1_DEVAPC;
+	apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+	clr_bit = 0xFFFFFFFF ^ (0x3 << (apc_set_index * 2));
+	set_bit = permission << (apc_set_index * 2);
+
+	/* Do boundary check */
+	if (slave_type == E_DAPC_INFRA_SLAVE &&
+		module <= SLAVE_INFRA_MAX_INDEX &&
+		domain_num <= E_DOMAIN_15)
+		base = (uint32_t *)((size_t)DEVAPC_SYS0_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+
+	else if (slave_type == E_DAPC_SRAMROM_SLAVE &&
+		module <= SLAVE_SRAMROM_MAX_INDEX &&
+		domain_num <= E_DOMAIN_8)
+		base = (uint32_t *)((size_t)DEVAPC_SYS1_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+
+	else if (slave_type == E_DAPC_MD_SLAVE &&
+		module <= SLAVE_MD_MAX_INDEX &&
+		domain_num <= E_DOMAIN_3)
+		base = (uint32_t *)((size_t)DEVAPC_SYS2_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+	else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+			"slave_type", slave_type,
+			"module", module,
+			"domain_num", domain_num);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		devapc_writel((devapc_readl(base) & clr_bit), base);
+		devapc_writel((devapc_readl(base) | set_bit), base);
+
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_transaction(enum DAPC_MASTER_TYPE master_type,
+		uint32_t master_index, enum E_TRANSACTION transaction_type)
+{
+	uint32_t *base = NULL;
+	uint32_t master_set_index;
+
+	master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+	if (master_type == E_DAPC_MASTER &&
+		master_index <= MASTER_INFRA_MAX_INDEX)
+		base = (uint32_t *)DEVAPC_INFRA_MAS_SEC_0;
+
+	else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+		master_index <= MASTER_INFRACFG_AO_MAX_INDEX)
+		base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_SEC;
+
+	else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x\n",
+			"master_type", master_type,
+			"master_index", master_index);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		if (transaction_type == NON_SECURE_TRANSACTION)
+			devapc_writel(devapc_readl(base) &
+				(0xFFFFFFFF ^ (0x1 << master_set_index)), base);
+		else if (transaction_type == SECURE_TRANSACTION)
+			devapc_writel(devapc_readl(base) |
+				(0x1 << master_set_index), base);
+		else {
+			ERROR("transaction=0x%x is not supported!\n",
+					transaction_type);
+			return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+		}
+
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_domain(enum DAPC_MASTER_TYPE master_type,
+		uint32_t master_index, enum E_MASK_DOM dom_num)
+{
+	uint32_t *base = NULL;
+	uint32_t master_reg_index;
+	uint32_t master_set_index;
+	uint32_t set_bit;
+
+	if (master_type == E_DAPC_MASTER &&
+		master_index <= MASTER_INFRA_MAX_INDEX &&
+		dom_num <= E_DOMAIN_15) {
+		master_reg_index = master_index / MAS_DOM_NO_IN_1_DEVAPC;
+		master_set_index = master_index % MAS_DOM_NO_IN_1_DEVAPC;
+		set_bit = dom_num << (master_set_index * 8);
+
+		base = (uint32_t *)((size_t)DEVAPC_INFRA_MAS_DOM_0 + master_reg_index * 4);
+
+	} else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+		master_index <= MASTER_INFRACFG_AO_MAX_INDEX &&
+		dom_num <= E_DOMAIN_15) {
+		set_bit = dom_num << (master_index * 4);
+		base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_DOM;
+
+	} else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+			"master_type", master_type,
+			"master_index", master_index,
+			"dom_num", dom_num);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		devapc_writel(devapc_readl(base) | set_bit, base);
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static void dump_infra_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0; d < DEVAPC_INFRA_DOM_MAX; d++) {
+		if (d != E_DOMAIN_0 && d != E_DOMAIN_1 && d != E_DOMAIN_9 && d != E_DOMAIN_11)
+			continue;
+
+		for (i = 0; i < DEVAPC_INFRA_APC_NUM; i++) {
+			INFO("(INFRA)SYS0_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS0_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS0_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+	}
+
+	INFO("(INFRA)MAS_SEC_0 = 0x%x\n", devapc_readl(DEVAPC_INFRA_MAS_SEC_0));
+}
+
+static void dump_sramrom_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0 ; d < DEVAPC_SRAMROM_DOM_MAX ; d++)
+		for (i = 0; i < DEVAPC_SRAMROM_APC_NUM; i++) {
+			INFO("(MD)SYS1_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS1_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS1_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+}
+
+static void dump_md_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0 ; d < DEVAPC_MD_DOM_MAX ; d++) {
+		if (d != E_DOMAIN_0)
+			continue;
+
+		for (i = 0; i < DEVAPC_MD_APC_NUM; i++) {
+			INFO("(MD)SYS2_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS2_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS2_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+	}
+}
+
+/*
+static void dump_pms_info(void)
+{
+	INFO("[PMS]AP2MD1_PMS_CTRL_EN = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN));
+	INFO("[PMS]AP2MD1_PMS_CTRL_EN_LOCK = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK));
+}
+*/
+
+static void print_vio_mask_sta(void)
+{
+	int i;
+
+	for (i = 0; i < VIO_MASK_STA_NUM; i++) {
+		INFO("%s: (%d:0x%x) %s: (%d:0x%x)\n",
+			"INFRA VIO_MASK", i,
+			devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(i)),
+			"INFRA VIO_STA", i,
+			devapc_readl(DEVAPC_PD_INFRA_VIO_STA(i))
+		);
+	}
+}
+
+static void unmask_infra_module(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	devapc_writel(devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(apc_index)) &
+		(0xFFFFFFFF ^ (1 << apc_bit_index)),
+		DEVAPC_PD_INFRA_VIO_MASK(apc_index));
+}
+
+static uint32_t clear_infra_vio_status(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	devapc_writel(0x1 << apc_bit_index,
+		DEVAPC_PD_INFRA_VIO_STA(apc_index));
+
+	return 0;
+}
+
+static int check_infra_vio_status(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	if (devapc_readl(DEVAPC_PD_INFRA_VIO_STA(apc_index)) &
+			(0x1 << apc_bit_index))
+		return VIOLATION_TRIGGERED;
+
+	return 0;
+}
+
+static bool vio_shift_sta_handler(void)
+{
+	uint32_t vio_shift_sta = 0;
+
+	vio_shift_sta = devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+	INFO("(Pre)VIO_SHIFT_STA = 0x%x\n", vio_shift_sta);
+
+	if (vio_shift_sta) {
+		devapc_writel(vio_shift_sta, DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+		INFO("(Post)clear VIO_SHIFT_STA = 0x%x\n",
+			devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA));
+	}
+
+	return vio_shift_sta ? true : false;
+}
+
+static void devapc_irq_handler(void)
+{
+	int i;
+	uint64_t vio_sta;
+	uint64_t vio_addr;
+
+	INFO("enter %s...\n", __func__);
+	print_vio_mask_sta();
+	if (!vio_shift_sta_handler()) {
+		INFO("violation is not triggered or is clean before\n");
+		return;
+	}
+
+	for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+		if (check_infra_vio_status(i) == VIOLATION_TRIGGERED) {
+			INFO("violation is triggered, vio_idx=%d\n", i);
+			if (i == SRAMROM_VIO_INDEX)
+				handle_sramrom_vio(&vio_sta, &vio_addr);
+
+			clear_infra_vio_status(i);
+		}
+	}
+
+	print_vio_mask_sta();
+}
+
+#ifdef DEVAPC_UT
+static void devapc_ut(void)
+{
+	INFO("test violation...\n");
+
+	INFO("read blocked reg = 0x%x\n",
+		devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+	devapc_writel(0xdead, (unsigned int *)BLOCKED_REG_BASE);
+	INFO("read blocked reg = 0x%x\n",
+		devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+	devapc_irq_handler();
+
+	mt_irq_dump_status(DEVAPC_IRQ_BIT_ID);
+}
+#endif
+
+static void devapc_set_dom(void)
+{
+
+	/* For EMI workaround, need set SPM as secure master to rw EMI self
+	 * test start/end address
+	 */
+	set_master_transaction(E_DAPC_MASTER, MASTER_SPM_SEC_INDEX, SECURE_TRANSACTION);
+
+	INFO("Setup master secure: %s = (0x%x), %s = (0x%x)\n",
+			"DEVAPC_INFRA_MAS_SEC_0",
+			devapc_readl(DEVAPC_INFRA_MAS_SEC_0),
+			"INFRACFG_AO_DEVAPC_MAS_SEC",
+			devapc_readl(INFRACFG_AO_DEVAPC_MAS_SEC)
+	);
+
+/******************************************************************************/
+/* Infra Master Domain Setting */
+
+	/* Set MD1 to DOMAIN1 */
+	set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_MD_INDEX, E_DOMAIN_1);
+
+	/* Set SPM to DOMAIN9 */
+	set_master_domain(E_DAPC_MASTER, MASTER_SPM_DOM_INDEX, E_DOMAIN_9);
+
+	/* Set HSM to DOMAIN11 */
+	set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_HSM_INDEX, E_DOMAIN_11);
+
+	INFO("Setup master domain MAS_DOM_x: (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n",
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_0),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_1),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_2),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_3),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_4)
+	);
+
+	INFO("Setup master domain INFRACFG_AO_DEVAPC_MAS_DOM: (0x%x)\n",
+			devapc_readl(INFRACFG_AO_DEVAPC_MAS_DOM)
+	);
+
+/******************************************************************************/
+/*Infra Domain Remap Setting */
+/* Infra: no domain remap */
+
+/* SRAMROM Domain Remap Setting */
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_0);
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_1);
+
+	reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_0_0, SRAMROM_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to SRAMROM domain 0
+
+	/* HW BUG: DOM_REMAP reg cannot read */
+/*	INFO("Setup SRAMROM domain remap: (0x%x), (0x%x)\n",
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_0),
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_1)
+	);
+*/
+/* MD Domain Remap Setting */
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_1_0);
+	reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_1_0, MD_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to MD domain 0
+
+	/* HW BUG: DOM_REMAP reg cannot read */
+/*	INFO("Setup MD domain remap: (0x%x)\n",
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_1_0)
+	);
+*/
+}
+
+static void devapc_set_apc(void)
+{
+	uint32_t module_index, dom_index;
+	uint32_t infra_size = sizeof(D_APC_INFRA_Devices)/
+		sizeof(struct INFRA_PERI_DEVICE_INFO);
+	uint32_t md_size = sizeof(D_APC_MD_Devices)/
+		sizeof(struct MD_DEVICE_INFO);
+	enum E_MASK_DOM dom_id;
+
+	/* Initial Permission */
+	INFO("Walk initial permission setting - Infra_peri\n");
+	for (module_index = 0; module_index < infra_size; module_index++) {
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_0,
+				D_APC_INFRA_Devices[module_index].d0_permission);	/* APMCU */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_1,
+				D_APC_INFRA_Devices[module_index].d1_permission);	/* MD1 */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_9,
+				D_APC_INFRA_Devices[module_index].d9_permission);	/* SPM */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_11,
+				D_APC_INFRA_Devices[module_index].d11_permission);	/* HSM */
+
+		/* block all reserved domain */
+		for (dom_id = E_DOMAIN_0; dom_id <= E_DOMAIN_15; dom_id++) {
+			if (dom_id != E_DOMAIN_0 && dom_id != E_DOMAIN_1 &&
+				dom_id != E_DOMAIN_9 && dom_id != E_DOMAIN_11)
+				set_module_apc(E_DAPC_INFRA_SLAVE, module_index,
+						dom_id, E_FORBIDDEN);
+		}
+	}
+
+	INFO("Walk initial permission setting - SRAMROM\n");
+	for (dom_index = 0; dom_index <= E_DOMAIN_8; dom_index++) {
+		if (dom_index == E_DOMAIN_0)
+			set_module_apc(E_DAPC_SRAMROM_SLAVE,
+					DEVAPC_CTRL_SRAMROM_INDEX,
+					dom_index, E_NO_PROTECTION);
+		else
+			set_module_apc(E_DAPC_SRAMROM_SLAVE,
+					DEVAPC_CTRL_SRAMROM_INDEX,
+					dom_index, E_FORBIDDEN);
+	}
+
+	/* MD 2nd level protection */
+	INFO("Walk initial permission setting - MD\n");
+	for (module_index = 0; module_index < md_size; module_index++) {
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_0,
+				D_APC_MD_Devices[module_index].d0_permission);
+		/* block all reserved domain */
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_1,
+				E_FORBIDDEN);
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_2,
+				E_FORBIDDEN);
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_3,
+				E_FORBIDDEN);
+	}
+
+	/* Dump Permission */
+	dump_infra_apc();
+	dump_sramrom_apc();
+	dump_md_apc();
+
+	/* Set CG to Secure (INFRACFG_AO) */
+//	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON0) | SEJ_CG_PROTECT_BIT,
+//			INFRA_AO_SEC_CG_CON0);
+//	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | TRNG_CG_PROTECT_BIT,
+//			INFRA_AO_SEC_CG_CON1);
+	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | DEVAPC_CG_PROTECT_BIT,
+			INFRA_AO_SEC_CG_CON1);
+
+
+	INFO("INFRA_APC_CON = 0x%x\n", devapc_readl(DEVAPC_INFRA_APC_CON));
+
+	/* Set PMS(MD devapc) enable */
+//	devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN) | 0x1, AP2MD1_PMS_CTRL_EN);
+//	devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK) | 0x1, AP2MD1_PMS_CTRL_EN_LOCK);
+//	dump_pms_info();
+
+	if (vio_shift_sta_handler()) {
+		INFO("violation happened after %s\n", __func__);
+		print_vio_mask_sta();
+	}
+
+#ifdef DEVAPC_UT
+	devapc_ut();
+#endif
+
+}
+
+static void sramrom_set_apc(void)
+{
+	INFO("[Pre] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+		devapc_readl(SRAMROM_SEC_ADDR),
+		devapc_readl(SRAMROM_SEC_ADDR1),
+		devapc_readl(SRAMROM_SEC_ADDR2)
+	);
+	INFO("[Pre] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+		devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+		devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+	);
+
+	/* Split 2 regions: 96KB(SEC), 96KB(NON_SEC) */
+	TZ_SRAMROM_SET_REGION_0_SIZE_KB(96);
+
+	/* Set APC to region 0 */
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM0_MASK, PERMIT_S_RW_NS_BLOCK    << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT);
+
+	/* Set APC to region 1 */
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM0_MASK, PERMIT_S_RW_NS_RW       << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT);
+
+	/* Enable region 0 & region 1 protection */
+	DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC0_SEC_EN));
+	DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC1_SEC_EN));
+
+	INFO("[Post] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+		devapc_readl(SRAMROM_SEC_ADDR),
+		devapc_readl(SRAMROM_SEC_ADDR1),
+		devapc_readl(SRAMROM_SEC_ADDR2)
+	);
+	INFO("[Post] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+		devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+		devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+	);
+
+}
+
+void devapc_init(void)
+{
+	uint64_t sramrom_vio_sta;
+	uint64_t sramrom_vio_addr;
+	int i;
+
+	INFO("%s...\n", __func__);
+	/* Enable Devapc */
+	/* Lock DEVAPC_AO/DEVAPC_CON to secure access only */
+	devapc_writel(0x80000001, DEVAPC_INFRA_APC_CON);
+	devapc_writel(0x1, INFRACFG_AO_DEVAPC_CON);
+	devapc_writel(0x80000000, DEVAPC_PD_INFRA_APC_CON);
+
+	INFO("(Post) DEVAPC_INFRA_APC_CON:0x%x\n",
+			devapc_readl(DEVAPC_INFRA_APC_CON));
+	INFO("(Post) INFRACFG_AO_DEVAPC_CON:0x%x\n",
+			devapc_readl(INFRACFG_AO_DEVAPC_CON));
+	INFO("(Post) DEVAPC_PD_INFRA_APC_CON:0x%x\n",
+			devapc_readl(DEVAPC_PD_INFRA_APC_CON));
+
+	/* clr sramrom vio if any */
+	handle_sramrom_vio(&sramrom_vio_sta, &sramrom_vio_addr);
+
+//	print_vio_mask_sta();
+	if (!vio_shift_sta_handler())
+		INFO("no violation happened before init\n");
+
+	/* clear vio_status & unmask vio_mask */
+	INFO("clear vio_staus & unmask modules\n");
+	for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+		clear_infra_vio_status(i);
+		unmask_infra_module(i);
+	}
+
+//	print_vio_mask_sta();
+
+	devapc_set_dom();
+#if CFG_DEVAPC_SET_PROTECT
+	devapc_set_apc();
+#else
+	INFO("Skip to set APC\n");
+#endif
+	sramrom_set_apc();
+
+	INFO("%s done\n", __func__);
+}
+
+/* It should clear SRAMROM vio before clear DEVAPC vio */
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr)
+{
+	int sramrom = -1;
+
+	if (devapc_readl(SRAMROM_SEC_VIO_STA) & SRAM_SEC_VIO_BIT) {		/* SRAM part */
+		INFO("SRAM violation is triggered\n");
+
+		sramrom = 1;
+		*vio_sta = devapc_readl(SRAMROM_SEC_VIO_STA);
+		*vio_addr = devapc_readl(SRAMROM_SEC_VIO_ADDR);
+
+		INFO("(Pre) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			(uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+		devapc_writel(0x1, SRAMROM_SEC_VIO_CLR);
+
+		INFO("(Post) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			devapc_readl(SRAMROM_SEC_VIO_STA),
+			devapc_readl(SRAMROM_SEC_VIO_ADDR));
+
+	} else if (devapc_readl(SRAMROM_ROM_SEC_VIO_STA) & ROM_SEC_VIO_BIT) {	/* ROM part */
+		INFO("ROM violation is triggered\n");
+
+		sramrom = 0;
+		*vio_sta = devapc_readl(SRAMROM_ROM_SEC_VIO_STA);
+		*vio_addr = devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR);
+
+		INFO("(Pre) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			(uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+		devapc_writel(0x1, SRAMROM_ROM_SEC_VIO_CLR);
+
+		INFO("(Post) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			devapc_readl(SRAMROM_ROM_SEC_VIO_STA),
+			devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR));
+	} else {
+		INFO("SRAMROM violation is not triggered\n");
+	}
+
+	return sramrom;
+}
+
+unsigned int devapc_perm_get(int type, int domain, int index)
+{
+	int d = domain; /* domain id */
+	int reg = index / MOD_NO_IN_1_DEVAPC; /* register num */
+	unsigned int value = 0xdeadbeaf;
+
+	INFO("[INFRA] default value is 0x%x\n", value);
+	if (type == E_DAPC_INFRA_SLAVE) {
+		if (index > SLAVE_INFRA_MAX_INDEX)
+			INFO("[INFRA] slave index out of range\n");
+		else if (d > E_DOMAIN_15)
+			INFO("[INFRA] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS0_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[INFRA] SYS0_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else if (type == E_DAPC_SRAMROM_SLAVE) {
+		if (index > SLAVE_SRAMROM_MAX_INDEX)
+			INFO("[SRAMROM] slave index out of range\n");
+		else if (d > E_DOMAIN_8)
+			INFO("[SRAMROM] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS1_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[SRAMROM] SYS1_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else if (type == E_DAPC_MD_SLAVE) {
+		if (index > SLAVE_MD_MAX_INDEX)
+			INFO("[MD] slave index out of range\n");
+		else if (d > E_DOMAIN_3)
+			INFO("[MD] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS2_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[MD] SYS2_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else {
+		dump_infra_apc();
+		dump_sramrom_apc();
+		dump_md_apc();
+
+//		INFO("%s: dump PMS(DEVAPC) reg:\n", __func__);
+//		dump_pms_info();
+	}
+
+	return value;
+}
+
+void tz_dapc_sec_init(void)
+{
+	//nothing
+}
+
+void tz_dapc_sec_postinit(void)
+{
+	//nothing
+}
+
+void tz_apc_common_init(void)
+{
+	devapc_init();
+}
+
+void tz_apc_common_postinit(void)
+{
+	//nothing
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/main.c b/src/bsp/trustzone/teeloader/mt2731/src/main.c
new file mode 100644
index 0000000..f96ef0c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/main.c
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#include "platform.h"
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg, unsigned long boot_reason)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = ATF_INIT_ARG_ADDR;
+    atf_arg->boot_reason = boot_reason;
+}
+
+int teeloader_main(unsigned long bl33_addr, unsigned long boot_reason)
+{
+    u32 tee_addr = 0;
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+
+    // Force to 32-bit
+    boot_reason &= 0xffffffff;
+    set_atf_parameters(atf_arg, boot_reason);
+
+    /* marked because no device APC support */
+	//device_APC_dom_setup();
+    trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+    tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+    /* set tee entry address */
+    tee_set_entry(tee_addr);
+    tee_set_hwuid();
+    tee_set_msg_auth_key();
+
+    trustzone_post_init();
+    trustzone_jump(BL31, BL33, tee_addr);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/print.c b/src/bsp/trustzone/teeloader/mt2731/src/print.c
new file mode 100644
index 0000000..34622c7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c b/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c
new file mode 100644
index 0000000..59419d8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c
@@ -0,0 +1,100 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "hacc_export.h"
+#include "string.h"
+#include "print.h"
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#define HRID                            (0x10206140UL)
+#define SOC_DATA                        (0x08000000UL)
+#define HW_DATA_SIZE                    (0x4UL)
+
+#define MOD "[SECLIB]"
+
+int seclib_get_key(u32 hwaddr, u8 *key, u32 key_size, int index)
+{
+    u32 hwdata[HW_DATA_SIZE] = {0};
+    int i = 0;
+
+    if (key_size != sizeof(hwdata))
+    {
+        return -1;
+    }
+    for (i = 0; i < HW_DATA_SIZE; i++)
+    {
+        hwdata[i] = READ_REGISTER_UINT32(hwaddr + (i * sizeof(u32)));
+    }
+    if (0 != seclib_get_data_key((u8 *)hwdata, key_size, (u8 *)key, index))
+    {
+        return -1;
+    }
+    DBG_MSG("%s HWDATA : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, hwdata[0], hwdata[1], hwdata[2], hwdata[3]);
+
+    return 0;
+}
+
+int seclib_get_hrid_key(u32 *key, u32 key_size)
+{
+    u32 hrkey[HW_DATA_SIZE] = {0};
+
+    if (0 != seclib_get_key(HRID, (u8 *)hrkey, sizeof(hrkey), 1))
+    {
+        return -1;
+    }
+    key[0]=hrkey[0];
+    key[1]=hrkey[1];
+
+    return 0;
+}
+
+int seclib_get_hwid_key(u8 *key, u32 key_size)
+{
+    return seclib_get_key(SOC_DATA, key, key_size, 2);
+}
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..d7e006b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c
@@ -0,0 +1,267 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+
+    if (end <= start)
+    {
+        DBG_MSG("%s, Invalid address! End address should larger than start address.\n", MOD);
+        return -1;
+    }
+
+
+    if((end >> 31) && !(start >> 31))
+    {
+        DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n", MOD);
+        return -1;
+    }
+
+    if ((readl(PERIAXI_BUS_CTL3) & PERISYS_4G_SUPPORT) == 0)
+    {
+        start = start - EMI_PHY_OFFSET;
+        end = end - EMI_PHY_OFFSET;
+        DBG_MSG("%s, MPU 2GB mode.\n", MOD);
+    }
+    else
+        DBG_MSG("%s, MPU 4GB mode.\n", MOD);
+
+    /*Address 64KB alignment*/
+    start = start >> 16;
+    end = end >> 16;
+
+    switch (region) {
+    case 0:
+        writel(0, EMI_MPU_APC0);
+        writel(start, EMI_MPU_SA0);
+        writel(end, EMI_MPU_EA0);
+        writel(access_permission, EMI_MPU_APC0);
+        break;
+
+    case 1:
+        writel(0, EMI_MPU_APC1);
+        writel(start, EMI_MPU_SA1);
+        writel(end, EMI_MPU_EA1);
+        writel(access_permission, EMI_MPU_APC1);
+        break;
+
+    case 2:
+        writel(0, EMI_MPU_APC2);
+        writel(start, EMI_MPU_SA2);
+        writel(end, EMI_MPU_EA2);
+        writel(access_permission, EMI_MPU_APC2);
+        break;
+
+    case 3:
+        writel(0, EMI_MPU_APC3);
+        writel(start, EMI_MPU_SA3);
+        writel(end, EMI_MPU_EA3);
+        writel(access_permission, EMI_MPU_APC3);
+        break;
+
+    case 4:
+        writel(0, EMI_MPU_APC4);
+        writel(start, EMI_MPU_SA4);
+        writel(end, EMI_MPU_EA4);
+        writel(access_permission, EMI_MPU_APC4);
+        break;
+
+    case 5:
+        writel(0, EMI_MPU_APC5);
+        writel(start, EMI_MPU_SA5);
+        writel(end, EMI_MPU_EA5);
+        writel(access_permission, EMI_MPU_APC5);
+        break;
+
+    case 6:
+        writel(0, EMI_MPU_APC6);
+        writel(start, EMI_MPU_SA6);
+        writel(end, EMI_MPU_EA6);
+        writel(access_permission, EMI_MPU_APC6);
+        break;
+
+    case 7:
+        writel(0, EMI_MPU_APC7);
+        writel(start, EMI_MPU_SA7);
+        writel(end, EMI_MPU_EA7);
+        writel(access_permission, EMI_MPU_APC7);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+/* sample code for scenario as below: */
+/* mpu region2: 0x40000000 - 0xe0000000 (2.5GB) is secure RW and non-secure RW for domain 0, 3.*/
+/* mpu region3: 0xe0000000 - 0xe0080000 (512K) is secure RW and non-secure RW for domain 0, 2, 3.*/
+/* mpu region4: 0xe0080000 - 0xe0880000 (8M) is secure and non-secure RW for domain 2, 3.*/
+/* mpu region5: 0xe0880000 - 0xec880000 (384M) is secure RW and non-secure RW for domain 1, 2, 3.*/
+/* mpu region6: 0xec880000 - 0xec8e0000 (384K) is secure RW and non-secure RW for domain 0, 1, 3.*/
+/* mpu region7: 0xec8e0000 - 0xf48e0000 (128M) is secure RW for domain 0, 3.*/
+
+void tz_emi_mpu_init_2(void)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+
+    /*region2 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0x40000000,               /*START_ADDR*/
+                                            0xe0000000,           /*END_ADDR*/
+                                            2,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region3 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xe0000000,               /*START_ADDR*/
+                                            0xe0080000,           /*END_ADDR*/
+                                            3,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region4 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0080000,               /*START_ADDR*/
+                                            0xe0880000,           /*END_ADDR*/
+                                            4,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region5 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0880000,               /*START_ADDR*/
+                                            0xec880000,           /*END_ADDR*/
+                                            5,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region6 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xec880000,               /*START_ADDR*/
+                                            0xec8e0000,           /*END_ADDR*/
+                                            6,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region7 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xec8e0000,               /*START_ADDR*/
+                                            0xf48e0000,           /*END_ADDR*/
+                                            7,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    if(ret)
+        DBG_MSG("%s MPU error!!\n", MOD);
+
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch(mpu_region)
+    {
+        case SECURE_OS_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        case ATF_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        default:
+            DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+            return;
+    }
+
+    DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,  /*START_ADDR*/
+                                        sec_mem_phy_end,    /*END_ADDR*/
+                                        mpu_region,         /*region*/
+                                        sec_mem_mpu_attr);
+
+    if(ret)
+    {
+        DBG_MSG("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c
new file mode 100644
index 0000000..ba5313a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c
@@ -0,0 +1,256 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "seclib.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "device_apc.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+/**************************************************************************
+ *  MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000U)  //4K Alignment
+#define TEE_ENABLE_VERIFY (1U)
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ *  INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+static u32 msg_auth_key[8];
+
+/**************************************************************************
+ *  INTERNAL FUNCTIONS
+ **************************************************************************/
+
+static u64 trustzone_get_atf_init_param_addr(void)
+{
+    return ATF_INIT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+
+void tee_set_entry(u32 addr)
+{
+    tee_entry_addr = addr;
+
+    DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(void)
+{
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[0], g_hwuid[1], g_hwuid[2], g_hwuid[3]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[4], g_hwuid[5], g_hwuid[6], g_hwuid[7]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[8], g_hwuid[9], g_hwuid[10], g_hwuid[11]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[12], g_hwuid[13], g_hwuid[14], g_hwuid[15]);
+    memcpy(teearg->hwuid, g_hwuid, sizeof(g_hwuid));
+    g_hwuid_initialized = 1;
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+    int ret = 0;
+
+    if (!g_hwuid_initialized)
+    {
+        ret = seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+        if(ret != 0)
+            return ret;
+    }
+
+    memcpy(id, g_hwuid, size);
+
+    return ret;
+}
+
+void tee_set_msg_auth_key(void)
+{
+    int i;
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    seclib_get_msg_auth_key((unsigned char *) msg_auth_key, 32);
+
+    DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[0], msg_auth_key[1], msg_auth_key[2], msg_auth_key[3]);
+    DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[4], msg_auth_key[5], msg_auth_key[6], msg_auth_key[7]);
+
+    memcpy(teearg->msg_auth_key, msg_auth_key, sizeof(msg_auth_key));
+}
+
+static void tee_sec_config(void)
+{
+    u32 atf_entry_addr = BL31;
+
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    /* memory protection for TEE */
+    u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+
+    tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+    DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+        secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+
+    /* memory protection for ATF */
+    atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+    u32 atf_end_addr = atf_entry_addr + BL31_SIZE - 1;
+
+    DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+    tz_sec_mem_init(atf_entry_addr, atf_end_addr, ATF_MPU_REGION_ID);
+    DBG_MSG("%s set ATF memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+        atf_end_addr, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+#if CFG_ATF_LOG_SUPPORT
+    atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#endif
+
+#if CFG_TEE_SUPPORT
+    tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+    tz_apc_common_init();
+}
+
+void trustzone_post_init(void)
+{
+    atf_arg_t_ptr atf_init_arg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    atf_init_arg->atf_magic = ATF_BOOTCFG_MAGIC;
+    atf_init_arg->tee_entry = tee_entry_addr;
+    atf_init_arg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+    seclib_get_hrid_key(atf_init_arg->HRID, sizeof(atf_init_arg->HRID));
+    atf_init_arg->atf_log_port = 0x11002000;
+    atf_init_arg->atf_log_baudrate = 0xE1000;
+    atf_init_arg->atf_irq_num = 267; /* reserve SPI ID for ATF log */
+    atf_init_arg->devinfo[0] = 0;
+    atf_init_arg->devinfo[1] = 0;
+    atf_init_arg->devinfo[2] = 0xFFFFFFFF;
+    atf_init_arg->devinfo[3] = 0xFFFFFFFF;
+
+    DBG_MSG("%s HRID[0] : 0x%x\n", MOD, atf_init_arg->HRID[0]);
+    DBG_MSG("%s HRID[1] : 0x%x\n", MOD, atf_init_arg->HRID[1]);
+    DBG_MSG("%s atf_log_port : 0x%x\n", MOD, atf_init_arg->atf_log_port);
+    DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, atf_init_arg->atf_log_baudrate);
+    DBG_MSG("%s atf_irq_num : %d\n", MOD, atf_init_arg->atf_irq_num);
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+    tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        tee_secmem_size);
+    tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+    atf_init_arg->tee_support = 1;
+#elif CFG_OPTEE_TEE_SUPPORT
+    atf_init_arg->tee_support = 1;
+#else
+    atf_init_arg->tee_support = 0;
+#endif
+
+#if CFG_ATF_LOG_SUPPORT
+    atf_init_arg->atf_log_buf_start = atf_log_buf_start;
+    atf_init_arg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+    atf_init_arg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+    atf_init_arg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+    atf_init_arg->atf_log_buf_start = 0;
+    atf_init_arg->atf_log_buf_size = 0;
+    atf_init_arg->atf_aee_debug_buf_start = 0;
+    atf_init_arg->atf_aee_debug_buf_size = 0;
+#endif
+    DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, atf_init_arg->atf_log_buf_start);
+    DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, atf_init_arg->atf_log_buf_size);
+    DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_start);
+    DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry = (void *)addr;
+
+    /* EMI MPU support */
+    tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+    DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+    DBG_MSG("%s Jump to ATF, then jump to bl33 0x%x\n", MOD, arg1);
+#endif
+
+    atf_entry = (jump_atf)BL31;
+    DBG_MSG("[teeloader] teeloader jump to atf!\n");
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..dd49816
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+    tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c
new file mode 100644
index 0000000..8e14488
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c
@@ -0,0 +1,149 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+
+#define MOD "[TZ_TBASE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+    u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+    int ret = 0;
+    sec_mem_arg_t sec_mem_arg;
+    u8 hwuid[16];
+    unsigned char i, *ptmp, tmpbuf;
+
+    ret = tee_get_hwuid(hwuid, 16);
+    if (ret)
+        DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+    /* Prepare secure memory configuration parameters */
+    sec_mem_arg.magic = SEC_MEM_MAGIC;
+    sec_mem_arg.version = SEC_MEM_VERSION;
+    sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+    sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+    sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+    sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+    /* dummy function because of no seclib support */
+    seclib_get_msg_auth_key((unsigned char *) sec_mem_arg.msg_auth_key, 32);
+    /*ptmp = (unsigned char *)sec_mem_arg.msg_auth_key;
+    for(i=0;i<32/2;i++) {
+        tmpbuf = ptmp[i];
+        ptmp[i] = ptmp[31-i];
+        ptmp[31-i] = tmpbuf;
+    }*/
+    sec_mem_arg.rpmb_size = 128*1024; /* 128kx1: minimum size */
+    sec_mem_arg.emmc_rel_wr_sec_c = 1;
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    sec_mem_arg.secmem_obfuscation = 1;
+#else
+    sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+    DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+    DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+    DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+    DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+    DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+    DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+    DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+    DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+    DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+    DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+    DBG_MSG("%s emmc_rel_wr_sec_c: 0x%x\n", MOD, sec_mem_arg.emmc_rel_wr_sec_c);
+
+    memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+    u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+    /* Prepare TEE boot parameters */
+    teearg->magic                 = TBASE_BOOTCFG_MAGIC;             /* Trustonic's TEE magic number */
+    teearg->length                = sizeof(tee_arg_t);               /* Trustonic's TEE argument block size */
+    //teearg->version               = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+    teearg->dRamBase              = dram_base;                       /* DRAM base address */
+    teearg->dRamSize              = dram_size;                       /* Full DRAM size */
+    teearg->secDRamBase           = tee_entry;                       /* Secure DRAM base address */
+    teearg->secDRamSize           = tbase_sec_dram_size;             /* Secure DRAM size */
+    teearg->secIRamBase           = TEE_SECURE_ISRAM_ADDR;           /* Secure SRAM base address */
+    teearg->secIRamSize           = TEE_SECURE_ISRAM_SIZE;           /* Secure SRAM size */
+    //teearg->conf_mair_el3         = read_mair_el3();
+    //teearg->MSMPteCount           = totalPages;
+    //teearg->MSMBase               = (u64)registerFileL2;
+    //teearg->gic_distributor_base  = TBASE_GIC_DIST_BASE;
+    //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+    //teearg->gic_version           = TBASE_GIC_VERSION;
+    teearg->total_number_spi      = 256;                      /* Support total 256 SPIs */
+    teearg->ssiq_number           = 247;                      /* reserve SPI ID 266 for <t-base */
+    //teearg->flags                 = TBASE_MONITOR_FLAGS;
+
+    DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+    DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+    DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+    DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+    DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+    DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+    DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+    DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+    DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+    DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/start.s b/src/bsp/trustzone/teeloader/mt2731/src/start.s
new file mode 100644
index 0000000..6559241
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/start.s
@@ -0,0 +1,71 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*
+ * Register use:
+ *  x9-x10  Scratch
+ */
+tmp                     .req x9
+tmp2                    .req x10
+
+.section .text.start
+
+.globl _start
+_start:
+/*
+ * Note: MT2731 BL2 is built as aarch32. Tee loader is built as aarch64.
+ * CPU context initialization code is required. 0x240000 is the end of l2$. (not good writing...)
+ */
+    mrs     tmp, CurrentEL
+    cmp     tmp, #(0b11 << 2)
+    b.ne    .Lsetup_el2_or_el3_stack
+
+    /* el3 set secure timer */
+    ldr     tmp2, =13000000
+    msr     cntfrq_el0, tmp2
+
+    /* el3 enable smp bit */
+    mrs     tmp2, s3_1_c15_c2_1
+    orr     tmp2, tmp, #(1<<6)
+    msr     s3_1_c15_c2_1, tmp2
+
+.Lsetup_el2_or_el3_stack:
+    /* set el2 or el3 stack pointer */
+    ldr     tmp2, =0x240000
+    mov     sp, tmp2
+
+    b teeloader_main
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/string.c b/src/bsp/trustzone/teeloader/mt2731/src/string.c
new file mode 100644
index 0000000..d916f3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+    const char *sc;
+
+    for (sc = s; *sc != '\0'; ++sc)
+    {
+    }
+    return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+    signed char __res;
+
+    while (1)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+    signed char __res = 0;
+
+    while (count)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+        count--;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+    char *xs = s;
+
+    while (count--)
+        *xs++ = c;
+    return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+    char *tmp = dest;
+    const char *s = src;
+
+    while (count--)
+        *tmp++ = *s++;
+    return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+    const unsigned char *su1, *su2;
+    int res = 0;
+
+    for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+        if ((res = *su1 - *su2) != 0)
+            break;
+    return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+	char *_dst = dst;
+	const char *_src = src;
+
+	if (dst == src)
+		return dst;
+
+	if (dst < src)
+		return memcpy(dst, src, count);
+
+	_dst += count;
+	_src += count;
+	while(count--)
+		*--_dst = *--_src;
+
+	return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/uart.c b/src/bsp/trustzone/teeloader/mt2731/src/uart.c
new file mode 100644
index 0000000..e93d4dc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/tllink.lds b/src/bsp/trustzone/teeloader/mt2731/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt2735/Makefile b/src/bsp/trustzone/teeloader/mt2735/Makefile
new file mode 100644
index 0000000..7ae84be
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/Makefile
@@ -0,0 +1,71 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/device_apc.c \
+	$(DIR_SRC)/security/tz_init.c \
+	$(DIR_SRC)/security/tz_emi_mpu.c \
+	$(DIR_SRC)/security/tz_sec_cfg.c \
+	$(DIR_SRC)/security/seclib.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+	$(DIR_SRC)/security/tz_tbase.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin -fno-stack-protector ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2735/custom/auto2731m1v1-ivi_agl/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2735/custom/auto2731m1v1-ivi_agl/cust_tee.mak
new file mode 100644
index 0000000..3818332
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/custom/auto2731m1v1-ivi_agl/cust_tee.mak
@@ -0,0 +1,7 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
diff --git a/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp1/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp1/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp1/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp2/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp2/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/custom/mt2731evb-ivt-vp2/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2735/default.mak b/src/bsp/trustzone/teeloader/mt2735/default.mak
new file mode 100644
index 0000000..3c327dd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/default.mak
@@ -0,0 +1,14 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT2735
+CFG_ATF_LOG_SUPPORT := 0
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+CFG_TZ_SRAMROM_SUPPORT := 1
+CFG_TZ_UART_APDMA_SUPPORT := 1
+CFG_DEVAPC_SET_PROTECT := 1
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x4FFC0000
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2735/feature.mak b/src/bsp/trustzone/teeloader/mt2735/feature.mak
new file mode 100644
index 0000000..3ba5fe6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/feature.mak
@@ -0,0 +1,58 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
+
+ifdef CFG_TZ_SRAMROM_SUPPORT
+C_OPTION += -DCFG_TZ_SRAMROM_SUPPORT=${CFG_TZ_SRAMROM_SUPPORT}
+export CFG_TZ_SRAMROM_SUPPORT
+endif
+
+ifdef CFG_DEVAPC_SET_PROTECT
+C_OPTION += -DCFG_DEVAPC_SET_PROTECT=${CFG_DEVAPC_SET_PROTECT}
+export CFG_DEVAPC_SET_PROTECT
+endif
+
+ifdef CFG_TZ_UART_APDMA_SUPPORT
+C_OPTION += -DCFG_TZ_UART_APDMA_SUPPORT=${CFG_TZ_UART_APDMA_SUPPORT}
+export CFG_TZ_UART_APDMA_SUPPORT
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2735/include/device_apc.h
new file mode 100644
index 0000000..263d492
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/device_apc.h
@@ -0,0 +1,409 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+/* #define DEVAPC_UT */
+
+/******************************************************************************
+ * SIP CMD DEFINITION
+ ******************************************************************************/
+#define SIP_APC_MODULE_SET	0x1
+#define SIP_APC_MM2ND_SET	0x2
+#define SIP_APC_MASTER_SET	0x3
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void tz_apc_common_init(void);
+void tz_apc_common_postinit(void);
+void devapc_init(void);
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr);
+unsigned int devapc_perm_get(int, int, int);
+uint64_t sip_tee_apc_request(uint32_t cmd, uint32_t x1, uint32_t x2, uint32_t x3);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum E_TRANSACTION {
+	NON_SECURE_TRANSACTION = 0,
+	SECURE_TRANSACTION,
+	E_TRANSACTION_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum APC_ATTR {
+	E_NO_PROTECTION = 0,
+	E_SEC_RW_ONLY,
+	E_SEC_RW_NS_R,
+	E_FORBIDDEN,
+	E_APC_ATTR_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum E_MASK_DOM {
+	E_DOMAIN_0 = 0,
+	E_DOMAIN_1,
+	E_DOMAIN_2,
+	E_DOMAIN_3,
+	E_DOMAIN_4,
+	E_DOMAIN_5,
+	E_DOMAIN_6,
+	E_DOMAIN_7,
+	E_DOMAIN_8,
+	E_DOMAIN_9,
+	E_DOMAIN_10,
+	E_DOMAIN_11,
+	E_DOMAIN_12,
+	E_DOMAIN_13,
+	E_DOMAIN_14,
+	E_DOMAIN_15,
+	E_MASK_DOM_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_MASTER_TYPE {
+	E_DAPC_MASTER = 0,
+	E_DAPC_INFRACFG_AO_MASTER,
+	E_DAPC_MASTER_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_SLAVE_TYPE {
+	E_DAPC_INFRA_SLAVE = 0,
+	E_DAPC_SRAMROM_SLAVE,
+	E_DAPC_MD_SLAVE,
+	E_DAPC_OTHERS_SLAVE,
+	E_DAPC_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+enum DAPC_PD_SLAVE_TYPE {
+	E_DAPC_PD_INFRA_MM_MD_SLAVE = 0,
+	E_DAPC_PD_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF  /* force enum to use 32 bits */
+};
+
+struct INFRA_PERI_DEVICE_INFO {
+	unsigned char       d0_permission;
+	unsigned char       d1_permission;
+	unsigned char       d9_permission;
+	unsigned char       d11_permission;
+};
+
+#define DAPC_INFRA_ATTR(DEV_NAME, PERM_ATTR1, PERM_ATTR2, PERM_ATTR3, PERM_ATTR4) \
+{(unsigned char)PERM_ATTR1, (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, (unsigned char)PERM_ATTR4}
+
+struct MD_DEVICE_INFO {
+	unsigned char       d0_permission;
+};
+
+#define DAPC_MD_ATTR(DEV_NAME, PERM_ATTR1) {(unsigned char)PERM_ATTR1}
+
+enum DEVAPC_ERR_STATUS {
+	DEVAPC_OK = 0x0,
+
+	DEVAPC_ERR_GENERIC = 0x1000,
+	DEVAPC_ERR_INVALID_CMD = 0x1001,
+	DEVAPC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+	DEVAPC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+	DEVAPC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+	DEVAPC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+	DEVAPC_ERR_OUT_OF_BOUNDARY = 0x1006,
+};
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+
+#define devapc_writel(VAL, REG)		__raw_writel(VAL, REG)
+#define devapc_readl(REG)		__raw_readl(REG)
+
+static void tz_set_field(volatile u32 *reg, u32 field, u32 val)
+{
+	u32 tv = (u32)*reg;
+	tv &= ~(field);
+	tv |= val;
+	*reg = tv;
+}
+
+#define reg_set_field(r, f, v)	tz_set_field((volatile u32 *)r, f, v)
+
+/******************************************************************************
+ *
+ * REGISTER ADDRESS DEFINITION
+ *
+ ******************************************************************************/
+#define DEVAPC_AO_INFRA_BASE        0x1001C000
+#define DEVAPC_PD_INFRA_BASE        0x10207000
+
+#define SRAMROM_BASE                0x10214000
+#define INFRACFG_AO_BASE            0x10001000
+#define SECURITY_AO_BASE            0x1001A000
+
+/* #define BLOCKED_REG_BASE            0x10400000 */
+
+/*******************************************************************************************/
+/* Device APC AO */
+#define DEVAPC_SYS0_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0000))
+#define DEVAPC_SYS1_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x1000))
+#define DEVAPC_SYS2_D0_APC_0           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x2000))
+
+#define DEVAPC_INFRA_MAS_DOM_0         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0900))
+#define DEVAPC_INFRA_MAS_DOM_1         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0904))
+#define DEVAPC_INFRA_MAS_DOM_2         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0908))
+#define DEVAPC_INFRA_MAS_DOM_3         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x090C))
+#define DEVAPC_INFRA_MAS_DOM_4         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0910))
+
+#define DEVAPC_INFRA_MAS_SEC_0         ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0A00))
+
+#define DEVAPC_INFRA_APC_CON           ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0F00))
+
+#define DEVAPC_SRAMROM_DOM_REMAP_0_0   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0800))
+#define DEVAPC_SRAMROM_DOM_REMAP_0_1   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0804))
+#define DEVAPC_SRAMROM_DOM_REMAP_1_0   ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0810))
+
+/* MD is combined into DEVAPC_AO SYS2 */
+
+/*******************************************************************************************/
+/* Device APC PD */
+#define DEVAPC_PD_INFRA_VIO_MASK(index) \
+	((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_STA(index) \
+	((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x400 + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_DBG0       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0900))
+#define DEVAPC_PD_INFRA_VIO_DBG1       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0904))
+#define DEVAPC_PD_INFRA_VIO_DBG2       ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0908))
+
+#define DEVAPC_PD_INFRA_APC_CON        ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F00))
+
+#define DEVAPC_PD_INFRA_VIO_SHIFT_STA  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F10))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_SEL  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F14))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_CON  ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F20))
+
+/*******************************************************************************************/
+
+#define INFRA_AO_SEC_CON		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F80))
+
+/* INFRACFG AO */
+#define INFRA_AO_SEC_CG_CON0		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F84))
+#define INFRA_AO_SEC_CG_CON1		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F88))
+#define INFRA_AO_SEC_CG_CON2		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F9C))
+#define INFRA_AO_SEC_CG_CON3		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0FA4))
+
+#define INFRACFG_AO_DEVAPC_CON		((volatile unsigned int *)(INFRACFG_AO_BASE+0x0710))
+#define INFRACFG_AO_DEVAPC_MAS_DOM	((volatile unsigned int *)(INFRACFG_AO_BASE+0x0714))
+#define INFRACFG_AO_DEVAPC_MAS_SEC	((volatile unsigned int *)(INFRACFG_AO_BASE+0x0718))
+
+/* PMS(MD devapc) */
+/* #define AP2MD1_PMS_CTRL_EN             ((unsigned int *)0x100018AC) */
+/* #define AP2MD1_PMS_CTRL_EN_LOCK        ((unsigned int *)0x100018A8) */
+
+/*******************************************************************************************/
+
+#define SRAMROM_SEC_VIO_STA            ((volatile unsigned int *)(SRAMROM_BASE+0x010))
+#define SRAMROM_SEC_VIO_ADDR           ((volatile unsigned int *)(SRAMROM_BASE+0x014))
+#define SRAMROM_SEC_VIO_CLR            ((volatile unsigned int *)(SRAMROM_BASE+0x018))
+
+#define SRAMROM_ROM_SEC_VIO_STA        ((volatile unsigned int *)(SRAMROM_BASE+0x110))
+#define SRAMROM_ROM_SEC_VIO_ADDR       ((volatile unsigned int *)(SRAMROM_BASE+0x114))
+#define SRAMROM_ROM_SEC_VIO_CLR        ((volatile unsigned int *)(SRAMROM_BASE+0x118))
+
+
+#define SRAMROM_SEC_CTRL               ((volatile unsigned int *)(SECURITY_AO_BASE+0x010))
+#define SRAMROM_SEC_CTRL2              ((volatile unsigned int *)(SECURITY_AO_BASE+0x018))
+#define SRAMROM_SEC_CTRL5              ((volatile unsigned int *)(SECURITY_AO_BASE+0x024))
+#define SRAMROM_SEC_CTRL6              ((volatile unsigned int *)(SECURITY_AO_BASE+0x028))
+#define SRAMROM_SEC_ADDR               ((volatile unsigned int *)(SECURITY_AO_BASE+0x050))
+#define SRAMROM_SEC_ADDR1              ((volatile unsigned int *)(SECURITY_AO_BASE+0x054))
+#define SRAMROM_SEC_ADDR2              ((volatile unsigned int *)(SECURITY_AO_BASE+0x058))
+
+#define SRAMROM_SEC_ADDR_SEC0_SEC_EN       (28)
+#define SRAMROM_SEC_ADDR_SEC1_SEC_EN       (29)
+#define SRAMROM_SEC_ADDR_SEC2_SEC_EN       (30)
+#define SRAMROM_SEC_ADDR_SEC3_SEC_EN       (31)
+
+/* SEC means region (0~3) */
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT   (0)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT   (3)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT   (6)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT   (9)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT   (16)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT   (19)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT   (22)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT   (25)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT  (0)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT  (3)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT  (6)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT  (9)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT  (16)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT  (19)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT  (22)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT  (25)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT  (0)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT  (3)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT  (6)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT  (9)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT  (16)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT  (19)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT  (22)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT  (25)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT  (0)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT  (3)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT  (6)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT  (9)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT  (16)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT  (19)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT  (22)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT  (25)
+
+
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT)
+
+#define PERMIT_S_RW_NS_RW       (0x0)
+#define PERMIT_S_RW_NS_BLOCK    (0x1)
+#define PERMIT_S_RW_NS_RO       (0x2)
+#define PERMIT_S_RW_NS_WO       (0x3)
+#define PERMIT_S_RO_NS_RO       (0x4)
+#define PERMIT_S_BLOCK_NS_BLOCK (0x7)
+
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0) */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size)	(devapc_writel(((size & 0xff) << 10), SRAMROM_SEC_ADDR))
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+/* If you config register INFRA_AO_SEC_CON(address 0x10000F80) bit[4] = 1,
+ * the domain comes from device_apc. By default this register is 0,
+ * the domain comes form MD1
+ */
+#define FORCE_MD1_SIGNAL_FROM_DAPC      ((0x1) << 4)
+
+/* PROTECT BIT FOR INFRACFG AO */
+#define SEJ_CG_PROTECT_BIT              ((0x1) << 5)
+#define TRNG_CG_PROTECT_BIT             ((0x1) << 9)
+#define DEVAPC_CG_PROTECT_BIT           ((0x1) << 20)
+
+#define SRAM_SEC_VIO_BIT                (0x1)
+#define ROM_SEC_VIO_BIT                 (0x1)
+
+/*******************************************************************************************/
+/* Master domain/secure bit definition */
+#define MASTER_SPM_DOM_INDEX		(18)
+#define MASTER_SPM_SEC_INDEX		(19)
+#define MASTER_INFRA_MAX_INDEX		(19)
+
+/* Below master should be set in INFRACFG_AO */
+#define MASTER_INFRACFG_AO_MAX_INDEX	5
+#define MASTER_APMCU_INDEX		0
+#define MASTER_MD_INDEX			1
+#define MASTER_HSM_INDEX		2
+#define MASTER_USB_INDEX		3
+#define MASTER_SSUSB_INDEX		4
+#define MASTER_MSDC0_INDEX		5
+
+/*******************************************************************************************/
+/* Master domain remap */
+#define MASTER_DOM_RMP_INIT		(0xFFFFFFFF)
+#define SRAMROM_RMP_AP			(0x7 << 0)	// Infra domain 0
+
+#define MD_RMP_AP			(0x3 << 0)	// Infra domain 0
+
+/*******************************************************************************************/
+#define MOD_NO_IN_1_DEVAPC              16
+#define MAS_DOM_NO_IN_1_DEVAPC		4
+
+/* infra/sramrom/MD support maximum domain num */
+#define DEVAPC_INFRA_DOM_MAX		16
+#define DEVAPC_SRAMROM_DOM_MAX		8
+#define DEVAPC_MD_DOM_MAX		4
+
+/* infra/sramrom/MD APC number per domain */
+#define DEVAPC_INFRA_APC_NUM		10
+#define DEVAPC_SRAMROM_APC_NUM		1
+#define DEVAPC_MD_APC_NUM		3
+
+/* infra/sramrom/MD support maximum ctrl index */
+#define SLAVE_INFRA_MAX_INDEX		146
+#define SLAVE_SRAMROM_MAX_INDEX		0
+#define SLAVE_MD_MAX_INDEX		35
+
+#define VIO_MASK_STA_NUM		13
+#define SRAMROM_VIO_INDEX		355
+#define DEVAPC_CTRL_SRAMROM_INDEX	0
+/* devapc can only handle vio index 0 ~ sramrom */
+#define VIOLATION_MAX_INDEX		SRAMROM_VIO_INDEX
+#define VIOLATION_TRIGGERED		1
+
+#endif /* DEVICE_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2735/include/hacc_export.h
new file mode 100644
index 0000000..fc3e2d6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/hacc_export.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+				unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/platform.h b/src/bsp/trustzone/teeloader/mt2735/include/platform.h
new file mode 100644
index 0000000..4f9c524
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR	(0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE	(0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE               (0x500000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE               (0x500000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE           (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0xE00000UL) /* TEE max DRAM size is 14MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE           (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE           (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/print.h b/src/bsp/trustzone/teeloader/mt2735/include/print.h
new file mode 100644
index 0000000..176ca38
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/seclib.h b/src/bsp/trustzone/teeloader/mt2735/include/seclib.h
new file mode 100644
index 0000000..fab3935
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/seclib.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX          (0xFFFFFFFFUL)    /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/string.h b/src/bsp/trustzone/teeloader/mt2735/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2735/include/typedefs.h
new file mode 100644
index 0000000..5305aef
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/typedefs.h
@@ -0,0 +1,184 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+typedef unsigned long uintptr_t;
+typedef u64 uint64_t;
+typedef u32 uint32_t;
+typedef u32 size_t;
+typedef u8 uint8_t;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE   (0U)
+#endif
+#ifndef TRUE
+#define TRUE    (1U)
+#endif
+
+#ifndef NULL
+#define NULL    (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define printf	print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET      (0x40000000UL)
+#define EMI_MPU_ALIGNMENT   (0x10000UL)
+#define PERIAXI_BUS_CTL3    (0x10003208UL)
+#define PERISYS_4G_SUPPORT  (0x1 << 11)
+
+
+typedef enum
+{
+    TZ_MPU_SEC_RW_NSEC_RW = 0,      /* read and write for both secure and non-secure access */
+    TZ_MPU_SEC_RW_NSEC_DENY = 1,    /* read and write for secure access */
+    TZ_MPU_SEC_RW_NSEC_RO = 2,      /* read and write for secure access and read only for non-secure access */
+    TZ_MPU_SEC_RW_NSEC_WO = 3,      /* read and write for secure access and write only for non-secure access */
+    TZ_MPU_SEC_RO_NSEC_RO = 4,      /* read only for both secure access and non-secure access */
+    TZ_MPU_SEC_DENY_NSEC_DENY = 5,  /* Any access is prohibited */
+    TZ_MPU_SEC_RO_NSEC_RW = 6       /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID    (0)
+#define ATF_MPU_REGION_ID          (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE                (0x1020E000U)
+
+#define EMI_MPU_SA0                 ((P_U32)(EMI_MPU_BASE+0x100))  /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1                 ((P_U32)(EMI_MPU_BASE+0x104))  /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2                 ((P_U32)(EMI_MPU_BASE+0x108))  /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3                 ((P_U32)(EMI_MPU_BASE+0x10C))  /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4                 ((P_U32)(EMI_MPU_BASE+0x110))  /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5                 ((P_U32)(EMI_MPU_BASE+0x114))  /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6                 ((P_U32)(EMI_MPU_BASE+0x118))  /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7                 ((P_U32)(EMI_MPU_BASE+0x11C))  /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0                 ((P_U32)(EMI_MPU_BASE+0x200))  /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1                 ((P_U32)(EMI_MPU_BASE+0x204))  /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2                 ((P_U32)(EMI_MPU_BASE+0x208))  /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3                 ((P_U32)(EMI_MPU_BASE+0x20C))  /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4                 ((P_U32)(EMI_MPU_BASE+0x210))  /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5                 ((P_U32)(EMI_MPU_BASE+0x214))  /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6                 ((P_U32)(EMI_MPU_BASE+0x218))  /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7                 ((P_U32)(EMI_MPU_BASE+0x21C))  /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0                ((P_U32)(EMI_MPU_BASE+0x300))  /* EMI MPU APC 0 */
+#define EMI_MPU_APC1                ((P_U32)(EMI_MPU_BASE+0x304))  /* EMI MPU APC 1 */
+#define EMI_MPU_APC2                ((P_U32)(EMI_MPU_BASE+0x308))  /* EMI MPU APC 2 */
+#define EMI_MPU_APC3                ((P_U32)(EMI_MPU_BASE+0x30C))  /* EMI MPU APC 3 */
+#define EMI_MPU_APC4                ((P_U32)(EMI_MPU_BASE+0x310))  /* EMI MPU APC 4 */
+#define EMI_MPU_APC5                ((P_U32)(EMI_MPU_BASE+0x314))  /* EMI MPU APC 5 */
+#define EMI_MPU_APC6                ((P_U32)(EMI_MPU_BASE+0x318))  /* EMI MPU APC 6 */
+#define EMI_MPU_APC7                ((P_U32)(EMI_MPU_BASE+0x31C))  /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0             ((P_U32)(EMI_MPU_BASE+0x900))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1             ((P_U32)(EMI_MPU_BASE+0x904))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2             ((P_U32)(EMI_MPU_BASE+0x908))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3             ((P_U32)(EMI_MPU_BASE+0x90C))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4             ((P_U32)(EMI_MPU_BASE+0x910))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5             ((P_U32)(EMI_MPU_BASE+0x914))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6             ((P_U32)(EMI_MPU_BASE+0x918))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7             ((P_U32)(EMI_MPU_BASE+0x91C))  /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2735/include/tz_init.h
new file mode 100644
index 0000000..f370160
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/tz_init.h
@@ -0,0 +1,84 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+//Don't used the typedef of teeloader, as this file will be included in Trustonic tee.
+//Which MUST use specific gcc version compiler, and the compiler have some conflict define
+//with the typedef here.
+//#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+#define HRID_SIZE 2
+/* bootarg for ATF */
+typedef struct {
+    unsigned long long bootarg_loc;
+    unsigned long long bootarg_size;
+    unsigned long long bl33_start_addr;
+    unsigned long long tee_info_addr;
+    unsigned long long boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+    unsigned int atf_magic;
+    unsigned int tee_support;
+    unsigned int tee_entry;
+    unsigned long long tee_boot_arg_addr;
+    unsigned int hwuid[4];     // HW Unique id for t-base used
+    unsigned int HRID[HRID_SIZE];      // HW random id for t-base used
+    unsigned int atf_log_port;
+    unsigned int atf_log_baudrate;
+    unsigned long long atf_log_buf_start;
+    unsigned int atf_log_buf_size;
+    unsigned int atf_irq_num;
+    unsigned int devinfo[DEVINFO_SIZE];
+    unsigned long long atf_aee_debug_buf_start;
+    unsigned int atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+    unsigned int tee_rpmb_size;
+#endif
+}atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2735/include/tz_mem.h
new file mode 100644
index 0000000..223408f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/tz_mem.h
@@ -0,0 +1,102 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS   (0x00100000UL)
+#define SRAM_START_ADDR     (0x00102140UL)
+#define VECTOR_START        (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+    short next, previous;
+} tz_memory_t;
+
+#define FREE            ((short)(0x0001U))
+#define IS_FREE(x)      ((x)->next & FREE)
+#define CLEAR_FREE(x)   ((x)->next &= ~FREE)
+#define SET_FREE(x)     ((x)->next |= FREE)
+#define FROM_ADDR(x)    ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x)      ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC                   (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION                 (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE        (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE       (0x80000UL) //0.5MB by default
+
+#define BL31                            (0x42C01000UL)
+#define BL31_SIZE                       (0x40000UL)
+#define BL33                            (0x42110000UL)
+
+
+#define ATF_BOOT_ARG_ADDR                              (0x40000000UL)
+#define ATF_INIT_ARG_ADDR				(0x40000100UL)
+
+#define TEE_BOOT_ARG_ADDR                              (0x42000100UL)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR           (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE           (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+    unsigned int magic;              // Magic number
+    unsigned int version;            // version
+    unsigned int svp_mem_start;      // MM sec mem pool start addr.
+    unsigned int svp_mem_end;        // MM sec mem pool end addr.
+    unsigned int tplay_table_start;  // tplay handle-to-physical table start
+    unsigned int tplay_table_size;   // tplay handle-to-physical table size
+    unsigned int tplay_mem_start;    // tplay physcial memory start address for crypto operation
+    unsigned int tplay_mem_size;     // tplay phsycial memory size for crypto operation
+    unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+    unsigned int rpmb_size;          /* size of rpmb partition */
+    unsigned int msg_auth_key[8];    /* size of message auth key is 32bytes(256 bits) */
+    unsigned int emmc_rel_wr_sec_c;  // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2735/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+    u32 magic;        // magic value from information
+    u32 length;       // size of struct in bytes.
+    u64 version;      // Version of structure
+    u64 dRamBase;     // NonSecure DRAM start address
+    u64 dRamSize;     // NonSecure DRAM size
+    u64 secDRamBase;  // Secure DRAM start address
+    u64 secDRamSize;  // Secure DRAM size
+    u64 secIRamBase;  // Secure IRAM base
+    u64 secIRamSize;  // Secure IRam size
+    u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+    u32 RFU1;
+    u32 MSMPteCount;  // Number of MMU entries for MSM
+    u64 MSMBase;      // MMU entries for MSM
+    u64 gic_distributor_base;
+    u64 gic_cpuinterface_base;
+    u32 gic_version;
+    u32 RFU2;
+    u64 flags;
+    u32 total_number_spi;
+    u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2735/include/uart.h b/src/bsp/trustzone/teeloader/mt2735/include/uart.h
new file mode 100644
index 0000000..9a6ba92
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/include/uart.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include "typedefs.h"
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE      (1U << 5U)
+#define UART_THR(uart)     (UART_BASE(uart) + 0x0U)  /* Write only */
+
+#define IO_PHYS            (0x10000000UL)
+#define UART1_BASE         (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2735/prebuilt/libsec.a b/src/bsp/trustzone/teeloader/mt2735/prebuilt/libsec.a
new file mode 100644
index 0000000..b6fb1af
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/prebuilt/libsec.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2735/src/drivers/device_apc.c
new file mode 100644
index 0000000..6e5e942
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/drivers/device_apc.c
@@ -0,0 +1,984 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include <stdbool.h>
+#include "device_apc.h"
+#include "print.h"
+
+#define MTAG	"[DEVAPC]"
+#define DAPC_DEBUG
+
+#ifdef DAPC_DEBUG
+#define DBG(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG(str, ...) do {} while(0)
+#endif
+
+#define INFO(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#define ERROR(str, ...) do {print(MTAG "[ERROR]" str, ##__VA_ARGS__);} while(0)
+
+
+static const struct INFRA_PERI_DEVICE_INFO D_APC_INFRA_Devices[] = {
+	/*		module,					AP permission,   MD permission,   SPM permission,
+	 */
+
+	/* 0 */
+	DAPC_INFRA_ATTR("SPM_APB_S",                            E_NO_PROTECTION, E_SEC_RW_ONLY,   E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPM_APB_S-1",                          E_SEC_RW_ONLY,   E_SEC_RW_ONLY,   E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPM_APB_S-2",                          E_SEC_RW_ONLY,   E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOPCKGEN_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRACFG_AO_APB_S",                    E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("IOCFG_APB_S",                          E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PERICFG_AO_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EFUSE_DEBUG_AO_APB_S",                 E_SEC_RW_NS_R,   E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GPIO_APB_S",                           E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOPRGU_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 10 */
+	DAPC_INFRA_ATTR("APXGPT_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_RSV0_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SEJ_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AP_CIRQ_EINT_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("APMIXEDSYS_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PMIC_WRAP_APB_S",                      E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_RSV2_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("KP_APB_S",                             E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TOP_MISC_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DVFSRC_APB_S",                         E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 20 */
+	DAPC_INFRA_ATTR("MBIST_AO_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_AO_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRAAO_BCRM_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AES_TOP0_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SYS_TIMER_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MODEM_TEMP_SHARE_APB_S",               E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEBUG_CTRL_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SECURITY_AO_APB_S",                    E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("TOPCKGEN_INFRA_CFG_APB_S",             E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEVICE_APC_AO_APB_S",                  E_SEC_RW_ONLY,   E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 30 */
+	DAPC_INFRA_ATTR("PWM_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("HSM_AXI_S",                            E_SEC_RW_ONLY,   E_FORBIDDEN,     E_FORBIDDEN,     E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("PCIE_BR_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PCIE_PCI0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S-1",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SSUSB_S-2",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S",                                E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S-1",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("USB_S-2",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 40 */
+	DAPC_INFRA_ATTR("MCUPM_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUPM_APB_S-1",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUPM_APB_S-2",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AUDIO_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC0_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC1_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MSDC2_S",                              E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB1_S",                          E_NO_PROTECTION, E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EAST_APB2_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 50 */
+	DAPC_INFRA_ATTR("EAST_APB3_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB0_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("SOUTH_APB1_S",                         E_NO_PROTECTION, E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB2_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SOUTH_APB3_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB0_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB1_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB2_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("WEST_APB3_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB0_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 60 */
+	DAPC_INFRA_ATTR("NORTH_APB1_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB2_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NORTH_APB3_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MCUCFG_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SYS_CIRQ_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TRNG_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEVICE_APC_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DEBUG_TRACKER_APB_S",                  E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF0_AP_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF0_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 70 */
+	DAPC_INFRA_ATTR("CCIF1_AP_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF1_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("MBIST_PDN_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRACFG_PDN_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_NS_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_MMU_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CQ_DMA_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRA_RSV0_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SRAMROM_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+
+	/* 80 */
+	DAPC_INFRA_ATTR("INFRA_BCRM_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EMI_APB_S",                            E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("INFRA_RSV2_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_APB_S",                          E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CLDMA_MD_APB_S",                       E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("EMI_MPU_APB_S",                        E_SEC_RW_NS_R,   E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("INFRA_RSV3_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP0_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP1_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP2_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+
+	/* 90 */
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP3_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH0_TOP4_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP0_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP1_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP2_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP3_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DRAMC_CH1_TOP4_APB_S",                 E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCE_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF2_AP_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF2_MD_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 100 */
+	DAPC_INFRA_ATTR("CCIF3_AP_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("CCIF3_MD_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC2_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC3_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC4_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC5_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC6_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC7_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC8_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 110 */
+	DAPC_INFRA_ATTR("GCPU_ECC9_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC10_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC11_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC12_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC13_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC14_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC15_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("GCPU_ECC16_APB_S",                     E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("FAKE_ENG_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("TRFG_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 120 */
+	DAPC_INFRA_ATTR("DEBUG_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("APDMA_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("AUXADC_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART0_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("UART1_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_NO_PROTECTION),
+	DAPC_INFRA_ATTR("UART2_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART3_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_NO_PROTECTION, E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C0_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C1_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C2_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 130 */
+	DAPC_INFRA_ATTR("SPI0_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PTP_THERM_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("BTIF_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("PERI_RSV0_APB_S",                      E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("DISP_PWM_APB_S",                       E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C3_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI1_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("I2C4_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI2_APB_S",                           E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("SPI_SLV_APB_S",                        E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+	/* 140 */
+	DAPC_INFRA_ATTR("UART4_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART5_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("UART6_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("IMP_IIC_WRAP_APB_S",                   E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NFI_APB_S",                            E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("NFIECC_APB_S",                         E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+	DAPC_INFRA_ATTR("ETHER_APB_S",                          E_NO_PROTECTION, E_FORBIDDEN,     E_FORBIDDEN,     E_FORBIDDEN),
+
+};
+
+static const struct MD_DEVICE_INFO D_APC_MD_Devices[] = {
+	/*              module,                     AP permission */
+
+	 /* 0 */
+	DAPC_MD_ATTR("MDPERISYS_1",                 E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDPERISYS_2/MDTOP",           E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDMCUAPB",                    E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDCORESYS",                   E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDINFRA_APB_1",               E_NO_PROTECTION),
+	DAPC_MD_ATTR("MDINFRA_APB_2",               E_NO_PROTECTION),
+	DAPC_MD_ATTR("MML2",                        E_NO_PROTECTION),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+
+	 /* 10 */
+	DAPC_MD_ATTR("MD_INFRA",                    E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("uSIP Peripheral",             E_FORBIDDEN),
+	DAPC_MD_ATTR("modeml1_ao_top_pwr_wrap",     E_NO_PROTECTION),
+	DAPC_MD_ATTR("md2gsys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rxdfesys_pwr_wrap",           E_FORBIDDEN),
+
+	 /* 20 */
+	DAPC_MD_ATTR("cssys_pwr_wrap",              E_FORBIDDEN),
+	DAPC_MD_ATTR("txsys_pwr_wrap",              E_FORBIDDEN),
+	DAPC_MD_ATTR("bigramsys (mem)",             E_FORBIDDEN),
+	DAPC_MD_ATTR("md32scq share (mem)",         E_FORBIDDEN),
+	DAPC_MD_ATTR("md32scq_vu01 (mem)",          E_FORBIDDEN),
+	DAPC_MD_ATTR("peripheral (reg)",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rakesys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("rakesys_pwr_wrap",            E_FORBIDDEN),
+	DAPC_MD_ATTR("brpsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("brpsys_pwr_wrap",             E_FORBIDDEN),
+
+	 /* 30 */
+	DAPC_MD_ATTR("dmcsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("dmcsys_pwr_wrap",             E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+	DAPC_MD_ATTR("-",                           E_FORBIDDEN),
+
+};
+
+static uint32_t set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module,
+	enum E_MASK_DOM domain_num, enum APC_ATTR permission)
+{
+	uint32_t *base = NULL;
+	uint32_t apc_index;
+	uint32_t apc_set_index;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if (permission != E_NO_PROTECTION &&
+		permission != E_SEC_RW_ONLY &&
+		permission != E_SEC_RW_NS_R &&
+		permission != E_FORBIDDEN) {
+
+		ERROR("permission=0x%x is not supported!\n",
+			permission);
+		return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+	}
+
+	apc_index = module / MOD_NO_IN_1_DEVAPC;
+	apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+	clr_bit = 0xFFFFFFFF ^ (0x3 << (apc_set_index * 2));
+	set_bit = permission << (apc_set_index * 2);
+
+	/* Do boundary check */
+	if (slave_type == E_DAPC_INFRA_SLAVE &&
+		module <= SLAVE_INFRA_MAX_INDEX &&
+		domain_num <= E_DOMAIN_15)
+		base = (uint32_t *)((size_t)DEVAPC_SYS0_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+
+	else if (slave_type == E_DAPC_SRAMROM_SLAVE &&
+		module <= SLAVE_SRAMROM_MAX_INDEX &&
+		domain_num <= E_DOMAIN_8)
+		base = (uint32_t *)((size_t)DEVAPC_SYS1_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+
+	else if (slave_type == E_DAPC_MD_SLAVE &&
+		module <= SLAVE_MD_MAX_INDEX &&
+		domain_num <= E_DOMAIN_3)
+		base = (uint32_t *)((size_t)DEVAPC_SYS2_D0_APC_0 +
+				domain_num * 0x40 + apc_index * 4);
+	else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+			"slave_type", slave_type,
+			"module", module,
+			"domain_num", domain_num);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		devapc_writel((devapc_readl(base) & clr_bit), base);
+		devapc_writel((devapc_readl(base) | set_bit), base);
+
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_transaction(enum DAPC_MASTER_TYPE master_type,
+		uint32_t master_index, enum E_TRANSACTION transaction_type)
+{
+	uint32_t *base = NULL;
+	uint32_t master_set_index;
+
+	master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+	if (master_type == E_DAPC_MASTER &&
+		master_index <= MASTER_INFRA_MAX_INDEX)
+		base = (uint32_t *)DEVAPC_INFRA_MAS_SEC_0;
+
+	else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+		master_index <= MASTER_INFRACFG_AO_MAX_INDEX)
+		base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_SEC;
+
+	else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x\n",
+			"master_type", master_type,
+			"master_index", master_index);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		if (transaction_type == NON_SECURE_TRANSACTION)
+			devapc_writel(devapc_readl(base) &
+				(0xFFFFFFFF ^ (0x1 << master_set_index)), base);
+		else if (transaction_type == SECURE_TRANSACTION)
+			devapc_writel(devapc_readl(base) |
+				(0x1 << master_set_index), base);
+		else {
+			ERROR("transaction=0x%x is not supported!\n",
+					transaction_type);
+			return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+		}
+
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_domain(enum DAPC_MASTER_TYPE master_type,
+		uint32_t master_index, enum E_MASK_DOM dom_num)
+{
+	uint32_t *base = NULL;
+	uint32_t master_reg_index;
+	uint32_t master_set_index;
+	uint32_t set_bit;
+
+	if (master_type == E_DAPC_MASTER &&
+		master_index <= MASTER_INFRA_MAX_INDEX &&
+		dom_num <= E_DOMAIN_15) {
+		master_reg_index = master_index / MAS_DOM_NO_IN_1_DEVAPC;
+		master_set_index = master_index % MAS_DOM_NO_IN_1_DEVAPC;
+		set_bit = dom_num << (master_set_index * 8);
+
+		base = (uint32_t *)((size_t)DEVAPC_INFRA_MAS_DOM_0 + master_reg_index * 4);
+
+	} else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+		master_index <= MASTER_INFRACFG_AO_MAX_INDEX &&
+		dom_num <= E_DOMAIN_15) {
+		set_bit = dom_num << (master_index * 4);
+		base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_DOM;
+
+	} else {
+		ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+			"master_type", master_type,
+			"master_index", master_index,
+			"dom_num", dom_num);
+
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	if (base != NULL) {
+		devapc_writel(devapc_readl(base) | set_bit, base);
+		return DEVAPC_OK;
+	}
+
+	return DEVAPC_ERR_GENERIC;
+}
+
+static void dump_infra_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0; d < DEVAPC_INFRA_DOM_MAX; d++) {
+		if (d != E_DOMAIN_0 && d != E_DOMAIN_1 && d != E_DOMAIN_9 && d != E_DOMAIN_11)
+			continue;
+
+		for (i = 0; i < DEVAPC_INFRA_APC_NUM; i++) {
+			INFO("(INFRA)SYS0_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS0_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS0_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+	}
+
+	INFO("(INFRA)MAS_SEC_0 = 0x%x\n", devapc_readl(DEVAPC_INFRA_MAS_SEC_0));
+}
+
+static void dump_sramrom_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0 ; d < DEVAPC_SRAMROM_DOM_MAX ; d++)
+		for (i = 0; i < DEVAPC_SRAMROM_APC_NUM; i++) {
+			INFO("(MD)SYS1_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS1_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS1_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+}
+
+static void dump_md_apc(void)
+{
+	/* d: domain, i: register number */
+	int d, i;
+
+	for (d = 0 ; d < DEVAPC_MD_DOM_MAX ; d++) {
+		if (d != E_DOMAIN_0)
+			continue;
+
+		for (i = 0; i < DEVAPC_MD_APC_NUM; i++) {
+			INFO("(MD)SYS2_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+				((size_t)DEVAPC_SYS2_D0_APC_0 + 0x40 * d + i * 4),
+				devapc_readl((size_t)DEVAPC_SYS2_D0_APC_0 +
+					0x40 * d + i * 4)
+			);
+		}
+	}
+}
+
+/*
+static void dump_pms_info(void)
+{
+	INFO("[PMS]AP2MD1_PMS_CTRL_EN = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN));
+	INFO("[PMS]AP2MD1_PMS_CTRL_EN_LOCK = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK));
+}
+*/
+
+static void print_vio_mask_sta(void)
+{
+	int i;
+
+	for (i = 0; i < VIO_MASK_STA_NUM; i++) {
+		INFO("%s: (%d:0x%x) %s: (%d:0x%x)\n",
+			"INFRA VIO_MASK", i,
+			devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(i)),
+			"INFRA VIO_STA", i,
+			devapc_readl(DEVAPC_PD_INFRA_VIO_STA(i))
+		);
+	}
+}
+
+static void unmask_infra_module(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	devapc_writel(devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(apc_index)) &
+		(0xFFFFFFFF ^ (1 << apc_bit_index)),
+		DEVAPC_PD_INFRA_VIO_MASK(apc_index));
+}
+
+static uint32_t clear_infra_vio_status(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	devapc_writel(0x1 << apc_bit_index,
+		DEVAPC_PD_INFRA_VIO_STA(apc_index));
+
+	return 0;
+}
+
+static int check_infra_vio_status(uint32_t module)
+{
+	uint32_t apc_index = 0;
+	uint32_t apc_bit_index = 0;
+
+	if (module > VIOLATION_MAX_INDEX) {
+		ERROR("%s: module overflow!\n", __func__);
+		return DEVAPC_ERR_OUT_OF_BOUNDARY;
+	}
+
+	apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+	apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+	if (devapc_readl(DEVAPC_PD_INFRA_VIO_STA(apc_index)) &
+			(0x1 << apc_bit_index))
+		return VIOLATION_TRIGGERED;
+
+	return 0;
+}
+
+static bool vio_shift_sta_handler(void)
+{
+	uint32_t vio_shift_sta = 0;
+
+	vio_shift_sta = devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+	INFO("(Pre)VIO_SHIFT_STA = 0x%x\n", vio_shift_sta);
+
+	if (vio_shift_sta) {
+		devapc_writel(vio_shift_sta, DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+		INFO("(Post)clear VIO_SHIFT_STA = 0x%x\n",
+			devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA));
+	}
+
+	return vio_shift_sta ? true : false;
+}
+
+static void devapc_irq_handler(void)
+{
+	int i;
+	uint64_t vio_sta;
+	uint64_t vio_addr;
+
+	INFO("enter %s...\n", __func__);
+	print_vio_mask_sta();
+	if (!vio_shift_sta_handler()) {
+		INFO("violation is not triggered or is clean before\n");
+		return;
+	}
+
+	for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+		if (check_infra_vio_status(i) == VIOLATION_TRIGGERED) {
+			INFO("violation is triggered, vio_idx=%d\n", i);
+			if (i == SRAMROM_VIO_INDEX)
+				handle_sramrom_vio(&vio_sta, &vio_addr);
+
+			clear_infra_vio_status(i);
+		}
+	}
+
+	print_vio_mask_sta();
+}
+
+#ifdef DEVAPC_UT
+static void devapc_ut(void)
+{
+	INFO("test violation...\n");
+
+	INFO("read blocked reg = 0x%x\n",
+		devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+	devapc_writel(0xdead, (unsigned int *)BLOCKED_REG_BASE);
+	INFO("read blocked reg = 0x%x\n",
+		devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+	devapc_irq_handler();
+
+	mt_irq_dump_status(DEVAPC_IRQ_BIT_ID);
+}
+#endif
+
+static void devapc_set_dom(void)
+{
+
+	/* For EMI workaround, need set SPM as secure master to rw EMI self
+	 * test start/end address
+	 */
+	set_master_transaction(E_DAPC_MASTER, MASTER_SPM_SEC_INDEX, SECURE_TRANSACTION);
+
+	INFO("Setup master secure: %s = (0x%x), %s = (0x%x)\n",
+			"DEVAPC_INFRA_MAS_SEC_0",
+			devapc_readl(DEVAPC_INFRA_MAS_SEC_0),
+			"INFRACFG_AO_DEVAPC_MAS_SEC",
+			devapc_readl(INFRACFG_AO_DEVAPC_MAS_SEC)
+	);
+
+/******************************************************************************/
+/* Infra Master Domain Setting */
+
+	/* Set MD1 to DOMAIN1 */
+	set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_MD_INDEX, E_DOMAIN_1);
+
+	/* Set SPM to DOMAIN9 */
+	set_master_domain(E_DAPC_MASTER, MASTER_SPM_DOM_INDEX, E_DOMAIN_9);
+
+	/* Set HSM to DOMAIN11 */
+	set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_HSM_INDEX, E_DOMAIN_11);
+
+	INFO("Setup master domain MAS_DOM_x: (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n",
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_0),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_1),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_2),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_3),
+			devapc_readl(DEVAPC_INFRA_MAS_DOM_4)
+	);
+
+	INFO("Setup master domain INFRACFG_AO_DEVAPC_MAS_DOM: (0x%x)\n",
+			devapc_readl(INFRACFG_AO_DEVAPC_MAS_DOM)
+	);
+
+/******************************************************************************/
+/*Infra Domain Remap Setting */
+/* Infra: no domain remap */
+
+/* SRAMROM Domain Remap Setting */
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_0);
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_1);
+
+	reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_0_0, SRAMROM_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to SRAMROM domain 0
+
+	/* HW BUG: DOM_REMAP reg cannot read */
+/*	INFO("Setup SRAMROM domain remap: (0x%x), (0x%x)\n",
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_0),
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_1)
+	);
+*/
+/* MD Domain Remap Setting */
+	devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_1_0);
+	reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_1_0, MD_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to MD domain 0
+
+	/* HW BUG: DOM_REMAP reg cannot read */
+/*	INFO("Setup MD domain remap: (0x%x)\n",
+			devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_1_0)
+	);
+*/
+}
+
+static void devapc_set_apc(void)
+{
+	uint32_t module_index, dom_index;
+	uint32_t infra_size = sizeof(D_APC_INFRA_Devices)/
+		sizeof(struct INFRA_PERI_DEVICE_INFO);
+	uint32_t md_size = sizeof(D_APC_MD_Devices)/
+		sizeof(struct MD_DEVICE_INFO);
+	enum E_MASK_DOM dom_id;
+
+	/* Initial Permission */
+	INFO("Walk initial permission setting - Infra_peri\n");
+	for (module_index = 0; module_index < infra_size; module_index++) {
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_0,
+				D_APC_INFRA_Devices[module_index].d0_permission);	/* APMCU */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_1,
+				D_APC_INFRA_Devices[module_index].d1_permission);	/* MD1 */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_9,
+				D_APC_INFRA_Devices[module_index].d9_permission);	/* SPM */
+		set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_11,
+				D_APC_INFRA_Devices[module_index].d11_permission);	/* HSM */
+
+		/* block all reserved domain */
+		for (dom_id = E_DOMAIN_0; dom_id <= E_DOMAIN_15; dom_id++) {
+			if (dom_id != E_DOMAIN_0 && dom_id != E_DOMAIN_1 &&
+				dom_id != E_DOMAIN_9 && dom_id != E_DOMAIN_11)
+				set_module_apc(E_DAPC_INFRA_SLAVE, module_index,
+						dom_id, E_FORBIDDEN);
+		}
+	}
+
+	INFO("Walk initial permission setting - SRAMROM\n");
+	for (dom_index = 0; dom_index <= E_DOMAIN_8; dom_index++) {
+		if (dom_index == E_DOMAIN_0)
+			set_module_apc(E_DAPC_SRAMROM_SLAVE,
+					DEVAPC_CTRL_SRAMROM_INDEX,
+					dom_index, E_NO_PROTECTION);
+		else
+			set_module_apc(E_DAPC_SRAMROM_SLAVE,
+					DEVAPC_CTRL_SRAMROM_INDEX,
+					dom_index, E_FORBIDDEN);
+	}
+
+	/* MD 2nd level protection */
+	INFO("Walk initial permission setting - MD\n");
+	for (module_index = 0; module_index < md_size; module_index++) {
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_0,
+				D_APC_MD_Devices[module_index].d0_permission);
+		/* block all reserved domain */
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_1,
+				E_FORBIDDEN);
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_2,
+				E_FORBIDDEN);
+		set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_3,
+				E_FORBIDDEN);
+	}
+
+	/* Dump Permission */
+	dump_infra_apc();
+	dump_sramrom_apc();
+	dump_md_apc();
+
+	/* Set CG to Secure (INFRACFG_AO) */
+//	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON0) | SEJ_CG_PROTECT_BIT,
+//			INFRA_AO_SEC_CG_CON0);
+//	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | TRNG_CG_PROTECT_BIT,
+//			INFRA_AO_SEC_CG_CON1);
+	devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | DEVAPC_CG_PROTECT_BIT,
+			INFRA_AO_SEC_CG_CON1);
+
+
+	INFO("INFRA_APC_CON = 0x%x\n", devapc_readl(DEVAPC_INFRA_APC_CON));
+
+	/* Set PMS(MD devapc) enable */
+//	devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN) | 0x1, AP2MD1_PMS_CTRL_EN);
+//	devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK) | 0x1, AP2MD1_PMS_CTRL_EN_LOCK);
+//	dump_pms_info();
+
+	if (vio_shift_sta_handler()) {
+		INFO("violation happened after %s\n", __func__);
+		print_vio_mask_sta();
+	}
+
+#ifdef DEVAPC_UT
+	devapc_ut();
+#endif
+
+}
+
+static void sramrom_set_apc(void)
+{
+	INFO("[Pre] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+		devapc_readl(SRAMROM_SEC_ADDR),
+		devapc_readl(SRAMROM_SEC_ADDR1),
+		devapc_readl(SRAMROM_SEC_ADDR2)
+	);
+	INFO("[Pre] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+		devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+		devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+	);
+
+	/* Split 2 regions: 96KB(SEC), 96KB(NON_SEC) */
+	TZ_SRAMROM_SET_REGION_0_SIZE_KB(96);
+
+	/* Set APC to region 0 */
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM0_MASK, PERMIT_S_RW_NS_BLOCK    << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT);
+
+	/* Set APC to region 1 */
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM0_MASK, PERMIT_S_RW_NS_RW       << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT);
+	reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT);
+
+	/* Enable region 0 & region 1 protection */
+	DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC0_SEC_EN));
+	DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC1_SEC_EN));
+
+	INFO("[Post] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+		devapc_readl(SRAMROM_SEC_ADDR),
+		devapc_readl(SRAMROM_SEC_ADDR1),
+		devapc_readl(SRAMROM_SEC_ADDR2)
+	);
+	INFO("[Post] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+		devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+		devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+	);
+
+}
+
+void devapc_init(void)
+{
+	uint64_t sramrom_vio_sta;
+	uint64_t sramrom_vio_addr;
+	int i;
+
+	INFO("%s...\n", __func__);
+	/* Enable Devapc */
+	/* Lock DEVAPC_AO/DEVAPC_CON to secure access only */
+	devapc_writel(0x80000001, DEVAPC_INFRA_APC_CON);
+	devapc_writel(0x1, INFRACFG_AO_DEVAPC_CON);
+	devapc_writel(0x80000000, DEVAPC_PD_INFRA_APC_CON);
+
+	INFO("(Post) DEVAPC_INFRA_APC_CON:0x%x\n",
+			devapc_readl(DEVAPC_INFRA_APC_CON));
+	INFO("(Post) INFRACFG_AO_DEVAPC_CON:0x%x\n",
+			devapc_readl(INFRACFG_AO_DEVAPC_CON));
+	INFO("(Post) DEVAPC_PD_INFRA_APC_CON:0x%x\n",
+			devapc_readl(DEVAPC_PD_INFRA_APC_CON));
+
+	/* clr sramrom vio if any */
+	handle_sramrom_vio(&sramrom_vio_sta, &sramrom_vio_addr);
+
+//	print_vio_mask_sta();
+	if (!vio_shift_sta_handler())
+		INFO("no violation happened before init\n");
+
+	/* clear vio_status & unmask vio_mask */
+	INFO("clear vio_staus & unmask modules\n");
+	for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+		clear_infra_vio_status(i);
+		unmask_infra_module(i);
+	}
+
+//	print_vio_mask_sta();
+
+	devapc_set_dom();
+#if CFG_DEVAPC_SET_PROTECT
+	devapc_set_apc();
+#else
+	INFO("Skip to set APC\n");
+#endif
+	sramrom_set_apc();
+
+	INFO("%s done\n", __func__);
+}
+
+/* It should clear SRAMROM vio before clear DEVAPC vio */
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr)
+{
+	int sramrom = -1;
+
+	if (devapc_readl(SRAMROM_SEC_VIO_STA) & SRAM_SEC_VIO_BIT) {		/* SRAM part */
+		INFO("SRAM violation is triggered\n");
+
+		sramrom = 1;
+		*vio_sta = devapc_readl(SRAMROM_SEC_VIO_STA);
+		*vio_addr = devapc_readl(SRAMROM_SEC_VIO_ADDR);
+
+		INFO("(Pre) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			(uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+		devapc_writel(0x1, SRAMROM_SEC_VIO_CLR);
+
+		INFO("(Post) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			devapc_readl(SRAMROM_SEC_VIO_STA),
+			devapc_readl(SRAMROM_SEC_VIO_ADDR));
+
+	} else if (devapc_readl(SRAMROM_ROM_SEC_VIO_STA) & ROM_SEC_VIO_BIT) {	/* ROM part */
+		INFO("ROM violation is triggered\n");
+
+		sramrom = 0;
+		*vio_sta = devapc_readl(SRAMROM_ROM_SEC_VIO_STA);
+		*vio_addr = devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR);
+
+		INFO("(Pre) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			(uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+		devapc_writel(0x1, SRAMROM_ROM_SEC_VIO_CLR);
+
+		INFO("(Post) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+			devapc_readl(SRAMROM_ROM_SEC_VIO_STA),
+			devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR));
+	} else {
+		INFO("SRAMROM violation is not triggered\n");
+	}
+
+	return sramrom;
+}
+
+unsigned int devapc_perm_get(int type, int domain, int index)
+{
+	int d = domain; /* domain id */
+	int reg = index / MOD_NO_IN_1_DEVAPC; /* register num */
+	unsigned int value = 0xdeadbeaf;
+
+	INFO("[INFRA] default value is 0x%x\n", value);
+	if (type == E_DAPC_INFRA_SLAVE) {
+		if (index > SLAVE_INFRA_MAX_INDEX)
+			INFO("[INFRA] slave index out of range\n");
+		else if (d > E_DOMAIN_15)
+			INFO("[INFRA] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS0_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[INFRA] SYS0_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else if (type == E_DAPC_SRAMROM_SLAVE) {
+		if (index > SLAVE_SRAMROM_MAX_INDEX)
+			INFO("[SRAMROM] slave index out of range\n");
+		else if (d > E_DOMAIN_8)
+			INFO("[SRAMROM] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS1_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[SRAMROM] SYS1_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else if (type == E_DAPC_MD_SLAVE) {
+		if (index > SLAVE_MD_MAX_INDEX)
+			INFO("[MD] slave index out of range\n");
+		else if (d > E_DOMAIN_3)
+			INFO("[MD] domain id out of range\n");
+		else {
+			value = devapc_readl(DEVAPC_SYS2_D0_APC_0 + 0x40 * d + reg * 4);
+			INFO("[MD] SYS2_D%d_APC_%d = 0x%x\n", d, reg, value);
+		}
+	} else {
+		dump_infra_apc();
+		dump_sramrom_apc();
+		dump_md_apc();
+
+//		INFO("%s: dump PMS(DEVAPC) reg:\n", __func__);
+//		dump_pms_info();
+	}
+
+	return value;
+}
+
+void tz_dapc_sec_init(void)
+{
+	//nothing
+}
+
+void tz_dapc_sec_postinit(void)
+{
+	//nothing
+}
+
+void tz_apc_common_init(void)
+{
+	devapc_init();
+}
+
+void tz_apc_common_postinit(void)
+{
+	//nothing
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/main.c b/src/bsp/trustzone/teeloader/mt2735/src/main.c
new file mode 100644
index 0000000..0be38d0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/main.c
@@ -0,0 +1,84 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#include "platform.h"
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg, unsigned long boot_reason)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = ATF_INIT_ARG_ADDR;
+    atf_arg->boot_reason = boot_reason;
+}
+
+int teeloader_main(unsigned long bl33_addr, unsigned long boot_reason)
+{
+    u32 tee_addr = 0;
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+
+    // Force to 32-bit
+    boot_reason &= 0xffffffff;
+    set_atf_parameters(atf_arg, boot_reason);
+
+    /* marked because no device APC support */
+	//device_APC_dom_setup();
+    trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+    tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+    /* set tee entry address */
+    tee_set_entry(tee_addr);
+    tee_set_hwuid();
+
+    trustzone_post_init();
+    trustzone_jump(BL31, BL33, tee_addr);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/print.c b/src/bsp/trustzone/teeloader/mt2735/src/print.c
new file mode 100644
index 0000000..34622c7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/security/seclib.c b/src/bsp/trustzone/teeloader/mt2735/src/security/seclib.c
new file mode 100644
index 0000000..59419d8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/security/seclib.c
@@ -0,0 +1,100 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "hacc_export.h"
+#include "string.h"
+#include "print.h"
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#define HRID                            (0x10206140UL)
+#define SOC_DATA                        (0x08000000UL)
+#define HW_DATA_SIZE                    (0x4UL)
+
+#define MOD "[SECLIB]"
+
+int seclib_get_key(u32 hwaddr, u8 *key, u32 key_size, int index)
+{
+    u32 hwdata[HW_DATA_SIZE] = {0};
+    int i = 0;
+
+    if (key_size != sizeof(hwdata))
+    {
+        return -1;
+    }
+    for (i = 0; i < HW_DATA_SIZE; i++)
+    {
+        hwdata[i] = READ_REGISTER_UINT32(hwaddr + (i * sizeof(u32)));
+    }
+    if (0 != seclib_get_data_key((u8 *)hwdata, key_size, (u8 *)key, index))
+    {
+        return -1;
+    }
+    DBG_MSG("%s HWDATA : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, hwdata[0], hwdata[1], hwdata[2], hwdata[3]);
+
+    return 0;
+}
+
+int seclib_get_hrid_key(u32 *key, u32 key_size)
+{
+    u32 hrkey[HW_DATA_SIZE] = {0};
+
+    if (0 != seclib_get_key(HRID, (u8 *)hrkey, sizeof(hrkey), 1))
+    {
+        return -1;
+    }
+    key[0]=hrkey[0];
+    key[1]=hrkey[1];
+
+    return 0;
+}
+
+int seclib_get_hwid_key(u8 *key, u32 key_size)
+{
+    return seclib_get_key(SOC_DATA, key, key_size, 2);
+}
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..d7e006b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_emi_mpu.c
@@ -0,0 +1,267 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+
+    if (end <= start)
+    {
+        DBG_MSG("%s, Invalid address! End address should larger than start address.\n", MOD);
+        return -1;
+    }
+
+
+    if((end >> 31) && !(start >> 31))
+    {
+        DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n", MOD);
+        return -1;
+    }
+
+    if ((readl(PERIAXI_BUS_CTL3) & PERISYS_4G_SUPPORT) == 0)
+    {
+        start = start - EMI_PHY_OFFSET;
+        end = end - EMI_PHY_OFFSET;
+        DBG_MSG("%s, MPU 2GB mode.\n", MOD);
+    }
+    else
+        DBG_MSG("%s, MPU 4GB mode.\n", MOD);
+
+    /*Address 64KB alignment*/
+    start = start >> 16;
+    end = end >> 16;
+
+    switch (region) {
+    case 0:
+        writel(0, EMI_MPU_APC0);
+        writel(start, EMI_MPU_SA0);
+        writel(end, EMI_MPU_EA0);
+        writel(access_permission, EMI_MPU_APC0);
+        break;
+
+    case 1:
+        writel(0, EMI_MPU_APC1);
+        writel(start, EMI_MPU_SA1);
+        writel(end, EMI_MPU_EA1);
+        writel(access_permission, EMI_MPU_APC1);
+        break;
+
+    case 2:
+        writel(0, EMI_MPU_APC2);
+        writel(start, EMI_MPU_SA2);
+        writel(end, EMI_MPU_EA2);
+        writel(access_permission, EMI_MPU_APC2);
+        break;
+
+    case 3:
+        writel(0, EMI_MPU_APC3);
+        writel(start, EMI_MPU_SA3);
+        writel(end, EMI_MPU_EA3);
+        writel(access_permission, EMI_MPU_APC3);
+        break;
+
+    case 4:
+        writel(0, EMI_MPU_APC4);
+        writel(start, EMI_MPU_SA4);
+        writel(end, EMI_MPU_EA4);
+        writel(access_permission, EMI_MPU_APC4);
+        break;
+
+    case 5:
+        writel(0, EMI_MPU_APC5);
+        writel(start, EMI_MPU_SA5);
+        writel(end, EMI_MPU_EA5);
+        writel(access_permission, EMI_MPU_APC5);
+        break;
+
+    case 6:
+        writel(0, EMI_MPU_APC6);
+        writel(start, EMI_MPU_SA6);
+        writel(end, EMI_MPU_EA6);
+        writel(access_permission, EMI_MPU_APC6);
+        break;
+
+    case 7:
+        writel(0, EMI_MPU_APC7);
+        writel(start, EMI_MPU_SA7);
+        writel(end, EMI_MPU_EA7);
+        writel(access_permission, EMI_MPU_APC7);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+/* sample code for scenario as below: */
+/* mpu region2: 0x40000000 - 0xe0000000 (2.5GB) is secure RW and non-secure RW for domain 0, 3.*/
+/* mpu region3: 0xe0000000 - 0xe0080000 (512K) is secure RW and non-secure RW for domain 0, 2, 3.*/
+/* mpu region4: 0xe0080000 - 0xe0880000 (8M) is secure and non-secure RW for domain 2, 3.*/
+/* mpu region5: 0xe0880000 - 0xec880000 (384M) is secure RW and non-secure RW for domain 1, 2, 3.*/
+/* mpu region6: 0xec880000 - 0xec8e0000 (384K) is secure RW and non-secure RW for domain 0, 1, 3.*/
+/* mpu region7: 0xec8e0000 - 0xf48e0000 (128M) is secure RW for domain 0, 3.*/
+
+void tz_emi_mpu_init_2(void)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+
+    /*region2 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0x40000000,               /*START_ADDR*/
+                                            0xe0000000,           /*END_ADDR*/
+                                            2,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region3 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xe0000000,               /*START_ADDR*/
+                                            0xe0080000,           /*END_ADDR*/
+                                            3,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region4 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0080000,               /*START_ADDR*/
+                                            0xe0880000,           /*END_ADDR*/
+                                            4,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region5 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xe0880000,               /*START_ADDR*/
+                                            0xec880000,           /*END_ADDR*/
+                                            5,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region6 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW);
+    ret += emi_mpu_set_region_protection(0xec880000,               /*START_ADDR*/
+                                            0xec8e0000,           /*END_ADDR*/
+                                            6,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    /*region7 mpu*/
+    sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+        TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+    ret += emi_mpu_set_region_protection(0xec8e0000,               /*START_ADDR*/
+                                            0xf48e0000,           /*END_ADDR*/
+                                            7,                    /*region*/
+                                            sec_mem_mpu_attr);
+
+    if(ret)
+        DBG_MSG("%s MPU error!!\n", MOD);
+
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch(mpu_region)
+    {
+        case SECURE_OS_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        case ATF_MPU_REGION_ID:
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+                TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+            break;
+
+        default:
+            DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+            return;
+    }
+
+    DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,  /*START_ADDR*/
+                                        sec_mem_phy_end,    /*END_ADDR*/
+                                        mpu_region,         /*region*/
+                                        sec_mem_mpu_attr);
+
+    if(ret)
+    {
+        DBG_MSG("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_init.c
new file mode 100644
index 0000000..fe34154
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_init.c
@@ -0,0 +1,243 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "seclib.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "device_apc.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+
+/**************************************************************************
+ *  DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+/**************************************************************************
+ *  MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000U)  //4K Alignment
+#define TEE_ENABLE_VERIFY (1U)
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ *  INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+
+/**************************************************************************
+ *  INTERNAL FUNCTIONS
+ **************************************************************************/
+
+static u64 trustzone_get_atf_init_param_addr(void)
+{
+    return ATF_INIT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+
+void tee_set_entry(u32 addr)
+{
+    tee_entry_addr = addr;
+
+    DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(void)
+{
+    atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[0], g_hwuid[1], g_hwuid[2], g_hwuid[3]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[4], g_hwuid[5], g_hwuid[6], g_hwuid[7]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[8], g_hwuid[9], g_hwuid[10], g_hwuid[11]);
+    DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[12], g_hwuid[13], g_hwuid[14], g_hwuid[15]);
+    memcpy(teearg->hwuid, g_hwuid, sizeof(g_hwuid));
+    g_hwuid_initialized = 1;
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+    int ret = 0;
+
+    if (!g_hwuid_initialized)
+    {
+        ret = seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+        if(ret != 0)
+            return ret;
+    }
+
+    memcpy(id, g_hwuid, size);
+
+    return ret;
+}
+
+static void tee_sec_config(void)
+{
+    u32 atf_entry_addr = BL31;
+
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    /* memory protection for TEE */
+    u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+
+    tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+    DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+        secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+
+    /* memory protection for ATF */
+    atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+    u32 atf_end_addr = atf_entry_addr + BL31_SIZE - 1;
+
+    DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+    tz_sec_mem_init(atf_entry_addr, atf_end_addr, ATF_MPU_REGION_ID);
+    DBG_MSG("%s set ATF memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+        atf_end_addr, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+#if CFG_ATF_LOG_SUPPORT
+    atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#endif
+
+#if CFG_TEE_SUPPORT
+    tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+
+#if 0 //KH workaround for bringup
+    tz_apc_common_init();
+#endif
+}
+
+void trustzone_post_init(void)
+{
+    atf_arg_t_ptr atf_init_arg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+    atf_init_arg->atf_magic = ATF_BOOTCFG_MAGIC;
+    atf_init_arg->tee_entry = tee_entry_addr;
+    atf_init_arg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+    seclib_get_hrid_key(atf_init_arg->HRID, sizeof(atf_init_arg->HRID));
+    atf_init_arg->atf_log_port = 0x11002000;
+    atf_init_arg->atf_log_baudrate = 0xE1000;
+    atf_init_arg->atf_irq_num = 267; /* reserve SPI ID for ATF log */
+    atf_init_arg->devinfo[0] = 0;
+    atf_init_arg->devinfo[1] = 0;
+    atf_init_arg->devinfo[2] = 0xFFFFFFFF;
+    atf_init_arg->devinfo[3] = 0xFFFFFFFF;
+
+    DBG_MSG("%s HRID[0] : 0x%x\n", MOD, atf_init_arg->HRID[0]);
+    DBG_MSG("%s HRID[1] : 0x%x\n", MOD, atf_init_arg->HRID[1]);
+    DBG_MSG("%s atf_log_port : 0x%x\n", MOD, atf_init_arg->atf_log_port);
+    DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, atf_init_arg->atf_log_baudrate);
+    DBG_MSG("%s atf_irq_num : %d\n", MOD, atf_init_arg->atf_irq_num);
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+    tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        tee_secmem_size);
+    tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+        CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+    atf_init_arg->tee_support = 1;
+#else
+    atf_init_arg->tee_support = 0;
+#endif
+
+#if CFG_ATF_LOG_SUPPORT
+    atf_init_arg->atf_log_buf_start = atf_log_buf_start;
+    atf_init_arg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+    atf_init_arg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+    atf_init_arg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+    atf_init_arg->atf_log_buf_start = 0;
+    atf_init_arg->atf_log_buf_size = 0;
+    atf_init_arg->atf_aee_debug_buf_start = 0;
+    atf_init_arg->atf_aee_debug_buf_size = 0;
+#endif
+    DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, atf_init_arg->atf_log_buf_start);
+    DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, atf_init_arg->atf_log_buf_size);
+    DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_start);
+    DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry = (void *)addr;
+
+    /* EMI MPU support */
+    tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+    DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+    DBG_MSG("%s Jump to ATF, then jump to bl33 0x%x\n", MOD, arg1);
+#endif
+
+    atf_entry = (jump_atf)BL31;
+    DBG_MSG("[teeloader] teeloader jump to atf!\n");
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..dd49816
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_sec_cfg.c
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+    tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_tbase.c
new file mode 100644
index 0000000..8e14488
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/security/tz_tbase.c
@@ -0,0 +1,149 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+
+#define MOD "[TZ_TBASE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ *  EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+    u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+    int ret = 0;
+    sec_mem_arg_t sec_mem_arg;
+    u8 hwuid[16];
+    unsigned char i, *ptmp, tmpbuf;
+
+    ret = tee_get_hwuid(hwuid, 16);
+    if (ret)
+        DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+    /* Prepare secure memory configuration parameters */
+    sec_mem_arg.magic = SEC_MEM_MAGIC;
+    sec_mem_arg.version = SEC_MEM_VERSION;
+    sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+    sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+    sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+    sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+    sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+    /* dummy function because of no seclib support */
+    seclib_get_msg_auth_key((unsigned char *) sec_mem_arg.msg_auth_key, 32);
+    /*ptmp = (unsigned char *)sec_mem_arg.msg_auth_key;
+    for(i=0;i<32/2;i++) {
+        tmpbuf = ptmp[i];
+        ptmp[i] = ptmp[31-i];
+        ptmp[31-i] = tmpbuf;
+    }*/
+    sec_mem_arg.rpmb_size = 128*1024; /* 128kx1: minimum size */
+    sec_mem_arg.emmc_rel_wr_sec_c = 1;
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+    sec_mem_arg.secmem_obfuscation = 1;
+#else
+    sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+    DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+    DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+    DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+    DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+    DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+    DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+    DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+    DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+    DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+    DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+    DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+    DBG_MSG("%s emmc_rel_wr_sec_c: 0x%x\n", MOD, sec_mem_arg.emmc_rel_wr_sec_c);
+
+    memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+    u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+    tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+    /* Prepare TEE boot parameters */
+    teearg->magic                 = TBASE_BOOTCFG_MAGIC;             /* Trustonic's TEE magic number */
+    teearg->length                = sizeof(tee_arg_t);               /* Trustonic's TEE argument block size */
+    //teearg->version               = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+    teearg->dRamBase              = dram_base;                       /* DRAM base address */
+    teearg->dRamSize              = dram_size;                       /* Full DRAM size */
+    teearg->secDRamBase           = tee_entry;                       /* Secure DRAM base address */
+    teearg->secDRamSize           = tbase_sec_dram_size;             /* Secure DRAM size */
+    teearg->secIRamBase           = TEE_SECURE_ISRAM_ADDR;           /* Secure SRAM base address */
+    teearg->secIRamSize           = TEE_SECURE_ISRAM_SIZE;           /* Secure SRAM size */
+    //teearg->conf_mair_el3         = read_mair_el3();
+    //teearg->MSMPteCount           = totalPages;
+    //teearg->MSMBase               = (u64)registerFileL2;
+    //teearg->gic_distributor_base  = TBASE_GIC_DIST_BASE;
+    //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+    //teearg->gic_version           = TBASE_GIC_VERSION;
+    teearg->total_number_spi      = 256;                      /* Support total 256 SPIs */
+    teearg->ssiq_number           = 247;                      /* reserve SPI ID 266 for <t-base */
+    //teearg->flags                 = TBASE_MONITOR_FLAGS;
+
+    DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+    DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+    DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+    DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+    DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+    DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+    DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+    DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+    DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+    DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/start.s b/src/bsp/trustzone/teeloader/mt2735/src/start.s
new file mode 100644
index 0000000..5875d41
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/start.s
@@ -0,0 +1,72 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*
+ * Register use:
+ *  x9-x10  Scratch
+ */
+tmp                     .req x9
+tmp2                    .req x10
+
+.section .text.start
+
+.globl _start
+_start:
+/*
+ * Note: MT2735 BL2 is built as aarch32. Tee loader is built as aarch64.
+ * CPU context initialization code is required. 0x240000 is the end of l2$. (not good writing...)
+ */
+    mrs     tmp, CurrentEL
+    cmp     tmp, #(0b11 << 2)
+    b.ne    .Lsetup_el2_or_el3_stack
+
+    /* el3 set secure timer */
+    ldr     tmp2, =13000000
+    msr     cntfrq_el0, tmp2
+
+    /* el3 enable smp bit */
+    /* ToDo: KH will search the setting on CA55*/
+//    mrs     tmp2, s3_1_c15_c2_1
+//    orr     tmp2, tmp, #(1<<6)
+//    msr     s3_1_c15_c2_1, tmp2
+
+.Lsetup_el2_or_el3_stack:
+    /* set el2 or el3 stack pointer */
+    ldr     tmp2, =0x240000
+    mov     sp, tmp2
+
+    b teeloader_main
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/string.c b/src/bsp/trustzone/teeloader/mt2735/src/string.c
new file mode 100644
index 0000000..d916f3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+    const char *sc;
+
+    for (sc = s; *sc != '\0'; ++sc)
+    {
+    }
+    return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+    signed char __res;
+
+    while (1)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+    signed char __res = 0;
+
+    while (count)
+    {
+        if ((__res = *cs - *ct++) != 0 || !*cs++)
+            break;
+        count--;
+    }
+    return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+    char *xs = s;
+
+    while (count--)
+        *xs++ = c;
+    return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+    char *tmp = dest;
+    const char *s = src;
+
+    while (count--)
+        *tmp++ = *s++;
+    return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+    const unsigned char *su1, *su2;
+    int res = 0;
+
+    for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+        if ((res = *su1 - *su2) != 0)
+            break;
+    return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+	char *_dst = dst;
+	const char *_src = src;
+
+	if (dst == src)
+		return dst;
+
+	if (dst < src)
+		return memcpy(dst, src, count);
+
+	_dst += count;
+	_src += count;
+	while(count--)
+		*--_dst = *--_src;
+
+	return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2735/src/uart.c b/src/bsp/trustzone/teeloader/mt2735/src/uart.c
new file mode 100644
index 0000000..e93d4dc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2735/tllink.lds b/src/bsp/trustzone/teeloader/mt2735/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2735/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2735/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2735/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt6771/Makefile b/src/bsp/trustzone/teeloader/mt6771/Makefile
new file mode 100644
index 0000000..4f5705d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/Makefile
@@ -0,0 +1,54 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_dapc.c \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/print.h b/src/bsp/trustzone/teeloader/mt6771/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/typedefs.h b/src/bsp/trustzone/teeloader/mt6771/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/tz_dapc.h b/src/bsp/trustzone/teeloader/mt6771/include/tz_dapc.h
new file mode 100644
index 0000000..257989d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/tz_dapc.h
@@ -0,0 +1,169 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+#define DEVAPC_AO_INFRA_BASE        0x1000E000  // for INFRA/PERI
+#define DEVAPC_AO_MD_BASE           0x10019000  // for MD
+#define DEVAPC_AO_MM_BASE           0x1001C000  // for MM
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+/* Device APC AO for INFRA/PERI */
+
+#define DEVAPC_AO_INFRA_MAS_DOM_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A00))
+#define DEVAPC_AO_INFRA_MAS_DOM_1   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A04))
+#define DEVAPC_AO_INFRA_MAS_DOM_2   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A08))
+#define DEVAPC_AO_INFRA_MAS_DOM_3   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A0C))
+
+#define DEVAPC_AO_INFRA_MAS_SEC_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0B00))
+
+#define DEVAPC_AO_INFRA_DOM_RMP_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0D00))
+#define DEVAPC_AO_INFRA_DOM_RMP_1   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0D04))
+
+#define DEVAPC_AO_INFRA_APC_CON     ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0F00))
+
+/* ---------------------------------------------------------------------------------------- */
+/* Device APC AO for MD */
+
+#define DEVAPC_AO_MD_DOM_RMP_0      ((volatile unsigned int*)(DEVAPC_AO_MD_BASE+0x0D00))
+
+#define DEVAPC_AO_MD_APC_CON        ((volatile unsigned int*)(DEVAPC_AO_MD_BASE+0x0F00))
+
+/* ---------------------------------------------------------------------------------------- */
+/* Device APC AO for MM */
+
+#define DEVAPC_AO_MM_DOM_RMP_0      ((volatile unsigned int*)(DEVAPC_AO_MM_BASE+0x0D00))
+
+#define DEVAPC_AO_MM_APC_CON        ((volatile unsigned int*)(DEVAPC_AO_MM_BASE+0x0F00))
+
+/* ---------------------------------------------------------------------------------------- */
+
+#define MOD_NO_IN_1_DEVAPC          16
+#define MASTER_NUM_INFRA            30
+
+typedef enum {
+    NON_SECURE_TRAN = 0,
+    SECURE_TRAN
+} E_TRANSACTION;
+
+typedef enum {
+    MASTER_TYPE_INFRA = 0,
+} E_MASTER_TYPE;
+
+typedef enum {
+    DOMAIN_0 = 0,
+    DOMAIN_1,
+    DOMAIN_2,
+    DOMAIN_3,
+    DOMAIN_4,
+    DOMAIN_5,
+    DOMAIN_6,
+    DOMAIN_7,
+    DOMAIN_8,
+    DOMAIN_9,
+    DOMAIN_10,
+    DOMAIN_11,
+    DOMAIN_12,
+    DOMAIN_13,
+    DOMAIN_14,
+    DOMAIN_15,
+    DOMAIN_MAX,
+} E_DOMAIN;
+
+/* Masks for Domain Control for DEVAPC */
+#define CONN2AP        (0xF << 24)
+
+
+
+static inline unsigned int uffs(unsigned int x)
+{
+    unsigned int r = 1;
+
+    if (!x)
+        return 0;
+    if (!(x & 0xffff)) {
+        x >>= 16;
+        r += 16;
+    }
+    if (!(x & 0xff)) {
+        x >>= 8;
+        r += 8;
+    }
+    if (!(x & 0xf)) {
+        x >>= 4;
+        r += 4;
+    }
+    if (!(x & 3)) {
+        x >>= 2;
+        r += 2;
+    }
+    if (!(x & 1)) {
+        x >>= 1;
+        r += 1;
+    }
+    return r;
+}
+
+#define reg_read32(reg)        (*(volatile u32* const)(reg))
+#define reg_write32(reg,val)   ((*(volatile u32* const)(reg)) = (val))
+
+#define reg_set_bits(reg,bs)   ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs)   ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        tv &= ~(field); \
+        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+        reg_write32(reg,tv); \
+    } while(0)
+
+#define reg_get_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+    } while(0)
+
+
+void tz_dapc_sec_init(void);
+void tz_dapc_sec_postinit(void);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_mpu.h
new file mode 100644
index 0000000..03964fd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_mpu.h
@@ -0,0 +1,61 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET       (0x40000000UL)
+//#define EIGHT_DOMAIN
+
+#define NO_PROTECTION       (0)
+#define SEC_RW              (1)
+#define SEC_RW_NSEC_R       (2)
+#define SEC_RW_NSEC_W       (3)
+#define SEC_R_NSEC_R        (4)
+#define FORBIDDEN           (5)
+#define SEC_R_NSEC_RW       (6)
+
+#define SECURE_OS_MPU_REGION_ID    (0)
+#define ATF_MPU_REGION_ID          (1)
+
+#ifdef EIGHT_DOMAIN
+#define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) (((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) |((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#else
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#endif
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_reg.h
new file mode 100644
index 0000000..45eea66
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE                (0x10226000)
+
+#define EMI_MPU_SA0                 ((P_U32)(EMI_MPU_BASE+0x100))  /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1                 ((P_U32)(EMI_MPU_BASE+0x104))  /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2                 ((P_U32)(EMI_MPU_BASE+0x108))  /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3                 ((P_U32)(EMI_MPU_BASE+0x10C))  /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4                 ((P_U32)(EMI_MPU_BASE+0x110))  /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5                 ((P_U32)(EMI_MPU_BASE+0x114))  /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6                 ((P_U32)(EMI_MPU_BASE+0x118))  /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7                 ((P_U32)(EMI_MPU_BASE+0x11C))  /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0                 ((P_U32)(EMI_MPU_BASE+0x200))  /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1                 ((P_U32)(EMI_MPU_BASE+0x204))  /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2                 ((P_U32)(EMI_MPU_BASE+0x208))  /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3                 ((P_U32)(EMI_MPU_BASE+0x20C))  /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4                 ((P_U32)(EMI_MPU_BASE+0x210))  /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5                 ((P_U32)(EMI_MPU_BASE+0x214))  /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6                 ((P_U32)(EMI_MPU_BASE+0x218))  /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7                 ((P_U32)(EMI_MPU_BASE+0x21C))  /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0                ((P_U32)(EMI_MPU_BASE+0x300))  /* EMI MPU APC 0 */
+#define EMI_MPU_APC1                ((P_U32)(EMI_MPU_BASE+0x304))  /* EMI MPU APC 1 */
+#define EMI_MPU_APC2                ((P_U32)(EMI_MPU_BASE+0x308))  /* EMI MPU APC 2 */
+#define EMI_MPU_APC3                ((P_U32)(EMI_MPU_BASE+0x30C))  /* EMI MPU APC 3 */
+#define EMI_MPU_APC4                ((P_U32)(EMI_MPU_BASE+0x310))  /* EMI MPU APC 4 */
+#define EMI_MPU_APC5                ((P_U32)(EMI_MPU_BASE+0x314))  /* EMI MPU APC 5 */
+#define EMI_MPU_APC6                ((P_U32)(EMI_MPU_BASE+0x318))  /* EMI MPU APC 6 */
+#define EMI_MPU_APC7                ((P_U32)(EMI_MPU_BASE+0x31C))  /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0             ((P_U32)(EMI_MPU_BASE+0x800))  /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1             ((P_U32)(EMI_MPU_BASE+0x804))  /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2             ((P_U32)(EMI_MPU_BASE+0x808))  /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3             ((P_U32)(EMI_MPU_BASE+0x80C))  /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4             ((P_U32)(EMI_MPU_BASE+0x810))  /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5             ((P_U32)(EMI_MPU_BASE+0x814))  /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6             ((P_U32)(EMI_MPU_BASE+0x818))  /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7             ((P_U32)(EMI_MPU_BASE+0x81C))  /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0             ((P_U32)(EMI_MPU_BASE+0x900))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1             ((P_U32)(EMI_MPU_BASE+0x904))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2             ((P_U32)(EMI_MPU_BASE+0x908))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3             ((P_U32)(EMI_MPU_BASE+0x90C))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4             ((P_U32)(EMI_MPU_BASE+0x910))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5             ((P_U32)(EMI_MPU_BASE+0x914))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6             ((P_U32)(EMI_MPU_BASE+0x918))  /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7             ((P_U32)(EMI_MPU_BASE+0x91C))  /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/tz_init.h b/src/bsp/trustzone/teeloader/mt6771/include/tz_init.h
new file mode 100644
index 0000000..bba9e9e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/tz_init.h
@@ -0,0 +1,84 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TZ_INIT_H__
+#define __TZ_INIT_H__
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x41e00000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct atf_arg_t{
+	unsigned int atf_magic;
+	unsigned int tee_support;
+	unsigned int tee_entry;
+	unsigned int tee_boot_arg_addr;
+	unsigned int hwuid[4];     // HW Unique id for t-base used
+	unsigned int atf_hrid_size; // Check this atf_hrid_size to read from HRID array
+	unsigned int HRID[8];      // HW random id for t-base used
+	unsigned int atf_log_port;
+	unsigned int atf_log_baudrate;
+	unsigned int atf_log_buf_start;
+	unsigned int atf_log_buf_size;
+	unsigned int atf_irq_num;
+	unsigned int devinfo[DEVINFO_SIZE];
+	unsigned int atf_aee_debug_buf_start;
+	unsigned int atf_aee_debug_buf_size;
+	unsigned int msg_fde_key[4]; /* size of message auth key is 16bytes(128 bits) */
+#if CFG_TEE_SUPPORT
+	unsigned int tee_rpmb_size;
+#endif
+}atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* __TZ_INIT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt6771/include/uart.h b/src/bsp/trustzone/teeloader/mt6771/include/uart.h
new file mode 100644
index 0000000..8efeeca
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART0_BASE         (IO_PHYS + 0x01002000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_dapc.c b/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_dapc.c
new file mode 100644
index 0000000..4c16464
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_dapc.c
@@ -0,0 +1,153 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES                                                          */
+/*=======================================================================*/
+#include <tz_dapc.h>
+#include <print.h>
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE       (0x00000000U)      /* No event */
+#define DBG_EVT_ERR        (0x00000001U)      /* ERR related event */
+#define DBG_EVT_DOM        (0x00000002U)      /* DOM related event */
+
+#define DBG_EVT_ALL        (0xffffffffU)
+
+#define DBG_EVT_MASK       (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+    do {    \
+        if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+            tl_printf(fmt, ##args); \
+        } \
+    } while(0)
+
+#define MSG_FUNC_ENTRY(f)   MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{} while(0)
+#define MSG_FUNC_ENTRY(f)      do{} while(0)
+#endif
+
+/*=======================================================================*/
+/* STATIC FUNCTIONS                                                      */
+/*=======================================================================*/
+static void tz_dapc_set_master_transaction(E_MASTER_TYPE master_type, unsigned int master_index, E_TRANSACTION permisssion_control)
+{
+    volatile unsigned int *base = 0;
+    unsigned int master_register_index = 0;
+    unsigned int master_set_index = 0;
+
+    master_register_index = master_index / (MOD_NO_IN_1_DEVAPC * 2);
+    master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+    if (master_type == MASTER_TYPE_INFRA && master_index < MASTER_NUM_INFRA) {
+        base = (volatile unsigned int *)((unsigned int)DEVAPC_AO_INFRA_MAS_SEC_0 + master_register_index * 4);
+    } else {
+        return;
+    }
+
+    if (base != 0) {
+        reg_set_field(base, 0x1 << master_set_index, permisssion_control);
+    }
+}
+
+static void DAPC_dom_init(void)
+{
+    /* Set master domain here if needed */
+
+    /* Set CONN2AP to DOMAIN2(CONN) */
+    reg_set_field(DEVAPC_AO_INFRA_MAS_DOM_2, CONN2AP, DOMAIN_2);
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Master Domain Setup Infra (0x%x), (0x%x), (0x%x), (0x%x)\n",
+        reg_read32(DEVAPC_AO_INFRA_MAS_DOM_0), reg_read32(DEVAPC_AO_INFRA_MAS_DOM_1),
+        reg_read32(DEVAPC_AO_INFRA_MAS_DOM_2), reg_read32(DEVAPC_AO_INFRA_MAS_DOM_3));
+#endif
+}
+
+static void DAPC_trans_init(void)
+{
+    /* Set master transaction here if needed */
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Master Transaction Setup (0x%x)\n", reg_read32(DEVAPC_AO_INFRA_MAS_SEC_0));
+#endif
+
+}
+
+static void DAPC_slave_perm_init(void)
+{
+    /* Set slave permissions here if needed
+     * Default is NO_PROTECTION */
+}
+
+static void tz_dapc_default_setting(void)
+{
+    /* Lock DAPC to secure access only  && unmask debug bit && clear VIO status */
+    reg_write32(DEVAPC_AO_INFRA_APC_CON, 0x80000001);
+    reg_write32(DEVAPC_AO_MD_APC_CON, 0x80000001);
+    reg_write32(DEVAPC_AO_MM_APC_CON, 0x80000001);
+
+    /* Set domain of masters */
+    DAPC_dom_init();
+
+    /* Set the transaction type of masters */
+    //DAPC_trans_init();
+
+    /* Set the access permission of slaves in domain 0 */
+    //DAPC_slave_perm_init();
+}
+
+
+/*=======================================================================*/
+/* INIT FUNCTIONS                                                        */
+/*=======================================================================*/
+
+void tz_dapc_sec_init(void)
+{
+    /* do initial settings */
+    tz_dapc_default_setting();
+}
+
+void tz_dapc_sec_postinit(void)
+{
+}
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..5912860
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,202 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (*(volatile unsigned int*)(addr))
+#define writel(b,addr) (*(volatile unsigned int*)(addr) = b)
+#define IOMEM(reg) (reg)
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {tl_printf(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {tl_printf(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {tl_printf(str, ##__VA_ARGS__);} while(0)
+#endif
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+
+    if (end <= start)
+    {
+        DBG_MSG("%s, Invalid address! End address should larger than start address.\n");
+        return -1;
+    }
+
+
+    if((end >> 31) && !(start >> 31))
+    {
+        DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n");
+        return -1;
+    }
+
+    start = start - EMI_PHY_OFFSET;
+    end = end - EMI_PHY_OFFSET;
+
+
+    /*Address 64KB alignment*/
+    start = start >> 16;
+    end = end >> 16;
+
+    switch (region) {
+    case 0:
+        writel(0, EMI_MPU_APC0);
+        writel(start, EMI_MPU_SA0);
+        writel(end, EMI_MPU_EA0);
+        writel(access_permission, EMI_MPU_APC0);
+        break;
+
+    case 1:
+        writel(0, EMI_MPU_APC1);
+        writel(start, EMI_MPU_SA1);
+        writel(end, EMI_MPU_EA1);
+        writel(access_permission, EMI_MPU_APC1);
+        break;
+
+    case 2:
+        writel(0, EMI_MPU_APC2);
+        writel(start, EMI_MPU_SA2);
+        writel(end, EMI_MPU_EA2);
+        writel(access_permission, EMI_MPU_APC2);
+        break;
+
+    case 3:
+        writel(0, EMI_MPU_APC3);
+        writel(start, EMI_MPU_SA3);
+        writel(end, EMI_MPU_EA3);
+        writel(access_permission, EMI_MPU_APC3);
+        break;
+
+    case 4:
+        writel(0, EMI_MPU_APC4);
+        writel(start, EMI_MPU_SA4);
+        writel(end, EMI_MPU_EA4);
+        writel(access_permission, EMI_MPU_APC4);
+        break;
+
+    case 5:
+        writel(0, EMI_MPU_APC5);
+        writel(start, EMI_MPU_SA5);
+        writel(end, EMI_MPU_EA5);
+        writel(access_permission, EMI_MPU_APC5);
+        break;
+
+    case 6:
+        writel(0, EMI_MPU_APC6);
+        writel(start, EMI_MPU_SA6);
+        writel(end, EMI_MPU_EA6);
+        writel(access_permission, EMI_MPU_APC6);
+        break;
+
+    case 7:
+        writel(0, EMI_MPU_APC7);
+        writel(start, EMI_MPU_SA7);
+        writel(end, EMI_MPU_EA7);
+        writel(access_permission, EMI_MPU_APC7);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch(mpu_region)
+    {
+        case SECURE_OS_MPU_REGION_ID:
+#ifdef EIGHT_DOMAIN
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+#else
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(SEC_RW, FORBIDDEN, FORBIDDEN, SEC_RW);
+#endif
+            break;
+
+        case ATF_MPU_REGION_ID:
+#ifdef EIGHT_DOMAIN
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+#else
+            sec_mem_mpu_attr = SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+#endif
+            break;
+
+        default:
+            DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+            return;
+    }
+
+    DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,  /*START_ADDR*/
+                                        sec_mem_phy_end,    /*END_ADDR*/
+                                        mpu_region,         /*region*/
+                                        sec_mem_mpu_attr);
+
+    if(ret)
+    {
+        DBG_MSG("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/main.c b/src/bsp/trustzone/teeloader/mt6771/src/main.c
new file mode 100644
index 0000000..588fdeb
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/main.c
@@ -0,0 +1,116 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = 0x11002000;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+#if 1
+    tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                    (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                    ATF_MPU_REGION_ID);
+#endif
+
+    tz_dapc_sec_init();
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/print.c b/src/bsp/trustzone/teeloader/mt6771/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/start.s b/src/bsp/trustzone/teeloader/mt6771/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt6771/src/uart.c b/src/bsp/trustzone/teeloader/mt6771/src/uart.c
new file mode 100644
index 0000000..b238868
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART0_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART0_BASE));
+
+	writel((unsigned int)c, UART_THR(UART0_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt6771/tllink.lds b/src/bsp/trustzone/teeloader/mt6771/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt6771/zero_padding.sh b/src/bsp/trustzone/teeloader/mt6771/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt6771/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8133/Makefile b/src/bsp/trustzone/teeloader/mt8133/Makefile
new file mode 100644
index 0000000..61662f1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/Makefile
@@ -0,0 +1,53 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/print.h b/src/bsp/trustzone/teeloader/mt8133/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8133/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bdb4801
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_mpu.h
@@ -0,0 +1,23 @@
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+
+#define SECURE_OS_MPU_REGION_ID      0
+#define ATF_MPU_REGION_ID            1
+
+#define LOCK                1
+#define UNLOCK              0
+#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | ((((d7) << 9) | ((d6) << 6) | ((d5) << 3) | (d4)) << 16) | (lock << 15))
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_reg.h
new file mode 100644
index 0000000..622d7f2
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/tz_emi_reg.h
@@ -0,0 +1,276 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS            	    0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00203000)
+
+/*EMI PSRAM (NOR) and DRAM control registers*/
+#define EMI_CONA                 ((P_U32)(EMI_BASE+0x0000))  /* EMI control register for bank 0 */
+#define EMI_CONB                 ((P_U32)(EMI_BASE+0x0008))  /* EMI control register for bank 1 */
+#define EMI_CONC                 ((P_U32)(EMI_BASE+0x0010))  /* EMI control register for bank 2 */
+#define EMI_COND                 ((P_U32)(EMI_BASE+0x0018))  /* EMI control register for bank 3 */
+#define EMI_CONE                 ((P_U32)(EMI_BASE+0x0020))  /* EMI control register for bank 0 */
+#define EMI_CONF                 ((P_U32)(EMI_BASE+0x0028))  /* EMI control register for bank 1 */
+#define EMI_CONG                 ((P_U32)(EMI_BASE+0x0030))  /* EMI control register for bank 0 */
+#define EMI_CONH                 ((P_U32)(EMI_BASE+0x0038))  /* EMI control register for bank 1 */
+#define EMI_CONI                 ((P_U32)(EMI_BASE+0x0040))  /* EMI control register 0 for Mobile-RAM */
+#define EMI_CONJ                 ((P_U32)(EMI_BASE+0x0048))  /* EMI control register 1 for Mobile-RAM */
+#define EMI_CONK                 ((P_U32)(EMI_BASE+0x0050))  /* EMI control register 2 for Mobile-RAM */
+#define EMI_CONL                 ((P_U32)(EMI_BASE+0x0058))  /* EMI control register 3 for Mobile-RAM */
+#define EMI_CONM                 ((P_U32)(EMI_BASE+0x0060))
+#define EMI_CONN                 ((P_U32)(EMI_BASE+0x0068))
+#define CAL_EN                   (1 << 8)
+#define EMI_GENA                 ((P_U32)(EMI_BASE+0x0070))
+#define EMI_REMAP                 EMI_GENA
+#define EMI_DRCT                 ((P_U32)(EMI_BASE+0x0078))
+#define EMI_DDRV                 ((P_U32)(EMI_BASE+0x0080))
+#define EMI_GEND                 ((P_U32)(EMI_BASE+0x0088))
+#define EMI_PPCT                 ((P_U32)(EMI_BASE+0x0090)) /* EMI Performance and Power Control Register */
+
+#define EMI_DLLV                 ((P_U32)(EMI_BASE+0x00A0))
+
+#define EMI_DFTC                 ((P_U32)(EMI_BASE+0x00F0))
+#define EMI_DFTD                 ((P_U32)(EMI_BASE+0x00F8))
+
+/* EMI bandwith filter and MPU control registers */
+#define EMI_ARBA                 ((P_U32)(EMI_BASE+0x0100))
+#define EMI_ARBB                 ((P_U32)(EMI_BASE+0x0108))
+#define EMI_ARBC                 ((P_U32)(EMI_BASE+0x0110))
+#define EMI_ARBD                 ((P_U32)(EMI_BASE+0x0118))
+#define EMI_ARBE                 ((P_U32)(EMI_BASE+0x0120))
+#define EMI_ARBF                 ((P_U32)(EMI_BASE+0x0128))
+#define EMI_ARBG                 ((P_U32)(EMI_BASE+0x0130))
+
+#define EMI_SLCT                 ((P_U32)(EMI_BASE+0x0150))
+#define EMI_ABCT	             ((P_U32)(EMI_BASE+0x0158))
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA                 ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB                 ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC                 ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD                 ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE                ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF	        ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG	        ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH	        ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI	        ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUI_2ND	    ((P_U32)(EMI_BASE+0x01A4))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUJ_2ND	    ((P_U32)(EMI_BASE+0x01AC))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUK_2ND        ((P_U32)(EMI_BASE+0x01B4))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUL_2ND        ((P_U32)(EMI_BASE+0x01BC))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#define EMI_MPUA2		((P_U32)(EMI_BASE+0x0260))  
+#define EMI_MPUB2		((P_U32)(EMI_BASE+0x0268))  
+#define EMI_MPUC2		((P_U32)(EMI_BASE+0x0270))  
+#define EMI_MPUD2		((P_U32)(EMI_BASE+0x0278))
+#define EMI_MPUE2		((P_U32)(EMI_BASE+0x0280))  
+#define EMI_MPUF2		((P_U32)(EMI_BASE+0x0288))
+#define EMI_MPUG2		((P_U32)(EMI_BASE+0x0290)) 
+#define EMI_MPUH2		((P_U32)(EMI_BASE+0x0298))  
+#define EMI_MPUI2		((P_U32)(EMI_BASE+0x02A0))  
+#define EMI_MPUI2_2ND	((P_U32)(EMI_BASE+0x02A4))  
+#define EMI_MPUJ2		((P_U32)(EMI_BASE+0x02A8))  
+#define EMI_MPUJ2_2ND	((P_U32)(EMI_BASE+0x02AC))  
+#define EMI_MPUK2		((P_U32)(EMI_BASE+0x02B0)) 
+#define EMI_MPUK2_2ND	((P_U32)(EMI_BASE+0x02B4))  
+#define EMI_MPUL2		((P_U32)(EMI_BASE+0x02B8))  
+#define EMI_MPUL2_2ND	((P_U32)(EMI_BASE+0x02BC))  
+#define EMI_MPUM2		((P_U32)(EMI_BASE+0x02C0)) 
+#define EMI_MPUN2		((P_U32)(EMI_BASE+0x02C8)) 
+#define EMI_MPUO2		((P_U32)(EMI_BASE+0x02D0)) 
+#define EMI_MPUP2		((P_U32)(EMI_BASE+0x02D8)) 
+#define EMI_MPUQ2		((P_U32)(EMI_BASE+0x02E0)) 
+#define EMI_MPUR2		((P_U32)(EMI_BASE+0x02E8))  
+#define EMI_MPUU2		((P_U32)(EMI_BASE+0x0300))  
+#define EMI_MPUY2		((P_U32)(EMI_BASE+0x0320))
+
+/* EMI IO delay, driving and MISC control registers */
+#define EMI_IDLA            ((P_U32)(EMI_BASE+0x0200))
+#define EMI_IDLB            ((P_U32)(EMI_BASE+0x0208))
+#define EMI_IDLC            ((P_U32)(EMI_BASE+0x0210))
+#define EMI_IDLD            ((P_U32)(EMI_BASE+0x0218))
+#define EMI_IDLE            ((P_U32)(EMI_BASE+0x0220))
+#define EMI_IDLF            ((P_U32)(EMI_BASE+0x0228))
+#define EMI_IDLG            ((P_U32)(EMI_BASE+0x0230))
+#define EMI_IDLH            ((P_U32)(EMI_BASE+0x0238))
+#define EMI_IDLI            ((P_U32)(EMI_BASE+0x0240)) // IO input delay (DQS0 ~ DQS4)
+#define EMI_IDLJ            ((P_U32)(EMI_BASE+0x0248))
+#define EMI_IDLK            ((P_U32)(EMI_BASE+0x0250))
+
+#define EMI_ODLA           ((P_U32)(EMI_BASE+0x0258))
+#define EMI_ODLB           ((P_U32)(EMI_BASE+0x0260))
+#define EMI_ODLC           ((P_U32)(EMI_BASE+0x0268))
+#define EMI_ODLD           ((P_U32)(EMI_BASE+0x0270))
+#define EMI_ODLE           ((P_U32)(EMI_BASE+0x0278))
+#define EMI_ODLF           ((P_U32)(EMI_BASE+0x0280))
+#define EMI_ODLG           ((P_U32)(EMI_BASE+0x0288))
+
+#define EMI_DUTA           ((P_U32)(EMI_BASE+0x0290))
+#define EMI_DUTB           ((P_U32)(EMI_BASE+0x0298))
+#define EMI_DUTC           ((P_U32)(EMI_BASE+0x02A0))
+
+#define EMI_DRVA           ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_DRVB           ((P_U32)(EMI_BASE+0x02B0))
+
+#define EMI_IOCL           ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_IOCM           ((P_U32)(EMI_BASE+0x02C0)) //IvanTseng, for 4T mode
+#define EMI_IODC           ((P_U32)(EMI_BASE+0x02C8))
+
+#define EMI_ODTA           ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_ODTB           ((P_U32)(EMI_BASE+0x02D8))
+
+/* EMI auto-tracking control registers */
+#define EMI_DQSA           ((P_U32)(EMI_BASE+0x0300))
+#define EMI_DQSB           ((P_U32)(EMI_BASE+0x0308))
+#define EMI_DQSC           ((P_U32)(EMI_BASE+0x0310))
+#define EMI_DQSD           ((P_U32)(EMI_BASE+0x0318))
+
+
+#define EMI_DQSE           ((P_U32)(EMI_BASE+0x0320))
+#define EMI_DQSV           ((P_U32)(EMI_BASE+0x0328))
+
+#define EMI_CALA           ((P_U32)(EMI_BASE+0x0330))
+#define EMI_CALB           ((P_U32)(EMI_BASE+0x0338))
+#define EMI_CALC           ((P_U32)(EMI_BASE+0x0340))
+#define EMI_CALD           ((P_U32)(EMI_BASE+0x0348))
+
+
+#define EMI_CALE           ((P_U32)(EMI_BASE+0x0350)) //DDR data auto tracking control
+#define EMI_CALF           ((P_U32)(EMI_BASE+0x0358))
+#define EMI_CALG           ((P_U32)(EMI_BASE+0x0360)) //DDR data auto tracking control
+#define EMI_CALH           ((P_U32)(EMI_BASE+0x0368))
+
+#define EMI_CALI           ((P_U32)(EMI_BASE+0x0370))
+#define EMI_CALJ           ((P_U32)(EMI_BASE+0x0378))
+#define EMI_CALK           ((P_U32)(EMI_BASE+0x0380))
+#define EMI_CALL           ((P_U32)(EMI_BASE+0x0388))
+
+
+#define EMI_CALM           ((P_U32)(EMI_BASE+0x0390))
+#define EMI_CALN           ((P_U32)(EMI_BASE+0x0398))
+
+#define EMI_CALO           ((P_U32)(EMI_BASE+0x03A0))
+#define EMI_CALP           ((P_U32)(EMI_BASE+0x03A8))
+
+#define EMI_DUCA           ((P_U32)(EMI_BASE+0x03B0))
+#define EMI_DUCB           ((P_U32)(EMI_BASE+0x03B8))
+#define EMI_DUCC           ((P_U32)(EMI_BASE+0x03C0))
+#define EMI_DUCD           ((P_U32)(EMI_BASE+0x03C8))
+#define EMI_DUCE           ((P_U32)(EMI_BASE+0x03D0))
+
+/* EMI bus monitor control registers */
+#define EMI_BMEN           ((P_U32)(EMI_BASE+0x0400))
+#define EMI_BCNT           ((P_U32)(EMI_BASE+0x0408))
+#define EMI_TACT           ((P_U32)(EMI_BASE+0x0410))
+#define EMI_TSCT           ((P_U32)(EMI_BASE+0x0418))
+#define EMI_WACT           ((P_U32)(EMI_BASE+0x0420))
+#define EMI_WSCT           ((P_U32)(EMI_BASE+0x0428))
+#define EMI_BACT           ((P_U32)(EMI_BASE+0x0430))
+#define EMI_BSCT           ((P_U32)(EMI_BASE+0x0438))
+#define EMI_MSEL           ((P_U32)(EMI_BASE+0x0440))
+#define EMI_TSCT2           ((P_U32)(EMI_BASE+0x0448))
+#define EMI_TSCT3           ((P_U32)(EMI_BASE+0x0450))
+#define EMI_WSCT2           ((P_U32)(EMI_BASE+0x0458))
+#define EMI_WSCT3           ((P_U32)(EMI_BASE+0x0460))
+#define EMI_MSEL2           ((P_U32)(EMI_BASE+0x0468))
+#define EMI_MSEL3           ((P_U32)(EMI_BASE+0x0470))
+#define EMI_MSEL4           ((P_U32)(EMI_BASE+0x0478))
+#define EMI_MSEL5           ((P_U32)(EMI_BASE+0x0480))
+#define EMI_MSEL6           ((P_U32)(EMI_BASE+0x0488))
+#define EMI_MSEL7           ((P_U32)(EMI_BASE+0x0490))
+#define EMI_MSEL8           ((P_U32)(EMI_BASE+0x0498))
+#define EMI_MSEL9           ((P_U32)(EMI_BASE+0x04A0))
+#define EMI_MSEL10           ((P_U32)(EMI_BASE+0x04A8))
+#define EMI_BMID0            ((P_U32)(EMI_BASE+0x04B0))
+#define EMI_BMID1            ((P_U32)(EMI_BASE+0x04B8))
+#define EMI_BMID2            ((P_U32)(EMI_BASE+0x04C0))
+#define EMI_BMID3            ((P_U32)(EMI_BASE+0x04C8))
+#define EMI_BMID4            ((P_U32)(EMI_BASE+0x04D0))
+#define EMI_BMID5            ((P_U32)(EMI_BASE+0x04D8))
+
+#define EMI_TTYPE1            ((P_U32)(EMI_BASE+0x0500))
+#define EMI_TTYPE2            ((P_U32)(EMI_BASE+0x0508))
+#define EMI_TTYPE3            ((P_U32)(EMI_BASE+0x0510))
+#define EMI_TTYPE4            ((P_U32)(EMI_BASE+0x0518))
+#define EMI_TTYPE5            ((P_U32)(EMI_BASE+0x0520))
+#define EMI_TTYPE6            ((P_U32)(EMI_BASE+0x0528))
+#define EMI_TTYPE7            ((P_U32)(EMI_BASE+0x0530))
+#define EMI_TTYPE8            ((P_U32)(EMI_BASE+0x0538))
+#define EMI_TTYPE9            ((P_U32)(EMI_BASE+0x0540))
+#define EMI_TTYPE10            ((P_U32)(EMI_BASE+0x0548))
+#define EMI_TTYPE11            ((P_U32)(EMI_BASE+0x0550))
+#define EMI_TTYPE12            ((P_U32)(EMI_BASE+0x0558))
+#define EMI_TTYPE13            ((P_U32)(EMI_BASE+0x0560))
+#define EMI_TTYPE14            ((P_U32)(EMI_BASE+0x0568))
+#define EMI_TTYPE15            ((P_U32)(EMI_BASE+0x0570))
+#define EMI_TTYPE16            ((P_U32)(EMI_BASE+0x0578))
+#define EMI_TTYPE17            ((P_U32)(EMI_BASE+0x0580))
+#define EMI_TTYPE18            ((P_U32)(EMI_BASE+0x0588))
+#define EMI_TTYPE19            ((P_U32)(EMI_BASE+0x0590))
+#define EMI_TTYPE20            ((P_U32)(EMI_BASE+0x0598))
+#define EMI_TTYPE21            ((P_U32)(EMI_BASE+0x05A0))
+
+/* EMI MBIST control registers*/
+#define EMI_MBISTA            ((P_U32)(EMI_BASE+0x0600))
+#define EMI_MBISTB            ((P_U32)(EMI_BASE+0x0608))
+#define EMI_MBISTC            ((P_U32)(EMI_BASE+0x0610))
+#define EMI_MBISTD            ((P_U32)(EMI_BASE+0x0618))
+#define EMI_MBISTE            ((P_U32)(EMI_BASE+0x0620)) /* EMI MBIST status register */
+
+
+/* EMI Flow control register A */
+#define EMI_RFCA            ((P_U32)(EMI_BASE+0x0630))
+#define EMI_RFCB            ((P_U32)(EMI_BASE+0x0638))
+#define EMI_RFCC            ((P_U32)(EMI_BASE+0x0640))
+#define EMI_RFCD            ((P_U32)(EMI_BASE+0x0648))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8133/include/tz_init.h
new file mode 100644
index 0000000..61ca3ee
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/tz_init.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2011
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x43200000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+    u32 atf_magic;
+    u32 tee_support;
+    u32 tee_entry;
+    u32 tee_boot_arg_addr;
+    u32 hwuid[4];     // HW Unique id for t-base used
+    u32 atf_hrid_size;
+    u32 HRID[8];      // HW random id for t-base used
+    u32 atf_log_port;
+    u32 atf_log_baudrate;
+    u32 atf_log_buf_start;
+    u32 atf_log_buf_size;
+    u32 atf_irq_num;
+    u32 devinfo[DEVINFO_SIZE];
+    u32 atf_aee_debug_buf_start;
+    u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+    u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* TRUSTZONE_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt8133/include/uart.h b/src/bsp/trustzone/teeloader/mt8133/include/uart.h
new file mode 100644
index 0000000..13cabd0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/include/uart.h
@@ -0,0 +1,62 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART0_BASE         (IO_PHYS + 0x01002000)
+#define UART1_BASE         (IO_PHYS + 0x01003000)
+#define UART2_BASE         (IO_PHYS + 0x01004000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8133/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8133/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..1aec1d9
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,304 @@
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+#define print tl_printf
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp, tmp2;
+    unsigned int ax_pm, ax_pm2;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end <= start)
+        {
+            return -1;
+        }
+    }
+
+    ax_pm  = (access_permission << 16) >> 16;
+    ax_pm2 = (access_permission >> 16);
+
+    switch (region) {
+    case 0:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp2 | ax_pm2, EMI_MPUI_2ND);
+        writel(tmp | ax_pm, EMI_MPUI);
+        break;
+
+    case 1:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUC);
+        writel(tmp2 | ax_pm2, EMI_MPUJ_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ);
+        break;
+
+    case 3:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp2 | ax_pm2, EMI_MPUK_2ND);
+        writel(tmp | ax_pm, EMI_MPUK);
+        break;
+
+    case 5:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK);
+        break;
+
+    case 6:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp2 | ax_pm2, EMI_MPUL_2ND);
+        writel(tmp | ax_pm, EMI_MPUL);
+        break;
+
+    case 7:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL);
+        break;
+
+    case 8:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUA2);
+        writel(tmp2 | ax_pm2, EMI_MPUI2_2ND);
+        writel(tmp | ax_pm, EMI_MPUI2);
+        break;
+
+    case 9:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUB2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI2);
+        break;
+
+    case 10:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUC2);
+        writel(tmp2 | ax_pm2, EMI_MPUJ2_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ2);
+        break;
+
+    case 11:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUD2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ2);
+        break;
+
+    case 12:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUE2);
+        writel(tmp2 | ax_pm2, EMI_MPUK2_2ND);
+        writel(tmp | ax_pm, EMI_MPUK2);
+        break;
+
+    case 13:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUF2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK2);
+        break;
+
+    case 14:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUG2);
+        writel(tmp2 | ax_pm2, EMI_MPUL2_2ND);
+        writel(tmp | ax_pm, EMI_MPUL2);
+        break;
+
+    case 15:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUH2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL2);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+    unsigned int temp;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    // For MT6589
+    //==================================================================================================================
+    //            | Region |  D0(AP)  |  D1(MD0)  |  D2(Conn) |  D3(MD32) |  D4(MM)  |  D5(MD1)  |  D6(MFG)  |  D7(N/A)
+    //------------+---------------------------------------------------------------------------------------------------
+    // Secure OS  |    0   |RW(S)     |Forbidden  |Forbidden  |Forbidden  |RW(S)     |Forbidden  |Forbidden  |Forbidden
+    //------------+---------------------------------------------------------------------------------------------------
+    // MD0 ROM    |    1   |RO(S/NS)  |RO(S/NS)   |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 R/W+   |    2   |Forbidden |No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 ROM    |    3   |RO(S/NS)  |Forbidden  |RO(S/NS)   |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 R/W+   |    4   |Forbidden |Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 Share  |    5   |No protect|No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 Share  |    6   |No protect|Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // AP         |    7   |No protect|Forbidden  |Forbidden  |No protect
+    //===================================================================
+
+    switch (mpu_region) {
+    case SECURE_OS_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    case ATF_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    default:
+        print("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+        return;
+    }
+
+    print("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,      /*START_ADDR*/
+                                        sec_mem_phy_end,      /*END_ADDR*/
+                                        mpu_region,       /*region*/
+                                        sec_mem_mpu_attr);
+
+
+    if(ret)
+    {
+        print("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8133/src/main.c b/src/bsp/trustzone/teeloader/mt8133/src/main.c
new file mode 100644
index 0000000..2efa9bd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/src/main.c
@@ -0,0 +1,115 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "uart.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+extern void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region);
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = UART0_BASE;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+    tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                    (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                    ATF_MPU_REGION_ID);
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8133/src/print.c b/src/bsp/trustzone/teeloader/mt8133/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8133/src/start.s b/src/bsp/trustzone/teeloader/mt8133/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8133/src/uart.c b/src/bsp/trustzone/teeloader/mt8133/src/uart.c
new file mode 100644
index 0000000..b238868
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART0_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART0_BASE));
+
+	writel((unsigned int)c, UART_THR(UART0_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8133/tllink.lds b/src/bsp/trustzone/teeloader/mt8133/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8133/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8133/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8133/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8512/Makefile b/src/bsp/trustzone/teeloader/mt8512/Makefile
new file mode 100644
index 0000000..9879df0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/Makefile
@@ -0,0 +1,57 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c \
+	$(DIR_SRC)/drivers/tz_dapc.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+ifeq ($(strip $(TRUSTEDOS_SIZE)),)
+TRUSTEDOS_SIZE := 0
+endif
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -DTRUSTEDOS_SIZE=${TRUSTEDOS_SIZE} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/print.h b/src/bsp/trustzone/teeloader/mt8512/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h
new file mode 100644
index 0000000..59615c6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h
@@ -0,0 +1,183 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+/* DEVAPC  = "DEVAPC"
+ * DEVAPC0 = "DEVAPC_AO_INFRA_PERI"
+ * DEVAPC1 = "DEVAPC_AO_MM"
+ */
+
+#define DEVAPC_BASE          (0x10207000U)
+#define DEVAPC0_BASE         (0x1000E000U)
+#define DEVAPC1_BASE         (0x1001C000U)
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define PERM_OFF(x) (0x4 * x)
+
+/* DEVAPC_AO_INFRA_PERI */
+#define DEVAPC0_D0_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0000+PERM_OFF(n)))
+#define DEVAPC0_D1_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0100+PERM_OFF(n)))
+#define DEVAPC0_D2_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0200+PERM_OFF(n)))
+#define DEVAPC0_D3_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0300+PERM_OFF(n)))
+#define DEVAPC0_D4_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0400+PERM_OFF(n)))
+#define DEVAPC0_D5_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0500+PERM_OFF(n)))
+#define DEVAPC0_D6_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0600+PERM_OFF(n)))
+#define DEVAPC0_D7_APC(n)     ((volatile unsigned int*)(DEVAPC0_BASE+0x0700+PERM_OFF(n)))
+
+#define DEVAPC0_APC_CON       ((volatile unsigned int*)(DEVAPC0_BASE+0x0F00))
+#define DEVAPC0_MAS_DOM_0     ((volatile unsigned int*)(DEVAPC0_BASE+0x0A00))
+#define DEVAPC0_MAS_DOM_1     ((volatile unsigned int*)(DEVAPC0_BASE+0x0A04))
+#define DEVAPC0_MAS_DOM_2     ((volatile unsigned int*)(DEVAPC0_BASE+0x0A08))
+#define DEVAPC0_MAS_SEC_0     ((volatile unsigned int*)(DEVAPC0_BASE+0x0B00))
+
+/* DEVAPC_AO_MM */
+#define DEVAPC1_APC_CON       ((volatile unsigned int*)(DEVAPC1_BASE+0x0F00))
+
+/* DEVAPC */
+#define DEVAPC_APC_CON        ((volatile unsigned int*)(DEVAPC_BASE+0x0F00))
+
+
+typedef enum {
+    NS_TRANSACTION = 0,
+    S_TRANSACTION,
+} E_TRANSACTION;
+
+typedef enum {
+    DOMAIN_0 = 0,
+    DOMAIN_1,
+    DOMAIN_2,
+    DOMAIN_3,
+    DOMAIN_4,
+    DOMAIN_5,
+    DOMAIN_6,
+    DOMAIN_7,
+} E_DOMAIN;
+
+typedef enum {
+    NO_PROTECTION = 0,
+    SEC_RW_ONLY,
+    SEC_RW_NSEC_R,
+    NOT_ACCESSIBLE,
+} E_SLAVE_PERMISSION;
+
+static inline unsigned int uffs(unsigned int x)
+{
+    unsigned int r = 1;
+
+    if (!x)
+        return 0;
+    if (!(x & 0xffff)) {
+        x >>= 16;
+        r += 16;
+    }
+    if (!(x & 0xff)) {
+        x >>= 8;
+        r += 8;
+    }
+    if (!(x & 0xf)) {
+        x >>= 4;
+        r += 4;
+    }
+    if (!(x & 3)) {
+        x >>= 2;
+        r += 2;
+    }
+    if (!(x & 1)) {
+        x >>= 1;
+        r += 1;
+    }
+    return r;
+}
+
+#define reg_read32(reg)        (*(volatile u32* const)(reg))
+#define reg_write32(reg,val)   ((*(volatile u32* const)(reg)) = (val))
+
+#define reg_set_bits(reg,bs)   ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs)   ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        tv &= ~(field); \
+        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+        reg_write32(reg,tv); \
+    } while(0)
+
+#define reg_get_field(reg,field,val) \
+    do {    \
+        volatile unsigned int tv = reg_read32(reg); \
+        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+    } while(0)
+
+
+
+typedef enum {
+    MASTER_NFI = 0,
+    MASTER_SSUSB_XHCI = 1,
+    MASTER_PWM = 3,
+    MASTER_MSDC0 = 5,
+    MASTER_MSDC1 = 6,
+} E_MASTER;
+
+
+#define MODULE_TRANSACTION(index, is_secure) (is_secure << index)
+#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)
+
+#define MODULE_DOMAIN(index, domain) (domain << (4 * (index % 8)))
+#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)
+
+#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))
+#define DAPC_SET_SLAVE_PERMISSION(devapc_register, permission) reg_write32(devapc_register, permission)
+
+typedef enum{
+    INFRA_AO_SEJ = 10,
+    INFRA_AO_DEVICE_APC_AO_INFRA_PERI = 14,
+    INFRA_AO_DEVICE_APC_AO_MM = 28,
+    INFRASYS_DEVICE_APC = 39,
+} E_DEVAPC0_SLAVE;
+
+
+void tz_dapc_sec_init(void);
+void tz_dapc_sec_postinit(void);
+void tz_dapc_set_master_transaction(unsigned int  master_index , E_TRANSACTION permisssion_control);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bdb4801
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h
@@ -0,0 +1,23 @@
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+
+#define SECURE_OS_MPU_REGION_ID      0
+#define ATF_MPU_REGION_ID            1
+
+#define LOCK                1
+#define UNLOCK              0
+#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | ((((d7) << 9) | ((d6) << 6) | ((d5) << 3) | (d4)) << 16) | (lock << 15))
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h
new file mode 100644
index 0000000..622d7f2
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h
@@ -0,0 +1,276 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS            	    0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00203000)
+
+/*EMI PSRAM (NOR) and DRAM control registers*/
+#define EMI_CONA                 ((P_U32)(EMI_BASE+0x0000))  /* EMI control register for bank 0 */
+#define EMI_CONB                 ((P_U32)(EMI_BASE+0x0008))  /* EMI control register for bank 1 */
+#define EMI_CONC                 ((P_U32)(EMI_BASE+0x0010))  /* EMI control register for bank 2 */
+#define EMI_COND                 ((P_U32)(EMI_BASE+0x0018))  /* EMI control register for bank 3 */
+#define EMI_CONE                 ((P_U32)(EMI_BASE+0x0020))  /* EMI control register for bank 0 */
+#define EMI_CONF                 ((P_U32)(EMI_BASE+0x0028))  /* EMI control register for bank 1 */
+#define EMI_CONG                 ((P_U32)(EMI_BASE+0x0030))  /* EMI control register for bank 0 */
+#define EMI_CONH                 ((P_U32)(EMI_BASE+0x0038))  /* EMI control register for bank 1 */
+#define EMI_CONI                 ((P_U32)(EMI_BASE+0x0040))  /* EMI control register 0 for Mobile-RAM */
+#define EMI_CONJ                 ((P_U32)(EMI_BASE+0x0048))  /* EMI control register 1 for Mobile-RAM */
+#define EMI_CONK                 ((P_U32)(EMI_BASE+0x0050))  /* EMI control register 2 for Mobile-RAM */
+#define EMI_CONL                 ((P_U32)(EMI_BASE+0x0058))  /* EMI control register 3 for Mobile-RAM */
+#define EMI_CONM                 ((P_U32)(EMI_BASE+0x0060))
+#define EMI_CONN                 ((P_U32)(EMI_BASE+0x0068))
+#define CAL_EN                   (1 << 8)
+#define EMI_GENA                 ((P_U32)(EMI_BASE+0x0070))
+#define EMI_REMAP                 EMI_GENA
+#define EMI_DRCT                 ((P_U32)(EMI_BASE+0x0078))
+#define EMI_DDRV                 ((P_U32)(EMI_BASE+0x0080))
+#define EMI_GEND                 ((P_U32)(EMI_BASE+0x0088))
+#define EMI_PPCT                 ((P_U32)(EMI_BASE+0x0090)) /* EMI Performance and Power Control Register */
+
+#define EMI_DLLV                 ((P_U32)(EMI_BASE+0x00A0))
+
+#define EMI_DFTC                 ((P_U32)(EMI_BASE+0x00F0))
+#define EMI_DFTD                 ((P_U32)(EMI_BASE+0x00F8))
+
+/* EMI bandwith filter and MPU control registers */
+#define EMI_ARBA                 ((P_U32)(EMI_BASE+0x0100))
+#define EMI_ARBB                 ((P_U32)(EMI_BASE+0x0108))
+#define EMI_ARBC                 ((P_U32)(EMI_BASE+0x0110))
+#define EMI_ARBD                 ((P_U32)(EMI_BASE+0x0118))
+#define EMI_ARBE                 ((P_U32)(EMI_BASE+0x0120))
+#define EMI_ARBF                 ((P_U32)(EMI_BASE+0x0128))
+#define EMI_ARBG                 ((P_U32)(EMI_BASE+0x0130))
+
+#define EMI_SLCT                 ((P_U32)(EMI_BASE+0x0150))
+#define EMI_ABCT	             ((P_U32)(EMI_BASE+0x0158))
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA                 ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB                 ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC                 ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD                 ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE                ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF	        ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG	        ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH	        ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI	        ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUI_2ND	    ((P_U32)(EMI_BASE+0x01A4))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUJ_2ND	    ((P_U32)(EMI_BASE+0x01AC))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUK_2ND        ((P_U32)(EMI_BASE+0x01B4))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUL_2ND        ((P_U32)(EMI_BASE+0x01BC))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#define EMI_MPUA2		((P_U32)(EMI_BASE+0x0260))  
+#define EMI_MPUB2		((P_U32)(EMI_BASE+0x0268))  
+#define EMI_MPUC2		((P_U32)(EMI_BASE+0x0270))  
+#define EMI_MPUD2		((P_U32)(EMI_BASE+0x0278))
+#define EMI_MPUE2		((P_U32)(EMI_BASE+0x0280))  
+#define EMI_MPUF2		((P_U32)(EMI_BASE+0x0288))
+#define EMI_MPUG2		((P_U32)(EMI_BASE+0x0290)) 
+#define EMI_MPUH2		((P_U32)(EMI_BASE+0x0298))  
+#define EMI_MPUI2		((P_U32)(EMI_BASE+0x02A0))  
+#define EMI_MPUI2_2ND	((P_U32)(EMI_BASE+0x02A4))  
+#define EMI_MPUJ2		((P_U32)(EMI_BASE+0x02A8))  
+#define EMI_MPUJ2_2ND	((P_U32)(EMI_BASE+0x02AC))  
+#define EMI_MPUK2		((P_U32)(EMI_BASE+0x02B0)) 
+#define EMI_MPUK2_2ND	((P_U32)(EMI_BASE+0x02B4))  
+#define EMI_MPUL2		((P_U32)(EMI_BASE+0x02B8))  
+#define EMI_MPUL2_2ND	((P_U32)(EMI_BASE+0x02BC))  
+#define EMI_MPUM2		((P_U32)(EMI_BASE+0x02C0)) 
+#define EMI_MPUN2		((P_U32)(EMI_BASE+0x02C8)) 
+#define EMI_MPUO2		((P_U32)(EMI_BASE+0x02D0)) 
+#define EMI_MPUP2		((P_U32)(EMI_BASE+0x02D8)) 
+#define EMI_MPUQ2		((P_U32)(EMI_BASE+0x02E0)) 
+#define EMI_MPUR2		((P_U32)(EMI_BASE+0x02E8))  
+#define EMI_MPUU2		((P_U32)(EMI_BASE+0x0300))  
+#define EMI_MPUY2		((P_U32)(EMI_BASE+0x0320))
+
+/* EMI IO delay, driving and MISC control registers */
+#define EMI_IDLA            ((P_U32)(EMI_BASE+0x0200))
+#define EMI_IDLB            ((P_U32)(EMI_BASE+0x0208))
+#define EMI_IDLC            ((P_U32)(EMI_BASE+0x0210))
+#define EMI_IDLD            ((P_U32)(EMI_BASE+0x0218))
+#define EMI_IDLE            ((P_U32)(EMI_BASE+0x0220))
+#define EMI_IDLF            ((P_U32)(EMI_BASE+0x0228))
+#define EMI_IDLG            ((P_U32)(EMI_BASE+0x0230))
+#define EMI_IDLH            ((P_U32)(EMI_BASE+0x0238))
+#define EMI_IDLI            ((P_U32)(EMI_BASE+0x0240)) // IO input delay (DQS0 ~ DQS4)
+#define EMI_IDLJ            ((P_U32)(EMI_BASE+0x0248))
+#define EMI_IDLK            ((P_U32)(EMI_BASE+0x0250))
+
+#define EMI_ODLA           ((P_U32)(EMI_BASE+0x0258))
+#define EMI_ODLB           ((P_U32)(EMI_BASE+0x0260))
+#define EMI_ODLC           ((P_U32)(EMI_BASE+0x0268))
+#define EMI_ODLD           ((P_U32)(EMI_BASE+0x0270))
+#define EMI_ODLE           ((P_U32)(EMI_BASE+0x0278))
+#define EMI_ODLF           ((P_U32)(EMI_BASE+0x0280))
+#define EMI_ODLG           ((P_U32)(EMI_BASE+0x0288))
+
+#define EMI_DUTA           ((P_U32)(EMI_BASE+0x0290))
+#define EMI_DUTB           ((P_U32)(EMI_BASE+0x0298))
+#define EMI_DUTC           ((P_U32)(EMI_BASE+0x02A0))
+
+#define EMI_DRVA           ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_DRVB           ((P_U32)(EMI_BASE+0x02B0))
+
+#define EMI_IOCL           ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_IOCM           ((P_U32)(EMI_BASE+0x02C0)) //IvanTseng, for 4T mode
+#define EMI_IODC           ((P_U32)(EMI_BASE+0x02C8))
+
+#define EMI_ODTA           ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_ODTB           ((P_U32)(EMI_BASE+0x02D8))
+
+/* EMI auto-tracking control registers */
+#define EMI_DQSA           ((P_U32)(EMI_BASE+0x0300))
+#define EMI_DQSB           ((P_U32)(EMI_BASE+0x0308))
+#define EMI_DQSC           ((P_U32)(EMI_BASE+0x0310))
+#define EMI_DQSD           ((P_U32)(EMI_BASE+0x0318))
+
+
+#define EMI_DQSE           ((P_U32)(EMI_BASE+0x0320))
+#define EMI_DQSV           ((P_U32)(EMI_BASE+0x0328))
+
+#define EMI_CALA           ((P_U32)(EMI_BASE+0x0330))
+#define EMI_CALB           ((P_U32)(EMI_BASE+0x0338))
+#define EMI_CALC           ((P_U32)(EMI_BASE+0x0340))
+#define EMI_CALD           ((P_U32)(EMI_BASE+0x0348))
+
+
+#define EMI_CALE           ((P_U32)(EMI_BASE+0x0350)) //DDR data auto tracking control
+#define EMI_CALF           ((P_U32)(EMI_BASE+0x0358))
+#define EMI_CALG           ((P_U32)(EMI_BASE+0x0360)) //DDR data auto tracking control
+#define EMI_CALH           ((P_U32)(EMI_BASE+0x0368))
+
+#define EMI_CALI           ((P_U32)(EMI_BASE+0x0370))
+#define EMI_CALJ           ((P_U32)(EMI_BASE+0x0378))
+#define EMI_CALK           ((P_U32)(EMI_BASE+0x0380))
+#define EMI_CALL           ((P_U32)(EMI_BASE+0x0388))
+
+
+#define EMI_CALM           ((P_U32)(EMI_BASE+0x0390))
+#define EMI_CALN           ((P_U32)(EMI_BASE+0x0398))
+
+#define EMI_CALO           ((P_U32)(EMI_BASE+0x03A0))
+#define EMI_CALP           ((P_U32)(EMI_BASE+0x03A8))
+
+#define EMI_DUCA           ((P_U32)(EMI_BASE+0x03B0))
+#define EMI_DUCB           ((P_U32)(EMI_BASE+0x03B8))
+#define EMI_DUCC           ((P_U32)(EMI_BASE+0x03C0))
+#define EMI_DUCD           ((P_U32)(EMI_BASE+0x03C8))
+#define EMI_DUCE           ((P_U32)(EMI_BASE+0x03D0))
+
+/* EMI bus monitor control registers */
+#define EMI_BMEN           ((P_U32)(EMI_BASE+0x0400))
+#define EMI_BCNT           ((P_U32)(EMI_BASE+0x0408))
+#define EMI_TACT           ((P_U32)(EMI_BASE+0x0410))
+#define EMI_TSCT           ((P_U32)(EMI_BASE+0x0418))
+#define EMI_WACT           ((P_U32)(EMI_BASE+0x0420))
+#define EMI_WSCT           ((P_U32)(EMI_BASE+0x0428))
+#define EMI_BACT           ((P_U32)(EMI_BASE+0x0430))
+#define EMI_BSCT           ((P_U32)(EMI_BASE+0x0438))
+#define EMI_MSEL           ((P_U32)(EMI_BASE+0x0440))
+#define EMI_TSCT2           ((P_U32)(EMI_BASE+0x0448))
+#define EMI_TSCT3           ((P_U32)(EMI_BASE+0x0450))
+#define EMI_WSCT2           ((P_U32)(EMI_BASE+0x0458))
+#define EMI_WSCT3           ((P_U32)(EMI_BASE+0x0460))
+#define EMI_MSEL2           ((P_U32)(EMI_BASE+0x0468))
+#define EMI_MSEL3           ((P_U32)(EMI_BASE+0x0470))
+#define EMI_MSEL4           ((P_U32)(EMI_BASE+0x0478))
+#define EMI_MSEL5           ((P_U32)(EMI_BASE+0x0480))
+#define EMI_MSEL6           ((P_U32)(EMI_BASE+0x0488))
+#define EMI_MSEL7           ((P_U32)(EMI_BASE+0x0490))
+#define EMI_MSEL8           ((P_U32)(EMI_BASE+0x0498))
+#define EMI_MSEL9           ((P_U32)(EMI_BASE+0x04A0))
+#define EMI_MSEL10           ((P_U32)(EMI_BASE+0x04A8))
+#define EMI_BMID0            ((P_U32)(EMI_BASE+0x04B0))
+#define EMI_BMID1            ((P_U32)(EMI_BASE+0x04B8))
+#define EMI_BMID2            ((P_U32)(EMI_BASE+0x04C0))
+#define EMI_BMID3            ((P_U32)(EMI_BASE+0x04C8))
+#define EMI_BMID4            ((P_U32)(EMI_BASE+0x04D0))
+#define EMI_BMID5            ((P_U32)(EMI_BASE+0x04D8))
+
+#define EMI_TTYPE1            ((P_U32)(EMI_BASE+0x0500))
+#define EMI_TTYPE2            ((P_U32)(EMI_BASE+0x0508))
+#define EMI_TTYPE3            ((P_U32)(EMI_BASE+0x0510))
+#define EMI_TTYPE4            ((P_U32)(EMI_BASE+0x0518))
+#define EMI_TTYPE5            ((P_U32)(EMI_BASE+0x0520))
+#define EMI_TTYPE6            ((P_U32)(EMI_BASE+0x0528))
+#define EMI_TTYPE7            ((P_U32)(EMI_BASE+0x0530))
+#define EMI_TTYPE8            ((P_U32)(EMI_BASE+0x0538))
+#define EMI_TTYPE9            ((P_U32)(EMI_BASE+0x0540))
+#define EMI_TTYPE10            ((P_U32)(EMI_BASE+0x0548))
+#define EMI_TTYPE11            ((P_U32)(EMI_BASE+0x0550))
+#define EMI_TTYPE12            ((P_U32)(EMI_BASE+0x0558))
+#define EMI_TTYPE13            ((P_U32)(EMI_BASE+0x0560))
+#define EMI_TTYPE14            ((P_U32)(EMI_BASE+0x0568))
+#define EMI_TTYPE15            ((P_U32)(EMI_BASE+0x0570))
+#define EMI_TTYPE16            ((P_U32)(EMI_BASE+0x0578))
+#define EMI_TTYPE17            ((P_U32)(EMI_BASE+0x0580))
+#define EMI_TTYPE18            ((P_U32)(EMI_BASE+0x0588))
+#define EMI_TTYPE19            ((P_U32)(EMI_BASE+0x0590))
+#define EMI_TTYPE20            ((P_U32)(EMI_BASE+0x0598))
+#define EMI_TTYPE21            ((P_U32)(EMI_BASE+0x05A0))
+
+/* EMI MBIST control registers*/
+#define EMI_MBISTA            ((P_U32)(EMI_BASE+0x0600))
+#define EMI_MBISTB            ((P_U32)(EMI_BASE+0x0608))
+#define EMI_MBISTC            ((P_U32)(EMI_BASE+0x0610))
+#define EMI_MBISTD            ((P_U32)(EMI_BASE+0x0618))
+#define EMI_MBISTE            ((P_U32)(EMI_BASE+0x0620)) /* EMI MBIST status register */
+
+
+/* EMI Flow control register A */
+#define EMI_RFCA            ((P_U32)(EMI_BASE+0x0630))
+#define EMI_RFCB            ((P_U32)(EMI_BASE+0x0638))
+#define EMI_RFCC            ((P_U32)(EMI_BASE+0x0640))
+#define EMI_RFCD            ((P_U32)(EMI_BASE+0x0648))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h
new file mode 100644
index 0000000..23a5649
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2011
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x43a00000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+    u32 atf_magic;
+    u32 tee_support;
+    u32 tee_entry;
+    u32 tee_boot_arg_addr;
+    u32 hwuid[4];     // HW Unique id for t-base used
+    u32 atf_hrid_size;
+    u32 HRID[8];      // HW random id for t-base used
+    u32 atf_log_port;
+    u32 atf_log_baudrate;
+    u32 atf_log_buf_start;
+    u32 atf_log_buf_size;
+    u32 atf_irq_num;
+    u32 devinfo[DEVINFO_SIZE];
+    u32 atf_aee_debug_buf_start;
+    u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+    u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* TRUSTZONE_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/uart.h b/src/bsp/trustzone/teeloader/mt8512/include/uart.h
new file mode 100644
index 0000000..13cabd0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/uart.h
@@ -0,0 +1,62 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART0_BASE         (IO_PHYS + 0x01002000)
+#define UART1_BASE         (IO_PHYS + 0x01003000)
+#define UART2_BASE         (IO_PHYS + 0x01004000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c
new file mode 100644
index 0000000..a4b3cd5
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c
@@ -0,0 +1,194 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES                                                          */
+/*=======================================================================*/
+#include <tz_dapc.h>
+#include <print.h>
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE       (0x00000000U)      /* No event */
+#define DBG_EVT_ERR        (0x00000001U)      /* ERR related event */
+#define DBG_EVT_DOM        (0x00000002U)      /* DOM related event */
+
+#define DBG_EVT_ALL        (0xffffffffU)
+
+#define DBG_EVT_MASK       (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+    do {    \
+        if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+            tl_printf(fmt, ##args); \
+        } \
+    } while(0)
+
+#define MSG_FUNC_ENTRY(f)   MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{} while(0)
+#define MSG_FUNC_ENTRY(f)      do{} while(0)
+#endif
+
+/*=======================================================================*/
+/* STATIC FUNCTIONS                                                      */
+/*=======================================================================*/
+static void DAPC_dom_init(void)
+{
+    MSG(DOM, "\nDevice APC domain init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+
+    /* Set masters to DOMAINX here if needed
+     * Default is DOMAIN_0 */
+
+    /* example */
+    /*DAPC_SET_MASTER_DOMAIN(
+        DEVAPC0_MAS_DOM_0,
+        MODULE_DOMAIN(MASTER_SSUSB_XHCI,   DOMAIN_0) |
+        MODULE_DOMAIN(MASTER_PWM,          DOMAIN_1) |
+        MODULE_DOMAIN(MASTER_MSDC0,        DOMAIN_2) |
+        MODULE_DOMAIN(MASTER_MSDC1,        DOMAIN_3)
+    );*/
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Device APC domain after setup:\n");
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+    MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+}
+
+static void DAPC_trans_init(void)
+{
+    MSG(DOM, "\nDevice APC master transcation init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Master Transaction (0x%x)\n", reg_read32(DEVAPC0_MAS_SEC_0));
+#endif
+
+    /* Set master transaction here if needed,
+     * default is non-secure transaction */
+
+    /* example */
+    /*DAPC_SET_MASTER_TRANSACTION(
+        DEVAPC0_MAS_SEC_0,
+        MODULE_TRANSACTION(MASTER_NFI,          NS_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_SSUSB_XHCI,    S_TRANSACTION) |
+        MODULE_TRANSACTION(MASTER_PWM,          NS_TRANSACTION)
+    );*/
+
+#ifdef DBG_DEVAPC
+    MSG(DOM, "Master Transaction After Init (0x%x)\n", reg_read32(DEVAPC0_MAS_SEC_0));
+#endif
+
+}
+
+static void DAPC_slave_perm_init(void)
+{
+    MSG(DOM, "\nDevice APC slave permission init setup:\n\n");
+
+    /* Set slave permissions here if needed
+     * Default is NO_PROTECTION */
+
+    /* Set SEJ and DAPC to secure RW only */
+    DAPC_SET_SLAVE_PERMISSION(
+        DEVAPC0_D0_APC(0),
+        MODULE_PERMISSION(INFRA_AO_SEJ                        , SEC_RW_ONLY) |
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO_INFRA_PERI   , SEC_RW_ONLY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION(
+        DEVAPC0_D0_APC(1),
+        MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO_MM   , SEC_RW_ONLY)
+    );
+
+    DAPC_SET_SLAVE_PERMISSION(
+        DEVAPC0_D0_APC(2),
+        MODULE_PERMISSION(INFRASYS_DEVICE_APC   , SEC_RW_ONLY)
+    );
+
+}
+
+static void tz_dapc_default_setting(void)
+{
+
+    /* Lock DAPC to secure access only  && unmask debug bit && clear VIO status */
+    reg_write32(DEVAPC_APC_CON,  0x80000001);
+    reg_write32(DEVAPC0_APC_CON, 0x80000001);
+    reg_write32(DEVAPC1_APC_CON, 0x80000001);
+
+    /* Set domain of masters */
+    //DAPC_dom_init();
+
+    /* Set the transaction type of masters */
+    //DAPC_trans_init();
+
+    /* Set the access permission of slaves in domain 0 */
+    DAPC_slave_perm_init();
+}
+
+
+/*=======================================================================*/
+/* API                                                                   */
+/*=======================================================================*/
+void tz_dapc_set_master_transaction(unsigned int  master_index , E_TRANSACTION permisssion_control)
+{
+    reg_set_field(DEVAPC0_MAS_SEC_0 , (0x1 << master_index), permisssion_control);
+}
+
+
+/*=======================================================================*/
+/* INIT FUNCTIONS                                                        */
+/*=======================================================================*/
+
+void tz_dapc_sec_init(void)
+{
+    /* do initial settings */
+    tz_dapc_default_setting();
+}
+
+void tz_dapc_sec_postinit(void)
+{
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..1aec1d9
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,304 @@
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+#define print tl_printf
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp, tmp2;
+    unsigned int ax_pm, ax_pm2;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end <= start)
+        {
+            return -1;
+        }
+    }
+
+    ax_pm  = (access_permission << 16) >> 16;
+    ax_pm2 = (access_permission >> 16);
+
+    switch (region) {
+    case 0:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp2 | ax_pm2, EMI_MPUI_2ND);
+        writel(tmp | ax_pm, EMI_MPUI);
+        break;
+
+    case 1:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUC);
+        writel(tmp2 | ax_pm2, EMI_MPUJ_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ);
+        break;
+
+    case 3:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp2 | ax_pm2, EMI_MPUK_2ND);
+        writel(tmp | ax_pm, EMI_MPUK);
+        break;
+
+    case 5:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK);
+        break;
+
+    case 6:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp2 | ax_pm2, EMI_MPUL_2ND);
+        writel(tmp | ax_pm, EMI_MPUL);
+        break;
+
+    case 7:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL);
+        break;
+
+    case 8:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUA2);
+        writel(tmp2 | ax_pm2, EMI_MPUI2_2ND);
+        writel(tmp | ax_pm, EMI_MPUI2);
+        break;
+
+    case 9:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUB2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI2);
+        break;
+
+    case 10:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUC2);
+        writel(tmp2 | ax_pm2, EMI_MPUJ2_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ2);
+        break;
+
+    case 11:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUD2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ2);
+        break;
+
+    case 12:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUE2);
+        writel(tmp2 | ax_pm2, EMI_MPUK2_2ND);
+        writel(tmp | ax_pm, EMI_MPUK2);
+        break;
+
+    case 13:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUF2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK2);
+        break;
+
+    case 14:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUG2);
+        writel(tmp2 | ax_pm2, EMI_MPUL2_2ND);
+        writel(tmp | ax_pm, EMI_MPUL2);
+        break;
+
+    case 15:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUH2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL2);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+    unsigned int temp;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    // For MT6589
+    //==================================================================================================================
+    //            | Region |  D0(AP)  |  D1(MD0)  |  D2(Conn) |  D3(MD32) |  D4(MM)  |  D5(MD1)  |  D6(MFG)  |  D7(N/A)
+    //------------+---------------------------------------------------------------------------------------------------
+    // Secure OS  |    0   |RW(S)     |Forbidden  |Forbidden  |Forbidden  |RW(S)     |Forbidden  |Forbidden  |Forbidden
+    //------------+---------------------------------------------------------------------------------------------------
+    // MD0 ROM    |    1   |RO(S/NS)  |RO(S/NS)   |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 R/W+   |    2   |Forbidden |No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 ROM    |    3   |RO(S/NS)  |Forbidden  |RO(S/NS)   |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 R/W+   |    4   |Forbidden |Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 Share  |    5   |No protect|No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 Share  |    6   |No protect|Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // AP         |    7   |No protect|Forbidden  |Forbidden  |No protect
+    //===================================================================
+
+    switch (mpu_region) {
+    case SECURE_OS_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    case ATF_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    default:
+        print("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+        return;
+    }
+
+    print("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,      /*START_ADDR*/
+                                        sec_mem_phy_end,      /*END_ADDR*/
+                                        mpu_region,       /*region*/
+                                        sec_mem_mpu_attr);
+
+
+    if(ret)
+    {
+        print("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/main.c b/src/bsp/trustzone/teeloader/mt8512/src/main.c
new file mode 100644
index 0000000..8a9a454
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/main.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "uart.h"
+#include "print.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+extern void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region);
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = UART0_BASE;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+    if (BL31_BASE+BL31_SIZE == TRUSTEDOS_ENTRYPOINT) {
+        /* we can combine the two regions into one */
+        tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                        (BL31_BASE & 0xffff0000) +
+                         BL31_SIZE + TRUSTEDOS_SIZE - 1,
+                        SECURE_OS_MPU_REGION_ID);
+    }
+    else {
+        if (TRUSTEDOS_ENTRYPOINT != 0) {
+            tz_emi_mpu_init((TRUSTEDOS_ENTRYPOINT & 0xffff0000),
+                            (TRUSTEDOS_ENTRYPOINT & 0xffff0000) +
+                             TRUSTEDOS_SIZE - 1,
+                            SECURE_OS_MPU_REGION_ID);
+        }
+
+        tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                        (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                        ATF_MPU_REGION_ID);
+    }
+
+    /* DAPC init */
+    tz_dapc_sec_init();
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    if(bl33_addr)
+        atf_arg->bl33_start_addr = bl33_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/print.c b/src/bsp/trustzone/teeloader/mt8512/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/start.s b/src/bsp/trustzone/teeloader/mt8512/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/uart.c b/src/bsp/trustzone/teeloader/mt8512/src/uart.c
new file mode 100644
index 0000000..b238868
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART0_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART0_BASE));
+
+	writel((unsigned int)c, UART_THR(UART0_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/tllink.lds b/src/bsp/trustzone/teeloader/mt8512/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8516/Makefile b/src/bsp/trustzone/teeloader/mt8516/Makefile
new file mode 100644
index 0000000..61662f1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/Makefile
@@ -0,0 +1,53 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/print.h b/src/bsp/trustzone/teeloader/mt8516/include/print.h
new file mode 100755
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8516/include/typedefs.h
new file mode 100755
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_mpu.h
new file mode 100644
index 0000000..86d4e50
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_mpu.h
@@ -0,0 +1,63 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+#define SEC_R_NSEC_RW       6
+#define SEC_R               7
+
+#define SECURE_OS_MPU_REGION_ID      0
+#define ATF_MPU_REGION_ID            1
+
+#define LOCK                1
+#define UNLOCK              0
+#define SET_ACCESS_PERMISSON(lock, d3, d2, d1, d0) ((lock << 15) | (d3 << 9) | (d2 << 6) | (d1 << 3) | d0)
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_reg.h
new file mode 100644
index 0000000..9757991
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/tz_emi_reg.h
@@ -0,0 +1,68 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS                 0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00205000)
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA            ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB            ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC            ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD            ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE            ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF            ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG            ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH            ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI            ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8516/include/tz_init.h
new file mode 100755
index 0000000..57aa089
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/tz_init.h
@@ -0,0 +1,79 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TZ_INIT_H__
+#define __TZ_INIT_H__
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x41e00000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+    u32 atf_magic;
+    u32 tee_support;
+    u32 tee_entry;
+    u32 tee_boot_arg_addr;
+    u32 hwuid[4];     // HW Unique id for t-base used
+    u32 HRID[2];      // HW random id for t-base used
+    u32 atf_log_port;
+    u32 atf_log_baudrate;
+    u32 atf_log_buf_start;
+    u32 atf_log_buf_size;
+    u32 atf_irq_num;
+    u32 devinfo[DEVINFO_SIZE];
+    u32 atf_aee_debug_buf_start;
+    u32 atf_aee_debug_buf_size;
+} atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* __TZ_INIT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8516/include/uart.h b/src/bsp/trustzone/teeloader/mt8516/include/uart.h
new file mode 100644
index 0000000..b348fdb
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART1_BASE         (IO_PHYS + 0x01005000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8516/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8516/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..3c8b468
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,188 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end < start)
+        {
+            return -1;
+        }
+    }
+
+    switch (region) {
+    case 0:
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp | access_permission, EMI_MPUI);
+        break;
+
+    case 1:
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp | (access_permission << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUC);
+        writel(tmp | access_permission, EMI_MPUJ);
+        break;
+
+    case 3:
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp | (access_permission << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp | access_permission, EMI_MPUK);
+        break;
+
+    case 5:
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp | (access_permission << 16), EMI_MPUK);
+        break;
+
+    case 6:
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp | access_permission, EMI_MPUL);
+        break;
+
+    case 7:
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp | (access_permission << 16), EMI_MPUL);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+    unsigned int temp;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch (mpu_region) {
+    case SECURE_OS_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        tl_printf(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        tl_printf(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    case ATF_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        tl_printf(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        tl_printf(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    default:
+        tl_printf("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+        return;
+    }
+
+    tl_printf("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,      /*START_ADDR*/
+                                        sec_mem_phy_end,      /*END_ADDR*/
+                                        mpu_region,       /*region*/
+                                        sec_mem_mpu_attr);
+
+
+    if(ret)
+    {
+        tl_printf("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8516/src/main.c b/src/bsp/trustzone/teeloader/mt8516/src/main.c
new file mode 100644
index 0000000..c426302
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/src/main.c
@@ -0,0 +1,112 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = 0x11005000;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+    tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                    (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                    ATF_MPU_REGION_ID);
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8516/src/print.c b/src/bsp/trustzone/teeloader/mt8516/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8516/src/start.s b/src/bsp/trustzone/teeloader/mt8516/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8516/src/uart.c b/src/bsp/trustzone/teeloader/mt8516/src/uart.c
new file mode 100644
index 0000000..2126b16
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8516/tllink.lds b/src/bsp/trustzone/teeloader/mt8516/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8516/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8516/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8516/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8518/Makefile b/src/bsp/trustzone/teeloader/mt8518/Makefile
new file mode 100644
index 0000000..bec229d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/Makefile
@@ -0,0 +1,53 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/print.h b/src/bsp/trustzone/teeloader/mt8518/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8518/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_mpu.h
new file mode 100644
index 0000000..86d4e50
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_mpu.h
@@ -0,0 +1,63 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+#define SEC_R_NSEC_RW       6
+#define SEC_R               7
+
+#define SECURE_OS_MPU_REGION_ID      0
+#define ATF_MPU_REGION_ID            1
+
+#define LOCK                1
+#define UNLOCK              0
+#define SET_ACCESS_PERMISSON(lock, d3, d2, d1, d0) ((lock << 15) | (d3 << 9) | (d2 << 6) | (d1 << 3) | d0)
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_reg.h
new file mode 100644
index 0000000..9757991
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/tz_emi_reg.h
@@ -0,0 +1,68 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS                 0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00205000)
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA            ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB            ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC            ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD            ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE            ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF            ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG            ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH            ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI            ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8518/include/tz_init.h
new file mode 100644
index 0000000..6f4bba3
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/tz_init.h
@@ -0,0 +1,81 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TZ_INIT_H__
+#define __TZ_INIT_H__
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x41e00000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+    u32 atf_magic;
+    u32 tee_support;
+    u32 tee_entry;
+    u32 tee_boot_arg_addr;
+    u32 hwuid[4];     // HW Unique id for t-base used
+    u32 HRID[2];      // HW random id for t-base used
+    u32 atf_log_port;
+    u32 atf_log_baudrate;
+    u32 atf_log_buf_start;
+    u32 atf_log_buf_size;
+    u32 atf_irq_num;
+    u32 devinfo[DEVINFO_SIZE];
+    u32 atf_aee_debug_buf_start;
+    u32 atf_aee_debug_buf_size;
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern int teeloader_prepare_tee(void *paddr);
+
+#endif /* __TZ_INIT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8518/include/uart.h b/src/bsp/trustzone/teeloader/mt8518/include/uart.h
new file mode 100644
index 0000000..b348fdb
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART1_BASE         (IO_PHYS + 0x01005000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8518/prebuilt/HwCryptoLib.a b/src/bsp/trustzone/teeloader/mt8518/prebuilt/HwCryptoLib.a
new file mode 100644
index 0000000..4d87bfc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/prebuilt/HwCryptoLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8518/prebuilt/libsec_img.a b/src/bsp/trustzone/teeloader/mt8518/prebuilt/libsec_img.a
new file mode 100644
index 0000000..0474c7e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/prebuilt/libsec_img.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8518/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8518/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..3c8b468
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,188 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end < start)
+        {
+            return -1;
+        }
+    }
+
+    switch (region) {
+    case 0:
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp | access_permission, EMI_MPUI);
+        break;
+
+    case 1:
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp | (access_permission << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUC);
+        writel(tmp | access_permission, EMI_MPUJ);
+        break;
+
+    case 3:
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp | (access_permission << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp | access_permission, EMI_MPUK);
+        break;
+
+    case 5:
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp | (access_permission << 16), EMI_MPUK);
+        break;
+
+    case 6:
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp | access_permission, EMI_MPUL);
+        break;
+
+    case 7:
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp | (access_permission << 16), EMI_MPUL);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+    unsigned int temp;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    switch (mpu_region) {
+    case SECURE_OS_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        tl_printf(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        tl_printf(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    case ATF_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        tl_printf(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        tl_printf(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    default:
+        tl_printf("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+        return;
+    }
+
+    tl_printf("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,      /*START_ADDR*/
+                                        sec_mem_phy_end,      /*END_ADDR*/
+                                        mpu_region,       /*region*/
+                                        sec_mem_mpu_attr);
+
+
+    if(ret)
+    {
+        tl_printf("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8518/src/main.c b/src/bsp/trustzone/teeloader/mt8518/src/main.c
new file mode 100644
index 0000000..20ed23c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/src/main.c
@@ -0,0 +1,114 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = 0x11005000;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+    teeloader_prepare_tee((void *)TRUSTEDOS_ENTRYPOINT);
+
+    tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                    (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                    ATF_MPU_REGION_ID);
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8518/src/print.c b/src/bsp/trustzone/teeloader/mt8518/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8518/src/start.s b/src/bsp/trustzone/teeloader/mt8518/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8518/src/uart.c b/src/bsp/trustzone/teeloader/mt8518/src/uart.c
new file mode 100644
index 0000000..2126b16
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8518/tllink.lds b/src/bsp/trustzone/teeloader/mt8518/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8518/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8518/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8518/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8521/Makefile b/src/bsp/trustzone/teeloader/mt8521/Makefile
new file mode 100644
index 0000000..8c0efe0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/Makefile
@@ -0,0 +1,49 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: $(DIR_SRC)/%.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DTL_VERIFY_ENABLE=${TL_VERIFY_ENABLE} -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -c $^ -o $@ 
+
+$(DIR_OBJ)/%.o: $(DIR_SRC)/%.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_dec_key.py b/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_dec_key.py
new file mode 100755
index 0000000..213c87e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_dec_key.py
@@ -0,0 +1,149 @@
+# This script modfiy teeloader tz_keys.h MTEE_IMG_VFY_PUBK item when customer set they own keys
+
+import os
+import struct
+import sys
+import binascii
+
+IMG_KEY_PATH = "./teeloader/include"
+IMG_KEY_NAME = "mtee_key.pem"
+
+TARGET_H_FILE_PATH = "./teeloader/include"
+TARGET_H_FILE_NAME = "tz_keys.h"
+
+def parse_key(keyfile):
+	temp_key_file = "%s.temp" % keyfile
+	if os.path.exists(temp_key_file):
+		os.remove(temp_key_file)
+
+	cmdline = "openssl rsa -text -in %s -pubout > %s" % (keyfile, temp_key_file)
+	os.system(cmdline)
+	#check if keyfile generated success
+	if not os.path.exists(temp_key_file):
+		print "[error] command line excute failed: %s , please check you linux environment" % cmdline
+		exit(-1)
+
+	#parse keys
+	#read keyfile
+	lines = ""
+	for line in open(temp_key_file):
+		lines += line
+
+	#replace \r \next
+	lines = lines.replace("\n", "")
+	lines = lines.replace(" ", "")
+
+	#get public key
+	#from modulus to publicExponent
+	start_idx = lines.find("modulus:") + len("modulus:")
+	end_idx = lines.find("publicExponent")
+	public_key = lines[start_idx:end_idx]
+	if public_key[:2] == "00":
+		public_key = public_key[2:]
+	public_key = public_key.replace(":", "")
+	print "public_key :" + public_key
+
+	#get private key
+	#from privateExponent to prime1
+	start_idx = lines.find("privateExponent:") + len("privateExponent:")
+	end_idx = lines.find("prime1")
+	private_key = lines[start_idx:end_idx]
+	if private_key[:2] == "00":
+		private_key = private_key[2:]
+	private_key = private_key.replace(":", "")
+	print "\nprivate_key:" + private_key
+
+	os.remove(temp_key_file)
+
+	return (public_key, private_key)
+
+def string_to_bin(string,output_file):
+	if os.path.exists(output_file):
+		os.remove(output_file)
+
+	if (len(string) != 256*2):
+		print "[error] key length is not 256, please check"
+		exit(-1)
+
+	of = open(output_file, 'wb')
+
+	for i in range(0,len(string),2):
+		num=(int(string[i],16)<<4) + int(string[i+1],16)
+		byte=struct.pack('B',num)
+		of.write(byte)
+
+	of.close
+
+def bin_file_to_h_file(in_bin_file,out_h_file):
+	if not os.path.exists(in_bin_file):
+		print "[error] File %s not exist, please check" % in_bin_file
+		exit(-2)
+
+	if os.path.exists(out_h_file):
+		os.remove(out_h_file)
+
+	of = open(out_h_file, 'w')
+
+	j = 0
+	with open(in_bin_file, 'rb') as f:
+		content = f.read()
+		for i in range(len(content)):
+			if j % 8 == 0:
+				of.write("\n    ")
+			j += 1
+
+			of.write("0x%s," % binascii.hexlify(content[i])),
+		of.write("\n")
+
+	f.close()
+	of.close()
+
+def gen_final_h_file(in_h_file,out_h_file):
+	if not os.path.exists(in_h_file):
+		print "[error] File %s not exist, please check" % in_h_file
+		exit(-2)
+
+	if os.path.exists(out_h_file):
+		os.remove(out_h_file)
+
+	inf = open(in_h_file, 'r')
+	of = open(out_h_file, 'w')
+
+	of.write("u8 MTEE_IMG_VFY_PUBK[256] = {")
+	of.write(inf.read())
+	of.write("};\n")
+
+	inf.close()
+	of.close()
+
+if __name__ == "__main__":
+	key_file_path = IMG_KEY_PATH + "/" + IMG_KEY_NAME
+	if not os.path.exists(key_file_path):
+		print "[error] File %s not exist, please check" % key_file_path
+		exit(-1)
+
+	(img_auth_public_key, img_auth_private_key) = parse_key(key_file_path)
+
+	public_key_out_file = "%s.pub_out" % key_file_path
+	private_key_out_file = "%s.pri_out" % key_file_path
+
+	string_to_bin(img_auth_public_key,public_key_out_file)
+	string_to_bin(img_auth_private_key,private_key_out_file)
+
+	h_file = "%s.temp" % public_key_out_file 
+	bin_file_to_h_file(public_key_out_file,h_file);
+
+	final_h_file = "%s.h" % h_file
+	gen_final_h_file(h_file,final_h_file)
+
+	target_h_file = TARGET_H_FILE_PATH + "/" + TARGET_H_FILE_NAME
+	cmd="cp -f %s %s" %(final_h_file , target_h_file)
+	os.system(cmd)
+
+	temp_file = "./teeloader/include/mtee_key.pem.temp"
+	if os.path.exists(temp_file):
+		os.remove(temp_file)
+	os.remove(h_file)
+	os.remove(final_h_file)
+	os.remove(public_key_out_file)
+	os.remove(private_key_out_file)
diff --git a/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_enc_key.py b/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_enc_key.py
new file mode 100755
index 0000000..b39aa05
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/cus_tzimg_enc_key.py
@@ -0,0 +1,80 @@
+# This script modfiy TRUSTZONE_IMG_PROTECT_CFG.ini AUTH_PARAM_N and AUTH_PARAM_D items when customer set they own keys
+
+import os
+import sys
+
+TARGET_PLATFORM = sys.argv[1]
+MTEE_IMG_KEY_FILE = "./teeloader/include/mtee_key.pem"
+TRUSTZONE_IMG_PROTECT_CFG_FILE = "./mtee/build/cfg/" + TARGET_PLATFORM + "/TRUSTZONE_IMG_PROTECT_CFG.ini"
+TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP = "./mtee/build/cfg/" + TARGET_PLATFORM + "/TRUSTZONE_IMG_PROTECT_CFG_TEMP.ini"
+
+def parse_key(keyfile):
+	temp_key_file = "%s.temp" % keyfile
+	cmdline = "openssl rsa -text -in %s -pubout > %s" % (keyfile, temp_key_file)
+	os.system(cmdline)
+	#check if keyfile generated success
+	if not os.path.exists(temp_key_file):
+		print "[error] command line excute failed: %s , please check you linux environment" % cmdline
+		exit(-1)
+
+	#parse keys
+	#read keyfile
+	lines = ""
+	for line in open(temp_key_file):
+		lines += line
+
+	#replace \r \next
+	lines = lines.replace("\n", "")
+	lines = lines.replace(" ", "")
+
+	#get public key
+	#from modulus to publicExponent
+	start_idx = lines.find("modulus:") + len("modulus:")
+	end_idx = lines.find("publicExponent")
+	public_key = lines[start_idx:end_idx]
+	if public_key[:2] == "00":
+		public_key = public_key[2:]
+	public_key = public_key.replace(":", "")
+	#print "public_key :" + public_key
+
+	#get private key
+	#from privateExponent to prime1
+	start_idx = lines.find("privateExponent:") + len("privateExponent:")
+	end_idx = lines.find("prime1")
+	private_key = lines[start_idx:end_idx]
+	if private_key[:2] == "00":
+		private_key = private_key[2:]
+	private_key = private_key.replace(":", "")
+	#print "private_key:" + private_key
+
+	os.remove(temp_key_file)
+
+	return (public_key, private_key)
+
+#check paramters
+if len(sys.argv) < 2:
+	print "miss parameter"
+	print "usage: python cus_mtee_enc_key.py platform(ex: mt2701)\n"
+
+#generate temp file used to modify original config
+if os.path.exists(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP):
+	os.remove(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP)
+cmd = "cp -f " + TRUSTZONE_IMG_PROTECT_CFG_FILE + " " + TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP
+os.system(cmd)
+
+#modify AUTH_PARAM_N and AUTH_PARAM_D
+(img_auth_public_key, img_auth_private_key) = parse_key(MTEE_IMG_KEY_FILE)
+img_auth_key_list = open(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP).readlines()
+tmp = open(TRUSTZONE_IMG_PROTECT_CFG_FILE, "w+")
+for i in range(0, len(img_auth_key_list)):
+	if img_auth_key_list[i].startswith("AUTH_PARAM_N"):
+		img_auth_key_list[i] = "AUTH_PARAM_N = 0x" + img_auth_public_key + "\n"
+		tmp.write(img_auth_key_list[i])
+	elif img_auth_key_list[i].startswith("AUTH_PARAM_D"):
+		img_auth_key_list[i] = "AUTH_PARAM_D = 0x" + img_auth_private_key + "\n"
+		tmp.write(img_auth_key_list[i])
+	else:
+		tmp.write(img_auth_key_list[i])
+
+#job done, remove temp file
+os.remove(TRUSTZONE_IMG_PROTECT_CFG_FILE_TEMP)
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/blkdev.h b/src/bsp/trustzone/teeloader/mt8521/include/blkdev.h
new file mode 100644
index 0000000..64077dd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/blkdev.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef BLKDEV_H
+#define BLKDEV_H
+
+#include "typedefs.h"
+
+typedef struct blkdev blkdev_t;
+
+struct blkdev {
+	u32 type;       /* block device type */
+	u32 blksz;      /* block size. (read/write unit) */
+	u32 erasesz;    /* erase size */
+	u32 blks;       /* number of blocks in the device */
+	u32 offset;     /* user area offset in blksz unit */
+	u8 *blkbuf;     /* block size buffer */
+	void *priv;     /* device private data */    
+	blkdev_t *next; /* next block device */
+	int (*bread)(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+	int (*bwrite)(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+};
+
+extern int blkdev_register(blkdev_t *bdev);
+extern int blkdev_read(blkdev_t *bdev, u64 src, u32 size, u8 *dst, u32 part_id);
+extern int blkdev_write(blkdev_t *bdev, u64 dst, u32 size, u8 *src, u32 part_id);
+extern int blkdev_bread(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+extern int blkdev_bwrite(blkdev_t *bdev, u32 blknr, u32 blks, u8 *buf, u32 part_id);
+extern blkdev_t *blkdev_get(u32 type);
+
+#endif /* BLKDEV_H */
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/buffer.h b/src/bsp/trustzone/teeloader/mt8521/include/buffer.h
new file mode 100644
index 0000000..05c8568
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/buffer.h
@@ -0,0 +1,75 @@
+/*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*/
+/* MediaTek Inc. (C) 2016. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver's
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef BUFFER_ADDR_H
+#define BUFFER_ADDR_H
+
+#include "dram_buffer.h"
+
+#define SEC_SECRO_BUFFER_START      sec_secro_buf
+#define SEC_SECRO_BUFFER_LENGTH     DRAM_SEC_SECRO_BUFFER_LENGTH
+
+#define SEC_WORKING_BUFFER_START    sec_working_buf
+#define SEC_WORKING_BUFFER_LENGTH   DRAM_SEC_WORKING_BUFFER_LENGTH
+
+#define SEC_UTIL_BUFFER_START       sec_util_buf
+#define SEC_UTIL_BUFFER_LENGTH      DRAM_SEC_UTIL_BUFFER_LENGTH
+
+/*SecLib.a use DRAM*/
+#define SEC_LIB_HEAP_START          sec_lib_heap_buf
+#define SEC_LIB_HEAP_LENGTH         DRAM_SEC_LIB_HEAP_LENGTH
+
+/*For v3 verify check buffer */
+#define SEC_IMG_BUFFER_START        sec_img_buf
+#define SEC_IMG_BUFFER_LENGTH       DRAM_SEC_IMG_BUFFER_LENGTH
+
+#define SEC_CHUNK_BUFFER_START      sec_chunk_buf
+#define SEC_CHUNK_BUFFER_LENGTH     DRAM_SEC_CHUNK_BUFFER_LENGTH
+
+#define DA_RAM_ADDR                 (CFG_DA_RAM_ADDR)
+#define DA_RAM_LENGTH               (0x30000)
+
+#define DA_RAM_RELOCATE_ADDR        (CFG_DA_RAM_ADDR + DA_RAM_LENGTH)
+#define DA_RAM_RELOCATE_LENGTH      (DA_RAM_LENGTH)
+
+#define  sec_secro_buf    g_dram_buf->sec_secro_buf 
+#define  sec_working_buf  g_sec_buf.sram_sec_working_buf
+#define  sec_util_buf     g_dram_buf->sec_util_buf
+#define  sec_lib_heap_buf g_dram_buf->sec_lib_heap_buf
+#define  sec_img_buf      g_sec_buf.sram_sec_img_buf
+#define  sec_chunk_buf    g_dram_buf->sec_chunk_buf
+#endif
+
+
+
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/dram_buffer.h b/src/bsp/trustzone/teeloader/mt8521/include/dram_buffer.h
new file mode 100644
index 0000000..df86f38
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/dram_buffer.h
@@ -0,0 +1,142 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+ 
+#ifndef DRAM_BUFFER_H 
+#define DRAM_BUFFER_H
+
+#include "partition.h"
+
+#define BMT_BUFFER_SIZE     0x10000
+#define PART_HDR_BUF_SIZE 512
+#define GPT_BUFFER_SIZE    (0x4000)
+#define STORAGE_BUFFER_SIZE 0x10000
+#define IMG_HDR_BUF_SIZE 512
+#define LOG_BUFFER_MAX_SIZE             (0x10000)
+#define DRAM_SEC_SECRO_BUFFER_LENGTH     (0x3000)
+#define DRAM_SEC_WORKING_BUFFER_LENGTH   0x2000  
+#define DRAM_SEC_UTIL_BUFFER_LENGTH      0x1000   
+#define DRAM_SEC_LIB_HEAP_LENGTH         0x4000   
+#define DRAM_SEC_IMG_BUFFER_LENGTH       0x3000    
+#define DRAM_SEC_CHUNK_BUFFER_LENGTH     0x100000 
+#define CFG_DRAM_ADDR                   (0x00240000)
+#define MAX_MAIN_SIZE                (0x1000)
+#define MAX_SPAR_SIZE                (0x80)
+#define BMT_DAT_BUFFER_SIZE         (MAX_MAIN_SIZE + MAX_SPAR_SIZE) 
+#define PMT_DAT_BUFFER_SIZE         (MAX_MAIN_SIZE + MAX_SPAR_SIZE)
+#define PMT_READ_BUFFER_SIZE        (MAX_MAIN_SIZE)
+#define NAND_NFI_BUFFER_SIZE          0x1000
+#define PART_MAX_NUM   20
+
+#if CFG_BYPASS_EMI
+typedef struct {
+	u8 bmt_buf[0x1000];
+	u8 bmt_dat_buf[BMT_DAT_BUFFER_SIZE];
+	u8 nand_nfi_buf[0x1000];
+	part_hdr_t part_hdr_buf[1];
+	u32 crc32_table[256];
+	u8 pgpt_header_buf[512];
+	u8 sgpt_header_buf[512];
+	u8 pgpt_entries_buf[GPT_BUFFER_SIZE];
+	u8 sgpt_entries_buf[GPT_BUFFER_SIZE];
+	unsigned char storage_buffer[16];
+	u8 img_hdr_buf[IMG_HDR_BUF_SIZE];
+	unsigned int part_num;
+	part_hdr_t   part_info[2];
+	part_t  partition_info[2];
+#ifdef MTK_EMMC_SUPPORT
+	struct part_meta_info meta_info[1];
+#endif
+	u32 bootarg;
+	u8 log_dram_buf[0x1000];
+	u8  sec_secro_buf[DRAM_SEC_SECRO_BUFFER_LENGTH];
+	u8  sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];/*This dram Buffer not used for security concern*/
+	u8  sec_util_buf[DRAM_SEC_UTIL_BUFFER_LENGTH];
+	u8  sec_lib_heap_buf[DRAM_SEC_LIB_HEAP_LENGTH];
+	u8  sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];        /*This dram Buffer not used for security concern*/
+	u8  sec_chunk_buf[0x4000];
+	u32 *boottag; 
+} dram_buf_t;
+#else
+typedef struct {
+	/*bmt.c*/
+	u8 bmt_buf[BMT_BUFFER_SIZE];
+	u8 bmt_dat_buf[BMT_DAT_BUFFER_SIZE];
+	/*nand.c*/
+	u8 nand_nfi_buf[NAND_NFI_BUFFER_SIZE];
+	
+	/*download.c*/
+	part_hdr_t part_hdr_buf[PART_HDR_BUF_SIZE];  
+	/*efi.c*/
+	u32 crc32_table[256];
+	u8 pgpt_header_buf[512];
+	u8 sgpt_header_buf[512];
+	u8 pgpt_entries_buf[GPT_BUFFER_SIZE];
+	u8 sgpt_entries_buf[GPT_BUFFER_SIZE];
+	/*mmc_common_inter.c*/
+	unsigned char storage_buffer[STORAGE_BUFFER_SIZE];
+	/*partition.c*/
+	u8 img_hdr_buf[IMG_HDR_BUF_SIZE];
+	unsigned int part_num;
+	part_hdr_t   part_info[PART_MAX_NUM];
+	part_t  partition_info[128];
+	
+#ifdef MTK_EMMC_SUPPORT
+	struct part_meta_info meta_info[128];
+#endif
+	u32 bootarg;
+	u8 log_dram_buf[LOG_BUFFER_MAX_SIZE];
+	u8  sec_secro_buf[DRAM_SEC_SECRO_BUFFER_LENGTH];
+	u8  sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];/*This dram Buffer not used for security concern*/
+	u8  sec_util_buf[DRAM_SEC_UTIL_BUFFER_LENGTH];
+	u8  sec_lib_heap_buf[DRAM_SEC_LIB_HEAP_LENGTH];
+	u8  sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];        /*This dram Buffer not used for security concern*/
+	u8  sec_chunk_buf[DRAM_SEC_CHUNK_BUFFER_LENGTH]; 
+	u32 *boottag;
+} dram_buf_t;
+#endif
+
+typedef struct {
+	u8 sram_sec_working_buf[DRAM_SEC_WORKING_BUFFER_LENGTH];
+	u8 sram_sec_img_buf[DRAM_SEC_IMG_BUFFER_LENGTH];
+} sec_buf_t;
+
+void init_dram_buffer();
+u64 platform_memory_size(void);
+dram_buf_t *g_dram_buf;
+sec_buf_t  g_sec_buf;
+
+#endif /*DRAM_BUFFER_H*/
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/partition.h b/src/bsp/trustzone/teeloader/mt8521/include/partition.h
new file mode 100644
index 0000000..7c0fb8f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/partition.h
@@ -0,0 +1,94 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PARTITION_H
+#define PARTITION_H
+
+#include "typedefs.h"
+#include "blkdev.h"
+
+#define PART_HEADER_DEFAULT_ADDR    (0xFFFFFFFF)
+#define LOAD_ADDR_MODE_BACKWARD     (0x00000000)
+#define PART_MAGIC          0x58881688
+
+typedef union {
+	struct {
+		unsigned int magic;     /* partition magic */
+		unsigned int dsize;     /* partition data size */
+		char name[32];          /* partition name */
+		unsigned int maddr;     /* partition memory address */
+		unsigned int mode;      /* memory addressing mode */
+	} info;
+	unsigned char data[512];
+} part_hdr_t;
+
+#if 1
+#define PART_META_INFO_NAMELEN  64
+#define PART_META_INFO_UUIDLEN  16
+
+struct part_meta_info {
+	u8 name[PART_META_INFO_NAMELEN];
+	u8 uuid[PART_META_INFO_UUIDLEN];
+};
+
+typedef struct {
+	unsigned long start_sect;
+	unsigned long nr_sects;
+	unsigned int part_id;
+	struct part_meta_info *info;
+} part_t;
+#else
+typedef struct {
+	unsigned char *name;        /* partition name */
+	unsigned long startblk;     /* partition start blk */
+	unsigned long size;         /* partition size */
+	unsigned long blks;         /* partition blks */
+	unsigned long flags;        /* partition flags */
+	unsigned int part_id;
+} part_t;
+#endif
+
+extern int part_init(void);
+extern part_t *part_get(char *name);
+extern int part_load(blkdev_t *bdev, part_t *part, u32 *addr, u32 offset, u32 *size);
+extern void part_dump(void);
+
+extern part_t *get_part(char *name);
+extern void put_part(part_t *part);
+extern int part_load_raw_part(blkdev_t *bdev, part_t *part, u32 *addr, u32 offset, u32 *size);
+
+#endif /* PARTITION_H */
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/print.h b/src/bsp/trustzone/teeloader/mt8521/include/print.h
new file mode 100644
index 0000000..50e2385
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/print.h
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void dbg_print(char *sz, ...);
+extern void print(char *sz, ...);
+extern void log_buf_ctrl(int drambuf);
+extern void log_ctrl(int enable);
+extern int  log_status(void);
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/stdlib.h b/src/bsp/trustzone/teeloader/mt8521/include/stdlib.h
new file mode 100644
index 0000000..91eb793
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/stdlib.h
@@ -0,0 +1,44 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __STDLIB_H__
+#define __STDLIB_H__
+
+int atoi(const char *s);
+long long atoll(const char *num);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/string.h b/src/bsp/trustzone/teeloader/mt8521/include/string.h
new file mode 100644
index 0000000..5436663
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/string.h
@@ -0,0 +1,48 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#endif /* STRING_H */
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8521/include/typedefs.h
new file mode 100644
index 0000000..dcf93d1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/typedefs.h
@@ -0,0 +1,303 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#define __NOBITS_SECTION__(x) __attribute__((section(#x ", \"aw\", %nobits@")))
+#define __SRAM__  __NOBITS_SECTION__(.secbuf)
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+//------------------------------------------------------------------
+
+typedef volatile unsigned char *P_kal_uint8;
+typedef volatile unsigned short *P_kal_uint16;
+typedef volatile unsigned int *P_kal_uint32;
+
+typedef long LONG;
+typedef unsigned char UBYTE;
+typedef short SHORT;
+
+typedef signed char kal_int8;
+typedef signed short kal_int16;
+typedef signed int kal_int32;
+typedef long long kal_int64;
+typedef unsigned char kal_uint8;
+typedef unsigned short kal_uint16;
+typedef unsigned int kal_uint32;
+typedef unsigned long long kal_uint64;
+typedef char kal_char;
+
+typedef unsigned int *UINT32P;
+typedef volatile unsigned short *UINT16P;
+typedef volatile unsigned char *UINT8P;
+typedef unsigned char *U8P;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char U8;
+typedef signed char S8;
+typedef unsigned short U16;
+typedef signed short S16;
+typedef unsigned int U32;
+typedef signed int S32;
+typedef unsigned long long U64;
+typedef signed long long S64;
+typedef unsigned char bool;
+
+//------------------------------------------------------------------
+
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+#define BITS_PER_LONG               32
+/* Dma addresses are 32-bits wide.  */
+typedef u32 dma_addr_t;
+
+//------------------------------------------------------------------
+
+#define FALSE                       0
+#define TRUE                        1
+
+#define IMPORT  EXTERN
+#ifndef __cplusplus
+#define EXTERN  extern
+#else
+#define EXTERN  extern "C"
+#endif
+#define LOCAL     static
+#define GLOBAL
+#define EXPORT    GLOBAL
+
+#define EQ        ==
+#define NEQ       !=
+#define AND       &&
+#define OR        ||
+#define XOR(A,B)  ((!(A) AND (B)) OR ((A) AND !(B)))
+
+#ifndef FALSE
+#define FALSE   0
+#endif
+
+#ifndef TRUE
+#define TRUE    1
+#endif
+
+#ifndef NULL
+#define NULL    0
+#endif
+
+enum boolean {
+	false,
+	true
+};
+
+enum {
+	RX,
+	TX,
+	NONE
+};
+
+#ifndef BOOL
+typedef unsigned char BOOL;
+#endif
+
+typedef enum {
+	KAL_FALSE = 0,
+	KAL_TRUE = 1,
+} kal_bool;
+
+/*==== EXPORTED MACRO ===================================================*/
+
+#define MAXIMUM(A,B)                (((A)>(B))?(A):(B))
+#define MINIMUM(A,B)                (((A)<(B))?(A):(B))
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+    (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+    (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+    (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+    (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x)                   READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y)               WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y)               OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y)               OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z)           OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x)                  READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y)              WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y)              OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y)              OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z)          OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x)                  READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y)              WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y)              OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y)              OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z)          OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr)              INREG8(addr)
+#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
+
+#define DRV_Reg16(addr)             INREG16(addr)
+#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
+
+#define DRV_Reg32(addr)             INREG32(addr)
+#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
+
+// !!! DEPRECATED, WILL BE REMOVED LATER !!!
+#define DRV_Reg(addr)               DRV_Reg16(addr)
+#define DRV_WriteReg(addr, data)    DRV_WriteReg16(addr, data)
+#define DRV_SetReg(addr, data)      DRV_SetReg16(addr, data)
+#define DRV_ClrReg(addr, data)      DRV_ClrReg16(addr, data)
+
+#define __raw_readb(REG)            DRV_Reg8(REG)
+#define __raw_readw(REG)            DRV_Reg16(REG)
+#define __raw_readl(REG)            DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG)      DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG)      DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG)      DRV_WriteReg32(REG,VAL)
+
+#define dsb()	\
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
+
+#if 0
+extern void platform_assert(char *file, int line, char *expr);
+
+#define ASSERT(expr) \
+    do{ if(!(expr)){platform_assert(__FILE__, __LINE__, #expr);} }while(0)
+#endif
+
+// compile time assert 
+//#define COMPILE_ASSERT(condition) ((void)sizeof(char[1 - 2*!!!(condition)]))
+
+#define printf          print
+#define tl_printf       tl_print
+//#define BUG_ON(expr)    ASSERT(!(expr))
+
+#if defined(MACH_TYPE_MT6735M)
+#define printf(fmt, args...)          do{}while(0)
+#endif
+
+//------------------------------------------------------------------
+
+#if 0
+typedef char *va_list;
+#define _INTSIZEOF(n) ( (sizeof(n) + sizeof(int) - 1) & ~(sizeof(int) - 1) )
+#define va_start(ap,v) ( ap = (va_list)&v + _INTSIZEOF(v) )
+#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+#else
+#include <stdarg.h>
+#endif
+
+#define READ_REG(REG)           __raw_readl(REG)
+#define WRITE_REG(VAL, REG)     __raw_writel(VAL, REG)
+
+#ifndef min
+#define min(x, y)   (x < y ? x : y)
+#endif
+#ifndef max
+#define max(x, y)   (x > y ? x : y)
+#endif
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8521/include/tz_init.h
new file mode 100644
index 0000000..948103e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/tz_init.h
@@ -0,0 +1,89 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "tz_keys.h"
+#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+#define DEVINFO_SIZE 4
+
+#define MCUSYS_CFGREG_BASE  (0x10000000 + 0x00200000)
+#define RVBADDRESS_CPU0     (MCUSYS_CFGREG_BASE + 0x38)
+
+/* 
+    RSA2048 public key for verifying mtee image
+    It should be the same as AUTH_PARAM_N in alps\mediatek\custom\mt6752_evb\trustzone\TRUSTZONE_IMG_PROTECT_CFG.ini
+*/
+#define MTEE_IMG_VFY_PUBK_SZ 256
+
+typedef struct {
+	u32 atf_magic;
+	u32 tee_support;
+	u32 tee_entry;
+	u32 tee_boot_arg_addr;
+	u32 hwuid[4];     // HW Unique id for t-base used
+	u32 HRID[2];      // HW random id for t-base used
+	u32 atf_log_port;
+	u32 atf_log_baudrate;
+	u32 atf_log_buf_start;
+	u32 atf_log_buf_size;
+	u32 atf_irq_num;
+	u32 devinfo[DEVINFO_SIZE];
+	u32 atf_aee_debug_buf_start;
+	u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+	u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tee_get_secmem_start(u32 *addr);
+void tee_get_secmem_size(u32 *size);
+void tee_set_entry(u32 addr);
+void tee_set_hwuid(u8 *id, u32 size);
+int  tee_verify_image(u32 *addr, u32 size);
+u32 tee_get_load_addr(u32 maddr);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2);
+
+#endif /* TRUSTZONE_H */
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/tz_keys.h b/src/bsp/trustzone/teeloader/mt8521/include/tz_keys.h
new file mode 100644
index 0000000..c412839
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/tz_keys.h
@@ -0,0 +1,55 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+u8 MTEE_IMG_VFY_PUBK[256] = {
+	0xDA, 0xCD, 0x8B, 0x5F, 0xDA, 0x8A, 0x76, 0x6F, 0xB7, 0xBC, 0xAA, 0x43, 0xF0, 0xB1, 0x69, 0x15,
+	0xCE, 0x7B, 0x47, 0x71, 0x4F, 0x13, 0x95, 0xFD, 0xEB, 0xCF, 0x12, 0xA2, 0xD4, 0x11, 0x55, 0xB0,
+	0xFB, 0x58, 0x7A, 0x51, 0xFE, 0xCC, 0xCB, 0x4D, 0xDA, 0x1C, 0x8E, 0x5E, 0xB9, 0xEB, 0x69, 0xB8,
+	0x6D, 0xAF, 0x2C, 0x62, 0x0F, 0x6C, 0x27, 0x35, 0x21, 0x5A, 0x5F, 0x22, 0xC0, 0xB6, 0xCE, 0x37,
+	0x7A, 0xA0, 0xD0, 0x7E, 0xB3, 0x8E, 0xD3, 0x40, 0xB5, 0x62, 0x9F, 0xC2, 0x89, 0x04, 0x94, 0xB0,
+	0x78, 0xA6, 0x3D, 0x6D, 0x07, 0xFD, 0xEA, 0xCD, 0xBE, 0x3E, 0x7F, 0x27, 0xFD, 0xE4, 0xB1, 0x43,
+	0xF4, 0x9D, 0xB4, 0x97, 0x14, 0x37, 0xE6, 0xD0, 0x0D, 0x9E, 0x18, 0xB5, 0x6F, 0x02, 0xDA, 0xBE,
+	0xB0, 0x00, 0x0B, 0x6E, 0x79, 0x51, 0x6D, 0x0C, 0x80, 0x74, 0xB5, 0xA4, 0x25, 0x69, 0xFD, 0x0D,
+	0x91, 0x96, 0x65, 0x5D, 0x2A, 0x40, 0x30, 0xD4, 0x2D, 0xFE, 0x05, 0xE9, 0xF6, 0x48, 0x83, 0xE6,
+	0xD5, 0xF7, 0x9A, 0x5B, 0xFA, 0x3E, 0x70, 0x14, 0xC9, 0xA6, 0x28, 0x53, 0xDC, 0x1F, 0x21, 0xD5,
+	0xD6, 0x26, 0xF4, 0xD0, 0x84, 0x6D, 0xB1, 0x64, 0x52, 0x18, 0x7D, 0xD7, 0x76, 0xE8, 0x88, 0x6B,
+	0x48, 0xC2, 0x10, 0xC9, 0xE2, 0x08, 0x05, 0x9E, 0x7C, 0xAF, 0xC9, 0x97, 0xFD, 0x2C, 0xA2, 0x10,
+	0x77, 0x5C, 0x1A, 0x5D, 0x9A, 0xA2, 0x61, 0x25, 0x2F, 0xB9, 0x75, 0x26, 0x8D, 0x97, 0x0C, 0x62,
+	0x73, 0x38, 0x71, 0xD5, 0x78, 0x14, 0x09, 0x8A, 0x45, 0x3D, 0xF9, 0x2B, 0xC6, 0xCA, 0x19, 0x02,
+	0x5C, 0xD9, 0xD4, 0x30, 0xF0, 0x2E, 0xE4, 0x6F, 0x80, 0xDE, 0x6C, 0x63, 0xEA, 0x80, 0x2B, 0xEF,
+	0x90, 0x67, 0x3A, 0xAC, 0x4C, 0x66, 0x67, 0xF2, 0x88, 0x3F, 0xB4, 0x50, 0x1F, 0xA7, 0x74, 0x55
+};
diff --git a/src/bsp/trustzone/teeloader/mt8521/include/uart.h b/src/bsp/trustzone/teeloader/mt8521/include/uart.h
new file mode 100644
index 0000000..717090f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+ 
+#ifndef UART_H
+#define UART_H
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART1_BASE         (IO_PHYS + 0x01002000)
+
+int uart_putc(char c);
+
+#endif
+
diff --git a/src/bsp/trustzone/teeloader/mt8521/prebuild/DaVerifyLib.a b/src/bsp/trustzone/teeloader/mt8521/prebuild/DaVerifyLib.a
new file mode 100644
index 0000000..ff62514
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/prebuild/DaVerifyLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8521/prebuild/HwCryptoLib.a b/src/bsp/trustzone/teeloader/mt8521/prebuild/HwCryptoLib.a
new file mode 100644
index 0000000..be64f3e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/prebuild/HwCryptoLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8521/prebuild/SecLib.a b/src/bsp/trustzone/teeloader/mt8521/prebuild/SecLib.a
new file mode 100644
index 0000000..d8be539
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/prebuild/SecLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8521/prebuild/SecPlat.a b/src/bsp/trustzone/teeloader/mt8521/prebuild/SecPlat.a
new file mode 100644
index 0000000..c2a3b26
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/prebuild/SecPlat.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/div0.c b/src/bsp/trustzone/teeloader/mt8521/src/div0.c
new file mode 100644
index 0000000..278cf23
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/div0.c
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#include <typedefs.h>
+
+void __div0(void)
+{
+	//ASSERT(0);
+}
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/dram_buffer.c b/src/bsp/trustzone/teeloader/mt8521/src/dram_buffer.c
new file mode 100644
index 0000000..4547fd6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/dram_buffer.c
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "dram_buffer.h"
+#include "typedefs.h"
+
+#define MOD "[Dram_Buffer]"
+
+dram_buf_t *g_dram_buf = 0;
+
+u64 platform_memory_size(void)
+{
+	/* now use hard code */
+	u64 mem_size = 99;
+	return mem_size;
+}
+
+void init_dram_buffer()
+{
+	u32 structure_size = sizeof(dram_buf_t);
+
+	/*allocate dram_buf */
+	g_dram_buf = BASE_ADDR - 0x200000;
+	memset((void *)&(g_dram_buf->bootarg), 0, sizeof(u32));
+}
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/dummy.s b/src/bsp/trustzone/teeloader/mt8521/src/dummy.s
new file mode 100644
index 0000000..cd4d98c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/dummy.s
@@ -0,0 +1,15 @@
+.globl get_timer
+.type  get_timer, function
+
+.globl part_load
+.type  part_load, function
+
+.globl part_get
+.type  part_get, function
+
+get_timer:
+part_load:
+part_get:
+	mov	pc, lr
+
+
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/init.s b/src/bsp/trustzone/teeloader/mt8521/src/init.s
new file mode 100644
index 0000000..3da06a1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/init.s
@@ -0,0 +1,230 @@
+.section .text.start
+
+.equ MODE_USR       ,0x10
+.equ MODE_FIQ       ,0x11
+.equ MODE_IRQ       ,0x12
+.equ MODE_SVC       ,0x13
+.equ MODE_MON       ,0x16
+.equ MODE_ABT       ,0x17
+.equ MODE_UNDEF     ,0x1B
+.equ MODE_SYS       ,0x1F
+.equ I_BIT          ,0x80
+.equ F_BIT          ,0x40
+.equ INT_BIT        ,0xC0
+
+/* .equ RVBADDRESS_CPU0 ,0x10200038 */
+@.extern sys_stack
+@.extern sys_stack_sz
+@.extern bl31_base_addr
+@.extern rst_vector_base_addr
+/* wenmin: use this hard code to build pass, need check right number */
+sys_stack = 0xBFBF0000
+sys_stack_sz = 0x1000
+bl31_base_addr = 0x31
+rst_vector_base_addr = 0x0
+
+.globl _start
+.type  _start, function
+_start:
+	b resethandler
+bss_start:
+	.word _bss_start
+bss_end:
+	.word _bss_end
+stack:
+	.long sys_stack
+stacksz:
+	.long sys_stack_sz
+tee_entry:
+	.word 0x0
+
+resethandler:
+	ldr r5, =tee_entry
+	str r0, [r5]
+	MOV r0, #0
+	MOV r1, #0
+	MOV r2, #0
+	MOV r3, #0
+	MOV r4, #0
+	MOV r5, #0
+	MOV r6, #0
+	MOV r7, #0
+	MOV r8, #0
+	MOV r9, #0
+	MOV r10, #0
+	MOV r11, #0
+	MOV r12, #0
+	MOV sp, #0
+	MOV lr, #0
+
+	/* CONFIG_ARM_ERRATA_826319 */
+	mrc p15, 0, r8, c1, c0, 0    @ Read System Control Register into Rt
+	bic r8, r8, #0x4             @ disable D-Cache
+	bic r8, r8, #0x1000          @ clear I-Cache
+	mcr p15, 0, r8, c1, c0, 0    @ Write Rt to System Control Register
+
+	/* set the cpu to SVC32 mode */
+	MRS	r0,cpsr
+	BIC	r0,r0,#0x1f
+	ORR	r0,r0,#0xd3
+	MSR	cpsr,r0
+
+	/* disable interrupt */
+	MRS r0, cpsr
+	MOV r1, #INT_BIT
+	ORR r0, r0, r1
+	MSR cpsr_cxsf, r0
+
+	/* enable I+Z+SMP bits and disable D bit */
+	MRC p15, 0, ip, c1, c0, 0
+	ORR ip, ip, #0x1840   /* I+Z+SMP bits */
+	BIC ip, ip, #0x4      /* C bit */
+	MCR p15, 0, ip, c1, c0, 0
+
+clear_bss :
+	LDR r0, bss_start  /* find start of bss segment */
+	LDR r1, bss_end    /* stop here */
+	MOV r2, #0x00000000 /* clear */
+
+	CMP r0, r1
+	BEQ setup_stk
+
+	/*  clear loop... */
+clbss_l :
+	STR r2, [r0]
+	ADD r0, r0, #4
+	CMP r0, r1
+	BNE clbss_l
+
+setup_stk :
+	/* setup stack */
+	LDR r0, stack
+	LDR r1, =stacksz
+
+	/* buffer overflow detect pattern */
+	LDR r2, =0xDEADBEFF
+	STR r2, [r0]
+
+	LDR r1, [r1]
+	SUB r1, r1, #0x04
+	ADD r1, r0, r1
+
+	MOV sp, r1
+
+entry :
+	LDR r0, =tee_entry
+	LDR r0, [r0]
+	B   teeloader_main
+
+.globl jump
+.type  jump, function
+jump:
+	MOV r4, r1   /* r4 argument */
+	MOV r5, r2   /* r5 argument */
+	MOV pc, r0    /* jump to addr */
+
+.globl apmcu_icache_invalidate
+.type  apmcu_icache_invalidate, function
+apmcu_icache_invalidate:
+	MOV r0, #0
+	MCR p15, 0, r0, c7, c5, 0  /* CHECKME: c5 or c1 */
+	BX  lr
+
+.globl apmcu_isb
+.type  apmcu_isb, function
+apmcu_isb:
+	ISB
+	BX  lr
+
+.globl apmcu_disable_icache
+.type  apmcu_disable_icache, function
+apmcu_disable_icache:
+	MOV r0,#0
+	MCR p15,0,r0,c7,c5,6   /* Flush entire branch target cache */
+	MRC p15,0,r0,c1,c0,0
+	BIC r0,r0,#0x1800      /* I+Z bits */
+	MCR p15,0,r0,c1,c0,0
+	BX  lr
+
+.globl apmcu_disable_smp
+.type  apmcu_disable_smp, function
+apmcu_disable_smp:
+	MRC p15,0,r0,c1,c0,1
+	BIC r0,r0,#0x040       /* SMP bit */
+	MCR p15,0,r0,c1,c0,1
+	BX  lr
+
+.section .text.arch64
+.globl jumparch64
+.type  jumparch64, function
+jumparch64:
+	MOV r4, r1   /* r4 argument */
+	MOV r5, r2   /* r5 argument */
+	MOV r6, r0   /* keep LK jump addr */
+	
+	MOV r7, r3   /* r3 = TEE boot entry, relocate to r7 */
+
+	/* setup the reset vector base address after warm reset to Aarch64 */
+	LDR r0, =bl31_base_addr
+	LDR r0,[r0]
+
+	LDR r1, =rst_vector_base_addr
+	LDR r1,[r1]
+	str r0,[r1]
+
+	/* setup the excution state after warm reset: 1:Aarch64, 0:Aarch32 */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #1
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* do warm reset:reset request */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #2
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* set r0 as 0xC000_0000 for ATF OP code check */
+	MOV r0, #0xC0000000
+
+.globl WFI_LOOP
+.type  WFI_LOOP, function
+WFI_LOOP:
+	/* enter WFI to request a warm reset */
+	WFI
+	B WFI_LOOP
+
+.globl jumparch64_slt
+.type  jumparch64_slt, function
+jumparch64_slt:
+	/* setup the reset vector base address after warm reset to Aarch64 */
+	/* ldr r1,=RVBADDRESS_CPU0 */
+	/* ldr r1,[r1] */
+	/* LDR r0, =0x40000000 */
+	LDR r0, =0x40000000
+	LDR r1, =0x10200038
+	str r0,[r1]
+
+	/* setup the excution state after warm reset: 1:Aarch64, 0:Aarch32 */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #1
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* do warm reset:reset request */
+	MRC p15,0,r0,c12,c0,2
+	orr r0, r0, #2
+	MCR p15,0,r0,c12,c0,2
+	DSB
+	ISB
+
+	/* set r0 as 0x40000300 for dtb */
+	ldr r0, =0x40000300
+
+1:
+	/* enter WFI to request a warm reset */
+	WFI
+	B 1b
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/main.c b/src/bsp/trustzone/teeloader/mt8521/src/main.c
new file mode 100644
index 0000000..72f0b16
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/main.c
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/print.c b/src/bsp/trustzone/teeloader/mt8521/src/print.c
new file mode 100644
index 0000000..4c8140a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/print.c
@@ -0,0 +1,287 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "dram_buffer.h"
+#include "uart.h"
+
+#define C_LOG_SRAM_BUF_SIZE (20480)
+static char log_sram_buf[C_LOG_SRAM_BUF_SIZE];
+
+#define LOG_BUFFER_MAX_SIZE (0x10000)
+#define log_dram_buf g_dram_buf->log_dram_buf
+
+char *log_ptr;
+char *log_hdr;
+char *log_end;
+static int g_log_drambuf = 1;
+static int g_log_disable = 0;
+
+static int g_log_miss_chrs = 0;
+
+static void outchar(const char c)
+{
+	if (g_log_disable) {
+		if (log_ptr < log_end)
+			*log_ptr++ = (char)c;
+		else
+			g_log_miss_chrs++;
+	} else {
+		uart_putc(c);
+	}
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void log_buf_ctrl(int drambuf)
+{
+	if (drambuf) {
+		if ((g_log_disable) && (!g_log_drambuf)) {
+			char *buf_ptr = log_hdr;
+			U32 buf_len = log_ptr - log_hdr;
+
+			log_hdr = (char *)log_dram_buf;
+			log_end = log_hdr + LOG_BUFFER_MAX_SIZE;
+			log_ptr = log_hdr;
+			if (buf_len) {
+				memcpy(log_hdr, buf_ptr, buf_len);
+				log_ptr = log_hdr + buf_len;
+			}
+			if (g_log_miss_chrs) {
+				outstr("\n{MISS: ");
+				outdec(g_log_miss_chrs);
+				outstr(" chars}\n");
+				g_log_miss_chrs = 0;
+			}
+		} else if (!g_log_disable) {
+			log_hdr = (char *)log_dram_buf;
+			log_end = log_hdr + LOG_BUFFER_MAX_SIZE;
+			log_ptr = log_hdr;
+		}
+	} else {
+		log_hdr = (char *)log_sram_buf;
+		log_end = log_hdr + C_LOG_SRAM_BUF_SIZE;
+		log_ptr = log_hdr;
+	}
+
+	g_log_drambuf = drambuf ? 1 : 0;
+}
+
+void log_ctrl(int enable)
+{
+	u32 len;
+	char *ptr;
+
+	g_log_disable = enable ? 0 : 1;
+
+	/* flush log and reset log buf ptr */
+	if (enable) {
+		ptr = (char *)log_hdr;
+		len = (u32) log_ptr - (u32) ptr;
+		for (; len; len--) {
+			//outchar(*ptr++);
+		}
+		log_ptr = log_hdr;
+	}
+}
+
+int log_status(void)
+{
+	return g_log_disable == 0 ? 1 : 0;
+}
+
+void dbg_print(char *fmt, ...)
+{
+	print(fmt);
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+#ifdef __ARM_EABI__
+					/* Normally, compiler uses r0 to r6 to pass 32-bit or 64-bit 
+					 * arguments. But with EABI, 64-bit arguments will be aligned 
+					 * to an _even_ numbered register. for example:
+					 *
+					 *   int foo(int a, long long b, int c)
+					 *
+					 *   EABI: r0: a, r1: unused, r2-r3: b, r4: c
+					 *   Normal: r0: a, r1-r2: b, r3:c
+					 * 
+					 * For this reason, need to align to even numbered register
+					 * to retrieve 64-bit argument.
+					 */
+
+					/* odd and unused argument */
+					if (reg & 0x1) {
+						/* 64-bit argument starts from next 32-bit register */
+						reg++;
+						/* ignore this 32-bit register */
+						ltmp = va_arg(vl, unsigned int);
+					}
+					reg++;	/* 64-bit argument uses one more 32-bit register */
+#endif
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+
+	va_end(args);
+}
+
+void tl_print(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/stdlib.c b/src/bsp/trustzone/teeloader/mt8521/src/stdlib.c
new file mode 100644
index 0000000..73c7d1f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/stdlib.c
@@ -0,0 +1,164 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+char *strchr(const char *p, int ch)
+{
+	for (;; ++p) {
+		if (*p == ch)
+			return ((char *)p);
+		if (!*p)
+			return ((char *)NULL);
+	}
+	/* NOTREACHED */
+}
+
+int atoi(const char *s)
+{
+	/* make digits[] size 4 bytes align */
+	static const char digits[12] = "0123456789";	/* legal digits in order */
+	unsigned val = 0;	/* value we're accumulating */
+	int neg = 0;		/* set to true if we see a minus sign */
+
+	/* skip whitespace */
+	while (*s == ' ' || *s == '\t') {
+		s++;
+	}
+
+	/* check for sign */
+	if (*s == '-') {
+		neg = 1;
+		s++;
+	} else if (*s == '+') {
+		s++;
+	}
+
+	/* process each digit */
+	while (*s) {
+		const char *where;
+		unsigned digit;
+
+		/* look for the digit in the list of digits */
+		where = strchr(digits, *s);
+		if (where == 0) {
+			/* not found; not a digit, so stop */
+			break;
+		}
+
+		/* get the index into the digit list, which is the value */
+		digit = (where - digits);
+
+		/* could (should?) check for overflow here */
+
+		/* shift the number over and add in the new digit */
+		val = val * 10 + digit;
+
+		/* look at the next character */
+		s++;
+	}
+
+	/* handle negative numbers */
+	if (neg) {
+		return -val;
+	}
+
+	/* done */
+	return val;
+}
+
+int isdigit(char c)
+{
+	return ((c >= '0') && (c <= '9'));
+}
+
+int isxdigit(char c)
+{
+	return isdigit(c) || ((c >= 'a') && (c <= 'f'))
+	    || ((c >= 'A') && (c <= 'F'));
+}
+
+int hexval(char c)
+{
+	if ((c >= '0') && (c <= '9')) {
+		return c - '0';
+	}
+
+	if ((c >= 'a') && (c <= 'f')) {
+		return c - 'a' + 10;
+	}
+
+	if ((c >= 'A') && (c <= 'F')) {
+		return c - 'A' + 10;
+	}
+}
+
+long long atoll(const char *num)
+{
+	long long value = 0;
+	unsigned long long max;
+	int neg = 0;
+
+	if (num[0] == '0' && num[1] == 'x') {
+		// hex
+		num += 2;
+		while (*num && isxdigit(*num)) {
+			value = value * 16 + hexval(*num++);
+		}
+	} else {
+		// decimal
+		if (num[0] == '-') {
+			neg = 1;
+			num++;
+		}
+		while (*num && isdigit(*num))
+			value = value * 10 + *num++ - '0';
+	}
+
+	if (neg)
+		value = -value;
+
+	max = value;
+	return value;
+}
+
+void longjmperror(void)
+{
+	//ASSERT(0);
+}
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/string.c b/src/bsp/trustzone/teeloader/mt8521/src/string.c
new file mode 100644
index 0000000..aa455ad
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/string.c
@@ -0,0 +1,119 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+	const char *sc;
+
+	for (sc = s; *sc != '\0'; ++sc) {
+	}
+	return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+	signed char __res;
+
+	while (1) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+	}
+	return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+	signed char __res = 0;
+
+	while (count) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+		count--;
+	}
+	return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void *memset(void *s, int c, int count)
+{
+	char *xs = s;
+
+	while (count--)
+		*xs++ = c;
+
+	return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void *memcpy(void *dest, const void *src, int count)
+{
+	char *tmp = dest;
+	const char *s = src;
+
+	while (count--)
+		*tmp++ = *s++;
+
+	return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+	const unsigned char *su1, *su2;
+	int res = 0;
+
+	for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+		if ((res = *su1 - *su2) != 0)
+			break;
+
+	return res;
+}
+
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt8521/src/uart.c b/src/bsp/trustzone/teeloader/mt8521/src/uart.c
new file mode 100644
index 0000000..c42cb04
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+	
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+	
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+	
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8521/tllink.lds b/src/bsp/trustzone/teeloader/mt8521/tllink.lds
new file mode 100644
index 0000000..d55d335
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/tllink.lds
@@ -0,0 +1,51 @@
+OUTPUT_ARCH(arm)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {	
+		*(.text.start)
+	} 
+
+	. = . + 0x01FC;
+	.rom_info ALIGN(4) : {	    	    	    	     
+		*(.data.rom_info)
+	} 
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)        
+	} 
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)        
+	} 
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)        
+	} 
+	.got ALIGN(4) : {
+		*(.got)
+		*(.got.*)        
+	} 
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+	.secbuf ALIGN(4) : {
+		_secbuf_start = .;
+		*(.secbuf)
+		_secbuf_end = .;
+	} 
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8521/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8521/zero_padding.sh
new file mode 100755
index 0000000..79b2c5b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8521/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	#rm ${FILE_DIR}/padding.txt
+fi
diff --git a/src/bsp/trustzone/teeloader/mt8532/Makefile b/src/bsp/trustzone/teeloader/mt8532/Makefile
new file mode 100644
index 0000000..61662f1
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/Makefile
@@ -0,0 +1,53 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+	$(DIR_SRC)/drivers/tz_emi_mpu.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+	@if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+		mkdir -p `dirname $(BIN_TARGET).elf`; \
+	fi
+	sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+	$(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+	-echo "teeloader binary created"
+	$(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+	./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+	@if [ ! -d `dirname $@` ] ; then \
+		mkdir -p `dirname $@`; \
+	fi
+	$(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+	-@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/print.h b/src/bsp/trustzone/teeloader/mt8532/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8532/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bdb4801
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_mpu.h
@@ -0,0 +1,23 @@
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT   0x10000
+#define EMI_PHY_OFFSET       0x40000000
+#define SEC_PHY_SIZE        0x06000000
+
+#define NO_PROTECTION       0
+#define SEC_RW              1
+#define SEC_RW_NSEC_R       2
+#define SEC_RW_NSEC_W       3
+#define SEC_R_NSEC_R        4
+#define FORBIDDEN           5
+
+#define SECURE_OS_MPU_REGION_ID      0
+#define ATF_MPU_REGION_ID            1
+
+#define LOCK                1
+#define UNLOCK              0
+#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | ((((d7) << 9) | ((d6) << 6) | ((d5) << 3) | (d4)) << 16) | (lock << 15))
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_reg.h
new file mode 100644
index 0000000..622d7f2
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/tz_emi_reg.h
@@ -0,0 +1,276 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ * 
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ * 
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS            	    0x10000000
+#define EMI_BASE                (IO_PHYS + 0x00203000)
+
+/*EMI PSRAM (NOR) and DRAM control registers*/
+#define EMI_CONA                 ((P_U32)(EMI_BASE+0x0000))  /* EMI control register for bank 0 */
+#define EMI_CONB                 ((P_U32)(EMI_BASE+0x0008))  /* EMI control register for bank 1 */
+#define EMI_CONC                 ((P_U32)(EMI_BASE+0x0010))  /* EMI control register for bank 2 */
+#define EMI_COND                 ((P_U32)(EMI_BASE+0x0018))  /* EMI control register for bank 3 */
+#define EMI_CONE                 ((P_U32)(EMI_BASE+0x0020))  /* EMI control register for bank 0 */
+#define EMI_CONF                 ((P_U32)(EMI_BASE+0x0028))  /* EMI control register for bank 1 */
+#define EMI_CONG                 ((P_U32)(EMI_BASE+0x0030))  /* EMI control register for bank 0 */
+#define EMI_CONH                 ((P_U32)(EMI_BASE+0x0038))  /* EMI control register for bank 1 */
+#define EMI_CONI                 ((P_U32)(EMI_BASE+0x0040))  /* EMI control register 0 for Mobile-RAM */
+#define EMI_CONJ                 ((P_U32)(EMI_BASE+0x0048))  /* EMI control register 1 for Mobile-RAM */
+#define EMI_CONK                 ((P_U32)(EMI_BASE+0x0050))  /* EMI control register 2 for Mobile-RAM */
+#define EMI_CONL                 ((P_U32)(EMI_BASE+0x0058))  /* EMI control register 3 for Mobile-RAM */
+#define EMI_CONM                 ((P_U32)(EMI_BASE+0x0060))
+#define EMI_CONN                 ((P_U32)(EMI_BASE+0x0068))
+#define CAL_EN                   (1 << 8)
+#define EMI_GENA                 ((P_U32)(EMI_BASE+0x0070))
+#define EMI_REMAP                 EMI_GENA
+#define EMI_DRCT                 ((P_U32)(EMI_BASE+0x0078))
+#define EMI_DDRV                 ((P_U32)(EMI_BASE+0x0080))
+#define EMI_GEND                 ((P_U32)(EMI_BASE+0x0088))
+#define EMI_PPCT                 ((P_U32)(EMI_BASE+0x0090)) /* EMI Performance and Power Control Register */
+
+#define EMI_DLLV                 ((P_U32)(EMI_BASE+0x00A0))
+
+#define EMI_DFTC                 ((P_U32)(EMI_BASE+0x00F0))
+#define EMI_DFTD                 ((P_U32)(EMI_BASE+0x00F8))
+
+/* EMI bandwith filter and MPU control registers */
+#define EMI_ARBA                 ((P_U32)(EMI_BASE+0x0100))
+#define EMI_ARBB                 ((P_U32)(EMI_BASE+0x0108))
+#define EMI_ARBC                 ((P_U32)(EMI_BASE+0x0110))
+#define EMI_ARBD                 ((P_U32)(EMI_BASE+0x0118))
+#define EMI_ARBE                 ((P_U32)(EMI_BASE+0x0120))
+#define EMI_ARBF                 ((P_U32)(EMI_BASE+0x0128))
+#define EMI_ARBG                 ((P_U32)(EMI_BASE+0x0130))
+
+#define EMI_SLCT                 ((P_U32)(EMI_BASE+0x0150))
+#define EMI_ABCT	             ((P_U32)(EMI_BASE+0x0158))
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA                 ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB                 ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC                 ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD                 ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE                ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF	        ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG	        ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH	        ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI	        ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUI_2ND	    ((P_U32)(EMI_BASE+0x01A4))
+#define EMI_MPUJ            ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUJ_2ND	    ((P_U32)(EMI_BASE+0x01AC))
+#define EMI_MPUK            ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUK_2ND        ((P_U32)(EMI_BASE+0x01B4))
+#define EMI_MPUL            ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUL_2ND        ((P_U32)(EMI_BASE+0x01BC))
+#define EMI_MPUM            ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN            ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO            ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP            ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ            ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR            ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS            ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT            ((P_U32)(EMI_BASE+0x01F8))
+
+#define EMI_MPUA2		((P_U32)(EMI_BASE+0x0260))  
+#define EMI_MPUB2		((P_U32)(EMI_BASE+0x0268))  
+#define EMI_MPUC2		((P_U32)(EMI_BASE+0x0270))  
+#define EMI_MPUD2		((P_U32)(EMI_BASE+0x0278))
+#define EMI_MPUE2		((P_U32)(EMI_BASE+0x0280))  
+#define EMI_MPUF2		((P_U32)(EMI_BASE+0x0288))
+#define EMI_MPUG2		((P_U32)(EMI_BASE+0x0290)) 
+#define EMI_MPUH2		((P_U32)(EMI_BASE+0x0298))  
+#define EMI_MPUI2		((P_U32)(EMI_BASE+0x02A0))  
+#define EMI_MPUI2_2ND	((P_U32)(EMI_BASE+0x02A4))  
+#define EMI_MPUJ2		((P_U32)(EMI_BASE+0x02A8))  
+#define EMI_MPUJ2_2ND	((P_U32)(EMI_BASE+0x02AC))  
+#define EMI_MPUK2		((P_U32)(EMI_BASE+0x02B0)) 
+#define EMI_MPUK2_2ND	((P_U32)(EMI_BASE+0x02B4))  
+#define EMI_MPUL2		((P_U32)(EMI_BASE+0x02B8))  
+#define EMI_MPUL2_2ND	((P_U32)(EMI_BASE+0x02BC))  
+#define EMI_MPUM2		((P_U32)(EMI_BASE+0x02C0)) 
+#define EMI_MPUN2		((P_U32)(EMI_BASE+0x02C8)) 
+#define EMI_MPUO2		((P_U32)(EMI_BASE+0x02D0)) 
+#define EMI_MPUP2		((P_U32)(EMI_BASE+0x02D8)) 
+#define EMI_MPUQ2		((P_U32)(EMI_BASE+0x02E0)) 
+#define EMI_MPUR2		((P_U32)(EMI_BASE+0x02E8))  
+#define EMI_MPUU2		((P_U32)(EMI_BASE+0x0300))  
+#define EMI_MPUY2		((P_U32)(EMI_BASE+0x0320))
+
+/* EMI IO delay, driving and MISC control registers */
+#define EMI_IDLA            ((P_U32)(EMI_BASE+0x0200))
+#define EMI_IDLB            ((P_U32)(EMI_BASE+0x0208))
+#define EMI_IDLC            ((P_U32)(EMI_BASE+0x0210))
+#define EMI_IDLD            ((P_U32)(EMI_BASE+0x0218))
+#define EMI_IDLE            ((P_U32)(EMI_BASE+0x0220))
+#define EMI_IDLF            ((P_U32)(EMI_BASE+0x0228))
+#define EMI_IDLG            ((P_U32)(EMI_BASE+0x0230))
+#define EMI_IDLH            ((P_U32)(EMI_BASE+0x0238))
+#define EMI_IDLI            ((P_U32)(EMI_BASE+0x0240)) // IO input delay (DQS0 ~ DQS4)
+#define EMI_IDLJ            ((P_U32)(EMI_BASE+0x0248))
+#define EMI_IDLK            ((P_U32)(EMI_BASE+0x0250))
+
+#define EMI_ODLA           ((P_U32)(EMI_BASE+0x0258))
+#define EMI_ODLB           ((P_U32)(EMI_BASE+0x0260))
+#define EMI_ODLC           ((P_U32)(EMI_BASE+0x0268))
+#define EMI_ODLD           ((P_U32)(EMI_BASE+0x0270))
+#define EMI_ODLE           ((P_U32)(EMI_BASE+0x0278))
+#define EMI_ODLF           ((P_U32)(EMI_BASE+0x0280))
+#define EMI_ODLG           ((P_U32)(EMI_BASE+0x0288))
+
+#define EMI_DUTA           ((P_U32)(EMI_BASE+0x0290))
+#define EMI_DUTB           ((P_U32)(EMI_BASE+0x0298))
+#define EMI_DUTC           ((P_U32)(EMI_BASE+0x02A0))
+
+#define EMI_DRVA           ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_DRVB           ((P_U32)(EMI_BASE+0x02B0))
+
+#define EMI_IOCL           ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_IOCM           ((P_U32)(EMI_BASE+0x02C0)) //IvanTseng, for 4T mode
+#define EMI_IODC           ((P_U32)(EMI_BASE+0x02C8))
+
+#define EMI_ODTA           ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_ODTB           ((P_U32)(EMI_BASE+0x02D8))
+
+/* EMI auto-tracking control registers */
+#define EMI_DQSA           ((P_U32)(EMI_BASE+0x0300))
+#define EMI_DQSB           ((P_U32)(EMI_BASE+0x0308))
+#define EMI_DQSC           ((P_U32)(EMI_BASE+0x0310))
+#define EMI_DQSD           ((P_U32)(EMI_BASE+0x0318))
+
+
+#define EMI_DQSE           ((P_U32)(EMI_BASE+0x0320))
+#define EMI_DQSV           ((P_U32)(EMI_BASE+0x0328))
+
+#define EMI_CALA           ((P_U32)(EMI_BASE+0x0330))
+#define EMI_CALB           ((P_U32)(EMI_BASE+0x0338))
+#define EMI_CALC           ((P_U32)(EMI_BASE+0x0340))
+#define EMI_CALD           ((P_U32)(EMI_BASE+0x0348))
+
+
+#define EMI_CALE           ((P_U32)(EMI_BASE+0x0350)) //DDR data auto tracking control
+#define EMI_CALF           ((P_U32)(EMI_BASE+0x0358))
+#define EMI_CALG           ((P_U32)(EMI_BASE+0x0360)) //DDR data auto tracking control
+#define EMI_CALH           ((P_U32)(EMI_BASE+0x0368))
+
+#define EMI_CALI           ((P_U32)(EMI_BASE+0x0370))
+#define EMI_CALJ           ((P_U32)(EMI_BASE+0x0378))
+#define EMI_CALK           ((P_U32)(EMI_BASE+0x0380))
+#define EMI_CALL           ((P_U32)(EMI_BASE+0x0388))
+
+
+#define EMI_CALM           ((P_U32)(EMI_BASE+0x0390))
+#define EMI_CALN           ((P_U32)(EMI_BASE+0x0398))
+
+#define EMI_CALO           ((P_U32)(EMI_BASE+0x03A0))
+#define EMI_CALP           ((P_U32)(EMI_BASE+0x03A8))
+
+#define EMI_DUCA           ((P_U32)(EMI_BASE+0x03B0))
+#define EMI_DUCB           ((P_U32)(EMI_BASE+0x03B8))
+#define EMI_DUCC           ((P_U32)(EMI_BASE+0x03C0))
+#define EMI_DUCD           ((P_U32)(EMI_BASE+0x03C8))
+#define EMI_DUCE           ((P_U32)(EMI_BASE+0x03D0))
+
+/* EMI bus monitor control registers */
+#define EMI_BMEN           ((P_U32)(EMI_BASE+0x0400))
+#define EMI_BCNT           ((P_U32)(EMI_BASE+0x0408))
+#define EMI_TACT           ((P_U32)(EMI_BASE+0x0410))
+#define EMI_TSCT           ((P_U32)(EMI_BASE+0x0418))
+#define EMI_WACT           ((P_U32)(EMI_BASE+0x0420))
+#define EMI_WSCT           ((P_U32)(EMI_BASE+0x0428))
+#define EMI_BACT           ((P_U32)(EMI_BASE+0x0430))
+#define EMI_BSCT           ((P_U32)(EMI_BASE+0x0438))
+#define EMI_MSEL           ((P_U32)(EMI_BASE+0x0440))
+#define EMI_TSCT2           ((P_U32)(EMI_BASE+0x0448))
+#define EMI_TSCT3           ((P_U32)(EMI_BASE+0x0450))
+#define EMI_WSCT2           ((P_U32)(EMI_BASE+0x0458))
+#define EMI_WSCT3           ((P_U32)(EMI_BASE+0x0460))
+#define EMI_MSEL2           ((P_U32)(EMI_BASE+0x0468))
+#define EMI_MSEL3           ((P_U32)(EMI_BASE+0x0470))
+#define EMI_MSEL4           ((P_U32)(EMI_BASE+0x0478))
+#define EMI_MSEL5           ((P_U32)(EMI_BASE+0x0480))
+#define EMI_MSEL6           ((P_U32)(EMI_BASE+0x0488))
+#define EMI_MSEL7           ((P_U32)(EMI_BASE+0x0490))
+#define EMI_MSEL8           ((P_U32)(EMI_BASE+0x0498))
+#define EMI_MSEL9           ((P_U32)(EMI_BASE+0x04A0))
+#define EMI_MSEL10           ((P_U32)(EMI_BASE+0x04A8))
+#define EMI_BMID0            ((P_U32)(EMI_BASE+0x04B0))
+#define EMI_BMID1            ((P_U32)(EMI_BASE+0x04B8))
+#define EMI_BMID2            ((P_U32)(EMI_BASE+0x04C0))
+#define EMI_BMID3            ((P_U32)(EMI_BASE+0x04C8))
+#define EMI_BMID4            ((P_U32)(EMI_BASE+0x04D0))
+#define EMI_BMID5            ((P_U32)(EMI_BASE+0x04D8))
+
+#define EMI_TTYPE1            ((P_U32)(EMI_BASE+0x0500))
+#define EMI_TTYPE2            ((P_U32)(EMI_BASE+0x0508))
+#define EMI_TTYPE3            ((P_U32)(EMI_BASE+0x0510))
+#define EMI_TTYPE4            ((P_U32)(EMI_BASE+0x0518))
+#define EMI_TTYPE5            ((P_U32)(EMI_BASE+0x0520))
+#define EMI_TTYPE6            ((P_U32)(EMI_BASE+0x0528))
+#define EMI_TTYPE7            ((P_U32)(EMI_BASE+0x0530))
+#define EMI_TTYPE8            ((P_U32)(EMI_BASE+0x0538))
+#define EMI_TTYPE9            ((P_U32)(EMI_BASE+0x0540))
+#define EMI_TTYPE10            ((P_U32)(EMI_BASE+0x0548))
+#define EMI_TTYPE11            ((P_U32)(EMI_BASE+0x0550))
+#define EMI_TTYPE12            ((P_U32)(EMI_BASE+0x0558))
+#define EMI_TTYPE13            ((P_U32)(EMI_BASE+0x0560))
+#define EMI_TTYPE14            ((P_U32)(EMI_BASE+0x0568))
+#define EMI_TTYPE15            ((P_U32)(EMI_BASE+0x0570))
+#define EMI_TTYPE16            ((P_U32)(EMI_BASE+0x0578))
+#define EMI_TTYPE17            ((P_U32)(EMI_BASE+0x0580))
+#define EMI_TTYPE18            ((P_U32)(EMI_BASE+0x0588))
+#define EMI_TTYPE19            ((P_U32)(EMI_BASE+0x0590))
+#define EMI_TTYPE20            ((P_U32)(EMI_BASE+0x0598))
+#define EMI_TTYPE21            ((P_U32)(EMI_BASE+0x05A0))
+
+/* EMI MBIST control registers*/
+#define EMI_MBISTA            ((P_U32)(EMI_BASE+0x0600))
+#define EMI_MBISTB            ((P_U32)(EMI_BASE+0x0608))
+#define EMI_MBISTC            ((P_U32)(EMI_BASE+0x0610))
+#define EMI_MBISTD            ((P_U32)(EMI_BASE+0x0618))
+#define EMI_MBISTE            ((P_U32)(EMI_BASE+0x0620)) /* EMI MBIST status register */
+
+
+/* EMI Flow control register A */
+#define EMI_RFCA            ((P_U32)(EMI_BASE+0x0630))
+#define EMI_RFCB            ((P_U32)(EMI_BASE+0x0638))
+#define EMI_RFCC            ((P_U32)(EMI_BASE+0x0640))
+#define EMI_RFCD            ((P_U32)(EMI_BASE+0x0648))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8532/include/tz_init.h
new file mode 100644
index 0000000..23a5649
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/tz_init.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2011
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "typedefs.h"
+
+#define BL31        0x43001000UL
+#define BL33        0x43a00000UL
+#define BL31_BASE   0x43000000UL
+#define BL31_SIZE   0x00030000UL  /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+    u64 bootarg_loc;
+    u64 bootarg_size;
+    u64 bl33_start_addr;
+    u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+    u32 atf_magic;
+    u32 tee_support;
+    u32 tee_entry;
+    u32 tee_boot_arg_addr;
+    u32 hwuid[4];     // HW Unique id for t-base used
+    u32 atf_hrid_size;
+    u32 HRID[8];      // HW random id for t-base used
+    u32 atf_log_port;
+    u32 atf_log_baudrate;
+    u32 atf_log_buf_start;
+    u32 atf_log_buf_size;
+    u32 atf_irq_num;
+    u32 devinfo[DEVINFO_SIZE];
+    u32 atf_aee_debug_buf_start;
+    u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+    u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* TRUSTZONE_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt8532/include/uart.h b/src/bsp/trustzone/teeloader/mt8532/include/uart.h
new file mode 100644
index 0000000..94892bc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/include/uart.h
@@ -0,0 +1,62 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int    uint32_t;
+typedef unsigned long   uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart)    (uart)
+#define UART_LSR(uart)     (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE      (1 << 5)
+#define UART_THR(uart)     (UART_BASE(uart)+0x0)  /* Write only */
+
+#define IO_PHYS            0x10000000
+#define UART0_BASE         (IO_PHYS + 0x01002000)
+#define UART1_BASE         (IO_PHYS + 0x01002400)
+#define UART2_BASE         (IO_PHYS + 0x01002800)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8532/prebuilt/HwCryptoLib.a b/src/bsp/trustzone/teeloader/mt8532/prebuilt/HwCryptoLib.a
new file mode 100644
index 0000000..4d87bfc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/prebuilt/HwCryptoLib.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8532/prebuilt/libsec_img.a b/src/bsp/trustzone/teeloader/mt8532/prebuilt/libsec_img.a
new file mode 100644
index 0000000..0474c7e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/prebuilt/libsec_img.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt8532/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8532/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..1aec1d9
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,304 @@
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+    (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+    (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+#define print tl_printf
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+    int ret = 0;
+    unsigned int tmp, tmp2;
+    unsigned int ax_pm, ax_pm2;
+
+    if((end != 0) || (start !=0))
+    {
+        /*Address 64KB alignment*/
+        start -= EMI_PHY_OFFSET;
+        end -= EMI_PHY_OFFSET;
+        start = start >> 16;
+        end = end >> 16;
+
+        if (end <= start)
+        {
+            return -1;
+        }
+    }
+
+    ax_pm  = (access_permission << 16) >> 16;
+    ax_pm2 = (access_permission >> 16);
+
+    switch (region) {
+    case 0:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUA);
+        writel(tmp2 | ax_pm2, EMI_MPUI_2ND);
+        writel(tmp | ax_pm, EMI_MPUI);
+        break;
+
+    case 1:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI);
+        writel(0, EMI_MPUI_2ND);
+        writel((start << 16) | end, EMI_MPUB);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI);
+        break;
+
+    case 2:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUC);
+        writel(tmp2 | ax_pm2, EMI_MPUJ_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ);
+        break;
+
+    case 3:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ);
+        writel(0, EMI_MPUJ_2ND);
+        writel((start << 16) | end, EMI_MPUD);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ);
+        break;
+
+    case 4:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUE);
+        writel(tmp2 | ax_pm2, EMI_MPUK_2ND);
+        writel(tmp | ax_pm, EMI_MPUK);
+        break;
+
+    case 5:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK);
+        writel(0, EMI_MPUK_2ND);
+        writel((start << 16) | end, EMI_MPUF);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK);
+        break;
+
+    case 6:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUG);
+        writel(tmp2 | ax_pm2, EMI_MPUL_2ND);
+        writel(tmp | ax_pm, EMI_MPUL);
+        break;
+
+    case 7:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL);
+        writel(0, EMI_MPUL_2ND);
+        writel((start << 16) | end, EMI_MPUH);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL);
+        break;
+
+    case 8:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUA2);
+        writel(tmp2 | ax_pm2, EMI_MPUI2_2ND);
+        writel(tmp | ax_pm, EMI_MPUI2);
+        break;
+
+    case 9:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUI2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUI2);
+        writel(0, EMI_MPUI2_2ND);
+        writel((start << 16) | end, EMI_MPUB2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUI2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUI2);
+        break;
+
+    case 10:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUC2);
+        writel(tmp2 | ax_pm2, EMI_MPUJ2_2ND);
+        writel(tmp | ax_pm, EMI_MPUJ2);
+        break;
+
+    case 11:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUJ2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUJ2);
+        writel(0, EMI_MPUJ2_2ND);
+        writel((start << 16) | end, EMI_MPUD2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUJ2);
+        break;
+
+    case 12:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUE2);
+        writel(tmp2 | ax_pm2, EMI_MPUK2_2ND);
+        writel(tmp | ax_pm, EMI_MPUK2);
+        break;
+
+    case 13:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUK2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUK2);
+        writel(0, EMI_MPUK2_2ND);
+        writel((start << 16) | end, EMI_MPUF2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUK2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUK2);
+        break;
+
+    case 14:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0xFFFF0000;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0xFFFF0000;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUG2);
+        writel(tmp2 | ax_pm2, EMI_MPUL2_2ND);
+        writel(tmp | ax_pm, EMI_MPUL2);
+        break;
+
+    case 15:
+        //Marcos: Clear access right before setting MPU address (Mt6582 design)
+        tmp = readl(IOMEM(EMI_MPUL2)) & 0x0000FFFF;
+        tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0x0000FFFF;
+        writel(0, EMI_MPUL2);
+        writel(0, EMI_MPUL2_2ND);
+        writel((start << 16) | end, EMI_MPUH2);
+        writel(tmp2 | (ax_pm2 << 16), EMI_MPUL2_2ND);
+        writel(tmp | (ax_pm << 16), EMI_MPUL2);
+        break;
+
+    default:
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+    int ret = 0;
+    unsigned int sec_mem_mpu_attr;
+    unsigned int sec_mem_phy_start, sec_mem_phy_end;
+    unsigned int temp;
+
+    /* Caculate start/end address */
+    sec_mem_phy_start = start_add;
+    sec_mem_phy_end = end_addr;
+
+    // For MT6589
+    //==================================================================================================================
+    //            | Region |  D0(AP)  |  D1(MD0)  |  D2(Conn) |  D3(MD32) |  D4(MM)  |  D5(MD1)  |  D6(MFG)  |  D7(N/A)
+    //------------+---------------------------------------------------------------------------------------------------
+    // Secure OS  |    0   |RW(S)     |Forbidden  |Forbidden  |Forbidden  |RW(S)     |Forbidden  |Forbidden  |Forbidden
+    //------------+---------------------------------------------------------------------------------------------------
+    // MD0 ROM    |    1   |RO(S/NS)  |RO(S/NS)   |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 R/W+   |    2   |Forbidden |No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 ROM    |    3   |RO(S/NS)  |Forbidden  |RO(S/NS)   |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 R/W+   |    4   |Forbidden |Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // MD0 Share  |    5   |No protect|No protect |Forbidden  |Forbidden
+    //------------+------------------------------------------------------
+    // MD1 Share  |    6   |No protect|Forbidden  |No protect |Forbidden
+    //------------+------------------------------------------------------
+    // AP         |    7   |No protect|Forbidden  |Forbidden  |No protect
+    //===================================================================
+
+    switch (mpu_region) {
+    case SECURE_OS_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    case ATF_MPU_REGION_ID:
+    #ifdef DDR_RESERVE_MODE
+        print(" MPU [UNLOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #else
+        print(" MPU [LOCK\n");
+        sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+    #endif
+        break;
+    default:
+        print("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+        return;
+    }
+
+    print("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+    ret = emi_mpu_set_region_protection(sec_mem_phy_start,      /*START_ADDR*/
+                                        sec_mem_phy_end,      /*END_ADDR*/
+                                        mpu_region,       /*region*/
+                                        sec_mem_mpu_attr);
+
+
+    if(ret)
+    {
+        print("%s MPU error!!\n", MOD);
+    }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8532/src/main.c b/src/bsp/trustzone/teeloader/mt8532/src/main.c
new file mode 100644
index 0000000..a7abc3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/src/main.c
@@ -0,0 +1,121 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "uart.h"
+#include "print.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+extern void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region);
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+    return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+    return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+    atf_arg->bootarg_loc = 0;
+    atf_arg->bootarg_size = 0;
+    atf_arg->bl33_start_addr = BL33;
+    atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+    /* tee arguments */
+    tee_arg->atf_magic = 0x4D415446;
+    tee_arg->tee_support = 0x1;
+    tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+    tee_arg->tee_boot_arg_addr = 0x43000100;
+    tee_arg->hwuid[0] = 0x55C09893;
+    tee_arg->hwuid[1] = 0x2B404DDF;
+    tee_arg->hwuid[2] = 0x3ACE08B;
+    tee_arg->hwuid[3] = 0x1092600D;
+    tee_arg->HRID[0] = 0;
+    tee_arg->HRID[1] = 0;
+    tee_arg->atf_log_port = UART1_BASE;
+    tee_arg->atf_log_baudrate = 0xE1000;
+    tee_arg->atf_log_buf_start = 0x0;
+    tee_arg->atf_log_buf_size = 0x0;
+    tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+    tee_arg->devinfo[0] = 0;
+    tee_arg->devinfo[1] = 0;
+    tee_arg->devinfo[2] = 0xFFFFFFFF;
+    tee_arg->devinfo[3] = 0xFFFFFFFF;
+    tee_arg->atf_aee_debug_buf_start = 0x0;
+    tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+    u32 bl31_reserve = 0;
+    jump_atf atf_entry;
+
+    mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+    atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+#if 0 // for fpga bringup
+    tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+                    (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+                    ATF_MPU_REGION_ID);
+#endif
+
+    set_atf_parameters(atf_arg);
+    set_tee_parameters(tee_arg);
+
+    if(bl32_addr)
+        tee_arg->tee_entry = bl32_addr;
+
+    if(bl33_addr)
+        atf_arg->bl33_start_addr = bl33_addr;
+
+    atf_entry = (jump_atf)BL31;
+    /* jump to tz */
+
+    (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+    return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8532/src/print.c b/src/bsp/trustzone/teeloader/mt8532/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+	uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			outchar('\r');
+		outchar(*s++);
+	}
+}
+
+static void outdec(unsigned long n)
+{
+	if (n >= 10) {
+		outdec(n / 10);
+		n %= 10;
+	}
+	outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+	if (depth)
+		depth--;
+
+	if ((n & ~0xf) || depth) {
+		outhex(n >> 4, depth);
+		n &= 0xf;
+	}
+
+	if (n < 10) {
+		outchar((unsigned char)(n + '0'));
+	} else {
+		outchar((unsigned char)(n - 10 + 'A'));
+	}
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+	unsigned char c;
+	unsigned int reg = 1;	/* argument register number (32-bit) */
+
+	while (*fmt) {
+		c = *fmt++;
+		switch (c) {
+		case '%':
+			c = *fmt++;
+			switch (c) {
+			case 'x':
+				outhex(va_arg(vl, unsigned long), 0);
+				break;
+			case 'B':
+				outhex(va_arg(vl, unsigned long), 2);
+				break;
+			case 'H':
+				outhex(va_arg(vl, unsigned long), 4);
+				break;
+			case 'X':
+				outhex(va_arg(vl, unsigned long), 8);
+				break;
+			case 'l':
+				if (*fmt == 'l' && *(fmt + 1) == 'x') {
+					u32 ltmp;
+					u32 htmp;
+
+					ltmp = va_arg(vl, unsigned int);
+					htmp = va_arg(vl, unsigned int);
+
+					outhex(htmp, 8);
+					outhex(ltmp, 8);
+					fmt += 2;
+				}
+				break;
+			case 'd':
+				{
+					long l;
+
+					l = va_arg(vl, long);
+					if (l < 0) {
+						outchar('-');
+						l = -l;
+					}
+					outdec((unsigned long)l);
+				}
+				break;
+			case 'u':
+				outdec(va_arg(vl, unsigned long));
+				break;
+			case 's':
+				outstr((const unsigned char *)
+				       va_arg(vl, char *));
+				break;
+			case '%':
+				outchar('%');
+				break;
+			case 'c':
+				c = va_arg(vl, int);
+				outchar(c);
+				break;
+			default:
+				outchar(' ');
+				break;
+			}
+			reg++;	/* one argument uses 32-bit register */
+			break;
+		case '\r':
+			if (*fmt == '\n')
+				fmt++;
+			c = '\n';
+			// fall through
+		case '\n':
+			outchar('\r');
+			// fall through
+		default:
+			outchar(c);
+		}
+	}
+}
+
+void tl_printf(char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	tl_vprint(fmt, args);
+	va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8532/src/start.s b/src/bsp/trustzone/teeloader/mt8532/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+	b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8532/src/uart.c b/src/bsp/trustzone/teeloader/mt8532/src/uart.c
new file mode 100644
index 0000000..2126b16
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+	while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+	if (c == '\n')
+		writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+	writel((unsigned int)c, UART_THR(UART1_BASE));
+
+	return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8532/tllink.lds b/src/bsp/trustzone/teeloader/mt8532/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+	. = %BASE_ADDR%;
+	.start ALIGN(4) : {
+		*(.text.start)
+	}
+
+	. = . + 0x01FC;
+	.text ALIGN(4) : {
+		*(.text)
+		*(.text.*)
+	}
+	.rodata ALIGN(4) : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	.data ALIGN(4) : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = %BASE_ADDR%-0x100000 ;
+	.bss ALIGN(16) : {
+		_bss_start = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		/* make _bss_end as 4 bytes alignment */
+		. = ALIGN(4);
+		_bss_end = .;
+	}
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8532/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8532/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8532/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+	PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+	dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+	cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+	rm ${FILE_DIR}/padding.txt
+fi