[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/trustzone/teeloader/mt2712/Makefile b/src/bsp/trustzone/teeloader/mt2712/Makefile
new file mode 100644
index 0000000..d4e10e6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/Makefile
@@ -0,0 +1,76 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+ $(DIR_SRC)/drivers/device_apc.c \
+ $(DIR_SRC)/security/tz_init.c \
+ $(DIR_SRC)/security/tz_emi_mpu.c \
+ $(DIR_SRC)/security/tz_sec_cfg.c \
+ $(DIR_SRC)/security/seclib.c \
+ $(DIR_SRC)/drivers/tz_apc.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+ $(DIR_SRC)/security/tz_tbase.c
+endif
+ifeq ($(CFG_TRUSTKERNEL_TEE_SUPPORT),1)
+CSRCS += \
+ $(DIR_SRC)/security/tz_tkcore.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin -fno-stack-protector ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+ @if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+ mkdir -p `dirname $(BIN_TARGET).elf`; \
+ fi
+ sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+ $(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+ -echo "teeloader binary created"
+ $(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+ ./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+ -@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak
new file mode 100644
index 0000000..01ad308
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/auto2712p1v1-ivi_agl-vp1/cust_tee.mak
@@ -0,0 +1,12 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+# CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+# For Trustonic TEE default
+# CFG_TEE_SECMEM_SIZE = 0x3000000
+# For OPTEE default
+CFG_TEE_SECMEM_SIZE = 0x1000000
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak
new file mode 100644
index 0000000..e2b275d
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-optee/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x1000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak
new file mode 100644
index 0000000..30f2492
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tbase/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak
new file mode 100644
index 0000000..67a218f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/custom/mt2712-common-tkcore/cust_tee.mak
@@ -0,0 +1,9 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+#CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TRUSTKERNEL_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x1000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/default.mak b/src/bsp/trustzone/teeloader/mt2712/default.mak
new file mode 100644
index 0000000..6b85857
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/default.mak
@@ -0,0 +1,14 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT2712
+CFG_ATF_LOG_SUPPORT := 1
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+CFG_TZ_SRAMROM_SUPPORT := 1
+CFG_TZ_UART_APDMA_SUPPORT := 1
+CFG_TINYSYS_SCP_SUPPORT := 1
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x77e00000
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2712/feature.mak b/src/bsp/trustzone/teeloader/mt2712/feature.mak
new file mode 100644
index 0000000..e033ece
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/feature.mak
@@ -0,0 +1,68 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTKERNEL_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTKERNEL_TEE_SUPPORT=${CFG_TRUSTKERNEL_TEE_SUPPORT}
+export CFG_TRUSTKERNEL_TEE_SUPPORT
+endif
+
+ifdef CFG_OPTEE_TEE_SUPPORT
+C_OPTION += -DCFG_OPTEE_TEE_SUPPORT=${CFG_OPTEE_TEE_SUPPORT}
+export CFG_OPTEE_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
+
+ifdef CFG_TZ_SRAMROM_SUPPORT
+C_OPTION += -DCFG_TZ_SRAMROM_SUPPORT=${CFG_TZ_SRAMROM_SUPPORT}
+export CFG_TZ_SRAMROM_SUPPORT
+endif
+
+ifdef CFG_TZ_UART_APDMA_SUPPORT
+C_OPTION += -DCFG_TZ_UART_APDMA_SUPPORT=${CFG_TZ_UART_APDMA_SUPPORT}
+export CFG_TZ_UART_APDMA_SUPPORT
+endif
+
+ifdef CFG_TINYSYS_SCP_SUPPORT
+C_OPTION += -DCFG_TINYSYS_SCP_SUPPORT=${CFG_TINYSYS_SCP_SUPPORT}
+export CFG_TINYSYS_SCP_SUPPORT
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
new file mode 100644
index 0000000..7d5b170
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
@@ -0,0 +1,427 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+#define DEVAPC0_AO_BASE (0x1000E000U)
+#define DEVAPC0_PD_BASE (0x10207000U)
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define DEVAPC0_D0_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0000))
+#define DEVAPC0_D0_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0004))
+#define DEVAPC0_D0_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0008))
+#define DEVAPC0_D0_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x000C))
+#define DEVAPC0_D0_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0010))
+#define DEVAPC0_D0_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0014))
+#define DEVAPC0_D0_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0018))
+#define DEVAPC0_D0_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x001C))
+#define DEVAPC0_D0_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0024))
+#define DEVAPC0_D0_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0028))
+#define DEVAPC0_D0_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0030))
+#define DEVAPC0_D1_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0100))
+#define DEVAPC0_D1_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0104))
+#define DEVAPC0_D1_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0108))
+#define DEVAPC0_D1_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x010C))
+#define DEVAPC0_D1_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0110))
+#define DEVAPC0_D1_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0114))
+#define DEVAPC0_D1_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0118))
+#define DEVAPC0_D1_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x011C))
+#define DEVAPC0_D1_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0124))
+#define DEVAPC0_D1_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0128))
+#define DEVAPC0_D1_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0130))
+#define DEVAPC0_D2_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0200))
+#define DEVAPC0_D2_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0204))
+#define DEVAPC0_D2_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0208))
+#define DEVAPC0_D2_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x020C))
+#define DEVAPC0_D2_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0210))
+#define DEVAPC0_D2_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0214))
+#define DEVAPC0_D2_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0218))
+#define DEVAPC0_D2_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x021C))
+#define DEVAPC0_D2_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0224))
+#define DEVAPC0_D2_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0228))
+#define DEVAPC0_D2_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0230))
+#define DEVAPC0_D3_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0300))
+#define DEVAPC0_D3_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0304))
+#define DEVAPC0_D3_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0308))
+#define DEVAPC0_D3_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x030C))
+#define DEVAPC0_D3_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0310))
+#define DEVAPC0_D3_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0314))
+#define DEVAPC0_D3_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0318))
+#define DEVAPC0_D3_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x031C))
+#define DEVAPC0_D3_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0324))
+#define DEVAPC0_D3_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0328))
+#define DEVAPC0_D3_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0330))
+#define DEVAPC0_MAS_DOM_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0400))
+#define DEVAPC0_MAS_DOM_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0404))
+#define DEVAPC0_MAS_DOM_GROUP_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0408))
+#define DEVAPC0_MAS_SEC_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0500))
+#define DEVAPC0_MAS_SEC_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0504))
+#define DEVAPC0_APC_CON ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F00))
+#define DEVAPC0_PD_APC_CON ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F00))
+#define DEVAPC_APC_CON_CTRL (0x1U)
+#define DEVAPC_APC_CON_EN (0x1U)
+#define MASTER_MSDC0 4U
+
+typedef enum {
+ NON_SECURE_TRAN = 0,
+ SECURE_TRAN,
+} E_TRANSACTION;
+
+
+///* DOMAIN_SETUP */
+#define DOMAIN_0 0U
+#define DOMAIN_1 1U
+#define DOMAIN_2 2U
+#define DOMAIN_3 3U
+#define CONN2AP (0xf << 16)//index12 DEVAPC0_MAS_DOM_1
+#define GPU (0xf << 20)//index21 DEVAPC0_MAS_DOM_2
+
+static inline unsigned int uffs(unsigned int x)
+{
+ unsigned int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+#define reg_read16(reg) __raw_readw(reg)
+#define reg_read32(reg) __raw_readl(reg)
+#define reg_write16(reg,val) __raw_writew(val,reg)
+#define reg_write32(reg,val) __raw_writel(val,reg)
+
+#define reg_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ tv &= ~(field); \
+ tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+ reg_write32(reg,tv); \
+ } while(0)
+
+#define reg_get_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+ } while(0)
+
+#define DAPC_SEC_RW_NSEC_RW 0U /* read and write for both secure and non-secure access */
+#define DAPC_SEC_RW 1U /* read and write for secure access */
+#define DAPC_NSEC_RW 2U /* read and write for non-secure access */
+#define DAPC_SEC_DENY_NSEC_DENY 3U /* Any access is prohibited */
+
+#define DAPC_NS_TRANSACTION 0U /* Emit non-secure signal sideband */
+#define DAPC_S_TRANSACTION 1U /* Emit secure signal sideband */
+
+#define MASTER_NFI 0U
+#define MASTER_PWM 2U
+#define MASTER_THERMAL_CTRL 3U
+#define MASTER_MSDC0 4U
+#define MASTER_MSDC1 5U
+#define MASTER_MSDC2 6U
+#define MASTER_MSDC3 7U
+#define MASTER_SPI0 8U
+#define MASTER_SPM 9U
+#define MASTER_DEBUG_SYSTEM 11U
+#define MASTER_AUDIO_AFE 12U
+#define MASTER_APMCU 13U
+#define MASTER_MFG_M0 19U
+#define MASTER_USB30 20U
+#define MASTER_SPI1 22U
+#define MASTER_SPI2 23U
+#define MASTER_SPI3 24U
+#define MASTER_SPI4 25U
+#define MASTER_SPI5 26U
+#define MASTER_SCP 27U
+#define MASTER_USB30_2 28U
+#define MASTER_SFLASH 29U
+#define MASTER_GMAC 30U
+#define MASTER_PCIE0 31U
+#define MASTER_PCIE1 32U
+
+#define MODULE_TRANSACTION(index, is_secure) (is_secure << (index % 32))
+#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)
+
+#define MODULE_DOMAIN(index, domain) (domain << (2 * (index % 16)))
+#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)
+
+#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(devapc_register, permission) reg_write32(devapc_register, permission)
+
+#define INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR 0U
+#define INFRA_AO_INFRASYS_CONFIG_REGS 1U
+/* #define Reserved 2U */
+#define INFRA_AO_PERISYS_CONFIG_REGS 3U
+/* #define Reserved 4U */
+#define INFRA_AO_GPIO_CONTROLLER 5U
+#define INFRA_AO_TOP_LEVEL_SLP_MANAGER 6U
+#define INFRA_AO_TOP_LEVEL_RESET_GENERATOR 7U
+#define INFRA_AO_GPT 8U
+/* #define Reserved 9U */
+#define INFRA_AO_SEJ 10U
+#define INFRA_AO_APMCU_EINT_CONTROLLER 11U
+#define SYS_TIMER_CONTROL_REG 12U
+#define IRRX_CONTROL_REG 13U
+#define INFRA_AO_DEVICE_APC_AO 14U
+#define UART5_REG 15U
+#define INFRA_AO_KPAD_CONTROL_REG 16U
+#define TOP_RTC_REG 17U
+#define SPI4_REG 18U
+#define SPI1_REG 19U
+#define INFRA_AO_GPT2 20U
+#define DRAMC_CH0_REG 21U
+#define DRAMC_CH1_REG 22U
+#define DRAMC_CH2_REG 23U
+#define DRAMC_CH3_REG 24U
+#define INFRASYS_MCUSYS_CONFIG_REG 25U
+#define INFRASYS_CONTROL_REG 26U
+#define INFRASYS_BOOTROM_SRAM 27U
+#define INFRASYS_EMI_BUS_INTERFACE 28U
+#define INFRASYS_SYSTEM_CIRQ 29U
+#define INFRASYS_M4U_CONFIGURATION 30U
+#define INFRASYS_EFUSEC 31U
+#define INFRASYS_DEVICE_APC_MONITOR 32U
+#define BUS_DEBUG_TRAKER 33U
+#define INFRASYS_AP_MIXED_CONTROL_REG 34U
+#define INFRASYS_M4U_2_CONFIGURATION 35U
+#define ANA_MIPI_DSI3 36U
+/* #define Reserved 37U */
+#define INFRASYS_MBIST_CONTROL_REG 38U
+#define INFRASYS_EMI_MPU_CONTROL_REG 39U
+#define INFRASYS_TRNG 40U
+#define INFRASYS_GCPU 41U
+#define INFRASYS_GCPU_NS 42U
+#define INFRASYS_CQ_DMA 43U
+#define INFRASYS_GCPU_M4U 44U
+#define ANA_MIPI_DSI2 45U
+#define ANA_MIPI_DSI0 46U
+#define ANA_MIPI_DSI1 47U
+#define ANA_MIPI_CSI0 48U
+#define ANA_MIPI_CSI1 49U
+/* #define Reserved 50U */
+#define DEGBUG_CORESIGHT 51U
+#define DMA 52U
+#define AUXADC 53U
+#define UART0 54U
+#define UART1 55U
+#define UART2 56U
+#define UART3 57U
+#define PWM 58U
+#define I2C0 59U
+#define I2C1 60U
+#define I2C2 61U
+#define SPI0 62U
+#define THERM_CTRL 63U
+/* #define Reserved 64U */
+#define SPI_NOR 65U
+#define NFI 66U
+#define NFI_ECC 67U
+#define I2C3 68U
+#define I2C4 69U
+/* #define Reserved 70U */
+#define I2C5 71U
+/* #define Reserved 72U */
+#define SPI2 73U
+#define SPI3 74U
+/* #define Reserved 75U */
+/* #define Reserved 76U */
+#define UART4 77U
+/* #define Reserved 78U */
+#define GMAC 79U
+/* #define Reserved 80U */
+/* #define Reserved 81U */
+#define AUDIO 82U
+#define MSDC0 83U
+#define MSDC1 84U
+#define MSDC2 85U
+#define MSDC3 86U
+#define USB3_0 87U
+#define USB3_0SIF 88U
+#define USB3_0SIF2 89U
+#define USB3_0_2 90U
+#define USB3_0SIF_2 91U
+#define USB3_0SIF2_2 92U
+#define SCPSYS_SRAM 93U
+#define PCIe0 94U
+#define PCIe1 95U
+#define G3D_CONFIG 96U
+#define MMSYS_CONFIG 97U
+#define MDP_RDMA0 98U
+#define MDP_RDMA1 99U
+#define MDP_RSZ0 100U
+#define MDP_RSZ1 101U
+#define MDP_RSZ2 102U
+#define MDP_WDMA 103U
+#define MDP_WROT0 104U
+#define MDP_WROT1 105U
+#define MDP_TDSHP0 106U
+#define MDP_TDSHP1 107U
+/* #define Reserved 108U */
+#define DISP_OVL0 109U
+#define DISP_OVL1 110U
+#define DISP_RDMA0 111U
+#define DISP_RDMA1 112U
+#define DISP_RDMA2 113U
+#define DISP_WDMA0 114U
+#define DISP_WDMA1 115U
+#define DISP_COLOR0 116U
+#define DISP_COLOR1 117U
+#define DISP_AAL 118U
+#define DISP_GAMMA 119U
+/* #define Reserved 120U */
+#define DISP_SPLIT0 121U
+/* #define Reserved 122U */
+#define DISP_UFOE 123U
+#define DSI0 124U
+#define DSI1 125U
+#define DPI 126U
+#define DISP_PWM0 127U
+#define DISP_PWM1 128U
+#define MM_MUTEX 129U
+#define SMI_LARB0 130U
+#define SMI_COMMON 131U
+#define DISP_OD 132U
+#define DPI1 133U
+/* #define Reserved 134U */
+#define LVDS 135U
+#define SMI_LARB4 136U
+#define MDP_RDMA2 137U
+#define DISP_COLOR2 138U
+#define DISP_AAL1 139U
+#define DISP_OD1 140U
+#define DISP_OVL2 141U
+#define DISP_WDMA2 142U
+#define LVDS1 143U
+#define MDP_TDSHP2 144U
+#define SMI_LARB5 145U
+#define SMI_COMMON1 146U
+#define SMI_LARB7 147U
+#define MDP_RDMA3 148U
+#define MDP_WROT2 149U
+#define DSI2 150U
+#define DSI3 151U
+/* #define Reserved 152U */
+#define DISP_MONITOR0 153U
+#define DISP_MONITOR1 154U
+#define DISP_MONITOR2 155U
+#define DISP_MONITOR3 156U
+#define DISP_PWM2 157U
+#define IMGSYS_CONFIG 158U
+#define SMI_LARB2 159U
+#define SENINF_TOP0 160U
+#define SENINF_TOP1 161U
+#define CAMSV_TOP0 162U
+#define CAMSV_TOP1 163U
+#define CAMSV_TOP2 164U
+#define CAMSV_TOP3 165U
+#define CAMSV_TOP4 166U
+#define CAMSV_TOP5 167U
+/* #define Reserved 168U */
+/* #define Reserved 169U */
+/* #define Reserved 170U */
+/* #define Reserved 171U */
+/* #define Reserved 172U */
+/* #define Reserved 173U */
+#define BDP_DISPSYS_CONFIG 174U
+#define BDP_DISPFMT 175U
+#define BDP_VDO 176U
+#define BDP_NR 177U
+#define BDP_NR2 178U
+#define BDP_TVD 179U
+#define BDP_WR_CHANNEL_DI 180U
+#define BDP_WR_CHANNEL_VDI 181U
+#define BDP_LARB 182U
+#define BDP_LARB_RT 183U
+#define BDP_DRAM2AXI_BRIDGE 184U
+#define VDECSYS_CONFIGURATION 185U
+#define VDECSYS_SMI_LARB1 186U
+#define VDEC_FULL_TOP 187U
+#define IMGRZ 188U
+#define VDEC_MBIST 189U
+#define JPGDEC_CONFIGURATION 190U
+#define JPDEC 191U
+#define JPDGDEC1 192U
+/* #define Reserved 193U */
+#define VENC_CONFIGURATION 194U
+#define VENC_SMI_LARB3 195U
+#define VENC_SMI_LARB6 196U
+#define SMI_COMMON_2 197U
+#define VENC 198U
+/* #define Reserved 199U */
+#define SFLASH 200U
+
+extern void device_APC_dom_setup(void);
+extern void tz_dapc_sec_setting(void);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
new file mode 100644
index 0000000..926bc1f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
@@ -0,0 +1,53 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+ unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/platform.h b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
new file mode 100644
index 0000000..51dca91
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR (0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE (0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE (0x800000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE (0x800000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0xA000000UL) /* TEE max DRAM size is 160MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/print.h b/src/bsp/trustzone/teeloader/mt2712/include/print.h
new file mode 100644
index 0000000..732dc0e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/print.h
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define REL_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/seclib.h b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
new file mode 100644
index 0000000..abb4c8e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX (0xFFFFFFFFUL) /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/string.h b/src/bsp/trustzone/teeloader/mt2712/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
new file mode 100644
index 0000000..e49da76
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
@@ -0,0 +1,178 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE (0U)
+#endif
+#ifndef TRUE
+#define TRUE (1U)
+#endif
+
+#ifndef NULL
+#define NULL (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+ (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+ (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+ (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+ (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+ (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+ (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x) READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y) WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x) READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y) WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x) READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y) WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr) INREG8(addr)
+#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data) SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
+
+#define DRV_Reg16(addr) INREG16(addr)
+#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data) SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
+
+#define DRV_Reg32(addr) INREG32(addr)
+#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data) SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
+
+#define __raw_readb(REG) DRV_Reg8(REG)
+#define __raw_readw(REG) DRV_Reg16(REG)
+#define __raw_readl(REG) DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG) DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG) DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG) DRV_WriteReg32(REG,VAL)
+
+#define printf print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
new file mode 100644
index 0000000..c593c94
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
@@ -0,0 +1,155 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2018 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_APC_H
+#define TZ_APC_H
+
+#include "typedefs.h"
+
+/*****************************************************************************
+ * Register base address definition
+ *****************************************************************************/
+
+#define SRAMROM_SEC_CTRL ((volatile unsigned int*)(0x10001804U))
+#define SRAMROM_SEC_ADDR ((volatile unsigned int*)(0x10001808U))
+
+/* APDMA */
+#define APDMA_GLOBAL_GSEC_CTRL ((volatile unsigned int*)(0x11000014U))
+#define APDMA_UART_TX0_SEC_CTRL ((volatile unsigned int*)(0x11000038U))
+#define APDMA_UART_RX0_SEC_CTRL ((volatile unsigned int*)(0x1100003CU))
+#define APDMA_UART_TX1_SEC_CTRL ((volatile unsigned int*)(0x11000040U))
+#define APDMA_UART_RX1_SEC_CTRL ((volatile unsigned int*)(0x11000044U))
+#define APDMA_UART_TX2_SEC_CTRL ((volatile unsigned int*)(0x11000048U))
+#define APDMA_UART_RX2_SEC_CTRL ((volatile unsigned int*)(0x1100004CU))
+#define APDMA_UART_TX3_SEC_CTRL ((volatile unsigned int*)(0x11000050U))
+#define APDMA_UART_RX3_SEC_CTRL ((volatile unsigned int*)(0x11000054U))
+#define APDMA_UART_TX4_SEC_CTRL ((volatile unsigned int*)(0x11000058U))
+#define APDMA_UART_RX4_SEC_CTRL ((volatile unsigned int*)(0x1100005CU))
+#define APDMA_UART_TX5_SEC_CTRL ((volatile unsigned int*)(0x11000060U))
+#define APDMA_UART_RX5_SEC_CTRL ((volatile unsigned int*)(0x11000064U))
+#define APDMA_GLOBAL_GSEC_EN 0x1
+
+/* CQDMA */
+#define CQDMA_SEC_CTRL ((volatile unsigned int*)(0x10212C58U))
+
+/* SMI BDPSYS (larb8 and larb9) */
+#define SMI_BDPSYS_LARB8_BASE ((volatile unsigned int*)(0x1501a000U))
+#define SMI_BDPSYS_LARB9_BASE ((volatile unsigned int*)(0x1501a008U))
+#define SMI_BDPSYS_DOMAIN_MASK (0xf0000)
+#define SMI_BDPSYS_AR_DOMAIN(dom) (((dom) & 0x3) << 16)
+#define SMI_BDPSYS_AW_DOMAIN(dom) (((dom) & 0x3) << 18)
+
+/*****************************************************************************
+ * Enum
+ *****************************************************************************/
+typedef enum
+{
+ TZ_APC_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_APC_SEC_RW_NSEC_DENY, /* read and write for secure access */
+ TZ_APC_SEC_DENY_NSEC_RW, /* read and write for non-secure access */
+ TZ_APC_SEC_DENY_NSEC_DENY /* Any access is prohibited */
+} tz_apc_permission;
+
+typedef enum
+{
+ TZ_APC_DOMAIN_IVI = 0, /* The domain is for in-vehicle infotainment system (normally Linux OS). */
+ TZ_APC_DOMAIN_CLUSTER = 1, /* The domain is for cluster system. */
+ TZ_APC_DOMAIN_DSP = 2, /* The domain is for Audio DSP system. */
+ TZ_APC_DOMAIN_MCU = 3, /* AP MCU will access the bus throgh the domain ID. The MCU used by any of the sub-system,
+ including IVI, cluster, and DSP will access the bus with this domain.
+ This domain can access almost all the slave devices in secure and non-secure mode and
+ hence we must apply the MMU and MPU to protect the device access and memory access in
+ the system. */
+} tz_apc_domain_partition;
+
+typedef enum
+{
+ TZ_SRAMROM_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_DENY = 1, /* read and write for secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_RO = 2, /* read and write for secure access and read only for non-secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_WO = 3, /* read and write for secure access and write only for non-secure access */
+ TZ_SRAMROM_SEC_RO_NSEC_RO = 4, /* read only for both secure access and non-secure access */
+ TZ_SRAMROM_SEC_DENY_NSEC_DENY = 7 /* Any access is prohibited */
+} tz_sramrom_permission;
+
+typedef enum
+{
+ TZ_UART_APDMA_NSEC = 0, /* Read and write with non-secure sideband AXI signal. */
+ TZ_UART_APDMA_SEC = 1, /* Read and write with secure sideband AXI signal. */
+} tz_uart_apdma_permission;
+
+typedef enum
+{
+ TZ_CQDMA_NSEC = 0, /* Read and write with non-secure sideband AXI signal. */
+ TZ_CQDMA_SEC = 1, /* Read and write with secure sideband AXI signal. */
+} tz_cpdma_permission;
+
+typedef enum
+{
+ TZ_SRAMROM_REGION_0 = 0, /* Region 0 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+ TZ_SRAMROM_REGION_1 = 1 /* Region 1 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+} tz_sramrom_region;
+
+/*****************************************************************************
+ * Functions
+ *****************************************************************************/
+
+#define reg_read16(reg) __raw_readw(reg)
+#define reg_read32(reg) __raw_readl(reg)
+#define reg_write16(reg,val) __raw_writew(val,reg)
+#define reg_write32(reg,val) __raw_writel(val,reg)
+
+static inline u32 tz_sramrom_set_bitwise_domain_permision(tz_sramrom_region region,
+ tz_apc_domain_partition domain, tz_sramrom_permission permission)
+{
+ return (permission & 0x7) << ((domain * 3) + (region == TZ_SRAMROM_REGION_1 ? 16: 0));
+}
+
+/* Enabling this bit to protect all multimedia secure related registers, including SMI,
+ accessing in non-secure world. */
+#define TZ_SRAMROM_ENABLE_MULTIMEDIA_SECURE_ACCESS (u32)(0x1 << 30)
+
+/* Enabling this bit to protect sramrom region 1 by region 1's security setting */
+#define TZ_SRAMROM_ENABLE_REGION_1_PROTECTION (u32)(0x1 << 28)
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0). */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size) (reg_write32(SRAMROM_SEC_ADDR, ((size & 0xff) << 10)))
+
+extern void tz_apc_common_init();
+extern void tz_apc_common_postinit();
+
+#endif /* TZ_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET (0x40000000UL)
+#define EMI_MPU_ALIGNMENT (0x10000UL)
+#define PERIAXI_BUS_CTL3 (0x10003208UL)
+#define PERISYS_4G_SUPPORT (0x1 << 11)
+
+
+typedef enum
+{
+ TZ_MPU_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_MPU_SEC_RW_NSEC_DENY = 1, /* read and write for secure access */
+ TZ_MPU_SEC_RW_NSEC_RO = 2, /* read and write for secure access and read only for non-secure access */
+ TZ_MPU_SEC_RW_NSEC_WO = 3, /* read and write for secure access and write only for non-secure access */
+ TZ_MPU_SEC_RO_NSEC_RO = 4, /* read only for both secure access and non-secure access */
+ TZ_MPU_SEC_DENY_NSEC_DENY = 5, /* Any access is prohibited */
+ TZ_MPU_SEC_RO_NSEC_RW = 6 /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID (0)
+#define ATF_MPU_REGION_ID (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE (0x1020E000U)
+
+#define EMI_MPU_SA0 ((P_U32)(EMI_MPU_BASE+0x100)) /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1 ((P_U32)(EMI_MPU_BASE+0x104)) /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2 ((P_U32)(EMI_MPU_BASE+0x108)) /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3 ((P_U32)(EMI_MPU_BASE+0x10C)) /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4 ((P_U32)(EMI_MPU_BASE+0x110)) /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5 ((P_U32)(EMI_MPU_BASE+0x114)) /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6 ((P_U32)(EMI_MPU_BASE+0x118)) /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7 ((P_U32)(EMI_MPU_BASE+0x11C)) /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0 ((P_U32)(EMI_MPU_BASE+0x200)) /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1 ((P_U32)(EMI_MPU_BASE+0x204)) /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2 ((P_U32)(EMI_MPU_BASE+0x208)) /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3 ((P_U32)(EMI_MPU_BASE+0x20C)) /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4 ((P_U32)(EMI_MPU_BASE+0x210)) /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5 ((P_U32)(EMI_MPU_BASE+0x214)) /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6 ((P_U32)(EMI_MPU_BASE+0x218)) /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7 ((P_U32)(EMI_MPU_BASE+0x21C)) /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0 ((P_U32)(EMI_MPU_BASE+0x300)) /* EMI MPU APC 0 */
+#define EMI_MPU_APC1 ((P_U32)(EMI_MPU_BASE+0x304)) /* EMI MPU APC 1 */
+#define EMI_MPU_APC2 ((P_U32)(EMI_MPU_BASE+0x308)) /* EMI MPU APC 2 */
+#define EMI_MPU_APC3 ((P_U32)(EMI_MPU_BASE+0x30C)) /* EMI MPU APC 3 */
+#define EMI_MPU_APC4 ((P_U32)(EMI_MPU_BASE+0x310)) /* EMI MPU APC 4 */
+#define EMI_MPU_APC5 ((P_U32)(EMI_MPU_BASE+0x314)) /* EMI MPU APC 5 */
+#define EMI_MPU_APC6 ((P_U32)(EMI_MPU_BASE+0x318)) /* EMI MPU APC 6 */
+#define EMI_MPU_APC7 ((P_U32)(EMI_MPU_BASE+0x31C)) /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0 ((P_U32)(EMI_MPU_BASE+0x900)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1 ((P_U32)(EMI_MPU_BASE+0x904)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2 ((P_U32)(EMI_MPU_BASE+0x908)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3 ((P_U32)(EMI_MPU_BASE+0x90C)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4 ((P_U32)(EMI_MPU_BASE+0x910)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5 ((P_U32)(EMI_MPU_BASE+0x914)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6 ((P_U32)(EMI_MPU_BASE+0x918)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7 ((P_U32)(EMI_MPU_BASE+0x91C)) /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
new file mode 100644
index 0000000..6778589
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+
+#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+
+/* bootarg for ATF */
+typedef struct {
+ u64 bootarg_loc;
+ u64 bootarg_size;
+ u64 bl33_start_addr;
+ u64 tee_info_addr;
+ u64 boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+ unsigned int atf_magic;
+ unsigned int tee_support;
+ unsigned int tee_boot_arg_addr;
+ unsigned int tee_entry;
+ unsigned int hwuid[4]; // HW Unique id for t-base used
+ unsigned int HRID[2]; // HW random id for t-base used
+ unsigned int atf_log_port;
+ unsigned int atf_log_baudrate;
+ unsigned int atf_log_buf_start;
+ unsigned int atf_log_buf_size;
+ unsigned int atf_aee_debug_buf_start;
+ unsigned int atf_aee_debug_buf_size;
+ unsigned int devinfo[DEVINFO_SIZE];
+ unsigned int atf_irq_num;
+ unsigned int msg_auth_key[8]; /* size of message auth key is 256 bits */
+#if CFG_TEE_SUPPORT
+ unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
new file mode 100644
index 0000000..c330423
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
@@ -0,0 +1,102 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS (0x00100000UL)
+#define SRAM_START_ADDR (0x00102140UL)
+#define VECTOR_START (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+ short next, previous;
+} tz_memory_t;
+
+#define FREE ((short)(0x0001U))
+#define IS_FREE(x) ((x)->next & FREE)
+#define CLEAR_FREE(x) ((x)->next &= ~FREE)
+#define SET_FREE(x) ((x)->next |= FREE)
+#define FROM_ADDR(x) ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x) ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE (0x200000UL) //2MB by default
+
+#define BL31 (0x44e01000UL)
+#define BL31_SIZE (0x40000UL) //change to 256KB (192KB by default)
+#define BL33 (0x73500000UL)
+
+#define ATF_BOOT_ARG_ADDR (0x40000000UL)
+#define ATF_INIT_ARG_ADDR (0x40000100UL)
+#define TEE_BOOT_ARG_ADDR (0x44e00100UL)
+
+#define TEE_PARAMETER_BASE (TEE_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+ unsigned int magic; // Magic number
+ unsigned int version; // version
+ unsigned int svp_mem_start; // MM sec mem pool start addr.
+ unsigned int svp_mem_end; // MM sec mem pool end addr.
+ unsigned int tplay_table_start; // tplay handle-to-physical table start
+ unsigned int tplay_table_size; // tplay handle-to-physical table size
+ unsigned int tplay_mem_start; // tplay physcial memory start address for crypto operation
+ unsigned int tplay_mem_size; // tplay phsycial memory size for crypto operation
+ unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+ unsigned int rpmb_size; /* size of rpmb partition */
+ unsigned int msg_auth_key[8]; /* size of message auth key is 32bytes(256 bits) */
+ unsigned int emmc_rel_wr_sec_c; // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+ u32 magic; // magic value from information
+ u32 length; // size of struct in bytes.
+ u64 version; // Version of structure
+ u64 dRamBase; // NonSecure DRAM start address
+ u64 dRamSize; // NonSecure DRAM size
+ u64 secDRamBase; // Secure DRAM start address
+ u64 secDRamSize; // Secure DRAM size
+ u64 secIRamBase; // Secure IRAM base
+ u64 secIRamSize; // Secure IRam size
+ u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+ u32 RFU1;
+ u32 MSMPteCount; // Number of MMU entries for MSM
+ u64 MSMBase; // MMU entries for MSM
+ u64 gic_distributor_base;
+ u64 gic_cpuinterface_base;
+ u32 gic_version;
+ u32 RFU2;
+ u64 flags;
+ u32 total_number_spi;
+ u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
new file mode 100644
index 0000000..57efd71
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
@@ -0,0 +1,80 @@
+#ifndef TZ_TKCORE_H
+#define TZ_TKCORE_H
+
+#include "typedefs.h"
+
+#define TKCORE_BOOTCFG_MAGIC (0x54534958)
+
+#define TEE_ARGUMENT_VERSION_LEGACY (0x00010000U)
+#define TEE_ARGUMENT_VERSION_V1_0 (0x00010001U)
+#define TEE_ARGUMENT_VERSION_V1_1 (0x00010002U)
+#define TEE_ARGUMENT_VERSION_V1_2 (0x00010003U)
+
+#define TEE_ARGUMENT_VERSION TEE_ARGUMENT_VERSION_V1_2
+
+#define TKCORE_SHM_SIZE_LIMIT (0x400000U)
+
+#define RPMB_KEY_SIZE 32
+
+#define SDRPMB_FAILURE_MAGIC (0xCDCDCDCDU)
+/* effective data size */
+#define SDRPMB_DATA_SIZE (1U << 20)
+/* size of two write protected regions */
+#define SDRPMB_REGION_SIZE (16U << 20)
+/* granu of sdrpmb region */
+#define SDRPMB_REGION_ALIGNMENT (8U << 20)
+
+typedef struct {
+ u32 magic; // magic value from information
+ u32 length; // size of struct in bytes.
+ u64 version; // Version of structure
+ u64 dRamBase; // NonSecure DRAM start address
+ u64 dRamSize; // NonSecure DRAM size
+ u64 secDRamBase; // Secure DRAM start address
+ u64 secDRamSize; // Secure DRAM size
+ u64 secIRamBase; // Secure IRAM base
+ u64 secIRamSize; // Secure IRam size
+ u64 gic_distributor_base;
+ u64 gic_cpuinterface_base;
+ u32 gic_version;
+ u32 uart_base;
+ u32 total_number_spi;
+ u32 ssiq_number;
+ u64 flags;
+ u8 rpmb_key[RPMB_KEY_SIZE];
+
+ /* for TEE_ARGUMENT_VERSION_1 */
+ u8 rpmb_key_programmed;
+
+ /* for TEE_ARGUMENT_VERSION_2 (mt6580 specific) */
+ u32 nw_bootargs;
+ u32 nw_bootargs_size;
+
+ /* for TEE_ARGUMENT_VERSION_3 */
+ u32 sdrpmb_partaddr;
+ u32 sdrpmb_partsize;
+ u32 sdrpmb_starting_sector;
+ u32 sdrpmb_nr_sectors;
+
+ u8 resv[7];
+} __attribute__((packed)) tee_arg_t, *tee_arg_t_ptr;
+
+void tkcore_boot_param_prepare(u64 param_addr, u64 tee_entry,
+ u64 sec_dram_size, u64 dram_base, u64 dram_size, u32 uart_base);
+
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+void tkcore_boot_param_prepare_sdrpmb_region(part_t *part);
+
+void tkcore_boot_param_prepare_sdrpmb_data(mblock_info_t *mblock, blkdev_t *bootdev);
+
+void tkcore_boot_sdrpmb_init_finish(u32 param_addr);
+#endif
+
+void tkcore_boot_param_prepare_rpmbkey(u32 param_addr);
+
+void tkcore_boot_param_prepare_nwbootargs(u32 param_addr,
+ u32 addr, u32 size);
+
+void tkcore_dump_param(u32 param_addr);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/uart.h b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
new file mode 100644
index 0000000..9db4093
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+typedef unsigned int uint32_t;
+typedef unsigned long uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart) (uart)
+#define UART_LSR(uart) (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE (1U << 5U)
+#define UART_THR(uart) (UART_BASE(uart) + 0x0U) /* Write only */
+
+#define IO_PHYS (0x10000000UL)
+#define UART1_BASE (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a b/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a
new file mode 100644
index 0000000..8504221
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/prebuilt/libsec.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c
new file mode 100644
index 0000000..bee32c4
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/drivers/device_apc.c
@@ -0,0 +1,1199 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES */
+/*=======================================================================*/
+#include "device_apc.h"
+#include "print.h"
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE (0x00000000U) /* No event */
+#define DBG_EVT_ERR (0x00000001U) /* ERR related event */
+#define DBG_EVT_DOM (0x00000002U) /* DOM related event */
+
+#define DBG_EVT_ALL (0xffffffffU)
+
+#define DBG_EVT_MASK (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+ do { \
+ if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+ print(fmt, ##args); \
+ } \
+ } while(0)
+
+#define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{} while(0)
+#define MSG_FUNC_ENTRY(f) do{} while(0)
+#endif
+
+void tz_dapc_set_master_transaction(unsigned int master_index , E_TRANSACTION permisssion_control)
+{
+ reg_set_field(DEVAPC0_MAS_SEC_GROUP_0 , (0x1 << master_index), permisssion_control);
+}
+
+void tz_dapc_sec_init(void)
+{
+ /* lock dapc to security access only */
+ reg_write32(DEVAPC0_APC_CON, 0x1);
+
+ /* tz_dapc_set_master_transaction(MASTER_MSDC0 , SECURE_TRAN); */
+}
+
+void tz_dapc_sec_postinit(void)
+{
+ /* tz_dapc_set_master_transaction(MASTER_MSDC0 , NON_SECURE_TRAN); */
+}
+
+void device_APC_dom_setup(void)
+{
+ MSG(DOM, "\nDevice APC domain init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_0));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_1));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_2));
+#endif
+ /*Set masters to DOMAINX here if needed*/
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Device APC domain after setup:\n");
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_0));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_1));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_GROUP_2));
+#endif
+}
+
+void tz_dapc_sec_setting(void)
+{
+ /* Set domain of masters */
+ DAPC_SET_MASTER_DOMAIN(
+ DEVAPC0_MAS_DOM_GROUP_0,
+ MODULE_DOMAIN(MASTER_NFI, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_PWM, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_THERMAL_CTRL, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_MSDC0, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_MSDC1, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_MSDC2, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_MSDC3, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI0, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPM, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_DEBUG_SYSTEM, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_AUDIO_AFE, DOMAIN_2) |
+ MODULE_DOMAIN(MASTER_APMCU, DOMAIN_3)
+ );
+
+ DAPC_SET_MASTER_DOMAIN(
+ DEVAPC0_MAS_DOM_GROUP_1,
+ MODULE_DOMAIN(MASTER_MFG_M0, DOMAIN_1) |
+ MODULE_DOMAIN(MASTER_USB30, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI1, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI2, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI3, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI4, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SPI5, DOMAIN_0) |
+#ifdef CFG_TINYSYS_SCP_SUPPORT
+ MODULE_DOMAIN(MASTER_SCP, DOMAIN_3) |
+#else
+ MODULE_DOMAIN(MASTER_SCP, DOMAIN_1) |
+#endif
+ MODULE_DOMAIN(MASTER_USB30_2, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_SFLASH, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_GMAC, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_PCIE0, DOMAIN_0)
+ );
+
+ DAPC_SET_MASTER_DOMAIN(
+ DEVAPC0_MAS_DOM_GROUP_2,
+ MODULE_DOMAIN(MASTER_PCIE1, DOMAIN_0)
+ );
+
+ /* Set the transaction type of masters*/
+ DAPC_SET_MASTER_TRANSACTION(
+ DEVAPC0_MAS_SEC_GROUP_0,
+ MODULE_TRANSACTION(MASTER_NFI, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_PWM, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_THERMAL_CTRL, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_MSDC0, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_MSDC1, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_MSDC2, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_MSDC3, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI0, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPM, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_DEBUG_SYSTEM, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_AUDIO_AFE, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_APMCU, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_MFG_M0, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_USB30, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI1, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI2, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI3, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI4, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SPI5, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SCP, DAPC_S_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_USB30_2, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SFLASH, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_GMAC, DAPC_NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_PCIE0, DAPC_NS_TRANSACTION)
+ );
+
+ DAPC_SET_MASTER_TRANSACTION(
+ DEVAPC0_MAS_SEC_GROUP_1,
+ MODULE_TRANSACTION(MASTER_PCIE1, DAPC_NS_TRANSACTION)
+ );
+
+ /* Set the access permission of slaves in domain 0*/
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_0,
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_GPT ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_SEJ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SYS_TIMER_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IRRX_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO ,DAPC_SEC_RW) |
+ MODULE_PERMISSION(UART5_REG ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_1,
+ MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(TOP_RTC_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI4_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI1_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_GPT2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH0_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH1_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH2_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH3_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EFUSEC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_2,
+ MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BUS_DEBUG_TRAKER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_TRNG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU_NS ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_CQ_DMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU_M4U ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_3,
+ MODULE_PERMISSION(ANA_MIPI_CSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_CSI1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DEGBUG_CORESIGHT ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(AUXADC ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(PWM ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(THERM_CTRL ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_4,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SPI_NOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(NFI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(NFI_ECC ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C4 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(I2C5 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SPI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(UART4 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(GMAC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_5,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(AUDIO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF2_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SCPSYS_SRAM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PCIe0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(PCIe1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_6,
+ MODULE_PERMISSION(G3D_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MMSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WDMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_TDSHP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_TDSHP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_OVL0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OVL1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_RDMA0 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_7,
+ MODULE_PERMISSION(DISP_RDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_RDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_AAL ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_GAMMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_SPLIT0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_UFOE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DPI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_PWM0 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_8,
+ MODULE_PERMISSION(DISP_PWM1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MM_MUTEX ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OD ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DPI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(LVDS ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_AAL1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OD1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OVL2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(LVDS1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_9,
+ MODULE_PERMISSION(MDP_TDSHP2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB7 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_MONITOR0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_PWM2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IMGSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB2 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_10,
+ MODULE_PERMISSION(SENINF_TOP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SENINF_TOP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(BDP_DISPSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_DISPFMT ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_11,
+ MODULE_PERMISSION(BDP_VDO ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_NR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_NR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_TVD ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_DI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_VDI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_LARB ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_LARB_RT ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDECSYS_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDECSYS_SMI_LARB1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDEC_FULL_TOP ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IMGRZ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDEC_MBIST ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(JPGDEC_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(JPDEC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(
+ DEVAPC0_D0_APC_12,
+ MODULE_PERMISSION(JPDGDEC1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(VENC_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC_SMI_LARB3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC_SMI_LARB6 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SFLASH ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ /* Set the access permission of slaves in domain 1*/
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_0,
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_GPT ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_SEJ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SYS_TIMER_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IRRX_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART5_REG ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_1,
+ MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(TOP_RTC_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI4_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI1_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_GPT2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH0_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH1_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH2_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH3_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EFUSEC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_2,
+ MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BUS_DEBUG_TRAKER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_TRNG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU_NS ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_CQ_DMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU_M4U ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_CSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_CSI1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_3,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DEGBUG_CORESIGHT ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(AUXADC ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PWM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(THERM_CTRL ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_4,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SPI_NOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(NFI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(NFI_ECC ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(I2C5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SPI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(UART4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(GMAC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_5,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(AUDIO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF2_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SCPSYS_SRAM ,DAPC_SEC_RW) |
+ MODULE_PERMISSION(PCIe0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PCIe1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_6,
+ MODULE_PERMISSION(G3D_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MMSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WDMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_TDSHP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_TDSHP1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_OVL0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OVL1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_RDMA0 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_7,
+ MODULE_PERMISSION(DISP_RDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_RDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_AAL ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_GAMMA ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_SPLIT0 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_UFOE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DPI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_PWM0 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_8,
+ MODULE_PERMISSION(DISP_PWM1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MM_MUTEX ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OD ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DPI1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(LVDS ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB4 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_AAL1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OD1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OVL2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(LVDS1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_9,
+ MODULE_PERMISSION(MDP_TDSHP2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB5 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB7 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_MONITOR0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_PWM2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IMGSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB2 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_10,
+ MODULE_PERMISSION(SENINF_TOP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SENINF_TOP1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP4 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP5 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(BDP_DISPSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_DISPFMT ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_11,
+ MODULE_PERMISSION(BDP_VDO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_NR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_NR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_TVD ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_DI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_VDI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_LARB ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_LARB_RT ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDECSYS_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDECSYS_SMI_LARB1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDEC_FULL_TOP ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IMGRZ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDEC_MBIST ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(JPGDEC_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(JPDEC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(
+ DEVAPC0_D1_APC_12,
+ MODULE_PERMISSION(JPDGDEC1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(VENC_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC_SMI_LARB3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC_SMI_LARB6 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SFLASH ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ /* Set the access permission of slaves in domain 2*/
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_0,
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_GPT ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRA_AO_SEJ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SYS_TIMER_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IRRX_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART5_REG ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_1,
+ MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(TOP_RTC_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI4_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI1_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRA_AO_GPT2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH0_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH1_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH2_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DRAMC_CH3_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EFUSEC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_2,
+ MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BUS_DEBUG_TRAKER ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_TRNG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU_NS ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_CQ_DMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(INFRASYS_GCPU_M4U ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_DSI1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_3,
+ MODULE_PERMISSION(ANA_MIPI_CSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(ANA_MIPI_CSI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DEGBUG_CORESIGHT ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(AUXADC ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(UART3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PWM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(THERM_CTRL ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_4,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SPI_NOR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(NFI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(NFI_ECC ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(I2C4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(I2C5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SPI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SPI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(UART4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(GMAC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_5,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(AUDIO ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MSDC3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(USB3_0SIF2_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SCPSYS_SRAM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PCIe0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PCIe1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_6,
+ MODULE_PERMISSION(G3D_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MMSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RSZ2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WDMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_TDSHP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_TDSHP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_OVL0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OVL1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_RDMA0 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_7,
+ MODULE_PERMISSION(DISP_RDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_RDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_AAL ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_GAMMA ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_SPLIT0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_UFOE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DPI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_PWM0 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_8,
+ MODULE_PERMISSION(DISP_PWM1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MM_MUTEX ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OD ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DPI1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(LVDS ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_COLOR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_AAL1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OD1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_OVL2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_WDMA2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(LVDS1 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_9,
+ MODULE_PERMISSION(MDP_TDSHP2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB7 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_RDMA3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(MDP_WROT2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DSI3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(DISP_MONITOR0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_MONITOR3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(DISP_PWM2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IMGSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_LARB2 ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_10,
+ MODULE_PERMISSION(SENINF_TOP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SENINF_TOP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP0 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP4 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(CAMSV_TOP5 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(BDP_DISPSYS_CONFIG ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_DISPFMT ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_11,
+ MODULE_PERMISSION(BDP_VDO ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_NR ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_NR2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_TVD ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_DI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_VDI ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_LARB ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_LARB_RT ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDECSYS_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDECSYS_SMI_LARB1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDEC_FULL_TOP ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(IMGRZ ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VDEC_MBIST ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(JPGDEC_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(JPDEC ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(
+ DEVAPC0_D2_APC_12,
+ MODULE_PERMISSION(JPDGDEC1 ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(VENC_CONFIGURATION ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC_SMI_LARB3 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC_SMI_LARB6 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(SMI_COMMON_2 ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(VENC ,DAPC_SEC_DENY_NSEC_DENY) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_DENY_NSEC_DENY) | */
+ MODULE_PERMISSION(SFLASH ,DAPC_SEC_DENY_NSEC_DENY)
+ );
+
+ /* Set the access permission of slaves in domain 3*/
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_0,
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_INFRASYS_CONFIG_REGS ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_PERISYS_CONFIG_REGS ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_GPIO_CONTROLLER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_SLP_MANAGER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_TOP_LEVEL_RESET_GENERATOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_GPT ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRA_AO_SEJ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_APMCU_EINT_CONTROLLER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SYS_TIMER_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IRRX_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO ,DAPC_SEC_RW) |
+ MODULE_PERMISSION(UART5_REG ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_1,
+ MODULE_PERMISSION(INFRA_AO_KPAD_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(TOP_RTC_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI4_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI1_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRA_AO_GPT2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH0_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH1_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH2_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DRAMC_CH3_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_MCUSYS_CONFIG_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_BOOTROM_SRAM ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EMI_BUS_INTERFACE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_SYSTEM_CIRQ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_M4U_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EFUSEC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_2,
+ MODULE_PERMISSION(INFRASYS_DEVICE_APC_MONITOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BUS_DEBUG_TRAKER ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_AP_MIXED_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_M4U_2_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(INFRASYS_MBIST_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_EMI_MPU_CONTROL_REG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_TRNG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU_NS ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_CQ_DMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(INFRASYS_GCPU_M4U ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_DSI1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_3,
+ MODULE_PERMISSION(ANA_MIPI_CSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(ANA_MIPI_CSI1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DEGBUG_CORESIGHT ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(AUXADC ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(UART3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(PWM ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(THERM_CTRL ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_4,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SPI_NOR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(NFI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(NFI_ECC ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(I2C4 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(I2C5 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SPI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SPI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(UART4 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(GMAC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_5,
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(AUDIO ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MSDC3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(USB3_0SIF2_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SCPSYS_SRAM ,DAPC_SEC_DENY_NSEC_DENY) |
+ MODULE_PERMISSION(PCIe0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(PCIe1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_6,
+ MODULE_PERMISSION(G3D_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MMSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RSZ2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WDMA ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_TDSHP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_TDSHP1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_OVL0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OVL1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_RDMA0 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_7,
+ MODULE_PERMISSION(DISP_RDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_RDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_AAL ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_GAMMA ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_SPLIT0 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_UFOE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DPI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_PWM0 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_8,
+ MODULE_PERMISSION(DISP_PWM1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MM_MUTEX ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OD ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DPI1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(LVDS ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB4 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_COLOR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_AAL1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OD1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_OVL2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_WDMA2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(LVDS1 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_9,
+ MODULE_PERMISSION(MDP_TDSHP2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB5 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB7 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_RDMA3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(MDP_WROT2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DSI3 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(DISP_MONITOR0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_MONITOR3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(DISP_PWM2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IMGSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_LARB2 ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_10,
+ MODULE_PERMISSION(SENINF_TOP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SENINF_TOP1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP0 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP4 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(CAMSV_TOP5 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(BDP_DISPSYS_CONFIG ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_DISPFMT ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_11,
+ MODULE_PERMISSION(BDP_VDO ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_NR ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_NR2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_TVD ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_DI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_WR_CHANNEL_VDI ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_LARB ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_LARB_RT ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(BDP_DRAM2AXI_BRIDGE ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDECSYS_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDECSYS_SMI_LARB1 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDEC_FULL_TOP ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(IMGRZ ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VDEC_MBIST ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(JPGDEC_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(JPDEC ,DAPC_SEC_RW_NSEC_RW)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(
+ DEVAPC0_D3_APC_12,
+ MODULE_PERMISSION(JPDGDEC1 ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(VENC_CONFIGURATION ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC_SMI_LARB3 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC_SMI_LARB6 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(SMI_COMMON_2 ,DAPC_SEC_RW_NSEC_RW) |
+ MODULE_PERMISSION(VENC ,DAPC_SEC_RW_NSEC_RW) |
+ /* MODULE_PERMISSION(Reserved ,DAPC_SEC_RW_NSEC_RW) | */
+ MODULE_PERMISSION(SFLASH ,DAPC_SEC_RW_NSEC_RW)
+ );
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c b/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c
new file mode 100644
index 0000000..80bbcc0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/drivers/tz_apc.c
@@ -0,0 +1,211 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2018. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES */
+/*=======================================================================*/
+#include "tz_apc.h"
+#include "device_apc.h"
+#include "print.h"
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE (0x00000000U) /* No event */
+#define DBG_EVT_ERR (0x00000001U) /* ERR related event */
+#define DBG_EVT_DOM (0x00000002U) /* DOM related event */
+
+#define DBG_EVT_ALL (0xffffffffU)
+
+#define DBG_EVT_MASK (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+ do { \
+ if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+ print(fmt, ##args); \
+ } \
+ } while(0)
+
+#define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{}while(0)
+#define MSG_FUNC_ENTRY(f) do{}while(0)
+#endif
+
+/* MTK SMI bdpsys larb domain setting (larb8 and larb9) */
+static void tz_apc_smi_bdpsys_sec_init()
+{
+ u32 reg, domain = 0;/* always be domain 0.*/
+
+ /* Larb8 */
+ reg = reg_read32(SMI_BDPSYS_LARB8_BASE);
+ reg &= ~SMI_BDPSYS_DOMAIN_MASK;
+ reg |= SMI_BDPSYS_AR_DOMAIN(domain) | SMI_BDPSYS_AW_DOMAIN(domain);
+ reg_write32(SMI_BDPSYS_LARB8_BASE, reg);
+
+ /* Larb9 */
+ reg = reg_read32(SMI_BDPSYS_LARB9_BASE);
+ reg &= ~SMI_BDPSYS_DOMAIN_MASK;
+ reg |= SMI_BDPSYS_AR_DOMAIN(domain) | SMI_BDPSYS_AW_DOMAIN(domain);
+ reg_write32(SMI_BDPSYS_LARB9_BASE, reg);
+}
+
+void tz_apc_common_init()
+{
+#ifdef CFG_TZ_SRAMROM_SUPPORT
+ u32 domain_permission = 0U;
+#endif /* CFG_TZ_SRAMROM_SUPPORT */
+
+#ifdef CFG_TZ_SRAMROM_SUPPORT
+ /* Enabling this bit to protect all multimedia secure related registers,
+ including SMI, accessing in non-secure world. */
+ domain_permission |= TZ_SRAMROM_ENABLE_MULTIMEDIA_SECURE_ACCESS;
+ /* Enable this bit to protect sramrom region 1 by its security setting */
+ domain_permission |= TZ_SRAMROM_ENABLE_REGION_1_PROTECTION;
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+ TZ_APC_DOMAIN_IVI, TZ_SRAMROM_SEC_RW_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+ TZ_APC_DOMAIN_CLUSTER, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+ TZ_APC_DOMAIN_DSP, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_0,
+ TZ_APC_DOMAIN_MCU, TZ_SRAMROM_SEC_RW_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+ TZ_APC_DOMAIN_IVI, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+ TZ_APC_DOMAIN_CLUSTER, TZ_SRAMROM_SEC_DENY_NSEC_DENY);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+ TZ_APC_DOMAIN_DSP, TZ_SRAMROM_SEC_RW_NSEC_RW);
+ domain_permission |= tz_sramrom_set_bitwise_domain_permision(TZ_SRAMROM_REGION_1,
+ TZ_APC_DOMAIN_MCU, TZ_SRAMROM_SEC_RW_NSEC_RW);
+ reg_write32(SRAMROM_SEC_CTRL, domain_permission);
+ TZ_SRAMROM_SET_REGION_0_SIZE_KB(96);
+#endif /* CFG_TZ_SRAMROM_SUPPORT */
+
+#ifdef CFG_TZ_UART_APDMA_SUPPORT
+
+ /* GLOBAL GSEC_EN */
+ reg_write32(APDMA_GLOBAL_GSEC_CTRL, reg_read32(APDMA_GLOBAL_GSEC_CTRL) | APDMA_GLOBAL_GSEC_EN);
+
+#if 0
+ /* Setting TX0/RX0 */
+ domain_permission = reg_read32(APDMA_UART_TX0_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX0_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX0_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX0_SEC_CTRL, domain_permission);
+
+ /* Setting TX1/RX1 */
+ domain_permission = reg_read32(APDMA_UART_TX1_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX1_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX1_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX1_SEC_CTRL, domain_permission);
+
+ /* Setting TX2/RX2 */
+ domain_permission = reg_read32(APDMA_UART_TX2_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX2_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX2_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX2_SEC_CTRL, domain_permission);
+
+ /* Setting TX3/RX3 */
+ domain_permission = reg_read32(APDMA_UART_TX3_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX3_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX3_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX3_SEC_CTRL, domain_permission);
+#endif
+
+ /* Setting TX4/RX4 */
+ domain_permission = reg_read32(APDMA_UART_TX4_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_IVI<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX4_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX4_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_IVI<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX4_SEC_CTRL, domain_permission);
+
+#if 0
+ /* Setting TX5/RX5 */
+ domain_permission = reg_read32(APDMA_UART_TX5_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_TX5_SEC_CTRL, domain_permission);
+
+ domain_permission = reg_read32(APDMA_UART_RX5_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_UART_APDMA_NSEC;
+ reg_write32(APDMA_UART_RX5_SEC_CTRL, domain_permission);
+
+ /* Setting CQDMA */
+ domain_permission = reg_read32(CQDMA_SEC_CTRL);
+ domain_permission |= TZ_APC_DOMAIN_CLUSTER<<1;
+ domain_permission |= TZ_CQDMA_NSEC;
+ reg_write32(CQDMA_SEC_CTRL, domain_permission);
+#endif
+#endif
+
+ /* Set domain of masters and their transaction type.
+ Set access permission of slaves in each domain. */
+ tz_dapc_sec_setting();
+}
+
+void tz_apc_common_postinit()
+{
+ tz_apc_smi_bdpsys_sec_init();
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/main.c b/src/bsp/trustzone/teeloader/mt2712/src/main.c
new file mode 100644
index 0000000..c3ea768
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/main.c
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#include "platform.h"
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+ return ATF_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg, unsigned long boot_reason)
+{
+ atf_arg->bootarg_loc = 0;
+ atf_arg->bootarg_size = 0;
+ atf_arg->bl33_start_addr = BL33;
+ atf_arg->tee_info_addr = ATF_INIT_ARG_ADDR;
+ atf_arg->boot_reason = boot_reason;
+}
+
+int teeloader_main(unsigned long bl33_addr, unsigned long boot_reason)
+{
+ u32 tee_addr = 0;
+ mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+
+ set_atf_parameters(atf_arg, boot_reason);
+
+ /* marked because no device APC support */
+ //device_APC_dom_setup();
+ trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+ tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+ /* set tee entry address */
+ tee_set_entry(tee_addr);
+ tee_set_hwuid();
+ tee_set_msg_auth_key();
+
+ trustzone_post_init();
+ trustzone_jump(BL31, BL33, tee_addr);
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/print.c b/src/bsp/trustzone/teeloader/mt2712/src/print.c
new file mode 100644
index 0000000..34622c7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+ uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+ while (*s) {
+ if (*s == '\n')
+ outchar('\r');
+ outchar(*s++);
+ }
+}
+
+static void outdec(unsigned long n)
+{
+ if (n >= 10) {
+ outdec(n / 10);
+ n %= 10;
+ }
+ outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+ if (depth)
+ depth--;
+
+ if ((n & ~0xf) || depth) {
+ outhex(n >> 4, depth);
+ n &= 0xf;
+ }
+
+ if (n < 10) {
+ outchar((unsigned char)(n + '0'));
+ } else {
+ outchar((unsigned char)(n - 10 + 'A'));
+ }
+}
+
+void vprint(char *fmt, va_list vl)
+{
+ unsigned char c;
+ unsigned int reg = 1; /* argument register number (32-bit) */
+
+ while (*fmt) {
+ c = *fmt++;
+ switch (c) {
+ case '%':
+ c = *fmt++;
+ switch (c) {
+ case 'x':
+ outhex(va_arg(vl, unsigned long), 0);
+ break;
+ case 'B':
+ outhex(va_arg(vl, unsigned long), 2);
+ break;
+ case 'H':
+ outhex(va_arg(vl, unsigned long), 4);
+ break;
+ case 'X':
+ outhex(va_arg(vl, unsigned long), 8);
+ break;
+ case 'l':
+ if (*fmt == 'l' && *(fmt + 1) == 'x') {
+ u32 ltmp;
+ u32 htmp;
+
+ ltmp = va_arg(vl, unsigned int);
+ htmp = va_arg(vl, unsigned int);
+
+ outhex(htmp, 8);
+ outhex(ltmp, 8);
+ fmt += 2;
+ }
+ break;
+ case 'd':
+ {
+ long l;
+
+ l = va_arg(vl, long);
+ if (l < 0) {
+ outchar('-');
+ l = -l;
+ }
+ outdec((unsigned long)l);
+ }
+ break;
+ case 'u':
+ outdec(va_arg(vl, unsigned long));
+ break;
+ case 's':
+ outstr((const unsigned char *)
+ va_arg(vl, char *));
+ break;
+ case '%':
+ outchar('%');
+ break;
+ case 'c':
+ c = va_arg(vl, int);
+ outchar(c);
+ break;
+ default:
+ outchar(' ');
+ break;
+ }
+ reg++; /* one argument uses 32-bit register */
+ break;
+ case '\r':
+ if (*fmt == '\n')
+ fmt++;
+ c = '\n';
+ // fall through
+ case '\n':
+ outchar('\r');
+ // fall through
+ default:
+ outchar(c);
+ }
+ }
+}
+
+void print(char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vprint(fmt, args);
+ va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c b/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c
new file mode 100644
index 0000000..b70f923
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/seclib.c
@@ -0,0 +1,88 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "hacc_export.h"
+#include "string.h"
+#include "print.h"
+
+#define HRID (0x10206140UL)
+#define SOC_DATA (0x08000000UL)
+#define HW_DATA_SIZE (0x4UL)
+
+#define MOD "[SECLIB]"
+
+int seclib_get_key(u32 hwaddr, u8 *key, u32 key_size, int index)
+{
+ u32 hwdata[HW_DATA_SIZE] = {0};
+ int i = 0;
+
+ if (key_size != sizeof(hwdata))
+ {
+ return -1;
+ }
+ for (i = 0; i < HW_DATA_SIZE; i++)
+ {
+ hwdata[i] = READ_REGISTER_UINT32(hwaddr + (i * sizeof(u32)));
+ }
+ if (0 != seclib_get_data_key((u8 *)hwdata, key_size, (u8 *)key, index))
+ {
+ return -1;
+ }
+ DBG_MSG("%s HWDATA : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, hwdata[0], hwdata[1], hwdata[2], hwdata[3]);
+
+ return 0;
+}
+
+int seclib_get_hrid_key(u32 *key, u32 key_size)
+{
+ u32 hrkey[HW_DATA_SIZE] = {0};
+
+ if (0 != seclib_get_key(HRID, (u8 *)hrkey, sizeof(hrkey), 1))
+ {
+ return -1;
+ }
+ key[0]=hrkey[0];
+ key[1]=hrkey[1];
+
+ return 0;
+}
+
+int seclib_get_hwid_key(u8 *key, u32 key_size)
+{
+ return seclib_get_key(SOC_DATA, key, key_size, 2);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..cbeb21a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_emi_mpu.c
@@ -0,0 +1,258 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+ int ret = 0;
+
+ if (end <= start)
+ {
+ DBG_MSG("%s, Invalid address! End address should larger than start address.\n", MOD);
+ return -1;
+ }
+
+
+ if((end >> 31) && !(start >> 31))
+ {
+ DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n", MOD);
+ return -1;
+ }
+
+ if ((readl(PERIAXI_BUS_CTL3) & PERISYS_4G_SUPPORT) == 0)
+ {
+ start = start - EMI_PHY_OFFSET;
+ end = end - EMI_PHY_OFFSET;
+ DBG_MSG("%s, MPU 2GB mode.\n", MOD);
+ }
+ else
+ DBG_MSG("%s, MPU 4GB mode.\n", MOD);
+
+ /*Address 64KB alignment*/
+ start = start >> 16;
+ end = end >> 16;
+
+ switch (region) {
+ case 0:
+ writel(0, EMI_MPU_APC0);
+ writel(start, EMI_MPU_SA0);
+ writel(end, EMI_MPU_EA0);
+ writel(access_permission, EMI_MPU_APC0);
+ break;
+
+ case 1:
+ writel(0, EMI_MPU_APC1);
+ writel(start, EMI_MPU_SA1);
+ writel(end, EMI_MPU_EA1);
+ writel(access_permission, EMI_MPU_APC1);
+ break;
+
+ case 2:
+ writel(0, EMI_MPU_APC2);
+ writel(start, EMI_MPU_SA2);
+ writel(end, EMI_MPU_EA2);
+ writel(access_permission, EMI_MPU_APC2);
+ break;
+
+ case 3:
+ writel(0, EMI_MPU_APC3);
+ writel(start, EMI_MPU_SA3);
+ writel(end, EMI_MPU_EA3);
+ writel(access_permission, EMI_MPU_APC3);
+ break;
+
+ case 4:
+ writel(0, EMI_MPU_APC4);
+ writel(start, EMI_MPU_SA4);
+ writel(end, EMI_MPU_EA4);
+ writel(access_permission, EMI_MPU_APC4);
+ break;
+
+ case 5:
+ writel(0, EMI_MPU_APC5);
+ writel(start, EMI_MPU_SA5);
+ writel(end, EMI_MPU_EA5);
+ writel(access_permission, EMI_MPU_APC5);
+ break;
+
+ case 6:
+ writel(0, EMI_MPU_APC6);
+ writel(start, EMI_MPU_SA6);
+ writel(end, EMI_MPU_EA6);
+ writel(access_permission, EMI_MPU_APC6);
+ break;
+
+ case 7:
+ writel(0, EMI_MPU_APC7);
+ writel(start, EMI_MPU_SA7);
+ writel(end, EMI_MPU_EA7);
+ writel(access_permission, EMI_MPU_APC7);
+ break;
+
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+/* sample code for scenario as below: */
+/* mpu region2: 0x40000000 - 0xe0000000 (2.5GB) is secure RW and non-secure RW for domain 0, 3.*/
+/* mpu region3: 0xe0000000 - 0xe0080000 (512K) is secure RW and non-secure RW for domain 0, 2, 3.*/
+/* mpu region4: 0xe0080000 - 0xe0880000 (8M) is secure and non-secure RW for domain 2, 3.*/
+/* mpu region5: 0xe0880000 - 0xec880000 (384M) is secure RW and non-secure RW for domain 1, 2, 3.*/
+/* mpu region6: 0xec880000 - 0xec8e0000 (384K) is secure RW and non-secure RW for domain 0, 1, 3.*/
+/* mpu region7: 0xec8e0000 - 0xf48e0000 (128M) is secure RW for domain 0, 3.*/
+
+void tz_emi_mpu_init_2(void)
+{
+ int ret = 0;
+ unsigned int sec_mem_mpu_attr;
+
+ /*region2 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0x40000000, /*START_ADDR*/
+ 0xe0000000, /*END_ADDR*/
+ 2, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region3 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0xe0000000, /*START_ADDR*/
+ 0xe0080000, /*END_ADDR*/
+ 3, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region4 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xe0080000, /*START_ADDR*/
+ 0xe0880000, /*END_ADDR*/
+ 4, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region5 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xe0880000, /*START_ADDR*/
+ 0xec880000, /*END_ADDR*/
+ 5, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region6 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0xec880000, /*START_ADDR*/
+ 0xec8e0000, /*END_ADDR*/
+ 6, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region7 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xec8e0000, /*START_ADDR*/
+ 0xf48e0000, /*END_ADDR*/
+ 7, /*region*/
+ sec_mem_mpu_attr);
+
+ if(ret)
+ DBG_MSG("%s MPU error!!\n", MOD);
+
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+ int ret = 0;
+ unsigned int sec_mem_mpu_attr;
+ unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+ /* Caculate start/end address */
+ sec_mem_phy_start = start_add;
+ sec_mem_phy_end = end_addr;
+
+ switch(mpu_region)
+ {
+ case SECURE_OS_MPU_REGION_ID:
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ break;
+
+ case ATF_MPU_REGION_ID:
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ break;
+
+ default:
+ DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+ return;
+ }
+
+ DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+ ret = emi_mpu_set_region_protection(sec_mem_phy_start, /*START_ADDR*/
+ sec_mem_phy_end, /*END_ADDR*/
+ mpu_region, /*region*/
+ sec_mem_mpu_attr);
+
+ if(ret)
+ {
+ DBG_MSG("%s MPU error!!\n", MOD);
+ }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c
new file mode 100644
index 0000000..7d05e99
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_init.c
@@ -0,0 +1,268 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "seclib.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "tz_apc.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+#if CFG_TRUSTKERNEL_TEE_SUPPORT
+#include "tz_tkcore.h"
+#endif
+
+/**************************************************************************
+ * DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+/**************************************************************************
+ * MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000U) //4K Alignment
+#define TEE_ENABLE_VERIFY (1U)
+
+/**************************************************************************
+ * EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ * INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+static u32 msg_auth_key[8];
+
+/**************************************************************************
+ * INTERNAL FUNCTIONS
+ **************************************************************************/
+
+static u64 trustzone_get_atf_init_param_addr(void)
+{
+ return ATF_INIT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+
+void tee_set_entry(u32 addr)
+{
+ tee_entry_addr = addr;
+
+ DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(void)
+{
+ atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[0], g_hwuid[1], g_hwuid[2], g_hwuid[3]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[4], g_hwuid[5], g_hwuid[6], g_hwuid[7]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[8], g_hwuid[9], g_hwuid[10], g_hwuid[11]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[12], g_hwuid[13], g_hwuid[14], g_hwuid[15]);
+ memcpy(teearg->hwuid, g_hwuid, sizeof(g_hwuid));
+ g_hwuid_initialized = 1;
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+ int ret = 0;
+
+ if (!g_hwuid_initialized)
+ {
+ ret = seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+ if(ret != 0)
+ return ret;
+ }
+ memcpy(id, g_hwuid, size);
+ return ret;
+}
+
+void tee_set_msg_auth_key(void)
+{
+ int i;
+ atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ seclib_get_msg_auth_key((unsigned char *) msg_auth_key, 32);
+
+ DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[0], msg_auth_key[1], msg_auth_key[2], msg_auth_key[3]);
+ DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[4], msg_auth_key[5], msg_auth_key[6], msg_auth_key[7]);
+
+ memcpy(teearg->msg_auth_key, msg_auth_key, sizeof(msg_auth_key));
+}
+
+static void tee_sec_config(void)
+{
+ u32 atf_entry_addr = BL31;
+
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+ /* memory protection for TEE */
+#if CFG_TRUSTKERNEL_TEE_SUPPORT
+ u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - TKCORE_SHM_SIZE_LIMIT - 1;
+#else
+ u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+#endif
+
+ tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+ DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+ secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+
+ /* memory protection for ATF */
+ atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+ u32 atf_end_addr = atf_entry_addr + BL31_SIZE - 1;
+
+ DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+ tz_sec_mem_init(atf_entry_addr, atf_end_addr, ATF_MPU_REGION_ID);
+ DBG_MSG("%s set ATF memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+ atf_end_addr, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+ tz_dapc_sec_init();
+
+#if CFG_ATF_LOG_SUPPORT
+ atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#endif
+
+#if CFG_TEE_SUPPORT
+ tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+ tz_apc_common_init();
+}
+
+void trustzone_post_init(void)
+{
+ atf_arg_t_ptr atf_init_arg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ atf_init_arg->atf_magic = ATF_BOOTCFG_MAGIC;
+ atf_init_arg->tee_entry = tee_entry_addr;
+ atf_init_arg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+ seclib_get_hrid_key(atf_init_arg->HRID, sizeof(atf_init_arg->HRID));
+ atf_init_arg->atf_log_port = 0x11002000;
+ atf_init_arg->atf_log_baudrate = 0xE1000;
+ atf_init_arg->atf_irq_num = 267; /* reserve SPI ID for ATF log */
+ atf_init_arg->devinfo[0] = 0;
+ atf_init_arg->devinfo[1] = 0;
+ atf_init_arg->devinfo[2] = 0xFFFFFFFF;
+ atf_init_arg->devinfo[3] = 0xFFFFFFFF;
+
+ DBG_MSG("%s HRID[0] : 0x%x\n", MOD, atf_init_arg->HRID[0]);
+ DBG_MSG("%s HRID[1] : 0x%x\n", MOD, atf_init_arg->HRID[1]);
+ DBG_MSG("%s atf_log_port : 0x%x\n", MOD, atf_init_arg->atf_log_port);
+ DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, atf_init_arg->atf_log_baudrate);
+ DBG_MSG("%s atf_irq_num : %d\n", MOD, atf_init_arg->atf_irq_num);
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+ tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+ tee_secmem_size);
+ tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+ CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+ atf_init_arg->tee_support = 1;
+#elif CFG_TRUSTKERNEL_TEE_SUPPORT
+ tkcore_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, tee_secmem_size,
+ CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE,
+ atf_init_arg->atf_log_port);
+ tkcore_boot_param_prepare_rpmbkey(TEE_BOOT_ARG_ADDR);
+ /* only useful for non-ATF platform */
+ tkcore_boot_param_prepare_nwbootargs(TEE_BOOT_ARG_ADDR, 0U, 0U);
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+ tkcore_boot_sdrpmb_init_finish(TEE_BOOT_ARG_ADDR);
+#endif
+ //prepare the parameter for secure driver here
+ atf_init_arg->tee_support = 1;
+#elif CFG_OPTEE_TEE_SUPPORT
+ atf_init_arg->tee_support = 1;
+#else
+ atf_init_arg->tee_support = 0;
+#endif
+ tz_dapc_sec_postinit();
+ tz_apc_common_postinit();
+
+#if CFG_ATF_LOG_SUPPORT
+ atf_init_arg->atf_log_buf_start = atf_log_buf_start;
+ atf_init_arg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+ atf_init_arg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+ atf_init_arg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+ atf_init_arg->atf_log_buf_start = 0;
+ atf_init_arg->atf_log_buf_size = 0;
+ atf_init_arg->atf_aee_debug_buf_start = 0;
+ atf_init_arg->atf_aee_debug_buf_size = 0;
+#endif
+ DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, atf_init_arg->atf_log_buf_start);
+ DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, atf_init_arg->atf_log_buf_size);
+ DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_start);
+ DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+ u32 bl31_reserve = 0;
+ jump_atf atf_entry = (void *)addr;
+
+ /* EMI MPU support */
+ tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+ DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+ DBG_MSG("%s Jump to ATF, then jump 0x%x\n", MOD, arg1);
+#endif
+
+ atf_entry = (jump_atf)BL31;
+ REL_MSG("[teeloader] tl jump to atf!\n");
+ (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..e60d671
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_sec_cfg.c
@@ -0,0 +1,47 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+ tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c
new file mode 100644
index 0000000..e5da33a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tbase.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+
+#define MOD "[TZ_TBASE]"
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ * EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+ u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+ int ret = 0;
+ sec_mem_arg_t sec_mem_arg;
+ u8 hwuid[16];
+ unsigned char i, *ptmp, tmpbuf;
+
+ ret = tee_get_hwuid(hwuid, 16);
+ if (ret)
+ DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+ /* Prepare secure memory configuration parameters */
+ sec_mem_arg.magic = SEC_MEM_MAGIC;
+ sec_mem_arg.version = SEC_MEM_VERSION;
+ sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+ sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+ sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+ sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+ sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+ sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+ /* set msg auth key by seclib support */
+ seclib_get_msg_auth_key((unsigned char *) sec_mem_arg.msg_auth_key, 32);
+
+ sec_mem_arg.rpmb_size = 128*1024; /* 128kx1: minimum size */
+ sec_mem_arg.emmc_rel_wr_sec_c = 1;
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+ sec_mem_arg.secmem_obfuscation = 1;
+#else
+ sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+ DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+ DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+ DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+ DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+ DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+ DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+ DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+ DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+ DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+ DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+ DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+ DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+ DBG_MSG("%s emmc_rel_wr_sec_c: 0x%x\n", MOD, sec_mem_arg.emmc_rel_wr_sec_c);
+
+ memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+ u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+ /* Prepare TEE boot parameters */
+ teearg->magic = TBASE_BOOTCFG_MAGIC; /* Trustonic's TEE magic number */
+ teearg->length = sizeof(tee_arg_t); /* Trustonic's TEE argument block size */
+ //teearg->version = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+ teearg->dRamBase = dram_base; /* DRAM base address */
+ teearg->dRamSize = dram_size; /* Full DRAM size */
+ teearg->secDRamBase = tee_entry; /* Secure DRAM base address */
+ teearg->secDRamSize = tbase_sec_dram_size; /* Secure DRAM size */
+ teearg->secIRamBase = TEE_SECURE_ISRAM_ADDR; /* Secure SRAM base address */
+ teearg->secIRamSize = TEE_SECURE_ISRAM_SIZE; /* Secure SRAM size */
+ //teearg->conf_mair_el3 = read_mair_el3();
+ //teearg->MSMPteCount = totalPages;
+ //teearg->MSMBase = (u64)registerFileL2;
+ //teearg->gic_distributor_base = TBASE_GIC_DIST_BASE;
+ //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+ //teearg->gic_version = TBASE_GIC_VERSION;
+ teearg->total_number_spi = 256; /* Support total 256 SPIs */
+ teearg->ssiq_number = 266; /* reserve SPI ID 266 for <t-base */
+ //teearg->flags = TBASE_MONITOR_FLAGS;
+
+ DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+ DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+ DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+ DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+ DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+ DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+ DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+ DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+ DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+ DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c
new file mode 100644
index 0000000..15aeddf
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/security/tz_tkcore.c
@@ -0,0 +1,396 @@
+/* Include header files */
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "uart.h"
+#include "platform.h"
+
+#include "tz_tkcore.h"
+
+#define MOD "[TZ_TKCORE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+#if CFG_BOOT_ARGUMENT_BY_ATAG
+extern unsigned int g_uart;
+#elif CFG_BOOT_ARGUMENT && !CFG_BOOT_ARGUMENT_BY_ATAG
+#define bootarg g_dram_buf->bootarg
+#endif
+
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+
+struct sdrpmb_info {
+ int failed; int part_id;
+ u32 sdrpmb_part_start;
+
+ u32 sdrpmb_partaddr;
+ u32 sdrpmb_partsize;
+ u32 sdrpmb_starting_sector;
+ u32 sdrpmb_nr_sectors;
+} sdrpmb_info = { 0, -1, 0U, 0U, 0U, 0U, 0U };
+
+int tz_mmc_clr_write_prot(struct mmc_card *card, u32 addr);
+
+void clr_wp(u32 wp_sector, u32 nr_sects)
+{
+ u32 i;
+ int err = 0;
+ struct mmc_card *card;
+
+ u32 grpsector = SDRPMB_REGION_ALIGNMENT / 512;
+
+ print("Clear WP 0x%x 0x%x\n", wp_sector, nr_sects);
+
+ if (!(card = mmc_get_card(0))) {
+ print("invalid card\n");
+ return;
+ }
+
+ if (!mmc_card_mmc(card)) {
+ print("not mmc card!!!\n");
+ return;
+ }
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+ print("invalid mmc spec: 0x%x", card->csd.mmca_vsn);
+ return;
+ }
+
+ for (i = 0; i < nr_sects; i += grpsector) {
+ err = tz_mmc_clr_write_prot(card, wp_sector + i);
+ if (err) {
+ print("clear wp 0x%x failed with %d\n",
+ wp_sector + i, err);
+ }
+ }
+
+ return;
+}
+
+static u64 mblock_reserve_dryrun(mblock_info_t *mblock_info, u64 reserved_size)
+{
+ int i, max_rank, target = -1;
+ u64 start, end, sz, max_addr = 0;
+ u64 reserved_addr = 0, align, limit;
+ mblock_t mblock;
+
+ align = 1ULL << 20;
+ /* address cannot go beyond 64bit */
+ limit = 0x100000000ULL;
+ /* always allocate from the larger rank */
+ max_rank = mblock_info->mblock_num - 1;
+
+ for (i = 0; i < mblock_info->mblock_num; i++) {
+ start = mblock_info->mblock[i].start;
+ sz = mblock_info->mblock[i].size;
+ end = limit < (start + sz)? limit: (start + sz);
+ reserved_addr = (end - reserved_size);
+ reserved_addr &= ~(align - 1);
+ if ((reserved_addr + reserved_size <= start + sz) &&
+ (reserved_addr >= start) &&
+ (mblock_info->mblock[i].rank <= max_rank) &&
+ (start + sz > max_addr) &&
+ (reserved_addr + reserved_size <= limit)) {
+ max_addr = start + sz;
+ target = i;
+ }
+ }
+
+ if (target < 0) {
+ printf("mblock_reserve error\n");
+ return 0;
+ }
+
+ start = mblock_info->mblock[target].start;
+ sz = mblock_info->mblock[target].size;
+ end = limit < (start + sz)? limit: (start + sz);
+ reserved_addr = (end - reserved_size);
+ reserved_addr &= ~(align - 1);
+
+ return reserved_addr;
+}
+
+/* note that memory is not really reserved */
+static int reserve_tmpmem(mblock_info_t *mblock_info, u32 *addr, u32 size)
+{
+ u64 _addr = mblock_reserve_dryrun(mblock_info, size);
+ if (_addr == 0ULL) {
+ return -1;
+ }
+
+ /* we only reserve memory lower than 32-bit address, thus
+ we can safely convert variable to u32 */
+ *addr = (u32) _addr;
+ return 0;
+}
+
+void sdrpmb_init_set_failed(void)
+{
+ sdrpmb_info.failed = 1;
+ sdrpmb_info.sdrpmb_partaddr = SDRPMB_FAILURE_MAGIC;
+ sdrpmb_info.sdrpmb_partsize = 0;
+}
+
+void tkcore_boot_param_prepare_sdrpmb_region(part_t *part)
+{
+ if (sdrpmb_info.failed || part == NULL) {
+ return;
+ }
+
+ sdrpmb_info.part_id = part->part_id;
+
+ u32 sect = part->start_sect + part->nr_sects;
+
+ if (sect < SDRPMB_REGION_SIZE / 512) {
+ printf("%s: unexpected MMC size: %u sectors\n", MOD, sect);
+ goto err;
+ }
+ sect -= SDRPMB_REGION_SIZE / 512;
+ /* sect % N must be smaller than sect */
+ sect -= sect % (SDRPMB_REGION_ALIGNMENT / 512);
+
+ if (sect < part->start_sect) {
+ printf("%s: unexpected sdrpmb partition start: %u size: %u\n", MOD, part->start_sect, part->nr_sects);
+ goto err;
+ }
+
+ sdrpmb_info.sdrpmb_part_start = part->start_sect;
+
+ sdrpmb_info.sdrpmb_starting_sector = sect;
+ sdrpmb_info.sdrpmb_nr_sectors = SDRPMB_REGION_SIZE / 512;
+
+ return;
+
+err:
+ sdrpmb_init_set_failed();
+}
+
+#define TKCORE_MAGIC 0xdeadbeef
+
+void check_for_sdrpmb_flag(u64 start_byte ,blkdev_t *bootdev)
+{
+ int ret;
+ u32 magic;
+
+ if (sdrpmb_info.failed)
+ return;
+
+ /* check if sdrpmb region is not reserved */
+ if (sdrpmb_info.part_id < 0)
+ return;
+
+ if ((ret = blkdev_read(bootdev, start_byte, 4, (u8 *) &magic, sdrpmb_info.part_id))) {
+ print("%s: read magic failed with %d", MOD, ret);
+ return;
+ }
+
+ if (magic == TKCORE_MAGIC)
+ return;
+
+ magic = TKCORE_MAGIC;
+
+ if ((ret = blkdev_write(bootdev, start_byte, 4, (u8 *) &magic, sdrpmb_info.part_id))) {
+ print("%s: write magic failed with %d", MOD, ret);
+ }
+
+ clr_wp(sdrpmb_info.sdrpmb_starting_sector, sdrpmb_info.sdrpmb_nr_sectors);
+}
+
+void tkcore_boot_param_prepare_sdrpmb_data(mblock_info_t *mblock, blkdev_t *bootdev)
+{
+ int ret = 0;
+ u64 start_byte;
+
+ if (sdrpmb_info.failed)
+ return;
+
+ /* check if sdrpmb region is not reserved */
+ if (sdrpmb_info.part_id < 0)
+ return;
+
+ if (mblock == NULL || bootdev == NULL) {
+ ret = -1;
+ goto out;
+ }
+
+ sdrpmb_info.sdrpmb_partsize = SDRPMB_DATA_SIZE << 1;
+ ret = reserve_tmpmem(mblock, &(sdrpmb_info.sdrpmb_partaddr), SDRPMB_DATA_SIZE << 1);
+ if (ret) {
+ printf("%s: reserve memory failed\n", MOD);
+ goto out;
+ }
+
+ check_for_sdrpmb_flag(((u64) sdrpmb_info.sdrpmb_part_start) * 512,
+ bootdev);
+
+ /* TODO use sector size instead of the hard coded 512 */
+ start_byte = ((u64) sdrpmb_info.sdrpmb_starting_sector) * 512;
+
+ if ((ret = blkdev_read(bootdev, start_byte, SDRPMB_DATA_SIZE,
+ (u8 *) (sdrpmb_info.sdrpmb_partaddr), sdrpmb_info.part_id))) {
+ printf("%s: read SDRPMB.0 failed", MOD);
+ goto out;
+ }
+
+ if ((ret = blkdev_read(bootdev, start_byte + SDRPMB_REGION_ALIGNMENT,
+ SDRPMB_DATA_SIZE, (u8 *) (sdrpmb_info.sdrpmb_partaddr + SDRPMB_DATA_SIZE),
+ sdrpmb_info.part_id))) {
+ printf("%s: read SDRPMB.1 failed", MOD);
+ goto out;
+ }
+
+out:
+ if (ret)
+ sdrpmb_init_set_failed();
+ return;
+}
+
+static void get_wp_status(u32 wp_addr)
+{
+ int err;
+ struct mmc_card *card;
+ u32 wp_status;
+
+ if (!(card = mmc_get_card(0))) {
+ print("invalid card\n");
+ return;
+ }
+
+ if (!mmc_card_mmc(card)) {
+ print("not mmc card!!!\n");
+ return;
+ }
+
+ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+ print("invalid mmc spec: 0x%x", card->csd.mmca_vsn);
+ return;
+ }
+
+ err = mmc_send_write_prot(card, wp_addr, &wp_status);
+ if (err) {
+ print("bad send_write prot failed with %d\n", err);
+ return;
+ }
+
+ print("addr: 0x%x wp_status: 0x%x\n", wp_addr, wp_status);
+}
+
+void tkcore_boot_sdrpmb_init_finish(u32 param_addr)
+{
+ int ret = 0;
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+ if (teearg == NULL)
+ return;
+
+ if (sdrpmb_info.failed || sdrpmb_info.part_id < 0)
+ return;
+
+ get_wp_status(sdrpmb_info.sdrpmb_starting_sector);
+
+ teearg->sdrpmb_partaddr = sdrpmb_info.sdrpmb_partaddr;
+ teearg->sdrpmb_partsize = sdrpmb_info.sdrpmb_partsize;
+ teearg->sdrpmb_starting_sector = sdrpmb_info.sdrpmb_starting_sector - sdrpmb_info.sdrpmb_part_start;
+ teearg->sdrpmb_nr_sectors = sdrpmb_info.sdrpmb_nr_sectors;
+
+ return;
+}
+#endif
+
+void tkcore_boot_param_prepare(u64 param_addr, u64 tee_entry,
+ u64 sec_dram_size, u64 dram_base, u64 dram_size, u32 uart_base)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+ if (teearg == NULL) {
+ return;
+ }
+
+ /* Prepare TEE boot parameters */
+ teearg->magic = TKCORE_BOOTCFG_MAGIC;
+ teearg->length = sizeof(tee_arg_t);
+ teearg->version = (u64) TEE_ARGUMENT_VERSION;
+ teearg->dRamBase = dram_base;
+ teearg->dRamSize = dram_size;
+ teearg->secDRamBase = tee_entry;
+ teearg->secDRamSize = sec_dram_size;
+ teearg->secIRamBase = TEE_SECURE_ISRAM_ADDR;
+ teearg->secIRamSize = TEE_SECURE_ISRAM_SIZE;
+
+ /* GIC parameters */
+ teearg->total_number_spi = 352;
+ /* SSI Reserve */
+ teearg->ssiq_number = 32 + 296;
+
+ teearg->flags = 0;
+
+ teearg->uart_base = uart_base;
+}
+
+void tkcore_dump_param(u32 param_addr)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+#if 0
+ DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+ DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+ DBG_MSG("%s teearg.version: 0x%x\n", MOD, teearg->version);
+ DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+ DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+ DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+ DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+ DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+ DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+ DBG_MSG("%s teearg.gic_dist_base: 0x%x\n", MOD, teearg->gic_distributor_base);
+ DBG_MSG("%s teearg.gic_cpu_base: 0x%x\n", MOD, teearg->gic_cpuinterface_base);
+ DBG_MSG("%s teearg.gic_version: 0x%x\n", MOD, teearg->gic_version);
+ DBG_MSG("%s teearg.uart_base: 0x%x\n", MOD, teearg->uart_base);
+ DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+ DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+ DBG_MSG("%s teearg.flags: %x\n", MOD, teearg->flags);
+#endif
+ if (teearg->version >= TEE_ARGUMENT_VERSION_V1_0) {
+ // DBG_MSG("%s teearg.rpmb_key_programmed : %d\n",
+ // MOD, teearg->rpmb_key_programmed);
+ }
+
+ if (teearg->version >= TEE_ARGUMENT_VERSION_V1_1) {
+ // DBG_MSG("%s teearg.nw_bootargs: 0x%x\n", MOD, teearg->nw_bootargs);
+ // DBG_MSG("%s teearg.nw_bootargs_size: 0x%x\n", MOD, teearg->nw_bootargs_size);
+ }
+
+ if (teearg->version >= TEE_ARGUMENT_VERSION_V1_2) {
+ DBG_MSG("%s teearg.sdrpmb_partaddr: 0x%x\n", MOD, teearg->sdrpmb_partaddr);
+ DBG_MSG("%s teearg.sdrpmb_partsize: 0x%x\n", MOD, teearg->sdrpmb_partsize);
+ DBG_MSG("%s teearg.sdrpmb_starting_sector: 0x%x\n", MOD, teearg->sdrpmb_starting_sector);
+ DBG_MSG("%s teearg.sdrpmb_nr_sectors: 0x%x\n", MOD, teearg->sdrpmb_nr_sectors);
+ }
+}
+
+void tkcore_boot_param_prepare_nwbootargs(u32 param_addr, u32 addr, u32 size)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+ if (teearg == NULL)
+ return;
+ //fix unalign problem with memory copy.
+ memcpy(&teearg->nw_bootargs, &addr, sizeof(addr));
+ memcpy(&teearg->nw_bootargs_size, &size, sizeof(size));
+}
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+void tkcore_boot_param_prepare_rpmbkey(u32 param_addr)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr) param_addr;
+
+ if (teearg == NULL) {
+ return ;
+ }
+
+ seclib_get_msg_auth_key(teearg->rpmb_key, RPMB_KEY_SIZE);
+ print("I'm OK!\n");
+ teearg->rpmb_key_programmed = 1;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/start.s b/src/bsp/trustzone/teeloader/mt2712/src/start.s
new file mode 100644
index 0000000..47d2284
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+ b teeloader_main
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/string.c b/src/bsp/trustzone/teeloader/mt2712/src/string.c
new file mode 100644
index 0000000..d916f3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+ const char *sc;
+
+ for (sc = s; *sc != '\0'; ++sc)
+ {
+ }
+ return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+ signed char __res;
+
+ while (1)
+ {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ }
+ return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+ signed char __res = 0;
+
+ while (count)
+ {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ count--;
+ }
+ return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+ char *xs = s;
+
+ while (count--)
+ *xs++ = c;
+ return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+ char *tmp = dest;
+ const char *s = src;
+
+ while (count--)
+ *tmp++ = *s++;
+ return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+ const unsigned char *su1, *su2;
+ int res = 0;
+
+ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+ if ((res = *su1 - *su2) != 0)
+ break;
+ return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+ char *_dst = dst;
+ const char *_src = src;
+
+ if (dst == src)
+ return dst;
+
+ if (dst < src)
+ return memcpy(dst, src, count);
+
+ _dst += count;
+ _src += count;
+ while(count--)
+ *--_dst = *--_src;
+
+ return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2712/src/uart.c b/src/bsp/trustzone/teeloader/mt2712/src/uart.c
new file mode 100644
index 0000000..e93d4dc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+ while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+ if (c == '\n')
+ writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+ writel((unsigned int)c, UART_THR(UART1_BASE));
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2712/tllink.lds b/src/bsp/trustzone/teeloader/mt2712/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+ . = %BASE_ADDR%;
+ .start ALIGN(4) : {
+ *(.text.start)
+ }
+
+ . = . + 0x01FC;
+ .text ALIGN(4) : {
+ *(.text)
+ *(.text.*)
+ }
+ .rodata ALIGN(4) : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+ .data ALIGN(4) : {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = %BASE_ADDR%-0x100000 ;
+ .bss ALIGN(16) : {
+ _bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ /* make _bss_end as 4 bytes alignment */
+ . = ALIGN(4);
+ _bss_end = .;
+ }
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+ PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+ dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+ cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+ rm ${FILE_DIR}/padding.txt
+fi