[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
new file mode 100644
index 0000000..7d5b170
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/device_apc.h
@@ -0,0 +1,427 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+#define DEVAPC0_AO_BASE (0x1000E000U)
+#define DEVAPC0_PD_BASE (0x10207000U)
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define DEVAPC0_D0_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0000))
+#define DEVAPC0_D0_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0004))
+#define DEVAPC0_D0_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0008))
+#define DEVAPC0_D0_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x000C))
+#define DEVAPC0_D0_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0010))
+#define DEVAPC0_D0_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0014))
+#define DEVAPC0_D0_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0018))
+#define DEVAPC0_D0_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x001C))
+#define DEVAPC0_D0_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))
+#define DEVAPC0_D0_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0024))
+#define DEVAPC0_D0_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0028))
+#define DEVAPC0_D0_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0030))
+#define DEVAPC0_D1_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0100))
+#define DEVAPC0_D1_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0104))
+#define DEVAPC0_D1_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0108))
+#define DEVAPC0_D1_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x010C))
+#define DEVAPC0_D1_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0110))
+#define DEVAPC0_D1_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0114))
+#define DEVAPC0_D1_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0118))
+#define DEVAPC0_D1_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x011C))
+#define DEVAPC0_D1_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))
+#define DEVAPC0_D1_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0124))
+#define DEVAPC0_D1_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0128))
+#define DEVAPC0_D1_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0130))
+#define DEVAPC0_D2_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0200))
+#define DEVAPC0_D2_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0204))
+#define DEVAPC0_D2_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0208))
+#define DEVAPC0_D2_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x020C))
+#define DEVAPC0_D2_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0210))
+#define DEVAPC0_D2_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0214))
+#define DEVAPC0_D2_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0218))
+#define DEVAPC0_D2_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x021C))
+#define DEVAPC0_D2_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))
+#define DEVAPC0_D2_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0224))
+#define DEVAPC0_D2_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0228))
+#define DEVAPC0_D2_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0230))
+#define DEVAPC0_D3_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0300))
+#define DEVAPC0_D3_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0304))
+#define DEVAPC0_D3_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0308))
+#define DEVAPC0_D3_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x030C))
+#define DEVAPC0_D3_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0310))
+#define DEVAPC0_D3_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0314))
+#define DEVAPC0_D3_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0318))
+#define DEVAPC0_D3_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x031C))
+#define DEVAPC0_D3_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))
+#define DEVAPC0_D3_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0324))
+#define DEVAPC0_D3_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0328))
+#define DEVAPC0_D3_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0330))
+#define DEVAPC0_MAS_DOM_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0400))
+#define DEVAPC0_MAS_DOM_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0404))
+#define DEVAPC0_MAS_DOM_GROUP_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0408))
+#define DEVAPC0_MAS_SEC_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0500))
+#define DEVAPC0_MAS_SEC_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0504))
+#define DEVAPC0_APC_CON ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F00))
+#define DEVAPC0_PD_APC_CON ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F00))
+#define DEVAPC_APC_CON_CTRL (0x1U)
+#define DEVAPC_APC_CON_EN (0x1U)
+#define MASTER_MSDC0 4U
+
+typedef enum {
+ NON_SECURE_TRAN = 0,
+ SECURE_TRAN,
+} E_TRANSACTION;
+
+
+///* DOMAIN_SETUP */
+#define DOMAIN_0 0U
+#define DOMAIN_1 1U
+#define DOMAIN_2 2U
+#define DOMAIN_3 3U
+#define CONN2AP (0xf << 16)//index12 DEVAPC0_MAS_DOM_1
+#define GPU (0xf << 20)//index21 DEVAPC0_MAS_DOM_2
+
+static inline unsigned int uffs(unsigned int x)
+{
+ unsigned int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+#define reg_read16(reg) __raw_readw(reg)
+#define reg_read32(reg) __raw_readl(reg)
+#define reg_write16(reg,val) __raw_writew(val,reg)
+#define reg_write32(reg,val) __raw_writel(val,reg)
+
+#define reg_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ tv &= ~(field); \
+ tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+ reg_write32(reg,tv); \
+ } while(0)
+
+#define reg_get_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+ } while(0)
+
+#define DAPC_SEC_RW_NSEC_RW 0U /* read and write for both secure and non-secure access */
+#define DAPC_SEC_RW 1U /* read and write for secure access */
+#define DAPC_NSEC_RW 2U /* read and write for non-secure access */
+#define DAPC_SEC_DENY_NSEC_DENY 3U /* Any access is prohibited */
+
+#define DAPC_NS_TRANSACTION 0U /* Emit non-secure signal sideband */
+#define DAPC_S_TRANSACTION 1U /* Emit secure signal sideband */
+
+#define MASTER_NFI 0U
+#define MASTER_PWM 2U
+#define MASTER_THERMAL_CTRL 3U
+#define MASTER_MSDC0 4U
+#define MASTER_MSDC1 5U
+#define MASTER_MSDC2 6U
+#define MASTER_MSDC3 7U
+#define MASTER_SPI0 8U
+#define MASTER_SPM 9U
+#define MASTER_DEBUG_SYSTEM 11U
+#define MASTER_AUDIO_AFE 12U
+#define MASTER_APMCU 13U
+#define MASTER_MFG_M0 19U
+#define MASTER_USB30 20U
+#define MASTER_SPI1 22U
+#define MASTER_SPI2 23U
+#define MASTER_SPI3 24U
+#define MASTER_SPI4 25U
+#define MASTER_SPI5 26U
+#define MASTER_SCP 27U
+#define MASTER_USB30_2 28U
+#define MASTER_SFLASH 29U
+#define MASTER_GMAC 30U
+#define MASTER_PCIE0 31U
+#define MASTER_PCIE1 32U
+
+#define MODULE_TRANSACTION(index, is_secure) (is_secure << (index % 32))
+#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)
+
+#define MODULE_DOMAIN(index, domain) (domain << (2 * (index % 16)))
+#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)
+
+#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(devapc_register, permission) reg_write32(devapc_register, permission)
+#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(devapc_register, permission) reg_write32(devapc_register, permission)
+
+#define INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR 0U
+#define INFRA_AO_INFRASYS_CONFIG_REGS 1U
+/* #define Reserved 2U */
+#define INFRA_AO_PERISYS_CONFIG_REGS 3U
+/* #define Reserved 4U */
+#define INFRA_AO_GPIO_CONTROLLER 5U
+#define INFRA_AO_TOP_LEVEL_SLP_MANAGER 6U
+#define INFRA_AO_TOP_LEVEL_RESET_GENERATOR 7U
+#define INFRA_AO_GPT 8U
+/* #define Reserved 9U */
+#define INFRA_AO_SEJ 10U
+#define INFRA_AO_APMCU_EINT_CONTROLLER 11U
+#define SYS_TIMER_CONTROL_REG 12U
+#define IRRX_CONTROL_REG 13U
+#define INFRA_AO_DEVICE_APC_AO 14U
+#define UART5_REG 15U
+#define INFRA_AO_KPAD_CONTROL_REG 16U
+#define TOP_RTC_REG 17U
+#define SPI4_REG 18U
+#define SPI1_REG 19U
+#define INFRA_AO_GPT2 20U
+#define DRAMC_CH0_REG 21U
+#define DRAMC_CH1_REG 22U
+#define DRAMC_CH2_REG 23U
+#define DRAMC_CH3_REG 24U
+#define INFRASYS_MCUSYS_CONFIG_REG 25U
+#define INFRASYS_CONTROL_REG 26U
+#define INFRASYS_BOOTROM_SRAM 27U
+#define INFRASYS_EMI_BUS_INTERFACE 28U
+#define INFRASYS_SYSTEM_CIRQ 29U
+#define INFRASYS_M4U_CONFIGURATION 30U
+#define INFRASYS_EFUSEC 31U
+#define INFRASYS_DEVICE_APC_MONITOR 32U
+#define BUS_DEBUG_TRAKER 33U
+#define INFRASYS_AP_MIXED_CONTROL_REG 34U
+#define INFRASYS_M4U_2_CONFIGURATION 35U
+#define ANA_MIPI_DSI3 36U
+/* #define Reserved 37U */
+#define INFRASYS_MBIST_CONTROL_REG 38U
+#define INFRASYS_EMI_MPU_CONTROL_REG 39U
+#define INFRASYS_TRNG 40U
+#define INFRASYS_GCPU 41U
+#define INFRASYS_GCPU_NS 42U
+#define INFRASYS_CQ_DMA 43U
+#define INFRASYS_GCPU_M4U 44U
+#define ANA_MIPI_DSI2 45U
+#define ANA_MIPI_DSI0 46U
+#define ANA_MIPI_DSI1 47U
+#define ANA_MIPI_CSI0 48U
+#define ANA_MIPI_CSI1 49U
+/* #define Reserved 50U */
+#define DEGBUG_CORESIGHT 51U
+#define DMA 52U
+#define AUXADC 53U
+#define UART0 54U
+#define UART1 55U
+#define UART2 56U
+#define UART3 57U
+#define PWM 58U
+#define I2C0 59U
+#define I2C1 60U
+#define I2C2 61U
+#define SPI0 62U
+#define THERM_CTRL 63U
+/* #define Reserved 64U */
+#define SPI_NOR 65U
+#define NFI 66U
+#define NFI_ECC 67U
+#define I2C3 68U
+#define I2C4 69U
+/* #define Reserved 70U */
+#define I2C5 71U
+/* #define Reserved 72U */
+#define SPI2 73U
+#define SPI3 74U
+/* #define Reserved 75U */
+/* #define Reserved 76U */
+#define UART4 77U
+/* #define Reserved 78U */
+#define GMAC 79U
+/* #define Reserved 80U */
+/* #define Reserved 81U */
+#define AUDIO 82U
+#define MSDC0 83U
+#define MSDC1 84U
+#define MSDC2 85U
+#define MSDC3 86U
+#define USB3_0 87U
+#define USB3_0SIF 88U
+#define USB3_0SIF2 89U
+#define USB3_0_2 90U
+#define USB3_0SIF_2 91U
+#define USB3_0SIF2_2 92U
+#define SCPSYS_SRAM 93U
+#define PCIe0 94U
+#define PCIe1 95U
+#define G3D_CONFIG 96U
+#define MMSYS_CONFIG 97U
+#define MDP_RDMA0 98U
+#define MDP_RDMA1 99U
+#define MDP_RSZ0 100U
+#define MDP_RSZ1 101U
+#define MDP_RSZ2 102U
+#define MDP_WDMA 103U
+#define MDP_WROT0 104U
+#define MDP_WROT1 105U
+#define MDP_TDSHP0 106U
+#define MDP_TDSHP1 107U
+/* #define Reserved 108U */
+#define DISP_OVL0 109U
+#define DISP_OVL1 110U
+#define DISP_RDMA0 111U
+#define DISP_RDMA1 112U
+#define DISP_RDMA2 113U
+#define DISP_WDMA0 114U
+#define DISP_WDMA1 115U
+#define DISP_COLOR0 116U
+#define DISP_COLOR1 117U
+#define DISP_AAL 118U
+#define DISP_GAMMA 119U
+/* #define Reserved 120U */
+#define DISP_SPLIT0 121U
+/* #define Reserved 122U */
+#define DISP_UFOE 123U
+#define DSI0 124U
+#define DSI1 125U
+#define DPI 126U
+#define DISP_PWM0 127U
+#define DISP_PWM1 128U
+#define MM_MUTEX 129U
+#define SMI_LARB0 130U
+#define SMI_COMMON 131U
+#define DISP_OD 132U
+#define DPI1 133U
+/* #define Reserved 134U */
+#define LVDS 135U
+#define SMI_LARB4 136U
+#define MDP_RDMA2 137U
+#define DISP_COLOR2 138U
+#define DISP_AAL1 139U
+#define DISP_OD1 140U
+#define DISP_OVL2 141U
+#define DISP_WDMA2 142U
+#define LVDS1 143U
+#define MDP_TDSHP2 144U
+#define SMI_LARB5 145U
+#define SMI_COMMON1 146U
+#define SMI_LARB7 147U
+#define MDP_RDMA3 148U
+#define MDP_WROT2 149U
+#define DSI2 150U
+#define DSI3 151U
+/* #define Reserved 152U */
+#define DISP_MONITOR0 153U
+#define DISP_MONITOR1 154U
+#define DISP_MONITOR2 155U
+#define DISP_MONITOR3 156U
+#define DISP_PWM2 157U
+#define IMGSYS_CONFIG 158U
+#define SMI_LARB2 159U
+#define SENINF_TOP0 160U
+#define SENINF_TOP1 161U
+#define CAMSV_TOP0 162U
+#define CAMSV_TOP1 163U
+#define CAMSV_TOP2 164U
+#define CAMSV_TOP3 165U
+#define CAMSV_TOP4 166U
+#define CAMSV_TOP5 167U
+/* #define Reserved 168U */
+/* #define Reserved 169U */
+/* #define Reserved 170U */
+/* #define Reserved 171U */
+/* #define Reserved 172U */
+/* #define Reserved 173U */
+#define BDP_DISPSYS_CONFIG 174U
+#define BDP_DISPFMT 175U
+#define BDP_VDO 176U
+#define BDP_NR 177U
+#define BDP_NR2 178U
+#define BDP_TVD 179U
+#define BDP_WR_CHANNEL_DI 180U
+#define BDP_WR_CHANNEL_VDI 181U
+#define BDP_LARB 182U
+#define BDP_LARB_RT 183U
+#define BDP_DRAM2AXI_BRIDGE 184U
+#define VDECSYS_CONFIGURATION 185U
+#define VDECSYS_SMI_LARB1 186U
+#define VDEC_FULL_TOP 187U
+#define IMGRZ 188U
+#define VDEC_MBIST 189U
+#define JPGDEC_CONFIGURATION 190U
+#define JPDEC 191U
+#define JPDGDEC1 192U
+/* #define Reserved 193U */
+#define VENC_CONFIGURATION 194U
+#define VENC_SMI_LARB3 195U
+#define VENC_SMI_LARB6 196U
+#define SMI_COMMON_2 197U
+#define VENC 198U
+/* #define Reserved 199U */
+#define SFLASH 200U
+
+extern void device_APC_dom_setup(void);
+extern void tz_dapc_sec_setting(void);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
new file mode 100644
index 0000000..926bc1f
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/hacc_export.h
@@ -0,0 +1,53 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+ unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/platform.h b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
new file mode 100644
index 0000000..51dca91
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR (0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE (0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE (0x800000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE (0x800000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0xA000000UL) /* TEE max DRAM size is 160MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/print.h b/src/bsp/trustzone/teeloader/mt2712/include/print.h
new file mode 100644
index 0000000..732dc0e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/print.h
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define REL_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/seclib.h b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
new file mode 100644
index 0000000..abb4c8e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/seclib.h
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX (0xFFFFFFFFUL) /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/string.h b/src/bsp/trustzone/teeloader/mt2712/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
new file mode 100644
index 0000000..e49da76
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/typedefs.h
@@ -0,0 +1,178 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE (0U)
+#endif
+#ifndef TRUE
+#define TRUE (1U)
+#endif
+
+#ifndef NULL
+#define NULL (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+ (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+ (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+ (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+ (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+ (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+ (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x) READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y) WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x) READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y) WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x) READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y) WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr) INREG8(addr)
+#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data) SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
+
+#define DRV_Reg16(addr) INREG16(addr)
+#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data) SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
+
+#define DRV_Reg32(addr) INREG32(addr)
+#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data) SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
+
+#define __raw_readb(REG) DRV_Reg8(REG)
+#define __raw_readw(REG) DRV_Reg16(REG)
+#define __raw_readl(REG) DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG) DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG) DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG) DRV_WriteReg32(REG,VAL)
+
+#define printf print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
new file mode 100644
index 0000000..c593c94
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_apc.h
@@ -0,0 +1,155 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2018 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_APC_H
+#define TZ_APC_H
+
+#include "typedefs.h"
+
+/*****************************************************************************
+ * Register base address definition
+ *****************************************************************************/
+
+#define SRAMROM_SEC_CTRL ((volatile unsigned int*)(0x10001804U))
+#define SRAMROM_SEC_ADDR ((volatile unsigned int*)(0x10001808U))
+
+/* APDMA */
+#define APDMA_GLOBAL_GSEC_CTRL ((volatile unsigned int*)(0x11000014U))
+#define APDMA_UART_TX0_SEC_CTRL ((volatile unsigned int*)(0x11000038U))
+#define APDMA_UART_RX0_SEC_CTRL ((volatile unsigned int*)(0x1100003CU))
+#define APDMA_UART_TX1_SEC_CTRL ((volatile unsigned int*)(0x11000040U))
+#define APDMA_UART_RX1_SEC_CTRL ((volatile unsigned int*)(0x11000044U))
+#define APDMA_UART_TX2_SEC_CTRL ((volatile unsigned int*)(0x11000048U))
+#define APDMA_UART_RX2_SEC_CTRL ((volatile unsigned int*)(0x1100004CU))
+#define APDMA_UART_TX3_SEC_CTRL ((volatile unsigned int*)(0x11000050U))
+#define APDMA_UART_RX3_SEC_CTRL ((volatile unsigned int*)(0x11000054U))
+#define APDMA_UART_TX4_SEC_CTRL ((volatile unsigned int*)(0x11000058U))
+#define APDMA_UART_RX4_SEC_CTRL ((volatile unsigned int*)(0x1100005CU))
+#define APDMA_UART_TX5_SEC_CTRL ((volatile unsigned int*)(0x11000060U))
+#define APDMA_UART_RX5_SEC_CTRL ((volatile unsigned int*)(0x11000064U))
+#define APDMA_GLOBAL_GSEC_EN 0x1
+
+/* CQDMA */
+#define CQDMA_SEC_CTRL ((volatile unsigned int*)(0x10212C58U))
+
+/* SMI BDPSYS (larb8 and larb9) */
+#define SMI_BDPSYS_LARB8_BASE ((volatile unsigned int*)(0x1501a000U))
+#define SMI_BDPSYS_LARB9_BASE ((volatile unsigned int*)(0x1501a008U))
+#define SMI_BDPSYS_DOMAIN_MASK (0xf0000)
+#define SMI_BDPSYS_AR_DOMAIN(dom) (((dom) & 0x3) << 16)
+#define SMI_BDPSYS_AW_DOMAIN(dom) (((dom) & 0x3) << 18)
+
+/*****************************************************************************
+ * Enum
+ *****************************************************************************/
+typedef enum
+{
+ TZ_APC_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_APC_SEC_RW_NSEC_DENY, /* read and write for secure access */
+ TZ_APC_SEC_DENY_NSEC_RW, /* read and write for non-secure access */
+ TZ_APC_SEC_DENY_NSEC_DENY /* Any access is prohibited */
+} tz_apc_permission;
+
+typedef enum
+{
+ TZ_APC_DOMAIN_IVI = 0, /* The domain is for in-vehicle infotainment system (normally Linux OS). */
+ TZ_APC_DOMAIN_CLUSTER = 1, /* The domain is for cluster system. */
+ TZ_APC_DOMAIN_DSP = 2, /* The domain is for Audio DSP system. */
+ TZ_APC_DOMAIN_MCU = 3, /* AP MCU will access the bus throgh the domain ID. The MCU used by any of the sub-system,
+ including IVI, cluster, and DSP will access the bus with this domain.
+ This domain can access almost all the slave devices in secure and non-secure mode and
+ hence we must apply the MMU and MPU to protect the device access and memory access in
+ the system. */
+} tz_apc_domain_partition;
+
+typedef enum
+{
+ TZ_SRAMROM_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_DENY = 1, /* read and write for secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_RO = 2, /* read and write for secure access and read only for non-secure access */
+ TZ_SRAMROM_SEC_RW_NSEC_WO = 3, /* read and write for secure access and write only for non-secure access */
+ TZ_SRAMROM_SEC_RO_NSEC_RO = 4, /* read only for both secure access and non-secure access */
+ TZ_SRAMROM_SEC_DENY_NSEC_DENY = 7 /* Any access is prohibited */
+} tz_sramrom_permission;
+
+typedef enum
+{
+ TZ_UART_APDMA_NSEC = 0, /* Read and write with non-secure sideband AXI signal. */
+ TZ_UART_APDMA_SEC = 1, /* Read and write with secure sideband AXI signal. */
+} tz_uart_apdma_permission;
+
+typedef enum
+{
+ TZ_CQDMA_NSEC = 0, /* Read and write with non-secure sideband AXI signal. */
+ TZ_CQDMA_SEC = 1, /* Read and write with secure sideband AXI signal. */
+} tz_cpdma_permission;
+
+typedef enum
+{
+ TZ_SRAMROM_REGION_0 = 0, /* Region 0 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+ TZ_SRAMROM_REGION_1 = 1 /* Region 1 set by SRAMROM_SEC_ADD. Refer to TZ_SRAMROM_SET_REGION_SIZE for more info */
+} tz_sramrom_region;
+
+/*****************************************************************************
+ * Functions
+ *****************************************************************************/
+
+#define reg_read16(reg) __raw_readw(reg)
+#define reg_read32(reg) __raw_readl(reg)
+#define reg_write16(reg,val) __raw_writew(val,reg)
+#define reg_write32(reg,val) __raw_writel(val,reg)
+
+static inline u32 tz_sramrom_set_bitwise_domain_permision(tz_sramrom_region region,
+ tz_apc_domain_partition domain, tz_sramrom_permission permission)
+{
+ return (permission & 0x7) << ((domain * 3) + (region == TZ_SRAMROM_REGION_1 ? 16: 0));
+}
+
+/* Enabling this bit to protect all multimedia secure related registers, including SMI,
+ accessing in non-secure world. */
+#define TZ_SRAMROM_ENABLE_MULTIMEDIA_SECURE_ACCESS (u32)(0x1 << 30)
+
+/* Enabling this bit to protect sramrom region 1 by region 1's security setting */
+#define TZ_SRAMROM_ENABLE_REGION_1_PROTECTION (u32)(0x1 << 28)
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0). */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size) (reg_write32(SRAMROM_SEC_ADDR, ((size & 0xff) << 10)))
+
+extern void tz_apc_common_init();
+extern void tz_apc_common_postinit();
+
+#endif /* TZ_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET (0x40000000UL)
+#define EMI_MPU_ALIGNMENT (0x10000UL)
+#define PERIAXI_BUS_CTL3 (0x10003208UL)
+#define PERISYS_4G_SUPPORT (0x1 << 11)
+
+
+typedef enum
+{
+ TZ_MPU_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_MPU_SEC_RW_NSEC_DENY = 1, /* read and write for secure access */
+ TZ_MPU_SEC_RW_NSEC_RO = 2, /* read and write for secure access and read only for non-secure access */
+ TZ_MPU_SEC_RW_NSEC_WO = 3, /* read and write for secure access and write only for non-secure access */
+ TZ_MPU_SEC_RO_NSEC_RO = 4, /* read only for both secure access and non-secure access */
+ TZ_MPU_SEC_DENY_NSEC_DENY = 5, /* Any access is prohibited */
+ TZ_MPU_SEC_RO_NSEC_RW = 6 /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID (0)
+#define ATF_MPU_REGION_ID (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE (0x1020E000U)
+
+#define EMI_MPU_SA0 ((P_U32)(EMI_MPU_BASE+0x100)) /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1 ((P_U32)(EMI_MPU_BASE+0x104)) /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2 ((P_U32)(EMI_MPU_BASE+0x108)) /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3 ((P_U32)(EMI_MPU_BASE+0x10C)) /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4 ((P_U32)(EMI_MPU_BASE+0x110)) /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5 ((P_U32)(EMI_MPU_BASE+0x114)) /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6 ((P_U32)(EMI_MPU_BASE+0x118)) /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7 ((P_U32)(EMI_MPU_BASE+0x11C)) /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0 ((P_U32)(EMI_MPU_BASE+0x200)) /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1 ((P_U32)(EMI_MPU_BASE+0x204)) /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2 ((P_U32)(EMI_MPU_BASE+0x208)) /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3 ((P_U32)(EMI_MPU_BASE+0x20C)) /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4 ((P_U32)(EMI_MPU_BASE+0x210)) /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5 ((P_U32)(EMI_MPU_BASE+0x214)) /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6 ((P_U32)(EMI_MPU_BASE+0x218)) /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7 ((P_U32)(EMI_MPU_BASE+0x21C)) /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0 ((P_U32)(EMI_MPU_BASE+0x300)) /* EMI MPU APC 0 */
+#define EMI_MPU_APC1 ((P_U32)(EMI_MPU_BASE+0x304)) /* EMI MPU APC 1 */
+#define EMI_MPU_APC2 ((P_U32)(EMI_MPU_BASE+0x308)) /* EMI MPU APC 2 */
+#define EMI_MPU_APC3 ((P_U32)(EMI_MPU_BASE+0x30C)) /* EMI MPU APC 3 */
+#define EMI_MPU_APC4 ((P_U32)(EMI_MPU_BASE+0x310)) /* EMI MPU APC 4 */
+#define EMI_MPU_APC5 ((P_U32)(EMI_MPU_BASE+0x314)) /* EMI MPU APC 5 */
+#define EMI_MPU_APC6 ((P_U32)(EMI_MPU_BASE+0x318)) /* EMI MPU APC 6 */
+#define EMI_MPU_APC7 ((P_U32)(EMI_MPU_BASE+0x31C)) /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0 ((P_U32)(EMI_MPU_BASE+0x900)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1 ((P_U32)(EMI_MPU_BASE+0x904)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2 ((P_U32)(EMI_MPU_BASE+0x908)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3 ((P_U32)(EMI_MPU_BASE+0x90C)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4 ((P_U32)(EMI_MPU_BASE+0x910)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5 ((P_U32)(EMI_MPU_BASE+0x914)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6 ((P_U32)(EMI_MPU_BASE+0x918)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7 ((P_U32)(EMI_MPU_BASE+0x91C)) /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
new file mode 100644
index 0000000..6778589
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_init.h
@@ -0,0 +1,83 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+
+#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+
+/* bootarg for ATF */
+typedef struct {
+ u64 bootarg_loc;
+ u64 bootarg_size;
+ u64 bl33_start_addr;
+ u64 tee_info_addr;
+ u64 boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+ unsigned int atf_magic;
+ unsigned int tee_support;
+ unsigned int tee_boot_arg_addr;
+ unsigned int tee_entry;
+ unsigned int hwuid[4]; // HW Unique id for t-base used
+ unsigned int HRID[2]; // HW random id for t-base used
+ unsigned int atf_log_port;
+ unsigned int atf_log_baudrate;
+ unsigned int atf_log_buf_start;
+ unsigned int atf_log_buf_size;
+ unsigned int atf_aee_debug_buf_start;
+ unsigned int atf_aee_debug_buf_size;
+ unsigned int devinfo[DEVINFO_SIZE];
+ unsigned int atf_irq_num;
+ unsigned int msg_auth_key[8]; /* size of message auth key is 256 bits */
+#if CFG_TEE_SUPPORT
+ unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
new file mode 100644
index 0000000..c330423
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_mem.h
@@ -0,0 +1,102 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS (0x00100000UL)
+#define SRAM_START_ADDR (0x00102140UL)
+#define VECTOR_START (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+ short next, previous;
+} tz_memory_t;
+
+#define FREE ((short)(0x0001U))
+#define IS_FREE(x) ((x)->next & FREE)
+#define CLEAR_FREE(x) ((x)->next &= ~FREE)
+#define SET_FREE(x) ((x)->next |= FREE)
+#define FROM_ADDR(x) ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x) ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE (0x200000UL) //2MB by default
+
+#define BL31 (0x44e01000UL)
+#define BL31_SIZE (0x40000UL) //change to 256KB (192KB by default)
+#define BL33 (0x73500000UL)
+
+#define ATF_BOOT_ARG_ADDR (0x40000000UL)
+#define ATF_INIT_ARG_ADDR (0x40000100UL)
+#define TEE_BOOT_ARG_ADDR (0x44e00100UL)
+
+#define TEE_PARAMETER_BASE (TEE_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+ unsigned int magic; // Magic number
+ unsigned int version; // version
+ unsigned int svp_mem_start; // MM sec mem pool start addr.
+ unsigned int svp_mem_end; // MM sec mem pool end addr.
+ unsigned int tplay_table_start; // tplay handle-to-physical table start
+ unsigned int tplay_table_size; // tplay handle-to-physical table size
+ unsigned int tplay_mem_start; // tplay physcial memory start address for crypto operation
+ unsigned int tplay_mem_size; // tplay phsycial memory size for crypto operation
+ unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+ unsigned int rpmb_size; /* size of rpmb partition */
+ unsigned int msg_auth_key[8]; /* size of message auth key is 32bytes(256 bits) */
+ unsigned int emmc_rel_wr_sec_c; // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+ u32 magic; // magic value from information
+ u32 length; // size of struct in bytes.
+ u64 version; // Version of structure
+ u64 dRamBase; // NonSecure DRAM start address
+ u64 dRamSize; // NonSecure DRAM size
+ u64 secDRamBase; // Secure DRAM start address
+ u64 secDRamSize; // Secure DRAM size
+ u64 secIRamBase; // Secure IRAM base
+ u64 secIRamSize; // Secure IRam size
+ u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+ u32 RFU1;
+ u32 MSMPteCount; // Number of MMU entries for MSM
+ u64 MSMBase; // MMU entries for MSM
+ u64 gic_distributor_base;
+ u64 gic_cpuinterface_base;
+ u32 gic_version;
+ u32 RFU2;
+ u64 flags;
+ u32 total_number_spi;
+ u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
new file mode 100644
index 0000000..57efd71
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/tz_tkcore.h
@@ -0,0 +1,80 @@
+#ifndef TZ_TKCORE_H
+#define TZ_TKCORE_H
+
+#include "typedefs.h"
+
+#define TKCORE_BOOTCFG_MAGIC (0x54534958)
+
+#define TEE_ARGUMENT_VERSION_LEGACY (0x00010000U)
+#define TEE_ARGUMENT_VERSION_V1_0 (0x00010001U)
+#define TEE_ARGUMENT_VERSION_V1_1 (0x00010002U)
+#define TEE_ARGUMENT_VERSION_V1_2 (0x00010003U)
+
+#define TEE_ARGUMENT_VERSION TEE_ARGUMENT_VERSION_V1_2
+
+#define TKCORE_SHM_SIZE_LIMIT (0x400000U)
+
+#define RPMB_KEY_SIZE 32
+
+#define SDRPMB_FAILURE_MAGIC (0xCDCDCDCDU)
+/* effective data size */
+#define SDRPMB_DATA_SIZE (1U << 20)
+/* size of two write protected regions */
+#define SDRPMB_REGION_SIZE (16U << 20)
+/* granu of sdrpmb region */
+#define SDRPMB_REGION_ALIGNMENT (8U << 20)
+
+typedef struct {
+ u32 magic; // magic value from information
+ u32 length; // size of struct in bytes.
+ u64 version; // Version of structure
+ u64 dRamBase; // NonSecure DRAM start address
+ u64 dRamSize; // NonSecure DRAM size
+ u64 secDRamBase; // Secure DRAM start address
+ u64 secDRamSize; // Secure DRAM size
+ u64 secIRamBase; // Secure IRAM base
+ u64 secIRamSize; // Secure IRam size
+ u64 gic_distributor_base;
+ u64 gic_cpuinterface_base;
+ u32 gic_version;
+ u32 uart_base;
+ u32 total_number_spi;
+ u32 ssiq_number;
+ u64 flags;
+ u8 rpmb_key[RPMB_KEY_SIZE];
+
+ /* for TEE_ARGUMENT_VERSION_1 */
+ u8 rpmb_key_programmed;
+
+ /* for TEE_ARGUMENT_VERSION_2 (mt6580 specific) */
+ u32 nw_bootargs;
+ u32 nw_bootargs_size;
+
+ /* for TEE_ARGUMENT_VERSION_3 */
+ u32 sdrpmb_partaddr;
+ u32 sdrpmb_partsize;
+ u32 sdrpmb_starting_sector;
+ u32 sdrpmb_nr_sectors;
+
+ u8 resv[7];
+} __attribute__((packed)) tee_arg_t, *tee_arg_t_ptr;
+
+void tkcore_boot_param_prepare(u64 param_addr, u64 tee_entry,
+ u64 sec_dram_size, u64 dram_base, u64 dram_size, u32 uart_base);
+
+#if CFG_TRUSTKERNEL_TEE_SDRPMB_SUPPORT
+void tkcore_boot_param_prepare_sdrpmb_region(part_t *part);
+
+void tkcore_boot_param_prepare_sdrpmb_data(mblock_info_t *mblock, blkdev_t *bootdev);
+
+void tkcore_boot_sdrpmb_init_finish(u32 param_addr);
+#endif
+
+void tkcore_boot_param_prepare_rpmbkey(u32 param_addr);
+
+void tkcore_boot_param_prepare_nwbootargs(u32 param_addr,
+ u32 addr, u32 size);
+
+void tkcore_dump_param(u32 param_addr);
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt2712/include/uart.h b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
new file mode 100644
index 0000000..9db4093
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2712/include/uart.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+typedef unsigned int uint32_t;
+typedef unsigned long uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart) (uart)
+#define UART_LSR(uart) (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE (1U << 5U)
+#define UART_THR(uart) (UART_BASE(uart) + 0x0U) /* Write only */
+
+#define IO_PHYS (0x10000000UL)
+#define UART1_BASE (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+