[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/trustzone/teeloader/mt2731/Makefile b/src/bsp/trustzone/teeloader/mt2731/Makefile
new file mode 100644
index 0000000..7ae84be
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/Makefile
@@ -0,0 +1,71 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+CUST_TEE := ./custom/$(TZ_PROJECT)/cust_tee.mak
+CUST_TEE_EXIST := $(if $(wildcard $(CUST_TEE)),TRUE,FALSE)
+
+include ./default.mak
+ifeq ("$(CUST_TEE_EXIST)","TRUE")
+include ./custom/$(TZ_PROJECT)/cust_tee.mak
+endif
+include ./feature.mak
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuilt
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+ $(DIR_SRC)/drivers/device_apc.c \
+ $(DIR_SRC)/security/tz_init.c \
+ $(DIR_SRC)/security/tz_emi_mpu.c \
+ $(DIR_SRC)/security/tz_sec_cfg.c \
+ $(DIR_SRC)/security/seclib.c
+
+ifeq ($(CFG_TRUSTONIC_TEE_SUPPORT),1)
+CSRCS += \
+ $(DIR_SRC)/security/tz_tbase.c
+endif
+
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+CFLAGS += -fno-builtin -fno-stack-protector ${C_OPTION}
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+all: $(OBJS)
+ @if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+ mkdir -p `dirname $(BIN_TARGET).elf`; \
+ fi
+ sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+ $(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+ -echo "teeloader binary created"
+ $(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+ ./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(COBJS): $(CSRCS)
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -I$(DIR_INC) $(CFLAGS) -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(AOBJS): $(ASRCS)
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -c $(filter %$(patsubst %.o,%.s,$(notdir $@)),$(ASRCS)) -o $@
+
+.PHONY: clean
+clean:
+ -@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak
new file mode 100644
index 0000000..3818332
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/auto2731m1v1-ivi_agl/cust_tee.mak
@@ -0,0 +1,7 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak
new file mode 100644
index 0000000..36e0ddd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-optee/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_OPTEE_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x900000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak
new file mode 100644
index 0000000..a7a488a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731-common-tbase/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0xA00000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp1/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak
new file mode 100644
index 0000000..2a01648
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/custom/mt2731evb-ivt-vp2/cust_tee.mak
@@ -0,0 +1,8 @@
+###################################################################
+# Include Project Feature
+###################################################################
+
+CFG_TEE_SUPPORT := 1
+CFG_TRUSTONIC_TEE_SUPPORT := 1
+CFG_TEE_SECURE_MEM_PROTECTED := 1
+CFG_TEE_SECMEM_SIZE = 0x700000
diff --git a/src/bsp/trustzone/teeloader/mt2731/default.mak b/src/bsp/trustzone/teeloader/mt2731/default.mak
new file mode 100644
index 0000000..1b0035b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/default.mak
@@ -0,0 +1,14 @@
+###################################################################
+# Default Project Feautre
+###################################################################
+MACH_TYPE := MT2731
+CFG_ATF_LOG_SUPPORT := 0
+CFG_TEE_SUPPORT := 0
+CFG_TRUSTONIC_TEE_SUPPORT := 0
+CFG_TEE_SECURE_MEM_PROTECTED := 0
+CFG_TZ_SRAMROM_SUPPORT := 1
+CFG_TZ_UART_APDMA_SUPPORT := 1
+CFG_DEVAPC_SET_PROTECT := 1
+
+CFG_ATF_LOG_BUFFER_ADDR := 0x4FFC0000
+CFG_TEE_SECMEM_SIZE = 0x3000000
diff --git a/src/bsp/trustzone/teeloader/mt2731/feature.mak b/src/bsp/trustzone/teeloader/mt2731/feature.mak
new file mode 100644
index 0000000..3ba5fe6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/feature.mak
@@ -0,0 +1,58 @@
+
+ifdef MACH_TYPE
+C_OPTION += -DMACH_TYPE_$(shell echo $(MACH_TYPE) | tr '[a-z]' '[A-Z]')
+endif
+
+ifdef BASE_ADDR
+C_OPTION += -DBASE_ADDR=${BASE_ADDR}
+endif
+
+ifdef CFG_ATF_LOG_SUPPORT
+C_OPTION += -DCFG_ATF_LOG_SUPPORT=${CFG_ATF_LOG_SUPPORT}
+export CFG_ATF_LOG_SUPPORT
+endif
+
+ifdef CFG_ATF_LOG_BUFFER_ADDR
+C_OPTION += -DCFG_ATF_LOG_BUFFER_ADDR=${CFG_ATF_LOG_BUFFER_ADDR}
+export CFG_ATF_LOG_BUFFER_ADDR
+endif
+
+ifdef TRUSTEDOS_ENTRYPOINT
+C_OPTION += -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT}
+export TRUSTEDOS_ENTRYPOINT
+endif
+
+ifdef CFG_TEE_SUPPORT
+C_OPTION += -DCFG_TEE_SUPPORT=${CFG_TEE_SUPPORT}
+export CFG_TEE_SUPPORT
+endif
+
+ifdef CFG_TRUSTONIC_TEE_SUPPORT
+C_OPTION += -DCFG_TRUSTONIC_TEE_SUPPORT=${CFG_TRUSTONIC_TEE_SUPPORT}
+export CFG_TRUSTONIC_TEE_SUPPORT
+endif
+
+ifdef CFG_TEE_SECURE_MEM_PROTECTED
+C_OPTION += -DCFG_TEE_SECURE_MEM_PROTECTED=${CFG_TEE_SECURE_MEM_PROTECTED}
+export CFG_TEE_SECURE_MEM_PROTECTED
+endif
+
+ifdef CFG_TEE_SECMEM_SIZE
+C_OPTION += -DCFG_TEE_SECMEM_SIZE=${CFG_TEE_SECMEM_SIZE}
+export CFG_TEE_SECMEM_SIZE
+endif
+
+ifdef CFG_TZ_SRAMROM_SUPPORT
+C_OPTION += -DCFG_TZ_SRAMROM_SUPPORT=${CFG_TZ_SRAMROM_SUPPORT}
+export CFG_TZ_SRAMROM_SUPPORT
+endif
+
+ifdef CFG_DEVAPC_SET_PROTECT
+C_OPTION += -DCFG_DEVAPC_SET_PROTECT=${CFG_DEVAPC_SET_PROTECT}
+export CFG_DEVAPC_SET_PROTECT
+endif
+
+ifdef CFG_TZ_UART_APDMA_SUPPORT
+C_OPTION += -DCFG_TZ_UART_APDMA_SUPPORT=${CFG_TZ_UART_APDMA_SUPPORT}
+export CFG_TZ_UART_APDMA_SUPPORT
+endif
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h b/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h
new file mode 100644
index 0000000..263d492
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/device_apc.h
@@ -0,0 +1,409 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+/* #define DEVAPC_UT */
+
+/******************************************************************************
+ * SIP CMD DEFINITION
+ ******************************************************************************/
+#define SIP_APC_MODULE_SET 0x1
+#define SIP_APC_MM2ND_SET 0x2
+#define SIP_APC_MASTER_SET 0x3
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void tz_apc_common_init(void);
+void tz_apc_common_postinit(void);
+void devapc_init(void);
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr);
+unsigned int devapc_perm_get(int, int, int);
+uint64_t sip_tee_apc_request(uint32_t cmd, uint32_t x1, uint32_t x2, uint32_t x3);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum E_TRANSACTION {
+ NON_SECURE_TRANSACTION = 0,
+ SECURE_TRANSACTION,
+ E_TRANSACTION_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+enum APC_ATTR {
+ E_NO_PROTECTION = 0,
+ E_SEC_RW_ONLY,
+ E_SEC_RW_NS_R,
+ E_FORBIDDEN,
+ E_APC_ATTR_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+enum E_MASK_DOM {
+ E_DOMAIN_0 = 0,
+ E_DOMAIN_1,
+ E_DOMAIN_2,
+ E_DOMAIN_3,
+ E_DOMAIN_4,
+ E_DOMAIN_5,
+ E_DOMAIN_6,
+ E_DOMAIN_7,
+ E_DOMAIN_8,
+ E_DOMAIN_9,
+ E_DOMAIN_10,
+ E_DOMAIN_11,
+ E_DOMAIN_12,
+ E_DOMAIN_13,
+ E_DOMAIN_14,
+ E_DOMAIN_15,
+ E_MASK_DOM_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+enum DAPC_MASTER_TYPE {
+ E_DAPC_MASTER = 0,
+ E_DAPC_INFRACFG_AO_MASTER,
+ E_DAPC_MASTER_TYPE_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+enum DAPC_SLAVE_TYPE {
+ E_DAPC_INFRA_SLAVE = 0,
+ E_DAPC_SRAMROM_SLAVE,
+ E_DAPC_MD_SLAVE,
+ E_DAPC_OTHERS_SLAVE,
+ E_DAPC_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+enum DAPC_PD_SLAVE_TYPE {
+ E_DAPC_PD_INFRA_MM_MD_SLAVE = 0,
+ E_DAPC_PD_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
+};
+
+struct INFRA_PERI_DEVICE_INFO {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d9_permission;
+ unsigned char d11_permission;
+};
+
+#define DAPC_INFRA_ATTR(DEV_NAME, PERM_ATTR1, PERM_ATTR2, PERM_ATTR3, PERM_ATTR4) \
+{(unsigned char)PERM_ATTR1, (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, (unsigned char)PERM_ATTR4}
+
+struct MD_DEVICE_INFO {
+ unsigned char d0_permission;
+};
+
+#define DAPC_MD_ATTR(DEV_NAME, PERM_ATTR1) {(unsigned char)PERM_ATTR1}
+
+enum DEVAPC_ERR_STATUS {
+ DEVAPC_OK = 0x0,
+
+ DEVAPC_ERR_GENERIC = 0x1000,
+ DEVAPC_ERR_INVALID_CMD = 0x1001,
+ DEVAPC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+ DEVAPC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+ DEVAPC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+ DEVAPC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+ DEVAPC_ERR_OUT_OF_BOUNDARY = 0x1006,
+};
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+
+#define devapc_writel(VAL, REG) __raw_writel(VAL, REG)
+#define devapc_readl(REG) __raw_readl(REG)
+
+static void tz_set_field(volatile u32 *reg, u32 field, u32 val)
+{
+ u32 tv = (u32)*reg;
+ tv &= ~(field);
+ tv |= val;
+ *reg = tv;
+}
+
+#define reg_set_field(r, f, v) tz_set_field((volatile u32 *)r, f, v)
+
+/******************************************************************************
+ *
+ * REGISTER ADDRESS DEFINITION
+ *
+ ******************************************************************************/
+#define DEVAPC_AO_INFRA_BASE 0x1001C000
+#define DEVAPC_PD_INFRA_BASE 0x10207000
+
+#define SRAMROM_BASE 0x10214000
+#define INFRACFG_AO_BASE 0x10001000
+#define SECURITY_AO_BASE 0x1001A000
+
+/* #define BLOCKED_REG_BASE 0x10400000 */
+
+/*******************************************************************************************/
+/* Device APC AO */
+#define DEVAPC_SYS0_D0_APC_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0000))
+#define DEVAPC_SYS1_D0_APC_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x1000))
+#define DEVAPC_SYS2_D0_APC_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x2000))
+
+#define DEVAPC_INFRA_MAS_DOM_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0900))
+#define DEVAPC_INFRA_MAS_DOM_1 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0904))
+#define DEVAPC_INFRA_MAS_DOM_2 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0908))
+#define DEVAPC_INFRA_MAS_DOM_3 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x090C))
+#define DEVAPC_INFRA_MAS_DOM_4 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0910))
+
+#define DEVAPC_INFRA_MAS_SEC_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0A00))
+
+#define DEVAPC_INFRA_APC_CON ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0F00))
+
+#define DEVAPC_SRAMROM_DOM_REMAP_0_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0800))
+#define DEVAPC_SRAMROM_DOM_REMAP_0_1 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0804))
+#define DEVAPC_SRAMROM_DOM_REMAP_1_0 ((volatile unsigned int *)(DEVAPC_AO_INFRA_BASE+0x0810))
+
+/* MD is combined into DEVAPC_AO SYS2 */
+
+/*******************************************************************************************/
+/* Device APC PD */
+#define DEVAPC_PD_INFRA_VIO_MASK(index) \
+ ((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_STA(index) \
+ ((uintptr_t)(DEVAPC_PD_INFRA_BASE + 0x400 + 0x4 * index))
+
+#define DEVAPC_PD_INFRA_VIO_DBG0 ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0900))
+#define DEVAPC_PD_INFRA_VIO_DBG1 ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0904))
+#define DEVAPC_PD_INFRA_VIO_DBG2 ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0908))
+
+#define DEVAPC_PD_INFRA_APC_CON ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F00))
+
+#define DEVAPC_PD_INFRA_VIO_SHIFT_STA ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F10))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_SEL ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F14))
+#define DEVAPC_PD_INFRA_VIO_SHIFT_CON ((volatile unsigned int *)(DEVAPC_PD_INFRA_BASE+0x0F20))
+
+/*******************************************************************************************/
+
+#define INFRA_AO_SEC_CON ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F80))
+
+/* INFRACFG AO */
+#define INFRA_AO_SEC_CG_CON0 ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F84))
+#define INFRA_AO_SEC_CG_CON1 ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F88))
+#define INFRA_AO_SEC_CG_CON2 ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0F9C))
+#define INFRA_AO_SEC_CG_CON3 ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0FA4))
+
+#define INFRACFG_AO_DEVAPC_CON ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0710))
+#define INFRACFG_AO_DEVAPC_MAS_DOM ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0714))
+#define INFRACFG_AO_DEVAPC_MAS_SEC ((volatile unsigned int *)(INFRACFG_AO_BASE+0x0718))
+
+/* PMS(MD devapc) */
+/* #define AP2MD1_PMS_CTRL_EN ((unsigned int *)0x100018AC) */
+/* #define AP2MD1_PMS_CTRL_EN_LOCK ((unsigned int *)0x100018A8) */
+
+/*******************************************************************************************/
+
+#define SRAMROM_SEC_VIO_STA ((volatile unsigned int *)(SRAMROM_BASE+0x010))
+#define SRAMROM_SEC_VIO_ADDR ((volatile unsigned int *)(SRAMROM_BASE+0x014))
+#define SRAMROM_SEC_VIO_CLR ((volatile unsigned int *)(SRAMROM_BASE+0x018))
+
+#define SRAMROM_ROM_SEC_VIO_STA ((volatile unsigned int *)(SRAMROM_BASE+0x110))
+#define SRAMROM_ROM_SEC_VIO_ADDR ((volatile unsigned int *)(SRAMROM_BASE+0x114))
+#define SRAMROM_ROM_SEC_VIO_CLR ((volatile unsigned int *)(SRAMROM_BASE+0x118))
+
+
+#define SRAMROM_SEC_CTRL ((volatile unsigned int *)(SECURITY_AO_BASE+0x010))
+#define SRAMROM_SEC_CTRL2 ((volatile unsigned int *)(SECURITY_AO_BASE+0x018))
+#define SRAMROM_SEC_CTRL5 ((volatile unsigned int *)(SECURITY_AO_BASE+0x024))
+#define SRAMROM_SEC_CTRL6 ((volatile unsigned int *)(SECURITY_AO_BASE+0x028))
+#define SRAMROM_SEC_ADDR ((volatile unsigned int *)(SECURITY_AO_BASE+0x050))
+#define SRAMROM_SEC_ADDR1 ((volatile unsigned int *)(SECURITY_AO_BASE+0x054))
+#define SRAMROM_SEC_ADDR2 ((volatile unsigned int *)(SECURITY_AO_BASE+0x058))
+
+#define SRAMROM_SEC_ADDR_SEC0_SEC_EN (28)
+#define SRAMROM_SEC_ADDR_SEC1_SEC_EN (29)
+#define SRAMROM_SEC_ADDR_SEC2_SEC_EN (30)
+#define SRAMROM_SEC_ADDR_SEC3_SEC_EN (31)
+
+/* SEC means region (0~3) */
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT (0)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT (3)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT (6)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT (9)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT (16)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT (19)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT (22)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT (25)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT (0)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT (3)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT (6)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT (9)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT (16)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT (19)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT (22)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT (25)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT (0)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT (3)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT (6)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT (9)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT (16)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT (19)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT (22)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT (25)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT (0)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT (3)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT (6)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT (9)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT (16)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT (19)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT (22)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT (25)
+
+
+#define SRAMROM_SEC_CTRL_SEC0_DOM0_MASK (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM1_MASK (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM2_MASK (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC0_DOM3_MASK (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM0_MASK (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM1_MASK (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM2_MASK (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL_SEC1_DOM3_MASK (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT)
+
+#define SRAMROM_SEC_CTRL5_SEC2_DOM0_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM1_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM2_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC2_DOM3_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM0_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM1_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM2_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT)
+#define SRAMROM_SEC_CTRL5_SEC3_DOM3_MASK (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT)
+
+#define SRAMROM_SEC_CTRL6_SEC2_DOM4_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM5_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM6_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC2_DOM7_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM4_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM5_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM6_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT)
+#define SRAMROM_SEC_CTRL6_SEC3_DOM7_MASK (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT)
+
+#define PERMIT_S_RW_NS_RW (0x0)
+#define PERMIT_S_RW_NS_BLOCK (0x1)
+#define PERMIT_S_RW_NS_RO (0x2)
+#define PERMIT_S_RW_NS_WO (0x3)
+#define PERMIT_S_RO_NS_RO (0x4)
+#define PERMIT_S_BLOCK_NS_BLOCK (0x7)
+
+
+/* Set the region 0 size of the on-chip SRAM and the region 1 size will be (192KB - size_of_region_0) */
+#define TZ_SRAMROM_SET_REGION_0_SIZE_KB(size) (devapc_writel(((size & 0xff) << 10), SRAMROM_SEC_ADDR))
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+/* If you config register INFRA_AO_SEC_CON(address 0x10000F80) bit[4] = 1,
+ * the domain comes from device_apc. By default this register is 0,
+ * the domain comes form MD1
+ */
+#define FORCE_MD1_SIGNAL_FROM_DAPC ((0x1) << 4)
+
+/* PROTECT BIT FOR INFRACFG AO */
+#define SEJ_CG_PROTECT_BIT ((0x1) << 5)
+#define TRNG_CG_PROTECT_BIT ((0x1) << 9)
+#define DEVAPC_CG_PROTECT_BIT ((0x1) << 20)
+
+#define SRAM_SEC_VIO_BIT (0x1)
+#define ROM_SEC_VIO_BIT (0x1)
+
+/*******************************************************************************************/
+/* Master domain/secure bit definition */
+#define MASTER_SPM_DOM_INDEX (18)
+#define MASTER_SPM_SEC_INDEX (19)
+#define MASTER_INFRA_MAX_INDEX (19)
+
+/* Below master should be set in INFRACFG_AO */
+#define MASTER_INFRACFG_AO_MAX_INDEX 5
+#define MASTER_APMCU_INDEX 0
+#define MASTER_MD_INDEX 1
+#define MASTER_HSM_INDEX 2
+#define MASTER_USB_INDEX 3
+#define MASTER_SSUSB_INDEX 4
+#define MASTER_MSDC0_INDEX 5
+
+/*******************************************************************************************/
+/* Master domain remap */
+#define MASTER_DOM_RMP_INIT (0xFFFFFFFF)
+#define SRAMROM_RMP_AP (0x7 << 0) // Infra domain 0
+
+#define MD_RMP_AP (0x3 << 0) // Infra domain 0
+
+/*******************************************************************************************/
+#define MOD_NO_IN_1_DEVAPC 16
+#define MAS_DOM_NO_IN_1_DEVAPC 4
+
+/* infra/sramrom/MD support maximum domain num */
+#define DEVAPC_INFRA_DOM_MAX 16
+#define DEVAPC_SRAMROM_DOM_MAX 8
+#define DEVAPC_MD_DOM_MAX 4
+
+/* infra/sramrom/MD APC number per domain */
+#define DEVAPC_INFRA_APC_NUM 10
+#define DEVAPC_SRAMROM_APC_NUM 1
+#define DEVAPC_MD_APC_NUM 3
+
+/* infra/sramrom/MD support maximum ctrl index */
+#define SLAVE_INFRA_MAX_INDEX 146
+#define SLAVE_SRAMROM_MAX_INDEX 0
+#define SLAVE_MD_MAX_INDEX 35
+
+#define VIO_MASK_STA_NUM 13
+#define SRAMROM_VIO_INDEX 355
+#define DEVAPC_CTRL_SRAMROM_INDEX 0
+/* devapc can only handle vio index 0 ~ sramrom */
+#define VIOLATION_MAX_INDEX SRAMROM_VIO_INDEX
+#define VIOLATION_TRIGGERED 1
+
+#endif /* DEVICE_APC_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h b/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h
new file mode 100644
index 0000000..fc3e2d6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/hacc_export.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef HACC_EXPORT_H
+#define HACC_EXPORT_H
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+extern int seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+
+/* @function: seclib_get_data_key
+ * @in: input buffer
+ * @size: divisible by 16
+ * @out: output buffer, could re-use input buffer
+ * @user: crypto parameter, should be 1 or 2
+ */
+extern int seclib_get_data_key(unsigned char *in, unsigned int size,
+ unsigned char *out, unsigned short user);
+#endif /* HACC_EXPORT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/platform.h b/src/bsp/trustzone/teeloader/mt2731/include/platform.h
new file mode 100644
index 0000000..4f9c524
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/platform.h
@@ -0,0 +1,60 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#define CFG_DRAM_ADDR (0x40000000UL)
+#define CFG_PLATFORM_DRAM_SIZE (0x40000000UL)
+
+#if CFG_TEE_SUPPORT
+#ifdef CFG_TEE_TRUSTED_APP_HEAP_SIZE
+#define CFG_TEE_CORE_SIZE (0x500000UL + CFG_TEE_TRUSTED_APP_HEAP_SIZE)
+#else
+#define CFG_TEE_CORE_SIZE (0x500000UL)
+#endif
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#define CFG_MIN_TEE_DRAM_SIZE (0x600000UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0xE00000UL) /* TEE max DRAM size is 14MB */
+#else
+#define CFG_MIN_TEE_DRAM_SIZE (0UL)
+#define CFG_MAX_TEE_DRAM_SIZE (0UL) /* TEE max DRAM size is 0 if TEE is not enabled */
+#endif
+#endif
+
+#endif /* PLATFORM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/print.h b/src/bsp/trustzone/teeloader/mt2731/include/print.h
new file mode 100644
index 0000000..176ca38
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+extern void print(char *fmt, ...);
+
+#endif /* PRINT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/seclib.h b/src/bsp/trustzone/teeloader/mt2731/include/seclib.h
new file mode 100644
index 0000000..fab3935
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/seclib.h
@@ -0,0 +1,52 @@
+/* Copyright Statement:
+*
+* This software/firmware and related documentation ("MediaTek Software") are
+* protected under relevant copyright laws. The information contained herein
+* is confidential and proprietary to MediaTek Inc. and/or its licensors.
+* Without the prior written permission of MediaTek inc. and/or its licensors,
+* any reproduction, modification, use or disclosure of MediaTek Software,
+* and information contained herein, in whole or in part, shall be strictly prohibited.
+*
+* MediaTek Inc. (C) 2017. All rights reserved.
+*
+* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* The following software/firmware and/or related documentation ("MediaTek Software")
+* have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
+* applicable license agreements with MediaTek Inc.
+*/
+
+#ifndef SEC_LIB_H
+#define SEC_LIB_H
+
+#include "typedefs.h"
+
+/******************************************************************************
+ * CONSTANT DEFINITIONS
+ ******************************************************************************/
+#define INCORRECT_INDEX (0xFFFFFFFFUL) /* incorrect register index */
+
+/******************************************************************************
+ * EXPORT FUNCTION
+ ******************************************************************************/
+int seclib_get_hrid_key(u32 *key, u32 key_size);
+int seclib_get_hwid_key(u8 *key, u32 key_size);
+#endif /* SEC_LIB_H*/
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/string.h b/src/bsp/trustzone/teeloader/mt2731/include/string.h
new file mode 100644
index 0000000..bf18bea
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/string.h
@@ -0,0 +1,57 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef STRING_H
+#define STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, int count);
+extern void *memset(void *s, int c, int count);
+extern void *memcpy(void *dest, const void *src, int count);
+extern int memcmp(const void *cs, const void *ct, int count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STRING_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h b/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h
new file mode 100644
index 0000000..5305aef
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/typedefs.h
@@ -0,0 +1,184 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TYPEDEFS_H
+#define TYPEDEFS_H
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef volatile unsigned char *P_U8;
+typedef volatile signed char *P_S8;
+typedef volatile unsigned short *P_U16;
+typedef volatile signed short *P_S16;
+typedef volatile unsigned int *P_U32;
+typedef volatile signed int *P_S32;
+typedef unsigned long long *P_U64;
+typedef signed long long *P_S64;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+//------------------------------------------------------------------
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned short USHORT;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed int INT32;
+typedef signed int DWORD;
+typedef void VOID;
+typedef unsigned char BYTE;
+typedef float FLOAT;
+
+typedef char *LPCSTR;
+typedef short *LPWSTR;
+
+//------------------------------------------------------------------
+typedef char __s8;
+typedef unsigned char __u8;
+typedef short __s16;
+typedef unsigned short __u16;
+typedef int __s32;
+typedef unsigned int __u32;
+typedef long long __s64;
+typedef unsigned long long __u64;
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+typedef unsigned long uintptr_t;
+typedef u64 uint64_t;
+typedef u32 uint32_t;
+typedef u32 size_t;
+typedef u8 uint8_t;
+
+//------------------------------------------------------------------
+#ifndef FALSE
+#define FALSE (0U)
+#endif
+#ifndef TRUE
+#define TRUE (1U)
+#endif
+
+#ifndef NULL
+#define NULL (0U)
+#endif
+
+/*==== EXPORTED MACRO ===================================================*/
+#define READ_REGISTER_UINT32(reg) \
+ (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+ (*(volatile UINT32 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT16(reg) \
+ (*(volatile UINT16 * const)(reg))
+
+#define WRITE_REGISTER_UINT16(reg, val) \
+ (*(volatile UINT16 * const)(reg)) = (val)
+
+#define READ_REGISTER_UINT8(reg) \
+ (*(volatile UINT8 * const)(reg))
+
+#define WRITE_REGISTER_UINT8(reg, val) \
+ (*(volatile UINT8 * const)(reg)) = (val)
+
+#define INREG8(x) READ_REGISTER_UINT8((UINT8*)(x))
+#define OUTREG8(x, y) WRITE_REGISTER_UINT8((UINT8*)(x), (UINT8)(y))
+#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
+#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
+
+#define INREG16(x) READ_REGISTER_UINT16((UINT16*)(x))
+#define OUTREG16(x, y) WRITE_REGISTER_UINT16((UINT16*)(x),(UINT16)(y))
+#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
+#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
+
+#define INREG32(x) READ_REGISTER_UINT32((UINT32*)(x))
+#define OUTREG32(x, y) WRITE_REGISTER_UINT32((UINT32*)(x), (UINT32)(y))
+#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
+#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
+
+#define DRV_Reg8(addr) INREG8(addr)
+#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
+#define DRV_SetReg8(addr, data) SETREG8(addr, data)
+#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
+
+#define DRV_Reg16(addr) INREG16(addr)
+#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
+#define DRV_SetReg16(addr, data) SETREG16(addr, data)
+#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
+
+#define DRV_Reg32(addr) INREG32(addr)
+#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
+#define DRV_SetReg32(addr, data) SETREG32(addr, data)
+#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
+
+#define __raw_readb(REG) DRV_Reg8(REG)
+#define __raw_readw(REG) DRV_Reg16(REG)
+#define __raw_readl(REG) DRV_Reg32(REG)
+#define __raw_writeb(VAL, REG) DRV_WriteReg8(REG,VAL)
+#define __raw_writew(VAL, REG) DRV_WriteReg16(REG,VAL)
+#define __raw_writel(VAL, REG) DRV_WriteReg32(REG,VAL)
+
+#define printf print
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bf3deaa
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_mpu.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017 All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_MPU_H
+#define TZ_EMI_MPU_H
+
+#define EMI_PHY_OFFSET (0x40000000UL)
+#define EMI_MPU_ALIGNMENT (0x10000UL)
+#define PERIAXI_BUS_CTL3 (0x10003208UL)
+#define PERISYS_4G_SUPPORT (0x1 << 11)
+
+
+typedef enum
+{
+ TZ_MPU_SEC_RW_NSEC_RW = 0, /* read and write for both secure and non-secure access */
+ TZ_MPU_SEC_RW_NSEC_DENY = 1, /* read and write for secure access */
+ TZ_MPU_SEC_RW_NSEC_RO = 2, /* read and write for secure access and read only for non-secure access */
+ TZ_MPU_SEC_RW_NSEC_WO = 3, /* read and write for secure access and write only for non-secure access */
+ TZ_MPU_SEC_RO_NSEC_RO = 4, /* read only for both secure access and non-secure access */
+ TZ_MPU_SEC_DENY_NSEC_DENY = 5, /* Any access is prohibited */
+ TZ_MPU_SEC_RO_NSEC_RW = 6 /* read and write for non-secure access and read only for secure access */
+} tz_mpu_permission;
+
+#define SECURE_OS_MPU_REGION_ID (0)
+#define ATF_MPU_REGION_ID (1)
+
+/*SET_ACCESS_PERMISSON is used to merge domain permission into one setting*/
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+
+
+#endif /* TZ_EMI_MPU_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h
new file mode 100644
index 0000000..dc844f7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_emi_reg.h
@@ -0,0 +1,97 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_EMI_REG_H
+#define TZ_EMI_REG_H
+
+#define EMI_MPU_BASE (0x1020E000U)
+
+#define EMI_MPU_SA0 ((P_U32)(EMI_MPU_BASE+0x100)) /* EMI MPU start addr 0 */
+#define EMI_MPU_SA1 ((P_U32)(EMI_MPU_BASE+0x104)) /* EMI MPU start addr 1 */
+#define EMI_MPU_SA2 ((P_U32)(EMI_MPU_BASE+0x108)) /* EMI MPU start addr 2 */
+#define EMI_MPU_SA3 ((P_U32)(EMI_MPU_BASE+0x10C)) /* EMI MPU start addr 3 */
+#define EMI_MPU_SA4 ((P_U32)(EMI_MPU_BASE+0x110)) /* EMI MPU start addr 4 */
+#define EMI_MPU_SA5 ((P_U32)(EMI_MPU_BASE+0x114)) /* EMI MPU start addr 5 */
+#define EMI_MPU_SA6 ((P_U32)(EMI_MPU_BASE+0x118)) /* EMI MPU start addr 6 */
+#define EMI_MPU_SA7 ((P_U32)(EMI_MPU_BASE+0x11C)) /* EMI MPU start addr 7 */
+
+#define EMI_MPU_EA0 ((P_U32)(EMI_MPU_BASE+0x200)) /* EMI MPU end addr 0 */
+#define EMI_MPU_EA1 ((P_U32)(EMI_MPU_BASE+0x204)) /* EMI MPU end addr 1 */
+#define EMI_MPU_EA2 ((P_U32)(EMI_MPU_BASE+0x208)) /* EMI MPU end addr 2 */
+#define EMI_MPU_EA3 ((P_U32)(EMI_MPU_BASE+0x20C)) /* EMI MPU end addr 3 */
+#define EMI_MPU_EA4 ((P_U32)(EMI_MPU_BASE+0x210)) /* EMI MPU end addr 4 */
+#define EMI_MPU_EA5 ((P_U32)(EMI_MPU_BASE+0x214)) /* EMI MPU end addr 5 */
+#define EMI_MPU_EA6 ((P_U32)(EMI_MPU_BASE+0x218)) /* EMI MPU end addr 6 */
+#define EMI_MPU_EA7 ((P_U32)(EMI_MPU_BASE+0x21C)) /* EMI MPU end addr 7 */
+
+#define EMI_MPU_APC0 ((P_U32)(EMI_MPU_BASE+0x300)) /* EMI MPU APC 0 */
+#define EMI_MPU_APC1 ((P_U32)(EMI_MPU_BASE+0x304)) /* EMI MPU APC 1 */
+#define EMI_MPU_APC2 ((P_U32)(EMI_MPU_BASE+0x308)) /* EMI MPU APC 2 */
+#define EMI_MPU_APC3 ((P_U32)(EMI_MPU_BASE+0x30C)) /* EMI MPU APC 3 */
+#define EMI_MPU_APC4 ((P_U32)(EMI_MPU_BASE+0x310)) /* EMI MPU APC 4 */
+#define EMI_MPU_APC5 ((P_U32)(EMI_MPU_BASE+0x314)) /* EMI MPU APC 5 */
+#define EMI_MPU_APC6 ((P_U32)(EMI_MPU_BASE+0x318)) /* EMI MPU APC 6 */
+#define EMI_MPU_APC7 ((P_U32)(EMI_MPU_BASE+0x31C)) /* EMI MPU APC 7 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 0 */
+
+#define EMI_MPU_CTRL_D0 ((P_U32)(EMI_MPU_BASE+0x800)) /* EMI MPU DOMAIN CTRL 0 */
+#define EMI_MPU_CTRL_D1 ((P_U32)(EMI_MPU_BASE+0x804)) /* EMI MPU DOMAIN CTRL 1 */
+#define EMI_MPU_CTRL_D2 ((P_U32)(EMI_MPU_BASE+0x808)) /* EMI MPU DOMAIN CTRL 2 */
+#define EMI_MPU_CTRL_D3 ((P_U32)(EMI_MPU_BASE+0x80C)) /* EMI MPU DOMAIN CTRL 3 */
+#define EMI_MPU_CTRL_D4 ((P_U32)(EMI_MPU_BASE+0x810)) /* EMI MPU DOMAIN CTRL 4 */
+#define EMI_MPU_CTRL_D5 ((P_U32)(EMI_MPU_BASE+0x814)) /* EMI MPU DOMAIN CTRL 5 */
+#define EMI_MPU_CTRL_D6 ((P_U32)(EMI_MPU_BASE+0x818)) /* EMI MPU DOMAIN CTRL 6 */
+#define EMI_MPU_CTRL_D7 ((P_U32)(EMI_MPU_BASE+0x81C)) /* EMI MPU DOMAIN CTRL 7 */
+
+#define EMI_MPU_MASK_D0 ((P_U32)(EMI_MPU_BASE+0x900)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D1 ((P_U32)(EMI_MPU_BASE+0x904)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D2 ((P_U32)(EMI_MPU_BASE+0x908)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D3 ((P_U32)(EMI_MPU_BASE+0x90C)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D4 ((P_U32)(EMI_MPU_BASE+0x910)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D5 ((P_U32)(EMI_MPU_BASE+0x914)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D6 ((P_U32)(EMI_MPU_BASE+0x918)) /* EMI MPU DOMAIN MASK 0 */
+#define EMI_MPU_MASK_D7 ((P_U32)(EMI_MPU_BASE+0x91C)) /* EMI MPU DOMAIN MASK 0 */
+
+#endif /* TZ_EMI_REG_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h
new file mode 100644
index 0000000..63d22bd
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_init.h
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_INIT_H
+#define TZ_INIT_H
+//Don't used the typedef of teeloader, as this file will be included in Trustonic tee.
+//Which MUST use specific gcc version compiler, and the compiler have some conflict define
+//with the typedef here.
+//#include "typedefs.h"
+
+#define ATF_BOOTCFG_MAGIC (0x4D415446U) // String MATF in little-endian
+
+#define DEVINFO_SIZE (4U)
+#define HRID_SIZE 2
+/* bootarg for ATF */
+typedef struct {
+ unsigned long long bootarg_loc;
+ unsigned long long bootarg_size;
+ unsigned long long bl33_start_addr;
+ unsigned long long tee_info_addr;
+ unsigned long long boot_reason; // pass boot reason from bl2 to bl33
+} mtk_bl_param_t;
+
+typedef struct {
+ unsigned int atf_magic;
+ unsigned int tee_support;
+ unsigned int tee_boot_arg_addr;
+ unsigned int tee_entry;
+ unsigned int hwuid[4]; // HW Unique id for t-base used
+ unsigned int HRID[HRID_SIZE]; // HW random id for t-base used
+ unsigned int atf_log_port;
+ unsigned int atf_log_baudrate;
+ unsigned int atf_log_buf_start;
+ unsigned int atf_log_buf_size;
+ unsigned int atf_aee_debug_buf_start;
+ unsigned int atf_aee_debug_buf_size;
+ unsigned int devinfo[DEVINFO_SIZE];
+ unsigned int atf_irq_num;
+ unsigned int msg_auth_key[8]; /* size of message auth key is 256 bits */
+#if CFG_TEE_SUPPORT
+ unsigned int tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+extern void tee_set_entry(unsigned int addr);
+extern void tee_set_hwuid(void);
+void trustzone_pre_init(void);
+void trustzone_post_init(void);
+void trustzone_jump(unsigned int addr, unsigned int arg1, unsigned int arg2);
+
+#endif /* TZ_INIT_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h
new file mode 100644
index 0000000..6d157c6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_mem.h
@@ -0,0 +1,103 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_MEM_H
+#define TZ_MEM_H
+
+#include "tz_init.h"
+
+#define SRAM_BASE_ADDRESS (0x00100000UL)
+#define SRAM_START_ADDR (0x00102140UL)
+#define VECTOR_START (SRAM_START_ADDR + 0xBAC0UL)
+
+typedef struct tz_memory_t {
+ short next, previous;
+} tz_memory_t;
+
+#define FREE ((short)(0x0001U))
+#define IS_FREE(x) ((x)->next & FREE)
+#define CLEAR_FREE(x) ((x)->next &= ~FREE)
+#define SET_FREE(x) ((x)->next |= FREE)
+#define FROM_ADDR(x) ((short)(ptrdiff_t)(x))
+#define TO_ADDR(x) ((tz_memory_t *)(SRAM_BASE_ADDRESS + ((x) & ~FREE)))
+
+/* SEC MEM magic */
+#define SEC_MEM_MAGIC (0x3C562817U)
+/* SEC MEM version */
+#define SEC_MEM_VERSION (0x00010000U)
+/* Tplay Table Size */
+#define SEC_MEM_TPLAY_TABLE_SIZE (0x1000UL) //4KB by default
+#define SEC_MEM_TPLAY_MEMORY_SIZE (0x80000UL) //0.5MB by default
+
+#define BL31 (0x43001000UL)
+#define BL31_SIZE (0x40000UL) //change to 256KB (192KB by default)
+#define BL33 (0x42110000UL)
+
+
+#define ATF_BOOT_ARG_ADDR (0x40000000UL)
+#define ATF_INIT_ARG_ADDR (0x40000100UL)
+#define TEE_BOOT_ARG_ADDR (0x43000100UL)
+
+#define TEE_PARAMETER_BASE (TEE_BOOT_ARG_ADDR)
+#define TEE_PARAMETER_ADDR (TEE_BOOT_ARG_ADDR + 0x100UL)
+
+#define TEE_SECURE_ISRAM_ADDR (0x0UL)
+#define TEE_SECURE_ISRAM_SIZE (0x0UL)
+
+#if CFG_ATF_LOG_SUPPORT
+#define ATF_LOG_BUFFER_SIZE (0x40000UL) //256KB
+#define ATF_AEE_BUFFER_SIZE (0x4000UL) //16KB
+#else
+#define ATF_LOG_BUFFER_SIZE (0x0UL) //don't support ATF log
+#define ATF_AEE_BUFFER_SIZE (0x0UL) //don't support ATF log
+#endif
+
+typedef struct {
+ unsigned int magic; // Magic number
+ unsigned int version; // version
+ unsigned int svp_mem_start; // MM sec mem pool start addr.
+ unsigned int svp_mem_end; // MM sec mem pool end addr.
+ unsigned int tplay_table_start; // tplay handle-to-physical table start
+ unsigned int tplay_table_size; // tplay handle-to-physical table size
+ unsigned int tplay_mem_start; // tplay physcial memory start address for crypto operation
+ unsigned int tplay_mem_size; // tplay phsycial memory size for crypto operation
+ unsigned int secmem_obfuscation; // MM sec mem obfuscation or not
+ unsigned int rpmb_size; /* size of rpmb partition */
+ unsigned int msg_auth_key[8]; /* size of message auth key is 32bytes(256 bits) */
+ unsigned int emmc_rel_wr_sec_c; // emmc ext_csd[222]
+} sec_mem_arg_t;
+#endif /* TZ_MEM_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h b/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h
new file mode 100644
index 0000000..5ef1cf8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/tz_tbase.h
@@ -0,0 +1,78 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef TZ_TBASE_H
+#define TZ_TBASE_H
+
+#include "typedefs.h"
+
+/* Tbase Magic For Interface */
+#define TBASE_BOOTCFG_MAGIC (0x434d4254U) // String TBMC in little-endian
+
+/* TEE version */
+#define TEE_ARGUMENT_VERSION (0x00010000U)
+
+typedef struct {
+ u32 magic; // magic value from information
+ u32 length; // size of struct in bytes.
+ u64 version; // Version of structure
+ u64 dRamBase; // NonSecure DRAM start address
+ u64 dRamSize; // NonSecure DRAM size
+ u64 secDRamBase; // Secure DRAM start address
+ u64 secDRamSize; // Secure DRAM size
+ u64 secIRamBase; // Secure IRAM base
+ u64 secIRamSize; // Secure IRam size
+ u64 conf_mair_el3;// MAIR_EL3 for memory attributes sharing
+ u32 RFU1;
+ u32 MSMPteCount; // Number of MMU entries for MSM
+ u64 MSMBase; // MMU entries for MSM
+ u64 gic_distributor_base;
+ u64 gic_cpuinterface_base;
+ u32 gic_version;
+ u32 RFU2;
+ u64 flags;
+ u32 total_number_spi;
+ u32 ssiq_number;
+}tee_arg_t, *tee_arg_t_ptr;
+
+/**************************************************************************
+ * EXPORTED FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry, u32 tbase_sec_dram_size, u32 tee_smem_size);
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry, u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size);
+
+#endif /* TZ_TBASE_H */
diff --git a/src/bsp/trustzone/teeloader/mt2731/include/uart.h b/src/bsp/trustzone/teeloader/mt2731/include/uart.h
new file mode 100644
index 0000000..9a6ba92
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/include/uart.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include "typedefs.h"
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart) (uart)
+#define UART_LSR(uart) (UART_BASE(uart) + 0x14U)
+#define UART_LSR_THRE (1U << 5U)
+#define UART_THR(uart) (UART_BASE(uart) + 0x0U) /* Write only */
+
+#define IO_PHYS (0x10000000UL)
+#define UART1_BASE (IO_PHYS + 0x01002000UL)
+
+int uart_putc(char c);
+
+#endif /* UART_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a b/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a
new file mode 100644
index 0000000..f524098
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/prebuilt/libsec.a
Binary files differ
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c b/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c
new file mode 100644
index 0000000..6e5e942
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/drivers/device_apc.c
@@ -0,0 +1,984 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include <stdbool.h>
+#include "device_apc.h"
+#include "print.h"
+
+#define MTAG "[DEVAPC]"
+#define DAPC_DEBUG
+
+#ifdef DAPC_DEBUG
+#define DBG(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG(str, ...) do {} while(0)
+#endif
+
+#define INFO(str, ...) do {print(MTAG str, ##__VA_ARGS__);} while(0)
+#define ERROR(str, ...) do {print(MTAG "[ERROR]" str, ##__VA_ARGS__);} while(0)
+
+
+static const struct INFRA_PERI_DEVICE_INFO D_APC_INFRA_Devices[] = {
+ /* module, AP permission, MD permission, SPM permission,
+ */
+
+ /* 0 */
+ DAPC_INFRA_ATTR("SPM_APB_S", E_NO_PROTECTION, E_SEC_RW_ONLY, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SPM_APB_S-1", E_SEC_RW_ONLY, E_SEC_RW_ONLY, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SPM_APB_S-2", E_SEC_RW_ONLY, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("TOPCKGEN_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRACFG_AO_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("IOCFG_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("PERICFG_AO_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EFUSE_DEBUG_AO_APB_S", E_SEC_RW_NS_R, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GPIO_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("TOPRGU_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+
+ /* 10 */
+ DAPC_INFRA_ATTR("APXGPT_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRAAO_RSV0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SEJ_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("AP_CIRQ_EINT_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("APMIXEDSYS_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("PMIC_WRAP_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRAAO_RSV2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("KP_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("TOP_MISC_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DVFSRC_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+
+ /* 20 */
+ DAPC_INFRA_ATTR("MBIST_AO_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CLDMA_AO_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRAAO_BCRM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("AES_TOP0_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SYS_TIMER_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MODEM_TEMP_SHARE_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DEBUG_CTRL_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SECURITY_AO_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("TOPCKGEN_INFRA_CFG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DEVICE_APC_AO_APB_S", E_SEC_RW_ONLY, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 30 */
+ DAPC_INFRA_ATTR("PWM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("HSM_AXI_S", E_SEC_RW_ONLY, E_FORBIDDEN, E_FORBIDDEN, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("PCIE_BR_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("PCIE_PCI0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SSUSB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SSUSB_S-1", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SSUSB_S-2", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("USB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("USB_S-1", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("USB_S-2", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 40 */
+ DAPC_INFRA_ATTR("MCUPM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MCUPM_APB_S-1", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MCUPM_APB_S-2", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("AUDIO_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MSDC0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MSDC1_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MSDC2_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EAST_APB0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EAST_APB1_S", E_NO_PROTECTION, E_SEC_RW_NS_R, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EAST_APB2_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 50 */
+ DAPC_INFRA_ATTR("EAST_APB3_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SOUTH_APB0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("SOUTH_APB1_S", E_NO_PROTECTION, E_SEC_RW_NS_R, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SOUTH_APB2_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SOUTH_APB3_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("WEST_APB0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("WEST_APB1_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("WEST_APB2_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("WEST_APB3_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("NORTH_APB0_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 60 */
+ DAPC_INFRA_ATTR("NORTH_APB1_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("NORTH_APB2_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("NORTH_APB3_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MCUCFG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SYS_CIRQ_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("TRNG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DEVICE_APC_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DEBUG_TRACKER_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF0_AP_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF0_MD_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 70 */
+ DAPC_INFRA_ATTR("CCIF1_AP_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF1_MD_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("MBIST_PDN_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRACFG_PDN_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_NS_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_MMU_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CQ_DMA_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRA_RSV0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SRAMROM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_NO_PROTECTION),
+
+ /* 80 */
+ DAPC_INFRA_ATTR("INFRA_BCRM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EMI_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("INFRA_RSV2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CLDMA_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CLDMA_MD_APB_S", E_NO_PROTECTION, E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("EMI_MPU_APB_S", E_SEC_RW_NS_R, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("INFRA_RSV3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH0_TOP0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH0_TOP1_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH0_TOP2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+
+ /* 90 */
+ DAPC_INFRA_ATTR("DRAMC_CH0_TOP3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH0_TOP4_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH1_TOP0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH1_TOP1_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH1_TOP2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH1_TOP3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DRAMC_CH1_TOP4_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCE_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF2_AP_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF2_MD_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 100 */
+ DAPC_INFRA_ATTR("CCIF3_AP_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("CCIF3_MD_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC4_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC5_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC6_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC7_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC8_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 110 */
+ DAPC_INFRA_ATTR("GCPU_ECC9_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC10_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC11_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC12_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC13_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC14_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC15_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("GCPU_ECC16_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("FAKE_ENG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("TRFG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 120 */
+ DAPC_INFRA_ATTR("DEBUG_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("APDMA_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("AUXADC_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("UART0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("UART1_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_NO_PROTECTION),
+ DAPC_INFRA_ATTR("UART2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("UART3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_NO_PROTECTION, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("I2C0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("I2C1_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("I2C2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 130 */
+ DAPC_INFRA_ATTR("SPI0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("PTP_THERM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("BTIF_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("PERI_RSV0_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("DISP_PWM_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("I2C3_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SPI1_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("I2C4_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SPI2_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("SPI_SLV_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+ /* 140 */
+ DAPC_INFRA_ATTR("UART4_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("UART5_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("UART6_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("IMP_IIC_WRAP_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("NFI_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("NFIECC_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+ DAPC_INFRA_ATTR("ETHER_APB_S", E_NO_PROTECTION, E_FORBIDDEN, E_FORBIDDEN, E_FORBIDDEN),
+
+};
+
+static const struct MD_DEVICE_INFO D_APC_MD_Devices[] = {
+ /* module, AP permission */
+
+ /* 0 */
+ DAPC_MD_ATTR("MDPERISYS_1", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MDPERISYS_2/MDTOP", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MDMCUAPB", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MDCORESYS", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MDINFRA_APB_1", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MDINFRA_APB_2", E_NO_PROTECTION),
+ DAPC_MD_ATTR("MML2", E_NO_PROTECTION),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+
+ /* 10 */
+ DAPC_MD_ATTR("MD_INFRA", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("uSIP Peripheral", E_FORBIDDEN),
+ DAPC_MD_ATTR("modeml1_ao_top_pwr_wrap", E_NO_PROTECTION),
+ DAPC_MD_ATTR("md2gsys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("rxdfesys_pwr_wrap", E_FORBIDDEN),
+
+ /* 20 */
+ DAPC_MD_ATTR("cssys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("txsys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("bigramsys (mem)", E_FORBIDDEN),
+ DAPC_MD_ATTR("md32scq share (mem)", E_FORBIDDEN),
+ DAPC_MD_ATTR("md32scq_vu01 (mem)", E_FORBIDDEN),
+ DAPC_MD_ATTR("peripheral (reg)", E_FORBIDDEN),
+ DAPC_MD_ATTR("rakesys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("rakesys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("brpsys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("brpsys_pwr_wrap", E_FORBIDDEN),
+
+ /* 30 */
+ DAPC_MD_ATTR("dmcsys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("dmcsys_pwr_wrap", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+ DAPC_MD_ATTR("-", E_FORBIDDEN),
+
+};
+
+static uint32_t set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module,
+ enum E_MASK_DOM domain_num, enum APC_ATTR permission)
+{
+ uint32_t *base = NULL;
+ uint32_t apc_index;
+ uint32_t apc_set_index;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ if (permission != E_NO_PROTECTION &&
+ permission != E_SEC_RW_ONLY &&
+ permission != E_SEC_RW_NS_R &&
+ permission != E_FORBIDDEN) {
+
+ ERROR("permission=0x%x is not supported!\n",
+ permission);
+ return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+ }
+
+ apc_index = module / MOD_NO_IN_1_DEVAPC;
+ apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+ clr_bit = 0xFFFFFFFF ^ (0x3 << (apc_set_index * 2));
+ set_bit = permission << (apc_set_index * 2);
+
+ /* Do boundary check */
+ if (slave_type == E_DAPC_INFRA_SLAVE &&
+ module <= SLAVE_INFRA_MAX_INDEX &&
+ domain_num <= E_DOMAIN_15)
+ base = (uint32_t *)((size_t)DEVAPC_SYS0_D0_APC_0 +
+ domain_num * 0x40 + apc_index * 4);
+
+ else if (slave_type == E_DAPC_SRAMROM_SLAVE &&
+ module <= SLAVE_SRAMROM_MAX_INDEX &&
+ domain_num <= E_DOMAIN_8)
+ base = (uint32_t *)((size_t)DEVAPC_SYS1_D0_APC_0 +
+ domain_num * 0x40 + apc_index * 4);
+
+ else if (slave_type == E_DAPC_MD_SLAVE &&
+ module <= SLAVE_MD_MAX_INDEX &&
+ domain_num <= E_DOMAIN_3)
+ base = (uint32_t *)((size_t)DEVAPC_SYS2_D0_APC_0 +
+ domain_num * 0x40 + apc_index * 4);
+ else {
+ ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+ "slave_type", slave_type,
+ "module", module,
+ "domain_num", domain_num);
+
+ return DEVAPC_ERR_OUT_OF_BOUNDARY;
+ }
+
+ if (base != NULL) {
+ devapc_writel((devapc_readl(base) & clr_bit), base);
+ devapc_writel((devapc_readl(base) | set_bit), base);
+
+ return DEVAPC_OK;
+ }
+
+ return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_transaction(enum DAPC_MASTER_TYPE master_type,
+ uint32_t master_index, enum E_TRANSACTION transaction_type)
+{
+ uint32_t *base = NULL;
+ uint32_t master_set_index;
+
+ master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+ if (master_type == E_DAPC_MASTER &&
+ master_index <= MASTER_INFRA_MAX_INDEX)
+ base = (uint32_t *)DEVAPC_INFRA_MAS_SEC_0;
+
+ else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+ master_index <= MASTER_INFRACFG_AO_MAX_INDEX)
+ base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_SEC;
+
+ else {
+ ERROR("out of boundary, %s=0x%x, %s=0x%x\n",
+ "master_type", master_type,
+ "master_index", master_index);
+
+ return DEVAPC_ERR_OUT_OF_BOUNDARY;
+ }
+
+ if (base != NULL) {
+ if (transaction_type == NON_SECURE_TRANSACTION)
+ devapc_writel(devapc_readl(base) &
+ (0xFFFFFFFF ^ (0x1 << master_set_index)), base);
+ else if (transaction_type == SECURE_TRANSACTION)
+ devapc_writel(devapc_readl(base) |
+ (0x1 << master_set_index), base);
+ else {
+ ERROR("transaction=0x%x is not supported!\n",
+ transaction_type);
+ return DEVAPC_ERR_PERMISSION_NOT_SUPPORTED;
+ }
+
+ return DEVAPC_OK;
+ }
+
+ return DEVAPC_ERR_GENERIC;
+}
+
+static uint32_t set_master_domain(enum DAPC_MASTER_TYPE master_type,
+ uint32_t master_index, enum E_MASK_DOM dom_num)
+{
+ uint32_t *base = NULL;
+ uint32_t master_reg_index;
+ uint32_t master_set_index;
+ uint32_t set_bit;
+
+ if (master_type == E_DAPC_MASTER &&
+ master_index <= MASTER_INFRA_MAX_INDEX &&
+ dom_num <= E_DOMAIN_15) {
+ master_reg_index = master_index / MAS_DOM_NO_IN_1_DEVAPC;
+ master_set_index = master_index % MAS_DOM_NO_IN_1_DEVAPC;
+ set_bit = dom_num << (master_set_index * 8);
+
+ base = (uint32_t *)((size_t)DEVAPC_INFRA_MAS_DOM_0 + master_reg_index * 4);
+
+ } else if (master_type == E_DAPC_INFRACFG_AO_MASTER &&
+ master_index <= MASTER_INFRACFG_AO_MAX_INDEX &&
+ dom_num <= E_DOMAIN_15) {
+ set_bit = dom_num << (master_index * 4);
+ base = (uint32_t *)INFRACFG_AO_DEVAPC_MAS_DOM;
+
+ } else {
+ ERROR("out of boundary, %s=0x%x, %s=0x%x, %s=0x%x\n",
+ "master_type", master_type,
+ "master_index", master_index,
+ "dom_num", dom_num);
+
+ return DEVAPC_ERR_OUT_OF_BOUNDARY;
+ }
+
+ if (base != NULL) {
+ devapc_writel(devapc_readl(base) | set_bit, base);
+ return DEVAPC_OK;
+ }
+
+ return DEVAPC_ERR_GENERIC;
+}
+
+static void dump_infra_apc(void)
+{
+ /* d: domain, i: register number */
+ int d, i;
+
+ for (d = 0; d < DEVAPC_INFRA_DOM_MAX; d++) {
+ if (d != E_DOMAIN_0 && d != E_DOMAIN_1 && d != E_DOMAIN_9 && d != E_DOMAIN_11)
+ continue;
+
+ for (i = 0; i < DEVAPC_INFRA_APC_NUM; i++) {
+ INFO("(INFRA)SYS0_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+ ((size_t)DEVAPC_SYS0_D0_APC_0 + 0x40 * d + i * 4),
+ devapc_readl((size_t)DEVAPC_SYS0_D0_APC_0 +
+ 0x40 * d + i * 4)
+ );
+ }
+ }
+
+ INFO("(INFRA)MAS_SEC_0 = 0x%x\n", devapc_readl(DEVAPC_INFRA_MAS_SEC_0));
+}
+
+static void dump_sramrom_apc(void)
+{
+ /* d: domain, i: register number */
+ int d, i;
+
+ for (d = 0 ; d < DEVAPC_SRAMROM_DOM_MAX ; d++)
+ for (i = 0; i < DEVAPC_SRAMROM_APC_NUM; i++) {
+ INFO("(MD)SYS1_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+ ((size_t)DEVAPC_SYS1_D0_APC_0 + 0x40 * d + i * 4),
+ devapc_readl((size_t)DEVAPC_SYS1_D0_APC_0 +
+ 0x40 * d + i * 4)
+ );
+ }
+}
+
+static void dump_md_apc(void)
+{
+ /* d: domain, i: register number */
+ int d, i;
+
+ for (d = 0 ; d < DEVAPC_MD_DOM_MAX ; d++) {
+ if (d != E_DOMAIN_0)
+ continue;
+
+ for (i = 0; i < DEVAPC_MD_APC_NUM; i++) {
+ INFO("(MD)SYS2_D%d_APC_%d(0x%x) = 0x%x\n", d, i,
+ ((size_t)DEVAPC_SYS2_D0_APC_0 + 0x40 * d + i * 4),
+ devapc_readl((size_t)DEVAPC_SYS2_D0_APC_0 +
+ 0x40 * d + i * 4)
+ );
+ }
+ }
+}
+
+/*
+static void dump_pms_info(void)
+{
+ INFO("[PMS]AP2MD1_PMS_CTRL_EN = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN));
+ INFO("[PMS]AP2MD1_PMS_CTRL_EN_LOCK = 0x%x\n", devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK));
+}
+*/
+
+static void print_vio_mask_sta(void)
+{
+ int i;
+
+ for (i = 0; i < VIO_MASK_STA_NUM; i++) {
+ INFO("%s: (%d:0x%x) %s: (%d:0x%x)\n",
+ "INFRA VIO_MASK", i,
+ devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(i)),
+ "INFRA VIO_STA", i,
+ devapc_readl(DEVAPC_PD_INFRA_VIO_STA(i))
+ );
+ }
+}
+
+static void unmask_infra_module(uint32_t module)
+{
+ uint32_t apc_index = 0;
+ uint32_t apc_bit_index = 0;
+
+ if (module > VIOLATION_MAX_INDEX) {
+ ERROR("%s: module overflow!\n", __func__);
+ return;
+ }
+
+ apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+ apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+ devapc_writel(devapc_readl(DEVAPC_PD_INFRA_VIO_MASK(apc_index)) &
+ (0xFFFFFFFF ^ (1 << apc_bit_index)),
+ DEVAPC_PD_INFRA_VIO_MASK(apc_index));
+}
+
+static uint32_t clear_infra_vio_status(uint32_t module)
+{
+ uint32_t apc_index = 0;
+ uint32_t apc_bit_index = 0;
+
+ if (module > VIOLATION_MAX_INDEX) {
+ ERROR("%s: module overflow!\n", __func__);
+ return DEVAPC_ERR_OUT_OF_BOUNDARY;
+ }
+
+ apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+ apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+ devapc_writel(0x1 << apc_bit_index,
+ DEVAPC_PD_INFRA_VIO_STA(apc_index));
+
+ return 0;
+}
+
+static int check_infra_vio_status(uint32_t module)
+{
+ uint32_t apc_index = 0;
+ uint32_t apc_bit_index = 0;
+
+ if (module > VIOLATION_MAX_INDEX) {
+ ERROR("%s: module overflow!\n", __func__);
+ return DEVAPC_ERR_OUT_OF_BOUNDARY;
+ }
+
+ apc_index = module / (MOD_NO_IN_1_DEVAPC * 2);
+ apc_bit_index = module % (MOD_NO_IN_1_DEVAPC * 2);
+
+ if (devapc_readl(DEVAPC_PD_INFRA_VIO_STA(apc_index)) &
+ (0x1 << apc_bit_index))
+ return VIOLATION_TRIGGERED;
+
+ return 0;
+}
+
+static bool vio_shift_sta_handler(void)
+{
+ uint32_t vio_shift_sta = 0;
+
+ vio_shift_sta = devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+ INFO("(Pre)VIO_SHIFT_STA = 0x%x\n", vio_shift_sta);
+
+ if (vio_shift_sta) {
+ devapc_writel(vio_shift_sta, DEVAPC_PD_INFRA_VIO_SHIFT_STA);
+ INFO("(Post)clear VIO_SHIFT_STA = 0x%x\n",
+ devapc_readl(DEVAPC_PD_INFRA_VIO_SHIFT_STA));
+ }
+
+ return vio_shift_sta ? true : false;
+}
+
+static void devapc_irq_handler(void)
+{
+ int i;
+ uint64_t vio_sta;
+ uint64_t vio_addr;
+
+ INFO("enter %s...\n", __func__);
+ print_vio_mask_sta();
+ if (!vio_shift_sta_handler()) {
+ INFO("violation is not triggered or is clean before\n");
+ return;
+ }
+
+ for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+ if (check_infra_vio_status(i) == VIOLATION_TRIGGERED) {
+ INFO("violation is triggered, vio_idx=%d\n", i);
+ if (i == SRAMROM_VIO_INDEX)
+ handle_sramrom_vio(&vio_sta, &vio_addr);
+
+ clear_infra_vio_status(i);
+ }
+ }
+
+ print_vio_mask_sta();
+}
+
+#ifdef DEVAPC_UT
+static void devapc_ut(void)
+{
+ INFO("test violation...\n");
+
+ INFO("read blocked reg = 0x%x\n",
+ devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+ devapc_writel(0xdead, (unsigned int *)BLOCKED_REG_BASE);
+ INFO("read blocked reg = 0x%x\n",
+ devapc_readl((unsigned int *)BLOCKED_REG_BASE));
+
+ devapc_irq_handler();
+
+ mt_irq_dump_status(DEVAPC_IRQ_BIT_ID);
+}
+#endif
+
+static void devapc_set_dom(void)
+{
+
+ /* For EMI workaround, need set SPM as secure master to rw EMI self
+ * test start/end address
+ */
+ set_master_transaction(E_DAPC_MASTER, MASTER_SPM_SEC_INDEX, SECURE_TRANSACTION);
+
+ INFO("Setup master secure: %s = (0x%x), %s = (0x%x)\n",
+ "DEVAPC_INFRA_MAS_SEC_0",
+ devapc_readl(DEVAPC_INFRA_MAS_SEC_0),
+ "INFRACFG_AO_DEVAPC_MAS_SEC",
+ devapc_readl(INFRACFG_AO_DEVAPC_MAS_SEC)
+ );
+
+/******************************************************************************/
+/* Infra Master Domain Setting */
+
+ /* Set MD1 to DOMAIN1 */
+ set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_MD_INDEX, E_DOMAIN_1);
+
+ /* Set SPM to DOMAIN9 */
+ set_master_domain(E_DAPC_MASTER, MASTER_SPM_DOM_INDEX, E_DOMAIN_9);
+
+ /* Set HSM to DOMAIN11 */
+ set_master_domain(E_DAPC_INFRACFG_AO_MASTER, MASTER_HSM_INDEX, E_DOMAIN_11);
+
+ INFO("Setup master domain MAS_DOM_x: (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n",
+ devapc_readl(DEVAPC_INFRA_MAS_DOM_0),
+ devapc_readl(DEVAPC_INFRA_MAS_DOM_1),
+ devapc_readl(DEVAPC_INFRA_MAS_DOM_2),
+ devapc_readl(DEVAPC_INFRA_MAS_DOM_3),
+ devapc_readl(DEVAPC_INFRA_MAS_DOM_4)
+ );
+
+ INFO("Setup master domain INFRACFG_AO_DEVAPC_MAS_DOM: (0x%x)\n",
+ devapc_readl(INFRACFG_AO_DEVAPC_MAS_DOM)
+ );
+
+/******************************************************************************/
+/*Infra Domain Remap Setting */
+/* Infra: no domain remap */
+
+/* SRAMROM Domain Remap Setting */
+ devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_0);
+ devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_0_1);
+
+ reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_0_0, SRAMROM_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to SRAMROM domain 0
+
+ /* HW BUG: DOM_REMAP reg cannot read */
+/* INFO("Setup SRAMROM domain remap: (0x%x), (0x%x)\n",
+ devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_0),
+ devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_0_1)
+ );
+*/
+/* MD Domain Remap Setting */
+ devapc_writel(MASTER_DOM_RMP_INIT, DEVAPC_SRAMROM_DOM_REMAP_1_0);
+ reg_set_field(DEVAPC_SRAMROM_DOM_REMAP_1_0, MD_RMP_AP, E_DOMAIN_0); // remap Infra domain 0 to MD domain 0
+
+ /* HW BUG: DOM_REMAP reg cannot read */
+/* INFO("Setup MD domain remap: (0x%x)\n",
+ devapc_readl(DEVAPC_SRAMROM_DOM_REMAP_1_0)
+ );
+*/
+}
+
+static void devapc_set_apc(void)
+{
+ uint32_t module_index, dom_index;
+ uint32_t infra_size = sizeof(D_APC_INFRA_Devices)/
+ sizeof(struct INFRA_PERI_DEVICE_INFO);
+ uint32_t md_size = sizeof(D_APC_MD_Devices)/
+ sizeof(struct MD_DEVICE_INFO);
+ enum E_MASK_DOM dom_id;
+
+ /* Initial Permission */
+ INFO("Walk initial permission setting - Infra_peri\n");
+ for (module_index = 0; module_index < infra_size; module_index++) {
+ set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_0,
+ D_APC_INFRA_Devices[module_index].d0_permission); /* APMCU */
+ set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_1,
+ D_APC_INFRA_Devices[module_index].d1_permission); /* MD1 */
+ set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_9,
+ D_APC_INFRA_Devices[module_index].d9_permission); /* SPM */
+ set_module_apc(E_DAPC_INFRA_SLAVE, module_index, E_DOMAIN_11,
+ D_APC_INFRA_Devices[module_index].d11_permission); /* HSM */
+
+ /* block all reserved domain */
+ for (dom_id = E_DOMAIN_0; dom_id <= E_DOMAIN_15; dom_id++) {
+ if (dom_id != E_DOMAIN_0 && dom_id != E_DOMAIN_1 &&
+ dom_id != E_DOMAIN_9 && dom_id != E_DOMAIN_11)
+ set_module_apc(E_DAPC_INFRA_SLAVE, module_index,
+ dom_id, E_FORBIDDEN);
+ }
+ }
+
+ INFO("Walk initial permission setting - SRAMROM\n");
+ for (dom_index = 0; dom_index <= E_DOMAIN_8; dom_index++) {
+ if (dom_index == E_DOMAIN_0)
+ set_module_apc(E_DAPC_SRAMROM_SLAVE,
+ DEVAPC_CTRL_SRAMROM_INDEX,
+ dom_index, E_NO_PROTECTION);
+ else
+ set_module_apc(E_DAPC_SRAMROM_SLAVE,
+ DEVAPC_CTRL_SRAMROM_INDEX,
+ dom_index, E_FORBIDDEN);
+ }
+
+ /* MD 2nd level protection */
+ INFO("Walk initial permission setting - MD\n");
+ for (module_index = 0; module_index < md_size; module_index++) {
+ set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_0,
+ D_APC_MD_Devices[module_index].d0_permission);
+ /* block all reserved domain */
+ set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_1,
+ E_FORBIDDEN);
+ set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_2,
+ E_FORBIDDEN);
+ set_module_apc(E_DAPC_MD_SLAVE, module_index, E_DOMAIN_3,
+ E_FORBIDDEN);
+ }
+
+ /* Dump Permission */
+ dump_infra_apc();
+ dump_sramrom_apc();
+ dump_md_apc();
+
+ /* Set CG to Secure (INFRACFG_AO) */
+// devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON0) | SEJ_CG_PROTECT_BIT,
+// INFRA_AO_SEC_CG_CON0);
+// devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | TRNG_CG_PROTECT_BIT,
+// INFRA_AO_SEC_CG_CON1);
+ devapc_writel(devapc_readl(INFRA_AO_SEC_CG_CON1) | DEVAPC_CG_PROTECT_BIT,
+ INFRA_AO_SEC_CG_CON1);
+
+
+ INFO("INFRA_APC_CON = 0x%x\n", devapc_readl(DEVAPC_INFRA_APC_CON));
+
+ /* Set PMS(MD devapc) enable */
+// devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN) | 0x1, AP2MD1_PMS_CTRL_EN);
+// devapc_writel(devapc_readl(AP2MD1_PMS_CTRL_EN_LOCK) | 0x1, AP2MD1_PMS_CTRL_EN_LOCK);
+// dump_pms_info();
+
+ if (vio_shift_sta_handler()) {
+ INFO("violation happened after %s\n", __func__);
+ print_vio_mask_sta();
+ }
+
+#ifdef DEVAPC_UT
+ devapc_ut();
+#endif
+
+}
+
+static void sramrom_set_apc(void)
+{
+ INFO("[Pre] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+ devapc_readl(SRAMROM_SEC_ADDR),
+ devapc_readl(SRAMROM_SEC_ADDR1),
+ devapc_readl(SRAMROM_SEC_ADDR2)
+ );
+ INFO("[Pre] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+ devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+ devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+ );
+
+ /* Split 2 regions: 96KB(SEC), 96KB(NON_SEC) */
+ TZ_SRAMROM_SET_REGION_0_SIZE_KB(96);
+
+ /* Set APC to region 0 */
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM0_MASK, PERMIT_S_RW_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC0_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT);
+
+ /* Set APC to region 1 */
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM0_MASK, PERMIT_S_RW_NS_RW << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM1_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM2_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL, SRAMROM_SEC_CTRL_SEC1_DOM3_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT);
+ reg_set_field(SRAMROM_SEC_CTRL2, SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK, PERMIT_S_BLOCK_NS_BLOCK << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT);
+
+ /* Enable region 0 & region 1 protection */
+ DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC0_SEC_EN));
+ DRV_SetReg32(SRAMROM_SEC_ADDR, (0x1<<SRAMROM_SEC_ADDR_SEC1_SEC_EN));
+
+ INFO("[Post] SRAMROM SEC_ADDR:0x%x, SEC_ADDR1:0x%x, SEC_ADDR2:0x%x\n",
+ devapc_readl(SRAMROM_SEC_ADDR),
+ devapc_readl(SRAMROM_SEC_ADDR1),
+ devapc_readl(SRAMROM_SEC_ADDR2)
+ );
+ INFO("[Post] SRAMROM SEC_CTRL:0x%x, SEC_CTRL2:0x%x, SEC_CTRL5:0x%x, SEC_CTRL6:0x%x\n",
+ devapc_readl(SRAMROM_SEC_CTRL), devapc_readl(SRAMROM_SEC_CTRL2),
+ devapc_readl(SRAMROM_SEC_CTRL5), devapc_readl(SRAMROM_SEC_CTRL6)
+ );
+
+}
+
+void devapc_init(void)
+{
+ uint64_t sramrom_vio_sta;
+ uint64_t sramrom_vio_addr;
+ int i;
+
+ INFO("%s...\n", __func__);
+ /* Enable Devapc */
+ /* Lock DEVAPC_AO/DEVAPC_CON to secure access only */
+ devapc_writel(0x80000001, DEVAPC_INFRA_APC_CON);
+ devapc_writel(0x1, INFRACFG_AO_DEVAPC_CON);
+ devapc_writel(0x80000000, DEVAPC_PD_INFRA_APC_CON);
+
+ INFO("(Post) DEVAPC_INFRA_APC_CON:0x%x\n",
+ devapc_readl(DEVAPC_INFRA_APC_CON));
+ INFO("(Post) INFRACFG_AO_DEVAPC_CON:0x%x\n",
+ devapc_readl(INFRACFG_AO_DEVAPC_CON));
+ INFO("(Post) DEVAPC_PD_INFRA_APC_CON:0x%x\n",
+ devapc_readl(DEVAPC_PD_INFRA_APC_CON));
+
+ /* clr sramrom vio if any */
+ handle_sramrom_vio(&sramrom_vio_sta, &sramrom_vio_addr);
+
+// print_vio_mask_sta();
+ if (!vio_shift_sta_handler())
+ INFO("no violation happened before init\n");
+
+ /* clear vio_status & unmask vio_mask */
+ INFO("clear vio_staus & unmask modules\n");
+ for (i = 0; i <= VIOLATION_MAX_INDEX; i++) {
+ clear_infra_vio_status(i);
+ unmask_infra_module(i);
+ }
+
+// print_vio_mask_sta();
+
+ devapc_set_dom();
+#if CFG_DEVAPC_SET_PROTECT
+ devapc_set_apc();
+#else
+ INFO("Skip to set APC\n");
+#endif
+ sramrom_set_apc();
+
+ INFO("%s done\n", __func__);
+}
+
+/* It should clear SRAMROM vio before clear DEVAPC vio */
+int handle_sramrom_vio(uint64_t *vio_sta, uint64_t *vio_addr)
+{
+ int sramrom = -1;
+
+ if (devapc_readl(SRAMROM_SEC_VIO_STA) & SRAM_SEC_VIO_BIT) { /* SRAM part */
+ INFO("SRAM violation is triggered\n");
+
+ sramrom = 1;
+ *vio_sta = devapc_readl(SRAMROM_SEC_VIO_STA);
+ *vio_addr = devapc_readl(SRAMROM_SEC_VIO_ADDR);
+
+ INFO("(Pre) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+ (uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+ devapc_writel(0x1, SRAMROM_SEC_VIO_CLR);
+
+ INFO("(Post) SRAMROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+ devapc_readl(SRAMROM_SEC_VIO_STA),
+ devapc_readl(SRAMROM_SEC_VIO_ADDR));
+
+ } else if (devapc_readl(SRAMROM_ROM_SEC_VIO_STA) & ROM_SEC_VIO_BIT) { /* ROM part */
+ INFO("ROM violation is triggered\n");
+
+ sramrom = 0;
+ *vio_sta = devapc_readl(SRAMROM_ROM_SEC_VIO_STA);
+ *vio_addr = devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR);
+
+ INFO("(Pre) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+ (uint32_t)*vio_sta, (uint32_t)*vio_addr);
+
+ devapc_writel(0x1, SRAMROM_ROM_SEC_VIO_CLR);
+
+ INFO("(Post) SRAMROM_ROM_SEC_VIO_STA: 0x%x, VIO_ADDR: 0x%x\n",
+ devapc_readl(SRAMROM_ROM_SEC_VIO_STA),
+ devapc_readl(SRAMROM_ROM_SEC_VIO_ADDR));
+ } else {
+ INFO("SRAMROM violation is not triggered\n");
+ }
+
+ return sramrom;
+}
+
+unsigned int devapc_perm_get(int type, int domain, int index)
+{
+ int d = domain; /* domain id */
+ int reg = index / MOD_NO_IN_1_DEVAPC; /* register num */
+ unsigned int value = 0xdeadbeaf;
+
+ INFO("[INFRA] default value is 0x%x\n", value);
+ if (type == E_DAPC_INFRA_SLAVE) {
+ if (index > SLAVE_INFRA_MAX_INDEX)
+ INFO("[INFRA] slave index out of range\n");
+ else if (d > E_DOMAIN_15)
+ INFO("[INFRA] domain id out of range\n");
+ else {
+ value = devapc_readl(DEVAPC_SYS0_D0_APC_0 + 0x40 * d + reg * 4);
+ INFO("[INFRA] SYS0_D%d_APC_%d = 0x%x\n", d, reg, value);
+ }
+ } else if (type == E_DAPC_SRAMROM_SLAVE) {
+ if (index > SLAVE_SRAMROM_MAX_INDEX)
+ INFO("[SRAMROM] slave index out of range\n");
+ else if (d > E_DOMAIN_8)
+ INFO("[SRAMROM] domain id out of range\n");
+ else {
+ value = devapc_readl(DEVAPC_SYS1_D0_APC_0 + 0x40 * d + reg * 4);
+ INFO("[SRAMROM] SYS1_D%d_APC_%d = 0x%x\n", d, reg, value);
+ }
+ } else if (type == E_DAPC_MD_SLAVE) {
+ if (index > SLAVE_MD_MAX_INDEX)
+ INFO("[MD] slave index out of range\n");
+ else if (d > E_DOMAIN_3)
+ INFO("[MD] domain id out of range\n");
+ else {
+ value = devapc_readl(DEVAPC_SYS2_D0_APC_0 + 0x40 * d + reg * 4);
+ INFO("[MD] SYS2_D%d_APC_%d = 0x%x\n", d, reg, value);
+ }
+ } else {
+ dump_infra_apc();
+ dump_sramrom_apc();
+ dump_md_apc();
+
+// INFO("%s: dump PMS(DEVAPC) reg:\n", __func__);
+// dump_pms_info();
+ }
+
+ return value;
+}
+
+void tz_dapc_sec_init(void)
+{
+ //nothing
+}
+
+void tz_dapc_sec_postinit(void)
+{
+ //nothing
+}
+
+void tz_apc_common_init(void)
+{
+ devapc_init();
+}
+
+void tz_apc_common_postinit(void)
+{
+ //nothing
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/main.c b/src/bsp/trustzone/teeloader/mt2731/src/main.c
new file mode 100644
index 0000000..f96ef0c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/main.c
@@ -0,0 +1,85 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//#include "device_apc.h"
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+#include "platform.h"
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+ return ATF_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg, unsigned long boot_reason)
+{
+ atf_arg->bootarg_loc = 0;
+ atf_arg->bootarg_size = 0;
+ atf_arg->bl33_start_addr = BL33;
+ atf_arg->tee_info_addr = ATF_INIT_ARG_ADDR;
+ atf_arg->boot_reason = boot_reason;
+}
+
+int teeloader_main(unsigned long bl33_addr, unsigned long boot_reason)
+{
+ u32 tee_addr = 0;
+ mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+
+ // Force to 32-bit
+ boot_reason &= 0xffffffff;
+ set_atf_parameters(atf_arg, boot_reason);
+
+ /* marked because no device APC support */
+ //device_APC_dom_setup();
+ trustzone_pre_init();
+
+#if CFG_TEE_SUPPORT
+ tee_addr = TRUSTEDOS_ENTRYPOINT;
+#endif
+ /* set tee entry address */
+ tee_set_entry(tee_addr);
+ tee_set_hwuid();
+ tee_set_msg_auth_key();
+
+ trustzone_post_init();
+ trustzone_jump(BL31, BL33, tee_addr);
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/print.c b/src/bsp/trustzone/teeloader/mt2731/src/print.c
new file mode 100644
index 0000000..34622c7
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+ uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+ while (*s) {
+ if (*s == '\n')
+ outchar('\r');
+ outchar(*s++);
+ }
+}
+
+static void outdec(unsigned long n)
+{
+ if (n >= 10) {
+ outdec(n / 10);
+ n %= 10;
+ }
+ outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+ if (depth)
+ depth--;
+
+ if ((n & ~0xf) || depth) {
+ outhex(n >> 4, depth);
+ n &= 0xf;
+ }
+
+ if (n < 10) {
+ outchar((unsigned char)(n + '0'));
+ } else {
+ outchar((unsigned char)(n - 10 + 'A'));
+ }
+}
+
+void vprint(char *fmt, va_list vl)
+{
+ unsigned char c;
+ unsigned int reg = 1; /* argument register number (32-bit) */
+
+ while (*fmt) {
+ c = *fmt++;
+ switch (c) {
+ case '%':
+ c = *fmt++;
+ switch (c) {
+ case 'x':
+ outhex(va_arg(vl, unsigned long), 0);
+ break;
+ case 'B':
+ outhex(va_arg(vl, unsigned long), 2);
+ break;
+ case 'H':
+ outhex(va_arg(vl, unsigned long), 4);
+ break;
+ case 'X':
+ outhex(va_arg(vl, unsigned long), 8);
+ break;
+ case 'l':
+ if (*fmt == 'l' && *(fmt + 1) == 'x') {
+ u32 ltmp;
+ u32 htmp;
+
+ ltmp = va_arg(vl, unsigned int);
+ htmp = va_arg(vl, unsigned int);
+
+ outhex(htmp, 8);
+ outhex(ltmp, 8);
+ fmt += 2;
+ }
+ break;
+ case 'd':
+ {
+ long l;
+
+ l = va_arg(vl, long);
+ if (l < 0) {
+ outchar('-');
+ l = -l;
+ }
+ outdec((unsigned long)l);
+ }
+ break;
+ case 'u':
+ outdec(va_arg(vl, unsigned long));
+ break;
+ case 's':
+ outstr((const unsigned char *)
+ va_arg(vl, char *));
+ break;
+ case '%':
+ outchar('%');
+ break;
+ case 'c':
+ c = va_arg(vl, int);
+ outchar(c);
+ break;
+ default:
+ outchar(' ');
+ break;
+ }
+ reg++; /* one argument uses 32-bit register */
+ break;
+ case '\r':
+ if (*fmt == '\n')
+ fmt++;
+ c = '\n';
+ // fall through
+ case '\n':
+ outchar('\r');
+ // fall through
+ default:
+ outchar(c);
+ }
+ }
+}
+
+void print(char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vprint(fmt, args);
+ va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c b/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c
new file mode 100644
index 0000000..59419d8
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/seclib.c
@@ -0,0 +1,100 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "hacc_export.h"
+#include "string.h"
+#include "print.h"
+
+/**************************************************************************
+ * DEBUG FUNCTIONS
+ **************************************************************************/
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+#define HRID (0x10206140UL)
+#define SOC_DATA (0x08000000UL)
+#define HW_DATA_SIZE (0x4UL)
+
+#define MOD "[SECLIB]"
+
+int seclib_get_key(u32 hwaddr, u8 *key, u32 key_size, int index)
+{
+ u32 hwdata[HW_DATA_SIZE] = {0};
+ int i = 0;
+
+ if (key_size != sizeof(hwdata))
+ {
+ return -1;
+ }
+ for (i = 0; i < HW_DATA_SIZE; i++)
+ {
+ hwdata[i] = READ_REGISTER_UINT32(hwaddr + (i * sizeof(u32)));
+ }
+ if (0 != seclib_get_data_key((u8 *)hwdata, key_size, (u8 *)key, index))
+ {
+ return -1;
+ }
+ DBG_MSG("%s HWDATA : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, hwdata[0], hwdata[1], hwdata[2], hwdata[3]);
+
+ return 0;
+}
+
+int seclib_get_hrid_key(u32 *key, u32 key_size)
+{
+ u32 hrkey[HW_DATA_SIZE] = {0};
+
+ if (0 != seclib_get_key(HRID, (u8 *)hrkey, sizeof(hrkey), 1))
+ {
+ return -1;
+ }
+ key[0]=hrkey[0];
+ key[1]=hrkey[1];
+
+ return 0;
+}
+
+int seclib_get_hwid_key(u8 *key, u32 key_size)
+{
+ return seclib_get_key(SOC_DATA, key, key_size, 2);
+}
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c
new file mode 100644
index 0000000..d7e006b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_emi_mpu.c
@@ -0,0 +1,267 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "tz_emi_reg.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define readl(addr) (__raw_readl(addr))
+#define writel(b,addr) __raw_writel(b,addr)
+#define IOMEM(reg) (reg)
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned long start, unsigned long end, int region, unsigned int access_permission)
+{
+ int ret = 0;
+
+ if (end <= start)
+ {
+ DBG_MSG("%s, Invalid address! End address should larger than start address.\n", MOD);
+ return -1;
+ }
+
+
+ if((end >> 31) && !(start >> 31))
+ {
+ DBG_MSG("%s, Invalid address! MPU region should not across 32bit. Please divide the memory into two regions.\n", MOD);
+ return -1;
+ }
+
+ if ((readl(PERIAXI_BUS_CTL3) & PERISYS_4G_SUPPORT) == 0)
+ {
+ start = start - EMI_PHY_OFFSET;
+ end = end - EMI_PHY_OFFSET;
+ DBG_MSG("%s, MPU 2GB mode.\n", MOD);
+ }
+ else
+ DBG_MSG("%s, MPU 4GB mode.\n", MOD);
+
+ /*Address 64KB alignment*/
+ start = start >> 16;
+ end = end >> 16;
+
+ switch (region) {
+ case 0:
+ writel(0, EMI_MPU_APC0);
+ writel(start, EMI_MPU_SA0);
+ writel(end, EMI_MPU_EA0);
+ writel(access_permission, EMI_MPU_APC0);
+ break;
+
+ case 1:
+ writel(0, EMI_MPU_APC1);
+ writel(start, EMI_MPU_SA1);
+ writel(end, EMI_MPU_EA1);
+ writel(access_permission, EMI_MPU_APC1);
+ break;
+
+ case 2:
+ writel(0, EMI_MPU_APC2);
+ writel(start, EMI_MPU_SA2);
+ writel(end, EMI_MPU_EA2);
+ writel(access_permission, EMI_MPU_APC2);
+ break;
+
+ case 3:
+ writel(0, EMI_MPU_APC3);
+ writel(start, EMI_MPU_SA3);
+ writel(end, EMI_MPU_EA3);
+ writel(access_permission, EMI_MPU_APC3);
+ break;
+
+ case 4:
+ writel(0, EMI_MPU_APC4);
+ writel(start, EMI_MPU_SA4);
+ writel(end, EMI_MPU_EA4);
+ writel(access_permission, EMI_MPU_APC4);
+ break;
+
+ case 5:
+ writel(0, EMI_MPU_APC5);
+ writel(start, EMI_MPU_SA5);
+ writel(end, EMI_MPU_EA5);
+ writel(access_permission, EMI_MPU_APC5);
+ break;
+
+ case 6:
+ writel(0, EMI_MPU_APC6);
+ writel(start, EMI_MPU_SA6);
+ writel(end, EMI_MPU_EA6);
+ writel(access_permission, EMI_MPU_APC6);
+ break;
+
+ case 7:
+ writel(0, EMI_MPU_APC7);
+ writel(start, EMI_MPU_SA7);
+ writel(end, EMI_MPU_EA7);
+ writel(access_permission, EMI_MPU_APC7);
+ break;
+
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+/* sample code for scenario as below: */
+/* mpu region2: 0x40000000 - 0xe0000000 (2.5GB) is secure RW and non-secure RW for domain 0, 3.*/
+/* mpu region3: 0xe0000000 - 0xe0080000 (512K) is secure RW and non-secure RW for domain 0, 2, 3.*/
+/* mpu region4: 0xe0080000 - 0xe0880000 (8M) is secure and non-secure RW for domain 2, 3.*/
+/* mpu region5: 0xe0880000 - 0xec880000 (384M) is secure RW and non-secure RW for domain 1, 2, 3.*/
+/* mpu region6: 0xec880000 - 0xec8e0000 (384K) is secure RW and non-secure RW for domain 0, 1, 3.*/
+/* mpu region7: 0xec8e0000 - 0xf48e0000 (128M) is secure RW for domain 0, 3.*/
+
+void tz_emi_mpu_init_2(void)
+{
+ int ret = 0;
+ unsigned int sec_mem_mpu_attr;
+
+ /*region2 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0x40000000, /*START_ADDR*/
+ 0xe0000000, /*END_ADDR*/
+ 2, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region3 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0xe0000000, /*START_ADDR*/
+ 0xe0080000, /*END_ADDR*/
+ 3, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region4 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xe0080000, /*START_ADDR*/
+ 0xe0880000, /*END_ADDR*/
+ 4, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region5 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_DENY_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xe0880000, /*START_ADDR*/
+ 0xec880000, /*END_ADDR*/
+ 5, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region6 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_RW, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_RW, TZ_MPU_SEC_RW_NSEC_RW);
+ ret += emi_mpu_set_region_protection(0xec880000, /*START_ADDR*/
+ 0xec8e0000, /*END_ADDR*/
+ 6, /*region*/
+ sec_mem_mpu_attr);
+
+ /*region7 mpu*/
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ ret += emi_mpu_set_region_protection(0xec8e0000, /*START_ADDR*/
+ 0xf48e0000, /*END_ADDR*/
+ 7, /*region*/
+ sec_mem_mpu_attr);
+
+ if(ret)
+ DBG_MSG("%s MPU error!!\n", MOD);
+
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+ int ret = 0;
+ unsigned int sec_mem_mpu_attr;
+ unsigned int sec_mem_phy_start, sec_mem_phy_end;
+
+ /* Caculate start/end address */
+ sec_mem_phy_start = start_add;
+ sec_mem_phy_end = end_addr;
+
+ switch(mpu_region)
+ {
+ case SECURE_OS_MPU_REGION_ID:
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ break;
+
+ case ATF_MPU_REGION_ID:
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(TZ_MPU_SEC_RW_NSEC_DENY, \
+ TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_DENY_NSEC_DENY, TZ_MPU_SEC_RW_NSEC_DENY);
+ break;
+
+ default:
+ DBG_MSG("%s Warning - MPU region '%d' is not supported for preloader!\n", MOD, mpu_region);
+ return;
+ }
+
+ DBG_MSG("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+ ret = emi_mpu_set_region_protection(sec_mem_phy_start, /*START_ADDR*/
+ sec_mem_phy_end, /*END_ADDR*/
+ mpu_region, /*region*/
+ sec_mem_mpu_attr);
+
+ if(ret)
+ {
+ DBG_MSG("%s MPU error!!\n", MOD);
+ }
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c
new file mode 100644
index 0000000..ba5313a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_init.c
@@ -0,0 +1,256 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "platform.h"
+#include "print.h"
+#include "seclib.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_emi_mpu.h"
+#include "tz_init.h"
+#include "device_apc.h"
+#include "tz_mem.h"
+#if CFG_TRUSTONIC_TEE_SUPPORT
+#include "tz_tbase.h"
+#endif
+
+/**************************************************************************
+ * DEBUG FUNCTIONS
+ **************************************************************************/
+#define MOD "[TZ_INIT]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#define DBG_INFO(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#endif
+
+/**************************************************************************
+ * MACROS
+ **************************************************************************/
+#define TEE_MEM_ALIGNMENT (0x1000U) //4K Alignment
+#define TEE_ENABLE_VERIFY (1U)
+
+/**************************************************************************
+ * EXTERNAL FUNCTIONS
+ **************************************************************************/
+extern void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region);
+extern void tz_dapc_sec_init(void);
+extern void tz_dapc_sec_postinit(void);
+
+/**************************************************************************
+ * INTERNAL VARIABLES
+ **************************************************************************/
+static u32 tee_entry_addr = 0;
+static u8 g_hwuid[16];
+static u8 g_hwuid_initialized = 0;
+static u32 msg_auth_key[8];
+
+/**************************************************************************
+ * INTERNAL FUNCTIONS
+ **************************************************************************/
+
+static u64 trustzone_get_atf_init_param_addr(void)
+{
+ return ATF_INIT_ARG_ADDR;
+}
+
+static u32 tee_secmem_size = 0;
+static u32 tee_secmem_start = 0;
+static u32 atf_log_buf_start = 0;
+
+void tee_set_entry(u32 addr)
+{
+ tee_entry_addr = addr;
+
+ DBG_MSG("%s TEE start entry : 0x%x\n", MOD, tee_entry_addr);
+}
+
+void tee_set_hwuid(void)
+{
+ atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[0], g_hwuid[1], g_hwuid[2], g_hwuid[3]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[4], g_hwuid[5], g_hwuid[6], g_hwuid[7]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[8], g_hwuid[9], g_hwuid[10], g_hwuid[11]);
+ DBG_MSG("%s HWID : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, g_hwuid[12], g_hwuid[13], g_hwuid[14], g_hwuid[15]);
+ memcpy(teearg->hwuid, g_hwuid, sizeof(g_hwuid));
+ g_hwuid_initialized = 1;
+}
+
+int tee_get_hwuid(u8 *id, u32 size)
+{
+ int ret = 0;
+
+ if (!g_hwuid_initialized)
+ {
+ ret = seclib_get_hwid_key(g_hwuid, sizeof(g_hwuid));
+ if(ret != 0)
+ return ret;
+ }
+
+ memcpy(id, g_hwuid, size);
+
+ return ret;
+}
+
+void tee_set_msg_auth_key(void)
+{
+ int i;
+ atf_arg_t_ptr teearg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ seclib_get_msg_auth_key((unsigned char *) msg_auth_key, 32);
+
+ DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[0], msg_auth_key[1], msg_auth_key[2], msg_auth_key[3]);
+ DBG_MSG("%s msg_auth_key : 0x%x, 0x%x, 0x%x, 0x%x\n", MOD, msg_auth_key[4], msg_auth_key[5], msg_auth_key[6], msg_auth_key[7]);
+
+ memcpy(teearg->msg_auth_key, msg_auth_key, sizeof(msg_auth_key));
+}
+
+static void tee_sec_config(void)
+{
+ u32 atf_entry_addr = BL31;
+
+#if CFG_TEE_SUPPORT
+#if CFG_TEE_SECURE_MEM_PROTECTED
+ /* memory protection for TEE */
+ u32 secmem_end_addr = tee_entry_addr + tee_secmem_size - 1;
+
+ tz_sec_mem_init(tee_entry_addr, secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+ DBG_MSG("%s set secure memory protection : 0x%x, 0x%x (%d)\n", MOD, tee_entry_addr,
+ secmem_end_addr, SECURE_OS_MPU_REGION_ID);
+#endif
+#endif
+
+ /* memory protection for ATF */
+ atf_entry_addr = atf_entry_addr & ~(EMI_MPU_ALIGNMENT - 1);
+ u32 atf_end_addr = atf_entry_addr + BL31_SIZE - 1;
+
+ DBG_MSG("%s ATF entry addr, aligned addr : 0x%x, 0x%x\n", MOD, BL31, atf_entry_addr);
+
+ tz_sec_mem_init(atf_entry_addr, atf_end_addr, ATF_MPU_REGION_ID);
+ DBG_MSG("%s set ATF memory protection : 0x%x, 0x%x (%d)\n", MOD, atf_entry_addr,
+ atf_end_addr, ATF_MPU_REGION_ID);
+}
+
+void trustzone_pre_init(void)
+{
+#if CFG_ATF_LOG_SUPPORT
+ atf_log_buf_start = CFG_ATF_LOG_BUFFER_ADDR;
+#endif
+
+#if CFG_TEE_SUPPORT
+ tee_secmem_size = CFG_TEE_SECMEM_SIZE;
+#endif
+ tz_apc_common_init();
+}
+
+void trustzone_post_init(void)
+{
+ atf_arg_t_ptr atf_init_arg = (atf_arg_t_ptr)(void *)trustzone_get_atf_init_param_addr();
+
+ atf_init_arg->atf_magic = ATF_BOOTCFG_MAGIC;
+ atf_init_arg->tee_entry = tee_entry_addr;
+ atf_init_arg->tee_boot_arg_addr = TEE_BOOT_ARG_ADDR;
+ seclib_get_hrid_key(atf_init_arg->HRID, sizeof(atf_init_arg->HRID));
+ atf_init_arg->atf_log_port = 0x11002000;
+ atf_init_arg->atf_log_baudrate = 0xE1000;
+ atf_init_arg->atf_irq_num = 267; /* reserve SPI ID for ATF log */
+ atf_init_arg->devinfo[0] = 0;
+ atf_init_arg->devinfo[1] = 0;
+ atf_init_arg->devinfo[2] = 0xFFFFFFFF;
+ atf_init_arg->devinfo[3] = 0xFFFFFFFF;
+
+ DBG_MSG("%s HRID[0] : 0x%x\n", MOD, atf_init_arg->HRID[0]);
+ DBG_MSG("%s HRID[1] : 0x%x\n", MOD, atf_init_arg->HRID[1]);
+ DBG_MSG("%s atf_log_port : 0x%x\n", MOD, atf_init_arg->atf_log_port);
+ DBG_MSG("%s atf_log_baudrate : 0x%x\n", MOD, atf_init_arg->atf_log_baudrate);
+ DBG_MSG("%s atf_irq_num : %d\n", MOD, atf_init_arg->atf_irq_num);
+
+#if CFG_TRUSTONIC_TEE_SUPPORT
+ tbase_secmem_param_prepare(TEE_PARAMETER_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+ tee_secmem_size);
+ tbase_boot_param_prepare(TEE_BOOT_ARG_ADDR, tee_entry_addr, CFG_TEE_CORE_SIZE,
+ CFG_DRAM_ADDR, CFG_PLATFORM_DRAM_SIZE);
+ atf_init_arg->tee_support = 1;
+#elif CFG_OPTEE_TEE_SUPPORT
+ atf_init_arg->tee_support = 1;
+#else
+ atf_init_arg->tee_support = 0;
+#endif
+
+#if CFG_ATF_LOG_SUPPORT
+ atf_init_arg->atf_log_buf_start = atf_log_buf_start;
+ atf_init_arg->atf_log_buf_size = ATF_LOG_BUFFER_SIZE;
+ atf_init_arg->atf_aee_debug_buf_start = (atf_log_buf_start + ATF_LOG_BUFFER_SIZE - ATF_AEE_BUFFER_SIZE);
+ atf_init_arg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
+#else
+ atf_init_arg->atf_log_buf_start = 0;
+ atf_init_arg->atf_log_buf_size = 0;
+ atf_init_arg->atf_aee_debug_buf_start = 0;
+ atf_init_arg->atf_aee_debug_buf_size = 0;
+#endif
+ DBG_MSG("%s ATF log buffer start : 0x%x\n", MOD, atf_init_arg->atf_log_buf_start);
+ DBG_MSG("%s ATF log buffer size : 0x%x\n", MOD, atf_init_arg->atf_log_buf_size);
+ DBG_MSG("%s ATF aee buffer start : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_start);
+ DBG_MSG("%s ATF aee buffer size : 0x%x\n", MOD, atf_init_arg->atf_aee_debug_buf_size);
+}
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+void trustzone_jump(u32 addr, u32 arg1, u32 arg2)
+{
+ u32 bl31_reserve = 0;
+ jump_atf atf_entry = (void *)addr;
+
+ /* EMI MPU support */
+ tee_sec_config();
+
+#if CFG_TEE_SUPPORT
+ DBG_MSG("%s Jump to ATF, then 0x%x and 0x%x\n", MOD, arg1, arg2);
+#else
+ DBG_MSG("%s Jump to ATF, then jump to bl33 0x%x\n", MOD, arg1);
+#endif
+
+ atf_entry = (jump_atf)BL31;
+ DBG_MSG("[teeloader] teeloader jump to atf!\n");
+ (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c
new file mode 100644
index 0000000..dd49816
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_sec_cfg.c
@@ -0,0 +1,54 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+
+#define MOD "[TZ_SEC_CFG]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern void tz_emi_mpu_init(u32 start, u32 end, u32 mpu_region);
+
+void tz_sec_mem_init(u32 start, u32 end, u32 mpu_region)
+{
+ tz_emi_mpu_init(start, end, mpu_region);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c
new file mode 100644
index 0000000..8e14488
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/security/tz_tbase.c
@@ -0,0 +1,149 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "print.h"
+#include "string.h"
+#include "typedefs.h"
+#include "tz_mem.h"
+#include "tz_tbase.h"
+
+#define MOD "[TZ_TBASE]"
+
+#define TEE_DEBUG
+#ifdef TEE_DEBUG
+#define DBG_MSG(str, ...) do {print(str, ##__VA_ARGS__);} while(0)
+#else
+#define DBG_MSG(str, ...) do {} while(0)
+#endif
+
+extern u32 seclib_get_msg_auth_key(unsigned char *key, unsigned int key_size);
+extern int tee_get_hwuid(u8 *id, u32 size);
+
+/**************************************************************************
+ * EXTERNAL FUNCTIONS
+ **************************************************************************/
+void tbase_secmem_param_prepare(u32 param_addr, u32 tee_entry,
+ u32 tbase_sec_dram_size, u32 tee_smem_size)
+{
+ int ret = 0;
+ sec_mem_arg_t sec_mem_arg;
+ u8 hwuid[16];
+ unsigned char i, *ptmp, tmpbuf;
+
+ ret = tee_get_hwuid(hwuid, 16);
+ if (ret)
+ DBG_MSG("%s hwuid not initialized yet\n", MOD);
+
+ /* Prepare secure memory configuration parameters */
+ sec_mem_arg.magic = SEC_MEM_MAGIC;
+ sec_mem_arg.version = SEC_MEM_VERSION;
+ sec_mem_arg.svp_mem_start = tee_entry + tbase_sec_dram_size;
+ sec_mem_arg.tplay_mem_size = SEC_MEM_TPLAY_MEMORY_SIZE;
+ sec_mem_arg.tplay_mem_start = tee_entry + (tee_smem_size - SEC_MEM_TPLAY_MEMORY_SIZE);
+ sec_mem_arg.tplay_table_size = SEC_MEM_TPLAY_TABLE_SIZE;
+ sec_mem_arg.tplay_table_start = sec_mem_arg.tplay_mem_start - SEC_MEM_TPLAY_TABLE_SIZE;
+ sec_mem_arg.svp_mem_end = sec_mem_arg.tplay_table_start;
+ /* dummy function because of no seclib support */
+ seclib_get_msg_auth_key((unsigned char *) sec_mem_arg.msg_auth_key, 32);
+ /*ptmp = (unsigned char *)sec_mem_arg.msg_auth_key;
+ for(i=0;i<32/2;i++) {
+ tmpbuf = ptmp[i];
+ ptmp[i] = ptmp[31-i];
+ ptmp[31-i] = tmpbuf;
+ }*/
+ sec_mem_arg.rpmb_size = 128*1024; /* 128kx1: minimum size */
+ sec_mem_arg.emmc_rel_wr_sec_c = 1;
+
+#if CFG_TEE_SECURE_MEM_PROTECTED
+ sec_mem_arg.secmem_obfuscation = 1;
+#else
+ sec_mem_arg.secmem_obfuscation = 0;
+#endif
+
+ DBG_MSG("%s sec_mem_arg.magic: 0x%x\n", MOD, sec_mem_arg.magic);
+ DBG_MSG("%s sec_mem_arg.version: 0x%x\n", MOD, sec_mem_arg.version);
+ DBG_MSG("%s sec_mem_arg.svp_mem_start: 0x%x\n", MOD, sec_mem_arg.svp_mem_start);
+ DBG_MSG("%s sec_mem_arg.svp_mem_end: 0x%x\n", MOD, sec_mem_arg.svp_mem_end);
+ DBG_MSG("%s sec_mem_arg.tplay_mem_start: 0x%x\n", MOD, sec_mem_arg.tplay_mem_start);
+ DBG_MSG("%s sec_mem_arg.tplay_mem_size: 0x%x\n", MOD, sec_mem_arg.tplay_mem_size);
+ DBG_MSG("%s sec_mem_arg.tplay_table_start: 0x%x\n", MOD, sec_mem_arg.tplay_table_start);
+ DBG_MSG("%s sec_mem_arg.tplay_table_size: 0x%x\n", MOD, sec_mem_arg.tplay_table_size);
+ DBG_MSG("%s sec_mem_arg.secmem_obfuscation: 0x%x\n", MOD, sec_mem_arg.secmem_obfuscation);
+ DBG_MSG("%s tee_entry_addr: 0x%x\n", MOD, tee_entry);
+ DBG_MSG("%s tee_secmem_size: 0x%x\n", MOD, tee_smem_size);
+ DBG_MSG("%s rpmb_size: 0x%x\n", MOD, sec_mem_arg.rpmb_size);
+ DBG_MSG("%s emmc_rel_wr_sec_c: 0x%x\n", MOD, sec_mem_arg.emmc_rel_wr_sec_c);
+
+ memcpy((void*)param_addr, &sec_mem_arg, sizeof(sec_mem_arg_t));
+}
+
+void tbase_boot_param_prepare(u32 param_addr, u32 tee_entry,
+ u64 tbase_sec_dram_size, u64 dram_base, u64 dram_size)
+{
+ tee_arg_t_ptr teearg = (tee_arg_t_ptr)param_addr;
+
+ /* Prepare TEE boot parameters */
+ teearg->magic = TBASE_BOOTCFG_MAGIC; /* Trustonic's TEE magic number */
+ teearg->length = sizeof(tee_arg_t); /* Trustonic's TEE argument block size */
+ //teearg->version = TBASE_MONITOR_INTERFACE_VERSION; /* Trustonic's TEE argument block version */
+ teearg->dRamBase = dram_base; /* DRAM base address */
+ teearg->dRamSize = dram_size; /* Full DRAM size */
+ teearg->secDRamBase = tee_entry; /* Secure DRAM base address */
+ teearg->secDRamSize = tbase_sec_dram_size; /* Secure DRAM size */
+ teearg->secIRamBase = TEE_SECURE_ISRAM_ADDR; /* Secure SRAM base address */
+ teearg->secIRamSize = TEE_SECURE_ISRAM_SIZE; /* Secure SRAM size */
+ //teearg->conf_mair_el3 = read_mair_el3();
+ //teearg->MSMPteCount = totalPages;
+ //teearg->MSMBase = (u64)registerFileL2;
+ //teearg->gic_distributor_base = TBASE_GIC_DIST_BASE;
+ //teearg->gic_cpuinterface_base = TBASE_GIC_CPU_BASE;
+ //teearg->gic_version = TBASE_GIC_VERSION;
+ teearg->total_number_spi = 256; /* Support total 256 SPIs */
+ teearg->ssiq_number = 247; /* reserve SPI ID 266 for <t-base */
+ //teearg->flags = TBASE_MONITOR_FLAGS;
+
+ DBG_MSG("%s teearg.magic: 0x%x\n", MOD, teearg->magic);
+ DBG_MSG("%s teearg.length: 0x%x\n", MOD, teearg->length);
+ DBG_MSG("%s teearg.dRamBase: 0x%x\n", MOD, teearg->dRamBase);
+ DBG_MSG("%s teearg.dRamSize: 0x%x\n", MOD, teearg->dRamSize);
+ DBG_MSG("%s teearg.secDRamBase: 0x%x\n", MOD, teearg->secDRamBase);
+ DBG_MSG("%s teearg.secDRamSize: 0x%x\n", MOD, teearg->secDRamSize);
+ DBG_MSG("%s teearg.secIRamBase: 0x%x\n", MOD, teearg->secIRamBase);
+ DBG_MSG("%s teearg.secIRamSize: 0x%x\n", MOD, teearg->secIRamSize);
+ DBG_MSG("%s teearg.total_number_spi: %d\n", MOD, teearg->total_number_spi);
+ DBG_MSG("%s teearg.ssiq_number: %d\n", MOD, teearg->ssiq_number);
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/start.s b/src/bsp/trustzone/teeloader/mt2731/src/start.s
new file mode 100644
index 0000000..6559241
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/start.s
@@ -0,0 +1,71 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*
+ * Register use:
+ * x9-x10 Scratch
+ */
+tmp .req x9
+tmp2 .req x10
+
+.section .text.start
+
+.globl _start
+_start:
+/*
+ * Note: MT2731 BL2 is built as aarch32. Tee loader is built as aarch64.
+ * CPU context initialization code is required. 0x240000 is the end of l2$. (not good writing...)
+ */
+ mrs tmp, CurrentEL
+ cmp tmp, #(0b11 << 2)
+ b.ne .Lsetup_el2_or_el3_stack
+
+ /* el3 set secure timer */
+ ldr tmp2, =13000000
+ msr cntfrq_el0, tmp2
+
+ /* el3 enable smp bit */
+ mrs tmp2, s3_1_c15_c2_1
+ orr tmp2, tmp, #(1<<6)
+ msr s3_1_c15_c2_1, tmp2
+
+.Lsetup_el2_or_el3_stack:
+ /* set el2 or el3 stack pointer */
+ ldr tmp2, =0x240000
+ mov sp, tmp2
+
+ b teeloader_main
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/string.c b/src/bsp/trustzone/teeloader/mt2731/src/string.c
new file mode 100644
index 0000000..d916f3c
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/string.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+//---------------------------------------------------------------------------
+int strlen(const char *s)
+{
+ const char *sc;
+
+ for (sc = s; *sc != '\0'; ++sc)
+ {
+ }
+ return sc - s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strcmp(const char *cs, const char *ct)
+{
+ signed char __res;
+
+ while (1)
+ {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ }
+ return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int strncmp(const char *cs, const char *ct, int count)
+{
+ signed char __res = 0;
+
+ while (count)
+ {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ count--;
+ }
+ return __res;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memset(void *s, int c, int count)
+{
+ char *xs = s;
+
+ while (count--)
+ *xs++ = c;
+ return s;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+void * memcpy(void *dest, const void *src, int count)
+{
+ char *tmp = dest;
+ const char *s = src;
+
+ while (count--)
+ *tmp++ = *s++;
+ return dest;
+}
+
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+int memcmp(const void *cs, const void *ct, int count)
+{
+ const unsigned char *su1, *su2;
+ int res = 0;
+
+ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+ if ((res = *su1 - *su2) != 0)
+ break;
+ return res;
+}
+
+void *memmove(void *dst, const void *src, int count)
+{
+ char *_dst = dst;
+ const char *_src = src;
+
+ if (dst == src)
+ return dst;
+
+ if (dst < src)
+ return memcpy(dst, src, count);
+
+ _dst += count;
+ _src += count;
+ while(count--)
+ *--_dst = *--_src;
+
+ return dst;
+}
+//---------------------------------------------------------------------------
diff --git a/src/bsp/trustzone/teeloader/mt2731/src/uart.c b/src/bsp/trustzone/teeloader/mt2731/src/uart.c
new file mode 100644
index 0000000..e93d4dc
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/src/uart.c
@@ -0,0 +1,50 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+ while (!(readl(UART_LSR(UART1_BASE)) & UART_LSR_THRE));
+
+ if (c == '\n')
+ writel((unsigned int)'\r', UART_THR(UART1_BASE));
+
+ writel((unsigned int)c, UART_THR(UART1_BASE));
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt2731/tllink.lds b/src/bsp/trustzone/teeloader/mt2731/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+ . = %BASE_ADDR%;
+ .start ALIGN(4) : {
+ *(.text.start)
+ }
+
+ . = . + 0x01FC;
+ .text ALIGN(4) : {
+ *(.text)
+ *(.text.*)
+ }
+ .rodata ALIGN(4) : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+ .data ALIGN(4) : {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = %BASE_ADDR%-0x100000 ;
+ .bss ALIGN(16) : {
+ _bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ /* make _bss_end as 4 bytes alignment */
+ . = ALIGN(4);
+ _bss_end = .;
+ }
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh b/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt2731/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+ PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+ dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+ cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+ rm ${FILE_DIR}/padding.txt
+fi