[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/bsp/trustzone/teeloader/mt8512/Makefile b/src/bsp/trustzone/teeloader/mt8512/Makefile
new file mode 100644
index 0000000..9879df0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/Makefile
@@ -0,0 +1,57 @@
+CC := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OBJCOPY := ${CROSS_COMPILE}objcopy
+
+LDS = tllink.lds
+
+DIR_INC = ./include
+DIR_SRC = ./src
+DIR_PREBUILT = ./prebuild
+DIR_OBJ = ${TL_RAW_OUT}/obj
+DIR_BIN = ${TL_RAW_OUT}/bin
+
+ASRCS = $(wildcard $(DIR_SRC)/*.s)
+CSRCS = $(wildcard $(DIR_SRC)/*.c)
+CSRCS += \
+ $(DIR_SRC)/drivers/tz_emi_mpu.c \
+ $(DIR_SRC)/drivers/tz_dapc.c
+
+VPATH = $(DIR_SRC):$(DIR_SRC)/drivers
+SRCS = $(ASRCS) $(CSRCS)
+AOBJS = $(patsubst %.s, $(DIR_OBJ)/%.o, $(notdir $(ASRCS)))
+COBJS = $(patsubst %.c, $(DIR_OBJ)/%.o, $(notdir $(CSRCS)))
+SOBJS = $(wildcard $(DIR_PREBUILT)/*.a)
+OBJS = $(AOBJS) $(COBJS) $(SOBJS)
+
+TARGET = teeloader
+BIN_TARGET = $(DIR_BIN)/$(TARGET)
+
+ifeq ($(strip $(TRUSTEDOS_SIZE)),)
+TRUSTEDOS_SIZE := 0
+endif
+all: $(OBJS)
+ @if [ ! -d `dirname $(BIN_TARGET).elf` ] ; then \
+ mkdir -p `dirname $(BIN_TARGET).elf`; \
+ fi
+ sed "s/%BASE_ADDR%/${BASE_ADDR}/g" $(LDS) > $(DIR_OBJ)/$(LDS)
+ $(LD) --start-group $^ --end-group -T$(DIR_OBJ)/$(LDS) -o $(BIN_TARGET).elf
+ -echo "teeloader binary created"
+ $(OBJCOPY) -O binary $(BIN_TARGET).elf $(BIN_TARGET).bin
+ ./zero_padding.sh $(BIN_TARGET).bin ${TL_ALIGN_SIZE}
+
+$(DIR_OBJ)/%.o: %.c
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -I$(DIR_INC) -DBASE_ADDR=${BASE_ADDR} -DTL_ALIGN_SIZE=${TL_ALIGN_SIZE} -DTRUSTEDOS_ENTRYPOINT=${TRUSTEDOS_ENTRYPOINT} -DTRUSTEDOS_SIZE=${TRUSTEDOS_SIZE} -c $(filter %$(patsubst %.o,%.c,$(notdir $@)),$(CSRCS)) -o $@
+
+$(DIR_OBJ)/%.o: %.s
+ @if [ ! -d `dirname $@` ] ; then \
+ mkdir -p `dirname $@`; \
+ fi
+ $(CC) -c $^ -o $@
+
+.PHONY: clean
+clean:
+ -@rm -rf $(DIR_OBJ)/* $(DIR_BIN)/*
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/print.h b/src/bsp/trustzone/teeloader/mt8512/include/print.h
new file mode 100644
index 0000000..1b06fb0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/print.h
@@ -0,0 +1,43 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __PRINT_H__
+#define __PRINT_H__
+
+void tl_printf(char *fmt, ...);
+
+#endif /* __PRINT_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h b/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h
new file mode 100644
index 0000000..9d2a01e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/typedefs.h
@@ -0,0 +1,65 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef unsigned int UINT32;
+typedef volatile unsigned int *P_U32;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned int u32;
+typedef signed int s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h
new file mode 100644
index 0000000..59615c6
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_dapc.h
@@ -0,0 +1,183 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef DEVICE_APC_H
+#define DEVICE_APC_H
+
+#include "typedefs.h"
+
+/* DEVAPC = "DEVAPC"
+ * DEVAPC0 = "DEVAPC_AO_INFRA_PERI"
+ * DEVAPC1 = "DEVAPC_AO_MM"
+ */
+
+#define DEVAPC_BASE (0x10207000U)
+#define DEVAPC0_BASE (0x1000E000U)
+#define DEVAPC1_BASE (0x1001C000U)
+
+/*******************************************************************************
+ * REGISTER ADDRESS DEFINATION
+ ******************************************************************************/
+#define PERM_OFF(x) (0x4 * x)
+
+/* DEVAPC_AO_INFRA_PERI */
+#define DEVAPC0_D0_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0000+PERM_OFF(n)))
+#define DEVAPC0_D1_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0100+PERM_OFF(n)))
+#define DEVAPC0_D2_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0200+PERM_OFF(n)))
+#define DEVAPC0_D3_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0300+PERM_OFF(n)))
+#define DEVAPC0_D4_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0400+PERM_OFF(n)))
+#define DEVAPC0_D5_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0500+PERM_OFF(n)))
+#define DEVAPC0_D6_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0600+PERM_OFF(n)))
+#define DEVAPC0_D7_APC(n) ((volatile unsigned int*)(DEVAPC0_BASE+0x0700+PERM_OFF(n)))
+
+#define DEVAPC0_APC_CON ((volatile unsigned int*)(DEVAPC0_BASE+0x0F00))
+#define DEVAPC0_MAS_DOM_0 ((volatile unsigned int*)(DEVAPC0_BASE+0x0A00))
+#define DEVAPC0_MAS_DOM_1 ((volatile unsigned int*)(DEVAPC0_BASE+0x0A04))
+#define DEVAPC0_MAS_DOM_2 ((volatile unsigned int*)(DEVAPC0_BASE+0x0A08))
+#define DEVAPC0_MAS_SEC_0 ((volatile unsigned int*)(DEVAPC0_BASE+0x0B00))
+
+/* DEVAPC_AO_MM */
+#define DEVAPC1_APC_CON ((volatile unsigned int*)(DEVAPC1_BASE+0x0F00))
+
+/* DEVAPC */
+#define DEVAPC_APC_CON ((volatile unsigned int*)(DEVAPC_BASE+0x0F00))
+
+
+typedef enum {
+ NS_TRANSACTION = 0,
+ S_TRANSACTION,
+} E_TRANSACTION;
+
+typedef enum {
+ DOMAIN_0 = 0,
+ DOMAIN_1,
+ DOMAIN_2,
+ DOMAIN_3,
+ DOMAIN_4,
+ DOMAIN_5,
+ DOMAIN_6,
+ DOMAIN_7,
+} E_DOMAIN;
+
+typedef enum {
+ NO_PROTECTION = 0,
+ SEC_RW_ONLY,
+ SEC_RW_NSEC_R,
+ NOT_ACCESSIBLE,
+} E_SLAVE_PERMISSION;
+
+static inline unsigned int uffs(unsigned int x)
+{
+ unsigned int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+#define reg_read32(reg) (*(volatile u32* const)(reg))
+#define reg_write32(reg,val) ((*(volatile u32* const)(reg)) = (val))
+
+#define reg_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
+#define reg_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
+
+#define reg_set_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ tv &= ~(field); \
+ tv |= ((val) << (uffs((unsigned int)field) - 1)); \
+ reg_write32(reg,tv); \
+ } while(0)
+
+#define reg_get_field(reg,field,val) \
+ do { \
+ volatile unsigned int tv = reg_read32(reg); \
+ val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
+ } while(0)
+
+
+
+typedef enum {
+ MASTER_NFI = 0,
+ MASTER_SSUSB_XHCI = 1,
+ MASTER_PWM = 3,
+ MASTER_MSDC0 = 5,
+ MASTER_MSDC1 = 6,
+} E_MASTER;
+
+
+#define MODULE_TRANSACTION(index, is_secure) (is_secure << index)
+#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)
+
+#define MODULE_DOMAIN(index, domain) (domain << (4 * (index % 8)))
+#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)
+
+#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))
+#define DAPC_SET_SLAVE_PERMISSION(devapc_register, permission) reg_write32(devapc_register, permission)
+
+typedef enum{
+ INFRA_AO_SEJ = 10,
+ INFRA_AO_DEVICE_APC_AO_INFRA_PERI = 14,
+ INFRA_AO_DEVICE_APC_AO_MM = 28,
+ INFRASYS_DEVICE_APC = 39,
+} E_DEVAPC0_SLAVE;
+
+
+void tz_dapc_sec_init(void);
+void tz_dapc_sec_postinit(void);
+void tz_dapc_set_master_transaction(unsigned int master_index , E_TRANSACTION permisssion_control);
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h
new file mode 100644
index 0000000..bdb4801
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_mpu.h
@@ -0,0 +1,23 @@
+#ifndef _EMI_MPU_H_
+#define _EMI_MPU_H_
+
+/* EMI memory protection align 64K */
+#define EMI_MPU_ALIGNMENT 0x10000
+#define EMI_PHY_OFFSET 0x40000000
+#define SEC_PHY_SIZE 0x06000000
+
+#define NO_PROTECTION 0
+#define SEC_RW 1
+#define SEC_RW_NSEC_R 2
+#define SEC_RW_NSEC_W 3
+#define SEC_R_NSEC_R 4
+#define FORBIDDEN 5
+
+#define SECURE_OS_MPU_REGION_ID 0
+#define ATF_MPU_REGION_ID 1
+
+#define LOCK 1
+#define UNLOCK 0
+#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) ((((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | ((((d7) << 9) | ((d6) << 6) | ((d5) << 3) | (d4)) << 16) | (lock << 15))
+
+#endif
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h
new file mode 100644
index 0000000..622d7f2
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_emi_reg.h
@@ -0,0 +1,276 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#define IO_PHYS 0x10000000
+#define EMI_BASE (IO_PHYS + 0x00203000)
+
+/*EMI PSRAM (NOR) and DRAM control registers*/
+#define EMI_CONA ((P_U32)(EMI_BASE+0x0000)) /* EMI control register for bank 0 */
+#define EMI_CONB ((P_U32)(EMI_BASE+0x0008)) /* EMI control register for bank 1 */
+#define EMI_CONC ((P_U32)(EMI_BASE+0x0010)) /* EMI control register for bank 2 */
+#define EMI_COND ((P_U32)(EMI_BASE+0x0018)) /* EMI control register for bank 3 */
+#define EMI_CONE ((P_U32)(EMI_BASE+0x0020)) /* EMI control register for bank 0 */
+#define EMI_CONF ((P_U32)(EMI_BASE+0x0028)) /* EMI control register for bank 1 */
+#define EMI_CONG ((P_U32)(EMI_BASE+0x0030)) /* EMI control register for bank 0 */
+#define EMI_CONH ((P_U32)(EMI_BASE+0x0038)) /* EMI control register for bank 1 */
+#define EMI_CONI ((P_U32)(EMI_BASE+0x0040)) /* EMI control register 0 for Mobile-RAM */
+#define EMI_CONJ ((P_U32)(EMI_BASE+0x0048)) /* EMI control register 1 for Mobile-RAM */
+#define EMI_CONK ((P_U32)(EMI_BASE+0x0050)) /* EMI control register 2 for Mobile-RAM */
+#define EMI_CONL ((P_U32)(EMI_BASE+0x0058)) /* EMI control register 3 for Mobile-RAM */
+#define EMI_CONM ((P_U32)(EMI_BASE+0x0060))
+#define EMI_CONN ((P_U32)(EMI_BASE+0x0068))
+#define CAL_EN (1 << 8)
+#define EMI_GENA ((P_U32)(EMI_BASE+0x0070))
+#define EMI_REMAP EMI_GENA
+#define EMI_DRCT ((P_U32)(EMI_BASE+0x0078))
+#define EMI_DDRV ((P_U32)(EMI_BASE+0x0080))
+#define EMI_GEND ((P_U32)(EMI_BASE+0x0088))
+#define EMI_PPCT ((P_U32)(EMI_BASE+0x0090)) /* EMI Performance and Power Control Register */
+
+#define EMI_DLLV ((P_U32)(EMI_BASE+0x00A0))
+
+#define EMI_DFTC ((P_U32)(EMI_BASE+0x00F0))
+#define EMI_DFTD ((P_U32)(EMI_BASE+0x00F8))
+
+/* EMI bandwith filter and MPU control registers */
+#define EMI_ARBA ((P_U32)(EMI_BASE+0x0100))
+#define EMI_ARBB ((P_U32)(EMI_BASE+0x0108))
+#define EMI_ARBC ((P_U32)(EMI_BASE+0x0110))
+#define EMI_ARBD ((P_U32)(EMI_BASE+0x0118))
+#define EMI_ARBE ((P_U32)(EMI_BASE+0x0120))
+#define EMI_ARBF ((P_U32)(EMI_BASE+0x0128))
+#define EMI_ARBG ((P_U32)(EMI_BASE+0x0130))
+
+#define EMI_SLCT ((P_U32)(EMI_BASE+0x0150))
+#define EMI_ABCT ((P_U32)(EMI_BASE+0x0158))
+
+/* EMI Memory Protect Unit */
+#define EMI_MPUA ((P_U32)(EMI_BASE+0x0160))
+#define EMI_MPUB ((P_U32)(EMI_BASE+0x0168))
+#define EMI_MPUC ((P_U32)(EMI_BASE+0x0170))
+#define EMI_MPUD ((P_U32)(EMI_BASE+0x0178))
+#define EMI_MPUE ((P_U32)(EMI_BASE+0x0180))
+#define EMI_MPUF ((P_U32)(EMI_BASE+0x0188))
+#define EMI_MPUG ((P_U32)(EMI_BASE+0x0190))
+#define EMI_MPUH ((P_U32)(EMI_BASE+0x0198))
+
+#define EMI_MPUI ((P_U32)(EMI_BASE+0x01A0))
+#define EMI_MPUI_2ND ((P_U32)(EMI_BASE+0x01A4))
+#define EMI_MPUJ ((P_U32)(EMI_BASE+0x01A8))
+#define EMI_MPUJ_2ND ((P_U32)(EMI_BASE+0x01AC))
+#define EMI_MPUK ((P_U32)(EMI_BASE+0x01B0))
+#define EMI_MPUK_2ND ((P_U32)(EMI_BASE+0x01B4))
+#define EMI_MPUL ((P_U32)(EMI_BASE+0x01B8))
+#define EMI_MPUL_2ND ((P_U32)(EMI_BASE+0x01BC))
+#define EMI_MPUM ((P_U32)(EMI_BASE+0x01C0))
+#define EMI_MPUN ((P_U32)(EMI_BASE+0x01C8))
+#define EMI_MPUO ((P_U32)(EMI_BASE+0x01D0))
+#define EMI_MPUP ((P_U32)(EMI_BASE+0x01D8))
+#define EMI_MPUQ ((P_U32)(EMI_BASE+0x01E0))
+#define EMI_MPUR ((P_U32)(EMI_BASE+0x01E8))
+#define EMI_MPUS ((P_U32)(EMI_BASE+0x01F0))
+#define EMI_MPUT ((P_U32)(EMI_BASE+0x01F8))
+
+#define EMI_MPUA2 ((P_U32)(EMI_BASE+0x0260))
+#define EMI_MPUB2 ((P_U32)(EMI_BASE+0x0268))
+#define EMI_MPUC2 ((P_U32)(EMI_BASE+0x0270))
+#define EMI_MPUD2 ((P_U32)(EMI_BASE+0x0278))
+#define EMI_MPUE2 ((P_U32)(EMI_BASE+0x0280))
+#define EMI_MPUF2 ((P_U32)(EMI_BASE+0x0288))
+#define EMI_MPUG2 ((P_U32)(EMI_BASE+0x0290))
+#define EMI_MPUH2 ((P_U32)(EMI_BASE+0x0298))
+#define EMI_MPUI2 ((P_U32)(EMI_BASE+0x02A0))
+#define EMI_MPUI2_2ND ((P_U32)(EMI_BASE+0x02A4))
+#define EMI_MPUJ2 ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_MPUJ2_2ND ((P_U32)(EMI_BASE+0x02AC))
+#define EMI_MPUK2 ((P_U32)(EMI_BASE+0x02B0))
+#define EMI_MPUK2_2ND ((P_U32)(EMI_BASE+0x02B4))
+#define EMI_MPUL2 ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_MPUL2_2ND ((P_U32)(EMI_BASE+0x02BC))
+#define EMI_MPUM2 ((P_U32)(EMI_BASE+0x02C0))
+#define EMI_MPUN2 ((P_U32)(EMI_BASE+0x02C8))
+#define EMI_MPUO2 ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_MPUP2 ((P_U32)(EMI_BASE+0x02D8))
+#define EMI_MPUQ2 ((P_U32)(EMI_BASE+0x02E0))
+#define EMI_MPUR2 ((P_U32)(EMI_BASE+0x02E8))
+#define EMI_MPUU2 ((P_U32)(EMI_BASE+0x0300))
+#define EMI_MPUY2 ((P_U32)(EMI_BASE+0x0320))
+
+/* EMI IO delay, driving and MISC control registers */
+#define EMI_IDLA ((P_U32)(EMI_BASE+0x0200))
+#define EMI_IDLB ((P_U32)(EMI_BASE+0x0208))
+#define EMI_IDLC ((P_U32)(EMI_BASE+0x0210))
+#define EMI_IDLD ((P_U32)(EMI_BASE+0x0218))
+#define EMI_IDLE ((P_U32)(EMI_BASE+0x0220))
+#define EMI_IDLF ((P_U32)(EMI_BASE+0x0228))
+#define EMI_IDLG ((P_U32)(EMI_BASE+0x0230))
+#define EMI_IDLH ((P_U32)(EMI_BASE+0x0238))
+#define EMI_IDLI ((P_U32)(EMI_BASE+0x0240)) // IO input delay (DQS0 ~ DQS4)
+#define EMI_IDLJ ((P_U32)(EMI_BASE+0x0248))
+#define EMI_IDLK ((P_U32)(EMI_BASE+0x0250))
+
+#define EMI_ODLA ((P_U32)(EMI_BASE+0x0258))
+#define EMI_ODLB ((P_U32)(EMI_BASE+0x0260))
+#define EMI_ODLC ((P_U32)(EMI_BASE+0x0268))
+#define EMI_ODLD ((P_U32)(EMI_BASE+0x0270))
+#define EMI_ODLE ((P_U32)(EMI_BASE+0x0278))
+#define EMI_ODLF ((P_U32)(EMI_BASE+0x0280))
+#define EMI_ODLG ((P_U32)(EMI_BASE+0x0288))
+
+#define EMI_DUTA ((P_U32)(EMI_BASE+0x0290))
+#define EMI_DUTB ((P_U32)(EMI_BASE+0x0298))
+#define EMI_DUTC ((P_U32)(EMI_BASE+0x02A0))
+
+#define EMI_DRVA ((P_U32)(EMI_BASE+0x02A8))
+#define EMI_DRVB ((P_U32)(EMI_BASE+0x02B0))
+
+#define EMI_IOCL ((P_U32)(EMI_BASE+0x02B8))
+#define EMI_IOCM ((P_U32)(EMI_BASE+0x02C0)) //IvanTseng, for 4T mode
+#define EMI_IODC ((P_U32)(EMI_BASE+0x02C8))
+
+#define EMI_ODTA ((P_U32)(EMI_BASE+0x02D0))
+#define EMI_ODTB ((P_U32)(EMI_BASE+0x02D8))
+
+/* EMI auto-tracking control registers */
+#define EMI_DQSA ((P_U32)(EMI_BASE+0x0300))
+#define EMI_DQSB ((P_U32)(EMI_BASE+0x0308))
+#define EMI_DQSC ((P_U32)(EMI_BASE+0x0310))
+#define EMI_DQSD ((P_U32)(EMI_BASE+0x0318))
+
+
+#define EMI_DQSE ((P_U32)(EMI_BASE+0x0320))
+#define EMI_DQSV ((P_U32)(EMI_BASE+0x0328))
+
+#define EMI_CALA ((P_U32)(EMI_BASE+0x0330))
+#define EMI_CALB ((P_U32)(EMI_BASE+0x0338))
+#define EMI_CALC ((P_U32)(EMI_BASE+0x0340))
+#define EMI_CALD ((P_U32)(EMI_BASE+0x0348))
+
+
+#define EMI_CALE ((P_U32)(EMI_BASE+0x0350)) //DDR data auto tracking control
+#define EMI_CALF ((P_U32)(EMI_BASE+0x0358))
+#define EMI_CALG ((P_U32)(EMI_BASE+0x0360)) //DDR data auto tracking control
+#define EMI_CALH ((P_U32)(EMI_BASE+0x0368))
+
+#define EMI_CALI ((P_U32)(EMI_BASE+0x0370))
+#define EMI_CALJ ((P_U32)(EMI_BASE+0x0378))
+#define EMI_CALK ((P_U32)(EMI_BASE+0x0380))
+#define EMI_CALL ((P_U32)(EMI_BASE+0x0388))
+
+
+#define EMI_CALM ((P_U32)(EMI_BASE+0x0390))
+#define EMI_CALN ((P_U32)(EMI_BASE+0x0398))
+
+#define EMI_CALO ((P_U32)(EMI_BASE+0x03A0))
+#define EMI_CALP ((P_U32)(EMI_BASE+0x03A8))
+
+#define EMI_DUCA ((P_U32)(EMI_BASE+0x03B0))
+#define EMI_DUCB ((P_U32)(EMI_BASE+0x03B8))
+#define EMI_DUCC ((P_U32)(EMI_BASE+0x03C0))
+#define EMI_DUCD ((P_U32)(EMI_BASE+0x03C8))
+#define EMI_DUCE ((P_U32)(EMI_BASE+0x03D0))
+
+/* EMI bus monitor control registers */
+#define EMI_BMEN ((P_U32)(EMI_BASE+0x0400))
+#define EMI_BCNT ((P_U32)(EMI_BASE+0x0408))
+#define EMI_TACT ((P_U32)(EMI_BASE+0x0410))
+#define EMI_TSCT ((P_U32)(EMI_BASE+0x0418))
+#define EMI_WACT ((P_U32)(EMI_BASE+0x0420))
+#define EMI_WSCT ((P_U32)(EMI_BASE+0x0428))
+#define EMI_BACT ((P_U32)(EMI_BASE+0x0430))
+#define EMI_BSCT ((P_U32)(EMI_BASE+0x0438))
+#define EMI_MSEL ((P_U32)(EMI_BASE+0x0440))
+#define EMI_TSCT2 ((P_U32)(EMI_BASE+0x0448))
+#define EMI_TSCT3 ((P_U32)(EMI_BASE+0x0450))
+#define EMI_WSCT2 ((P_U32)(EMI_BASE+0x0458))
+#define EMI_WSCT3 ((P_U32)(EMI_BASE+0x0460))
+#define EMI_MSEL2 ((P_U32)(EMI_BASE+0x0468))
+#define EMI_MSEL3 ((P_U32)(EMI_BASE+0x0470))
+#define EMI_MSEL4 ((P_U32)(EMI_BASE+0x0478))
+#define EMI_MSEL5 ((P_U32)(EMI_BASE+0x0480))
+#define EMI_MSEL6 ((P_U32)(EMI_BASE+0x0488))
+#define EMI_MSEL7 ((P_U32)(EMI_BASE+0x0490))
+#define EMI_MSEL8 ((P_U32)(EMI_BASE+0x0498))
+#define EMI_MSEL9 ((P_U32)(EMI_BASE+0x04A0))
+#define EMI_MSEL10 ((P_U32)(EMI_BASE+0x04A8))
+#define EMI_BMID0 ((P_U32)(EMI_BASE+0x04B0))
+#define EMI_BMID1 ((P_U32)(EMI_BASE+0x04B8))
+#define EMI_BMID2 ((P_U32)(EMI_BASE+0x04C0))
+#define EMI_BMID3 ((P_U32)(EMI_BASE+0x04C8))
+#define EMI_BMID4 ((P_U32)(EMI_BASE+0x04D0))
+#define EMI_BMID5 ((P_U32)(EMI_BASE+0x04D8))
+
+#define EMI_TTYPE1 ((P_U32)(EMI_BASE+0x0500))
+#define EMI_TTYPE2 ((P_U32)(EMI_BASE+0x0508))
+#define EMI_TTYPE3 ((P_U32)(EMI_BASE+0x0510))
+#define EMI_TTYPE4 ((P_U32)(EMI_BASE+0x0518))
+#define EMI_TTYPE5 ((P_U32)(EMI_BASE+0x0520))
+#define EMI_TTYPE6 ((P_U32)(EMI_BASE+0x0528))
+#define EMI_TTYPE7 ((P_U32)(EMI_BASE+0x0530))
+#define EMI_TTYPE8 ((P_U32)(EMI_BASE+0x0538))
+#define EMI_TTYPE9 ((P_U32)(EMI_BASE+0x0540))
+#define EMI_TTYPE10 ((P_U32)(EMI_BASE+0x0548))
+#define EMI_TTYPE11 ((P_U32)(EMI_BASE+0x0550))
+#define EMI_TTYPE12 ((P_U32)(EMI_BASE+0x0558))
+#define EMI_TTYPE13 ((P_U32)(EMI_BASE+0x0560))
+#define EMI_TTYPE14 ((P_U32)(EMI_BASE+0x0568))
+#define EMI_TTYPE15 ((P_U32)(EMI_BASE+0x0570))
+#define EMI_TTYPE16 ((P_U32)(EMI_BASE+0x0578))
+#define EMI_TTYPE17 ((P_U32)(EMI_BASE+0x0580))
+#define EMI_TTYPE18 ((P_U32)(EMI_BASE+0x0588))
+#define EMI_TTYPE19 ((P_U32)(EMI_BASE+0x0590))
+#define EMI_TTYPE20 ((P_U32)(EMI_BASE+0x0598))
+#define EMI_TTYPE21 ((P_U32)(EMI_BASE+0x05A0))
+
+/* EMI MBIST control registers*/
+#define EMI_MBISTA ((P_U32)(EMI_BASE+0x0600))
+#define EMI_MBISTB ((P_U32)(EMI_BASE+0x0608))
+#define EMI_MBISTC ((P_U32)(EMI_BASE+0x0610))
+#define EMI_MBISTD ((P_U32)(EMI_BASE+0x0618))
+#define EMI_MBISTE ((P_U32)(EMI_BASE+0x0620)) /* EMI MBIST status register */
+
+
+/* EMI Flow control register A */
+#define EMI_RFCA ((P_U32)(EMI_BASE+0x0630))
+#define EMI_RFCB ((P_U32)(EMI_BASE+0x0638))
+#define EMI_RFCC ((P_U32)(EMI_BASE+0x0640))
+#define EMI_RFCD ((P_U32)(EMI_BASE+0x0648))
+
+#endif // __EMI_H__
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h b/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h
new file mode 100644
index 0000000..23a5649
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/tz_init.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef TRUSTZONE_H
+#define TRUSTZONE_H
+
+#include "typedefs.h"
+
+#define BL31 0x43001000UL
+#define BL33 0x43a00000UL
+#define BL31_BASE 0x43000000UL
+#define BL31_SIZE 0x00030000UL /* default is 192K Bytes */
+
+#define ATF_BOOT_ARG_ADDR (0x40000000)
+#define TEE_BOOT_ARG_ADDR (0x40001000)
+#define ATF_BOOTCFG_MAGIC (0x4D415446) // String MATF in little-endian
+
+#define DEVINFO_SIZE 4
+
+/* bootarg for ATF */
+typedef struct {
+ u64 bootarg_loc;
+ u64 bootarg_size;
+ u64 bl33_start_addr;
+ u64 tee_info_addr;
+} mtk_bl_param_t;
+
+typedef struct {
+ u32 atf_magic;
+ u32 tee_support;
+ u32 tee_entry;
+ u32 tee_boot_arg_addr;
+ u32 hwuid[4]; // HW Unique id for t-base used
+ u32 atf_hrid_size;
+ u32 HRID[8]; // HW random id for t-base used
+ u32 atf_log_port;
+ u32 atf_log_baudrate;
+ u32 atf_log_buf_start;
+ u32 atf_log_buf_size;
+ u32 atf_irq_num;
+ u32 devinfo[DEVINFO_SIZE];
+ u32 atf_aee_debug_buf_start;
+ u32 atf_aee_debug_buf_size;
+#if CFG_TEE_SUPPORT
+ u32 tee_rpmb_size;
+#endif
+} atf_arg_t, *atf_arg_t_ptr;
+
+#endif /* TRUSTZONE_H */
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/include/uart.h b/src/bsp/trustzone/teeloader/mt8512/include/uart.h
new file mode 100644
index 0000000..13cabd0
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/include/uart.h
@@ -0,0 +1,62 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+typedef unsigned int uint32_t;
+typedef unsigned long uintptr_t;
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define writel(v, a) (*REG32(a) = (v))
+#define readl(a) (*REG32(a))
+
+#define UART_BASE(uart) (uart)
+#define UART_LSR(uart) (UART_BASE(uart)+0x14)
+#define UART_LSR_THRE (1 << 5)
+#define UART_THR(uart) (UART_BASE(uart)+0x0) /* Write only */
+
+#define IO_PHYS 0x10000000
+#define UART0_BASE (IO_PHYS + 0x01002000)
+#define UART1_BASE (IO_PHYS + 0x01003000)
+#define UART2_BASE (IO_PHYS + 0x01004000)
+
+int uart_putc(char c);
+
+#endif /* __UART_H__ */
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c
new file mode 100644
index 0000000..a4b3cd5
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_dapc.c
@@ -0,0 +1,194 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2017. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+/*=======================================================================*/
+/* HEADER FILES */
+/*=======================================================================*/
+#include <tz_dapc.h>
+#include <print.h>
+
+#define _DEBUG_
+#define DBG_DEVAPC
+
+/* Debug message event */
+#define DBG_EVT_NONE (0x00000000U) /* No event */
+#define DBG_EVT_ERR (0x00000001U) /* ERR related event */
+#define DBG_EVT_DOM (0x00000002U) /* DOM related event */
+
+#define DBG_EVT_ALL (0xffffffffU)
+
+#define DBG_EVT_MASK (DBG_EVT_DOM)
+
+#ifdef _DEBUG_
+#define MSG(evt, fmt, args...) \
+ do { \
+ if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
+ tl_printf(fmt, ##args); \
+ } \
+ } while(0)
+
+#define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
+#else
+#define MSG(evt, fmt, args...) do{} while(0)
+#define MSG_FUNC_ENTRY(f) do{} while(0)
+#endif
+
+/*=======================================================================*/
+/* STATIC FUNCTIONS */
+/*=======================================================================*/
+static void DAPC_dom_init(void)
+{
+ MSG(DOM, "\nDevice APC domain init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+
+ /* Set masters to DOMAINX here if needed
+ * Default is DOMAIN_0 */
+
+ /* example */
+ /*DAPC_SET_MASTER_DOMAIN(
+ DEVAPC0_MAS_DOM_0,
+ MODULE_DOMAIN(MASTER_SSUSB_XHCI, DOMAIN_0) |
+ MODULE_DOMAIN(MASTER_PWM, DOMAIN_1) |
+ MODULE_DOMAIN(MASTER_MSDC0, DOMAIN_2) |
+ MODULE_DOMAIN(MASTER_MSDC1, DOMAIN_3)
+ );*/
+
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Device APC domain after setup:\n");
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
+ MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_2));
+#endif
+}
+
+static void DAPC_trans_init(void)
+{
+ MSG(DOM, "\nDevice APC master transcation init setup:\n\n");
+
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Master Transaction (0x%x)\n", reg_read32(DEVAPC0_MAS_SEC_0));
+#endif
+
+ /* Set master transaction here if needed,
+ * default is non-secure transaction */
+
+ /* example */
+ /*DAPC_SET_MASTER_TRANSACTION(
+ DEVAPC0_MAS_SEC_0,
+ MODULE_TRANSACTION(MASTER_NFI, NS_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_SSUSB_XHCI, S_TRANSACTION) |
+ MODULE_TRANSACTION(MASTER_PWM, NS_TRANSACTION)
+ );*/
+
+#ifdef DBG_DEVAPC
+ MSG(DOM, "Master Transaction After Init (0x%x)\n", reg_read32(DEVAPC0_MAS_SEC_0));
+#endif
+
+}
+
+static void DAPC_slave_perm_init(void)
+{
+ MSG(DOM, "\nDevice APC slave permission init setup:\n\n");
+
+ /* Set slave permissions here if needed
+ * Default is NO_PROTECTION */
+
+ /* Set SEJ and DAPC to secure RW only */
+ DAPC_SET_SLAVE_PERMISSION(
+ DEVAPC0_D0_APC(0),
+ MODULE_PERMISSION(INFRA_AO_SEJ , SEC_RW_ONLY) |
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO_INFRA_PERI , SEC_RW_ONLY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION(
+ DEVAPC0_D0_APC(1),
+ MODULE_PERMISSION(INFRA_AO_DEVICE_APC_AO_MM , SEC_RW_ONLY)
+ );
+
+ DAPC_SET_SLAVE_PERMISSION(
+ DEVAPC0_D0_APC(2),
+ MODULE_PERMISSION(INFRASYS_DEVICE_APC , SEC_RW_ONLY)
+ );
+
+}
+
+static void tz_dapc_default_setting(void)
+{
+
+ /* Lock DAPC to secure access only && unmask debug bit && clear VIO status */
+ reg_write32(DEVAPC_APC_CON, 0x80000001);
+ reg_write32(DEVAPC0_APC_CON, 0x80000001);
+ reg_write32(DEVAPC1_APC_CON, 0x80000001);
+
+ /* Set domain of masters */
+ //DAPC_dom_init();
+
+ /* Set the transaction type of masters */
+ //DAPC_trans_init();
+
+ /* Set the access permission of slaves in domain 0 */
+ DAPC_slave_perm_init();
+}
+
+
+/*=======================================================================*/
+/* API */
+/*=======================================================================*/
+void tz_dapc_set_master_transaction(unsigned int master_index , E_TRANSACTION permisssion_control)
+{
+ reg_set_field(DEVAPC0_MAS_SEC_0 , (0x1 << master_index), permisssion_control);
+}
+
+
+/*=======================================================================*/
+/* INIT FUNCTIONS */
+/*=======================================================================*/
+
+void tz_dapc_sec_init(void)
+{
+ /* do initial settings */
+ tz_dapc_default_setting();
+}
+
+void tz_dapc_sec_postinit(void)
+{
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c
new file mode 100644
index 0000000..1aec1d9
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/drivers/tz_emi_mpu.c
@@ -0,0 +1,304 @@
+#include "print.h"
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_reg.h"
+#include "tz_emi_mpu.h"
+
+#define MOD "[TZ_EMI_MPU]"
+
+#define READ_REGISTER_UINT32(reg) \
+ (*(volatile UINT32 * const)(reg))
+
+#define WRITE_REGISTER_UINT32(reg, val) \
+ (*(volatile UINT32 * const)(reg)) = (val)
+
+
+#define readl(addr) (READ_REGISTER_UINT32(addr))
+#define writel(b,addr) (WRITE_REGISTER_UINT32(addr, b))
+#define IOMEM(reg) (reg)
+#define print tl_printf
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(unsigned int start, unsigned int end, int region, unsigned int access_permission)
+{
+ int ret = 0;
+ unsigned int tmp, tmp2;
+ unsigned int ax_pm, ax_pm2;
+
+ if((end != 0) || (start !=0))
+ {
+ /*Address 64KB alignment*/
+ start -= EMI_PHY_OFFSET;
+ end -= EMI_PHY_OFFSET;
+ start = start >> 16;
+ end = end >> 16;
+
+ if (end <= start)
+ {
+ return -1;
+ }
+ }
+
+ ax_pm = (access_permission << 16) >> 16;
+ ax_pm2 = (access_permission >> 16);
+
+ switch (region) {
+ case 0:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUI)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUI);
+ writel(0, EMI_MPUI_2ND);
+ writel((start << 16) | end, EMI_MPUA);
+ writel(tmp2 | ax_pm2, EMI_MPUI_2ND);
+ writel(tmp | ax_pm, EMI_MPUI);
+ break;
+
+ case 1:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUI)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUI_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUI);
+ writel(0, EMI_MPUI_2ND);
+ writel((start << 16) | end, EMI_MPUB);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUI_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUI);
+ break;
+
+ case 2:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUJ)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUJ);
+ writel(0, EMI_MPUJ_2ND);
+ writel((start << 16) | end, EMI_MPUC);
+ writel(tmp2 | ax_pm2, EMI_MPUJ_2ND);
+ writel(tmp | ax_pm, EMI_MPUJ);
+ break;
+
+ case 3:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUJ)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUJ_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUJ);
+ writel(0, EMI_MPUJ_2ND);
+ writel((start << 16) | end, EMI_MPUD);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUJ);
+ break;
+
+ case 4:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUK)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUK);
+ writel(0, EMI_MPUK_2ND);
+ writel((start << 16) | end, EMI_MPUE);
+ writel(tmp2 | ax_pm2, EMI_MPUK_2ND);
+ writel(tmp | ax_pm, EMI_MPUK);
+ break;
+
+ case 5:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUK)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUK_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUK);
+ writel(0, EMI_MPUK_2ND);
+ writel((start << 16) | end, EMI_MPUF);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUK_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUK);
+ break;
+
+ case 6:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUL)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUL);
+ writel(0, EMI_MPUL_2ND);
+ writel((start << 16) | end, EMI_MPUG);
+ writel(tmp2 | ax_pm2, EMI_MPUL_2ND);
+ writel(tmp | ax_pm, EMI_MPUL);
+ break;
+
+ case 7:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUL)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUL_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUL);
+ writel(0, EMI_MPUL_2ND);
+ writel((start << 16) | end, EMI_MPUH);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUL_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUL);
+ break;
+
+ case 8:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUI2)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUI2);
+ writel(0, EMI_MPUI2_2ND);
+ writel((start << 16) | end, EMI_MPUA2);
+ writel(tmp2 | ax_pm2, EMI_MPUI2_2ND);
+ writel(tmp | ax_pm, EMI_MPUI2);
+ break;
+
+ case 9:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUI2)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUI2_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUI2);
+ writel(0, EMI_MPUI2_2ND);
+ writel((start << 16) | end, EMI_MPUB2);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUI2_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUI2);
+ break;
+
+ case 10:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUJ2)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUJ2);
+ writel(0, EMI_MPUJ2_2ND);
+ writel((start << 16) | end, EMI_MPUC2);
+ writel(tmp2 | ax_pm2, EMI_MPUJ2_2ND);
+ writel(tmp | ax_pm, EMI_MPUJ2);
+ break;
+
+ case 11:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUJ2)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUJ2_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUJ2);
+ writel(0, EMI_MPUJ2_2ND);
+ writel((start << 16) | end, EMI_MPUD2);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUJ2_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUJ2);
+ break;
+
+ case 12:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUK2)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUK2);
+ writel(0, EMI_MPUK2_2ND);
+ writel((start << 16) | end, EMI_MPUE2);
+ writel(tmp2 | ax_pm2, EMI_MPUK2_2ND);
+ writel(tmp | ax_pm, EMI_MPUK2);
+ break;
+
+ case 13:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUK2)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUK2_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUK2);
+ writel(0, EMI_MPUK2_2ND);
+ writel((start << 16) | end, EMI_MPUF2);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUK2_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUK2);
+ break;
+
+ case 14:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUL2)) & 0xFFFF0000;
+ tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0xFFFF0000;
+ writel(0, EMI_MPUL2);
+ writel(0, EMI_MPUL2_2ND);
+ writel((start << 16) | end, EMI_MPUG2);
+ writel(tmp2 | ax_pm2, EMI_MPUL2_2ND);
+ writel(tmp | ax_pm, EMI_MPUL2);
+ break;
+
+ case 15:
+ //Marcos: Clear access right before setting MPU address (Mt6582 design)
+ tmp = readl(IOMEM(EMI_MPUL2)) & 0x0000FFFF;
+ tmp2 = readl(IOMEM(EMI_MPUL2_2ND)) & 0x0000FFFF;
+ writel(0, EMI_MPUL2);
+ writel(0, EMI_MPUL2_2ND);
+ writel((start << 16) | end, EMI_MPUH2);
+ writel(tmp2 | (ax_pm2 << 16), EMI_MPUL2_2ND);
+ writel(tmp | (ax_pm << 16), EMI_MPUL2);
+ break;
+
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region)
+{
+ int ret = 0;
+ unsigned int sec_mem_mpu_attr;
+ unsigned int sec_mem_phy_start, sec_mem_phy_end;
+ unsigned int temp;
+
+ /* Caculate start/end address */
+ sec_mem_phy_start = start_add;
+ sec_mem_phy_end = end_addr;
+
+ // For MT6589
+ //==================================================================================================================
+ // | Region | D0(AP) | D1(MD0) | D2(Conn) | D3(MD32) | D4(MM) | D5(MD1) | D6(MFG) | D7(N/A)
+ //------------+---------------------------------------------------------------------------------------------------
+ // Secure OS | 0 |RW(S) |Forbidden |Forbidden |Forbidden |RW(S) |Forbidden |Forbidden |Forbidden
+ //------------+---------------------------------------------------------------------------------------------------
+ // MD0 ROM | 1 |RO(S/NS) |RO(S/NS) |Forbidden |Forbidden
+ //------------+------------------------------------------------------
+ // MD0 R/W+ | 2 |Forbidden |No protect |Forbidden |Forbidden
+ //------------+------------------------------------------------------
+ // MD1 ROM | 3 |RO(S/NS) |Forbidden |RO(S/NS) |Forbidden
+ //------------+------------------------------------------------------
+ // MD1 R/W+ | 4 |Forbidden |Forbidden |No protect |Forbidden
+ //------------+------------------------------------------------------
+ // MD0 Share | 5 |No protect|No protect |Forbidden |Forbidden
+ //------------+------------------------------------------------------
+ // MD1 Share | 6 |No protect|Forbidden |No protect |Forbidden
+ //------------+------------------------------------------------------
+ // AP | 7 |No protect|Forbidden |Forbidden |No protect
+ //===================================================================
+
+ switch (mpu_region) {
+ case SECURE_OS_MPU_REGION_ID:
+ #ifdef DDR_RESERVE_MODE
+ print(" MPU [UNLOCK\n");
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ #else
+ print(" MPU [LOCK\n");
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ #endif
+ break;
+ case ATF_MPU_REGION_ID:
+ #ifdef DDR_RESERVE_MODE
+ print(" MPU [UNLOCK\n");
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(UNLOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ #else
+ print(" MPU [LOCK\n");
+ sec_mem_mpu_attr = SET_ACCESS_PERMISSON(LOCK, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ #endif
+ break;
+ default:
+ print("%s Warning - MPU region '%d' is not supported in pre-loader!\n", MOD, mpu_region);
+ return;
+ }
+
+ print("%s MPU [0x%x-0x%x]\n", MOD, sec_mem_phy_start, sec_mem_phy_end);
+
+ ret = emi_mpu_set_region_protection(sec_mem_phy_start, /*START_ADDR*/
+ sec_mem_phy_end, /*END_ADDR*/
+ mpu_region, /*region*/
+ sec_mem_mpu_attr);
+
+
+ if(ret)
+ {
+ print("%s MPU error!!\n", MOD);
+ }
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/main.c b/src/bsp/trustzone/teeloader/mt8512/src/main.c
new file mode 100644
index 0000000..8a9a454
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/main.c
@@ -0,0 +1,137 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "tz_init.h"
+#include "tz_emi_mpu.h"
+#include "uart.h"
+#include "print.h"
+
+typedef void (*jump_atf)(u64 addr ,u64 arg1) __attribute__ ((__noreturn__));
+
+extern void tz_emi_mpu_init(u32 start_add, u32 end_addr, u32 mpu_region);
+
+static u64 trustzone_get_atf_boot_param_addr(void)
+{
+ return ATF_BOOT_ARG_ADDR;
+}
+
+static u64 trustzone_get_tee_boot_param_addr(void)
+{
+ return TEE_BOOT_ARG_ADDR;
+}
+
+static void set_atf_parameters(mtk_bl_param_t *atf_arg)
+{
+ atf_arg->bootarg_loc = 0;
+ atf_arg->bootarg_size = 0;
+ atf_arg->bl33_start_addr = BL33;
+ atf_arg->tee_info_addr = TEE_BOOT_ARG_ADDR;
+}
+
+static void set_tee_parameters(atf_arg_t *tee_arg)
+{
+ /* tee arguments */
+ tee_arg->atf_magic = 0x4D415446;
+ tee_arg->tee_support = 0x1;
+ tee_arg->tee_entry = TRUSTEDOS_ENTRYPOINT;
+ tee_arg->tee_boot_arg_addr = 0x43000100;
+ tee_arg->hwuid[0] = 0x55C09893;
+ tee_arg->hwuid[1] = 0x2B404DDF;
+ tee_arg->hwuid[2] = 0x3ACE08B;
+ tee_arg->hwuid[3] = 0x1092600D;
+ tee_arg->HRID[0] = 0;
+ tee_arg->HRID[1] = 0;
+ tee_arg->atf_log_port = UART0_BASE;
+ tee_arg->atf_log_baudrate = 0xE1000;
+ tee_arg->atf_log_buf_start = 0x0;
+ tee_arg->atf_log_buf_size = 0x0;
+ tee_arg->atf_irq_num = 0x119; /* reserve SPI ID 249 for ATF log, which is ID 281 */
+ tee_arg->devinfo[0] = 0;
+ tee_arg->devinfo[1] = 0;
+ tee_arg->devinfo[2] = 0xFFFFFFFF;
+ tee_arg->devinfo[3] = 0xFFFFFFFF;
+ tee_arg->atf_aee_debug_buf_start = 0x0;
+ tee_arg->atf_aee_debug_buf_size = 0x0;
+}
+
+int teeloader_main(unsigned long long bl31_addr, unsigned long long bl33_addr,unsigned long long bl32_addr)
+{
+ u32 bl31_reserve = 0;
+ jump_atf atf_entry;
+ mtk_bl_param_t *atf_arg = (mtk_bl_param_t *)trustzone_get_atf_boot_param_addr();
+ atf_arg_t *tee_arg = (atf_arg_t *)trustzone_get_tee_boot_param_addr();
+
+ if (BL31_BASE+BL31_SIZE == TRUSTEDOS_ENTRYPOINT) {
+ /* we can combine the two regions into one */
+ tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+ (BL31_BASE & 0xffff0000) +
+ BL31_SIZE + TRUSTEDOS_SIZE - 1,
+ SECURE_OS_MPU_REGION_ID);
+ }
+ else {
+ if (TRUSTEDOS_ENTRYPOINT != 0) {
+ tz_emi_mpu_init((TRUSTEDOS_ENTRYPOINT & 0xffff0000),
+ (TRUSTEDOS_ENTRYPOINT & 0xffff0000) +
+ TRUSTEDOS_SIZE - 1,
+ SECURE_OS_MPU_REGION_ID);
+ }
+
+ tz_emi_mpu_init((BL31_BASE & 0xffff0000),
+ (BL31_BASE & 0xffff0000) + BL31_SIZE - 1,
+ ATF_MPU_REGION_ID);
+ }
+
+ /* DAPC init */
+ tz_dapc_sec_init();
+
+ set_atf_parameters(atf_arg);
+ set_tee_parameters(tee_arg);
+
+ if(bl32_addr)
+ tee_arg->tee_entry = bl32_addr;
+
+ if(bl33_addr)
+ atf_arg->bl33_start_addr = bl33_addr;
+
+ atf_entry = (jump_atf)BL31;
+ /* jump to tz */
+
+ (*atf_entry)(ATF_BOOT_ARG_ADDR, bl31_reserve);
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/print.c b/src/bsp/trustzone/teeloader/mt8512/src/print.c
new file mode 100644
index 0000000..5105290
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/print.c
@@ -0,0 +1,173 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#include "typedefs.h"
+#include "print.h"
+#include "uart.h"
+#include <stdarg.h>
+
+static void outchar(const char c)
+{
+ uart_putc(c);
+}
+
+static void outstr(const unsigned char *s)
+{
+ while (*s) {
+ if (*s == '\n')
+ outchar('\r');
+ outchar(*s++);
+ }
+}
+
+static void outdec(unsigned long n)
+{
+ if (n >= 10) {
+ outdec(n / 10);
+ n %= 10;
+ }
+ outchar((unsigned char)(n + '0'));
+}
+
+static void outhex(unsigned long n, long depth)
+{
+ if (depth)
+ depth--;
+
+ if ((n & ~0xf) || depth) {
+ outhex(n >> 4, depth);
+ n &= 0xf;
+ }
+
+ if (n < 10) {
+ outchar((unsigned char)(n + '0'));
+ } else {
+ outchar((unsigned char)(n - 10 + 'A'));
+ }
+}
+
+void tl_vprint(char *fmt, va_list vl)
+{
+ unsigned char c;
+ unsigned int reg = 1; /* argument register number (32-bit) */
+
+ while (*fmt) {
+ c = *fmt++;
+ switch (c) {
+ case '%':
+ c = *fmt++;
+ switch (c) {
+ case 'x':
+ outhex(va_arg(vl, unsigned long), 0);
+ break;
+ case 'B':
+ outhex(va_arg(vl, unsigned long), 2);
+ break;
+ case 'H':
+ outhex(va_arg(vl, unsigned long), 4);
+ break;
+ case 'X':
+ outhex(va_arg(vl, unsigned long), 8);
+ break;
+ case 'l':
+ if (*fmt == 'l' && *(fmt + 1) == 'x') {
+ u32 ltmp;
+ u32 htmp;
+
+ ltmp = va_arg(vl, unsigned int);
+ htmp = va_arg(vl, unsigned int);
+
+ outhex(htmp, 8);
+ outhex(ltmp, 8);
+ fmt += 2;
+ }
+ break;
+ case 'd':
+ {
+ long l;
+
+ l = va_arg(vl, long);
+ if (l < 0) {
+ outchar('-');
+ l = -l;
+ }
+ outdec((unsigned long)l);
+ }
+ break;
+ case 'u':
+ outdec(va_arg(vl, unsigned long));
+ break;
+ case 's':
+ outstr((const unsigned char *)
+ va_arg(vl, char *));
+ break;
+ case '%':
+ outchar('%');
+ break;
+ case 'c':
+ c = va_arg(vl, int);
+ outchar(c);
+ break;
+ default:
+ outchar(' ');
+ break;
+ }
+ reg++; /* one argument uses 32-bit register */
+ break;
+ case '\r':
+ if (*fmt == '\n')
+ fmt++;
+ c = '\n';
+ // fall through
+ case '\n':
+ outchar('\r');
+ // fall through
+ default:
+ outchar(c);
+ }
+ }
+}
+
+void tl_printf(char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ tl_vprint(fmt, args);
+ va_end(args);
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/start.s b/src/bsp/trustzone/teeloader/mt8512/src/start.s
new file mode 100644
index 0000000..aeda20a
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/start.s
@@ -0,0 +1,42 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2016. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+.section .text.start
+
+.globl _start
+_start:
+ b teeloader_main
\ No newline at end of file
diff --git a/src/bsp/trustzone/teeloader/mt8512/src/uart.c b/src/bsp/trustzone/teeloader/mt8512/src/uart.c
new file mode 100644
index 0000000..b238868
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/src/uart.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "uart.h"
+
+int uart_putc(char c)
+{
+ while (!(readl(UART_LSR(UART0_BASE)) & UART_LSR_THRE));
+
+ if (c == '\n')
+ writel((unsigned int)'\r', UART_THR(UART0_BASE));
+
+ writel((unsigned int)c, UART_THR(UART0_BASE));
+
+ return 0;
+}
diff --git a/src/bsp/trustzone/teeloader/mt8512/tllink.lds b/src/bsp/trustzone/teeloader/mt8512/tllink.lds
new file mode 100644
index 0000000..dc5a82b
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/tllink.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH(aarch64)
+
+ENTRY(_start)
+
+SECTIONS {
+
+ . = %BASE_ADDR%;
+ .start ALIGN(4) : {
+ *(.text.start)
+ }
+
+ . = . + 0x01FC;
+ .text ALIGN(4) : {
+ *(.text)
+ *(.text.*)
+ }
+ .rodata ALIGN(4) : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+ .data ALIGN(4) : {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = %BASE_ADDR%-0x100000 ;
+ .bss ALIGN(16) : {
+ _bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ /* make _bss_end as 4 bytes alignment */
+ . = ALIGN(4);
+ _bss_end = .;
+ }
+
+}
+
diff --git a/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh b/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh
new file mode 100755
index 0000000..e3fb84e
--- /dev/null
+++ b/src/bsp/trustzone/teeloader/mt8512/zero_padding.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+FILE_PATH=$1
+ALIGNMENT=$2
+PADDING_SIZE=0
+
+FILE_SIZE=$(($(wc -c < "${FILE_PATH}")))
+REMAINDER=$((${FILE_SIZE} % ${ALIGNMENT}))
+FILE_DIR=$(dirname "${FILE_PATH}")
+if [ ${REMAINDER} -ne 0 ]; then
+ PADDING_SIZE=$((${ALIGNMENT} - ${REMAINDER}))
+ dd if=/dev/zero of=${FILE_DIR}/padding.txt bs=$PADDING_SIZE count=1
+ cat ${FILE_DIR}/padding.txt>>${FILE_PATH}
+ rm ${FILE_DIR}/padding.txt
+fi