[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/devtools/met-driver/4.19/mt2712/mtk_emi_bm.h b/src/devtools/met-driver/4.19/mt2712/mtk_emi_bm.h
new file mode 100644
index 0000000..921d80d
--- /dev/null
+++ b/src/devtools/met-driver/4.19/mt2712/mtk_emi_bm.h
@@ -0,0 +1,414 @@
+#ifndef __MT_MET_EMI_BM_H__
+#define __MT_MET_EMI_BM_H__
+
+
+
+
+#define DEF_BM_RW_TYPE (BM_BOTH_READ_WRITE)
+#define NTS 2
+#define NWSCT 4
+#define NLATENCY 8
+#define NTRANS 8
+#define NALL 3
+#define NTTYPE 5
+#define NIDX_EMI (NTS + NWSCT + NLATENCY + NTRANS + NALL + NTTYPE)
+
+#define NCNT 9
+#define NCH 4
+#define NIDX_DRAMC (NCNT * NCH)
+#define NIDX (NIDX_EMI + NIDX_DRAMC)
+
+#define NCLK 1
+#define NARB 8
+#define NBW 10
+#define NIDX_BL (NCLK + NARB + NBW)
+
+/* 1000 To Khz and 4x freq & 2x data rate for LPDDR4 */
+/* 1000 To Khz and 2x freq & 2x data rate for LPDDR3*/
+/* TBD: calculate emi clock rate from DRAM DATA RATE */
+
+/*dram baseclock/EMI clock : LP4=4 LP3=2 */
+#define DRAM_EMI_BASECLOCK_RATE 4
+/*dram io width : LP4=x16 LP3=x32 or x16 */
+#define DRAM_IO_BUS_WIDTH 16
+/*dram datarate : DDR=double */
+#define DRAM_DATARATE 2
+
+#define ADDR_EMI ((unsigned long) BaseAddrEMI)
+#define ADDR_DRAMC0 ((unsigned long) BaseAddrDRAMC0)
+#define ADDR_DRAMC1 ((unsigned long) BaseAddrDRAMC1)
+#define ADDR_DRAMC2 ((unsigned long) BaseAddrDRAMC2)
+#define ADDR_DRAMC3 ((unsigned long) BaseAddrDRAMC3)
+
+static const char of_emi_desc[] = "mediatek,mt2712-emi";
+static const char of_dramc_desc[] = "mediatek,mt2712-dramc";
+
+typedef enum {
+ DRAMC_DTS_DRAMC0_AO = 0x0,
+ DRAMC_DTS_DRAMC0_NAO = 0x4,
+ DRAMC_DTS_DRAMC1_NAO = 0x5,
+ DRAMC_DTS_DRAMC2_NAO = 0x6,
+ DRAMC_DTS_DRAMC3_NAO = 0x7,
+ DRAMC_DTS_DDRPHY0_AO = 0x8,
+} BM_DRAMC_DTS_INDEX;
+
+#define BM_Master_M0_name "m0_APMCU0"
+#define BM_Master_M1_name "m1_APMCU1"
+#define BM_Master_M2_name "m2_MM1_M1"
+#define BM_Master_M3_name "m3_MM2_M1"
+#define BM_Master_M4_name "m4_MM2_M0"
+#define BM_Master_M5_name "m5_MM1_M0"
+#define BM_Master_M6_name "m6_PERI"
+#define BM_Master_M7_name "m7_GPU"
+
+#define BM_Master_GP_AP (BM_MASTER_M0 | BM_MASTER_M1)
+#define BM_Master_GP_MM (BM_MASTER_M2 | BM_MASTER_M3 | BM_MASTER_M4 | BM_MASTER_M5)
+#define BM_Master_GP_GPU (BM_MASTER_M7)
+#define BM_Master_GP_PERI (BM_MASTER_M6)
+
+
+/*Need no change by project*/
+#define BM_Master_GP_1_Default BM_Master_GP_AP
+#define BM_Master_GP_2_Default BM_Master_GP_MM
+#define BM_Master_GP_3_Default BM_Master_GP_GPU
+
+#define BM_MASTER_M0 (0x01)
+#define BM_MASTER_M1 (0x02)
+#define BM_MASTER_M2 (0x04)
+#define BM_MASTER_M3 (0x08)
+#define BM_MASTER_M4 (0x10)
+#define BM_MASTER_M5 (0x20)
+#define BM_MASTER_M6 (0x40)
+#define BM_MASTER_M7 (0x80)
+#define BM_MASTER_ALL (0xFF)
+
+typedef enum {
+ BM_RK0_PRE_STANDBY = 0x0,
+ BM_RK0_PRE_POWERDOWN,
+ BM_RK0_ACT_STANDBY,
+ BM_RK0_ACT_POWERDOWN,
+ BM_RK1_PRE_STANDBY,
+ BM_RK1_PRE_POWERDOWN,
+ BM_RK1_ACT_STANDBY,
+ BM_RK1_ACT_POWERDOWN,
+ BM_RK2_PRE_STANDBY,
+ BM_RK2_PRE_POWERDOWN,
+ BM_RK2_ACT_STANDBY,
+ BM_RK2_ACT_POWERDOWN,
+ DRAMC_Debug_MAX_CNT
+} DRAMC_Debug_Type;
+
+typedef enum {
+ DRAMC_R2R,
+ DRAMC_R2W,
+ DRAMC_W2R,
+ DRAMC_W2W,
+ DRAMC_ALL
+} DRAMC_Cnt_Type;
+
+typedef enum {
+ BM_BOTH_READ_WRITE,
+ BM_READ_ONLY,
+ BM_WRITE_ONLY
+} BM_RW_Type;
+
+enum {
+ BM_TRANS_TYPE_1BEAT = 0x0,
+ BM_TRANS_TYPE_2BEAT,
+ BM_TRANS_TYPE_3BEAT,
+ BM_TRANS_TYPE_4BEAT,
+ BM_TRANS_TYPE_5BEAT,
+ BM_TRANS_TYPE_6BEAT,
+ BM_TRANS_TYPE_7BEAT,
+ BM_TRANS_TYPE_8BEAT,
+ BM_TRANS_TYPE_9BEAT,
+ BM_TRANS_TYPE_10BEAT,
+ BM_TRANS_TYPE_11BEAT,
+ BM_TRANS_TYPE_12BEAT,
+ BM_TRANS_TYPE_13BEAT,
+ BM_TRANS_TYPE_14BEAT,
+ BM_TRANS_TYPE_15BEAT,
+ BM_TRANS_TYPE_16BEAT,
+ BM_TRANS_TYPE_1Byte = 0 << 4,
+ BM_TRANS_TYPE_2Byte = 1 << 4,
+ BM_TRANS_TYPE_4Byte = 2 << 4,
+ BM_TRANS_TYPE_8Byte = 3 << 4,
+ BM_TRANS_TYPE_16Byte = 4 << 4,
+ BM_TRANS_TYPE_32Byte = 5 << 4,
+ BM_TRANS_TYPE_BURST_WRAP = 0 << 7,
+ BM_TRANS_TYPE_BURST_INCR = 1 << 7
+};
+
+enum {
+ BM_TRANS_RW_DEFAULT = 0x0,
+ BM_TRANS_RW_READONLY,
+ BM_TRANS_RW_WRITEONLY,
+ BM_TRANS_RW_RWBOTH
+};
+
+
+/*coda busid 12bit, but HW support 16 bit*/
+#define EMI_BMID_MASK (0xFFFF)
+#define BM_COUNTER_MAX (21)
+
+/*
+*#define BUS_MON_EN (0x00000001)
+*#define BUS_MON_PAUSE (0x00000002)
+*#define BUS_MON_IDLE (0x00000008)
+*#define BC_OVERRUN (0x00000100)
+*/
+enum {
+ BUS_MON_EN_SHIFT = 0,
+ BUS_MON_PAUSE_SHIFT = 1,
+ BUS_MON_IDLE_SHIFT = 3,
+ BC_OVERRUN_SHIFT = 8,
+};
+
+#define BM_REQ_OK (0)
+#define BM_ERR_WRONG_REQ (-1)
+#define BM_ERR_OVERRUN (-2)
+
+#define BM_WSCT_TSCT_IDSEL_ENABLE (0)
+#define BM_WSCT_TSCT_IDSEL_DISABLE (-1)
+#define BM_TTYPE1_16_ENABLE (0)
+#define BM_TTYPE1_16_DISABLE (-1)
+#define BM_TTYPE17_21_ENABLE (0)
+#define BM_TTYPE17_21_DISABLE (-1)
+#define BM_BW_LIMITER_ENABLE (0)
+#define BM_BW_LIMITER_DISABLE (-1)
+
+#define M0_DOUBLE_HALF_BW_1CH (0x0)
+#define M0_DOUBLE_HALF_BW_2CH (0x1)
+#define M0_DOUBLE_HALF_BW_4CH (0x2)
+
+#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
+/*ondiemet emi ipi command*/
+typedef enum {
+ SET_BASE_EMI = 0x0,
+ SET_BASE_DRAMC0,
+ SET_BASE_DRAMC1,
+ SET_BASE_DRAMC2,
+ SET_BASE_DRAMC3,
+ SET_BASE_DDRPHY0AO,
+ SET_BASE_DRAMC0_AO,
+ SET_EBM_CONFIGS,
+} BM_EMI_IPI_Type;
+#endif
+
+#define EMI_OFF 0x0000
+#define EMI_CONA (0x000-EMI_OFF)
+#define EMI_CONH (0x038-EMI_OFF)
+#define EMI_CONM (0x060-EMI_OFF)
+#define EMI_CONO (0x070-EMI_OFF)
+
+#define EMI_MDCT (0x078-EMI_OFF)
+#define EMI_MDCT_2ND (0x07C-EMI_OFF)
+
+#define EMI_ARBA (0x100-EMI_OFF)
+#define EMI_ARBB (0x108-EMI_OFF)
+#define EMI_ARBC (0x110-EMI_OFF)
+#define EMI_ARBD (0x118-EMI_OFF)
+#define EMI_ARBE (0x120-EMI_OFF)
+#define EMI_ARBF (0x128-EMI_OFF)
+#define EMI_ARBG (0x130-EMI_OFF)
+#define EMI_ARBG_2ND (0x134-EMI_OFF)
+#define EMI_ARBH (0x138-EMI_OFF)
+
+#define EMI_BMEN (0x400-EMI_OFF)
+#define EMI_BCNT (0x408-EMI_OFF)
+#define EMI_TACT (0x410-EMI_OFF)
+#define EMI_TSCT (0x418-EMI_OFF)
+#define EMI_WACT (0x420-EMI_OFF)
+#define EMI_WSCT (0x428-EMI_OFF)
+#define EMI_BACT (0x430-EMI_OFF)
+#define EMI_BSCT (0x438-EMI_OFF)
+
+#define EMI_MSEL (0x440-EMI_OFF)
+#define EMI_TSCT2 (0x448-EMI_OFF)
+#define EMI_TSCT3 (0x450-EMI_OFF)
+#define EMI_WSCT2 (0x458-EMI_OFF)
+#define EMI_WSCT3 (0x460-EMI_OFF)
+#define EMI_WSCT4 (0x464-EMI_OFF)
+#define EMI_MSEL2 (0x468-EMI_OFF)
+#define EMI_MSEL3 (0x470-EMI_OFF)
+#define EMI_MSEL4 (0x478-EMI_OFF)
+#define EMI_MSEL5 (0x480-EMI_OFF)
+#define EMI_MSEL6 (0x488-EMI_OFF)
+#define EMI_MSEL7 (0x490-EMI_OFF)
+#define EMI_MSEL8 (0x498-EMI_OFF)
+#define EMI_MSEL9 (0x4A0-EMI_OFF)
+#define EMI_MSEL10 (0x4A8-EMI_OFF)
+
+#define EMI_BMID0 (0x4B0-EMI_OFF)
+#define EMI_BMID1 (0x4B4-EMI_OFF)
+#define EMI_BMID2 (0x4B8-EMI_OFF)
+#define EMI_BMID3 (0x4BC-EMI_OFF)
+#define EMI_BMID4 (0x4C0-EMI_OFF)
+#define EMI_BMID5 (0x4C4-EMI_OFF)
+#define EMI_BMID6 (0x4C8-EMI_OFF)
+#define EMI_BMID7 (0x4CC-EMI_OFF)
+#define EMI_BMID8 (0x4D0-EMI_OFF)
+#define EMI_BMID9 (0x4D4-EMI_OFF)
+#define EMI_BMID10 (0x4D8-EMI_OFF)
+
+#define EMI_BMEN1 (0x4E0-EMI_OFF)
+#define EMI_BMEN2 (0x4E8-EMI_OFF)
+#define EMI_BMRW0 (0x4F8-EMI_OFF)
+#define EMI_BMRW1 (0x4FC-EMI_OFF)
+#define EMI_TTYPE1 (0x500-EMI_OFF)
+#define EMI_TTYPE2 (0x508-EMI_OFF)
+#define EMI_TTYPE3 (0x510-EMI_OFF)
+#define EMI_TTYPE4 (0x518-EMI_OFF)
+#define EMI_TTYPE5 (0x520-EMI_OFF)
+#define EMI_TTYPE6 (0x528-EMI_OFF)
+#define EMI_TTYPE7 (0x530-EMI_OFF)
+#define EMI_TTYPE8 (0x538-EMI_OFF)
+#define EMI_TTYPE9 (0x540-EMI_OFF)
+#define EMI_TTYPE10 (0x548-EMI_OFF)
+#define EMI_TTYPE11 (0x550-EMI_OFF)
+#define EMI_TTYPE12 (0x558-EMI_OFF)
+#define EMI_TTYPE13 (0x560-EMI_OFF)
+#define EMI_TTYPE14 (0x568-EMI_OFF)
+#define EMI_TTYPE15 (0x570-EMI_OFF)
+#define EMI_TTYPE16 (0x578-EMI_OFF)
+#define EMI_TTYPE17 (0x580-EMI_OFF)
+#define EMI_TTYPE18 (0x588-EMI_OFF)
+#define EMI_TTYPE19 (0x590-EMI_OFF)
+#define EMI_TTYPE20 (0x598-EMI_OFF)
+#define EMI_TTYPE21 (0x5A0-EMI_OFF)
+
+#define EMI_BWCT0 (0x5B0-EMI_OFF)
+#define EMI_BWCT1 (0x5B4-EMI_OFF)
+#define EMI_BWCT2 (0x5B8-EMI_OFF)
+#define EMI_BWCT3 (0x5BC-EMI_OFF)
+#define EMI_BWCT4 (0x5C0-EMI_OFF)
+#define EMI_BWST0 (0x5C4-EMI_OFF)
+#define EMI_BWST1 (0x5C8-EMI_OFF)
+
+#define EMI_BWCT0_2ND (0x6A0-EMI_OFF)
+#define EMI_BWCT1_2ND (0x6A4-EMI_OFF)
+#define EMI_BWST_2ND (0x6A8-EMI_OFF)
+
+#define DRAMC_DMMONITOR 0x24
+#define DRAMC_MISC_STATUSA 0x80
+#define DRAMC_REFRESH_POP 0x300
+#define DRAMC_FREERUN_26M 0x304
+#define DRAMC_R2R_PAGE_HIT 0x30C
+#define DRAMC_R2R_PAGE_MISS 0x310
+#define DRAMC_R2R_INTERBANK 0x314
+#define DRAMC_R2W_PAGE_HIT 0x318
+#define DRAMC_R2W_PAGE_MISS 0x31C
+#define DRAMC_R2W_INTERBANK 0x320
+#define DRAMC_W2R_PAGE_HIT 0x324
+#define DRAMC_W2R_PAGE_MISS 0x328
+#define DRAMC_W2R_INTERBANK 0x32C
+#define DRAMC_W2W_PAGE_HIT 0x330
+#define DRAMC_W2W_PAGE_MISS 0x334
+#define DRAMC_W2W_INTERBANK 0x338
+#define DRAMC_IDLE_COUNT 0x308
+#define DRAMC_RK0_PRE_STANDBY 0x33c
+#define DRAMC_RK0_PRE_POWERDOWN 0x340
+#define DRAMC_RK0_ACT_STANDBY 0x344
+#define DRAMC_RK0_ACT_POWERDOWN 0x348
+#define DRAMC_RK1_PRE_STANDBY 0x34c
+#define DRAMC_RK1_PRE_POWERDOWN 0x350
+#define DRAMC_RK1_ACT_STANDBY 0x354
+#define DRAMC_RK1_ACT_POWERDOWN 0x358
+#define DRAMC_RK2_PRE_STANDBY 0x35c
+#define DRAMC_RK2_PRE_POWERDOWN 0x360
+#define DRAMC_RK2_ACT_STANDBY 0x364
+#define DRAMC_RK2_ACT_POWERDOWN 0x368
+#define DRAMC_READ_BYTES 0x38c
+#define DRAMC_WRITE_BYTES 0x390
+
+
+extern void emi_dump_reg(void);
+extern int MET_BM_Init(void);
+extern void MET_BM_DeInit(void);
+extern void MET_BM_Enable(const unsigned int enable);
+extern void MET_BM_Pause(void);
+extern void MET_BM_Continue(void);
+extern unsigned int MET_BM_IsOverrun(void);
+extern unsigned int MET_BM_GetReadWriteType(void);
+extern void MET_BM_SetReadWriteType(const unsigned int ReadWriteType);
+extern int MET_BM_GetBusCycCount(void);
+extern unsigned int MET_BM_GetTransAllCount(void);
+extern int MET_BM_GetTransCount(const unsigned int counter_num);
+extern int MET_BM_GetWordAllCount(void);
+extern int MET_BM_GetWordCount(const unsigned int counter_num);
+extern unsigned int MET_BM_GetBandwidthWordCount(void);
+extern unsigned int MET_BM_GetOverheadWordCount(void);
+extern int MET_BM_GetTransTypeCount(const unsigned int counter_num);
+extern int MET_BM_GetMDCT(void);
+extern int MET_BM_GetMDCT_2(void);
+extern int MET_BM_GetMonitorCounter(const unsigned int counter_num,
+ unsigned int *master,
+ unsigned int *trans_type);
+extern int MET_BM_SetMDCT_MDMCU(unsigned int mdmcu_rd_buf);
+extern int MET_BM_SetMonitorCounter(const unsigned int counter_num,
+ const unsigned int master,
+ const unsigned int trans_type);
+extern int MET_BM_SetTtypeCounterRW(unsigned int bmrw0_val, unsigned int bmrw1_val);
+extern int MET_BM_Set_WsctTsct_id_sel(unsigned int counter_num, unsigned int enable);
+extern int MET_BM_SetMaster(const unsigned int counter_num,
+ const unsigned int master);
+extern int MET_BM_SetIDSelect(const unsigned int counter_num,
+ const unsigned int id,
+ const unsigned int enable);
+extern int MET_BM_SetUltraHighFilter(const unsigned int counter_num,
+ const unsigned int enable);
+extern int MET_BM_SetLatencyCounter(unsigned int enable);
+extern int MET_BM_GetLatencyCycle(const unsigned int counter_num);
+extern unsigned int MET_BM_GetEmiDcm(void);
+extern int MET_BM_SetEmiDcm(const unsigned int setting);
+
+/* DRAMC */
+extern unsigned int MET_DRAMC_GetPageHitCount(DRAMC_Cnt_Type CountType, int chann);
+extern unsigned int MET_DRAMC_GetPageMissCount(DRAMC_Cnt_Type CountType, int chann);
+extern unsigned int MET_DRAMC_GetInterbankCount(DRAMC_Cnt_Type CountType, int chann);
+extern unsigned int MET_DRAMC_GetIdleCount(int chann);
+extern unsigned int MET_DRAMC_Misc_Status(int chann);
+extern unsigned int MET_DRAMC_RefPop(int chann);
+extern unsigned int MET_DRAMC_Free26M(int chann);
+extern unsigned int MET_DRAMC_RByte(int chann);
+extern unsigned int MET_DRAMC_WByte(int chann);
+extern int MET_DRAMC_BMEnable(int chann, int set);
+extern int MET_DRAMC_BMPause(int chann, int set);
+extern unsigned int get_dram_data_rate(void);
+
+/* Config */
+unsigned int MET_EMI_GetARBA(void);
+unsigned int MET_EMI_GetARBB(void);
+unsigned int MET_EMI_GetARBC(void);
+unsigned int MET_EMI_GetARBD(void);
+unsigned int MET_EMI_GetARBE(void);
+unsigned int MET_EMI_GetARBF(void);
+unsigned int MET_EMI_GetARBG(void);
+unsigned int MET_EMI_GetARBH(void);
+
+/* Total BW status */
+extern unsigned int MET_EMI_GetBWCT0(void);
+extern unsigned int MET_EMI_GetBWCT1(void);
+extern unsigned int MET_EMI_GetBWCT2(void);
+extern unsigned int MET_EMI_GetBWCT3(void);
+extern unsigned int MET_EMI_GetBWCT4(void);
+extern unsigned int MET_EMI_GetBWST0(void);
+extern unsigned int MET_EMI_GetBWST1(void);
+/* C+G BW */
+extern unsigned int MET_EMI_GetBWCT0_2ND(void);
+extern unsigned int MET_EMI_GetBWCT1_2ND(void);
+extern unsigned int MET_EMI_GetBWST_2ND(void);
+
+unsigned int MET_EMI_GetBMRW0(void);
+unsigned int MET_EMI_GetDramChannNum(void);
+
+/* Debug Counter status */
+void MET_DRAMC_GetDebugCounter(int *value, int chann);
+
+/* ondiemet*/
+void MET_BM_IPI_baseaddr(void);
+void met_emi_phyaddr_debug(void);
+
+
+
+#endif /* !__MT_MET_EMI_BM_H__ */