[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Kconfig b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 0000000..849074e
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,89 @@
+if ARCH_MEDIATEK || COMPILE_TEST
+
+config EINT_MTK
+ bool "MediaTek External Interrupt Support"
+ depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST
+ select GPIOLIB
+ select IRQ_DOMAIN
+
+config PINCTRL_MTK
+ bool
+ depends on OF
+ select PINMUX
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select OF_GPIO
+
+config PINCTRL_MTK_PARIS
+ bool "MediaTek Paris Core that implements vendor binding"
+ depends on OF
+ select PINMUX
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select EINT_MTK
+ select OF_GPIO
+
+# For ARMv7 SoCs
+config PINCTRL_MT2701
+ bool "Mediatek MT2701 pin control"
+ depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
+ depends on OF
+ default MACH_MT2701
+ select PINCTRL_MTK
+
+config PINCTRL_MT8135
+ bool "Mediatek MT8135 pin control"
+ depends on MACH_MT8135 || COMPILE_TEST
+ depends on OF
+ default MACH_MT8135
+ select PINCTRL_MTK
+
+config PINCTRL_MT8127
+ bool "Mediatek MT8127 pin control"
+ depends on MACH_MT8127 || COMPILE_TEST
+ depends on OF
+ default MACH_MT8127
+ select PINCTRL_MTK
+
+# For ARMv8 SoCs
+config PINCTRL_MT2731
+ bool "Mediatek MT2731 pin control"
+ depends on OF
+ depends on MACH_MT2731 || COMPILE_TEST
+ default MACH_MT2731
+ select PINCTRL_MTK_PARIS
+
+config PINCTRL_MT8173
+ bool "Mediatek MT8173 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
+config PINCTRL_MT8183
+ bool "Mediatek MT8183 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
+# For PMIC
+config PINCTRL_MT6397
+ bool "Mediatek MT6397 pin control"
+ depends on MFD_MT6397 || COMPILE_TEST
+ depends on OF
+ default MFD_MT6397
+ select PINCTRL_MTK
+
+# For pintcrl command debug
+config PINCTRL_MTK_DEBUG
+ bool "Mediatek pin control common debug"
+ depends on OF
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+ help
+ Say yes here to enable support for MediaTek pinctrl debug command.
+ It can provide gpio status debug shell command.
+ We also can use these shell command to change gpio status.
+
+endif
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Makefile b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 0000000..e42bc3c
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_EINT_MTK) += mtk-eint.o
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o pinctrl-mtk-common-v2_debug.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2731) += pinctrl-mt2731.o
+obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
+obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
+obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
+obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
+obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.c
new file mode 100644
index 0000000..15ed882
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.c
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2014-2018 MediaTek Inc.
+
+/*
+ * Library for MediaTek External Interrupt Support
+ *
+ * Author: Maoguang Meng <maoguang.meng@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+#include <linux/wakeup_reason.h>
+
+#include "mtk-eint.h"
+
+#define MTK_EINT_EDGE_SENSITIVE 0
+#define MTK_EINT_LEVEL_SENSITIVE 1
+#define MTK_EINT_DBNC_SET_DBNC_BITS 4
+#define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
+#define MTK_EINT_DBNC_SET_EN (0x1 << 0)
+
+static const struct mtk_eint_regs mtk_generic_eint_regs = {
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+};
+
+static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
+ unsigned int eint_num,
+ unsigned int offset)
+{
+ unsigned int eint_base = 0;
+ void __iomem *reg;
+
+ if (eint_num >= eint->hw->ap_num)
+ eint_base = eint->hw->ap_num;
+
+ reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
+
+ return reg;
+}
+
+static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
+ unsigned int eint_num)
+{
+ unsigned int sens;
+ unsigned int bit = BIT(eint_num % 32);
+ void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
+ eint->regs->sens);
+
+ if (readl(reg) & bit)
+ sens = MTK_EINT_LEVEL_SENSITIVE;
+ else
+ sens = MTK_EINT_EDGE_SENSITIVE;
+
+ if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
+ return 1;
+ else
+ return 0;
+}
+
+static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
+{
+ int start_level, curr_level;
+ unsigned int reg_offset;
+ u32 mask = BIT(hwirq & 0x1f);
+ u32 port = (hwirq >> 5) & eint->hw->port_mask;
+ void __iomem *reg = eint->base + (port << 2);
+
+ curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
+
+ do {
+ start_level = curr_level;
+ if (start_level)
+ reg_offset = eint->regs->pol_clr;
+ else
+ reg_offset = eint->regs->pol_set;
+ writel(mask, reg + reg_offset);
+
+ curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
+ hwirq);
+ } while (start_level != curr_level);
+
+ return start_level;
+}
+
+static void mtk_eint_mask(struct irq_data *d)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+ eint->regs->mask_set);
+
+ writel(mask, reg);
+}
+
+static void mtk_eint_unmask(struct irq_data *d)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+ eint->regs->mask_clr);
+
+ writel(mask, reg);
+
+ if (eint->dual_edge[d->hwirq])
+ mtk_eint_flip_edge(eint, d->hwirq);
+}
+
+static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
+ unsigned int eint_num)
+{
+ unsigned int bit = BIT(eint_num % 32);
+ void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
+ eint->regs->mask);
+
+ return !!(readl(reg) & bit);
+}
+
+static void mtk_eint_ack(struct irq_data *d)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+ eint->regs->ack);
+
+ writel(mask, reg);
+}
+
+static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg;
+
+ if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
+ ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
+ dev_err(eint->dev,
+ "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
+ d->irq, d->hwirq, type);
+ return -EINVAL;
+ }
+
+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+ eint->dual_edge[d->hwirq] = 1;
+ else
+ eint->dual_edge[d->hwirq] = 0;
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
+ reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
+ writel(mask, reg);
+ } else {
+ reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
+ writel(mask, reg);
+ }
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+ reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
+ writel(mask, reg);
+ } else {
+ reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
+ writel(mask, reg);
+ }
+
+ if (eint->dual_edge[d->hwirq])
+ mtk_eint_flip_edge(eint, d->hwirq);
+
+ return 0;
+}
+
+static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ int shift = d->hwirq & 0x1f;
+ int reg = d->hwirq >> 5;
+
+ if (on)
+ eint->wake_mask[reg] |= BIT(shift);
+ else
+ eint->wake_mask[reg] &= ~BIT(shift);
+
+ return 0;
+}
+
+static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
+ void __iomem *base, u32 *buf)
+{
+ int port;
+ void __iomem *reg;
+
+ for (port = 0; port < eint->hw->ports; port++) {
+ reg = base + (port << 2);
+ writel_relaxed(~buf[port], reg + eint->regs->mask_set);
+ writel_relaxed(buf[port], reg + eint->regs->mask_clr);
+ }
+}
+
+static void mtk_eint_chip_read_mask(const struct mtk_eint *eint,
+ void __iomem *base, u32 *buf)
+{
+ int port;
+ void __iomem *reg;
+
+ for (port = 0; port < eint->hw->ports; port++) {
+ reg = base + eint->regs->mask + (port << 2);
+ buf[port] = ~readl_relaxed(reg);
+ /* Mask is 0 when irq is enabled, and 1 when disabled. */
+ }
+}
+
+static int mtk_eint_irq_request_resources(struct irq_data *d)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ struct gpio_chip *gpio_c;
+ unsigned int gpio_n;
+ int err;
+
+ err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
+ &gpio_n, &gpio_c);
+ if (err < 0) {
+ dev_err(eint->dev, "Can not find pin\n");
+ return err;
+ }
+
+ err = gpiochip_lock_as_irq(gpio_c, gpio_n);
+ if (err < 0) {
+ dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
+ irqd_to_hwirq(d));
+ return err;
+ }
+
+ err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
+ if (err < 0) {
+ dev_err(eint->dev, "Can not eint mode\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static void mtk_eint_irq_release_resources(struct irq_data *d)
+{
+ struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+ struct gpio_chip *gpio_c;
+ unsigned int gpio_n;
+
+ eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
+ &gpio_c);
+
+ gpiochip_unlock_as_irq(gpio_c, gpio_n);
+}
+
+static struct irq_chip mtk_eint_irq_chip = {
+ .name = "mt-eint",
+ .irq_disable = mtk_eint_mask,
+ .irq_mask = mtk_eint_mask,
+ .irq_unmask = mtk_eint_unmask,
+ .irq_ack = mtk_eint_ack,
+ .irq_set_type = mtk_eint_set_type,
+ .irq_set_wake = mtk_eint_irq_set_wake,
+ .irq_request_resources = mtk_eint_irq_request_resources,
+ .irq_release_resources = mtk_eint_irq_release_resources,
+};
+
+static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
+{
+ void __iomem *reg = eint->base + eint->regs->dom_en;
+ unsigned int i;
+
+ for (i = 0; i < eint->hw->ap_num; i += 32) {
+ writel(0xffffffff, reg);
+ reg += 4;
+ }
+
+ return 0;
+}
+
+static inline void
+mtk_eint_debounce_process(struct mtk_eint *eint, int index)
+{
+ unsigned int rst, ctrl_offset;
+ unsigned int bit, dbnc;
+
+ ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
+ dbnc = readl(eint->base + ctrl_offset);
+ bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
+ if ((bit & dbnc) > 0) {
+ ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
+ rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
+ writel(rst, eint->base + ctrl_offset);
+ }
+}
+
+static void mtk_eint_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct mtk_eint *eint = irq_desc_get_handler_data(desc);
+ unsigned int status, eint_num;
+ int offset, index, virq;
+ void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
+ int dual_edge, start_level, curr_level;
+
+ chained_irq_enter(chip, desc);
+ for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
+ reg += 4) {
+ status = readl(reg);
+ while (status) {
+ offset = __ffs(status);
+ index = eint_num + offset;
+ virq = irq_find_mapping(eint->domain, index);
+ status &= ~BIT(offset);
+
+ dual_edge = eint->dual_edge[index];
+ if (dual_edge) {
+ /*
+ * Clear soft-irq in case we raised it last
+ * time.
+ */
+ writel(BIT(offset), reg - eint->regs->stat +
+ eint->regs->soft_clr);
+
+ start_level =
+ eint->gpio_xlate->get_gpio_state(eint->pctl,
+ index);
+ }
+
+ generic_handle_irq(virq);
+
+ if (dual_edge) {
+ curr_level = mtk_eint_flip_edge(eint, index);
+
+ /*
+ * If level changed, we might lost one edge
+ * interrupt, raised it through soft-irq.
+ */
+ if (start_level != curr_level)
+ writel(BIT(offset), reg -
+ eint->regs->stat +
+ eint->regs->soft_set);
+ }
+
+ if (index < eint->hw->db_cnt)
+ mtk_eint_debounce_process(eint, index);
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+int mtk_eint_do_suspend(struct mtk_eint *eint)
+{
+ mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask);
+ mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
+
+ return 0;
+}
+
+int mtk_eint_do_resume(struct mtk_eint *eint)
+{
+ mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
+
+ return 0;
+}
+
+int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
+ unsigned int debounce)
+{
+ int virq, eint_offset;
+ unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
+ dbnc;
+ static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
+ 64000, 128000, 256000};
+ struct irq_data *d;
+
+ virq = irq_find_mapping(eint->domain, eint_num);
+ eint_offset = (eint_num % 4) * 8;
+ d = irq_get_irq_data(virq);
+
+ set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
+ clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
+
+ if (!mtk_eint_can_en_debounce(eint, eint_num))
+ return -EINVAL;
+
+ dbnc = ARRAY_SIZE(debounce_time);
+ for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
+ if (debounce <= debounce_time[i]) {
+ dbnc = i;
+ break;
+ }
+ }
+
+ if (!mtk_eint_get_mask(eint, eint_num)) {
+ mtk_eint_mask(d);
+ unmask = 1;
+ } else {
+ unmask = 0;
+ }
+
+ clr_bit = 0xff << eint_offset;
+ writel(clr_bit, eint->base + clr_offset);
+
+ bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
+ eint_offset;
+ rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
+ writel(rst | bit, eint->base + set_offset);
+
+ /*
+ * Delay a while (more than 2T) to wait for hw debounce counter reset
+ * work correctly.
+ */
+ udelay(1);
+ if (unmask == 1)
+ mtk_eint_unmask(d);
+
+ return 0;
+}
+
+int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
+{
+ int irq;
+
+ irq = irq_find_mapping(eint->domain, eint_n);
+ if (!irq)
+ return -EINVAL;
+
+ return irq;
+}
+
+static struct mtk_eint *g_eint;
+void mt_eint_log_resume_irq(void)
+{
+ unsigned int status, eint_num;
+ unsigned int offset;
+ const struct mtk_eint_regs *eint_offsets = g_eint->regs;
+ void __iomem *reg_base = mtk_eint_get_offset(g_eint, 0
+ , eint_offsets->stat);
+ unsigned int triggered_eint;
+
+ for (eint_num = 0; eint_num < g_eint->hw->ap_num;
+ reg_base += 4, eint_num += 32) {
+ /* read status register every 32 interrupts */
+ status = readl(reg_base);
+ if (!status)
+ continue;
+
+ while (status) {
+ offset = __ffs(status);
+ triggered_eint = eint_num + offset;
+ pr_info("EINT %d is pending\n", triggered_eint);
+ log_wakeup_reason(irq_find_mapping(g_eint->domain,
+ triggered_eint));
+ status &= ~BIT(offset);
+ }
+ }
+}
+
+
+static struct syscore_ops mtk_eint_syscore_ops = {
+ .resume = mt_eint_log_resume_irq,
+};
+
+int mtk_eint_do_init(struct mtk_eint *eint)
+{
+ int i;
+
+ /* If clients don't assign a specific regs, let's use generic one */
+ if (!eint->regs)
+ eint->regs = &mtk_generic_eint_regs;
+
+ eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
+ sizeof(*eint->wake_mask), GFP_KERNEL);
+ if (!eint->wake_mask)
+ return -ENOMEM;
+
+ eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
+ sizeof(*eint->cur_mask), GFP_KERNEL);
+ if (!eint->cur_mask)
+ return -ENOMEM;
+
+ eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
+ sizeof(int), GFP_KERNEL);
+ if (!eint->dual_edge)
+ return -ENOMEM;
+
+ eint->domain = irq_domain_add_linear(eint->dev->of_node,
+ eint->hw->ap_num,
+ &irq_domain_simple_ops, NULL);
+ if (!eint->domain)
+ return -ENOMEM;
+
+ mtk_eint_hw_init(eint);
+ for (i = 0; i < eint->hw->ap_num; i++) {
+ int virq = irq_create_mapping(eint->domain, i);
+
+ irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(virq, eint);
+ }
+
+ irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
+ eint);
+ g_eint = eint;
+ register_syscore_ops(&mtk_eint_syscore_ops);
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.h
new file mode 100644
index 0000000..af7e3b0
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/mtk-eint.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014-2018 MediaTek Inc.
+ *
+ * Author: Maoguang Meng <maoguang.meng@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+#ifndef __MTK_EINT_H
+#define __MTK_EINT_H
+
+#include <linux/irqdomain.h>
+
+struct mtk_eint_regs {
+ unsigned int stat;
+ unsigned int ack;
+ unsigned int mask;
+ unsigned int mask_set;
+ unsigned int mask_clr;
+ unsigned int sens;
+ unsigned int sens_set;
+ unsigned int sens_clr;
+ unsigned int soft;
+ unsigned int soft_set;
+ unsigned int soft_clr;
+ unsigned int pol;
+ unsigned int pol_set;
+ unsigned int pol_clr;
+ unsigned int dom_en;
+ unsigned int dbnc_ctrl;
+ unsigned int dbnc_set;
+ unsigned int dbnc_clr;
+};
+
+struct mtk_eint_hw {
+ u8 port_mask;
+ u8 ports;
+ unsigned int ap_num;
+ unsigned int db_cnt;
+};
+
+struct mtk_eint;
+
+struct mtk_eint_xt {
+ int (*get_gpio_n)(void *data, unsigned long eint_n,
+ unsigned int *gpio_n,
+ struct gpio_chip **gpio_chip);
+ int (*get_gpio_state)(void *data, unsigned long eint_n);
+ int (*set_gpio_as_eint)(void *data, unsigned long eint_n);
+};
+
+struct mtk_eint {
+ struct device *dev;
+ void __iomem *base;
+ struct irq_domain *domain;
+ int irq;
+
+ int *dual_edge;
+ u32 *wake_mask;
+ u32 *cur_mask;
+
+ /* Used to fit into various EINT device */
+ const struct mtk_eint_hw *hw;
+ const struct mtk_eint_regs *regs;
+
+ /* Used to fit into various pinctrl device */
+ void *pctl;
+ const struct mtk_eint_xt *gpio_xlate;
+};
+
+#if IS_ENABLED(CONFIG_EINT_MTK)
+int mtk_eint_do_init(struct mtk_eint *eint);
+int mtk_eint_do_suspend(struct mtk_eint *eint);
+int mtk_eint_do_resume(struct mtk_eint *eint);
+int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
+ unsigned int debounce);
+int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n);
+
+#else
+static inline int mtk_eint_do_init(struct mtk_eint *eint)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_do_suspend(struct mtk_eint *eint)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_do_resume(struct mtk_eint *eint)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_set_debounce(struct mtk_eint *eint,
+ unsigned long eint_n, unsigned int debounce)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+#endif /* __MTK_EINT_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2701.c
new file mode 100644
index 0000000..3bcfbbf
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2701.h"
+
+/**
+ * struct mtk_spec_pinmux_set
+ * - For special pins' mode setting
+ * @pin: The pin number.
+ * @offset: The offset of extra setting register.
+ * @bit: The bit of extra setting register.
+ */
+struct mtk_spec_pinmux_set {
+ unsigned short pin;
+ unsigned short offset;
+ unsigned char bit;
+};
+
+#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
+ { \
+ .pin = _pin, \
+ .offset = _offset, \
+ .bit = _bit, \
+ }
+
+static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
+ MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
+ MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
+ MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
+ MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
+ MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
+ MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
+ MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
+ MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
+ MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
+ MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
+ MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
+ MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
+ MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
+ MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
+ MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
+ MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
+ MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
+ MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14, 0),/* ms0 data7 */
+ MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10, 0), /* ms0 data6 */
+ MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6, 0), /* ms0 data5 */
+ MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2, 0), /* ms0 data4 */
+ MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2, 0), /* ms0 rstb */
+ MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10, 0), /* ms0 cmd */
+ MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10, 0), /* ms0 clk */
+ MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14, 0),/* ms0 data3 */
+ MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10, 0), /* ms0 data2 */
+ MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6, 0), /* ms0 data1 */
+ MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2, 0), /* ms0 data0 */
+
+ MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10, 0), /* ms1 cmd */
+ MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10, 0), /* ms1 clk */
+ MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2, 0), /* ms1 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8, 0), /* ms1 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6, 0), /* ms1 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14, 0),/* ms1 dat3 */
+
+ MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10, 0), /* ms2 cmd */
+ MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10, 0), /* ms2 clk */
+ MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2, 0), /* ms2 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8, 0), /* ms2 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6, 0), /* ms2 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14, 0), /* ms2 dat3 */
+
+ MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2, 0), /* ms0e rstb */
+ MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14, 0),/* ms0e dat7 */
+ MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10, 0), /* ms0e dat6 */
+ MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6, 0), /* ms0e dat5 */
+ MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2, 0), /* ms0e dat4 */
+ MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14, 0),/* ms0e dat3 */
+ MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10, 0), /* ms0e dat2 */
+ MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6, 0), /* ms0e dat1 */
+ MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2, 0), /* ms0e dat0 */
+ MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10, 0), /* ms0e cmd */
+ MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10, 0), /* ms0e clk */
+ MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10, 0), /* ms1 ins */
+};
+
+static int mt2701_spec_pull_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(pctl, regmap, mt2701_spec_pupd,
+ ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
+ MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
+ MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
+ MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
+ MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
+ MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
+ MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
+ MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
+ MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
+ MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
+ MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
+ MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
+ MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
+ MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
+ MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
+ MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
+ MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
+ MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
+ MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
+ MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
+ MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
+ MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
+ MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
+ MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
+ MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
+ MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
+ MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
+ MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
+ MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
+ MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
+ MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
+ MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
+ MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
+ MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
+ MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
+ MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
+ MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
+ MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
+ MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
+ MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
+ MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
+ MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
+ MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
+ MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
+ MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
+ MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
+ MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
+ MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
+ MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
+ MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
+ MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
+ MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
+ MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
+ MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
+ MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
+ MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
+ MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
+ MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
+ MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
+ MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
+ MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
+ MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
+ MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
+ MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
+ MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
+ MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
+ MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
+ MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
+};
+
+static int mt2701_ies_smt_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
+ ARRAY_SIZE(mt2701_ies_set), pin, align, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
+ ARRAY_SIZE(mt2701_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
+ MTK_PINMUX_SPEC(22, 0xb10, 3),
+ MTK_PINMUX_SPEC(23, 0xb10, 4),
+ MTK_PINMUX_SPEC(24, 0xb10, 5),
+ MTK_PINMUX_SPEC(29, 0xb10, 9),
+ MTK_PINMUX_SPEC(208, 0xb10, 7),
+ MTK_PINMUX_SPEC(209, 0xb10, 8),
+ MTK_PINMUX_SPEC(203, 0xf20, 0),
+ MTK_PINMUX_SPEC(204, 0xf20, 1),
+ MTK_PINMUX_SPEC(249, 0xef0, 0),
+ MTK_PINMUX_SPEC(250, 0xef0, 0),
+ MTK_PINMUX_SPEC(251, 0xef0, 0),
+ MTK_PINMUX_SPEC(252, 0xef0, 0),
+ MTK_PINMUX_SPEC(253, 0xef0, 0),
+ MTK_PINMUX_SPEC(254, 0xef0, 0),
+ MTK_PINMUX_SPEC(255, 0xef0, 0),
+ MTK_PINMUX_SPEC(256, 0xef0, 0),
+ MTK_PINMUX_SPEC(257, 0xef0, 0),
+ MTK_PINMUX_SPEC(258, 0xef0, 0),
+ MTK_PINMUX_SPEC(259, 0xef0, 0),
+ MTK_PINMUX_SPEC(260, 0xef0, 0),
+};
+
+static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
+ unsigned int mode)
+{
+ unsigned int i, value, mask;
+ unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
+ unsigned int spec_flag;
+
+ for (i = 0; i < info_num; i++) {
+ if (pin == mt2701_spec_pinmux[i].pin)
+ break;
+ }
+
+ if (i == info_num)
+ return;
+
+ spec_flag = (mode >> 3);
+ mask = BIT(mt2701_spec_pinmux[i].bit);
+ if (!spec_flag)
+ value = mask;
+ else
+ value = 0;
+ regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
+}
+
+static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
+{
+ if (pin > 175)
+ *reg_addr += 0x10;
+}
+
+static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
+ .pins = mtk_pins_mt2701,
+ .npins = ARRAY_SIZE(mtk_pins_mt2701),
+ .grp_desc = mt2701_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
+ .pin_drv_grp = mt2701_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
+ .spec_pull_set = mt2701_spec_pull_set,
+ .spec_ies_smt_set = mt2701_ies_smt_set,
+ .spec_pinmux_set = mt2701_spec_pinmux_set,
+ .spec_dir_set = mt2701_spec_dir_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0150,
+ .pullsel_offset = 0x0280,
+ .dout_offset = 0x0500,
+ .din_offset = 0x0630,
+ .pinmux_offset = 0x0760,
+ .type1_start = 280,
+ .type1_end = 280,
+ .regmap_num = 1,
+ .port_shf = 4,
+ .port_mask = 0x1f,
+ .port_align = 4,
+ .port_pin_shf = 4,
+ .eint_offsets = {
+ .name = "mt2701_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 6,
+ .ports = 6,
+ },
+ .ap_num = 169,
+ .db_cnt = 16,
+};
+
+static int mt2701_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt2701_pctrl_match[] = {
+ { .compatible = "mediatek,mt2701-pinctrl", },
+ { .compatible = "mediatek,mt7623-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt2701_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt2701-pinctrl",
+ .of_match_table = mt2701_pctrl_match,
+ .pm = &mtk_eint_pm_ops,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2731.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2731.c
new file mode 100644
index 0000000..e38ba56
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt2731.c
@@ -0,0 +1,828 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng <andy.teng@mediatek.com>
+ *
+ */
+
+#include "pinctrl-mtk-mt2731.h"
+#include "pinctrl-paris.h"
+
+/* MT2731 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_lm:0x10002000, iocfg_lb:0x10002200,
+ * iocfg_bl:0x10002400, iocfg_br:0x10002600, iocfg_rb:0x10002800,
+ * iocfg_rm:0x10002A00, iocfg_tr:0x10002C00, iocfg_tl:0x10002E00
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+static const struct mtk_pin_field_calc mt2731_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 160, 0, 0x0440, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 160, 0, 0x0050, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_di_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 160, 0, 0x0250, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_do_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 160, 0, 0x0150, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 2, 1, 0x00b0, 0x10, 2, 1),
+ PIN_FIELD_BASE(3, 3, 3, 0x00b0, 0x10, 3, 1),
+ PIN_FIELD_BASE(4, 7, 2, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 9, 3, 0x00b0, 0x10, 4, 1),
+ PIN_FIELD_BASE(10, 12, 5, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(13, 13, 2, 0x00a0, 0x10, 17, 1),
+ PIN_FIELD_BASE(14, 15, 2, 0x00a0, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 1, 0x00b0, 0x10, 22, 1),
+ PIN_FIELD_BASE(17, 17, 1, 0x00b0, 0x10, 24, 1),
+ PIN_FIELD_BASE(18, 18, 1, 0x00b0, 0x10, 23, 1),
+ PIN_FIELD_BASE(19, 19, 1, 0x00b0, 0x10, 25, 1),
+ PIN_FIELD_BASE(20, 20, 1, 0x00b0, 0x10, 16, 1),
+ PIN_FIELD_BASE(21, 23, 1, 0x00b0, 0x10, 13, 1),
+ PIN_FIELD_BASE(24, 24, 1, 0x00b0, 0x10, 1, 1),
+ PIN_FIELD_BASE(25, 25, 1, 0x00b0, 0x10, 5, 1),
+ PIN_FIELD_BASE(26, 26, 1, 0x00b0, 0x10, 21, 1),
+ PIN_FIELD_BASE(27, 27, 1, 0x00b0, 0x10, 20, 1),
+ PIN_FIELD_BASE(28, 28, 1, 0x00b0, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, 1, 0x00b0, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 1, 0x00b0, 0x10, 12, 1),
+ PIN_FIELD_BASE(31, 32, 1, 0x00b0, 0x10, 6, 1),
+ PIN_FIELD_BASE(33, 33, 1, 0x00b0, 0x10, 11, 1),
+ PIN_FIELD_BASE(34, 34, 1, 0x00b0, 0x10, 10, 1),
+ PIN_FIELD_BASE(35, 35, 1, 0x00b0, 0x10, 9, 1),
+ PIN_FIELD_BASE(36, 36, 1, 0x00b0, 0x10, 8, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x00a0, 0x10, 9, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x00a0, 0x10, 6, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x00a0, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 41, 2, 0x00a0, 0x10, 7, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x00a0, 0x10, 5, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 8, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(45, 45, 8, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(46, 46, 8, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(47, 48, 2, 0x00a0, 0x10, 12, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x00a0, 0x10, 11, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x00a0, 0x10, 14, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x00b0, 0x10, 9, 1),
+ PIN_FIELD_BASE(52, 54, 3, 0x00b0, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x00b0, 0x10, 10, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x00b0, 0x10, 18, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x00b0, 0x10, 17, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x00b0, 0x10, 11, 1),
+ PIN_FIELD_BASE(59, 59, 3, 0x00b0, 0x10, 13, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x00b0, 0x10, 17, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x00b0, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x00b0, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x00b0, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x00b0, 0x10, 12, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x00b0, 0x10, 0, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x00b0, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, 3, 0x00b0, 0x10, 1, 1),
+ PIN_FIELD_BASE(68, 70, 3, 0x00b0, 0x10, 19, 1),
+ PIN_FIELD_BASE(71, 71, 3, 0x00b0, 0x10, 18, 1),
+ PIN_FIELD_BASE(72, 72, 3, 0x00b0, 0x10, 22, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0090, 0x10, 14, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0090, 0x10, 13, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0090, 0x10, 12, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x0090, 0x10, 15, 1),
+ PIN_FIELD_BASE(79, 80, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(81, 81, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(82, 82, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(85, 85, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(87, 87, 4, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(88, 88, 4, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 92, 4, 0x0090, 0x10, 16, 1),
+ PIN_FIELD_BASE(93, 93, 5, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(94, 94, 5, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(95, 96, 5, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(97, 97, 5, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(98, 98, 5, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(99, 99, 5, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(100, 100, 5, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(101, 101, 5, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(102, 102, 5, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 5, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(104, 105, 5, 0x0080, 0x10, 18, 1),
+ PIN_FIELD_BASE(106, 106, 5, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(107, 107, 5, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(108, 108, 5, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(109, 109, 5, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(110, 111, 6, 0x00e0, 0x10, 23, 1),
+ PIN_FIELD_BASE(112, 112, 6, 0x00e0, 0x10, 22, 1),
+ PIN_FIELD_BASE(113, 114, 6, 0x00e0, 0x10, 20, 1),
+ PIN_FIELD_BASE(115, 115, 6, 0x00e0, 0x10, 19, 1),
+ PIN_FIELD_BASE(116, 116, 6, 0x00e0, 0x10, 15, 1),
+ PIN_FIELD_BASE(117, 117, 6, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(118, 118, 6, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(119, 119, 6, 0x00e0, 0x10, 12, 1),
+ PIN_FIELD_BASE(120, 120, 6, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(121, 121, 6, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(122, 122, 6, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(123, 123, 6, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(124, 124, 6, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(125, 125, 6, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(126, 126, 6, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(127, 127, 6, 0x00e0, 0x10, 16, 1),
+ PIN_FIELD_BASE(128, 129, 6, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(130, 130, 6, 0x00e0, 0x10, 17, 1),
+ PIN_FIELD_BASE(131, 131, 6, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(132, 133, 6, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(134, 134, 7, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(135, 135, 7, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(136, 137, 7, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(138, 138, 7, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(139, 139, 7, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 140, 7, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(141, 141, 7, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(142, 142, 7, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(143, 143, 7, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(144, 144, 7, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(145, 145, 7, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x00e0, 0x10, 18, 1),
+ PIN_FIELD_BASE(147, 155, 8, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 156, 8, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(157, 158, 8, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(159, 159, 8, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(160, 160, 8, 0x0080, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 2, 1, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(3, 3, 3, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(4, 7, 2, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 9, 3, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(10, 12, 5, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(13, 13, 2, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(14, 15, 2, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 1, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(17, 17, 1, 0x0030, 0x10, 24, 1),
+ PIN_FIELD_BASE(18, 18, 1, 0x0030, 0x10, 23, 1),
+ PIN_FIELD_BASE(19, 19, 1, 0x0030, 0x10, 25, 1),
+ PIN_FIELD_BASE(20, 20, 1, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(21, 23, 1, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(24, 24, 1, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(25, 25, 1, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(26, 26, 1, 0x0030, 0x10, 21, 1),
+ PIN_FIELD_BASE(27, 27, 1, 0x0030, 0x10, 20, 1),
+ PIN_FIELD_BASE(28, 28, 1, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, 1, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 1, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(31, 32, 1, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(33, 33, 1, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(34, 34, 1, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(35, 35, 1, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(36, 36, 1, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 41, 2, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 8, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(45, 45, 8, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(46, 46, 8, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(47, 48, 2, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(52, 54, 3, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(59, 59, 3, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(68, 70, 3, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(79, 80, 4, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(81, 81, 4, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(82, 82, 4, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 4, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 4, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(85, 85, 4, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 4, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(87, 87, 4, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(88, 88, 4, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 92, 4, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(93, 93, 5, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(94, 94, 5, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(95, 96, 5, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(97, 97, 5, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(98, 98, 5, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(99, 99, 5, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(100, 100, 5, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(101, 101, 5, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(102, 102, 5, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 5, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(104, 105, 5, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(106, 106, 5, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(107, 107, 5, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(108, 108, 5, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(109, 109, 5, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(110, 111, 6, 0x0030, 0x10, 23, 1),
+ PIN_FIELD_BASE(112, 112, 6, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(113, 114, 6, 0x0030, 0x10, 20, 1),
+ PIN_FIELD_BASE(115, 115, 6, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(116, 116, 6, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(117, 117, 6, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(118, 118, 6, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(119, 119, 6, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(120, 120, 6, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(121, 121, 6, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(122, 122, 6, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(123, 123, 6, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(124, 124, 6, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(125, 125, 6, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(126, 126, 6, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(127, 127, 6, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(128, 129, 6, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(130, 130, 6, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(131, 131, 6, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(132, 133, 6, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(134, 134, 7, 0x0020, 0x10, 8, 1),
+ PIN_FIELD_BASE(135, 135, 7, 0x0020, 0x10, 7, 1),
+ PIN_FIELD_BASE(136, 137, 7, 0x0020, 0x10, 9, 1),
+ PIN_FIELD_BASE(138, 138, 7, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(139, 139, 7, 0x0020, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 140, 7, 0x0020, 0x10, 11, 1),
+ PIN_FIELD_BASE(141, 141, 7, 0x0020, 0x10, 2, 1),
+ PIN_FIELD_BASE(142, 142, 7, 0x0020, 0x10, 1, 1),
+ PIN_FIELD_BASE(143, 143, 7, 0x0020, 0x10, 4, 1),
+ PIN_FIELD_BASE(144, 144, 7, 0x0020, 0x10, 6, 1),
+ PIN_FIELD_BASE(145, 145, 7, 0x0020, 0x10, 3, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(147, 155, 8, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 156, 8, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(157, 158, 8, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(159, 159, 8, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(160, 160, 8, 0x0030, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_pu_range[] = {
+ PIN_FIELD_BASE(0, 2, 1, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(3, 3, 3, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(4, 7, 2, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 9, 3, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(10, 12, 5, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(13, 13, 2, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(14, 15, 2, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 1, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(17, 17, 1, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(18, 18, 1, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(19, 19, 1, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(20, 20, 1, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(21, 23, 1, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(24, 24, 1, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(25, 25, 1, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(26, 26, 1, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(27, 27, 1, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(28, 28, 1, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(29, 29, 1, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 41, 2, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 8, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(45, 45, 8, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(46, 46, 8, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(47, 48, 2, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(52, 54, 3, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, 3, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(68, 70, 3, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(71, 71, 3, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(72, 72, 3, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(79, 80, 4, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(81, 81, 4, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(82, 82, 4, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 4, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 4, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(85, 85, 4, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 4, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(87, 87, 4, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(88, 88, 4, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 92, 4, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(93, 93, 5, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(94, 94, 5, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(95, 96, 5, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(97, 97, 5, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(98, 98, 5, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(99, 99, 5, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(100, 100, 5, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(101, 101, 5, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(102, 102, 5, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 5, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(104, 105, 5, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(106, 106, 5, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(107, 107, 5, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(108, 108, 5, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(109, 109, 5, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(116, 116, 6, 0x0070, 0x10, 15, 1),
+ PIN_FIELD_BASE(117, 117, 6, 0x0070, 0x10, 14, 1),
+ PIN_FIELD_BASE(118, 118, 6, 0x0070, 0x10, 13, 1),
+ PIN_FIELD_BASE(119, 119, 6, 0x0070, 0x10, 12, 1),
+ PIN_FIELD_BASE(120, 120, 6, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(121, 121, 6, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(122, 122, 6, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(123, 123, 6, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(124, 124, 6, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(125, 125, 6, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(126, 126, 6, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(127, 127, 6, 0x0070, 0x10, 16, 1),
+ PIN_FIELD_BASE(128, 129, 6, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(130, 130, 6, 0x0070, 0x10, 17, 1),
+ PIN_FIELD_BASE(131, 131, 6, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(132, 133, 6, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 18, 1),
+ PIN_FIELD_BASE(147, 155, 8, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 156, 8, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(157, 158, 8, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(159, 159, 8, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(160, 160, 8, 0x0050, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_pd_range[] = {
+ PIN_FIELD_BASE(0, 2, 1, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(3, 3, 3, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(4, 7, 2, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 9, 3, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(10, 12, 5, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(13, 13, 2, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(14, 15, 2, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 1, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(17, 17, 1, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(18, 18, 1, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(19, 19, 1, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(20, 20, 1, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(21, 23, 1, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(24, 24, 1, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(25, 25, 1, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(26, 26, 1, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(27, 27, 1, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(28, 28, 1, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(29, 29, 1, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 41, 2, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 8, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(45, 45, 8, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(46, 46, 8, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(47, 48, 2, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(52, 54, 3, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(56, 56, 1, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(57, 57, 1, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(68, 70, 3, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(78, 78, 4, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(79, 80, 4, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(81, 81, 4, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(82, 82, 4, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 4, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 4, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(85, 85, 4, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 4, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(87, 87, 4, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(88, 88, 4, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 92, 4, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(93, 93, 5, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(94, 94, 5, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(95, 96, 5, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(97, 97, 5, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(98, 98, 5, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(99, 99, 5, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(100, 100, 5, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(101, 101, 5, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(102, 102, 5, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 5, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(104, 105, 5, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(106, 106, 5, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(107, 107, 5, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(108, 108, 5, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(109, 109, 5, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(116, 116, 6, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(117, 117, 6, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(118, 118, 6, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(119, 119, 6, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(120, 120, 6, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(121, 121, 6, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(122, 122, 6, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(123, 123, 6, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(124, 124, 6, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(125, 125, 6, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(126, 126, 6, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(127, 127, 6, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(128, 129, 6, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(130, 130, 6, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(131, 131, 6, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(132, 133, 6, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(147, 155, 8, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 156, 8, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(157, 158, 8, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(159, 159, 8, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(160, 160, 8, 0x0040, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 2, 1, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(3, 3, 3, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(4, 7, 2, 0x0000, 0x10, 0, 2),
+ PIN_FIELD_BASE(8, 9, 3, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(10, 12, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(13, 13, 2, 0x0010, 0x10, 8, 2),
+ PIN_FIELD_BASE(14, 15, 2, 0x0010, 0x10, 4, 2),
+ PIN_FIELD_BASE(16, 16, 1, 0x0020, 0x10, 6, 3),
+ PIN_FIELD_BASE(17, 17, 1, 0x0020, 0x10, 12, 3),
+ PIN_FIELD_BASE(18, 18, 1, 0x0020, 0x10, 9, 3),
+ PIN_FIELD_BASE(19, 19, 1, 0x0020, 0x10, 15, 3),
+ PIN_FIELD_BASE(20, 20, 1, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(21, 23, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(24, 24, 1, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(25, 25, 1, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(26, 26, 1, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(27, 27, 1, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(28, 28, 1, 0x0010, 0x10, 27, 3),
+ PIN_FIELD_BASE(29, 29, 1, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(30, 30, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(31, 32, 1, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(33, 33, 1, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(34, 34, 1, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(35, 35, 1, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(36, 36, 1, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 22, 3),
+ PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 13, 3),
+ PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 25, 3),
+ PIN_FIELD_BASE(40, 41, 2, 0x0000, 0x10, 16, 3),
+ PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 10, 3),
+ PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 8, 2),
+ PIN_FIELD_BASE(44, 44, 8, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(45, 45, 8, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(46, 46, 8, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(47, 47, 2, 0x0000, 0x10, 30, 2),
+ PIN_FIELD_BASE(48, 48, 2, 0x0010, 0x10, 0, 2),
+ PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 28, 2),
+ PIN_FIELD_BASE(50, 50, 2, 0x0010, 0x10, 2, 2),
+ PIN_FIELD_BASE(51, 51, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(52, 54, 3, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(56, 56, 1, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(57, 57, 1, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(58, 58, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(59, 59, 3, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(60, 60, 3, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(61, 61, 3, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(62, 62, 3, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(63, 63, 3, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(64, 64, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(67, 67, 3, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(68, 68, 3, 0x0010, 0x10, 27, 3),
+ PIN_FIELD_BASE(69, 70, 3, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(71, 71, 3, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(72, 72, 3, 0x0020, 0x10, 6, 3),
+ PIN_FIELD_BASE(73, 73, 4, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(74, 74, 4, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(75, 75, 4, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(76, 76, 4, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(77, 77, 4, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(78, 78, 4, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(79, 80, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(81, 81, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(82, 82, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(83, 83, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(84, 84, 4, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(85, 85, 4, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(86, 86, 4, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(87, 87, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(88, 88, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(89, 92, 4, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(93, 93, 5, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(94, 94, 5, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(95, 96, 5, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(97, 97, 5, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(99, 99, 5, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(100, 100, 5, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(101, 101, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(102, 102, 5, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(103, 103, 5, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(104, 105, 5, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(106, 106, 5, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(107, 107, 5, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(108, 108, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(109, 109, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(110, 111, 6, 0x0010, 0x10, 14, 2),
+ PIN_FIELD_BASE(112, 112, 6, 0x0010, 0x10, 12, 2),
+ PIN_FIELD_BASE(113, 114, 6, 0x0010, 0x10, 8, 2),
+ PIN_FIELD_BASE(115, 115, 6, 0x0010, 0x10, 6, 2),
+ PIN_FIELD_BASE(116, 116, 6, 0x0000, 0x10, 30, 2),
+ PIN_FIELD_BASE(117, 117, 6, 0x0000, 0x10, 28, 2),
+ PIN_FIELD_BASE(118, 118, 6, 0x0000, 0x10, 26, 2),
+ PIN_FIELD_BASE(119, 119, 6, 0x0000, 0x10, 24, 2),
+ PIN_FIELD_BASE(120, 120, 6, 0x0000, 0x10, 16, 2),
+ PIN_FIELD_BASE(121, 121, 6, 0x0000, 0x10, 14, 2),
+ PIN_FIELD_BASE(122, 122, 6, 0x0000, 0x10, 12, 2),
+ PIN_FIELD_BASE(123, 123, 6, 0x0000, 0x10, 10, 2),
+ PIN_FIELD_BASE(124, 124, 6, 0x0000, 0x10, 22, 2),
+ PIN_FIELD_BASE(125, 125, 6, 0x0000, 0x10, 8, 2),
+ PIN_FIELD_BASE(126, 126, 6, 0x0000, 0x10, 18, 2),
+ PIN_FIELD_BASE(127, 127, 6, 0x0010, 0x10, 0, 2),
+ PIN_FIELD_BASE(128, 129, 6, 0x0000, 0x10, 4, 2),
+ PIN_FIELD_BASE(130, 130, 6, 0x0010, 0x10, 2, 2),
+ PIN_FIELD_BASE(131, 131, 6, 0x0000, 0x10, 20, 2),
+ PIN_FIELD_BASE(132, 133, 6, 0x0000, 0x10, 0, 2),
+ PIN_FIELD_BASE(134, 134, 7, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(135, 135, 7, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(136, 136, 7, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(137, 137, 7, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(138, 138, 7, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(139, 139, 7, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(140, 140, 7, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(141, 141, 7, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(142, 142, 7, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(143, 143, 7, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(144, 144, 7, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(145, 145, 7, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 4, 2),
+ PIN_FIELD_BASE(147, 155, 8, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(156, 156, 8, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(157, 158, 8, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(159, 159, 8, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(160, 160, 8, 0x0000, 0x10, 27, 3),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_pupd_range[] = {
+ PIN_FIELD_BASE(30, 30, 1, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(31, 32, 1, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(33, 33, 1, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(34, 34, 1, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(35, 35, 1, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(36, 36, 1, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 3, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(110, 111, 6, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(112, 112, 6, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(113, 114, 6, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(115, 115, 6, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(134, 134, 7, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(135, 135, 7, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(136, 137, 7, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(138, 138, 7, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(139, 139, 7, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 140, 7, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(141, 141, 7, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(142, 142, 7, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(143, 143, 7, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(144, 144, 7, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(145, 145, 7, 0x0030, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_r0_range[] = {
+ PIN_FIELD_BASE(30, 30, 1, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(31, 32, 1, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(33, 33, 1, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(34, 34, 1, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(35, 35, 1, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(36, 36, 1, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 3, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(110, 111, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(112, 112, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(113, 114, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(115, 115, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(134, 134, 7, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(135, 135, 7, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(136, 137, 7, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(138, 138, 7, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(139, 139, 7, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 140, 7, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(141, 141, 7, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(142, 142, 7, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(143, 143, 7, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(144, 144, 7, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(145, 145, 7, 0x0040, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt2731_pin_r1_range[] = {
+ PIN_FIELD_BASE(30, 30, 1, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(31, 32, 1, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(36, 36, 1, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, 3, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(110, 111, 6, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(112, 112, 6, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(113, 114, 6, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(115, 115, 6, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(134, 134, 7, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(135, 135, 7, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(136, 137, 7, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(138, 138, 7, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(139, 139, 7, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 140, 7, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(141, 141, 7, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(142, 142, 7, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(143, 143, 7, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(144, 144, 7, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(145, 145, 7, 0x0050, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_reg_calc mt2731_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt2731_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt2731_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt2731_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt2731_pin_do_range),
+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt2731_pin_dir_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt2731_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt2731_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt2731_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt2731_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt2731_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt2731_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt2731_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt2731_pin_r1_range),
+};
+
+static const char * const mt2731_pinctrl_register_base_names[] = {
+ "gpio", "iocfg_lm", "iocfg_lb", "iocfg_bl", "iocfg_br",
+ "iocfg_rb", "iocfg_rm", "iocfg_tr", "iocfg_tl",
+};
+
+static const struct mtk_eint_hw mt2731_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = ARRAY_SIZE(mtk_pins_mt2731),
+ .db_cnt = 13,
+};
+
+static const struct mtk_pin_soc mt2731_data = {
+ .reg_cal = mt2731_reg_cals,
+ .pins = mtk_pins_mt2731,
+ .npins = ARRAY_SIZE(mtk_pins_mt2731),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt2731),
+ .eint_hw = &mt2731_eint_hw,
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+ .pins_dir = mtk_bi_dir_mapping_mt2731,
+ .npins_dir = ARRAY_SIZE(mtk_bi_dir_mapping_mt2731),
+#endif
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mt2731_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt2731_pinctrl_register_base_names),
+ .bias_disable_set = mtk_pinconf_bias_disable_set,
+ .bias_disable_get = mtk_pinconf_bias_disable_get,
+ .bias_set = mtk_pinconf_bias_set,
+ .bias_get = mtk_pinconf_bias_get,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt2731_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt2731-pinctrl", },
+ { }
+};
+
+static int mt2731_pinctrl_probe(struct platform_device *pdev)
+{
+ void __iomem *event_mask = ioremap(0x1000B880, 0x16);
+ unsigned int i;
+
+ /*
+ * Set all event_mask unmasked to avoid wakeup source
+ * blocked in suspend
+ */
+ for (i = 0; i < 5; i++) {
+ writel(0xffffffff, event_mask);
+ event_mask += 4;
+ }
+
+ return mtk_paris_pinctrl_probe(pdev, &mt2731_data);
+}
+
+static struct platform_driver mt2731_pinctrl_driver = {
+ .driver = {
+ .name = "mt2731-pinctrl",
+ .of_match_table = mt2731_pinctrl_of_match,
+ },
+ .probe = mt2731_pinctrl_probe,
+};
+
+static int __init mt2731_pinctrl_init(void)
+{
+ return platform_driver_register(&mt2731_pinctrl_driver);
+}
+arch_initcall(mt2731_pinctrl_init);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt6397.c
new file mode 100644
index 0000000..198b107
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt6397.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/mfd/mt6397/core.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt6397.h"
+
+#define MT6397_PIN_REG_BASE 0xc000
+
+static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = {
+ .pins = mtk_pins_mt6397,
+ .npins = ARRAY_SIZE(mtk_pins_mt6397),
+ .dir_offset = (MT6397_PIN_REG_BASE + 0x000),
+ .ies_offset = MTK_PINCTRL_NOT_SUPPORT,
+ .smt_offset = MTK_PINCTRL_NOT_SUPPORT,
+ .pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
+ .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
+ .dout_offset = (MT6397_PIN_REG_BASE + 0x080),
+ .din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
+ .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
+ .type1_start = 41,
+ .type1_end = 41,
+ .regmap_num = 1,
+ .port_shf = 3,
+ .port_mask = 0x3,
+ .port_align = 2,
+ .port_pin_shf = 4,
+};
+
+static int mt6397_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mt6397_chip *mt6397;
+
+ mt6397 = dev_get_drvdata(pdev->dev.parent);
+ return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap);
+}
+
+static const struct of_device_id mt6397_pctrl_match[] = {
+ { .compatible = "mediatek,mt6397-pinctrl", },
+ { }
+};
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt6397_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt6397-pinctrl",
+ .of_match_table = mt6397_pctrl_match,
+ },
+};
+
+builtin_platform_driver(mtk_pinctrl_driver);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8127.c
new file mode 100644
index 0000000..f2383d7
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8127.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ * Yingjoe Chen <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8127.h"
+
+static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
+ MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
+ MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
+ MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
+ MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
+ MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
+ MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
+ MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
+ MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
+ MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
+ MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
+ MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
+ MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
+ MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
+ MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
+ MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
+ MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
+ MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
+ MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
+ MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
+ MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
+ MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
+ MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
+ MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
+ MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
+ MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
+ MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
+ MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
+ MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
+ MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
+ MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
+ MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
+ MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
+ MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
+ MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
+ MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
+ MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
+ MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
+ MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
+ MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
+ MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
+ MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
+ MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
+ MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
+ MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
+ MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
+ MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
+ MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
+ MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
+ MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
+ MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
+ MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
+ MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
+ MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
+ MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
+ MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
+ MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
+ MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
+ MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
+ MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
+ MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
+ MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
+ MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
+ MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
+ MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
+ MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1, 0), /* KPROW0 */
+ MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5, 0), /* KPROW1 */
+ MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9, 0), /* KPROW2 */
+ MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1, 0), /* KPCOL0 */
+ MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5, 0), /* KPCOL1 */
+ MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9, 0), /* KPCOL2 */
+ MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1, 0), /* EINT14 */
+ MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5, 0), /* EINT15 */
+ MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9, 0), /* EINT16 */
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13, 0),/* EINT17 */
+ MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9, 0), /* MSDC2_CMD */
+ MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9, 0), /* MSDC2_CLK */
+ MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1, 0), /* MSDC2_DAT0 */
+ MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5, 0), /* MSDC2_DAT1 */
+ MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9, 0), /* MSDC2_DAT2 */
+ MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13, 0),/* MSDC2_DAT3 */
+ MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9, 0), /* MSDC1_CMD */
+ MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9, 0), /* MSDC1_CLK */
+ MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1, 0), /* MSDC1_DAT0 */
+ MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5, 0), /* MSDC1_DAT1 */
+ MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9, 0), /* MSDC1_DAT2 */
+ MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13, 0),/* MSDC1_DAT3 */
+ MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13, 0),/* MSDC0_DAT7 */
+ MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9, 0), /* MSDC0_DAT6 */
+ MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5, 0), /* MSDC0_DAT5 */
+ MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1, 0), /* MSDC0_DAT4 */
+ MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1, 0), /* MSDC0_RSTB */
+ MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9, 0), /* MSDC0_CMD */
+ MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9, 0), /* MSDC0_CLK */
+ MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13, 0),/* MSDC0_DAT3 */
+ MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9, 0), /* MSDC0_DAT2 */
+ MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5, 0), /* MSDC0_DAT1 */
+ MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1, 0), /* MSDC0_DAT0 */
+ MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1, 0), /* EINT21 */
+};
+
+static int mt8127_spec_pull_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(pctl, regmap, mt8127_spec_pupd,
+ ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
+ MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
+ MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
+ MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
+ MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
+ MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
+ MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
+ MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
+ MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
+ MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
+ MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
+ MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
+ MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
+ MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
+ MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
+ MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
+ MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
+ MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
+ MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
+ MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
+ MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
+ MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
+ MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
+ MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
+ MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
+ MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
+ MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
+ MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
+ MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
+ MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
+ MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
+ MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
+ MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
+ MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
+ MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
+ MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
+ MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
+ MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
+ MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
+ MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
+ MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
+ MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
+ MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
+ MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
+ MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
+ MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
+};
+
+static int mt8127_ies_smt_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
+ ARRAY_SIZE(mt8127_ies_set), pin, align, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
+ ARRAY_SIZE(mt8127_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+
+static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
+ .pins = mtk_pins_mt8127,
+ .npins = ARRAY_SIZE(mtk_pins_mt8127),
+ .grp_desc = mt8127_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
+ .pin_drv_grp = mt8127_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
+ .spec_pull_set = mt8127_spec_pull_set,
+ .spec_ies_smt_set = mt8127_ies_smt_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0100,
+ .pullsel_offset = 0x0200,
+ .dout_offset = 0x0400,
+ .din_offset = 0x0500,
+ .pinmux_offset = 0x0600,
+ .type1_start = 143,
+ .type1_end = 143,
+ .regmap_num = 1,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+ .port_pin_shf = 4,
+ .eint_offsets = {
+ .name = "mt8127_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 7,
+ .ports = 6,
+ },
+ .ap_num = 143,
+ .db_cnt = 16,
+};
+
+static int mt8127_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt8127_pctrl_match[] = {
+ { .compatible = "mediatek,mt8127-pinctrl", },
+ { }
+};
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt8127_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt8127-pinctrl",
+ .of_match_table = mt8127_pctrl_match,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8135.c
new file mode 100644
index 0000000..2a134fe
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8135.h"
+
+#define DRV_BASE1 0x500
+#define DRV_BASE2 0x510
+#define PUPD_BASE1 0x400
+#define PUPD_BASE2 0x450
+#define R0_BASE1 0x4d0
+#define R1_BASE1 0x200
+#define R1_BASE2 0x250
+
+struct mtk_spec_pull_set {
+ unsigned char pin;
+ unsigned char pupd_bit;
+ unsigned short pupd_offset;
+ unsigned short r0_offset;
+ unsigned short r1_offset;
+ unsigned char r0_bit;
+ unsigned char r1_bit;
+};
+
+#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
+ _r0_bit, _r1_offset, _r1_bit) \
+ { \
+ .pin = _pin, \
+ .pupd_offset = _pupd_offset, \
+ .pupd_bit = _pupd_bit, \
+ .r0_offset = _r0_offset, \
+ .r0_bit = _r0_bit, \
+ .r1_offset = _r1_offset, \
+ .r1_bit = _r1_bit, \
+ }
+
+static const struct mtk_drv_group_desc mt8135_drv_grp[] = {
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2),
+ /* E8E4 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* E4E2 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 0, 1, 2),
+ /* E16E8E4 4/8/12/16/20/24/28/32 */
+ MTK_DRV_GRP(4, 32, 0, 2, 4)
+};
+
+static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
+ MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
+ MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
+ MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
+
+ MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
+ MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
+ MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
+ MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
+ MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
+ MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
+ MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
+ MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
+ MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
+ MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
+ MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
+ MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
+ MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
+ MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
+ MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
+
+ MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
+ MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
+ MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
+ MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
+ MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
+ MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
+ MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
+ MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
+
+ MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
+ MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
+ MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
+ MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
+ MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
+ MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
+ MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
+ MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
+
+ MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
+ MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
+ MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
+ MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
+ MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
+ MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
+ MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
+ MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
+ MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
+
+ MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
+ MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
+
+ MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
+ MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
+
+ MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
+ MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
+ MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
+ MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
+ MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
+ MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
+
+ MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
+
+ MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
+
+ MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
+ MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
+ MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
+ MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
+ MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
+
+
+ MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
+ MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
+ MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
+ MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
+ MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
+ MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
+ MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
+ MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
+ MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
+ MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
+ MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
+
+ MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
+ MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
+ MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
+ MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
+ MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
+ MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
+
+ MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
+ MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
+ MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
+ MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
+ MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
+
+ MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
+ MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
+ MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
+ MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
+ MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
+ MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
+ MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
+
+ MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
+ MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
+ MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
+ MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
+ MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
+ MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
+};
+
+static const struct mtk_spec_pull_set spec_pupd[] = {
+ SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
+ SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
+ SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
+ SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
+ SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
+ SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
+ SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
+ SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
+ SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
+ SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
+ SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
+ SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
+ SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
+ SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
+ SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
+ SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
+ SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
+ SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
+ SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
+ SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
+ SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
+ SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
+ SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
+ SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
+ SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
+ SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
+};
+
+static int spec_pull_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ unsigned int i;
+ unsigned int reg_pupd, reg_set_r0, reg_set_r1;
+ unsigned int reg_rst_r0, reg_rst_r1;
+ bool find = false;
+
+ for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
+ if (pin == spec_pupd[i].pin) {
+ find = true;
+ break;
+ }
+ }
+
+ if (!find)
+ return -EINVAL;
+
+ if (isup)
+ reg_pupd = spec_pupd[i].pupd_offset + align;
+ else
+ reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
+
+ regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
+
+ reg_set_r0 = spec_pupd[i].r0_offset + align;
+ reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
+ reg_set_r1 = spec_pupd[i].r1_offset + align;
+ reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
+
+ switch (r1r0) {
+ case MTK_PUPD_SET_R1R0_00:
+ regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
+ regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
+ break;
+ case MTK_PUPD_SET_R1R0_01:
+ regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
+ regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
+ break;
+ case MTK_PUPD_SET_R1R0_10:
+ regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
+ regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
+ break;
+ case MTK_PUPD_SET_R1R0_11:
+ regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
+ regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
+ .pins = mtk_pins_mt8135,
+ .npins = ARRAY_SIZE(mtk_pins_mt8135),
+ .grp_desc = mt8135_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
+ .pin_drv_grp = mt8135_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
+ .spec_pull_set = spec_pull_set,
+ .dir_offset = 0x0000,
+ .ies_offset = 0x0100,
+ .pullen_offset = 0x0200,
+ .smt_offset = 0x0300,
+ .pullsel_offset = 0x0400,
+ .dout_offset = 0x0800,
+ .din_offset = 0x0A00,
+ .pinmux_offset = 0x0C00,
+ .type1_start = 34,
+ .type1_end = 149,
+ .regmap_num = 2,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+ .port_pin_shf = 4,
+ .eint_offsets = {
+ .name = "mt8135_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 7,
+ .ports = 6,
+ },
+ .ap_num = 192,
+ .db_cnt = 16,
+};
+
+static int mt8135_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt8135_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt8135-pinctrl",
+ },
+ { }
+};
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt8135_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt8135-pinctrl",
+ .of_match_table = mt8135_pctrl_match,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8173.c
new file mode 100644
index 0000000..c9effdc
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8173.h"
+
+#define DRV_BASE 0xb00
+
+static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0, 0), /* KROW0 */
+ MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4, 0), /* KROW1 */
+ MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8, 0), /* KROW2 */
+ MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0, 0), /* KCOL0 */
+ MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4, 0), /* KCOL1 */
+ MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8, 0), /* KCOL2 */
+
+ MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0, 0), /* ms0 DS */
+ MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0, 0), /* ms0 RST */
+ MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0, 0), /* ms0 cmd */
+ MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0, 0), /* ms0 clk */
+ MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0, 0), /* ms0 data0 */
+ MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0, 0), /* ms0 data1 */
+ MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0, 0), /* ms0 data2 */
+ MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0, 0), /* ms0 data3 */
+ MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0, 0), /* ms0 data4 */
+ MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0, 0), /* ms0 data5 */
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0, 0), /* ms0 data6 */
+ MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0, 0), /* ms0 data7 */
+
+ MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0, 0), /* ms1 cmd */
+ MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0, 0), /* ms1 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4, 0), /* ms1 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8, 0), /* ms1 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12, 0), /* ms1 dat3 */
+ MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0, 0), /* ms1 clk */
+
+ MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0, 0), /* ms2 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4, 0), /* ms2 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8, 0), /* ms2 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12, 0), /* ms2 dat3 */
+ MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0, 0), /* ms2 clk */
+ MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0, 0), /* ms2 cmd */
+
+ MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0, 0), /* ms3 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4, 0), /* ms3 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8, 0), /* ms3 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12, 0), /* ms3 dat3 */
+ MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0, 0), /* ms3 clk */
+ MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0, 0) /* ms3 cmd */
+};
+
+static int mt8173_spec_pull_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(pctl, regmap, mt8173_spec_pupd,
+ ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
+ MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
+ MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
+ MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
+ MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
+ MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
+ MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
+ MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
+ MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
+ MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
+ MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
+ MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
+ MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
+ MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
+ MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
+ MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
+ MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
+ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
+ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
+ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
+ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
+ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
+ MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
+ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
+ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
+ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
+ MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
+ MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
+ MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
+ MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
+ MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
+ MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
+ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
+ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
+ MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
+ MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
+ MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
+ MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
+ MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
+ MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
+ MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
+ MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
+ MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
+ MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
+ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
+};
+
+static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
+ MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
+ MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
+ MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
+ MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
+ MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
+ MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
+ MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
+ MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
+ MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
+ MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
+ MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
+ MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
+ MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
+ MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
+ MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
+ MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
+ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
+ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
+ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
+ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
+ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
+ MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
+ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
+ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
+ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
+ MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
+ MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
+ MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
+ MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
+ MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
+ MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
+ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
+ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
+ MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
+ MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
+ MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
+ MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
+ MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
+ MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
+ MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
+ MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
+ MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
+ MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
+ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
+};
+
+static int mt8173_ies_smt_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
+ ARRAY_SIZE(mt8173_ies_set), pin, align, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
+ ARRAY_SIZE(mt8173_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
+ MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
+ MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
+ MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
+ MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
+ MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
+ MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
+ MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
+ MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
+ MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
+ MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
+ MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
+ MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
+ MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
+ MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
+ MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
+ MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
+ MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
+ MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
+ MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
+ MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
+ MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
+ MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
+ MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
+ MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
+ MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
+ MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
+ MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
+ MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
+ MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
+ MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
+ MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
+ MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
+ MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
+ MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
+ MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
+ MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
+ MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
+ MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
+ MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
+ MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
+ MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
+ MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
+ MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
+ MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
+ MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
+ MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
+ MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
+ MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
+ MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
+ MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
+ MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
+ MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
+ MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
+ MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
+ MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
+ MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
+ MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
+ MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
+ MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
+ MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
+ MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
+ MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
+ MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
+ MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
+ MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
+ MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
+ MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
+ MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
+ MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
+ MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
+ MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
+ MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
+ MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
+ MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
+ MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
+ MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
+ MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
+ MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
+ MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
+ MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
+ MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
+ MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
+ MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
+ MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
+ MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
+ MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
+ MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
+ MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
+ MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
+};
+
+static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
+ .pins = mtk_pins_mt8173,
+ .npins = ARRAY_SIZE(mtk_pins_mt8173),
+ .grp_desc = mt8173_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
+ .pin_drv_grp = mt8173_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
+ .spec_pull_set = mt8173_spec_pull_set,
+ .spec_ies_smt_set = mt8173_ies_smt_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0100,
+ .pullsel_offset = 0x0200,
+ .dout_offset = 0x0400,
+ .din_offset = 0x0500,
+ .pinmux_offset = 0x0600,
+ .type1_start = 135,
+ .type1_end = 135,
+ .regmap_num = 1,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+ .port_pin_shf = 4,
+ .eint_offsets = {
+ .name = "mt8173_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 7,
+ .ports = 6,
+ },
+ .ap_num = 224,
+ .db_cnt = 16,
+};
+
+static int mt8173_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt8173_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt8173-pinctrl",
+ },
+ { }
+};
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt8173_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt8173-pinctrl",
+ .of_match_table = mt8173_pctrl_match,
+ .pm = &mtk_eint_pm_ops,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8183.c
new file mode 100644
index 0000000..53048b4
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mt8183.c
@@ -0,0 +1,1821 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8183.h"
+
+#define MAX_GPIO_MODE_PER_REG 8
+#define GPIO_MODE_BITS 4
+
+struct mtk_pin_info mt8183_pin_info_ies[] = {
+ MTK_PIN_INFO(0, 0x000, 3, 1, 6),
+ MTK_PIN_INFO(1, 0x000, 3, 1, 6),
+ MTK_PIN_INFO(2, 0x000, 3, 1, 6),
+ MTK_PIN_INFO(3, 0x000, 3, 1, 6),
+ MTK_PIN_INFO(4, 0x000, 5, 1, 6),
+ MTK_PIN_INFO(5, 0x000, 5, 1, 6),
+ MTK_PIN_INFO(6, 0x000, 5, 1, 6),
+ MTK_PIN_INFO(7, 0x000, 5, 1, 6),
+ MTK_PIN_INFO(8, 0x000, 0, 1, 6),
+ MTK_PIN_INFO(9, 0x000, 12, 1, 6),
+ MTK_PIN_INFO(10, 0x000, 12, 1, 6),
+ MTK_PIN_INFO(11, 0x000, 3, 1, 1),
+ MTK_PIN_INFO(12, 0x000, 7, 1, 1),
+ MTK_PIN_INFO(13, 0x000, 2, 1, 2),
+ MTK_PIN_INFO(14, 0x000, 2, 1, 2),
+ MTK_PIN_INFO(15, 0x000, 2, 1, 2),
+ MTK_PIN_INFO(16, 0x000, 2, 1, 2),
+ MTK_PIN_INFO(17, 0x000, 3, 1, 2),
+ MTK_PIN_INFO(18, 0x000, 3, 1, 2),
+ MTK_PIN_INFO(19, 0x000, 3, 1, 2),
+ MTK_PIN_INFO(20, 0x000, 3, 1, 2),
+ MTK_PIN_INFO(21, 0x000, 4, 1, 2),
+ MTK_PIN_INFO(22, 0x000, 4, 1, 2),
+ MTK_PIN_INFO(23, 0x000, 4, 1, 2),
+ MTK_PIN_INFO(24, 0x000, 4, 1, 2),
+ MTK_PIN_INFO(25, 0x000, 5, 1, 2),
+ MTK_PIN_INFO(26, 0x000, 5, 1, 2),
+ MTK_PIN_INFO(27, 0x000, 5, 1, 2),
+ MTK_PIN_INFO(28, 0x000, 5, 1, 2),
+ MTK_PIN_INFO(29, 0x000, 6, 1, 2),
+ MTK_PIN_INFO(30, 0x000, 7, 1, 2),
+ MTK_PIN_INFO(31, 0x000, 8, 1, 2),
+ MTK_PIN_INFO(32, 0x000, 7, 1, 2),
+ MTK_PIN_INFO(33, 0x000, 7, 1, 2),
+ MTK_PIN_INFO(34, 0x000, 7, 1, 2),
+ MTK_PIN_INFO(35, 0x000, 0, 1, 3),
+ MTK_PIN_INFO(36, 0x000, 0, 1, 3),
+ MTK_PIN_INFO(37, 0x000, 0, 1, 3),
+ MTK_PIN_INFO(38, 0x000, 1, 1, 3),
+ MTK_PIN_INFO(39, 0x000, 1, 1, 3),
+ MTK_PIN_INFO(40, 0x000, 1, 1, 3),
+ MTK_PIN_INFO(41, 0x000, 2, 1, 3),
+ MTK_PIN_INFO(42, 0x000, 2, 1, 3),
+ MTK_PIN_INFO(43, 0x000, 3, 1, 3),
+ MTK_PIN_INFO(44, 0x000, 3, 1, 3),
+ MTK_PIN_INFO(45, 0x000, 3, 1, 3),
+ MTK_PIN_INFO(46, 0x000, 4, 1, 3),
+ MTK_PIN_INFO(47, 0x000, 4, 1, 3),
+ MTK_PIN_INFO(48, 0x000, 5, 1, 3),
+ MTK_PIN_INFO(49, 0x000, 5, 1, 3),
+ MTK_PIN_INFO(50, 0x000, 0, 1, 4),
+ MTK_PIN_INFO(51, 0x000, 0, 1, 4),
+ MTK_PIN_INFO(52, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(53, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(54, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(55, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(56, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(57, 0x000, 1, 1, 4),
+ MTK_PIN_INFO(58, 0x000, 2, 1, 4),
+ MTK_PIN_INFO(59, 0x000, 2, 1, 4),
+ MTK_PIN_INFO(60, 0x000, 2, 1, 4),
+ MTK_PIN_INFO(61, 0x000, 0, 1, 5),
+ MTK_PIN_INFO(62, 0x000, 0, 1, 5),
+ MTK_PIN_INFO(63, 0x000, 0, 1, 5),
+ MTK_PIN_INFO(64, 0x000, 0, 1, 5),
+ MTK_PIN_INFO(65, 0x000, 1, 1, 5),
+ MTK_PIN_INFO(66, 0x000, 1, 1, 5),
+ MTK_PIN_INFO(67, 0x000, 2, 1, 5),
+ MTK_PIN_INFO(68, 0x000, 2, 1, 5),
+ MTK_PIN_INFO(69, 0x000, 3, 1, 5),
+ MTK_PIN_INFO(70, 0x000, 3, 1, 5),
+ MTK_PIN_INFO(71, 0x000, 3, 1, 5),
+ MTK_PIN_INFO(72, 0x000, 4, 1, 5),
+ MTK_PIN_INFO(73, 0x000, 4, 1, 5),
+ MTK_PIN_INFO(74, 0x000, 4, 1, 5),
+ MTK_PIN_INFO(75, 0x000, 4, 1, 5),
+ MTK_PIN_INFO(76, 0x000, 4, 1, 5),
+ MTK_PIN_INFO(77, 0x000, 5, 1, 5),
+ MTK_PIN_INFO(78, 0x000, 5, 1, 5),
+ MTK_PIN_INFO(79, 0x000, 5, 1, 5),
+ MTK_PIN_INFO(80, 0x000, 5, 1, 5),
+ MTK_PIN_INFO(81, 0x000, 6, 1, 5),
+ MTK_PIN_INFO(82, 0x000, 7, 1, 5),
+ MTK_PIN_INFO(83, 0x000, 7, 1, 5),
+ MTK_PIN_INFO(84, 0x000, 6, 1, 5),
+ MTK_PIN_INFO(85, 0x000, 8, 1, 5),
+ MTK_PIN_INFO(86, 0x000, 8, 1, 5),
+ MTK_PIN_INFO(87, 0x000, 8, 1, 5),
+ MTK_PIN_INFO(88, 0x000, 8, 1, 5),
+ MTK_PIN_INFO(89, 0x000, 11, 1, 6),
+ MTK_PIN_INFO(90, 0x000, 1, 1, 6),
+ MTK_PIN_INFO(91, 0x000, 2, 1, 6),
+ MTK_PIN_INFO(92, 0x000, 2, 1, 6),
+ MTK_PIN_INFO(93, 0x000, 2, 1, 6),
+ MTK_PIN_INFO(94, 0x000, 2, 1, 6),
+ MTK_PIN_INFO(95, 0x000, 6, 1, 6),
+ MTK_PIN_INFO(96, 0x000, 6, 1, 6),
+ MTK_PIN_INFO(97, 0x000, 7, 1, 6),
+ MTK_PIN_INFO(98, 0x000, 7, 1, 6),
+ MTK_PIN_INFO(99, 0x000, 8, 1, 6),
+ MTK_PIN_INFO(100, 0x000, 9, 1, 6),
+ MTK_PIN_INFO(101, 0x000, 10, 1, 6),
+ MTK_PIN_INFO(102, 0x000, 10, 1, 6),
+ MTK_PIN_INFO(103, 0x000, 13, 1, 6),
+ MTK_PIN_INFO(104, 0x000, 13, 1, 6),
+ MTK_PIN_INFO(105, 0x000, 14, 1, 6),
+ MTK_PIN_INFO(106, 0x000, 14, 1, 6),
+ MTK_PIN_INFO(107, 0x000, 0, 1, 7),
+ MTK_PIN_INFO(108, 0x000, 1, 1, 7),
+ MTK_PIN_INFO(109, 0x000, 2, 1, 7),
+ MTK_PIN_INFO(110, 0x000, 0, 1, 7),
+ MTK_PIN_INFO(111, 0x000, 3, 1, 7),
+ MTK_PIN_INFO(112, 0x000, 2, 1, 7),
+ MTK_PIN_INFO(113, 0x000, 4, 1, 7),
+ MTK_PIN_INFO(114, 0x000, 5, 1, 7),
+ MTK_PIN_INFO(115, 0x000, 6, 1, 7),
+ MTK_PIN_INFO(116, 0x000, 7, 1, 7),
+ MTK_PIN_INFO(117, 0x000, 8, 1, 7),
+ MTK_PIN_INFO(118, 0x000, 9, 1, 7),
+ MTK_PIN_INFO(119, 0x000, 10, 1, 7),
+ MTK_PIN_INFO(120, 0x000, 11, 1, 7),
+ MTK_PIN_INFO(121, 0x000, 12, 1, 7),
+ MTK_PIN_INFO(122, 0x000, 0, 1, 8),
+ MTK_PIN_INFO(123, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(124, 0x000, 2, 1, 8),
+ MTK_PIN_INFO(125, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(126, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(127, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(128, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(129, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(130, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(131, 0x000, 3, 1, 8),
+ MTK_PIN_INFO(132, 0x000, 1, 1, 8),
+ MTK_PIN_INFO(133, 0x000, 4, 1, 8),
+ MTK_PIN_INFO(134, 0x000, 0, 1, 1),
+ MTK_PIN_INFO(135, 0x000, 1, 1, 1),
+ MTK_PIN_INFO(136, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(137, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(138, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(139, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(140, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(141, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(142, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(143, 0x000, 2, 1, 1),
+ MTK_PIN_INFO(144, 0x000, 4, 1, 1),
+ MTK_PIN_INFO(145, 0x000, 4, 1, 1),
+ MTK_PIN_INFO(146, 0x000, 4, 1, 1),
+ MTK_PIN_INFO(147, 0x000, 4, 1, 1),
+ MTK_PIN_INFO(148, 0x000, 5, 1, 1),
+ MTK_PIN_INFO(149, 0x000, 6, 1, 1),
+ MTK_PIN_INFO(150, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(151, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(152, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(153, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(154, 0x000, 9, 1, 1),
+ MTK_PIN_INFO(155, 0x000, 10, 1, 1),
+ MTK_PIN_INFO(156, 0x000, 10, 1, 1),
+ MTK_PIN_INFO(157, 0x000, 10, 1, 1),
+ MTK_PIN_INFO(158, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(159, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(160, 0x000, 8, 1, 1),
+ MTK_PIN_INFO(161, 0x000, 0, 1, 2),
+ MTK_PIN_INFO(162, 0x000, 0, 1, 2),
+ MTK_PIN_INFO(163, 0x000, 0, 1, 2),
+ MTK_PIN_INFO(164, 0x000, 0, 1, 2),
+ MTK_PIN_INFO(165, 0x000, 1, 1, 2),
+ MTK_PIN_INFO(166, 0x000, 1, 1, 2),
+ MTK_PIN_INFO(167, 0x000, 2, 1, 4),
+ MTK_PIN_INFO(168, 0x000, 2, 1, 4),
+ MTK_PIN_INFO(169, 0x000, 3, 1, 4),
+ MTK_PIN_INFO(170, 0x000, 4, 1, 4),
+ MTK_PIN_INFO(171, 0x000, 4, 1, 4),
+ MTK_PIN_INFO(172, 0x000, 4, 1, 4),
+ MTK_PIN_INFO(173, 0x000, 4, 1, 4),
+ MTK_PIN_INFO(174, 0x000, 4, 1, 4),
+ MTK_PIN_INFO(175, 0x000, 3, 1, 4),
+ MTK_PIN_INFO(176, 0x000, 3, 1, 4),
+ MTK_PIN_INFO(177, 0x000, 4, 1, 6),
+ MTK_PIN_INFO(178, 0x000, 4, 1, 6),
+ MTK_PIN_INFO(179, 0x000, 4, 1, 6),
+};
+
+struct mtk_pin_info mt8183_pin_info_smt[] = {
+ MTK_PIN_INFO(0, 0x010, 3, 1, 6),
+ MTK_PIN_INFO(1, 0x010, 3, 1, 6),
+ MTK_PIN_INFO(2, 0x010, 3, 1, 6),
+ MTK_PIN_INFO(3, 0x010, 3, 1, 6),
+ MTK_PIN_INFO(4, 0x010, 5, 1, 6),
+ MTK_PIN_INFO(5, 0x010, 5, 1, 6),
+ MTK_PIN_INFO(6, 0x010, 5, 1, 6),
+ MTK_PIN_INFO(7, 0x010, 5, 1, 6),
+ MTK_PIN_INFO(8, 0x010, 0, 1, 6),
+ MTK_PIN_INFO(9, 0x010, 12, 1, 6),
+ MTK_PIN_INFO(10, 0x010, 12, 1, 6),
+ MTK_PIN_INFO(11, 0x010, 3, 1, 1),
+ MTK_PIN_INFO(12, 0x010, 7, 1, 1),
+ MTK_PIN_INFO(13, 0x010, 2, 1, 2),
+ MTK_PIN_INFO(14, 0x010, 2, 1, 2),
+ MTK_PIN_INFO(15, 0x010, 2, 1, 2),
+ MTK_PIN_INFO(16, 0x010, 2, 1, 2),
+ MTK_PIN_INFO(17, 0x010, 3, 1, 2),
+ MTK_PIN_INFO(18, 0x010, 3, 1, 2),
+ MTK_PIN_INFO(19, 0x010, 3, 1, 2),
+ MTK_PIN_INFO(20, 0x010, 3, 1, 2),
+ MTK_PIN_INFO(21, 0x010, 4, 1, 2),
+ MTK_PIN_INFO(22, 0x010, 4, 1, 2),
+ MTK_PIN_INFO(23, 0x010, 4, 1, 2),
+ MTK_PIN_INFO(24, 0x010, 4, 1, 2),
+ MTK_PIN_INFO(25, 0x010, 5, 1, 2),
+ MTK_PIN_INFO(26, 0x010, 5, 1, 2),
+ MTK_PIN_INFO(27, 0x010, 5, 1, 2),
+ MTK_PIN_INFO(28, 0x010, 5, 1, 2),
+ MTK_PIN_INFO(29, 0x010, 6, 1, 2),
+ MTK_PIN_INFO(30, 0x010, 7, 1, 2),
+ MTK_PIN_INFO(31, 0x010, 8, 1, 2),
+ MTK_PIN_INFO(32, 0x010, 7, 1, 2),
+ MTK_PIN_INFO(33, 0x010, 7, 1, 2),
+ MTK_PIN_INFO(34, 0x010, 7, 1, 2),
+ MTK_PIN_INFO(35, 0x010, 0, 1, 3),
+ MTK_PIN_INFO(36, 0x010, 0, 1, 3),
+ MTK_PIN_INFO(37, 0x010, 0, 1, 3),
+ MTK_PIN_INFO(38, 0x010, 1, 1, 3),
+ MTK_PIN_INFO(39, 0x010, 1, 1, 3),
+ MTK_PIN_INFO(40, 0x010, 1, 1, 3),
+ MTK_PIN_INFO(41, 0x010, 2, 1, 3),
+ MTK_PIN_INFO(42, 0x010, 2, 1, 3),
+ MTK_PIN_INFO(43, 0x010, 3, 1, 3),
+ MTK_PIN_INFO(44, 0x010, 3, 1, 3),
+ MTK_PIN_INFO(45, 0x010, 3, 1, 3),
+ MTK_PIN_INFO(46, 0x010, 4, 1, 3),
+ MTK_PIN_INFO(47, 0x010, 4, 1, 3),
+ MTK_PIN_INFO(48, 0x010, 5, 1, 3),
+ MTK_PIN_INFO(49, 0x010, 5, 1, 3),
+ MTK_PIN_INFO(50, 0x010, 0, 1, 4),
+ MTK_PIN_INFO(51, 0x010, 0, 1, 4),
+ MTK_PIN_INFO(52, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(53, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(54, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(55, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(56, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(57, 0x010, 1, 1, 4),
+ MTK_PIN_INFO(58, 0x010, 2, 1, 4),
+ MTK_PIN_INFO(59, 0x010, 2, 1, 4),
+ MTK_PIN_INFO(60, 0x010, 2, 1, 4),
+ MTK_PIN_INFO(61, 0x010, 0, 1, 5),
+ MTK_PIN_INFO(62, 0x010, 0, 1, 5),
+ MTK_PIN_INFO(63, 0x010, 0, 1, 5),
+ MTK_PIN_INFO(64, 0x010, 0, 1, 5),
+ MTK_PIN_INFO(65, 0x010, 1, 1, 5),
+ MTK_PIN_INFO(66, 0x010, 1, 1, 5),
+ MTK_PIN_INFO(67, 0x010, 2, 1, 5),
+ MTK_PIN_INFO(68, 0x010, 2, 1, 5),
+ MTK_PIN_INFO(69, 0x010, 3, 1, 5),
+ MTK_PIN_INFO(70, 0x010, 3, 1, 5),
+ MTK_PIN_INFO(71, 0x010, 3, 1, 5),
+ MTK_PIN_INFO(72, 0x010, 4, 1, 5),
+ MTK_PIN_INFO(73, 0x010, 4, 1, 5),
+ MTK_PIN_INFO(74, 0x010, 4, 1, 5),
+ MTK_PIN_INFO(75, 0x010, 4, 1, 5),
+ MTK_PIN_INFO(76, 0x010, 4, 1, 5),
+ MTK_PIN_INFO(77, 0x010, 5, 1, 5),
+ MTK_PIN_INFO(78, 0x010, 5, 1, 5),
+ MTK_PIN_INFO(79, 0x010, 5, 1, 5),
+ MTK_PIN_INFO(80, 0x010, 5, 1, 5),
+ MTK_PIN_INFO(81, 0x010, 6, 1, 5),
+ MTK_PIN_INFO(82, 0x010, 7, 1, 5),
+ MTK_PIN_INFO(83, 0x010, 7, 1, 5),
+ MTK_PIN_INFO(84, 0x010, 6, 1, 5),
+ MTK_PIN_INFO(85, 0x010, 8, 1, 5),
+ MTK_PIN_INFO(86, 0x010, 8, 1, 5),
+ MTK_PIN_INFO(87, 0x010, 8, 1, 5),
+ MTK_PIN_INFO(88, 0x010, 8, 1, 5),
+ MTK_PIN_INFO(89, 0x010, 11, 1, 6),
+ MTK_PIN_INFO(90, 0x010, 1, 1, 6),
+ MTK_PIN_INFO(91, 0x010, 2, 1, 6),
+ MTK_PIN_INFO(92, 0x010, 2, 1, 6),
+ MTK_PIN_INFO(93, 0x010, 2, 1, 6),
+ MTK_PIN_INFO(94, 0x010, 2, 1, 6),
+ MTK_PIN_INFO(95, 0x010, 6, 1, 6),
+ MTK_PIN_INFO(96, 0x010, 6, 1, 6),
+ MTK_PIN_INFO(97, 0x010, 7, 1, 6),
+ MTK_PIN_INFO(98, 0x010, 7, 1, 6),
+ MTK_PIN_INFO(99, 0x010, 8, 1, 6),
+ MTK_PIN_INFO(100, 0x010, 9, 1, 6),
+ MTK_PIN_INFO(101, 0x010, 10, 1, 6),
+ MTK_PIN_INFO(102, 0x010, 10, 1, 6),
+ MTK_PIN_INFO(103, 0x010, 13, 1, 6),
+ MTK_PIN_INFO(104, 0x010, 13, 1, 6),
+ MTK_PIN_INFO(105, 0x010, 14, 1, 6),
+ MTK_PIN_INFO(106, 0x010, 14, 1, 6),
+ MTK_PIN_INFO(107, 0x010, 0, 1, 7),
+ MTK_PIN_INFO(108, 0x010, 1, 1, 7),
+ MTK_PIN_INFO(109, 0x010, 2, 1, 7),
+ MTK_PIN_INFO(110, 0x010, 0, 1, 7),
+ MTK_PIN_INFO(111, 0x010, 3, 1, 7),
+ MTK_PIN_INFO(112, 0x010, 2, 1, 7),
+ MTK_PIN_INFO(113, 0x010, 4, 1, 7),
+ MTK_PIN_INFO(114, 0x010, 5, 1, 7),
+ MTK_PIN_INFO(115, 0x010, 6, 1, 7),
+ MTK_PIN_INFO(116, 0x010, 7, 1, 7),
+ MTK_PIN_INFO(117, 0x010, 8, 1, 7),
+ MTK_PIN_INFO(118, 0x010, 9, 1, 7),
+ MTK_PIN_INFO(119, 0x010, 10, 1, 7),
+ MTK_PIN_INFO(120, 0x010, 11, 1, 7),
+ MTK_PIN_INFO(121, 0x010, 12, 1, 7),
+ MTK_PIN_INFO(122, 0x010, 0, 1, 8),
+ MTK_PIN_INFO(123, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(124, 0x010, 2, 1, 8),
+ MTK_PIN_INFO(125, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(126, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(127, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(128, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(129, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(130, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(131, 0x010, 3, 1, 8),
+ MTK_PIN_INFO(132, 0x010, 1, 1, 8),
+ MTK_PIN_INFO(133, 0x010, 4, 1, 8),
+ MTK_PIN_INFO(134, 0x010, 0, 1, 1),
+ MTK_PIN_INFO(135, 0x010, 1, 1, 1),
+ MTK_PIN_INFO(136, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(137, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(138, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(139, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(140, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(141, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(142, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(143, 0x010, 2, 1, 1),
+ MTK_PIN_INFO(144, 0x010, 4, 1, 1),
+ MTK_PIN_INFO(145, 0x010, 4, 1, 1),
+ MTK_PIN_INFO(146, 0x010, 4, 1, 1),
+ MTK_PIN_INFO(147, 0x010, 4, 1, 1),
+ MTK_PIN_INFO(148, 0x010, 5, 1, 1),
+ MTK_PIN_INFO(149, 0x010, 6, 1, 1),
+ MTK_PIN_INFO(150, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(151, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(152, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(153, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(154, 0x010, 9, 1, 1),
+ MTK_PIN_INFO(155, 0x010, 10, 1, 1),
+ MTK_PIN_INFO(156, 0x010, 10, 1, 1),
+ MTK_PIN_INFO(157, 0x010, 10, 1, 1),
+ MTK_PIN_INFO(158, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(159, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(160, 0x010, 8, 1, 1),
+ MTK_PIN_INFO(161, 0x010, 0, 1, 2),
+ MTK_PIN_INFO(162, 0x010, 0, 1, 2),
+ MTK_PIN_INFO(163, 0x010, 0, 1, 2),
+ MTK_PIN_INFO(164, 0x010, 0, 1, 2),
+ MTK_PIN_INFO(165, 0x010, 1, 1, 2),
+ MTK_PIN_INFO(166, 0x010, 1, 1, 2),
+ MTK_PIN_INFO(167, 0x010, 2, 1, 4),
+ MTK_PIN_INFO(168, 0x010, 2, 1, 4),
+ MTK_PIN_INFO(169, 0x010, 3, 1, 4),
+ MTK_PIN_INFO(170, 0x010, 4, 1, 4),
+ MTK_PIN_INFO(171, 0x010, 4, 1, 4),
+ MTK_PIN_INFO(172, 0x010, 4, 1, 4),
+ MTK_PIN_INFO(173, 0x010, 4, 1, 4),
+ MTK_PIN_INFO(174, 0x010, 4, 1, 4),
+ MTK_PIN_INFO(175, 0x010, 3, 1, 4),
+ MTK_PIN_INFO(176, 0x010, 3, 1, 4),
+ MTK_PIN_INFO(177, 0x010, 4, 1, 6),
+ MTK_PIN_INFO(178, 0x010, 4, 1, 6),
+ MTK_PIN_INFO(179, 0x010, 4, 1, 6),
+};
+
+struct mtk_pin_info mt8183_pin_info_pullen[] = {
+ MTK_PIN_INFO(0, 0x060, 6, 1, 6),
+ MTK_PIN_INFO(1, 0x060, 7, 1, 6),
+ MTK_PIN_INFO(2, 0x060, 8, 1, 6),
+ MTK_PIN_INFO(3, 0x060, 9, 1, 6),
+ MTK_PIN_INFO(4, 0x060, 11, 1, 6),
+ MTK_PIN_INFO(5, 0x060, 12, 1, 6),
+ MTK_PIN_INFO(6, 0x060, 13, 1, 6),
+ MTK_PIN_INFO(7, 0x060, 14, 1, 6),
+ MTK_PIN_INFO(8, 0x060, 0, 1, 6),
+ MTK_PIN_INFO(9, 0x060, 26, 1, 6),
+ MTK_PIN_INFO(10, 0x060, 27, 1, 6),
+ MTK_PIN_INFO(11, 0x060, 10, 1, 1),
+ MTK_PIN_INFO(12, 0x060, 17, 1, 1),
+ MTK_PIN_INFO(13, 0x060, 6, 1, 2),
+ MTK_PIN_INFO(14, 0x060, 7, 1, 2),
+ MTK_PIN_INFO(15, 0x060, 8, 1, 2),
+ MTK_PIN_INFO(16, 0x060, 9, 1, 2),
+ MTK_PIN_INFO(17, 0x060, 10, 1, 2),
+ MTK_PIN_INFO(18, 0x060, 11, 1, 2),
+ MTK_PIN_INFO(19, 0x060, 12, 1, 2),
+ MTK_PIN_INFO(20, 0x060, 13, 1, 2),
+ MTK_PIN_INFO(21, 0x060, 14, 1, 2),
+ MTK_PIN_INFO(22, 0x060, 15, 1, 2),
+ MTK_PIN_INFO(23, 0x060, 16, 1, 2),
+ MTK_PIN_INFO(24, 0x060, 17, 1, 2),
+ MTK_PIN_INFO(25, 0x060, 18, 1, 2),
+ MTK_PIN_INFO(26, 0x060, 19, 1, 2),
+ MTK_PIN_INFO(27, 0x060, 20, 1, 2),
+ MTK_PIN_INFO(28, 0x060, 21, 1, 2),
+ MTK_PIN_INFO(43, 0x060, 8, 1, 3),
+ MTK_PIN_INFO(44, 0x060, 9, 1, 3),
+ MTK_PIN_INFO(45, 0x060, 10, 1, 3),
+ MTK_PIN_INFO(46, 0x060, 11, 1, 3),
+ MTK_PIN_INFO(47, 0x060, 12, 1, 3),
+ MTK_PIN_INFO(48, 0x060, 13, 1, 3),
+ MTK_PIN_INFO(49, 0x060, 14, 1, 3),
+ MTK_PIN_INFO(50, 0x060, 0, 1, 4),
+ MTK_PIN_INFO(51, 0x060, 1, 1, 4),
+ MTK_PIN_INFO(52, 0x060, 2, 1, 4),
+ MTK_PIN_INFO(53, 0x060, 3, 1, 4),
+ MTK_PIN_INFO(54, 0x060, 4, 1, 4),
+ MTK_PIN_INFO(55, 0x060, 5, 1, 4),
+ MTK_PIN_INFO(56, 0x060, 6, 1, 4),
+ MTK_PIN_INFO(57, 0x060, 7, 1, 4),
+ MTK_PIN_INFO(58, 0x060, 8, 1, 4),
+ MTK_PIN_INFO(59, 0x060, 9, 1, 4),
+ MTK_PIN_INFO(60, 0x060, 10, 1, 4),
+ MTK_PIN_INFO(61, 0x060, 0, 1, 5),
+ MTK_PIN_INFO(62, 0x060, 1, 1, 5),
+ MTK_PIN_INFO(63, 0x060, 2, 1, 5),
+ MTK_PIN_INFO(64, 0x060, 3, 1, 5),
+ MTK_PIN_INFO(65, 0x060, 4, 1, 5),
+ MTK_PIN_INFO(66, 0x060, 5, 1, 5),
+ MTK_PIN_INFO(67, 0x060, 6, 1, 5),
+ MTK_PIN_INFO(68, 0x060, 7, 1, 5),
+ MTK_PIN_INFO(69, 0x060, 8, 1, 5),
+ MTK_PIN_INFO(70, 0x060, 9, 1, 5),
+ MTK_PIN_INFO(71, 0x060, 10, 1, 5),
+ MTK_PIN_INFO(72, 0x060, 11, 1, 5),
+ MTK_PIN_INFO(73, 0x060, 12, 1, 5),
+ MTK_PIN_INFO(74, 0x060, 13, 1, 5),
+ MTK_PIN_INFO(75, 0x060, 14, 1, 5),
+ MTK_PIN_INFO(76, 0x060, 15, 1, 5),
+ MTK_PIN_INFO(77, 0x060, 16, 1, 5),
+ MTK_PIN_INFO(78, 0x060, 17, 1, 5),
+ MTK_PIN_INFO(79, 0x060, 18, 1, 5),
+ MTK_PIN_INFO(80, 0x060, 19, 1, 5),
+ MTK_PIN_INFO(81, 0x060, 20, 1, 5),
+ MTK_PIN_INFO(82, 0x060, 21, 1, 5),
+ MTK_PIN_INFO(83, 0x060, 22, 1, 5),
+ MTK_PIN_INFO(84, 0x060, 23, 1, 5),
+ MTK_PIN_INFO(85, 0x060, 24, 1, 5),
+ MTK_PIN_INFO(86, 0x060, 25, 1, 5),
+ MTK_PIN_INFO(87, 0x060, 26, 1, 5),
+ MTK_PIN_INFO(88, 0x060, 27, 1, 5),
+ MTK_PIN_INFO(89, 0x060, 24, 1, 6),
+ MTK_PIN_INFO(90, 0x060, 1, 1, 6),
+ MTK_PIN_INFO(95, 0x060, 15, 1, 6),
+ MTK_PIN_INFO(96, 0x060, 17, 1, 6),
+ MTK_PIN_INFO(97, 0x060, 18, 1, 6),
+ MTK_PIN_INFO(98, 0x060, 19, 1, 6),
+ MTK_PIN_INFO(99, 0x060, 20, 1, 6),
+ MTK_PIN_INFO(100, 0x060, 21, 1, 6),
+ MTK_PIN_INFO(101, 0x060, 22, 1, 6),
+ MTK_PIN_INFO(102, 0x060, 23, 1, 6),
+ MTK_PIN_INFO(103, 0x060, 28, 1, 6),
+ MTK_PIN_INFO(104, 0x060, 29, 1, 6),
+ MTK_PIN_INFO(105, 0x060, 30, 1, 6),
+ MTK_PIN_INFO(106, 0x060, 31, 1, 6),
+ MTK_PIN_INFO(107, 0x060, 0, 1, 7),
+ MTK_PIN_INFO(108, 0x060, 1, 1, 7),
+ MTK_PIN_INFO(109, 0x060, 2, 1, 7),
+ MTK_PIN_INFO(110, 0x060, 3, 1, 7),
+ MTK_PIN_INFO(111, 0x060, 4, 1, 7),
+ MTK_PIN_INFO(112, 0x060, 5, 1, 7),
+ MTK_PIN_INFO(113, 0x060, 6, 1, 7),
+ MTK_PIN_INFO(114, 0x060, 7, 1, 7),
+ MTK_PIN_INFO(115, 0x060, 8, 1, 7),
+ MTK_PIN_INFO(116, 0x060, 9, 1, 7),
+ MTK_PIN_INFO(117, 0x060, 10, 1, 7),
+ MTK_PIN_INFO(118, 0x060, 11, 1, 7),
+ MTK_PIN_INFO(119, 0x060, 12, 1, 7),
+ MTK_PIN_INFO(120, 0x060, 13, 1, 7),
+ MTK_PIN_INFO(121, 0x060, 14, 1, 7),
+ MTK_PIN_INFO(134, 0x060, 0, 1, 1),
+ MTK_PIN_INFO(135, 0x060, 1, 1, 1),
+ MTK_PIN_INFO(136, 0x060, 2, 1, 1),
+ MTK_PIN_INFO(137, 0x060, 3, 1, 1),
+ MTK_PIN_INFO(138, 0x060, 4, 1, 1),
+ MTK_PIN_INFO(139, 0x060, 5, 1, 1),
+ MTK_PIN_INFO(140, 0x060, 6, 1, 1),
+ MTK_PIN_INFO(141, 0x060, 7, 1, 1),
+ MTK_PIN_INFO(142, 0x060, 8, 1, 1),
+ MTK_PIN_INFO(143, 0x060, 9, 1, 1),
+ MTK_PIN_INFO(144, 0x060, 11, 1, 1),
+ MTK_PIN_INFO(145, 0x060, 12, 1, 1),
+ MTK_PIN_INFO(146, 0x060, 13, 1, 1),
+ MTK_PIN_INFO(147, 0x060, 14, 1, 1),
+ MTK_PIN_INFO(148, 0x060, 15, 1, 1),
+ MTK_PIN_INFO(149, 0x060, 16, 1, 1),
+ MTK_PIN_INFO(150, 0x060, 18, 1, 1),
+ MTK_PIN_INFO(151, 0x060, 19, 1, 1),
+ MTK_PIN_INFO(152, 0x060, 20, 1, 1),
+ MTK_PIN_INFO(153, 0x060, 21, 1, 1),
+ MTK_PIN_INFO(154, 0x060, 22, 1, 1),
+ MTK_PIN_INFO(155, 0x060, 23, 1, 1),
+ MTK_PIN_INFO(156, 0x060, 24, 1, 1),
+ MTK_PIN_INFO(157, 0x060, 25, 1, 1),
+ MTK_PIN_INFO(158, 0x060, 26, 1, 1),
+ MTK_PIN_INFO(159, 0x060, 27, 1, 1),
+ MTK_PIN_INFO(160, 0x060, 28, 1, 1),
+ MTK_PIN_INFO(161, 0x060, 0, 1, 2),
+ MTK_PIN_INFO(162, 0x060, 1, 1, 2),
+ MTK_PIN_INFO(163, 0x060, 2, 1, 2),
+ MTK_PIN_INFO(164, 0x060, 3, 1, 2),
+ MTK_PIN_INFO(165, 0x060, 4, 1, 2),
+ MTK_PIN_INFO(166, 0x060, 5, 1, 2),
+ MTK_PIN_INFO(167, 0x060, 11, 1, 4),
+ MTK_PIN_INFO(168, 0x060, 12, 1, 4),
+ MTK_PIN_INFO(169, 0x060, 13, 1, 4),
+ MTK_PIN_INFO(170, 0x060, 14, 1, 4),
+ MTK_PIN_INFO(171, 0x060, 15, 1, 4),
+ MTK_PIN_INFO(172, 0x060, 16, 1, 4),
+ MTK_PIN_INFO(173, 0x060, 17, 1, 4),
+ MTK_PIN_INFO(174, 0x060, 18, 1, 4),
+ MTK_PIN_INFO(175, 0x060, 19, 1, 4),
+ MTK_PIN_INFO(176, 0x060, 20, 1, 4),
+ MTK_PIN_INFO(177, 0x060, 10, 1, 6),
+ MTK_PIN_INFO(178, 0x060, 16, 1, 6),
+ MTK_PIN_INFO(179, 0x060, 25, 1, 6),
+};
+
+struct mtk_pin_info mt8183_pin_info_pullsel[] = {
+ MTK_PIN_INFO(0, 0x080, 6, 1, 6),
+ MTK_PIN_INFO(1, 0x080, 7, 1, 6),
+ MTK_PIN_INFO(2, 0x080, 8, 1, 6),
+ MTK_PIN_INFO(3, 0x080, 9, 1, 6),
+ MTK_PIN_INFO(4, 0x080, 11, 1, 6),
+ MTK_PIN_INFO(5, 0x080, 12, 1, 6),
+ MTK_PIN_INFO(6, 0x080, 13, 1, 6),
+ MTK_PIN_INFO(7, 0x080, 14, 1, 6),
+ MTK_PIN_INFO(8, 0x080, 0, 1, 6),
+ MTK_PIN_INFO(9, 0x080, 26, 1, 6),
+ MTK_PIN_INFO(10, 0x080, 27, 1, 6),
+ MTK_PIN_INFO(11, 0x080, 10, 1, 1),
+ MTK_PIN_INFO(12, 0x080, 17, 1, 1),
+ MTK_PIN_INFO(13, 0x080, 6, 1, 2),
+ MTK_PIN_INFO(14, 0x080, 7, 1, 2),
+ MTK_PIN_INFO(15, 0x080, 8, 1, 2),
+ MTK_PIN_INFO(16, 0x080, 9, 1, 2),
+ MTK_PIN_INFO(17, 0x080, 10, 1, 2),
+ MTK_PIN_INFO(18, 0x080, 11, 1, 2),
+ MTK_PIN_INFO(19, 0x080, 12, 1, 2),
+ MTK_PIN_INFO(20, 0x080, 13, 1, 2),
+ MTK_PIN_INFO(21, 0x080, 14, 1, 2),
+ MTK_PIN_INFO(22, 0x080, 15, 1, 2),
+ MTK_PIN_INFO(23, 0x080, 16, 1, 2),
+ MTK_PIN_INFO(24, 0x080, 17, 1, 2),
+ MTK_PIN_INFO(25, 0x080, 18, 1, 2),
+ MTK_PIN_INFO(26, 0x080, 19, 1, 2),
+ MTK_PIN_INFO(27, 0x080, 20, 1, 2),
+ MTK_PIN_INFO(28, 0x080, 21, 1, 2),
+ MTK_PIN_INFO(43, 0x080, 8, 1, 3),
+ MTK_PIN_INFO(44, 0x080, 9, 1, 3),
+ MTK_PIN_INFO(45, 0x080, 10, 1, 3),
+ MTK_PIN_INFO(46, 0x080, 11, 1, 3),
+ MTK_PIN_INFO(47, 0x080, 12, 1, 3),
+ MTK_PIN_INFO(48, 0x080, 13, 1, 3),
+ MTK_PIN_INFO(49, 0x080, 14, 1, 3),
+ MTK_PIN_INFO(50, 0x080, 0, 1, 4),
+ MTK_PIN_INFO(51, 0x080, 1, 1, 4),
+ MTK_PIN_INFO(52, 0x080, 2, 1, 4),
+ MTK_PIN_INFO(53, 0x080, 3, 1, 4),
+ MTK_PIN_INFO(54, 0x080, 4, 1, 4),
+ MTK_PIN_INFO(55, 0x080, 5, 1, 4),
+ MTK_PIN_INFO(56, 0x080, 6, 1, 4),
+ MTK_PIN_INFO(57, 0x080, 7, 1, 4),
+ MTK_PIN_INFO(58, 0x080, 8, 1, 4),
+ MTK_PIN_INFO(59, 0x080, 9, 1, 4),
+ MTK_PIN_INFO(60, 0x080, 10, 1, 4),
+ MTK_PIN_INFO(61, 0x080, 0, 1, 5),
+ MTK_PIN_INFO(62, 0x080, 1, 1, 5),
+ MTK_PIN_INFO(63, 0x080, 2, 1, 5),
+ MTK_PIN_INFO(64, 0x080, 3, 1, 5),
+ MTK_PIN_INFO(65, 0x080, 4, 1, 5),
+ MTK_PIN_INFO(66, 0x080, 5, 1, 5),
+ MTK_PIN_INFO(67, 0x080, 6, 1, 5),
+ MTK_PIN_INFO(68, 0x080, 7, 1, 5),
+ MTK_PIN_INFO(69, 0x080, 8, 1, 5),
+ MTK_PIN_INFO(70, 0x080, 9, 1, 5),
+ MTK_PIN_INFO(71, 0x080, 10, 1, 5),
+ MTK_PIN_INFO(72, 0x080, 11, 1, 5),
+ MTK_PIN_INFO(73, 0x080, 12, 1, 5),
+ MTK_PIN_INFO(74, 0x080, 13, 1, 5),
+ MTK_PIN_INFO(75, 0x080, 14, 1, 5),
+ MTK_PIN_INFO(76, 0x080, 15, 1, 5),
+ MTK_PIN_INFO(77, 0x080, 16, 1, 5),
+ MTK_PIN_INFO(78, 0x080, 17, 1, 5),
+ MTK_PIN_INFO(79, 0x080, 18, 1, 5),
+ MTK_PIN_INFO(80, 0x080, 19, 1, 5),
+ MTK_PIN_INFO(81, 0x080, 20, 1, 5),
+ MTK_PIN_INFO(82, 0x080, 21, 1, 5),
+ MTK_PIN_INFO(83, 0x080, 22, 1, 5),
+ MTK_PIN_INFO(84, 0x080, 23, 1, 5),
+ MTK_PIN_INFO(85, 0x080, 24, 1, 5),
+ MTK_PIN_INFO(86, 0x080, 25, 1, 5),
+ MTK_PIN_INFO(87, 0x080, 26, 1, 5),
+ MTK_PIN_INFO(88, 0x080, 27, 1, 5),
+ MTK_PIN_INFO(89, 0x080, 24, 1, 6),
+ MTK_PIN_INFO(90, 0x080, 1, 1, 6),
+ MTK_PIN_INFO(95, 0x080, 15, 1, 6),
+ MTK_PIN_INFO(96, 0x080, 17, 1, 6),
+ MTK_PIN_INFO(97, 0x080, 18, 1, 6),
+ MTK_PIN_INFO(98, 0x080, 19, 1, 6),
+ MTK_PIN_INFO(99, 0x080, 20, 1, 6),
+ MTK_PIN_INFO(100, 0x080, 21, 1, 6),
+ MTK_PIN_INFO(101, 0x080, 22, 1, 6),
+ MTK_PIN_INFO(102, 0x080, 23, 1, 6),
+ MTK_PIN_INFO(103, 0x080, 28, 1, 6),
+ MTK_PIN_INFO(104, 0x080, 29, 1, 6),
+ MTK_PIN_INFO(105, 0x080, 30, 1, 6),
+ MTK_PIN_INFO(106, 0x080, 31, 1, 6),
+ MTK_PIN_INFO(107, 0x080, 0, 1, 7),
+ MTK_PIN_INFO(108, 0x080, 1, 1, 7),
+ MTK_PIN_INFO(109, 0x080, 2, 1, 7),
+ MTK_PIN_INFO(110, 0x080, 3, 1, 7),
+ MTK_PIN_INFO(111, 0x080, 4, 1, 7),
+ MTK_PIN_INFO(112, 0x080, 5, 1, 7),
+ MTK_PIN_INFO(113, 0x080, 6, 1, 7),
+ MTK_PIN_INFO(114, 0x080, 7, 1, 7),
+ MTK_PIN_INFO(115, 0x080, 8, 1, 7),
+ MTK_PIN_INFO(116, 0x080, 9, 1, 7),
+ MTK_PIN_INFO(117, 0x080, 10, 1, 7),
+ MTK_PIN_INFO(118, 0x080, 11, 1, 7),
+ MTK_PIN_INFO(119, 0x080, 12, 1, 7),
+ MTK_PIN_INFO(120, 0x080, 13, 1, 7),
+ MTK_PIN_INFO(121, 0x080, 14, 1, 7),
+ MTK_PIN_INFO(134, 0x080, 0, 1, 1),
+ MTK_PIN_INFO(135, 0x080, 1, 1, 1),
+ MTK_PIN_INFO(136, 0x080, 2, 1, 1),
+ MTK_PIN_INFO(137, 0x080, 3, 1, 1),
+ MTK_PIN_INFO(138, 0x080, 4, 1, 1),
+ MTK_PIN_INFO(139, 0x080, 5, 1, 1),
+ MTK_PIN_INFO(140, 0x080, 6, 1, 1),
+ MTK_PIN_INFO(141, 0x080, 7, 1, 1),
+ MTK_PIN_INFO(142, 0x080, 8, 1, 1),
+ MTK_PIN_INFO(143, 0x080, 9, 1, 1),
+ MTK_PIN_INFO(144, 0x080, 11, 1, 1),
+ MTK_PIN_INFO(145, 0x080, 12, 1, 1),
+ MTK_PIN_INFO(146, 0x080, 13, 1, 1),
+ MTK_PIN_INFO(147, 0x080, 14, 1, 1),
+ MTK_PIN_INFO(148, 0x080, 15, 1, 1),
+ MTK_PIN_INFO(149, 0x080, 16, 1, 1),
+ MTK_PIN_INFO(150, 0x080, 18, 1, 1),
+ MTK_PIN_INFO(151, 0x080, 19, 1, 1),
+ MTK_PIN_INFO(152, 0x080, 20, 1, 1),
+ MTK_PIN_INFO(153, 0x080, 21, 1, 1),
+ MTK_PIN_INFO(154, 0x080, 22, 1, 1),
+ MTK_PIN_INFO(155, 0x080, 23, 1, 1),
+ MTK_PIN_INFO(156, 0x080, 24, 1, 1),
+ MTK_PIN_INFO(157, 0x080, 25, 1, 1),
+ MTK_PIN_INFO(158, 0x080, 26, 1, 1),
+ MTK_PIN_INFO(159, 0x080, 27, 1, 1),
+ MTK_PIN_INFO(160, 0x080, 28, 1, 1),
+ MTK_PIN_INFO(161, 0x080, 0, 1, 2),
+ MTK_PIN_INFO(162, 0x080, 1, 1, 2),
+ MTK_PIN_INFO(163, 0x080, 2, 1, 2),
+ MTK_PIN_INFO(164, 0x080, 3, 1, 2),
+ MTK_PIN_INFO(165, 0x080, 4, 1, 2),
+ MTK_PIN_INFO(166, 0x080, 5, 1, 2),
+ MTK_PIN_INFO(167, 0x080, 11, 1, 4),
+ MTK_PIN_INFO(168, 0x080, 12, 1, 4),
+ MTK_PIN_INFO(169, 0x080, 13, 1, 4),
+ MTK_PIN_INFO(170, 0x080, 14, 1, 4),
+ MTK_PIN_INFO(171, 0x080, 15, 1, 4),
+ MTK_PIN_INFO(172, 0x080, 16, 1, 4),
+ MTK_PIN_INFO(173, 0x080, 17, 1, 4),
+ MTK_PIN_INFO(174, 0x080, 18, 1, 4),
+ MTK_PIN_INFO(175, 0x080, 19, 1, 4),
+ MTK_PIN_INFO(176, 0x080, 20, 1, 4),
+ MTK_PIN_INFO(177, 0x080, 10, 1, 6),
+ MTK_PIN_INFO(178, 0x080, 16, 1, 6),
+ MTK_PIN_INFO(179, 0x080, 25, 1, 6),
+};
+
+struct mtk_pin_info mt8183_pin_info_pupd_r1r0[] = {
+ MTK_PIN_INFO(29, 0x0C0, 0, 3, 2),
+ MTK_PIN_INFO(30, 0x0C0, 4, 3, 2),
+ MTK_PIN_INFO(31, 0x0C0, 8, 3, 2),
+ MTK_PIN_INFO(32, 0x0C0, 12, 3, 2),
+ MTK_PIN_INFO(33, 0x0C0, 16, 3, 2),
+ MTK_PIN_INFO(34, 0x0C0, 20, 3, 2),
+ MTK_PIN_INFO(35, 0x0C0, 0, 3, 3),
+ MTK_PIN_INFO(36, 0x0C0, 4, 3, 3),
+ MTK_PIN_INFO(37, 0x0C0, 8, 3, 3),
+ MTK_PIN_INFO(38, 0x0C0, 12, 3, 3),
+ MTK_PIN_INFO(39, 0x0C0, 16, 3, 3),
+ MTK_PIN_INFO(40, 0x0C0, 20, 3, 3),
+ MTK_PIN_INFO(41, 0x0C0, 24, 3, 3),
+ MTK_PIN_INFO(42, 0x0C0, 28, 3, 3),
+ MTK_PIN_INFO(91, 0x0C0, 0, 3, 6),
+ MTK_PIN_INFO(92, 0x0C0, 4, 3, 6),
+ MTK_PIN_INFO(93, 0x0C0, 8, 3, 6),
+ MTK_PIN_INFO(94, 0x0C0, 12, 3, 6),
+ MTK_PIN_INFO(122, 0x0C0, 0, 3, 8),
+ MTK_PIN_INFO(123, 0x0C0, 4, 3, 8),
+ MTK_PIN_INFO(124, 0x0C0, 8, 3, 8),
+ MTK_PIN_INFO(125, 0x0C0, 12, 3, 8),
+ MTK_PIN_INFO(126, 0x0C0, 16, 3, 8),
+ MTK_PIN_INFO(127, 0x0C0, 20, 3, 8),
+ MTK_PIN_INFO(128, 0x0C0, 24, 3, 8),
+ MTK_PIN_INFO(129, 0x0C0, 28, 3, 8),
+ MTK_PIN_INFO(130, 0x0D0, 0, 3, 8),
+ MTK_PIN_INFO(131, 0x0D0, 4, 3, 8),
+ MTK_PIN_INFO(132, 0x0D0, 8, 3, 8),
+ MTK_PIN_INFO(133, 0x0D0, 12, 3, 8),
+};
+
+struct mtk_pin_info mt8183_pin_info_mode[] = {
+ MTK_PIN_INFO(0, 0x300, 0, 3, 0),
+ MTK_PIN_INFO(1, 0x300, 4, 3, 0),
+ MTK_PIN_INFO(2, 0x300, 8, 3, 0),
+ MTK_PIN_INFO(3, 0x300, 12, 3, 0),
+ MTK_PIN_INFO(4, 0x300, 16, 3, 0),
+ MTK_PIN_INFO(5, 0x300, 20, 3, 0),
+ MTK_PIN_INFO(6, 0x300, 24, 3, 0),
+ MTK_PIN_INFO(7, 0x300, 28, 3, 0),
+ MTK_PIN_INFO(8, 0x310, 0, 3, 0),
+ MTK_PIN_INFO(9, 0x310, 4, 3, 0),
+ MTK_PIN_INFO(10, 0x310, 8, 3, 0),
+ MTK_PIN_INFO(11, 0x310, 12, 3, 0),
+ MTK_PIN_INFO(12, 0x310, 16, 3, 0),
+ MTK_PIN_INFO(13, 0x310, 20, 3, 0),
+ MTK_PIN_INFO(14, 0x310, 24, 3, 0),
+ MTK_PIN_INFO(15, 0x310, 28, 3, 0),
+ MTK_PIN_INFO(16, 0x320, 0, 3, 0),
+ MTK_PIN_INFO(17, 0x320, 4, 3, 0),
+ MTK_PIN_INFO(18, 0x320, 8, 3, 0),
+ MTK_PIN_INFO(19, 0x320, 12, 3, 0),
+ MTK_PIN_INFO(20, 0x320, 16, 3, 0),
+ MTK_PIN_INFO(21, 0x320, 20, 3, 0),
+ MTK_PIN_INFO(22, 0x320, 24, 3, 0),
+ MTK_PIN_INFO(23, 0x320, 28, 3, 0),
+ MTK_PIN_INFO(24, 0x330, 0, 3, 0),
+ MTK_PIN_INFO(25, 0x330, 4, 3, 0),
+ MTK_PIN_INFO(26, 0x330, 8, 3, 0),
+ MTK_PIN_INFO(27, 0x330, 12, 3, 0),
+ MTK_PIN_INFO(28, 0x330, 16, 3, 0),
+ MTK_PIN_INFO(29, 0x330, 20, 3, 0),
+ MTK_PIN_INFO(30, 0x330, 24, 3, 0),
+ MTK_PIN_INFO(31, 0x330, 28, 3, 0),
+ MTK_PIN_INFO(32, 0x340, 0, 3, 0),
+ MTK_PIN_INFO(33, 0x340, 4, 3, 0),
+ MTK_PIN_INFO(34, 0x340, 8, 3, 0),
+ MTK_PIN_INFO(35, 0x340, 12, 3, 0),
+ MTK_PIN_INFO(36, 0x340, 16, 3, 0),
+ MTK_PIN_INFO(37, 0x340, 20, 3, 0),
+ MTK_PIN_INFO(38, 0x340, 24, 3, 0),
+ MTK_PIN_INFO(39, 0x340, 28, 3, 0),
+ MTK_PIN_INFO(40, 0x350, 0, 3, 0),
+ MTK_PIN_INFO(41, 0x350, 4, 3, 0),
+ MTK_PIN_INFO(42, 0x350, 8, 3, 0),
+ MTK_PIN_INFO(43, 0x350, 12, 3, 0),
+ MTK_PIN_INFO(44, 0x350, 16, 3, 0),
+ MTK_PIN_INFO(45, 0x350, 20, 3, 0),
+ MTK_PIN_INFO(46, 0x350, 24, 3, 0),
+ MTK_PIN_INFO(47, 0x350, 28, 3, 0),
+ MTK_PIN_INFO(48, 0x360, 0, 3, 0),
+ MTK_PIN_INFO(49, 0x360, 4, 3, 0),
+ MTK_PIN_INFO(50, 0x360, 8, 3, 0),
+ MTK_PIN_INFO(51, 0x360, 12, 3, 0),
+ MTK_PIN_INFO(52, 0x360, 16, 3, 0),
+ MTK_PIN_INFO(53, 0x360, 20, 3, 0),
+ MTK_PIN_INFO(54, 0x360, 24, 3, 0),
+ MTK_PIN_INFO(55, 0x360, 28, 3, 0),
+ MTK_PIN_INFO(56, 0x370, 0, 3, 0),
+ MTK_PIN_INFO(57, 0x370, 4, 3, 0),
+ MTK_PIN_INFO(58, 0x370, 8, 3, 0),
+ MTK_PIN_INFO(59, 0x370, 12, 3, 0),
+ MTK_PIN_INFO(60, 0x370, 16, 3, 0),
+ MTK_PIN_INFO(61, 0x370, 20, 3, 0),
+ MTK_PIN_INFO(62, 0x370, 24, 3, 0),
+ MTK_PIN_INFO(63, 0x370, 28, 3, 0),
+ MTK_PIN_INFO(64, 0x380, 0, 3, 0),
+ MTK_PIN_INFO(65, 0x380, 4, 3, 0),
+ MTK_PIN_INFO(66, 0x380, 8, 3, 0),
+ MTK_PIN_INFO(67, 0x380, 12, 3, 0),
+ MTK_PIN_INFO(68, 0x380, 16, 3, 0),
+ MTK_PIN_INFO(69, 0x380, 20, 3, 0),
+ MTK_PIN_INFO(70, 0x380, 24, 3, 0),
+ MTK_PIN_INFO(71, 0x380, 28, 3, 0),
+ MTK_PIN_INFO(72, 0x390, 0, 3, 0),
+ MTK_PIN_INFO(73, 0x390, 4, 3, 0),
+ MTK_PIN_INFO(74, 0x390, 8, 3, 0),
+ MTK_PIN_INFO(75, 0x390, 12, 3, 0),
+ MTK_PIN_INFO(76, 0x390, 16, 3, 0),
+ MTK_PIN_INFO(77, 0x390, 20, 3, 0),
+ MTK_PIN_INFO(78, 0x390, 24, 3, 0),
+ MTK_PIN_INFO(79, 0x390, 28, 3, 0),
+ MTK_PIN_INFO(80, 0x3A0, 0, 3, 0),
+ MTK_PIN_INFO(81, 0x3A0, 4, 3, 0),
+ MTK_PIN_INFO(82, 0x3A0, 8, 3, 0),
+ MTK_PIN_INFO(83, 0x3A0, 12, 3, 0),
+ MTK_PIN_INFO(84, 0x3A0, 16, 3, 0),
+ MTK_PIN_INFO(85, 0x3A0, 20, 3, 0),
+ MTK_PIN_INFO(86, 0x3A0, 24, 3, 0),
+ MTK_PIN_INFO(87, 0x3A0, 28, 3, 0),
+ MTK_PIN_INFO(88, 0x3B0, 0, 3, 0),
+ MTK_PIN_INFO(89, 0x3B0, 4, 3, 0),
+ MTK_PIN_INFO(90, 0x3B0, 8, 3, 0),
+ MTK_PIN_INFO(91, 0x3B0, 12, 3, 0),
+ MTK_PIN_INFO(92, 0x3B0, 16, 3, 0),
+ MTK_PIN_INFO(93, 0x3B0, 20, 3, 0),
+ MTK_PIN_INFO(94, 0x3B0, 24, 3, 0),
+ MTK_PIN_INFO(95, 0x3B0, 28, 3, 0),
+ MTK_PIN_INFO(96, 0x3C0, 0, 3, 0),
+ MTK_PIN_INFO(97, 0x3C0, 4, 3, 0),
+ MTK_PIN_INFO(98, 0x3C0, 8, 3, 0),
+ MTK_PIN_INFO(99, 0x3C0, 12, 3, 0),
+ MTK_PIN_INFO(100, 0x3C0, 16, 3, 0),
+ MTK_PIN_INFO(101, 0x3C0, 20, 3, 0),
+ MTK_PIN_INFO(102, 0x3C0, 24, 3, 0),
+ MTK_PIN_INFO(103, 0x3C0, 28, 3, 0),
+ MTK_PIN_INFO(104, 0x3D0, 0, 3, 0),
+ MTK_PIN_INFO(105, 0x3D0, 4, 3, 0),
+ MTK_PIN_INFO(106, 0x3D0, 8, 3, 0),
+ MTK_PIN_INFO(107, 0x3D0, 12, 3, 0),
+ MTK_PIN_INFO(108, 0x3D0, 16, 3, 0),
+ MTK_PIN_INFO(109, 0x3D0, 20, 3, 0),
+ MTK_PIN_INFO(110, 0x3D0, 24, 3, 0),
+ MTK_PIN_INFO(111, 0x3D0, 28, 3, 0),
+ MTK_PIN_INFO(112, 0x3E0, 0, 3, 0),
+ MTK_PIN_INFO(113, 0x3E0, 4, 3, 0),
+ MTK_PIN_INFO(114, 0x3E0, 8, 3, 0),
+ MTK_PIN_INFO(115, 0x3E0, 12, 3, 0),
+ MTK_PIN_INFO(116, 0x3E0, 16, 3, 0),
+ MTK_PIN_INFO(117, 0x3E0, 20, 3, 0),
+ MTK_PIN_INFO(118, 0x3E0, 24, 3, 0),
+ MTK_PIN_INFO(119, 0x3E0, 28, 3, 0),
+ MTK_PIN_INFO(120, 0x3F0, 0, 3, 0),
+ MTK_PIN_INFO(121, 0x3F0, 4, 3, 0),
+ MTK_PIN_INFO(122, 0x3F0, 8, 3, 0),
+ MTK_PIN_INFO(123, 0x3F0, 12, 3, 0),
+ MTK_PIN_INFO(124, 0x3F0, 16, 3, 0),
+ MTK_PIN_INFO(125, 0x3F0, 20, 3, 0),
+ MTK_PIN_INFO(126, 0x3F0, 24, 3, 0),
+ MTK_PIN_INFO(127, 0x3F0, 28, 3, 0),
+ MTK_PIN_INFO(128, 0x400, 0, 3, 0),
+ MTK_PIN_INFO(129, 0x400, 4, 3, 0),
+ MTK_PIN_INFO(130, 0x400, 8, 3, 0),
+ MTK_PIN_INFO(131, 0x400, 12, 3, 0),
+ MTK_PIN_INFO(132, 0x400, 16, 3, 0),
+ MTK_PIN_INFO(133, 0x400, 20, 3, 0),
+ MTK_PIN_INFO(134, 0x400, 24, 3, 0),
+ MTK_PIN_INFO(135, 0x400, 28, 3, 0),
+ MTK_PIN_INFO(136, 0x410, 0, 3, 0),
+ MTK_PIN_INFO(137, 0x410, 4, 3, 0),
+ MTK_PIN_INFO(138, 0x410, 8, 3, 0),
+ MTK_PIN_INFO(139, 0x410, 12, 3, 0),
+ MTK_PIN_INFO(140, 0x410, 16, 3, 0),
+ MTK_PIN_INFO(141, 0x410, 20, 3, 0),
+ MTK_PIN_INFO(142, 0x410, 24, 3, 0),
+ MTK_PIN_INFO(143, 0x410, 28, 3, 0),
+ MTK_PIN_INFO(144, 0x420, 0, 3, 0),
+ MTK_PIN_INFO(145, 0x420, 4, 3, 0),
+ MTK_PIN_INFO(146, 0x420, 8, 3, 0),
+ MTK_PIN_INFO(147, 0x420, 12, 3, 0),
+ MTK_PIN_INFO(148, 0x420, 16, 3, 0),
+ MTK_PIN_INFO(149, 0x420, 20, 3, 0),
+ MTK_PIN_INFO(150, 0x420, 24, 3, 0),
+ MTK_PIN_INFO(151, 0x420, 28, 3, 0),
+ MTK_PIN_INFO(152, 0x430, 0, 3, 0),
+ MTK_PIN_INFO(153, 0x430, 4, 3, 0),
+ MTK_PIN_INFO(154, 0x430, 8, 3, 0),
+ MTK_PIN_INFO(155, 0x430, 12, 3, 0),
+ MTK_PIN_INFO(156, 0x430, 16, 3, 0),
+ MTK_PIN_INFO(157, 0x430, 20, 3, 0),
+ MTK_PIN_INFO(158, 0x430, 24, 3, 0),
+ MTK_PIN_INFO(159, 0x430, 28, 3, 0),
+ MTK_PIN_INFO(160, 0x440, 0, 3, 0),
+ MTK_PIN_INFO(161, 0x440, 4, 3, 0),
+ MTK_PIN_INFO(162, 0x440, 8, 3, 0),
+ MTK_PIN_INFO(163, 0x440, 12, 3, 0),
+ MTK_PIN_INFO(164, 0x440, 16, 3, 0),
+ MTK_PIN_INFO(165, 0x440, 20, 3, 0),
+ MTK_PIN_INFO(166, 0x440, 24, 3, 0),
+ MTK_PIN_INFO(167, 0x440, 28, 3, 0),
+ MTK_PIN_INFO(168, 0x450, 0, 3, 0),
+ MTK_PIN_INFO(169, 0x450, 4, 3, 0),
+ MTK_PIN_INFO(170, 0x450, 8, 3, 0),
+ MTK_PIN_INFO(171, 0x450, 12, 3, 0),
+ MTK_PIN_INFO(172, 0x450, 16, 3, 0),
+ MTK_PIN_INFO(173, 0x450, 20, 3, 0),
+ MTK_PIN_INFO(174, 0x450, 24, 3, 0),
+ MTK_PIN_INFO(175, 0x450, 28, 3, 0),
+ MTK_PIN_INFO(176, 0x460, 0, 3, 0),
+ MTK_PIN_INFO(177, 0x460, 4, 3, 0),
+ MTK_PIN_INFO(178, 0x460, 8, 3, 0),
+ MTK_PIN_INFO(179, 0x460, 12, 3, 0),
+};
+
+struct mtk_pin_info mt8183_pin_info_dataout[] = {
+ MTK_PIN_INFO(0, 0x100, 0, 1, 0),
+ MTK_PIN_INFO(1, 0x100, 1, 1, 0),
+ MTK_PIN_INFO(2, 0x100, 2, 1, 0),
+ MTK_PIN_INFO(3, 0x100, 3, 1, 0),
+ MTK_PIN_INFO(4, 0x100, 4, 1, 0),
+ MTK_PIN_INFO(5, 0x100, 5, 1, 0),
+ MTK_PIN_INFO(6, 0x100, 6, 1, 0),
+ MTK_PIN_INFO(7, 0x100, 7, 1, 0),
+ MTK_PIN_INFO(8, 0x100, 8, 1, 0),
+ MTK_PIN_INFO(9, 0x100, 9, 1, 0),
+ MTK_PIN_INFO(10, 0x100, 10, 1, 0),
+ MTK_PIN_INFO(11, 0x100, 11, 1, 0),
+ MTK_PIN_INFO(12, 0x100, 12, 1, 0),
+ MTK_PIN_INFO(13, 0x100, 13, 1, 0),
+ MTK_PIN_INFO(14, 0x100, 14, 1, 0),
+ MTK_PIN_INFO(15, 0x100, 15, 1, 0),
+ MTK_PIN_INFO(16, 0x100, 16, 1, 0),
+ MTK_PIN_INFO(17, 0x100, 17, 1, 0),
+ MTK_PIN_INFO(18, 0x100, 18, 1, 0),
+ MTK_PIN_INFO(19, 0x100, 19, 1, 0),
+ MTK_PIN_INFO(20, 0x100, 20, 1, 0),
+ MTK_PIN_INFO(21, 0x100, 21, 1, 0),
+ MTK_PIN_INFO(22, 0x100, 22, 1, 0),
+ MTK_PIN_INFO(23, 0x100, 23, 1, 0),
+ MTK_PIN_INFO(24, 0x100, 24, 1, 0),
+ MTK_PIN_INFO(25, 0x100, 25, 1, 0),
+ MTK_PIN_INFO(26, 0x100, 26, 1, 0),
+ MTK_PIN_INFO(27, 0x100, 27, 1, 0),
+ MTK_PIN_INFO(28, 0x100, 28, 1, 0),
+ MTK_PIN_INFO(29, 0x100, 29, 1, 0),
+ MTK_PIN_INFO(30, 0x100, 30, 1, 0),
+ MTK_PIN_INFO(31, 0x100, 31, 1, 0),
+ MTK_PIN_INFO(32, 0x110, 0, 1, 0),
+ MTK_PIN_INFO(33, 0x110, 1, 1, 0),
+ MTK_PIN_INFO(34, 0x110, 2, 1, 0),
+ MTK_PIN_INFO(35, 0x110, 3, 1, 0),
+ MTK_PIN_INFO(36, 0x110, 4, 1, 0),
+ MTK_PIN_INFO(37, 0x110, 5, 1, 0),
+ MTK_PIN_INFO(38, 0x110, 6, 1, 0),
+ MTK_PIN_INFO(39, 0x110, 7, 1, 0),
+ MTK_PIN_INFO(40, 0x110, 8, 1, 0),
+ MTK_PIN_INFO(41, 0x110, 9, 1, 0),
+ MTK_PIN_INFO(42, 0x110, 10, 1, 0),
+ MTK_PIN_INFO(43, 0x110, 11, 1, 0),
+ MTK_PIN_INFO(44, 0x110, 12, 1, 0),
+ MTK_PIN_INFO(45, 0x110, 13, 1, 0),
+ MTK_PIN_INFO(46, 0x110, 14, 1, 0),
+ MTK_PIN_INFO(47, 0x110, 15, 1, 0),
+ MTK_PIN_INFO(48, 0x110, 16, 1, 0),
+ MTK_PIN_INFO(49, 0x110, 17, 1, 0),
+ MTK_PIN_INFO(50, 0x110, 18, 1, 0),
+ MTK_PIN_INFO(51, 0x110, 19, 1, 0),
+ MTK_PIN_INFO(52, 0x110, 20, 1, 0),
+ MTK_PIN_INFO(53, 0x110, 21, 1, 0),
+ MTK_PIN_INFO(54, 0x110, 22, 1, 0),
+ MTK_PIN_INFO(55, 0x110, 23, 1, 0),
+ MTK_PIN_INFO(56, 0x110, 24, 1, 0),
+ MTK_PIN_INFO(57, 0x110, 25, 1, 0),
+ MTK_PIN_INFO(58, 0x110, 26, 1, 0),
+ MTK_PIN_INFO(59, 0x110, 27, 1, 0),
+ MTK_PIN_INFO(60, 0x110, 28, 1, 0),
+ MTK_PIN_INFO(61, 0x110, 29, 1, 0),
+ MTK_PIN_INFO(62, 0x110, 30, 1, 0),
+ MTK_PIN_INFO(63, 0x110, 31, 1, 0),
+ MTK_PIN_INFO(64, 0x120, 0, 1, 0),
+ MTK_PIN_INFO(65, 0x120, 1, 1, 0),
+ MTK_PIN_INFO(66, 0x120, 2, 1, 0),
+ MTK_PIN_INFO(67, 0x120, 3, 1, 0),
+ MTK_PIN_INFO(68, 0x120, 4, 1, 0),
+ MTK_PIN_INFO(69, 0x120, 5, 1, 0),
+ MTK_PIN_INFO(70, 0x120, 6, 1, 0),
+ MTK_PIN_INFO(71, 0x120, 7, 1, 0),
+ MTK_PIN_INFO(72, 0x120, 8, 1, 0),
+ MTK_PIN_INFO(73, 0x120, 9, 1, 0),
+ MTK_PIN_INFO(74, 0x120, 10, 1, 0),
+ MTK_PIN_INFO(75, 0x120, 11, 1, 0),
+ MTK_PIN_INFO(76, 0x120, 12, 1, 0),
+ MTK_PIN_INFO(77, 0x120, 13, 1, 0),
+ MTK_PIN_INFO(78, 0x120, 14, 1, 0),
+ MTK_PIN_INFO(79, 0x120, 15, 1, 0),
+ MTK_PIN_INFO(80, 0x120, 16, 1, 0),
+ MTK_PIN_INFO(81, 0x120, 17, 1, 0),
+ MTK_PIN_INFO(82, 0x120, 18, 1, 0),
+ MTK_PIN_INFO(83, 0x120, 19, 1, 0),
+ MTK_PIN_INFO(84, 0x120, 20, 1, 0),
+ MTK_PIN_INFO(85, 0x120, 21, 1, 0),
+ MTK_PIN_INFO(86, 0x120, 22, 1, 0),
+ MTK_PIN_INFO(87, 0x120, 23, 1, 0),
+ MTK_PIN_INFO(88, 0x120, 24, 1, 0),
+ MTK_PIN_INFO(89, 0x120, 25, 1, 0),
+ MTK_PIN_INFO(90, 0x120, 26, 1, 0),
+ MTK_PIN_INFO(91, 0x120, 27, 1, 0),
+ MTK_PIN_INFO(92, 0x120, 28, 1, 0),
+ MTK_PIN_INFO(93, 0x120, 29, 1, 0),
+ MTK_PIN_INFO(94, 0x120, 30, 1, 0),
+ MTK_PIN_INFO(95, 0x120, 31, 1, 0),
+ MTK_PIN_INFO(96, 0x130, 0, 1, 0),
+ MTK_PIN_INFO(97, 0x130, 1, 1, 0),
+ MTK_PIN_INFO(98, 0x130, 2, 1, 0),
+ MTK_PIN_INFO(99, 0x130, 3, 1, 0),
+ MTK_PIN_INFO(100, 0x130, 4, 1, 0),
+ MTK_PIN_INFO(101, 0x130, 5, 1, 0),
+ MTK_PIN_INFO(102, 0x130, 6, 1, 0),
+ MTK_PIN_INFO(103, 0x130, 7, 1, 0),
+ MTK_PIN_INFO(104, 0x130, 8, 1, 0),
+ MTK_PIN_INFO(105, 0x130, 9, 1, 0),
+ MTK_PIN_INFO(106, 0x130, 10, 1, 0),
+ MTK_PIN_INFO(107, 0x130, 11, 1, 0),
+ MTK_PIN_INFO(108, 0x130, 12, 1, 0),
+ MTK_PIN_INFO(109, 0x130, 13, 1, 0),
+ MTK_PIN_INFO(110, 0x130, 14, 1, 0),
+ MTK_PIN_INFO(111, 0x130, 15, 1, 0),
+ MTK_PIN_INFO(112, 0x130, 16, 1, 0),
+ MTK_PIN_INFO(113, 0x130, 17, 1, 0),
+ MTK_PIN_INFO(114, 0x130, 18, 1, 0),
+ MTK_PIN_INFO(115, 0x130, 19, 1, 0),
+ MTK_PIN_INFO(116, 0x130, 20, 1, 0),
+ MTK_PIN_INFO(117, 0x130, 21, 1, 0),
+ MTK_PIN_INFO(118, 0x130, 22, 1, 0),
+ MTK_PIN_INFO(119, 0x130, 23, 1, 0),
+ MTK_PIN_INFO(120, 0x130, 24, 1, 0),
+ MTK_PIN_INFO(121, 0x130, 25, 1, 0),
+ MTK_PIN_INFO(122, 0x130, 26, 1, 0),
+ MTK_PIN_INFO(123, 0x130, 27, 1, 0),
+ MTK_PIN_INFO(124, 0x130, 28, 1, 0),
+ MTK_PIN_INFO(125, 0x130, 29, 1, 0),
+ MTK_PIN_INFO(126, 0x130, 30, 1, 0),
+ MTK_PIN_INFO(127, 0x130, 31, 1, 0),
+ MTK_PIN_INFO(128, 0x140, 0, 1, 0),
+ MTK_PIN_INFO(129, 0x140, 1, 1, 0),
+ MTK_PIN_INFO(130, 0x140, 2, 1, 0),
+ MTK_PIN_INFO(131, 0x140, 3, 1, 0),
+ MTK_PIN_INFO(132, 0x140, 4, 1, 0),
+ MTK_PIN_INFO(133, 0x140, 5, 1, 0),
+ MTK_PIN_INFO(134, 0x140, 6, 1, 0),
+ MTK_PIN_INFO(135, 0x140, 7, 1, 0),
+ MTK_PIN_INFO(136, 0x140, 8, 1, 0),
+ MTK_PIN_INFO(137, 0x140, 9, 1, 0),
+ MTK_PIN_INFO(138, 0x140, 10, 1, 0),
+ MTK_PIN_INFO(139, 0x140, 11, 1, 0),
+ MTK_PIN_INFO(140, 0x140, 12, 1, 0),
+ MTK_PIN_INFO(141, 0x140, 13, 1, 0),
+ MTK_PIN_INFO(142, 0x140, 14, 1, 0),
+ MTK_PIN_INFO(143, 0x140, 15, 1, 0),
+ MTK_PIN_INFO(144, 0x140, 16, 1, 0),
+ MTK_PIN_INFO(145, 0x140, 17, 1, 0),
+ MTK_PIN_INFO(146, 0x140, 18, 1, 0),
+ MTK_PIN_INFO(147, 0x140, 19, 1, 0),
+ MTK_PIN_INFO(148, 0x140, 20, 1, 0),
+ MTK_PIN_INFO(149, 0x140, 21, 1, 0),
+ MTK_PIN_INFO(150, 0x140, 22, 1, 0),
+ MTK_PIN_INFO(151, 0x140, 23, 1, 0),
+ MTK_PIN_INFO(152, 0x140, 24, 1, 0),
+ MTK_PIN_INFO(153, 0x140, 25, 1, 0),
+ MTK_PIN_INFO(154, 0x140, 26, 1, 0),
+ MTK_PIN_INFO(155, 0x140, 27, 1, 0),
+ MTK_PIN_INFO(156, 0x140, 28, 1, 0),
+ MTK_PIN_INFO(157, 0x140, 29, 1, 0),
+ MTK_PIN_INFO(158, 0x140, 30, 1, 0),
+ MTK_PIN_INFO(159, 0x140, 31, 1, 0),
+ MTK_PIN_INFO(160, 0x150, 0, 1, 0),
+ MTK_PIN_INFO(161, 0x150, 1, 1, 0),
+ MTK_PIN_INFO(162, 0x150, 2, 1, 0),
+ MTK_PIN_INFO(163, 0x150, 3, 1, 0),
+ MTK_PIN_INFO(164, 0x150, 4, 1, 0),
+ MTK_PIN_INFO(165, 0x150, 5, 1, 0),
+ MTK_PIN_INFO(166, 0x150, 6, 1, 0),
+ MTK_PIN_INFO(167, 0x150, 7, 1, 0),
+ MTK_PIN_INFO(168, 0x150, 8, 1, 0),
+ MTK_PIN_INFO(169, 0x150, 9, 1, 0),
+ MTK_PIN_INFO(170, 0x150, 10, 1, 0),
+ MTK_PIN_INFO(171, 0x150, 11, 1, 0),
+ MTK_PIN_INFO(172, 0x150, 12, 1, 0),
+ MTK_PIN_INFO(173, 0x150, 13, 1, 0),
+ MTK_PIN_INFO(174, 0x150, 14, 1, 0),
+ MTK_PIN_INFO(175, 0x150, 15, 1, 0),
+ MTK_PIN_INFO(176, 0x150, 16, 1, 0),
+ MTK_PIN_INFO(177, 0x150, 17, 1, 0),
+ MTK_PIN_INFO(178, 0x150, 18, 1, 0),
+ MTK_PIN_INFO(179, 0x150, 19, 1, 0),
+};
+
+struct mtk_pin_info mt8183_pin_info_datain[] = {
+ MTK_PIN_INFO(0, 0x200, 0, 1, 0),
+ MTK_PIN_INFO(1, 0x200, 1, 1, 0),
+ MTK_PIN_INFO(2, 0x200, 2, 1, 0),
+ MTK_PIN_INFO(3, 0x200, 3, 1, 0),
+ MTK_PIN_INFO(4, 0x200, 4, 1, 0),
+ MTK_PIN_INFO(5, 0x200, 5, 1, 0),
+ MTK_PIN_INFO(6, 0x200, 6, 1, 0),
+ MTK_PIN_INFO(7, 0x200, 7, 1, 0),
+ MTK_PIN_INFO(8, 0x200, 8, 1, 0),
+ MTK_PIN_INFO(9, 0x200, 9, 1, 0),
+ MTK_PIN_INFO(10, 0x200, 10, 1, 0),
+ MTK_PIN_INFO(11, 0x200, 11, 1, 0),
+ MTK_PIN_INFO(12, 0x200, 12, 1, 0),
+ MTK_PIN_INFO(13, 0x200, 13, 1, 0),
+ MTK_PIN_INFO(14, 0x200, 14, 1, 0),
+ MTK_PIN_INFO(15, 0x200, 15, 1, 0),
+ MTK_PIN_INFO(16, 0x200, 16, 1, 0),
+ MTK_PIN_INFO(17, 0x200, 17, 1, 0),
+ MTK_PIN_INFO(18, 0x200, 18, 1, 0),
+ MTK_PIN_INFO(19, 0x200, 19, 1, 0),
+ MTK_PIN_INFO(20, 0x200, 20, 1, 0),
+ MTK_PIN_INFO(21, 0x200, 21, 1, 0),
+ MTK_PIN_INFO(22, 0x200, 22, 1, 0),
+ MTK_PIN_INFO(23, 0x200, 23, 1, 0),
+ MTK_PIN_INFO(24, 0x200, 24, 1, 0),
+ MTK_PIN_INFO(25, 0x200, 25, 1, 0),
+ MTK_PIN_INFO(26, 0x200, 26, 1, 0),
+ MTK_PIN_INFO(27, 0x200, 27, 1, 0),
+ MTK_PIN_INFO(28, 0x200, 28, 1, 0),
+ MTK_PIN_INFO(29, 0x200, 29, 1, 0),
+ MTK_PIN_INFO(30, 0x200, 30, 1, 0),
+ MTK_PIN_INFO(31, 0x200, 31, 1, 0),
+ MTK_PIN_INFO(32, 0x210, 0, 1, 0),
+ MTK_PIN_INFO(33, 0x210, 1, 1, 0),
+ MTK_PIN_INFO(34, 0x210, 2, 1, 0),
+ MTK_PIN_INFO(35, 0x210, 3, 1, 0),
+ MTK_PIN_INFO(36, 0x210, 4, 1, 0),
+ MTK_PIN_INFO(37, 0x210, 5, 1, 0),
+ MTK_PIN_INFO(38, 0x210, 6, 1, 0),
+ MTK_PIN_INFO(39, 0x210, 7, 1, 0),
+ MTK_PIN_INFO(40, 0x210, 8, 1, 0),
+ MTK_PIN_INFO(41, 0x210, 9, 1, 0),
+ MTK_PIN_INFO(42, 0x210, 10, 1, 0),
+ MTK_PIN_INFO(43, 0x210, 11, 1, 0),
+ MTK_PIN_INFO(44, 0x210, 12, 1, 0),
+ MTK_PIN_INFO(45, 0x210, 13, 1, 0),
+ MTK_PIN_INFO(46, 0x210, 14, 1, 0),
+ MTK_PIN_INFO(47, 0x210, 15, 1, 0),
+ MTK_PIN_INFO(48, 0x210, 16, 1, 0),
+ MTK_PIN_INFO(49, 0x210, 17, 1, 0),
+ MTK_PIN_INFO(50, 0x210, 18, 1, 0),
+ MTK_PIN_INFO(51, 0x210, 19, 1, 0),
+ MTK_PIN_INFO(52, 0x210, 20, 1, 0),
+ MTK_PIN_INFO(53, 0x210, 21, 1, 0),
+ MTK_PIN_INFO(54, 0x210, 22, 1, 0),
+ MTK_PIN_INFO(55, 0x210, 23, 1, 0),
+ MTK_PIN_INFO(56, 0x210, 24, 1, 0),
+ MTK_PIN_INFO(57, 0x210, 25, 1, 0),
+ MTK_PIN_INFO(58, 0x210, 26, 1, 0),
+ MTK_PIN_INFO(59, 0x210, 27, 1, 0),
+ MTK_PIN_INFO(60, 0x210, 28, 1, 0),
+ MTK_PIN_INFO(61, 0x210, 29, 1, 0),
+ MTK_PIN_INFO(62, 0x210, 30, 1, 0),
+ MTK_PIN_INFO(63, 0x210, 31, 1, 0),
+ MTK_PIN_INFO(64, 0x220, 0, 1, 0),
+ MTK_PIN_INFO(65, 0x220, 1, 1, 0),
+ MTK_PIN_INFO(66, 0x220, 2, 1, 0),
+ MTK_PIN_INFO(67, 0x220, 3, 1, 0),
+ MTK_PIN_INFO(68, 0x220, 4, 1, 0),
+ MTK_PIN_INFO(69, 0x220, 5, 1, 0),
+ MTK_PIN_INFO(70, 0x220, 6, 1, 0),
+ MTK_PIN_INFO(71, 0x220, 7, 1, 0),
+ MTK_PIN_INFO(72, 0x220, 8, 1, 0),
+ MTK_PIN_INFO(73, 0x220, 9, 1, 0),
+ MTK_PIN_INFO(74, 0x220, 10, 1, 0),
+ MTK_PIN_INFO(75, 0x220, 11, 1, 0),
+ MTK_PIN_INFO(76, 0x220, 12, 1, 0),
+ MTK_PIN_INFO(77, 0x220, 13, 1, 0),
+ MTK_PIN_INFO(78, 0x220, 14, 1, 0),
+ MTK_PIN_INFO(79, 0x220, 15, 1, 0),
+ MTK_PIN_INFO(80, 0x220, 16, 1, 0),
+ MTK_PIN_INFO(81, 0x220, 17, 1, 0),
+ MTK_PIN_INFO(82, 0x220, 18, 1, 0),
+ MTK_PIN_INFO(83, 0x220, 19, 1, 0),
+ MTK_PIN_INFO(84, 0x220, 20, 1, 0),
+ MTK_PIN_INFO(85, 0x220, 21, 1, 0),
+ MTK_PIN_INFO(86, 0x220, 22, 1, 0),
+ MTK_PIN_INFO(87, 0x220, 23, 1, 0),
+ MTK_PIN_INFO(88, 0x220, 24, 1, 0),
+ MTK_PIN_INFO(89, 0x220, 25, 1, 0),
+ MTK_PIN_INFO(90, 0x220, 26, 1, 0),
+ MTK_PIN_INFO(91, 0x220, 27, 1, 0),
+ MTK_PIN_INFO(92, 0x220, 28, 1, 0),
+ MTK_PIN_INFO(93, 0x220, 29, 1, 0),
+ MTK_PIN_INFO(94, 0x220, 30, 1, 0),
+ MTK_PIN_INFO(95, 0x220, 31, 1, 0),
+ MTK_PIN_INFO(96, 0x230, 0, 1, 0),
+ MTK_PIN_INFO(97, 0x230, 1, 1, 0),
+ MTK_PIN_INFO(98, 0x230, 2, 1, 0),
+ MTK_PIN_INFO(99, 0x230, 3, 1, 0),
+ MTK_PIN_INFO(100, 0x230, 4, 1, 0),
+ MTK_PIN_INFO(101, 0x230, 5, 1, 0),
+ MTK_PIN_INFO(102, 0x230, 6, 1, 0),
+ MTK_PIN_INFO(103, 0x230, 7, 1, 0),
+ MTK_PIN_INFO(104, 0x230, 8, 1, 0),
+ MTK_PIN_INFO(105, 0x230, 9, 1, 0),
+ MTK_PIN_INFO(106, 0x230, 10, 1, 0),
+ MTK_PIN_INFO(107, 0x230, 11, 1, 0),
+ MTK_PIN_INFO(108, 0x230, 12, 1, 0),
+ MTK_PIN_INFO(109, 0x230, 13, 1, 0),
+ MTK_PIN_INFO(110, 0x230, 14, 1, 0),
+ MTK_PIN_INFO(111, 0x230, 15, 1, 0),
+ MTK_PIN_INFO(112, 0x230, 16, 1, 0),
+ MTK_PIN_INFO(113, 0x230, 17, 1, 0),
+ MTK_PIN_INFO(114, 0x230, 18, 1, 0),
+ MTK_PIN_INFO(115, 0x230, 19, 1, 0),
+ MTK_PIN_INFO(116, 0x230, 20, 1, 0),
+ MTK_PIN_INFO(117, 0x230, 21, 1, 0),
+ MTK_PIN_INFO(118, 0x230, 22, 1, 0),
+ MTK_PIN_INFO(119, 0x230, 23, 1, 0),
+ MTK_PIN_INFO(120, 0x230, 24, 1, 0),
+ MTK_PIN_INFO(121, 0x230, 25, 1, 0),
+ MTK_PIN_INFO(122, 0x230, 26, 1, 0),
+ MTK_PIN_INFO(123, 0x230, 27, 1, 0),
+ MTK_PIN_INFO(124, 0x230, 28, 1, 0),
+ MTK_PIN_INFO(125, 0x230, 29, 1, 0),
+ MTK_PIN_INFO(126, 0x230, 30, 1, 0),
+ MTK_PIN_INFO(127, 0x230, 31, 1, 0),
+ MTK_PIN_INFO(128, 0x240, 0, 1, 0),
+ MTK_PIN_INFO(129, 0x240, 1, 1, 0),
+ MTK_PIN_INFO(130, 0x240, 2, 1, 0),
+ MTK_PIN_INFO(131, 0x240, 3, 1, 0),
+ MTK_PIN_INFO(132, 0x240, 4, 1, 0),
+ MTK_PIN_INFO(133, 0x240, 5, 1, 0),
+ MTK_PIN_INFO(134, 0x240, 6, 1, 0),
+ MTK_PIN_INFO(135, 0x240, 7, 1, 0),
+ MTK_PIN_INFO(136, 0x240, 8, 1, 0),
+ MTK_PIN_INFO(137, 0x240, 9, 1, 0),
+ MTK_PIN_INFO(138, 0x240, 10, 1, 0),
+ MTK_PIN_INFO(139, 0x240, 11, 1, 0),
+ MTK_PIN_INFO(140, 0x240, 12, 1, 0),
+ MTK_PIN_INFO(141, 0x240, 13, 1, 0),
+ MTK_PIN_INFO(142, 0x240, 14, 1, 0),
+ MTK_PIN_INFO(143, 0x240, 15, 1, 0),
+ MTK_PIN_INFO(144, 0x240, 16, 1, 0),
+ MTK_PIN_INFO(145, 0x240, 17, 1, 0),
+ MTK_PIN_INFO(146, 0x240, 18, 1, 0),
+ MTK_PIN_INFO(147, 0x240, 19, 1, 0),
+ MTK_PIN_INFO(148, 0x240, 20, 1, 0),
+ MTK_PIN_INFO(149, 0x240, 21, 1, 0),
+ MTK_PIN_INFO(150, 0x240, 22, 1, 0),
+ MTK_PIN_INFO(151, 0x240, 23, 1, 0),
+ MTK_PIN_INFO(152, 0x240, 24, 1, 0),
+ MTK_PIN_INFO(153, 0x240, 25, 1, 0),
+ MTK_PIN_INFO(154, 0x240, 26, 1, 0),
+ MTK_PIN_INFO(155, 0x240, 27, 1, 0),
+ MTK_PIN_INFO(156, 0x240, 28, 1, 0),
+ MTK_PIN_INFO(157, 0x240, 29, 1, 0),
+ MTK_PIN_INFO(158, 0x240, 30, 1, 0),
+ MTK_PIN_INFO(159, 0x240, 31, 1, 0),
+ MTK_PIN_INFO(160, 0x250, 0, 1, 0),
+ MTK_PIN_INFO(161, 0x250, 1, 1, 0),
+ MTK_PIN_INFO(162, 0x250, 2, 1, 0),
+ MTK_PIN_INFO(163, 0x250, 3, 1, 0),
+ MTK_PIN_INFO(164, 0x250, 4, 1, 0),
+ MTK_PIN_INFO(165, 0x250, 5, 1, 0),
+ MTK_PIN_INFO(166, 0x250, 6, 1, 0),
+ MTK_PIN_INFO(167, 0x250, 7, 1, 0),
+ MTK_PIN_INFO(168, 0x250, 8, 1, 0),
+ MTK_PIN_INFO(169, 0x250, 9, 1, 0),
+ MTK_PIN_INFO(170, 0x250, 10, 1, 0),
+ MTK_PIN_INFO(171, 0x250, 11, 1, 0),
+ MTK_PIN_INFO(172, 0x250, 12, 1, 0),
+ MTK_PIN_INFO(173, 0x250, 13, 1, 0),
+ MTK_PIN_INFO(174, 0x250, 14, 1, 0),
+ MTK_PIN_INFO(175, 0x250, 15, 1, 0),
+ MTK_PIN_INFO(176, 0x250, 16, 1, 0),
+ MTK_PIN_INFO(177, 0x250, 17, 1, 0),
+ MTK_PIN_INFO(178, 0x250, 18, 1, 0),
+ MTK_PIN_INFO(179, 0x250, 19, 1, 0),
+};
+
+struct mtk_pin_info mt8183_pin_info_dir[] = {
+ MTK_PIN_INFO(0, 0x000, 0, 1, 0),
+ MTK_PIN_INFO(1, 0x000, 1, 1, 0),
+ MTK_PIN_INFO(2, 0x000, 2, 1, 0),
+ MTK_PIN_INFO(3, 0x000, 3, 1, 0),
+ MTK_PIN_INFO(4, 0x000, 4, 1, 0),
+ MTK_PIN_INFO(5, 0x000, 5, 1, 0),
+ MTK_PIN_INFO(6, 0x000, 6, 1, 0),
+ MTK_PIN_INFO(7, 0x000, 7, 1, 0),
+ MTK_PIN_INFO(8, 0x000, 8, 1, 0),
+ MTK_PIN_INFO(9, 0x000, 9, 1, 0),
+ MTK_PIN_INFO(10, 0x000, 10, 1, 0),
+ MTK_PIN_INFO(11, 0x000, 11, 1, 0),
+ MTK_PIN_INFO(12, 0x000, 12, 1, 0),
+ MTK_PIN_INFO(13, 0x000, 13, 1, 0),
+ MTK_PIN_INFO(14, 0x000, 14, 1, 0),
+ MTK_PIN_INFO(15, 0x000, 15, 1, 0),
+ MTK_PIN_INFO(16, 0x000, 16, 1, 0),
+ MTK_PIN_INFO(17, 0x000, 17, 1, 0),
+ MTK_PIN_INFO(18, 0x000, 18, 1, 0),
+ MTK_PIN_INFO(19, 0x000, 19, 1, 0),
+ MTK_PIN_INFO(20, 0x000, 20, 1, 0),
+ MTK_PIN_INFO(21, 0x000, 21, 1, 0),
+ MTK_PIN_INFO(22, 0x000, 22, 1, 0),
+ MTK_PIN_INFO(23, 0x000, 23, 1, 0),
+ MTK_PIN_INFO(24, 0x000, 24, 1, 0),
+ MTK_PIN_INFO(25, 0x000, 25, 1, 0),
+ MTK_PIN_INFO(26, 0x000, 26, 1, 0),
+ MTK_PIN_INFO(27, 0x000, 27, 1, 0),
+ MTK_PIN_INFO(28, 0x000, 28, 1, 0),
+ MTK_PIN_INFO(29, 0x000, 29, 1, 0),
+ MTK_PIN_INFO(30, 0x000, 30, 1, 0),
+ MTK_PIN_INFO(31, 0x000, 31, 1, 0),
+ MTK_PIN_INFO(32, 0x010, 0, 1, 0),
+ MTK_PIN_INFO(33, 0x010, 1, 1, 0),
+ MTK_PIN_INFO(34, 0x010, 2, 1, 0),
+ MTK_PIN_INFO(35, 0x010, 3, 1, 0),
+ MTK_PIN_INFO(36, 0x010, 4, 1, 0),
+ MTK_PIN_INFO(37, 0x010, 5, 1, 0),
+ MTK_PIN_INFO(38, 0x010, 6, 1, 0),
+ MTK_PIN_INFO(39, 0x010, 7, 1, 0),
+ MTK_PIN_INFO(40, 0x010, 8, 1, 0),
+ MTK_PIN_INFO(41, 0x010, 9, 1, 0),
+ MTK_PIN_INFO(42, 0x010, 10, 1, 0),
+ MTK_PIN_INFO(43, 0x010, 11, 1, 0),
+ MTK_PIN_INFO(44, 0x010, 12, 1, 0),
+ MTK_PIN_INFO(45, 0x010, 13, 1, 0),
+ MTK_PIN_INFO(46, 0x010, 14, 1, 0),
+ MTK_PIN_INFO(47, 0x010, 15, 1, 0),
+ MTK_PIN_INFO(48, 0x010, 16, 1, 0),
+ MTK_PIN_INFO(49, 0x010, 17, 1, 0),
+ MTK_PIN_INFO(50, 0x010, 18, 1, 0),
+ MTK_PIN_INFO(51, 0x010, 19, 1, 0),
+ MTK_PIN_INFO(52, 0x010, 20, 1, 0),
+ MTK_PIN_INFO(53, 0x010, 21, 1, 0),
+ MTK_PIN_INFO(54, 0x010, 22, 1, 0),
+ MTK_PIN_INFO(55, 0x010, 23, 1, 0),
+ MTK_PIN_INFO(56, 0x010, 24, 1, 0),
+ MTK_PIN_INFO(57, 0x010, 25, 1, 0),
+ MTK_PIN_INFO(58, 0x010, 26, 1, 0),
+ MTK_PIN_INFO(59, 0x010, 27, 1, 0),
+ MTK_PIN_INFO(60, 0x010, 28, 1, 0),
+ MTK_PIN_INFO(61, 0x010, 29, 1, 0),
+ MTK_PIN_INFO(62, 0x010, 30, 1, 0),
+ MTK_PIN_INFO(63, 0x010, 31, 1, 0),
+ MTK_PIN_INFO(64, 0x020, 0, 1, 0),
+ MTK_PIN_INFO(65, 0x020, 1, 1, 0),
+ MTK_PIN_INFO(66, 0x020, 2, 1, 0),
+ MTK_PIN_INFO(67, 0x020, 3, 1, 0),
+ MTK_PIN_INFO(68, 0x020, 4, 1, 0),
+ MTK_PIN_INFO(69, 0x020, 5, 1, 0),
+ MTK_PIN_INFO(70, 0x020, 6, 1, 0),
+ MTK_PIN_INFO(71, 0x020, 7, 1, 0),
+ MTK_PIN_INFO(72, 0x020, 8, 1, 0),
+ MTK_PIN_INFO(73, 0x020, 9, 1, 0),
+ MTK_PIN_INFO(74, 0x020, 10, 1, 0),
+ MTK_PIN_INFO(75, 0x020, 11, 1, 0),
+ MTK_PIN_INFO(76, 0x020, 12, 1, 0),
+ MTK_PIN_INFO(77, 0x020, 13, 1, 0),
+ MTK_PIN_INFO(78, 0x020, 14, 1, 0),
+ MTK_PIN_INFO(79, 0x020, 15, 1, 0),
+ MTK_PIN_INFO(80, 0x020, 16, 1, 0),
+ MTK_PIN_INFO(81, 0x020, 17, 1, 0),
+ MTK_PIN_INFO(82, 0x020, 18, 1, 0),
+ MTK_PIN_INFO(83, 0x020, 19, 1, 0),
+ MTK_PIN_INFO(84, 0x020, 20, 1, 0),
+ MTK_PIN_INFO(85, 0x020, 21, 1, 0),
+ MTK_PIN_INFO(86, 0x020, 22, 1, 0),
+ MTK_PIN_INFO(87, 0x020, 23, 1, 0),
+ MTK_PIN_INFO(88, 0x020, 24, 1, 0),
+ MTK_PIN_INFO(89, 0x020, 25, 1, 0),
+ MTK_PIN_INFO(90, 0x020, 26, 1, 0),
+ MTK_PIN_INFO(91, 0x020, 27, 1, 0),
+ MTK_PIN_INFO(92, 0x020, 28, 1, 0),
+ MTK_PIN_INFO(93, 0x020, 29, 1, 0),
+ MTK_PIN_INFO(94, 0x020, 30, 1, 0),
+ MTK_PIN_INFO(95, 0x020, 31, 1, 0),
+ MTK_PIN_INFO(96, 0x030, 0, 1, 0),
+ MTK_PIN_INFO(97, 0x030, 1, 1, 0),
+ MTK_PIN_INFO(98, 0x030, 2, 1, 0),
+ MTK_PIN_INFO(99, 0x030, 3, 1, 0),
+ MTK_PIN_INFO(100, 0x030, 4, 1, 0),
+ MTK_PIN_INFO(101, 0x030, 5, 1, 0),
+ MTK_PIN_INFO(102, 0x030, 6, 1, 0),
+ MTK_PIN_INFO(103, 0x030, 7, 1, 0),
+ MTK_PIN_INFO(104, 0x030, 8, 1, 0),
+ MTK_PIN_INFO(105, 0x030, 9, 1, 0),
+ MTK_PIN_INFO(106, 0x030, 10, 1, 0),
+ MTK_PIN_INFO(107, 0x030, 11, 1, 0),
+ MTK_PIN_INFO(108, 0x030, 12, 1, 0),
+ MTK_PIN_INFO(109, 0x030, 13, 1, 0),
+ MTK_PIN_INFO(110, 0x030, 14, 1, 0),
+ MTK_PIN_INFO(111, 0x030, 15, 1, 0),
+ MTK_PIN_INFO(112, 0x030, 16, 1, 0),
+ MTK_PIN_INFO(113, 0x030, 17, 1, 0),
+ MTK_PIN_INFO(114, 0x030, 18, 1, 0),
+ MTK_PIN_INFO(115, 0x030, 19, 1, 0),
+ MTK_PIN_INFO(116, 0x030, 20, 1, 0),
+ MTK_PIN_INFO(117, 0x030, 21, 1, 0),
+ MTK_PIN_INFO(118, 0x030, 22, 1, 0),
+ MTK_PIN_INFO(119, 0x030, 23, 1, 0),
+ MTK_PIN_INFO(120, 0x030, 24, 1, 0),
+ MTK_PIN_INFO(121, 0x030, 25, 1, 0),
+ MTK_PIN_INFO(122, 0x030, 26, 1, 0),
+ MTK_PIN_INFO(123, 0x030, 27, 1, 0),
+ MTK_PIN_INFO(124, 0x030, 28, 1, 0),
+ MTK_PIN_INFO(125, 0x030, 29, 1, 0),
+ MTK_PIN_INFO(126, 0x030, 30, 1, 0),
+ MTK_PIN_INFO(127, 0x030, 31, 1, 0),
+ MTK_PIN_INFO(128, 0x040, 0, 1, 0),
+ MTK_PIN_INFO(129, 0x040, 1, 1, 0),
+ MTK_PIN_INFO(130, 0x040, 2, 1, 0),
+ MTK_PIN_INFO(131, 0x040, 3, 1, 0),
+ MTK_PIN_INFO(132, 0x040, 4, 1, 0),
+ MTK_PIN_INFO(133, 0x040, 5, 1, 0),
+ MTK_PIN_INFO(134, 0x040, 6, 1, 0),
+ MTK_PIN_INFO(135, 0x040, 7, 1, 0),
+ MTK_PIN_INFO(136, 0x040, 8, 1, 0),
+ MTK_PIN_INFO(137, 0x040, 9, 1, 0),
+ MTK_PIN_INFO(138, 0x040, 10, 1, 0),
+ MTK_PIN_INFO(139, 0x040, 11, 1, 0),
+ MTK_PIN_INFO(140, 0x040, 12, 1, 0),
+ MTK_PIN_INFO(141, 0x040, 13, 1, 0),
+ MTK_PIN_INFO(142, 0x040, 14, 1, 0),
+ MTK_PIN_INFO(143, 0x040, 15, 1, 0),
+ MTK_PIN_INFO(144, 0x040, 16, 1, 0),
+ MTK_PIN_INFO(145, 0x040, 17, 1, 0),
+ MTK_PIN_INFO(146, 0x040, 18, 1, 0),
+ MTK_PIN_INFO(147, 0x040, 19, 1, 0),
+ MTK_PIN_INFO(148, 0x040, 20, 1, 0),
+ MTK_PIN_INFO(149, 0x040, 21, 1, 0),
+ MTK_PIN_INFO(150, 0x040, 22, 1, 0),
+ MTK_PIN_INFO(151, 0x040, 23, 1, 0),
+ MTK_PIN_INFO(152, 0x040, 24, 1, 0),
+ MTK_PIN_INFO(153, 0x040, 25, 1, 0),
+ MTK_PIN_INFO(154, 0x040, 26, 1, 0),
+ MTK_PIN_INFO(155, 0x040, 27, 1, 0),
+ MTK_PIN_INFO(156, 0x040, 28, 1, 0),
+ MTK_PIN_INFO(157, 0x040, 29, 1, 0),
+ MTK_PIN_INFO(158, 0x040, 30, 1, 0),
+ MTK_PIN_INFO(159, 0x040, 31, 1, 0),
+ MTK_PIN_INFO(160, 0x050, 0, 1, 0),
+ MTK_PIN_INFO(161, 0x050, 1, 1, 0),
+ MTK_PIN_INFO(162, 0x050, 2, 1, 0),
+ MTK_PIN_INFO(163, 0x050, 3, 1, 0),
+ MTK_PIN_INFO(164, 0x050, 4, 1, 0),
+ MTK_PIN_INFO(165, 0x050, 5, 1, 0),
+ MTK_PIN_INFO(166, 0x050, 6, 1, 0),
+ MTK_PIN_INFO(167, 0x050, 7, 1, 0),
+ MTK_PIN_INFO(168, 0x050, 8, 1, 0),
+ MTK_PIN_INFO(169, 0x050, 9, 1, 0),
+ MTK_PIN_INFO(170, 0x050, 10, 1, 0),
+ MTK_PIN_INFO(171, 0x050, 11, 1, 0),
+ MTK_PIN_INFO(172, 0x050, 12, 1, 0),
+ MTK_PIN_INFO(173, 0x050, 13, 1, 0),
+ MTK_PIN_INFO(174, 0x050, 14, 1, 0),
+ MTK_PIN_INFO(175, 0x050, 15, 1, 0),
+ MTK_PIN_INFO(176, 0x050, 16, 1, 0),
+ MTK_PIN_INFO(177, 0x050, 17, 1, 0),
+ MTK_PIN_INFO(178, 0x050, 18, 1, 0),
+ MTK_PIN_INFO(179, 0x050, 19, 1, 0),
+};
+
+struct mtk_pin_info mt8183_pin_info_drv[] = {
+ MTK_PIN_INFO(0, 0x0A0, 12, 3, 6),
+ MTK_PIN_INFO(1, 0x0A0, 12, 3, 6),
+ MTK_PIN_INFO(2, 0x0A0, 12, 3, 6),
+ MTK_PIN_INFO(3, 0x0A0, 12, 3, 6),
+ MTK_PIN_INFO(4, 0x0A0, 20, 3, 6),
+ MTK_PIN_INFO(5, 0x0A0, 20, 3, 6),
+ MTK_PIN_INFO(6, 0x0A0, 20, 3, 6),
+ MTK_PIN_INFO(7, 0x0A0, 20, 3, 6),
+ MTK_PIN_INFO(8, 0x0A0, 0, 3, 6),
+ MTK_PIN_INFO(9, 0x0B0, 16, 3, 6),
+ MTK_PIN_INFO(10, 0x0B0, 16, 3, 6),
+ MTK_PIN_INFO(11, 0x0A0, 12, 3, 1),
+ MTK_PIN_INFO(12, 0x0A0, 28, 3, 1),
+ MTK_PIN_INFO(13, 0x0A0, 8, 3, 2),
+ MTK_PIN_INFO(14, 0x0A0, 8, 3, 2),
+ MTK_PIN_INFO(15, 0x0A0, 8, 3, 2),
+ MTK_PIN_INFO(16, 0x0A0, 8, 3, 2),
+ MTK_PIN_INFO(17, 0x0A0, 12, 3, 2),
+ MTK_PIN_INFO(18, 0x0A0, 12, 3, 2),
+ MTK_PIN_INFO(19, 0x0A0, 12, 3, 2),
+ MTK_PIN_INFO(20, 0x0A0, 12, 3, 2),
+ MTK_PIN_INFO(21, 0x0A0, 16, 3, 2),
+ MTK_PIN_INFO(22, 0x0A0, 16, 3, 2),
+ MTK_PIN_INFO(23, 0x0A0, 16, 3, 2),
+ MTK_PIN_INFO(24, 0x0A0, 16, 3, 2),
+ MTK_PIN_INFO(25, 0x0A0, 20, 3, 2),
+ MTK_PIN_INFO(26, 0x0A0, 20, 3, 2),
+ MTK_PIN_INFO(27, 0x0A0, 20, 3, 2),
+ MTK_PIN_INFO(28, 0x0A0, 20, 3, 2),
+ MTK_PIN_INFO(29, 0x0A0, 24, 3, 2),
+ MTK_PIN_INFO(30, 0x0A0, 28, 3, 2),
+ MTK_PIN_INFO(31, 0x0B0, 0, 3, 2),
+ MTK_PIN_INFO(32, 0x0A0, 28, 3, 2),
+ MTK_PIN_INFO(33, 0x0A0, 28, 3, 2),
+ MTK_PIN_INFO(34, 0x0A0, 28, 3, 2),
+ MTK_PIN_INFO(35, 0x0A0, 0, 3, 3),
+ MTK_PIN_INFO(36, 0x0A0, 0, 3, 3),
+ MTK_PIN_INFO(37, 0x0A0, 0, 3, 3),
+ MTK_PIN_INFO(38, 0x0A0, 4, 3, 3),
+ MTK_PIN_INFO(39, 0x0A0, 4, 3, 3),
+ MTK_PIN_INFO(40, 0x0A0, 4, 3, 3),
+ MTK_PIN_INFO(41, 0x0A0, 8, 3, 3),
+ MTK_PIN_INFO(42, 0x0A0, 8, 3, 3),
+ MTK_PIN_INFO(43, 0x0A0, 12, 3, 3),
+ MTK_PIN_INFO(44, 0x0A0, 12, 3, 3),
+ MTK_PIN_INFO(45, 0x0A0, 12, 3, 3),
+ MTK_PIN_INFO(46, 0x0A0, 16, 3, 3),
+ MTK_PIN_INFO(47, 0x0A0, 16, 3, 3),
+ MTK_PIN_INFO(48, 0x0A0, 20, 3, 3),
+ MTK_PIN_INFO(49, 0x0A0, 20, 3, 3),
+ MTK_PIN_INFO(50, 0x0A0, 0, 3, 4),
+ MTK_PIN_INFO(51, 0x0A0, 0, 3, 4),
+ MTK_PIN_INFO(52, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(53, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(54, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(55, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(56, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(57, 0x0A0, 4, 3, 4),
+ MTK_PIN_INFO(58, 0x0A0, 8, 3, 4),
+ MTK_PIN_INFO(59, 0x0A0, 8, 3, 4),
+ MTK_PIN_INFO(60, 0x0A0, 8, 3, 4),
+ MTK_PIN_INFO(61, 0x0A0, 0, 3, 5),
+ MTK_PIN_INFO(62, 0x0A0, 0, 3, 5),
+ MTK_PIN_INFO(63, 0x0A0, 0, 3, 5),
+ MTK_PIN_INFO(64, 0x0A0, 0, 3, 5),
+ MTK_PIN_INFO(65, 0x0A0, 4, 3, 5),
+ MTK_PIN_INFO(66, 0x0A0, 4, 3, 5),
+ MTK_PIN_INFO(67, 0x0A0, 8, 3, 5),
+ MTK_PIN_INFO(68, 0x0A0, 8, 3, 5),
+ MTK_PIN_INFO(69, 0x0A0, 12, 3, 5),
+ MTK_PIN_INFO(70, 0x0A0, 12, 3, 5),
+ MTK_PIN_INFO(71, 0x0A0, 12, 3, 5),
+ MTK_PIN_INFO(72, 0x0A0, 16, 3, 5),
+ MTK_PIN_INFO(73, 0x0A0, 16, 3, 5),
+ MTK_PIN_INFO(74, 0x0A0, 16, 3, 5),
+ MTK_PIN_INFO(75, 0x0A0, 16, 3, 5),
+ MTK_PIN_INFO(76, 0x0A0, 16, 3, 5),
+ MTK_PIN_INFO(77, 0x0A0, 20, 3, 5),
+ MTK_PIN_INFO(78, 0x0A0, 20, 3, 5),
+ MTK_PIN_INFO(79, 0x0A0, 20, 3, 5),
+ MTK_PIN_INFO(80, 0x0A0, 20, 3, 5),
+ MTK_PIN_INFO(81, 0x0A0, 24, 3, 5),
+ MTK_PIN_INFO(82, 0x0A0, 28, 3, 5),
+ MTK_PIN_INFO(83, 0x0A0, 28, 3, 5),
+ MTK_PIN_INFO(84, 0x0A0, 24, 3, 5),
+ MTK_PIN_INFO(85, 0x0B0, 0, 3, 5),
+ MTK_PIN_INFO(86, 0x0B0, 0, 3, 5),
+ MTK_PIN_INFO(87, 0x0B0, 0, 3, 5),
+ MTK_PIN_INFO(88, 0x0B0, 0, 3, 5),
+ MTK_PIN_INFO(89, 0x0B0, 12, 3, 6),
+ MTK_PIN_INFO(90, 0x0A0, 4, 3, 6),
+ MTK_PIN_INFO(91, 0x0A0, 8, 3, 6),
+ MTK_PIN_INFO(92, 0x0A0, 8, 3, 6),
+ MTK_PIN_INFO(93, 0x0A0, 8, 3, 6),
+ MTK_PIN_INFO(94, 0x0A0, 8, 3, 6),
+ MTK_PIN_INFO(95, 0x0A0, 24, 3, 6),
+ MTK_PIN_INFO(96, 0x0A0, 24, 3, 6),
+ MTK_PIN_INFO(97, 0x0A0, 28, 3, 6),
+ MTK_PIN_INFO(98, 0x0A0, 28, 3, 6),
+ MTK_PIN_INFO(99, 0x0B0, 0, 3, 6),
+ MTK_PIN_INFO(100, 0x0B0, 4, 3, 6),
+ MTK_PIN_INFO(101, 0x0B0, 8, 3, 6),
+ MTK_PIN_INFO(102, 0x0B0, 8, 3, 6),
+ MTK_PIN_INFO(103, 0x0B0, 20, 3, 6),
+ MTK_PIN_INFO(104, 0x0B0, 20, 3, 6),
+ MTK_PIN_INFO(105, 0x0B0, 24, 3, 6),
+ MTK_PIN_INFO(106, 0x0B0, 24, 3, 6),
+ MTK_PIN_INFO(107, 0x0A0, 0, 3, 7),
+ MTK_PIN_INFO(108, 0x0A0, 4, 3, 7),
+ MTK_PIN_INFO(109, 0x0A0, 8, 3, 7),
+ MTK_PIN_INFO(110, 0x0A0, 0, 3, 7),
+ MTK_PIN_INFO(111, 0x0A0, 12, 3, 7),
+ MTK_PIN_INFO(112, 0x0A0, 8, 3, 7),
+ MTK_PIN_INFO(113, 0x0A0, 16, 3, 7),
+ MTK_PIN_INFO(114, 0x0A0, 20, 3, 7),
+ MTK_PIN_INFO(115, 0x0A0, 24, 3, 7),
+ MTK_PIN_INFO(116, 0x0A0, 28, 3, 7),
+ MTK_PIN_INFO(117, 0x0B0, 0, 3, 7),
+ MTK_PIN_INFO(118, 0x0B0, 4, 3, 7),
+ MTK_PIN_INFO(119, 0x0B0, 8, 3, 7),
+ MTK_PIN_INFO(120, 0x0B0, 12, 3, 7),
+ MTK_PIN_INFO(121, 0x0B0, 16, 3, 7),
+ MTK_PIN_INFO(122, 0x0A0, 0, 3, 8),
+ MTK_PIN_INFO(123, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(124, 0x0A0, 8, 3, 8),
+ MTK_PIN_INFO(125, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(126, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(127, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(128, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(129, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(130, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(131, 0x0A0, 12, 3, 8),
+ MTK_PIN_INFO(132, 0x0A0, 4, 3, 8),
+ MTK_PIN_INFO(133, 0x0A0, 16, 3, 8),
+ MTK_PIN_INFO(134, 0x0A0, 0, 3, 1),
+ MTK_PIN_INFO(135, 0x0A0, 4, 3, 1),
+ MTK_PIN_INFO(136, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(137, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(138, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(139, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(140, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(141, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(142, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(143, 0x0A0, 8, 3, 1),
+ MTK_PIN_INFO(144, 0x0A0, 16, 3, 1),
+ MTK_PIN_INFO(145, 0x0A0, 16, 3, 1),
+ MTK_PIN_INFO(146, 0x0A0, 16, 3, 1),
+ MTK_PIN_INFO(147, 0x0A0, 16, 3, 1),
+ MTK_PIN_INFO(148, 0x0A0, 20, 3, 1),
+ MTK_PIN_INFO(149, 0x0A0, 24, 3, 1),
+ MTK_PIN_INFO(150, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(151, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(152, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(153, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(154, 0x0B0, 4, 3, 1),
+ MTK_PIN_INFO(155, 0x0B0, 8, 3, 1),
+ MTK_PIN_INFO(156, 0x0B0, 8, 3, 1),
+ MTK_PIN_INFO(157, 0x0B0, 8, 3, 1),
+ MTK_PIN_INFO(158, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(159, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(160, 0x0B0, 0, 3, 1),
+ MTK_PIN_INFO(161, 0x0A0, 0, 3, 2),
+ MTK_PIN_INFO(162, 0x0A0, 0, 3, 2),
+ MTK_PIN_INFO(163, 0x0A0, 0, 3, 2),
+ MTK_PIN_INFO(164, 0x0A0, 0, 3, 2),
+ MTK_PIN_INFO(165, 0x0A0, 4, 3, 2),
+ MTK_PIN_INFO(166, 0x0A0, 4, 3, 2),
+ MTK_PIN_INFO(167, 0x0A0, 8, 3, 4),
+ MTK_PIN_INFO(168, 0x0A0, 8, 3, 4),
+ MTK_PIN_INFO(169, 0x0A0, 12, 3, 4),
+ MTK_PIN_INFO(170, 0x0A0, 16, 3, 4),
+ MTK_PIN_INFO(171, 0x0A0, 16, 3, 4),
+ MTK_PIN_INFO(172, 0x0A0, 16, 3, 4),
+ MTK_PIN_INFO(173, 0x0A0, 16, 3, 4),
+ MTK_PIN_INFO(174, 0x0A0, 16, 3, 4),
+ MTK_PIN_INFO(175, 0x0A0, 12, 3, 4),
+ MTK_PIN_INFO(176, 0x0A0, 12, 3, 4),
+ MTK_PIN_INFO(177, 0x0A0, 16, 3, 6),
+ MTK_PIN_INFO(178, 0x0A0, 16, 3, 6),
+ MTK_PIN_INFO(179, 0x0A0, 16, 3, 6),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt8183_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(29, 0x0C0, 2, 1, 0, 2),
+ MTK_PIN_PUPD_SPEC_SR(30, 0x0C0, 6, 5, 4, 2),
+ MTK_PIN_PUPD_SPEC_SR(31, 0x0C0, 10, 9, 8, 2),
+ MTK_PIN_PUPD_SPEC_SR(32, 0x0C0, 14, 13, 12, 2),
+ MTK_PIN_PUPD_SPEC_SR(33, 0x0C0, 18, 17, 16, 2),
+ MTK_PIN_PUPD_SPEC_SR(34, 0x0C0, 22, 21, 20, 2),
+ MTK_PIN_PUPD_SPEC_SR(35, 0x0C0, 2, 1, 0, 3),
+ MTK_PIN_PUPD_SPEC_SR(36, 0x0C0, 6, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(37, 0x0C0, 10, 9, 8, 3),
+ MTK_PIN_PUPD_SPEC_SR(38, 0x0C0, 14, 13, 12, 3),
+ MTK_PIN_PUPD_SPEC_SR(39, 0x0C0, 18, 17, 16, 3),
+ MTK_PIN_PUPD_SPEC_SR(40, 0x0C0, 22, 21, 20, 3),
+ MTK_PIN_PUPD_SPEC_SR(41, 0x0C0, 26, 25, 24, 3),
+ MTK_PIN_PUPD_SPEC_SR(42, 0x0C0, 30, 29, 28, 3),
+ MTK_PIN_PUPD_SPEC_SR(91, 0x0C0, 2, 1, 0, 6),
+ MTK_PIN_PUPD_SPEC_SR(92, 0x0C0, 6, 5, 4, 6),
+ MTK_PIN_PUPD_SPEC_SR(93, 0x0C0, 10, 9, 8, 6),
+ MTK_PIN_PUPD_SPEC_SR(94, 0x0C0, 14, 13, 12, 6),
+ MTK_PIN_PUPD_SPEC_SR(122, 0x0C0, 2, 1, 0, 8),
+ MTK_PIN_PUPD_SPEC_SR(123, 0x0C0, 6, 5, 4, 8),
+ MTK_PIN_PUPD_SPEC_SR(124, 0x0C0, 10, 9, 8, 8),
+ MTK_PIN_PUPD_SPEC_SR(125, 0x0C0, 14, 13, 12, 8),
+ MTK_PIN_PUPD_SPEC_SR(126, 0x0C0, 18, 17, 16, 8),
+ MTK_PIN_PUPD_SPEC_SR(127, 0x0C0, 22, 21, 20, 8),
+ MTK_PIN_PUPD_SPEC_SR(128, 0x0C0, 26, 25, 24, 8),
+ MTK_PIN_PUPD_SPEC_SR(129, 0x0C0, 30, 29, 28, 8),
+ MTK_PIN_PUPD_SPEC_SR(130, 0x0D0, 2, 1, 0, 8),
+ MTK_PIN_PUPD_SPEC_SR(131, 0x0D0, 6, 5, 4, 8),
+ MTK_PIN_PUPD_SPEC_SR(132, 0x0D0, 10, 9, 8, 8),
+ MTK_PIN_PUPD_SPEC_SR(133, 0x0D0, 14, 13, 12, 8),
+};
+
+static int mtk_pinctrl_set_gpio_ies(struct mtk_pinctrl *pctl,
+ int pin, bool enable)
+{
+ return mtk_pinctrl_set_gpio_value(pctl, pin, enable,
+ pctl->devdata->n_pin_ies, pctl->devdata->pin_ies_grps);
+}
+
+static int mtk_pinctrl_set_gpio_smt(struct mtk_pinctrl *pctl,
+ int pin, bool enable)
+{
+ return mtk_pinctrl_set_gpio_value(pctl, pin, enable,
+ pctl->devdata->n_pin_smt, pctl->devdata->pin_smt_grps);
+}
+
+static int mt8183_ies_smt_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pinctrl_set_gpio_ies(pctl,
+ pin, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pinctrl_set_gpio_smt(pctl,
+ pin, value);
+ return -EINVAL;
+}
+
+static int mt8183_spec_pull_set(struct mtk_pinctrl *pctl,
+ struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(pctl, regmap, mt8183_spec_pupd,
+ ARRAY_SIZE(mt8183_spec_pupd), pin, align, isup, r1r0);
+}
+
+static void mt8183_spec_pinmux_set(struct regmap *reg, unsigned int pin,
+ unsigned int mode)
+{
+ unsigned int reg_addr;
+ unsigned char bit;
+ unsigned int val;
+ unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
+
+ reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << 4) + 0x0300;
+ mode &= mask;
+ bit = pin % MAX_GPIO_MODE_PER_REG;
+ mask <<= (GPIO_MODE_BITS * bit);
+ val = (mode << (GPIO_MODE_BITS * bit));
+
+ regmap_update_bits(reg, reg_addr, mask, val);
+}
+
+static const struct mtk_pinctrl_devdata mt8183_pinctrl_data = {
+ .pins = mtk_pins_mt8183,
+ .npins = ARRAY_SIZE(mtk_pins_mt8183),
+ .pin_drv_grps = mt8183_pin_info_drv,
+ .n_pin_drv = ARRAY_SIZE(mt8183_pin_info_drv),
+ .pin_mode_grps = mt8183_pin_info_mode,
+ .n_pin_mode = ARRAY_SIZE(mt8183_pin_info_mode),
+ .pin_ies_grps = mt8183_pin_info_ies,
+ .n_pin_ies = ARRAY_SIZE(mt8183_pin_info_ies),
+ .pin_smt_grps = mt8183_pin_info_smt,
+ .n_pin_smt = ARRAY_SIZE(mt8183_pin_info_smt),
+ .pin_pullsel_grps = mt8183_pin_info_pullsel,
+ .n_pin_pullsel = ARRAY_SIZE(mt8183_pin_info_pullsel),
+ .pin_pullen_grps = mt8183_pin_info_pullen,
+ .n_pin_pullen = ARRAY_SIZE(mt8183_pin_info_pullen),
+ .pin_pupd_r1r0_grps = mt8183_pin_info_pupd_r1r0,
+ .n_pin_pupd_r1r0 = ARRAY_SIZE(mt8183_pin_info_pupd_r1r0),
+ .spec_ies_smt_set = mt8183_ies_smt_set,
+ .spec_pull_set = mt8183_spec_pull_set,
+ .spec_pinmux_set = mt8183_spec_pinmux_set,
+ .dir_offset = 0x0000,
+ .dout_offset = 0x0100,
+ .din_offset = 0x0200,
+ .pinmux_offset = 0x0300,
+ .ies_offset = 0x0000,
+ .smt_offset = 0x0010,
+ .pullen_offset = 0x0060,
+ .pullsel_offset = 0x0080,
+ .drv_offset = 0x00a0,
+ .type1_start = 192,
+ .type1_end = 192,
+ .regmap_num = 9,
+ .port_shf = 4,
+ .port_mask = 0x1f,
+ .port_align = 4,
+ .port_pin_shf = 5,
+ .eint_offsets = {
+ .name = "mt8183_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 7,
+ .ports = 6,
+ },
+ .ap_num = 212,
+ .db_cnt = 13,
+};
+
+static int mtk_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8183_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt8183_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt8183-pinctrl",
+ },
+ { }
+};
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mtk_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt8183-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = mt8183_pctrl_match,
+ .pm = &mtk_eint_pm_ops,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+arch_initcall(mtk_pinctrl_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
+MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>");
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
new file mode 100644
index 0000000..49a66ef
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -0,0 +1,993 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "mtk-eint.h"
+#include "pinctrl-mtk-common-v2.h"
+
+/**
+ * struct mtk_drive_desc - the structure that holds the information
+ * of the driving current
+ * @min: the minimum current of this group
+ * @max: the maximum current of this group
+ * @step: the step current of this group
+ * @scal: the weight factor
+ *
+ * formula: output = ((input) / step - 1) * scal
+ */
+struct mtk_drive_desc {
+ u8 min;
+ u8 max;
+ u8 step;
+ u8 scal;
+};
+
+/* The groups of drive strength */
+static const struct mtk_drive_desc mtk_drive[] = {
+ [DRV_GRP0] = { 4, 16, 4, 1 },
+ [DRV_GRP1] = { 4, 16, 4, 2 },
+ [DRV_GRP2] = { 2, 8, 2, 1 },
+ [DRV_GRP3] = { 2, 8, 2, 2 },
+ [DRV_GRP4] = { 2, 16, 2, 1 },
+};
+
+static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
+{
+ writel_relaxed(val, pctl->base[i] + reg);
+}
+
+static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
+{
+ return readl_relaxed(pctl->base[i] + reg);
+}
+
+void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
+{
+ u32 val;
+
+ val = mtk_r32(pctl, i, reg);
+ val &= ~mask;
+ val |= set;
+ mtk_w32(pctl, i, reg, val);
+}
+
+static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ int field, struct mtk_pin_field *pfd)
+{
+ const struct mtk_pin_field_calc *c, *e;
+ const struct mtk_pin_reg_calc *rc;
+ u32 bits;
+
+ if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
+ rc = &hw->soc->reg_cal[field];
+ } else {
+ dev_dbg(hw->dev,
+ "Not support field %d for pin %d (%s)\n",
+ field, desc->number, desc->name);
+ return -ENOTSUPP;
+ }
+
+ c = rc->range;
+ e = c + rc->nranges;
+
+ while (c < e) {
+ if (desc->number >= c->s_pin && desc->number <= c->e_pin)
+ break;
+ c++;
+ }
+
+ if (c >= e) {
+ dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
+ field, desc->number, desc->name);
+ return -ENOTSUPP;
+ }
+
+ if (c->i_base > hw->nbase - 1) {
+ dev_err(hw->dev,
+ "Invalid base for field %d for pin = %d (%s)\n",
+ field, desc->number, desc->name);
+ return -EINVAL;
+ }
+
+ /* Calculated bits as the overall offset the pin is located at,
+ * if c->fixed is held, that determines the all the pins in the
+ * range use the same field with the s_pin.
+ */
+ bits = c->fixed ? c->s_bit : c->s_bit +
+ (desc->number - c->s_pin) * (c->x_bits);
+
+ /* Fill pfd from bits. For example 32-bit register applied is assumed
+ * when c->sz_reg is equal to 32.
+ */
+ pfd->index = c->i_base;
+ pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
+ pfd->bitpos = bits % c->sz_reg;
+ pfd->mask = (1 << c->x_bits) - 1;
+
+ /* pfd->next is used for indicating that bit wrapping-around happens
+ * which requires the manipulation for bit 0 starting in the next
+ * register to form the complete field read/write.
+ */
+ pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
+
+ return 0;
+}
+
+static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ int field, struct mtk_pin_field *pfd)
+{
+ if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
+ dev_err(hw->dev, "Invalid Field %d\n", field);
+ return -EINVAL;
+ }
+
+ return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
+}
+
+static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
+{
+ *l = 32 - pf->bitpos;
+ *h = get_count_order(pf->mask) - *l;
+}
+
+static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
+ struct mtk_pin_field *pf, int value)
+{
+ int nbits_l, nbits_h;
+
+ mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
+
+ mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
+ (value & pf->mask) << pf->bitpos);
+
+ mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
+ (value & pf->mask) >> nbits_l);
+}
+
+static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
+ struct mtk_pin_field *pf, int *value)
+{
+ int nbits_l, nbits_h, h, l;
+
+ mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
+
+ l = (mtk_r32(hw, pf->index, pf->offset)
+ >> pf->bitpos) & (BIT(nbits_l) - 1);
+ h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
+ & (BIT(nbits_h) - 1);
+
+ *value = (h << nbits_l) | l;
+}
+
+int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+ int field, int value)
+{
+ struct mtk_pin_field pf;
+ int err;
+
+ err = mtk_hw_pin_field_get(hw, desc, field, &pf);
+ if (err)
+ return err;
+
+ if (!pf.next)
+ mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
+ (value & pf.mask) << pf.bitpos);
+ else
+ mtk_hw_write_cross_field(hw, &pf, value);
+
+ return 0;
+}
+
+void mtk_hw_set_value_no_lookup(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ int value, struct mtk_pin_field *pf)
+{
+ if (value < 0 || value > pf->mask)
+ return;
+
+ if (!pf->next)
+ mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
+ (value & pf->mask) << pf->bitpos);
+ else
+ mtk_hw_write_cross_field(hw, pf, value);
+}
+
+int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+ int field, int *value)
+{
+ struct mtk_pin_field pf;
+ int err;
+
+ err = mtk_hw_pin_field_get(hw, desc, field, &pf);
+ if (err)
+ return err;
+
+ if (!pf.next)
+ *value = (mtk_r32(hw, pf.index, pf.offset)
+ >> pf.bitpos) & pf.mask;
+ else
+ mtk_hw_read_cross_field(hw, &pf, value);
+
+ return 0;
+}
+
+void mtk_hw_get_value_no_lookup(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ int *value, struct mtk_pin_field *pf)
+{
+ if (!pf->next)
+ *value = (mtk_r32(hw, pf->index, pf->offset)
+ >> pf->bitpos) & pf->mask;
+ else
+ mtk_hw_read_cross_field(hw, pf, value);
+}
+
+static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n,
+ unsigned int *virt_gpio)
+{
+ const struct mtk_pin_desc *desc;
+ int i = 0;
+
+ desc = (const struct mtk_pin_desc *)hw->soc->pins;
+
+ while (i < hw->soc->npins) {
+ if (desc[i].eint.eint_n == eint_n) {
+ if (desc[i].funcs[desc[i].eint.eint_m].name == 0)
+ *virt_gpio = 1;
+ return desc[i].number;
+ }
+ i++;
+ }
+
+ return EINT_NA;
+}
+
+static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
+ unsigned int *gpio_n,
+ struct gpio_chip **gpio_chip)
+{
+ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+ const struct mtk_pin_desc *desc;
+ unsigned int virt_gpio = 0;
+
+ desc = (const struct mtk_pin_desc *)hw->soc->pins;
+ *gpio_chip = &hw->chip;
+
+ /* Be greedy to guess first gpio_n is equal to eint_n */
+ if (desc[eint_n].eint.eint_n == eint_n)
+ *gpio_n = eint_n;
+ else
+ *gpio_n = mtk_xt_find_eint_num(hw, eint_n, &virt_gpio);
+
+ if (virt_gpio)
+ return EINT_NO_GPIO;
+
+ return *gpio_n == EINT_NA ? -EINVAL : 0;
+}
+
+static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
+{
+ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+ const struct mtk_pin_desc *desc;
+ struct gpio_chip *gpio_chip;
+ unsigned int gpio_n;
+ int value, err;
+
+ err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
+ if (err)
+ return err;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
+ if (err)
+ return err;
+
+ return !!value;
+}
+
+static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
+{
+ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+ const struct mtk_pin_desc *desc;
+ struct gpio_chip *gpio_chip;
+ unsigned int gpio_n;
+ int err;
+
+ err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
+ if (err)
+ return err;
+
+ if (err == EINT_NO_GPIO)
+ return 0;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+ desc->eint.eint_m);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
+ /* SMT is supposed to be supported by every real GPIO and doesn't
+ * support virtual GPIOs, so the extra condition err != -ENOTSUPP
+ * is just for adding EINT support to these virtual GPIOs. It should
+ * add an extra flag in the pin descriptor when more pins with
+ * distinctive characteristic come out.
+ */
+ if (err && err != -ENOTSUPP)
+ return err;
+
+ return 0;
+}
+
+static const struct mtk_eint_xt mtk_eint_xt = {
+ .get_gpio_n = mtk_xt_get_gpio_n,
+ .get_gpio_state = mtk_xt_get_gpio_state,
+ .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
+};
+
+int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *res;
+
+ if (!IS_ENABLED(CONFIG_EINT_MTK))
+ return 0;
+
+ if (!of_property_read_bool(np, "interrupt-controller"))
+ return -ENODEV;
+
+ hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
+ if (!hw->eint)
+ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get eint resource\n");
+ return -ENODEV;
+ }
+
+ hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hw->eint->base))
+ return PTR_ERR(hw->eint->base);
+
+ hw->eint->irq = irq_of_parse_and_map(np, 0);
+ if (!hw->eint->irq)
+ return -EINVAL;
+
+ if (!hw->soc->eint_hw)
+ return -ENODEV;
+
+ hw->eint->dev = &pdev->dev;
+ hw->eint->hw = hw->soc->eint_hw;
+ hw->eint->pctl = hw;
+ hw->eint->gpio_xlate = &mtk_eint_xt;
+
+ return mtk_eint_do_init(hw->eint);
+}
+
+/* Revision 0 */
+int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc)
+{
+ int err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
+ MTK_DISABLE);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
+ MTK_DISABLE);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *res)
+{
+ int v, v2;
+ int err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
+ if (err)
+ return err;
+
+ if (v == MTK_ENABLE || v2 == MTK_ENABLE)
+ return -EINVAL;
+
+ *res = 1;
+
+ return 0;
+}
+
+int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup)
+{
+ int err, arg;
+
+ arg = pullup ? 1 : 2;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
+ !!(arg & 2));
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup, int *res)
+{
+ int reg, err, v;
+
+ reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
+
+ err = mtk_hw_get_value(hw, desc, reg, &v);
+ if (err)
+ return err;
+
+ if (!v)
+ return -EINVAL;
+
+ *res = 1;
+
+ return 0;
+}
+
+/* Revision 1 */
+int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc)
+{
+ int err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
+ MTK_DISABLE);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *res)
+{
+ int v, err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
+ if (err)
+ return err;
+
+ if (v == MTK_ENABLE)
+ return -EINVAL;
+
+ *res = 1;
+
+ return 0;
+}
+
+int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ int *res)
+{
+ int err, v;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
+ if (err)
+ return err;
+
+ if (v == MTK_DISABLE)
+ return -EINVAL;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
+ if (err)
+ return err;
+
+ if (pullup ^ (v == MTK_PULLUP))
+ return -EINVAL;
+
+ *res = 1;
+
+ return 0;
+}
+
+/* Combo for the following pull register type:
+ * 1. PU + PD
+ * 2. PULLSEL + PULLEN
+ * 3. PUPD + R0 + R1
+ */
+int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL;
+ int pu, pd;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PU, &pf);
+ if (err)
+ goto out;
+
+ if (arg == MTK_DISABLE) {
+ pu = 0;
+ pd = 0;
+ } else if ((arg == MTK_ENABLE) && pullup) {
+ pu = 1;
+ pd = 0;
+ } else if ((arg == MTK_ENABLE) && !pullup) {
+ pu = 0;
+ pd = 1;
+ } else {
+ goto out;
+ }
+
+ mtk_hw_set_value_no_lookup(hw, desc, pu, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PD, &pf);
+ if (err)
+ goto out;
+
+ mtk_hw_set_value_no_lookup(hw, desc, pd, &pf);
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL, enable;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PULLEN, &pf);
+ if (err)
+ goto out;
+
+ if (arg == MTK_DISABLE)
+ enable = 0;
+ else if (arg == MTK_ENABLE)
+ enable = 1;
+ else
+ goto out;
+
+ mtk_hw_set_value_no_lookup(hw, desc, enable, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PULLSEL, &pf);
+ if (err)
+ goto out;
+ mtk_hw_set_value_no_lookup(hw, desc, pullup, &pf);
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL;
+ int r0, r1;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PUPD, &pf);
+ if (err)
+ goto out;
+
+ if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
+ pullup = 0;
+ r0 = 0;
+ r1 = 0;
+ } else if (arg == MTK_PUPD_SET_R1R0_01) {
+ r0 = 1;
+ r1 = 0;
+ } else if (arg == MTK_PUPD_SET_R1R0_10) {
+ r0 = 0;
+ r1 = 1;
+ } else if (arg == MTK_PUPD_SET_R1R0_11) {
+ r0 = 1;
+ r1 = 1;
+ } else
+ goto out;
+
+ /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
+ mtk_hw_set_value_no_lookup(hw, desc, !pullup, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_R0, &pf);
+ if (err)
+ goto out;
+ mtk_hw_set_value_no_lookup(hw, desc, r0, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_R1, &pf);
+ if (err)
+ goto out;
+ mtk_hw_set_value_no_lookup(hw, desc, r1, &pf);
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL;
+ int pu, pd;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PU, &pf);
+ if (err)
+ goto out;
+
+ mtk_hw_get_value_no_lookup(hw, desc, &pu, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PD, &pf);
+ if (err)
+ goto out;
+
+ mtk_hw_get_value_no_lookup(hw, desc, &pd, &pf);
+
+ if (pu == 0 && pd == 0) {
+ *pullup = 0;
+ *enable = MTK_DISABLE;
+ } else if (pu == 1 && pd == 0) {
+ *pullup = 1;
+ *enable = MTK_ENABLE;
+ } else if (pu == 0 && pd == 1) {
+ *pullup = 0;
+ *enable = MTK_ENABLE;
+ } else {
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PULLSEL, &pf);
+ if (err)
+ goto out;
+
+ mtk_hw_get_value_no_lookup(hw, desc, pullup, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PULLEN, &pf);
+ if (err)
+ goto out;
+
+ mtk_hw_get_value_no_lookup(hw, desc, enable, &pf);
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ struct mtk_pin_field pf;
+ int err = -EINVAL;
+ int r0, r1;
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_PUPD, &pf);
+ if (err)
+ goto out;
+
+ /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
+ mtk_hw_get_value_no_lookup(hw, desc, pullup, &pf);
+ *pullup = !(*pullup);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_R0, &pf);
+ if (err)
+ goto out;
+ mtk_hw_get_value_no_lookup(hw, desc, &r0, &pf);
+
+ err = mtk_hw_pin_field_lookup(hw, desc, PINCTRL_PIN_REG_R1, &pf);
+ if (err)
+ goto out;
+ mtk_hw_get_value_no_lookup(hw, desc, &r1, &pf);
+
+ if ((r1 == 0) && (r0 == 0))
+ *enable = MTK_PUPD_SET_R1R0_00;
+ else if ((r1 == 0) && (r0 == 1))
+ *enable = MTK_PUPD_SET_R1R0_01;
+ else if ((r1 == 1) && (r0 == 0))
+ *enable = MTK_PUPD_SET_R1R0_10;
+ else if ((r1 == 1) && (r0 == 1))
+ *enable = MTK_PUPD_SET_R1R0_11;
+ else
+ goto out;
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ int err;
+
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ if (!err)
+ goto out;
+
+ err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
+ if (!err)
+ goto out;
+
+ err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
+
+out:
+ return err;
+}
+
+int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ int err;
+
+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+ if (!err)
+ goto out;
+
+ err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
+ if (!err)
+ goto out;
+
+ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
+
+out:
+ return err;
+}
+
+/* Revision 0 */
+int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg)
+{
+ const struct mtk_drive_desc *tb;
+ int err = -ENOTSUPP;
+
+ tb = &mtk_drive[desc->drv_n];
+ /* 4mA when (e8, e4) = (0, 0)
+ * 8mA when (e8, e4) = (0, 1)
+ * 12mA when (e8, e4) = (1, 0)
+ * 16mA when (e8, e4) = (1, 1)
+ */
+ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
+ arg = (arg / tb->step - 1) * tb->scal;
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
+ arg & 0x1);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
+ (arg & 0x2) >> 1);
+ if (err)
+ return err;
+ }
+
+ return err;
+}
+
+int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup)
+{
+ int err, arg;
+
+ arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
+ MTK_ENABLE);
+ if (err)
+ return err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val)
+{
+ const struct mtk_drive_desc *tb;
+ int err, val1, val2;
+
+ tb = &mtk_drive[desc->drv_n];
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
+ if (err)
+ return err;
+
+ /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
+ * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
+ */
+ *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
+
+ return 0;
+}
+
+/* Revision 1 */
+int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg)
+{
+ const struct mtk_drive_desc *tb;
+ int err = -ENOTSUPP;
+
+ tb = &mtk_drive[desc->drv_n];
+
+ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
+ arg = (arg / tb->step - 1) * tb->scal;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
+ arg);
+ if (err)
+ return err;
+ }
+
+ return err;
+}
+
+int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val)
+{
+ const struct mtk_drive_desc *tb;
+ int err, val1;
+
+ tb = &mtk_drive[desc->drv_n];
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
+ if (err)
+ return err;
+
+ *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
+
+ return 0;
+}
+
+/* Revision direct value */
+int mtk_pinconf_drive_set_direct_val(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg)
+{
+ int err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
+
+ return err;
+}
+
+int mtk_pinconf_drive_get_direct_val(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val)
+{
+ int err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
+
+ return err;
+}
+
+int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 arg)
+{
+ int err;
+
+ /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
+ * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
+ * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
+ * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
+ */
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
+ if (err)
+ return 0;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
+ !!(arg & 2));
+ if (err)
+ return 0;
+
+ arg = pullup ? 0 : 1;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
+
+ /* If PUPD register is not supported for that pin, let's fallback to
+ * general bias control.
+ */
+ if (err == -ENOTSUPP) {
+ if (hw->soc->bias_set) {
+ err = hw->soc->bias_set(hw, desc, pullup);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ }
+
+ return err;
+}
+
+int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 *val)
+{
+ u32 t, t2;
+ int err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
+
+ /* If PUPD register is not supported for that pin, let's fallback to
+ * general bias control.
+ */
+ if (err == -ENOTSUPP) {
+ if (hw->soc->bias_get) {
+ err = hw->soc->bias_get(hw, desc, pullup, val);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ } else {
+ /* t == 0 supposes PULLUP for the customized PULL setup */
+ if (err)
+ return err;
+
+ if (pullup ^ !t)
+ return -EINVAL;
+ }
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
+ if (err)
+ return err;
+
+ *val = (t | t2 << 1) & 0x7;
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
new file mode 100644
index 0000000..69e9102
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -0,0 +1,316 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_COMMON_V2_H
+#define __PINCTRL_MTK_COMMON_V2_H
+
+#include <linux/gpio/driver.h>
+
+#define MTK_INPUT 0
+#define MTK_OUTPUT 1
+#define MTK_DISABLE 0
+#define MTK_ENABLE 1
+#define MTK_PULLDOWN 0
+#define MTK_PULLUP 1
+
+#define EINT_NA U16_MAX
+#define NO_EINT_SUPPORT EINT_NA
+#define EINT_NO_GPIO 9999
+
+#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
+ _s_bit, _x_bits, _sz_reg, _fixed) { \
+ .s_pin = _s_pin, \
+ .e_pin = _e_pin, \
+ .i_base = _i_base, \
+ .s_addr = _s_addr, \
+ .x_addrs = _x_addrs, \
+ .s_bit = _s_bit, \
+ .x_bits = _x_bits, \
+ .sz_reg = _sz_reg, \
+ .fixed = _fixed, \
+ }
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 0)
+
+#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 1)
+
+/* List these attributes which could be modified for the pin */
+enum {
+ PINCTRL_PIN_REG_MODE,
+ PINCTRL_PIN_REG_DIR,
+ PINCTRL_PIN_REG_DI,
+ PINCTRL_PIN_REG_DO,
+ PINCTRL_PIN_REG_SR,
+ PINCTRL_PIN_REG_SMT,
+ PINCTRL_PIN_REG_PD,
+ PINCTRL_PIN_REG_PU,
+ PINCTRL_PIN_REG_E4,
+ PINCTRL_PIN_REG_E8,
+ PINCTRL_PIN_REG_TDSEL,
+ PINCTRL_PIN_REG_RDSEL,
+ PINCTRL_PIN_REG_DRV,
+ PINCTRL_PIN_REG_PUPD,
+ PINCTRL_PIN_REG_R0,
+ PINCTRL_PIN_REG_R1,
+ PINCTRL_PIN_REG_IES,
+ PINCTRL_PIN_REG_PULLEN,
+ PINCTRL_PIN_REG_PULLSEL,
+ PINCTRL_PIN_REG_MAX,
+};
+
+/* Group the pins by the driving current */
+enum {
+ DRV_FIXED,
+ DRV_GRP0,
+ DRV_GRP1,
+ DRV_GRP2,
+ DRV_GRP3,
+ DRV_GRP4,
+ DRV_GRP_MAX,
+};
+
+static const char * const mtk_default_register_base_names[] = {
+ "base",
+};
+
+/* struct mtk_pin_field - the structure that holds the information of the field
+ * used to describe the attribute for the pin
+ * @base: the index pointing to the entry in base address list
+ * @offset: the register offset relative to the base address
+ * @mask: the mask used to filter out the field from the register
+ * @bitpos: the start bit relative to the register
+ * @next: the indication that the field would be extended to the
+ next register
+ */
+struct mtk_pin_field {
+ u8 index;
+ u32 offset;
+ u32 mask;
+ u8 bitpos;
+ u8 next;
+};
+
+/* struct mtk_pin_field_calc - the structure that holds the range providing
+ * the guide used to look up the relevant field
+ * @s_pin: the start pin within the range
+ * @e_pin: the end pin within the range
+ * @i_base: the index pointing to the entry in base address list
+ * @s_addr: the start address for the range
+ * @x_addrs: the address distance between two consecutive registers
+ * within the range
+ * @s_bit: the start bit for the first register within the range
+ * @x_bits: the bit distance between two consecutive pins within
+ * the range
+ * @sz_reg: the size of bits in a register
+ * @fixed: the consecutive pins share the same bits with the 1st
+ * pin
+ */
+struct mtk_pin_field_calc {
+ u16 s_pin;
+ u16 e_pin;
+ u8 i_base;
+ u32 s_addr;
+ u8 x_addrs;
+ u8 s_bit;
+ u8 x_bits;
+ u8 sz_reg;
+ u8 fixed;
+};
+
+/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
+ * determine which register the pin would make use of
+ * for certain pin attribute.
+ * @range: the start address for the range
+ * @nranges: the number of items in the range
+ */
+struct mtk_pin_reg_calc {
+ const struct mtk_pin_field_calc *range;
+ unsigned int nranges;
+};
+
+/**
+ * struct mtk_func_desc - the structure that providing information
+ * all the funcs for this pin
+ * @name: the name of function
+ * @muxval: the mux to the function
+ */
+struct mtk_func_desc {
+ const char *name;
+ u8 muxval;
+};
+
+/**
+ * struct mtk_eint_desc - the structure that providing information
+ * for eint data per pin
+ * @eint_m: the eint mux for this pin
+ * @eitn_n: the eint number for this pin
+ */
+struct mtk_eint_desc {
+ u16 eint_m;
+ u16 eint_n;
+};
+
+/**
+ * struct mtk_pin_desc - the structure that providing information
+ * for each pin of chips
+ * @number: unique pin number from the global pin number space
+ * @name: name for this pin
+ * @eint: the eint data for this pin
+ * @drv_n: the index with the driving group
+ * @funcs: all available functions for this pins (only used in
+ * those drivers compatible to pinctrl-mtk-common.c-like
+ * ones)
+ */
+struct mtk_pin_desc {
+ unsigned int number;
+ const char *name;
+ struct mtk_eint_desc eint;
+ u8 drv_n;
+ struct mtk_func_desc *funcs;
+};
+
+struct mtk_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned int pin;
+};
+
+struct mtk_pinctrl;
+
+/* struct mtk_pin_soc - the structure that holds SoC-specific data */
+struct mtk_pin_soc {
+ const struct mtk_pin_reg_calc *reg_cal;
+ const struct mtk_pin_desc *pins;
+ unsigned int npins;
+ const struct group_desc *grps;
+ unsigned int ngrps;
+ const struct function_desc *funcs;
+ unsigned int nfuncs;
+ const struct mtk_eint_regs *eint_regs;
+ const struct mtk_eint_hw *eint_hw;
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+ const struct pin_bi_dir_mapping *pins_dir;
+ unsigned int npins_dir;
+#endif
+
+ /* Specific parameters per SoC */
+ u8 gpio_m;
+ bool ies_present;
+ const char * const *base_names;
+ unsigned int nbase_names;
+
+ /* Specific pinconfig operations */
+ int (*bias_disable_set)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc);
+ int (*bias_disable_get)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *res);
+ int (*bias_set)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup);
+ int (*bias_get)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup, int *res);
+
+ int (*drive_set)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg);
+ int (*drive_get)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val);
+
+ int (*adv_pull_set)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 arg);
+ int (*adv_pull_get)(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 *val);
+
+ /* Specific driver data */
+ void *driver_data;
+};
+
+struct mtk_pinctrl {
+ struct pinctrl_dev *pctrl;
+ void __iomem **base;
+ u8 nbase;
+ struct device *dev;
+ struct gpio_chip chip;
+ const struct mtk_pin_soc *soc;
+ struct mtk_eint *eint;
+ struct mtk_pinctrl_group *groups;
+ const char **grp_names;
+};
+
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+struct pin_bi_dir_mapping {
+ char *pinmux_func;
+ int dir_at_suspend;
+};
+#endif
+
+void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
+
+int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+ int field, int value);
+int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+ int field, int *value);
+
+int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
+
+int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc);
+int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *res);
+int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup);
+int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ int *res);
+
+int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc);
+int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ int *res);
+int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup);
+int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ int *res);
+
+int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg);
+int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val);
+
+int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg);
+int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val);
+
+int mtk_pinconf_drive_set_direct_val(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, u32 arg);
+int mtk_pinconf_drive_get_direct_val(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val);
+
+int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 arg);
+int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 *val);
+
+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 enable);
+
+int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable);
+
+#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.c
new file mode 100644
index 0000000..f58be4b
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/gpio/consumer.h>
+#include <../../gpio/gpiolib.h>
+#include <linux/delay.h>
+#include "pinctrl-paris.h"
+//zhengzhou modify 20201110 start
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+//zhengzhou modify 20201110 end
+#define PULL_DELAY 50 /* in ms */
+#define FUN_3STATE "gpio_get_value_tristate"
+//zhengzhou modify 20201110 start start
+struct mtk_pinctrl *hw_file ;//= dev_get_drvdata(dev);
+struct device *dev_file;
+struct gpio_chip *chip_file;
+const struct mtk_pin_desc *desc_file;
+int read_gpio=0;
+#define PROC_NAME_OF_N5600 "n5600"
+//zhengzhou modify 20201110 end
+
+int gpio_get_tristate_input(unsigned int pin)
+{
+ struct gpio_device *gdev;
+ struct gpio_chip *chip = NULL;
+ struct mtk_pinctrl *hw = NULL;
+ const struct mtk_pin_desc *desc;
+ int val, val_up, val_down, ret, pullup, pullen;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+ list_for_each_entry(gdev, &gpio_devices, list) {
+
+ chip = gdev->chip;
+
+ hw = gpiochip_get_data(chip);
+
+ break;
+ }
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ if (!hw || !hw->soc) {
+ pr_notice("invalid gpio chip\n");
+ return -EINVAL;
+ }
+
+ if (pin < chip->base) {
+ pr_notice(FUN_3STATE ": please use virtual pin number\n");
+ return -EINVAL;
+ }
+
+ pin -= chip->base;
+ if (pin >= hw->soc->npins) {
+ pr_notice(FUN_3STATE ": invalid pin number: %u\n",
+ pin);
+ return -EINVAL;
+ }
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+ val = mtk_pctrl_get_pinmux(hw, pin);
+ if (val != 0) {
+ pr_notice(FUN_3STATE ":GPIO%d in mode %d, not GPIO mode\n",
+ pin, val);
+ return -EINVAL;
+ }
+
+ ret = mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ if (ret)
+ return ret;
+ if (pullen == 0 || pullen == MTK_PUPD_SET_R1R0_00) {
+ pr_notice(FUN_3STATE ":GPIO%d not pullen, skip floating test\n",
+ pin);
+ return mtk_pctrl_get_in(hw, pin);
+ }
+
+ /* set pullsel as pull-up and get input value */
+ pr_notice(FUN_3STATE ":pull up GPIO%d\n", pin);
+ mtk_pinconf_bias_set_combo(hw, desc, 1, pullen);
+ mdelay(PULL_DELAY);
+ val_up = mtk_pctrl_get_in(hw, pin),
+ pr_notice(FUN_3STATE ":GPIO%d input %d\n", pin, val_up);
+
+ /* set pullsel as pull-down and get input value */
+ pr_notice(FUN_3STATE ":pull down GPIO%d\n", pin);
+ mtk_pinconf_bias_set_combo(hw, desc, 0, pullen);
+ mdelay(PULL_DELAY);
+ val_down = mtk_pctrl_get_in(hw, pin);
+ pr_notice(FUN_3STATE ":GPIO%d input %d\n", pin, val_down);
+
+ if (val_up && val_down)
+ ret = 1;
+ else if (!val_up && !val_down)
+ ret = 0;
+ else if (val_up && !val_down)
+ ret = 2;
+ else {
+ pr_notice(FUN_3STATE ":GPIO%d pull HW is abnormal\n", pin);
+ ret = -EINVAL;
+ }
+
+ /* restore pullsel */
+ mtk_pinconf_bias_set_combo(hw, desc, pullup, pullen);
+
+ return ret;
+}
+
+static int mtk_hw_set_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio,
+ int value, int field)
+{
+ const struct mtk_pin_desc *desc;
+
+ if (gpio > hw->soc->npins)
+ return -EINVAL;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+ return mtk_hw_set_value(hw, desc, field, value);
+}
+
+#define mtk_pctrl_set_pinmux(hw, gpio, val) \
+ mtk_hw_set_value_wrap(hw, gpio, val, PINCTRL_PIN_REG_MODE)
+
+/* MTK HW use 0 as input, 1 for output
+ * This interface is for set direct register value,
+ * so don't reverse
+ */
+#define mtk_pctrl_set_direction(hw, gpio, val) \
+ mtk_hw_set_value_wrap(hw, gpio, val, PINCTRL_PIN_REG_DIR)
+
+#define mtk_pctrl_set_out(hw, gpio, val) \
+ mtk_hw_set_value_wrap(hw, gpio, val, PINCTRL_PIN_REG_DO)
+
+#define mtk_pctrl_set_smt(hw, gpio, val) \
+ mtk_hw_set_value_wrap(hw, gpio, val, PINCTRL_PIN_REG_SMT)
+
+#define mtk_pctrl_set_ies(hw, gpio, val) \
+ mtk_hw_set_value_wrap(hw, gpio, val, PINCTRL_PIN_REG_IES)
+
+static ssize_t mtk_gpio_show_pin(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+ unsigned int bufLen = PAGE_SIZE;
+ unsigned int i = 0;
+ struct mtk_pinctrl *hw = dev_get_drvdata(dev);
+ struct gpio_chip *chip;
+ pr_info("zz [pinctrl] mtk_gpio_show_pin!\n");
+ if (!hw || !buf) {
+ pr_debug("[pinctrl] Err: NULL pointer!\n");
+ return len;
+ }
+
+ chip = &hw->chip;
+
+ len += snprintf(buf+len, bufLen-len,
+ "pins base: %d, pins count: %d\n", chip->base, chip->ngpio);
+ len += snprintf(buf+len, bufLen-len,
+ "PIN: (MODE)(DIR)(DOUT)(DIN)-(DRIVE)-(SMT)(IES)-(PULL_EN)(PULL_SEL)[R1 R0]\n");
+
+ for (i = 0; i < chip->ngpio; i++) {
+ if (len > (bufLen - 96)) {
+ pr_debug("[pinctrl]err:%d exceed to max size %d\n",
+ len, (bufLen - 96));
+ break;
+ }
+ len += mtk_pctrl_show_one_pin(hw, i, buf + len, bufLen - len);
+ }
+ pr_info("zz [pinctrl] mtk_gpio_show_pin!\n");
+ return len;
+}
+
+void gpio_dump_regs_range(int start, int end)
+{
+ struct gpio_device *gdev;
+ struct mtk_pinctrl *hw;
+ struct gpio_chip *chip = NULL;
+ unsigned long flags;
+ char buf[96];
+ int i;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+ list_for_each_entry(gdev, &gpio_devices, list) {
+
+ chip = gdev->chip;
+
+ if (start < 0) {
+ start = 0;
+ end = chip->ngpio - 1;
+ }
+ if (end > chip->ngpio - 1)
+ end = chip->ngpio - 1;
+
+ pr_notice("PIN: (MODE)(DIR)(DOUT)(DIN)-(DRIVE)-(SMT)(IES)-(PULL_EN)(PULL_SEL) [R1 R0]\n");
+
+ hw = gpiochip_get_data(chip);
+ for (i = start; i < end; i++) {
+ (void)mtk_pctrl_show_one_pin(hw, i, buf, 96);
+ pr_notice("%s", buf);
+ }
+ break;
+ }
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+}
+
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+static int mtk_pctrl_get_bi_dir(struct mtk_pinctrl *hw, const char *pin_func)
+{
+ int i;
+
+ for (i = 0; i < hw->soc->npins_dir; i++) {
+ struct pin_bi_dir_mapping *pins_dir = &hw->soc->pins_dir[i];
+
+ if (strcmp(pins_dir->pinmux_func, pin_func) == 0)
+ return pins_dir->dir_at_suspend;
+ }
+ return -EINVAL;
+}
+
+static ssize_t mtk_pctrl_check_for_low_power(struct mtk_pinctrl *hw,
+ unsigned int gpio, char *buf, unsigned int bufLen)
+{
+ const struct mtk_pin_desc *desc;
+ const struct mtk_func_desc *desc_func;
+ int pinmux, pullup = -1, pullen = -1, len = 0, pin_dir = 0;
+ char pinmux_dir = '\0';
+
+ if (gpio > hw->soc->npins)
+ return -EINVAL;
+
+
+ desc = hw->soc->pins + gpio;
+ pinmux = mtk_pctrl_get_pinmux(hw, gpio);
+ if (pinmux >= hw->soc->nfuncs)
+ pinmux -= hw->soc->nfuncs;
+
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ if (pullen == MTK_PUPD_SET_R1R0_00)
+ pullen = 0;
+ else if (pullen == MTK_PUPD_SET_R1R0_01)
+ pullen = 1;
+ else if (pullen == MTK_PUPD_SET_R1R0_10)
+ pullen = 1;
+ else if (pullen == MTK_PUPD_SET_R1R0_11)
+ pullen = 1;
+ else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE)
+ pullen = 0;
+
+ desc_func = desc->funcs;
+ if (!desc_func)
+ return -EINVAL;
+
+
+ while (desc_func && desc_func->name) {
+ if (desc_func->muxval == pinmux)
+ break;
+ desc_func++;
+ }
+
+ if (desc_func->name == NULL) {
+ len += snprintf(buf + len,
+ bufLen - len,
+ "%03d: Virtual GPIO!\n",
+ gpio);
+ } else {
+ pinmux_dir = desc_func->name[0];
+ if (pinmux == 0) {
+ pin_dir = mtk_pctrl_get_direction(hw, gpio);
+ } else {
+ switch (pinmux_dir) {
+ case 'I':
+ /* I means Input */
+ pin_dir = 0;
+ break;
+ case 'O':
+ /* O means Output */
+ pin_dir = 1;
+ break;
+ case 'B':
+ /* B means Bi-Direction, confirm by Designer */
+ pin_dir =
+ mtk_pctrl_get_bi_dir(hw, desc_func->name);
+ break;
+ default:
+ pin_dir = mtk_pctrl_get_direction(hw, gpio);
+ break;
+ }
+ }
+
+ if (pin_dir == 0 && pullen == 0) {
+ len += snprintf(buf + len,
+ bufLen - len,
+ "%03d: [%d] Warning: Input+No pull\n",
+ gpio,
+ pin_dir);
+ } else if (pin_dir == 0 && pullen == 1
+ && mtk_pctrl_get_in(hw, gpio) != pullup) {
+ len += snprintf(buf + len,
+ bufLen - len,
+ "%03d: [%d] Error : Input+pull,but inconsistent with DIN\n",
+ gpio,
+ pin_dir);
+ } else if (pin_dir == 1 && pullen == 1) {
+ len += snprintf(buf + len,
+ bufLen - len,
+ "%03d: [%d] Error : Output+pull enable\n",
+ gpio,
+ pin_dir);
+ } else {
+ len += snprintf(buf + len,
+ bufLen - len,
+ "%03d: [%d] Pass\n",
+ gpio,
+ pin_dir);
+ }
+ }
+ return len;
+}
+
+void gpio_dump_low_power_error_handling(void)
+{
+ struct gpio_device *gdev;
+ struct mtk_pinctrl *hw;
+ struct gpio_chip *chip = NULL;
+ unsigned long flags;
+ char buf[96];
+ int i, end;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+ list_for_each_entry(gdev, &gpio_devices, list) {
+
+ chip = gdev->chip;
+ end = chip->ngpio - 1;
+ pr_notice("PIN: [Pinmux Dir] Low power state error or warning message\n");
+
+ hw = gpiochip_get_data(chip);
+ for (i = 0; i < end; i++) {
+ (void)mtk_pctrl_check_for_low_power(hw, i, buf, 96);
+ pr_notice("%s", buf);
+ }
+ break;
+ }
+ spin_unlock_irqrestore(&gpio_lock, flags);
+}
+#endif /* CONFIG_PINCTRL_MTK_DEBUG */
+
+void gpio_dump_regs(void)
+{
+ gpio_dump_regs_range(-1, -1);
+}
+
+static ssize_t mtk_gpio_store_pin(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int i, gpio, val, val2, pullup, pullen;
+ int vals[12];
+ char attrs[12];
+ struct mtk_pinctrl *hw = dev_get_drvdata(dev);
+ const struct mtk_pin_desc *desc;
+ struct gpio_chip *chip;
+ int r1r0_en[4] = {MTK_PUPD_SET_R1R0_00, MTK_PUPD_SET_R1R0_01,
+ MTK_PUPD_SET_R1R0_10, MTK_PUPD_SET_R1R0_11};
+ pr_info("zz [pinctrl]mtk_gpio_store_pin start \n");
+ if (!hw) {
+ pr_debug("[pinctrl] Err: NULL pointer!\n");
+ return count;
+ }
+
+ chip = &hw->chip;
+
+ if (!strncmp(buf, "mode", 4)
+ && (sscanf(buf+4, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_pinmux(hw, gpio, val);
+ } else if (!strncmp(buf, "dir", 3)
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_direction(hw, gpio, val);
+ } else if (!strncmp(buf, "out", 3)
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+//tianyan@2021.09.28 modify for gpio out start
+ mtk_pctrl_set_direction(hw, gpio, 1);
+//tianyan@2021.09.28 modify for gpio out end
+ /* mtk_gpio_set(chip, gpio, val); */
+ mtk_pctrl_set_out(hw, gpio, val);
+ } else if (!strncmp(buf, "pullen", 6)
+ && (sscanf(buf+6, "%d %d", &gpio, &val) == 2)) {
+ if (gpio < 0 || gpio > hw->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ if (pullen < MTK_PUPD_SET_R1R0_00) {
+ pullen = !!val;
+ } else {
+ if (val < 0)
+ val = 0;
+ else if (val > 3)
+ val = 3;
+ pullen = r1r0_en[val];
+ }
+ mtk_pinconf_bias_set_combo(hw, desc, pullup, pullen);
+ } else if ((!strncmp(buf, "pullsel", 7))
+ && (sscanf(buf+7, "%d %d", &gpio, &val) == 2)) {
+ if (gpio < 0 || gpio > hw->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ mtk_pinconf_bias_set_combo(hw, desc, !!val, pullen);
+ } else if ((!strncmp(buf, "ies", 3))
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_ies(hw, gpio, val);
+ } else if ((!strncmp(buf, "smt", 3))
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_smt(hw, gpio, val);
+ } else if ((!strncmp(buf, "driving", 7))
+ && (sscanf(buf+7, "%d %d", &gpio, &val) == 2)) {
+ if (gpio < 0 || gpio > hw->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ mtk_pinconf_drive_set_direct_val(hw, desc, val);
+ } else if ((!strncmp(buf, "r1r0", 4))
+ && (sscanf(buf+4, "%d %d %d", &gpio, &val, &val2) == 3)) {
+ if (gpio < 0 || gpio > hw->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ pullen = r1r0_en[(((!!val) << 1) + !!val2)];
+ mtk_pinconf_bias_set_combo(hw, desc, pullup, pullen);
+ } else if (!strncmp(buf, "set", 3)) {
+ val = sscanf(buf+3, "%d %c%c%c%c%c%c%c%c%c%c %c%c", &gpio,
+ &attrs[0], &attrs[1], &attrs[2], &attrs[3],
+ &attrs[4], &attrs[5], &attrs[6], &attrs[7],
+ &attrs[8], &attrs[9], &attrs[10], &attrs[11]);
+ for (i = 0; i < ARRAY_SIZE(attrs); i++) {
+ if ((attrs[i] >= '0') && (attrs[i] <= '9'))
+ vals[i] = attrs[i] - '0';
+ else
+ vals[i] = 0;
+ }
+ if (gpio < 0) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ /* MODE */
+ mtk_pctrl_set_pinmux(hw, gpio, vals[0]);
+ /* DIR */
+ mtk_pctrl_set_direction(hw, gpio, !!vals[1]);
+ /* DOUT */
+ if (vals[1])
+ /*mtk_gpio_set(chip, gpio, !!vals[2]); */
+ mtk_pctrl_set_out(hw, gpio, !!vals[2]);
+ /* DRIVING */
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ mtk_pinconf_drive_set_direct_val(hw, desc,
+ vals[4]*10 + vals[5]);
+ /* SMT */
+ mtk_pctrl_set_smt(hw, gpio, vals[6]);
+ /* IES */
+ mtk_pctrl_set_ies(hw, gpio, vals[7]);
+ /* PULL */
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ if (pullen < MTK_PUPD_SET_R1R0_00) {
+ mtk_pinconf_bias_set_combo(hw, desc, !!vals[9],
+ !!vals[8]);
+ } else {
+ pullen = r1r0_en[(((!!vals[10]) << 1) + !!vals[11])];
+ mtk_pinconf_bias_set_combo(hw, desc, !!vals[9],
+ pullen);
+ }
+ }
+ pr_info("zz [pinctrl]mtk_gpio_store_pin start \n");
+out:
+ return count;
+}
+
+static DEVICE_ATTR(mt_gpio, 0664, mtk_gpio_show_pin, mtk_gpio_store_pin);
+
+static struct device_attribute *gpio_attr_list[] = {
+ &dev_attr_mt_gpio,
+};
+//zhengzhou modify 20201110 start
+static ssize_t n5600_debug_write(struct file *filp, const char __user *buff, size_t len, loff_t *data)
+{
+unsigned char buf[1024] = {'\0'};
+ int copybufsize = 0;
+
+ int i, gpio, val, val2, pullup, pullen;
+ int vals[12];
+ char attrs[12];
+ pr_info("zz [pinctrl] n5600_debug_write! start\n");
+ copybufsize = (len<(sizeof(buf)%sizeof(buf[0])-1)) ? len :(sizeof(buf)%sizeof(buf[0])-1);
+ if (copy_from_user(&buf, buff, copybufsize))
+ {
+ printk("[n5600_proc] copy from user error\n");
+ return -EFAULT;
+ }
+ int r1r0_en[4] = {MTK_PUPD_SET_R1R0_00, MTK_PUPD_SET_R1R0_01,
+ MTK_PUPD_SET_R1R0_10, MTK_PUPD_SET_R1R0_11};
+
+ if (!hw_file) {
+ pr_debug("[pinctrl] Err: NULL pointer!\n");
+ return len;
+ }
+
+ chip_file = &hw_file->chip;
+ pr_info("zz [pinctrl] %s\n",buf);
+ if (!strncmp(buf, "gpio", 4)
+ && (sscanf(buf+4, "%d", &read_gpio) == 1)) {
+ pr_info("zz [pinctrl] read_gpio=%d \n",read_gpio);
+ // mtk_pctrl_set_pinmux(hw_file, gpio, val);
+ }
+
+ else if (!strncmp(buf, "mode", 4)
+ && (sscanf(buf+4, "%d %d", &gpio, &val) == 2)) {
+ pr_info("zz [pinctrl] mtk_pctrl_set_pinmux\n");
+ mtk_pctrl_set_pinmux(hw_file, gpio, val);
+ } else if (!strncmp(buf, "dir", 3)
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ pr_info("zz [pinctrl] mtk_pctrl_set_direction\n");
+ mtk_pctrl_set_direction(hw_file, gpio, val);
+ } else if (!strncmp(buf, "out", 3)
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ pr_info("zz [pinctrl] mtk_pctrl_set_out\n");
+ mtk_pctrl_set_direction(hw_file, gpio, val);
+ /* mtk_gpio_set(chip, gpio, val); */
+ mtk_pctrl_set_out(hw_file, gpio, val);
+ } else if (!strncmp(buf, "pullen", 6)
+ && (sscanf(buf+6, "%d %d", &gpio, &val) == 2)) {
+ pr_info("zz [pinctrl] pullen\n");
+ if (gpio < 0 || gpio > hw_file->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw_file, desc_file, &pullup, &pullen);
+ if (pullen < MTK_PUPD_SET_R1R0_00) {
+ pullen = !!val;
+ } else {
+ if (val < 0)
+ val = 0;
+ else if (val > 3)
+ val = 3;
+ pullen = r1r0_en[val];
+ }
+ mtk_pinconf_bias_set_combo(hw_file, desc_file, pullup, pullen);
+ } else if ((!strncmp(buf, "pullsel", 7))
+ && (sscanf(buf+7, "%d %d", &gpio, &val) == 2)) {
+ if (gpio < 0 || gpio > hw_file->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw_file, desc_file, &pullup, &pullen);
+ mtk_pinconf_bias_set_combo(hw_file, desc_file, !!val, pullen);
+ } else if ((!strncmp(buf, "ies", 3))
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_ies(hw_file, gpio, val);
+ } else if ((!strncmp(buf, "smt", 3))
+ && (sscanf(buf+3, "%d %d", &gpio, &val) == 2)) {
+ mtk_pctrl_set_smt(hw_file, gpio, val);
+ } else if ((!strncmp(buf, "driving", 7))
+ && (sscanf(buf+7, "%d %d", &gpio, &val) == 2)) {
+ if (gpio < 0 || gpio > hw_file->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ mtk_pinconf_drive_set_direct_val(hw_file, desc_file, val);
+ } else if ((!strncmp(buf, "r1r0", 4))
+ && (sscanf(buf+4, "%d %d %d", &gpio, &val, &val2) == 3)) {
+ if (gpio < 0 || gpio > hw_file->soc->npins) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ mtk_pinconf_bias_get_combo(hw_file, desc_file, &pullup, &pullen);
+ pullen = r1r0_en[(((!!val) << 1) + !!val2)];
+ mtk_pinconf_bias_set_combo(hw_file, desc_file, pullup, pullen);
+ } else if (!strncmp(buf, "set", 3)) {
+ val = sscanf(buf+3, "%d %c%c%c%c%c%c%c%c%c%c %c%c", &gpio,
+ &attrs[0], &attrs[1], &attrs[2], &attrs[3],
+ &attrs[4], &attrs[5], &attrs[6], &attrs[7],
+ &attrs[8], &attrs[9], &attrs[10], &attrs[11]);
+ for (i = 0; i < ARRAY_SIZE(attrs); i++) {
+ if ((attrs[i] >= '0') && (attrs[i] <= '9'))
+ vals[i] = attrs[i] - '0';
+ else
+ vals[i] = 0;
+ }
+ if (gpio < 0) {
+ pr_notice("invalid pin number\n");
+ goto out;
+ }
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ /* MODE */
+ mtk_pctrl_set_pinmux(hw_file, gpio, vals[0]);
+ /* DIR */
+ mtk_pctrl_set_direction(hw_file, gpio, !!vals[1]);
+ /* DOUT */
+ if (vals[1])
+ /*mtk_gpio_set(chip, gpio, !!vals[2]); */
+ mtk_pctrl_set_out(hw_file, gpio, !!vals[2]);
+ /* DRIVING */
+ desc_file = (const struct mtk_pin_desc *)&hw_file->soc->pins[gpio];
+ mtk_pinconf_drive_set_direct_val(hw_file, desc_file,
+ vals[4]*10 + vals[5]);
+ /* SMT */
+ mtk_pctrl_set_smt(hw_file, gpio, vals[6]);
+ /* IES */
+ mtk_pctrl_set_ies(hw_file, gpio, vals[7]);
+ /* PULL */
+ mtk_pinconf_bias_get_combo(hw_file, desc_file, &pullup, &pullen);
+ if (pullen < MTK_PUPD_SET_R1R0_00) {
+ mtk_pinconf_bias_set_combo(hw_file, desc_file, !!vals[9],
+ !!vals[8]);
+ } else {
+ pullen = r1r0_en[(((!!vals[10]) << 1) + !!vals[11])];
+ mtk_pinconf_bias_set_combo(hw_file, desc_file, !!vals[9],
+ pullen);
+ }
+ }
+ pr_info("zz [pinctrl] n5600_debug_write! end\n");
+ out:
+ return len;
+
+}
+static ssize_t n5600_debug_read(struct file *file, char __user *page, size_t count, loff_t *ppos)
+{
+ int ret = 0;
+//int len = 0;
+ unsigned char buf[100] = {0};
+ int len = 0;
+ unsigned int bufLen = PAGE_SIZE;
+ unsigned int i = 135;
+ // struct mtk_pinctrl *hw_file = dev_get_drvdata(dev_file);
+ // struct gpio_chip *chip_file;
+ pr_info("zz [pinctrl] n5600_debug_read! read_gpio=%d\n",read_gpio);
+ if (!hw_file) {
+ pr_debug("[pinctrl] Err: NULL pointer!\n");
+ return len;
+ }
+
+ chip_file = &hw_file->chip;
+
+ // len += snprintf(buf+len, bufLen-len,
+ // "pins base: %d, pins count: %d", chip_file->base, chip_file->ngpio);
+ // pr_info("zz11 [pinctrl] %s\n",buf);
+ // len += snprintf(buf+len, bufLen-len,
+ // "PIN: (MODE)(DIR)(DOUT)(DIN)-(DRIVE)-(SMT)(IES)-(PULL_EN)(PULL_SEL)[R1 R0]");
+ // pr_info("zz11 [pinctrl] %s\n",buf);
+// for (i = 0; i < chip_file->ngpio; i++)
+// for (i = 0; i < 2; i++)
+ // {
+ /// if (len > (bufLen - 96)) {
+ // pr_debug("[pinctrl]err:%d exceed to max size %d\n",
+ // len, (bufLen - 96));
+ // break;
+ // }
+ len += mtk_pctrl_show_one_pin(hw_file, read_gpio, buf + len, bufLen - len);
+ pr_info("zz11 [pinctrl] mtk_pctrl_show_one_pin %s\n",buf);
+ // }
+ if (copy_to_user(page, buf, len))
+ {
+ pr_info("zz11 [pinctrl] mtk_pctrl_show_one_pin %s\n",page);
+ len = - EFAULT;
+ }
+ pr_info("zz [pinctrl] n5600_debug_read! end\n");
+ return len;
+}
+static const struct file_operations n5600_debug_fops = {
+ .owner = THIS_MODULE,
+ .read = n5600_debug_read,
+ .write = n5600_debug_write,
+};
+//zhengzhou modify 20201110 end
+int mtk_gpio_create_attr(struct device *dev)
+{
+ int idx, err = 0;
+ int num = ARRAY_SIZE(gpio_attr_list);
+ //zhengzhou modify 20201110 start
+ dev_file=dev;
+ hw_file=dev_get_drvdata(dev_file);
+ chip_file = &hw_file->chip;
+ //zhengzhou modify 20201110 end
+ if (!dev)
+ return -EINVAL;
+
+ for (idx = 0; idx < num; idx++) {
+ err = device_create_file(dev, gpio_attr_list[idx]);
+ if (err)
+ break;
+ }
+ proc_create(PROC_NAME_OF_N5600, 0777, NULL, &n5600_debug_fops);//zhengzhou modify 20201110
+
+ return err;
+}
+
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.h
new file mode 100644
index 0000000..2ab7476
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2_debug.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_COMMON_V2_DEBUG_H
+#define __PINCTRL_MTK_COMMON_V2_DEBUG_H
+
+int gpio_get_tristate_input(unsigned int pin);
+int mtk_gpio_create_attr(struct device *dev);
+
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+void gpio_dump_regs(void);
+void gpio_dump_low_power_error_handling(void);
+#endif /* CONFIG_PINCTRL_MTK_DEBUG */
+
+#endif /* __PINCTRL_MTK_COMMON_V2_DEBUG_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
new file mode 100644
index 0000000..08a794d
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -0,0 +1,1805 @@
+/*
+ * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/gpio/driver.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-mtk-common.h"
+
+#define MAX_GPIO_MODE_PER_REG 5
+#define GPIO_MODE_BITS 3
+#define GPIO_MODE_PREFIX "GPIO"
+
+static const char * const mtk_gpio_functions[] = {
+ "func0", "func1", "func2", "func3",
+ "func4", "func5", "func6", "func7",
+ "func8", "func9", "func10", "func11",
+ "func12", "func13", "func14", "func15",
+};
+static const struct mtk_pin_info *mtk_pinctrl_get_gpio_array(int pin, int size,
+ const struct mtk_pin_info pArray[])
+{
+ int i = 0;
+
+ for (i = 0; i < size; i++) {
+ if (pin == pArray[i].pin)
+ return &pArray[i];
+ }
+ return NULL;
+}
+
+int mtk_pinctrl_set_gpio_value(struct mtk_pinctrl *pctl, int pin,
+ bool value, int size, const struct mtk_pin_info pin_info[])
+{
+ unsigned int reg_bit, reg_set_addr, reg_rst_addr;
+ const struct mtk_pin_info *spec_pin_info;
+ struct regmap *regmap;
+ unsigned char port_align;
+ unsigned char bit_width;
+ unsigned int mask, reg_value;
+
+ spec_pin_info = mtk_pinctrl_get_gpio_array(pin, size, pin_info);
+
+ if (spec_pin_info != NULL) {
+ port_align = pctl->devdata->port_align;
+ reg_set_addr = spec_pin_info->offset + port_align;
+ reg_rst_addr = spec_pin_info->offset + (port_align << 1);
+ reg_bit = BIT(spec_pin_info->bit);
+ regmap = pctl->regmap[spec_pin_info->ip_num];
+ reg_value = value << spec_pin_info->bit;
+ bit_width = spec_pin_info->width;
+ mask = (BIT(bit_width) - 1) << spec_pin_info->bit;
+ return regmap_update_bits(regmap,
+ spec_pin_info->offset, mask, reg_value);
+ } else {
+ return -EPERM;
+ }
+ return 0;
+}
+
+int mtk_pinctrl_update_gpio_value(struct mtk_pinctrl *pctl, int pin,
+ unsigned char value, int size, const struct mtk_pin_info pin_info[])
+{
+ unsigned int reg_update_addr;
+ unsigned int mask, reg_value;
+ const struct mtk_pin_info *spec_update_pin;
+ struct regmap *regmap;
+ unsigned char bit_width;
+
+ spec_update_pin = mtk_pinctrl_get_gpio_array(pin, size, pin_info);
+
+ if (spec_update_pin != NULL) {
+ reg_update_addr = spec_update_pin->offset;
+ regmap = pctl->regmap[spec_update_pin->ip_num];
+ reg_value = value << spec_update_pin->bit;
+ bit_width = spec_update_pin->width;
+ mask = (BIT(bit_width) - 1) << spec_update_pin->bit;
+ return regmap_update_bits(regmap,
+ reg_update_addr, mask, reg_value);
+ } else {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+int mtk_pinctrl_get_gpio_value(struct mtk_pinctrl *pctl,
+ int pin, int size, const struct mtk_pin_info pin_info[])
+{
+ unsigned int reg_value, reg_get_addr;
+ const struct mtk_pin_info *spec_pin_info;
+ struct regmap *regmap;
+ unsigned char bit_width, reg_bit;
+
+ spec_pin_info = mtk_pinctrl_get_gpio_array(pin, size, pin_info);
+
+ if (spec_pin_info != NULL) {
+ reg_get_addr = spec_pin_info->offset;
+ bit_width = spec_pin_info->width;
+ reg_bit = spec_pin_info->bit;
+ regmap = pctl->regmap[spec_pin_info->ip_num];
+ regmap_read(regmap, reg_get_addr, ®_value);
+ return ((reg_value >> reg_bit) & (BIT(bit_width) - 1));
+ } else {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * There are two base address for pull related configuration
+ * in mt8135, and different GPIO pins use different base address.
+ * When pin number greater than type1_start and less than type1_end,
+ * should use the second base address.
+ */
+static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
+ unsigned long pin)
+{
+ if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
+ return pctl->regmap2;
+ return pctl->regmap1;
+}
+
+static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
+{
+ /* Different SoC has different mask and port shift. */
+ return ((pin >> pctl->devdata->port_pin_shf) & pctl->devdata->port_mask)
+ << pctl->devdata->port_shf;
+}
+
+static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset,
+ bool input)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & pctl->devdata->port_mask);
+
+ if (pctl->devdata->spec_dir_set)
+ pctl->devdata->spec_dir_set(®_addr, offset);
+
+ if (input)
+ /* Different SoC has different alignment offset. */
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+ else
+ reg_addr = SET_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+ return 0;
+}
+
+static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
+ bit = BIT(offset & pctl->devdata->port_mask);
+
+ if (value)
+ reg_addr = SET_ADDR(reg_addr, pctl);
+ else
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+}
+
+static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
+ int value, enum pin_config_param arg)
+{
+ unsigned int reg_addr, offset;
+ unsigned int bit;
+
+ /**
+ * Due to some soc are not support ies/smt config, add this special
+ * control to handle it.
+ */
+ if (!pctl->devdata->spec_ies_smt_set &&
+ pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
+ arg == PIN_CONFIG_INPUT_ENABLE)
+ return -EINVAL;
+
+ if (!pctl->devdata->spec_ies_smt_set &&
+ pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
+ arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return -EINVAL;
+
+ /*
+ * Due to some pins are irregular, their input enable and smt
+ * control register are discontinuous, so we need this special handle.
+ */
+ if (pctl->devdata->spec_ies_smt_set) {
+ return pctl->devdata->spec_ies_smt_set(pctl,
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, value, arg);
+ }
+
+ bit = BIT(pin & 0xf);
+
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ offset = pctl->devdata->ies_offset;
+ else
+ offset = pctl->devdata->smt_offset;
+
+ if (value)
+ reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
+ else
+ reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
+ return 0;
+}
+
+int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
+ const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
+ unsigned int pin, unsigned char align, int value)
+{
+ unsigned int i, reg_addr, bit;
+
+ for (i = 0; i < info_num; i++) {
+ if (pin >= ies_smt_infos[i].start &&
+ pin <= ies_smt_infos[i].end) {
+ break;
+ }
+ }
+
+ if (i == info_num)
+ return -EINVAL;
+
+ if (value)
+ reg_addr = ies_smt_infos[i].offset + align;
+ else
+ reg_addr = ies_smt_infos[i].offset + (align << 1);
+
+ bit = BIT(ies_smt_infos[i].bit);
+ regmap_write(regmap, reg_addr, bit);
+ return 0;
+}
+
+static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
+ struct mtk_pinctrl *pctl, unsigned long pin) {
+ int i;
+
+ for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
+ const struct mtk_pin_drv_grp *pin_drv =
+ pctl->devdata->pin_drv_grp + i;
+ if (pin == pin_drv->pin)
+ return pin_drv;
+ }
+
+ return NULL;
+}
+
+static int mtk_pinctrl_set_gpio_driving(struct mtk_pinctrl *pctl,
+ int pin, unsigned char driving)
+{
+ return mtk_pinctrl_update_gpio_value(pctl, pin, driving,
+ pctl->devdata->n_pin_drv, pctl->devdata->pin_drv_grps);
+}
+
+static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
+ unsigned int pin, unsigned char driving)
+{
+ const struct mtk_pin_drv_grp *pin_drv;
+ unsigned int val;
+ unsigned int bits, mask, shift;
+ const struct mtk_drv_group_desc *drv_grp;
+
+ if (pctl->devdata->pin_drv_grps) {
+ return mtk_pinctrl_set_gpio_driving(pctl,
+ pin, driving);
+ }
+
+ if (pin >= pctl->devdata->npins)
+ return -EINVAL;
+
+ pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
+ if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
+ return -EINVAL;
+
+ drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
+ if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
+ && !(driving % drv_grp->step)) {
+ val = driving / drv_grp->step - 1;
+ bits = drv_grp->high_bit - drv_grp->low_bit + 1;
+ mask = BIT(bits) - 1;
+ shift = pin_drv->bit + drv_grp->low_bit;
+ mask <<= shift;
+ val <<= shift;
+ return regmap_update_bits(mtk_get_regmap(pctl, pin),
+ pin_drv->offset, mask, val);
+ }
+
+ return -EINVAL;
+}
+
+int mtk_pctrl_spec_pull_set_samereg(struct mtk_pinctrl *pctl,
+ struct regmap *regmap,
+ const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
+ unsigned int info_num, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ unsigned int i;
+ unsigned int reg_pupd, reg_set, reg_rst;
+ unsigned int bit_pupd, bit_r0, bit_r1;
+ const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
+ bool find = false;
+
+ for (i = 0; i < info_num; i++) {
+ if (pin == pupd_infos[i].pin) {
+ find = true;
+ break;
+ }
+ }
+
+ if (!find)
+ return -EINVAL;
+
+ spec_pupd_pin = pupd_infos + i;
+ reg_set = spec_pupd_pin->offset + align;
+ reg_rst = spec_pupd_pin->offset + (align << 1);
+
+ if (isup)
+ reg_pupd = reg_rst;
+ else
+ reg_pupd = reg_set;
+
+ if (spec_pupd_pin->ip_num != 0)
+ regmap = pctl->regmap[spec_pupd_pin->ip_num];
+ bit_pupd = BIT(spec_pupd_pin->pupd_bit);
+ regmap_write(regmap, reg_pupd, bit_pupd);
+
+ bit_r0 = BIT(spec_pupd_pin->r0_bit);
+ bit_r1 = BIT(spec_pupd_pin->r1_bit);
+
+ switch (r1r0) {
+ case MTK_PUPD_SET_R1R0_00:
+ regmap_write(regmap, reg_rst, bit_r0);
+ regmap_write(regmap, reg_rst, bit_r1);
+ break;
+ case MTK_PUPD_SET_R1R0_01:
+ regmap_write(regmap, reg_set, bit_r0);
+ regmap_write(regmap, reg_rst, bit_r1);
+ break;
+ case MTK_PUPD_SET_R1R0_10:
+ regmap_write(regmap, reg_rst, bit_r0);
+ regmap_write(regmap, reg_set, bit_r1);
+ break;
+ case MTK_PUPD_SET_R1R0_11:
+ regmap_write(regmap, reg_set, bit_r0);
+ regmap_write(regmap, reg_set, bit_r1);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
+ unsigned int pin, bool enable, bool isup, unsigned int arg)
+{
+ unsigned int bit;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
+ int ret;
+
+ /* Some pins' pull setting are very different,
+ * they have separate pull up/down bit, R0 and R1
+ * resistor bit, so we need this special handle.
+ */
+ if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+ * the parameter should be "MTK_PUPD_SET_R1R0_00".
+ */
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
+ ret = pctl->devdata->spec_pull_set(pctl,
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, isup, r1r0);
+ if (!ret)
+ return 0;
+ }
+
+ if (pctl->devdata->pin_pullen_grps ||
+ pctl->devdata->pin_pullsel_grps) {
+ mtk_pinctrl_set_gpio_value(pctl, pin, enable,
+ pctl->devdata->n_pin_pullen,
+ pctl->devdata->pin_pullen_grps);
+ mtk_pinctrl_set_gpio_value(pctl, pin, isup,
+ pctl->devdata->n_pin_pullsel,
+ pctl->devdata->pin_pullsel_grps);
+ return 0;
+ }
+
+ /* For generic pull config, default arg value should be 0 or 1. */
+ if (arg != 0 && arg != 1) {
+ dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
+ arg, pin);
+ return -EINVAL;
+ }
+
+ bit = BIT(pin & pctl->devdata->port_mask);
+ if (enable)
+ reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+ else
+ reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+
+ if (isup)
+ reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+ else
+ reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+ return 0;
+}
+
+static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
+ unsigned int pin, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ int ret = 0;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
+ ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ mtk_gpio_set(pctl->chip, pin, arg);
+ ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
+ ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = mtk_pconf_set_driving(pctl, pin, arg);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group,
+ unsigned long *config)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = pctl->groups[group].config;
+
+ return 0;
+}
+
+static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = &pctl->groups[group];
+ int i, ret;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = mtk_pconf_parse_conf(pctldev, g->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+
+ g->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops mtk_pconf_ops = {
+ .pin_config_group_get = mtk_pconf_group_get,
+ .pin_config_group_set = mtk_pconf_group_set,
+};
+
+static struct mtk_pinctrl_group *
+mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < pctl->ngroups; i++) {
+ struct mtk_pinctrl_group *grp = pctl->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
+ struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
+{
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
+ const struct mtk_desc_function *func = pin->functions;
+
+ while (func && func->name) {
+ if (func->muxval == fnum)
+ return func;
+ func++;
+ }
+
+ return NULL;
+}
+
+static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
+ u32 pin_num, u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (pin->pin.number == pin_num) {
+ const struct mtk_desc_function *func =
+ pin->functions;
+
+ while (func && func->name) {
+ if (func->muxval == fnum)
+ return true;
+ func++;
+ }
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
+ u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
+ struct pinctrl_map **map, unsigned *reserved_maps,
+ unsigned *num_maps)
+{
+ bool ret;
+
+ if (*num_maps == *reserved_maps)
+ return -ENOSPC;
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned *reserved_maps,
+ unsigned *num_maps)
+{
+ struct property *pins;
+ u32 pinfunc, pin, func;
+ int num_pins, num_funcs, maps_per_pin;
+ unsigned long *configs;
+ unsigned int num_configs;
+ bool has_config = false;
+ int i, err;
+ unsigned reserve = 0;
+ struct mtk_pinctrl_group *grp;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ pins = of_find_property(node, "pinmux", NULL);
+ if (!pins) {
+ dev_err(pctl->dev, "missing pins property in node %s .\n",
+ node->name);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
+ &num_configs);
+ if (err)
+ return err;
+
+ if (num_configs)
+ has_config = true;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ reserve = num_pins * maps_per_pin;
+
+ err = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps, num_maps, reserve);
+ if (err < 0)
+ goto exit;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "pinmux",
+ i, &pinfunc);
+ if (err)
+ goto exit;
+
+ pin = MTK_GET_PIN_NO(pinfunc);
+ func = MTK_GET_PIN_FUNC(pinfunc);
+
+ if (pin >= pctl->devdata->npins ||
+ func >= ARRAY_SIZE(mtk_gpio_functions)) {
+ dev_err(pctl->dev, "invalid pins value.\n");
+ err = -EINVAL;
+ goto exit;
+ }
+
+ grp = mtk_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n",
+ pin);
+ err = -EINVAL;
+ goto exit;
+ }
+
+ err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
+ reserved_maps, num_maps);
+ if (err < 0)
+ goto exit;
+
+ if (has_config) {
+ err = pinctrl_utils_add_map_configs(pctldev, map,
+ reserved_maps, num_maps, grp->name,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (err < 0)
+ goto exit;
+ }
+ }
+
+ err = 0;
+
+exit:
+ kfree(configs);
+ return err;
+}
+
+static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct device_node *np;
+ unsigned reserved_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ reserved_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
+ &reserved_maps, num_maps);
+ if (ret < 0) {
+ pinctrl_utils_free_map(pctldev, *map, *num_maps);
+ of_node_put(np);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned *)&pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops mtk_pctrl_ops = {
+ .dt_node_to_map = mtk_pctrl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
+ .get_groups_count = mtk_pctrl_get_groups_count,
+ .get_group_name = mtk_pctrl_get_group_name,
+ .get_group_pins = mtk_pctrl_get_group_pins,
+};
+
+static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mtk_gpio_functions);
+}
+
+static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ return mtk_gpio_functions[selector];
+}
+
+static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->grp_names;
+ *num_groups = pctl->ngroups;
+
+ return 0;
+}
+
+static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
+ unsigned long pin, unsigned long mode)
+{
+ unsigned int reg_addr;
+ unsigned char bit;
+ unsigned int val;
+ unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ if (pctl->devdata->spec_pinmux_set) {
+ pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
+ pin, mode);
+ return 0;
+ }
+
+ reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
+ + pctl->devdata->pinmux_offset;
+
+ mode &= mask;
+ bit = pin % MAX_GPIO_MODE_PER_REG;
+ mask <<= (GPIO_MODE_BITS * bit);
+ val = (mode << (GPIO_MODE_BITS * bit));
+ return regmap_update_bits(mtk_get_regmap(pctl, pin),
+ reg_addr, mask, val);
+}
+
+static const struct mtk_desc_pin *
+mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
+{
+ int i;
+ const struct mtk_desc_pin *pin;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ pin = pctl->devdata->pins + i;
+ if (pin->eint.eintnum == eint_num)
+ return pin;
+ }
+
+ return NULL;
+}
+
+static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
+{
+ bool ret;
+ const struct mtk_desc_function *desc;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = pctl->groups + group;
+
+ ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
+ if (!desc)
+ return -EINVAL;
+ mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
+ return 0;
+}
+
+static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
+ unsigned offset)
+{
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
+ const struct mtk_desc_function *func = pin->functions;
+
+ while (func && func->name) {
+ if (!strncmp(func->name, GPIO_MODE_PREFIX,
+ sizeof(GPIO_MODE_PREFIX)-1))
+ return func->muxval;
+ func++;
+ }
+ return -EINVAL;
+}
+
+static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset)
+{
+ int muxval;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ muxval = mtk_pmx_find_gpio_mode(pctl, offset);
+
+ if (muxval < 0) {
+ dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
+ return -EINVAL;
+ }
+
+ mtk_pmx_set_mode(pctldev, offset, muxval);
+ mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
+
+ return 0;
+}
+
+static const struct pinmux_ops mtk_pmx_ops = {
+ .get_functions_count = mtk_pmx_get_funcs_cnt,
+ .get_function_name = mtk_pmx_get_func_name,
+ .get_function_groups = mtk_pmx_get_func_groups,
+ .set_mux = mtk_pmx_set_mux,
+ .gpio_set_direction = mtk_pmx_gpio_set_direction,
+ .gpio_request_enable = mtk_pmx_gpio_request_enable,
+};
+
+static int mtk_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int mtk_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ mtk_gpio_set(chip, offset, value);
+ return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+
+ struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & 0xf);
+
+ if (pctl->devdata->spec_dir_set)
+ pctl->devdata->spec_dir_set(®_addr, offset);
+
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !(read_val & bit);
+}
+
+static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+ struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
+
+ reg_addr = mtk_get_port(pctl, offset) +
+ pctl->devdata->din_offset;
+
+ bit = BIT(offset & 0xf);
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !!(read_val & bit);
+}
+
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ const struct mtk_desc_pin *pin;
+ struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
+ int irq;
+
+ pin = pctl->devdata->pins + offset;
+ if (pin->eint.eintnum == NO_EINT_SUPPORT)
+ return -EINVAL;
+
+ irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
+ if (!irq)
+ return -EINVAL;
+
+ return irq;
+}
+
+static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_desc_pin *pin;
+ int ret;
+
+ pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
+
+ if (!pin) {
+ dev_err(pctl->dev, "Can not find pin\n");
+ return -EINVAL;
+ }
+
+ ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
+ if (ret) {
+ dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
+ irqd_to_hwirq(d));
+ return ret;
+ }
+
+ /* set mux to INT mode */
+ mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
+ /* set gpio direction to input */
+ mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
+ /* set input-enable */
+ mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
+
+ return 0;
+}
+
+static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_desc_pin *pin;
+
+ pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
+
+ if (!pin) {
+ dev_err(pctl->dev, "Can not find pin\n");
+ return;
+ }
+
+ gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
+}
+
+static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
+ unsigned int eint_num, unsigned int offset)
+{
+ unsigned int eint_base = 0;
+ void __iomem *reg;
+
+ if (eint_num >= pctl->devdata->ap_num)
+ eint_base = pctl->devdata->ap_num;
+
+ reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
+
+ return reg;
+}
+
+/*
+ * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
+ * @eint_num: the EINT number to setmtk_pinctrl
+ */
+static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
+ unsigned int eint_num)
+{
+ unsigned int sens;
+ unsigned int bit = BIT(eint_num % 32);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+
+ void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
+ eint_offsets->sens);
+
+ if (readl(reg) & bit)
+ sens = MT_LEVEL_SENSITIVE;
+ else
+ sens = MT_EDGE_SENSITIVE;
+
+ if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * mtk_eint_get_mask: To get the eint mask
+ * @eint_num: the EINT number to get
+ */
+static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
+ unsigned int eint_num)
+{
+ unsigned int bit = BIT(eint_num % 32);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+
+ void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
+ eint_offsets->mask);
+
+ return !!(readl(reg) & bit);
+}
+
+static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
+{
+ int start_level, curr_level;
+ unsigned int reg_offset;
+ const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
+ u32 mask = BIT(hwirq & 0x1f);
+ u32 port = (hwirq >> 5) & eint_offsets->port_mask;
+ void __iomem *reg = pctl->eint_reg_base + (port << 2);
+ const struct mtk_desc_pin *pin;
+
+ pin = mtk_find_pin_by_eint_num(pctl, hwirq);
+ curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
+ do {
+ start_level = curr_level;
+ if (start_level)
+ reg_offset = eint_offsets->pol_clr;
+ else
+ reg_offset = eint_offsets->pol_set;
+ writel(mask, reg + reg_offset);
+
+ curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
+ } while (start_level != curr_level);
+
+ return start_level;
+}
+
+static void mtk_eint_mask(struct irq_data *d)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->mask_set);
+
+ writel(mask, reg);
+}
+
+static void mtk_eint_unmask(struct irq_data *d)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->mask_clr);
+
+ writel(mask, reg);
+
+ if (pctl->eint_dual_edges[d->hwirq])
+ mtk_eint_flip_edge(pctl, d->hwirq);
+}
+
+static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
+ unsigned debounce)
+{
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
+ int eint_num, virq, eint_offset;
+ unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
+ static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
+ 128000, 256000};
+ const struct mtk_desc_pin *pin;
+ struct irq_data *d;
+
+ pin = pctl->devdata->pins + offset;
+ if (pin->eint.eintnum == NO_EINT_SUPPORT)
+ return -EINVAL;
+
+ eint_num = pin->eint.eintnum;
+ virq = irq_find_mapping(pctl->domain, eint_num);
+ eint_offset = (eint_num % 4) * 8;
+ d = irq_get_irq_data(virq);
+
+ set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
+ clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
+ if (!mtk_eint_can_en_debounce(pctl, eint_num))
+ return -ENOSYS;
+
+ dbnc = ARRAY_SIZE(debounce_time);
+ for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
+ if (debounce <= debounce_time[i]) {
+ dbnc = i;
+ break;
+ }
+ }
+
+ if (!mtk_eint_get_mask(pctl, eint_num)) {
+ mtk_eint_mask(d);
+ unmask = 1;
+ } else {
+ unmask = 0;
+ }
+
+ clr_bit = 0xff << eint_offset;
+ writel(clr_bit, pctl->eint_reg_base + clr_offset);
+
+ bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
+ eint_offset;
+ rst = EINT_DBNC_RST_BIT << eint_offset;
+ writel(rst | bit, pctl->eint_reg_base + set_offset);
+
+ /* Delay a while (more than 2T) to wait for hw debounce counter reset
+ work correctly */
+ udelay(1);
+ if (unmask == 1)
+ mtk_eint_unmask(d);
+
+ return 0;
+}
+
+static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
+ unsigned long config)
+{
+ u32 debounce;
+
+ if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
+ return -ENOTSUPP;
+
+ debounce = pinconf_to_config_argument(config);
+ return mtk_gpio_set_debounce(chip, offset, debounce);
+}
+
+#if defined(CONFIG_PINCTRL_MTK_DEBUG)
+static ssize_t mtk_gpio_show_pin(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+ int bufLen = (int)PAGE_SIZE;
+
+ len += snprintf(buf+len, bufLen-len,
+ "regmap[index]:[base register]\n");
+
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 0, 0x10005000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 1, 0x11f20000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 2, 0x11e80000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 3, 0x11e70000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 4, 0x11e90000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 5, 0x11d30000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 6, 0x11d20000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 7, 0x11c50000);
+ len += snprintf(buf+len, bufLen-len, "[%d]:[%x]\n", 8, 0x11f30000);
+
+ len += snprintf(buf+len, bufLen-len,
+ "sample cmd: echo wr index offset val > mt_gpio .\n");
+ len += snprintf(buf+len, bufLen-len,
+ "sample cmd: echo rr index offset > mt_gpio .\n");
+
+ return len;
+}
+
+static ssize_t mtk_gpio_store_pin(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ u32 index, offset, old_val, val, new_val;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(dev);
+
+ if ((strncmp(buf, "wr", 2) == 0)
+ && (sscanf(buf+2, "%d %x %x", &index, &offset, &val) == 3)) {
+ if ((index == 0) && (offset >= 0xf60)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 1) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 2) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 3) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 4) && (offset >= 0xb0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 5) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 6) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 7) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 8) && (offset >= 0xe0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ }
+
+ regmap_read(pctl->regmap[index], offset, &old_val);
+ regmap_write(pctl->regmap[index], offset, val);
+ regmap_read(pctl->regmap[index], offset, &new_val);
+ pr_info("old_val(0x%x)->new_val(0x%x).\n", old_val, new_val);
+ } else if ((strncmp(buf, "rr", 2) == 0)
+ && (sscanf(buf+2, "%d %x", &index, &offset) == 2)) {
+ if ((index == 0) && (offset >= 0xf60)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 1) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 2) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 3) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 4) && (offset >= 0xb0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 5) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 6) && (offset >= 0xd0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 7) && (offset >= 0xc0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ } else if ((index == 8) && (offset >= 0xe0)) {
+ pr_info("index(%d),offset(0x%x) invalid.\n",
+ index, offset);
+ goto err_return;
+ }
+
+ regmap_read(pctl->regmap[index], offset, &val);
+ pr_info("regmap[%d]+offset(%x)=0x%x.\n", index, offset, val);
+ } else {
+
+ }
+
+ return (ssize_t)count;
+
+err_return:
+
+ return (ssize_t)0;
+}
+
+static DEVICE_ATTR(mt_gpio, 0664, mtk_gpio_show_pin, mtk_gpio_store_pin);
+
+static struct device_attribute *gpio_attr_list[] = {
+ &dev_attr_mt_gpio,
+};
+
+static int mtk_gpio_create_attr(struct device *dev)
+{
+ int idx, err = 0;
+ int num = (int)ARRAY_SIZE(gpio_attr_list);
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ for (idx = 0; idx < num; idx++) {
+ err = device_create_file(dev, gpio_attr_list[idx]);
+ if (err > 0)
+ break;
+ }
+
+ return err;
+}
+#endif
+
+static const struct gpio_chip mtk_gpio_chip = {
+ .owner = THIS_MODULE,
+ .request = gpiochip_generic_request,
+ .free = gpiochip_generic_free,
+ .get_direction = mtk_gpio_get_direction,
+ .direction_input = mtk_gpio_direction_input,
+ .direction_output = mtk_gpio_direction_output,
+ .get = mtk_gpio_get,
+ .set = mtk_gpio_set,
+ .to_irq = mtk_gpio_to_irq,
+ .set_config = mtk_gpio_set_config,
+ .of_gpio_n_cells = 2,
+};
+
+static int mtk_eint_set_type(struct irq_data *d,
+ unsigned int type)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg;
+
+ if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
+ ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
+ dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
+ d->irq, d->hwirq, type);
+ return -EINVAL;
+ }
+
+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+ pctl->eint_dual_edges[d->hwirq] = 1;
+ else
+ pctl->eint_dual_edges[d->hwirq] = 0;
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
+ reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->pol_clr);
+ writel(mask, reg);
+ } else {
+ reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->pol_set);
+ writel(mask, reg);
+ }
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+ reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->sens_clr);
+ writel(mask, reg);
+ } else {
+ reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->sens_set);
+ writel(mask, reg);
+ }
+
+ if (pctl->eint_dual_edges[d->hwirq])
+ mtk_eint_flip_edge(pctl, d->hwirq);
+
+ return 0;
+}
+
+static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ int shift = d->hwirq & 0x1f;
+ int reg = d->hwirq >> 5;
+
+ if (on)
+ pctl->wake_mask[reg] |= BIT(shift);
+ else
+ pctl->wake_mask[reg] &= ~BIT(shift);
+
+ return 0;
+}
+
+static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
+ void __iomem *eint_reg_base, u32 *buf)
+{
+ int port;
+ void __iomem *reg;
+
+ for (port = 0; port < chip->ports; port++) {
+ reg = eint_reg_base + (port << 2);
+ writel_relaxed(~buf[port], reg + chip->mask_set);
+ writel_relaxed(buf[port], reg + chip->mask_clr);
+ }
+}
+
+static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
+ void __iomem *eint_reg_base, u32 *buf)
+{
+ int port;
+ void __iomem *reg;
+
+ for (port = 0; port < chip->ports; port++) {
+ reg = eint_reg_base + chip->mask + (port << 2);
+ buf[port] = ~readl_relaxed(reg);
+ /* Mask is 0 when irq is enabled, and 1 when disabled. */
+ }
+}
+
+static int mtk_eint_suspend(struct device *device)
+{
+ void __iomem *reg;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(device);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+
+ reg = pctl->eint_reg_base;
+ mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
+ mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
+
+ return 0;
+}
+
+static int mtk_eint_resume(struct device *device)
+{
+ struct mtk_pinctrl *pctl = dev_get_drvdata(device);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+
+ mtk_eint_chip_write_mask(eint_offsets,
+ pctl->eint_reg_base, pctl->cur_mask);
+
+ return 0;
+}
+
+const struct dev_pm_ops mtk_eint_pm_ops = {
+ .suspend_noirq = mtk_eint_suspend,
+ .resume_noirq = mtk_eint_resume,
+};
+
+static void mtk_eint_ack(struct irq_data *d)
+{
+ struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ u32 mask = BIT(d->hwirq & 0x1f);
+ void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
+ eint_offsets->ack);
+
+ writel(mask, reg);
+}
+
+static struct irq_chip mtk_pinctrl_irq_chip = {
+ .name = "mt-eint",
+ .irq_disable = mtk_eint_mask,
+ .irq_mask = mtk_eint_mask,
+ .irq_unmask = mtk_eint_unmask,
+ .irq_ack = mtk_eint_ack,
+ .irq_set_type = mtk_eint_set_type,
+ .irq_set_wake = mtk_eint_irq_set_wake,
+ .irq_request_resources = mtk_pinctrl_irq_request_resources,
+ .irq_release_resources = mtk_pinctrl_irq_release_resources,
+};
+
+static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
+{
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
+ unsigned int i;
+
+ for (i = 0; i < pctl->devdata->ap_num; i += 32) {
+ writel(0xffffffff, reg);
+ reg += 4;
+ }
+ return 0;
+}
+
+static inline void
+mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
+{
+ unsigned int rst, ctrl_offset;
+ unsigned int bit, dbnc;
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+
+ ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
+ dbnc = readl(pctl->eint_reg_base + ctrl_offset);
+ bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
+ if ((bit & dbnc) > 0) {
+ ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
+ rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
+ writel(rst, pctl->eint_reg_base + ctrl_offset);
+ }
+}
+
+static void mtk_eint_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
+ unsigned int status, eint_num;
+ int offset, index, virq;
+ const struct mtk_eint_offsets *eint_offsets =
+ &pctl->devdata->eint_offsets;
+ void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
+ int dual_edges, start_level, curr_level;
+ const struct mtk_desc_pin *pin;
+
+ chained_irq_enter(chip, desc);
+ for (eint_num = 0;
+ eint_num < pctl->devdata->ap_num;
+ eint_num += 32, reg += 4) {
+ status = readl(reg);
+ while (status) {
+ offset = __ffs(status);
+ index = eint_num + offset;
+ virq = irq_find_mapping(pctl->domain, index);
+ status &= ~BIT(offset);
+
+ dual_edges = pctl->eint_dual_edges[index];
+ if (dual_edges) {
+ /* Clear soft-irq in case we raised it
+ last time */
+ writel(BIT(offset), reg - eint_offsets->stat +
+ eint_offsets->soft_clr);
+
+ pin = mtk_find_pin_by_eint_num(pctl, index);
+ start_level = mtk_gpio_get(pctl->chip,
+ pin->pin.number);
+ }
+
+ generic_handle_irq(virq);
+
+ if (dual_edges) {
+ curr_level = mtk_eint_flip_edge(pctl, index);
+
+ /* If level changed, we might lost one edge
+ interrupt, raised it through soft-irq */
+ if (start_level != curr_level)
+ writel(BIT(offset), reg -
+ eint_offsets->stat +
+ eint_offsets->soft_set);
+ }
+
+ if (index < pctl->devdata->db_cnt)
+ mtk_eint_debounce_process(pctl , index);
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int mtk_pctrl_build_state(struct platform_device *pdev)
+{
+ struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
+ int i;
+
+ pctl->ngroups = pctl->devdata->npins;
+
+ /* Allocate groups */
+ pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
+ sizeof(*pctl->groups), GFP_KERNEL);
+ if (!pctl->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
+ sizeof(*pctl->grp_names), GFP_KERNEL);
+ if (!pctl->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+ struct mtk_pinctrl_group *group = pctl->groups + i;
+
+ group->name = pin->pin.name;
+ group->pin = pin->pin.number;
+
+ pctl->grp_names[i] = pin->pin.name;
+ }
+
+ return 0;
+}
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data,
+ struct regmap *regmap)
+{
+ struct pinctrl_pin_desc *pins;
+ struct mtk_pinctrl *pctl;
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct property *prop;
+ struct resource *res;
+ int i, ret, irq, ports_buf;
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pctl);
+
+ prop = of_find_property(np, "pins-are-numbered", NULL);
+ if (!prop) {
+ dev_err(&pdev->dev, "only support pins-are-numbered format\n");
+ return -EINVAL;
+ }
+
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
+ if (node) {
+ pctl->regmap1 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap1))
+ return PTR_ERR(pctl->regmap1);
+ } else if (regmap) {
+ pctl->regmap1 = regmap;
+ } else {
+ dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
+ return -EINVAL;
+ }
+
+ /* Only 8135 has two base addr, other SoCs have only one. */
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
+ if (node) {
+ pctl->regmap2 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap2))
+ return PTR_ERR(pctl->regmap2);
+ }
+
+ if (data->regmap_num > 2) {
+ for (i = 0; i <= data->regmap_num; i++) {
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", i);
+ if (node) {
+ pctl->regmap[i] = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap[i]))
+ return PTR_ERR(pctl->regmap[i]);
+ }
+ }
+ }
+
+ pctl->devdata = data;
+ ret = mtk_pctrl_build_state(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "build state failed: %d\n", ret);
+ return -EINVAL;
+ }
+
+ pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++)
+ pins[i] = pctl->devdata->pins[i].pin;
+
+ pctl->pctl_desc.name = dev_name(&pdev->dev);
+ pctl->pctl_desc.owner = THIS_MODULE;
+ pctl->pctl_desc.pins = pins;
+ pctl->pctl_desc.npins = pctl->devdata->npins;
+ pctl->pctl_desc.confops = &mtk_pconf_ops;
+ pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
+ pctl->pctl_desc.pmxops = &mtk_pmx_ops;
+ pctl->dev = &pdev->dev;
+
+ pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
+ pctl);
+ if (IS_ERR(pctl->pctl_dev)) {
+ dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+ return PTR_ERR(pctl->pctl_dev);
+ }
+
+ pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
+ if (!pctl->chip)
+ return -ENOMEM;
+
+ *pctl->chip = mtk_gpio_chip;
+ pctl->chip->ngpio = pctl->devdata->npins;
+ pctl->chip->label = dev_name(&pdev->dev);
+ pctl->chip->parent = &pdev->dev;
+ pctl->chip->base = -1;
+
+ ret = gpiochip_add_data(pctl->chip, pctl);
+ if (ret)
+ return -EINVAL;
+
+ /* Register the GPIO to pin mappings. */
+ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
+ 0, 0, pctl->devdata->npins);
+ if (ret) {
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+#if defined(CONFIG_PINCTRL_MTK_DEBUG)
+ ret = mtk_gpio_create_attr(&pdev->dev);
+ if (ret < 0)
+ pr_warn("mtk_gpio create attribute error\n");
+#endif
+
+ if (!of_property_read_bool(np, "interrupt-controller"))
+ return 0;
+
+ /* Get EINT register base from dts. */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+ pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pctl->eint_reg_base)) {
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+ ports_buf = pctl->devdata->eint_offsets.ports;
+ pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
+ sizeof(*pctl->wake_mask), GFP_KERNEL);
+ if (!pctl->wake_mask) {
+ ret = -ENOMEM;
+ goto chip_error;
+ }
+
+ pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
+ sizeof(*pctl->cur_mask), GFP_KERNEL);
+ if (!pctl->cur_mask) {
+ ret = -ENOMEM;
+ goto chip_error;
+ }
+
+ pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
+ sizeof(int), GFP_KERNEL);
+ if (!pctl->eint_dual_edges) {
+ ret = -ENOMEM;
+ goto chip_error;
+ }
+
+ irq = irq_of_parse_and_map(np, 0);
+ if (!irq) {
+ dev_err(&pdev->dev, "couldn't parse and map irq\n");
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+ pctl->domain = irq_domain_add_linear(np,
+ pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
+ if (!pctl->domain) {
+ dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
+ ret = -ENOMEM;
+ goto chip_error;
+ }
+
+ mtk_eint_init(pctl);
+ for (i = 0; i < pctl->devdata->ap_num; i++) {
+ int virq = irq_create_mapping(pctl->domain, i);
+
+ irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(virq, pctl);
+ }
+
+ irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
+ return 0;
+
+chip_error:
+ gpiochip_remove(pctl->chip);
+ return ret;
+}
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
new file mode 100644
index 0000000..456ba3c
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_COMMON_H
+#define __PINCTRL_MTK_COMMON_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#define NO_EINT_SUPPORT 255
+#define MT_EDGE_SENSITIVE 0
+#define MT_LEVEL_SENSITIVE 1
+#define EINT_DBNC_SET_DBNC_BITS 4
+#define EINT_DBNC_RST_BIT (0x1 << 1)
+#define EINT_DBNC_SET_EN (0x1 << 0)
+#define MAX_IP_BASE 10
+#define MTK_PINCTRL_NOT_SUPPORT (0xffff)
+
+struct mtk_desc_function {
+ const char *name;
+ unsigned char muxval;
+};
+
+struct mtk_desc_eint {
+ unsigned char eintmux;
+ unsigned char eintnum;
+};
+
+struct mtk_desc_pin {
+ struct pinctrl_pin_desc pin;
+ const struct mtk_desc_eint eint;
+ const struct mtk_desc_function *functions;
+};
+
+#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \
+ { \
+ .pin = _pin, \
+ .eint = _eint, \
+ .functions = (struct mtk_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \
+ { \
+ .eintmux = _eintmux, \
+ .eintnum = _eintnum, \
+ }
+
+#define MTK_FUNCTION(_val, _name) \
+ { \
+ .muxval = _val, \
+ .name = _name, \
+ }
+
+#define SET_ADDR(x, y) (x + (y->devdata->port_align))
+#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1))
+
+struct mtk_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned pin;
+};
+
+/**
+ * struct mtk_drv_group_desc - Provide driving group data.
+ * @max_drv: The maximum current of this group.
+ * @min_drv: The minimum current of this group.
+ * @low_bit: The lowest bit of this group.
+ * @high_bit: The highest bit of this group.
+ * @step: The step current of this group.
+ */
+struct mtk_drv_group_desc {
+ unsigned char min_drv;
+ unsigned char max_drv;
+ unsigned char low_bit;
+ unsigned char high_bit;
+ unsigned char step;
+};
+
+#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \
+ { \
+ .min_drv = _min, \
+ .max_drv = _max, \
+ .low_bit = _low, \
+ .high_bit = _high, \
+ .step = _step, \
+ }
+
+/**
+ * struct mtk_pin_drv_grp - Provide each pin driving info.
+ * @pin: The pin number.
+ * @offset: The offset of driving register for this pin.
+ * @bit: The bit of driving register for this pin.
+ * @grp: The group for this pin belongs to.
+ */
+struct mtk_pin_drv_grp {
+ unsigned short pin;
+ unsigned short offset;
+ unsigned char bit;
+ unsigned char grp;
+};
+
+#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \
+ { \
+ .pin = _pin, \
+ .offset = _offset, \
+ .bit = _bit, \
+ .grp = _grp, \
+ }
+
+/**
+ * struct mtk_pin_spec_pupd_set_samereg
+ * - For special pins' pull up/down setting which resides in same register
+ * @pin: The pin number.
+ * @offset: The offset of special pull up/down setting register.
+ * @pupd_bit: The pull up/down bit in this register.
+ * @r0_bit: The r0 bit of pull resistor.
+ * @r1_bit: The r1 bit of pull resistor.
+ */
+struct mtk_pin_spec_pupd_set_samereg {
+ unsigned short pin;
+ unsigned short offset;
+ unsigned char pupd_bit;
+ unsigned char r1_bit;
+ unsigned char r0_bit;
+ unsigned char ip_num;
+};
+
+#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0, _ip_num) \
+ { \
+ .pin = _pin, \
+ .offset = _offset, \
+ .pupd_bit = _pupd, \
+ .r1_bit = _r1, \
+ .r0_bit = _r0, \
+ .ip_num = _ip_num,\
+ }
+
+/**
+ * struct mtk_pin_ies_set - For special pins' ies and smt setting.
+ * @start: The start pin number of those special pins.
+ * @end: The end pin number of those special pins.
+ * @offset: The offset of special setting register.
+ * @bit: The bit of special setting register.
+ */
+struct mtk_pin_ies_smt_set {
+ unsigned short start;
+ unsigned short end;
+ unsigned short offset;
+ unsigned char bit;
+};
+
+#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \
+ { \
+ .start = _start, \
+ .end = _end, \
+ .bit = _bit, \
+ .offset = _offset, \
+ }
+
+struct mtk_eint_offsets {
+ const char *name;
+ unsigned int stat;
+ unsigned int ack;
+ unsigned int mask;
+ unsigned int mask_set;
+ unsigned int mask_clr;
+ unsigned int sens;
+ unsigned int sens_set;
+ unsigned int sens_clr;
+ unsigned int soft;
+ unsigned int soft_set;
+ unsigned int soft_clr;
+ unsigned int pol;
+ unsigned int pol_set;
+ unsigned int pol_clr;
+ unsigned int dom_en;
+ unsigned int dbnc_ctrl;
+ unsigned int dbnc_set;
+ unsigned int dbnc_clr;
+ u8 port_mask;
+ u8 ports;
+};
+
+/**
+ * struct mt_pin_info - For all pins' setting
+ * @pin: The pin number
+ * @offset: The address offset of pin setting register
+ * @bit: The bit shift at setting register
+ * @width: The bit width at setting register
+ * @ip_num: The IOConfiguration base index
+ */
+struct mtk_pin_info {
+ unsigned int pin;
+ unsigned int offset;
+ unsigned char bit;
+ unsigned char width;
+ unsigned char ip_num;
+};
+
+#define MTK_PIN_INFO(_pin, _offset, _bit, _width, _ip_num) \
+ { \
+ .pin = _pin, \
+ .offset = _offset, \
+ .bit = _bit, \
+ .width = _width, \
+ .ip_num = _ip_num,\
+ }
+
+struct mtk_pinctrl {
+ struct regmap *regmap1;
+ struct regmap *regmap2;
+ struct regmap *regmap[MAX_IP_BASE];
+ struct pinctrl_desc pctl_desc;
+ struct device *dev;
+ struct gpio_chip *chip;
+ struct mtk_pinctrl_group *groups;
+ unsigned int ngroups;
+ const char **grp_names;
+ struct pinctrl_dev *pctl_dev;
+ const struct mtk_pinctrl_devdata *devdata;
+ void __iomem *eint_reg_base;
+ struct irq_domain *domain;
+ int *eint_dual_edges;
+ u32 *wake_mask;
+ u32 *cur_mask;
+};
+
+/**
+ * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
+ * @pins: An array describing all pins the pin controller affects.
+ * @npins: The number of entries in @pins.
+ *
+ * @grp_desc: The driving group info.
+ * @pin_drv_grp: The driving group for all pins.
+ * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
+ * these pins' pull setting are very different, they have separate pull
+ * up/down bit, R0 and R1 resistor bit, so they need special pull setting.
+ * If special setting is success, this should return 0, otherwise it should
+ * return non-zero value.
+ * @spec_ies_smt_set: Some pins are irregular, their input enable and smt
+ * control register are discontinuous, but they are mapping together. That
+ * means when user set smt, input enable is set at the same time. So they
+ * also need special control. If special control is success, this should
+ * return 0, otherwise return non-zero value.
+ * @spec_pinmux_set: In some cases, there are two pinmux functions share
+ * the same value in the same segment of pinmux control register. If user
+ * want to use one of the two functions, they need an extra bit setting to
+ * select the right one.
+ * @spec_dir_set: In very few SoCs, direction control registers are not
+ * arranged continuously, they may be cut to parts. So they need special
+ * dir setting.
+
+ * @dir_offset: The direction register offset.
+ * @pullen_offset: The pull-up/pull-down enable register offset.
+ * @pinmux_offset: The pinmux register offset.
+ *
+ * @type1_start: Some chips have two base addresses for pull select register,
+ * that means some pins use the first address and others use the second. This
+ * member record the start of pin number to use the second address.
+ * @type1_end: The end of pin number to use the second address.
+ *
+ * @port_shf: The shift between two registers.
+ * @port_mask: The mask of register.
+ * @port_align: Provide clear register and set register step.
+ */
+struct mtk_pinctrl_devdata {
+ const struct mtk_desc_pin *pins;
+ unsigned int npins;
+ const struct mtk_drv_group_desc *grp_desc;
+ unsigned int n_grp_cls;
+ const struct mtk_pin_drv_grp *pin_drv_grp;
+ unsigned int n_pin_drv_grps;
+ const struct mtk_pin_info *pin_drv_grps;
+ unsigned int n_pin_drv;
+ const struct mtk_pin_info *pin_mode_grps;
+ unsigned int n_pin_mode;
+ const struct mtk_pin_info *pin_ies_grps;
+ unsigned int n_pin_ies;
+ const struct mtk_pin_info *pin_smt_grps;
+ unsigned int n_pin_smt;
+ const struct mtk_pin_info *pin_dout_grps;
+ unsigned int n_pin_dout;
+ const struct mtk_pin_info *pin_din_grps;
+ unsigned int n_pin_din;
+ const struct mtk_pin_info *pin_dir_grps;
+ unsigned int n_pin_dir;
+ const struct mtk_pin_info *pin_pullen_grps;
+ unsigned int n_pin_pullen;
+ const struct mtk_pin_info *pin_pullsel_grps;
+ unsigned int n_pin_pullsel;
+ const struct mtk_pin_info *pin_pupd_r1r0_grps;
+ unsigned int n_pin_pupd_r1r0;
+ int (*spec_pull_set)(struct mtk_pinctrl *pctl,
+ struct regmap *reg, unsigned int pin,
+ unsigned char align, bool isup, unsigned int arg);
+ int (*spec_ies_smt_set)(struct mtk_pinctrl *pctl,
+ struct regmap *reg, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg);
+ void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
+ unsigned int mode);
+ void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
+ unsigned int dir_offset;
+ unsigned int ies_offset;
+ unsigned int smt_offset;
+ unsigned int pullen_offset;
+ unsigned int pullsel_offset;
+ unsigned int drv_offset;
+ unsigned int dout_offset;
+ unsigned int din_offset;
+ unsigned int pinmux_offset;
+ unsigned short type1_start;
+ unsigned short type1_end;
+ unsigned char port_shf;
+ unsigned char port_mask;
+ unsigned char port_align;
+ unsigned char port_pin_shf;
+ unsigned int regmap_num;
+ struct mtk_eint_offsets eint_offsets;
+ unsigned int ap_num;
+ unsigned int db_cnt;
+};
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data,
+ struct regmap *regmap);
+
+int mtk_pctrl_spec_pull_set_samereg(struct mtk_pinctrl *pctl,
+ struct regmap *regmap,
+ const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
+ unsigned int info_num, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0);
+
+int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
+ const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
+ unsigned int pin, unsigned char align, int value);
+
+int mtk_pinctrl_get_gpio_value(struct mtk_pinctrl *pctl,
+ int pin, int size, const struct mtk_pin_info pin_info[]);
+
+int mtk_pinctrl_update_gpio_value(struct mtk_pinctrl *pctl, int pin,
+ unsigned char value, int size, const struct mtk_pin_info pin_info[]);
+
+int mtk_pinctrl_set_gpio_value(struct mtk_pinctrl *pctl, int pin,
+ bool value, int size, const struct mtk_pin_info pin_info[]);
+extern const struct dev_pm_ops mtk_eint_pm_ops;
+
+#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
new file mode 100644
index 0000000..1035df4
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
@@ -0,0 +1,2335 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT2701_H
+#define __PINCTRL_MTK_MT2701_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt2701[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 148),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 149),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "PWRAP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 150),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "PWRAP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 151),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 152),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 153),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
+ MTK_FUNCTION(5, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 154),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(7, "DBG_MON_A[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "SPI1_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 155),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI1_CS"),
+ MTK_FUNCTION(4, "KCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_B[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "SPI1_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 156),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "SPI1_MI"),
+ MTK_FUNCTION(2, "SPI1_MO"),
+ MTK_FUNCTION(4, "KCOL1"),
+ MTK_FUNCTION(7, "DBG_MON_B[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "SPI1_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 157),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "SPI1_MO"),
+ MTK_FUNCTION(2, "SPI1_MI"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "KCOL2"),
+ MTK_FUNCTION(7, "DBG_MON_B[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "RTC32K_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 158),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "WATCHDOG"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 159),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "SRCLKENA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 160),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "SRCLKENAI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 161),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "URXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 162),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "UTXD2"),
+ MTK_FUNCTION(5, "SRCCLKENAI2"),
+ MTK_FUNCTION(7, "DBG_MON_B[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "UTXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 163),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "URXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "I2S5_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 164),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "I2S5_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "I2S5_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 165),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "I2S5_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(4, "ANT_SEL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "PCM_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 166),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "PCM_CLK0"),
+ MTK_FUNCTION(2, "MRG_CLK"),
+ MTK_FUNCTION(4, "MM_TEST_CK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+ MTK_FUNCTION(7, "DBG_MON_A[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "PCM_SYNC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 167),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(2, "MRG_SYNC"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "PCM_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "PCM_RX"),
+ MTK_FUNCTION(2, "MRG_RX"),
+ MTK_FUNCTION(3, "MRG_TX"),
+ MTK_FUNCTION(4, "PCM_TX"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "WCN_PCM_RX"),
+ MTK_FUNCTION(7, "DBG_MON_A[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "PCM_TX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "PCM_TX"),
+ MTK_FUNCTION(2, "MRG_TX"),
+ MTK_FUNCTION(3, "MRG_RX"),
+ MTK_FUNCTION(4, "PCM_RX"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "WCN_PCM_TX"),
+ MTK_FUNCTION(7, "DBG_MON_A[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "EINT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "UCTS0"),
+ /* MT7623 take function 2 as PCIE0_PERST_N */
+ MTK_FUNCTION(2, "PCIE0_PERST_N"),
+ MTK_FUNCTION(3, "KCOL3"),
+ MTK_FUNCTION(4, "CONN_DSP_JDO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[30]"),
+ MTK_FUNCTION(10, "PCIE0_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "EINT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "URTS0"),
+ /* MT7623 take function 2 as PCIE1_PERST_N */
+ MTK_FUNCTION(2, "PCIE1_PERST_N"),
+ MTK_FUNCTION(3, "KCOL2"),
+ MTK_FUNCTION(4, "CONN_MCU_TDO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[29]"),
+ MTK_FUNCTION(10, "PCIE1_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "EINT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "UCTS1"),
+ /* MT7623 take function 2 as PCIE2_PERST_N */
+ MTK_FUNCTION(2, "PCIE2_PERST_N"),
+ MTK_FUNCTION(3, "KCOL1"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[28]"),
+ MTK_FUNCTION(10, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "EINT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION(3, "KCOL0"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "EINT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1"),
+ MTK_FUNCTION(3, "KROW3"),
+ MTK_FUNCTION(4, "CONN_MCU_TCK0"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_JCKC"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "EINT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "IDDIG_P1"),
+ MTK_FUNCTION(3, "KROW2"),
+ MTK_FUNCTION(4, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "EINT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "DRV_VBUS"),
+ MTK_FUNCTION(3, "KROW1"),
+ MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "EINT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ MTK_FUNCTION(3, "KROW0"),
+ MTK_FUNCTION(4, "CONN_MCU_TMS"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
+ /* MT7623 take function 6 as PCIE2_PERST_N */
+ MTK_FUNCTION(6, "PCIE2_PERST_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[23]"),
+ MTK_FUNCTION(14, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "I2S5_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 12),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "I2S5_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(4, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "I2S5_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 13),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "I2S5_MCLK"),
+ MTK_FUNCTION(4, "ANT_SEL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "I2S5_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "I2S5_DATA"),
+ MTK_FUNCTION(2, "I2S5_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "I2S1_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "I2S1_DATA"),
+ MTK_FUNCTION(2, "I2S1_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "IMG_TEST_CK"),
+ MTK_FUNCTION(5, "G1_RXD0"),
+ MTK_FUNCTION(6, "WCN_PCM_TX"),
+ MTK_FUNCTION(7, "DBG_MON_B[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "I2S1_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "I2S1_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "VDEC_TEST_CK"),
+ MTK_FUNCTION(5, "G1_RXD1"),
+ MTK_FUNCTION(6, "WCN_PCM_RX"),
+ MTK_FUNCTION(7, "DBG_MON_B[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "I2S1_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(5, "G1_RXD2"),
+ MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+ MTK_FUNCTION(7, "DBG_MON_B[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "I2S1_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(5, "G1_RXD3"),
+ MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_B[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "I2S1_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "I2S1_MCLK"),
+ MTK_FUNCTION(5, "G1_RXDV"),
+ MTK_FUNCTION(7, "DBG_MON_B[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "I2S2_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(2, "I2S2_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "DMIC_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "JTMS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "CONN_MCU_TMS"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
+ MTK_FUNCTION(4, "DFD_TMS_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "JTCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 22),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "CONN_MCU_TCK1"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
+ MTK_FUNCTION(4, "DFD_TCK_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "JTDI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "CONN_MCU_TDI"),
+ MTK_FUNCTION(4, "DFD_TDI_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "JTDO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "CONN_MCU_TDO"),
+ MTK_FUNCTION(4, "DFD_TDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "NCLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION(2, "EXT_XCS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "NCEB1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION(2, "IDDIG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "NCEB0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "IR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "IR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "NREB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION(2, "IDDIG_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "NRNB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "I2S0_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "I2S0_DATA"),
+ MTK_FUNCTION(2, "I2S0_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(6, "WCN_I2S_DO"),
+ MTK_FUNCTION(7, "DBG_MON_B[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "I2S2_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "I2S2_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(4, "DMIC_SCK1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "I2S2_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "I2S2_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "DMIC_SCK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "I2S2_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(4, "DMIC_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "SPI0_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI0_CS"),
+ MTK_FUNCTION(3, "SPDIF"),
+ MTK_FUNCTION(4, "ADC_CK"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_A[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "SPI0_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI0_CK"),
+ MTK_FUNCTION(3, "SPDIF_IN1"),
+ MTK_FUNCTION(4, "ADC_DAT_IN"),
+ MTK_FUNCTION(7, "DBG_MON_A[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "SPI0_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI0_MI"),
+ MTK_FUNCTION(2, "SPI0_MO"),
+ MTK_FUNCTION(3, "MSDC1_WP"),
+ MTK_FUNCTION(4, "ADC_WS"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(7, "DBG_MON_A[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "SPI0_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SPI0_MO"),
+ MTK_FUNCTION(2, "SPI0_MI"),
+ MTK_FUNCTION(3, "SPDIF_IN0"),
+ MTK_FUNCTION(7, "DBG_MON_A[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "SDA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "SCL1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "RAMBUF_I_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "RAMBUF_I_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "WB_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "WB_RSTB"),
+ MTK_FUNCTION(7, "DBG_MON_A[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "F2W_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "F2W_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "F2W_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "F2W_CK"),
+ MTK_FUNCTION(7, "DBG_MON_A[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "WB_SCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "WB_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "WB_SDATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "WB_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "WB_SEN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "WB_SEN"),
+ MTK_FUNCTION(7, "DBG_MON_A[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "WB_CRTL0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "WB_CRTL0"),
+ MTK_FUNCTION(5, "DFD_NTRST_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "WB_CRTL1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "WB_CRTL1"),
+ MTK_FUNCTION(5, "DFD_TMS_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "WB_CRTL2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "WB_CRTL2"),
+ MTK_FUNCTION(5, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "WB_CRTL3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "WB_CRTL3"),
+ MTK_FUNCTION(5, "DFD_TDI_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "WB_CRTL4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "WB_CRTL4"),
+ MTK_FUNCTION(5, "DFD_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_A[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "WB_CRTL5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "WB_CRTL5"),
+ MTK_FUNCTION(7, "DBG_MON_A[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "I2S0_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "I2S0_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "PWM0"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(6, "WCN_I2S_DI"),
+ MTK_FUNCTION(7, "DBG_MON_B[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "I2S0_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(6, "WCN_I2S_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "I2S0_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(6, "WCN_I2S_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "SDA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "SCL0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "SDA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "SCL2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "URXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "UTXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "URXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "UTXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "LCM_RST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "LCM_RST"),
+ MTK_FUNCTION(2, "VDAC_CK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_B[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "DSI_TE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "DSI_TE"),
+ MTK_FUNCTION(7, "DBG_MON_B[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC2_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC2_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC2_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC2_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC2_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC2_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "TDN3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI91"),
+ MTK_FUNCTION(1, "TDN3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "TDP3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI92"),
+ MTK_FUNCTION(1, "TDP3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "TDN2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI93"),
+ MTK_FUNCTION(1, "TDN2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "TDP2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI94"),
+ MTK_FUNCTION(1, "TDP2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "TCN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI95"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "TCP"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI96"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "TDN1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI97"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "TDP1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI98"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "TDN0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI99"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "TDP0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI100"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "SPI2_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SPI2_CS"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "KROW0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "SPI2_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "SPI2_MI"),
+ MTK_FUNCTION(2, "SPI2_MO"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "KROW1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "SPI2_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "SPI2_MO"),
+ MTK_FUNCTION(2, "SPI2_MI"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "KROW2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "SPI2_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "SPI2_CK"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "KROW3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "MSDC1_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "MSDC1_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "MSDC1_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_B[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "MSDC1_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_B[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "MSDC1_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2"),
+ MTK_FUNCTION(7, "DBG_MON_B[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "MSDC1_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3"),
+ MTK_FUNCTION(7, "DBG_MON_B[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "MSDC0_DAT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(4, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "MSDC0_DAT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(4, "NLD6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "MSDC0_DAT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(4, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "MSDC0_DAT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(4, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "MSDC0_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(4, "NLD8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "MSDC0_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(4, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "MSDC0_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(4, "NWEB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "MSDC0_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(4, "NLD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "MSDC0_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(4, "NLD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "MSDC0_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(4, "NLD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "MSDC0_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(4, "NLD0"),
+ MTK_FUNCTION(5, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "CEC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "CEC"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "HTPLG"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "HTPLG"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "HDMISCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "HDMISCK"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "HDMISD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "HDMISD"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "I2S0_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "I2S0_MCLK"),
+ MTK_FUNCTION(6, "WCN_I2S_MCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "RAMBUF_IDATA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "RAMBUF_IDATA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "RAMBUF_IDATA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "RAMBUF_IDATA3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "RAMBUF_IDATA4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "RAMBUF_IDATA5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "RAMBUF_IDATA6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "RAMBUF_IDATA7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "RAMBUF_IDATA8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "RAMBUF_IDATA9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "RAMBUF_IDATA10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "RAMBUF_IDATA11"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "RAMBUF_IDATA12"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "RAMBUF_IDATA13"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "RAMBUF_IDATA14"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "RAMBUF_IDATA15"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "RAMBUF_ODATA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "RAMBUF_ODATA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "RAMBUF_ODATA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "RAMBUF_ODATA3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "RAMBUF_ODATA4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "RAMBUF_ODATA5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "RAMBUF_ODATA6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "RAMBUF_ODATA7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "RAMBUF_ODATA8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "RAMBUF_ODATA9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "RAMBUF_ODATA10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "RAMBUF_ODATA11"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "RAMBUF_ODATA12"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "RAMBUF_ODATA13"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "RAMBUF_ODATA14"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "RAMBUF_ODATA15"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "RAMBUF_BE0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "RAMBUF_BE0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "RAMBUF_BE1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "RAMBUF_BE1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "AP2PT_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "AP2PT_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "AP2PT_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "AP2PT_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "PT2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "PT2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "PT2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "PT2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "AP2UP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "AP2UP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "AP2UP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "AP2UP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "UP2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "UP2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "UP2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "UP2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "RAMBUF_ADDR0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "RAMBUF_ADDR1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "RAMBUF_ADDR2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "RAMBUF_ADDR3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "RAMBUF_ADDR4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "RAMBUF_ADDR5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "RAMBUF_ADDR6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "RAMBUF_ADDR7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "RAMBUF_ADDR8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "RAMBUF_ADDR9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "RAMBUF_ADDR10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "RAMBUF_RW"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "RAMBUF_RW")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "RAMBUF_LAST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "RAMBUF_LAST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "RAMBUF_HP"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "RAMBUF_HP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "RAMBUF_REQ"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "RAMBUF_REQ")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "RAMBUF_ALE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "RAMBUF_ALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "RAMBUF_DLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "RAMBUF_DLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "RAMBUF_WDLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "RAMBUF_WDLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "RAMBUF_O_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "RAMBUF_O_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "I2S2_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "I2S2_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "I2S3_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(2, "I2S3_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "I2S3_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "I2S3_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "I2S3_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "I2S3_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "I2S3_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "I2S3_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "I2S3_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "I2S3_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "I2S4_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "I2S4_DATA"),
+ MTK_FUNCTION(2, "I2S4_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "I2S4_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "I2S4_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "I2S4_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "I2S4_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "I2S4_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "I2S4_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "I2S4_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "I2S4_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "SPI1_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "SPI1_CK"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "KCOL3"),
+ MTK_FUNCTION(7, "DBG_MON_B[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "SPDIF_OUT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "SPDIF_OUT"),
+ MTK_FUNCTION(5, "G1_TXD3"),
+ MTK_FUNCTION(6, "URXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "SPDIF_IN0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "SPDIF_IN0"),
+ MTK_FUNCTION(5, "G1_TXEN"),
+ MTK_FUNCTION(6, "UTXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "SPDIF_IN1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "SPDIF_IN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(203, "PWM0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(5, "G1_TXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[18]"),
+ MTK_FUNCTION(9, "I2S2_DATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(204, "PWM1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO204"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(5, "G1_TXD1"),
+ MTK_FUNCTION(7, "DBG_MON_B[19]"),
+ MTK_FUNCTION(9, "I2S3_DATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(205, "PWM2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO205"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(5, "G1_TXD0"),
+ MTK_FUNCTION(7, "DBG_MON_B[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(206, "PWM3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO206"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "G1_TXC"),
+ MTK_FUNCTION(7, "DBG_MON_B[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(207, "PWM4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO207"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "G1_RXC"),
+ MTK_FUNCTION(7, "DBG_MON_B[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(208, "AUD_EXT_CK1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO208"),
+ MTK_FUNCTION(1, "AUD_EXT_CK1"),
+ MTK_FUNCTION(2, "PWM0"),
+ /* MT7623 take function 3 as PCIE0_PERST_N */
+ MTK_FUNCTION(3, "PCIE0_PERST_N"),
+ MTK_FUNCTION(4, "ANT_SEL5"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(7, "DBG_MON_A[31]"),
+ MTK_FUNCTION(11, "PCIE0_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(209, "AUD_EXT_CK2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO209"),
+ MTK_FUNCTION(1, "AUD_EXT_CK2"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ /* MT7623 take function 3 as PCIE1_PERST_N */
+ MTK_FUNCTION(3, "PCIE1_PERST_N"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_A[32]"),
+ MTK_FUNCTION(11, "PCIE1_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(210, "AUD_CLOCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO210"),
+ MTK_FUNCTION(1, "AUD_CLOCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(211, "DVP_RESET"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO211"),
+ MTK_FUNCTION(1, "DVP_RESET")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(212, "DVP_CLOCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO212"),
+ MTK_FUNCTION(1, "DVP_CLOCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(213, "DVP_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO213"),
+ MTK_FUNCTION(1, "DVP_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(214, "DVP_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO214"),
+ MTK_FUNCTION(1, "DVP_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(215, "DVP_DI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO215"),
+ MTK_FUNCTION(1, "DVP_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(216, "DVP_DO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO216"),
+ MTK_FUNCTION(1, "DVP_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(217, "AP_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO217"),
+ MTK_FUNCTION(1, "AP_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(218, "AP_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO218"),
+ MTK_FUNCTION(1, "AP_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(219, "AP_DI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO219"),
+ MTK_FUNCTION(1, "AP_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(220, "AP_DO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO220"),
+ MTK_FUNCTION(1, "AP_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(221, "DVD_BCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO221"),
+ MTK_FUNCTION(1, "DVD_BCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(222, "T8032_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO222"),
+ MTK_FUNCTION(1, "T8032_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(223, "AP_BCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO223"),
+ MTK_FUNCTION(1, "AP_BCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(224, "HOST_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO224"),
+ MTK_FUNCTION(1, "HOST_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(225, "HOST_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO225"),
+ MTK_FUNCTION(1, "HOST_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(226, "HOST_DO0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO226"),
+ MTK_FUNCTION(1, "HOST_DO0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(227, "HOST_DO1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO227"),
+ MTK_FUNCTION(1, "HOST_DO1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(228, "SLV_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO228"),
+ MTK_FUNCTION(1, "SLV_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(229, "SLV_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO229"),
+ MTK_FUNCTION(1, "SLV_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(230, "SLV_DI0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO230"),
+ MTK_FUNCTION(1, "SLV_DI0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(231, "SLV_DI1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO231"),
+ MTK_FUNCTION(1, "SLV_DI1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(232, "AP2DSP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO232"),
+ MTK_FUNCTION(1, "AP2DSP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO233"),
+ MTK_FUNCTION(1, "AP2DSP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(234, "DSP2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO234"),
+ MTK_FUNCTION(1, "DSP2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO235"),
+ MTK_FUNCTION(1, "DSP2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(236, "EXT_SDIO3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO236"),
+ MTK_FUNCTION(1, "EXT_SDIO3"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(7, "DBG_MON_A[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(237, "EXT_SDIO2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO237"),
+ MTK_FUNCTION(1, "EXT_SDIO2"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(238, "EXT_SDIO1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO238"),
+ MTK_FUNCTION(1, "EXT_SDIO1"),
+ MTK_FUNCTION(2, "IDDIG_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(239, "EXT_SDIO0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO239"),
+ MTK_FUNCTION(1, "EXT_SDIO0"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(240, "EXT_XCS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO240"),
+ MTK_FUNCTION(1, "EXT_XCS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(241, "EXT_SCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO241"),
+ MTK_FUNCTION(1, "EXT_SCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(242, "URTS2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO242"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "UTXD3"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(7, "DBG_MON_B[32]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(243, "UCTS2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO243"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "URXD3"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(7, "DBG_MON_A[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(244, "HDMI_SDA_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO244"),
+ MTK_FUNCTION(1, "HDMI_SDA_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(245, "HDMI_SCL_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO245"),
+ MTK_FUNCTION(1, "HDMI_SCL_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(246, "MHL_SENCE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO246")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(247, "HDMI_HPD_CBUS_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO247"),
+ MTK_FUNCTION(1, "HDMI_HPD_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(248, "HDMI_TESTOUTP_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO248"),
+ MTK_FUNCTION(1, "HDMI_TESTOUTP_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(249, "MSDC0E_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO249"),
+ MTK_FUNCTION(1, "MSDC0E_RSTB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(250, "MSDC0E_DAT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO250"),
+ MTK_FUNCTION(1, "MSDC3_DAT7"),
+ MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(251, "MSDC0E_DAT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO251"),
+ MTK_FUNCTION(1, "MSDC3_DAT6"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(252, "MSDC0E_DAT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO252"),
+ MTK_FUNCTION(1, "MSDC3_DAT5"),
+ MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(253, "MSDC0E_DAT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 138),
+ MTK_FUNCTION(0, "GPIO253"),
+ MTK_FUNCTION(1, "MSDC3_DAT4"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(254, "MSDC0E_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 139),
+ MTK_FUNCTION(0, "GPIO254"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(255, "MSDC0E_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 140),
+ MTK_FUNCTION(0, "GPIO255"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(256, "MSDC0E_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 141),
+ MTK_FUNCTION(0, "GPIO256"),
+ MTK_FUNCTION(1, "MSDC3_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(257, "MSDC0E_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 142),
+ MTK_FUNCTION(0, "GPIO257"),
+ MTK_FUNCTION(1, "MSDC3_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(258, "MSDC0E_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 143),
+ MTK_FUNCTION(0, "GPIO258"),
+ MTK_FUNCTION(1, "MSDC3_CMD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(259, "MSDC0E_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 144),
+ MTK_FUNCTION(0, "GPIO259"),
+ MTK_FUNCTION(1, "MSDC3_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(260, "MSDC0E_DSL"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 145),
+ MTK_FUNCTION(0, "GPIO260"),
+ MTK_FUNCTION(1, "MSDC3_DSL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(261, "MSDC1_INS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 146),
+ MTK_FUNCTION(0, "GPIO261"),
+ MTK_FUNCTION(1, "MSDC1_INS"),
+ MTK_FUNCTION(7, "DBG_MON_B[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(262, "G2_TXEN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO262"),
+ MTK_FUNCTION(1, "G2_TXEN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(263, "G2_TXD3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO263"),
+ MTK_FUNCTION(1, "G2_TXD3"),
+ MTK_FUNCTION(6, "ANT_SEL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(264, "G2_TXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO264"),
+ MTK_FUNCTION(1, "G2_TXD2"),
+ MTK_FUNCTION(6, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(265, "G2_TXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO265"),
+ MTK_FUNCTION(1, "G2_TXD1"),
+ MTK_FUNCTION(6, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(266, "G2_TXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO266"),
+ MTK_FUNCTION(1, "G2_TXD0"),
+ MTK_FUNCTION(6, "ANT_SEL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(267, "G2_TXC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO267"),
+ MTK_FUNCTION(1, "G2_TXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(268, "G2_RXC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO268"),
+ MTK_FUNCTION(1, "G2_RXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(269, "G2_RXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO269"),
+ MTK_FUNCTION(1, "G2_RXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(270, "G2_RXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO270"),
+ MTK_FUNCTION(1, "G2_RXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(271, "G2_RXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO271"),
+ MTK_FUNCTION(1, "G2_RXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(272, "G2_RXD3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO272"),
+ MTK_FUNCTION(1, "G2_RXD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(273, "ESW_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 168),
+ MTK_FUNCTION(0, "GPIO273"),
+ MTK_FUNCTION(1, "ESW_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(274, "G2_RXDV"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO274"),
+ MTK_FUNCTION(1, "G2_RXDV")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(275, "MDC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO275"),
+ MTK_FUNCTION(1, "MDC"),
+ MTK_FUNCTION(6, "ANT_SEL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(276, "MDIO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO276"),
+ MTK_FUNCTION(1, "MDIO"),
+ MTK_FUNCTION(6, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(277, "ESW_RST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO277"),
+ MTK_FUNCTION(1, "ESW_RST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(278, "JTAG_RESET"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 147),
+ MTK_FUNCTION(0, "GPIO278"),
+ MTK_FUNCTION(1, "JTAG_RESET")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(279, "USB3_RES_BOND"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO279"),
+ MTK_FUNCTION(1, "USB3_RES_BOND")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT2701_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2731.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2731.h
new file mode 100644
index 0000000..ae4ed2d
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt2731.h
@@ -0,0 +1,1806 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng <andy.teng@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT2731_H
+#define __PINCTRL_MTK_MT2731_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt2731[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "I0:MD_INT0"),
+ MTK_FUNCTION(2, "I1:UCTS5"),
+ MTK_FUNCTION(3, "O:I2S4_MCK"),
+ MTK_FUNCTION(4, "O:I2S5_MCK"),
+ MTK_FUNCTION(6, "O:AUXIF_CLK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B8")
+ ),
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "I0:MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(2, "O:URTS5"),
+ MTK_FUNCTION(3, "B1:SDA_6306"),
+ MTK_FUNCTION(4, "I0:EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "O:AUXIF_ST"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B9")
+ ),
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "O:CLKM0"),
+ MTK_FUNCTION(2, "I0:NOR_BYPASS_ROOM_BOOT"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B17")
+ ),
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(2, "O:SPI0_B_CS0C"),
+ MTK_FUNCTION(3, "B1:SDA0"),
+ MTK_FUNCTION(4, "O:UTXD3"),
+ MTK_FUNCTION(5, "O:PWM2"),
+ MTK_FUNCTION(6, "B1:SDA4")
+ ),
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "I0:SPI1_A_MI"),
+ MTK_FUNCTION(2, "O:CLKM1"),
+ MTK_FUNCTION(3, "B1:SDA3"),
+ MTK_FUNCTION(4, "I0:SPIS_MOSI"),
+ MTK_FUNCTION(5, "O:I2S4_BCK")
+ ),
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "O:SPI1_A_MO"),
+ MTK_FUNCTION(2, "O:CLKM2"),
+ MTK_FUNCTION(3, "B1:SCL3"),
+ MTK_FUNCTION(4, "O:SPIS_MISO"),
+ MTK_FUNCTION(5, "O:I2S4_LRCK")
+ ),
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "O:SPI1_A_CS1A"),
+ MTK_FUNCTION(2, "B1:SDA4"),
+ MTK_FUNCTION(3, "B1:SDA_6306"),
+ MTK_FUNCTION(4, "I1:SPIS_CSB"),
+ MTK_FUNCTION(5, "O:I2S4_MCK")
+ ),
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "O:SPI1_A_CLK"),
+ MTK_FUNCTION(2, "B1:SCL4"),
+ MTK_FUNCTION(3, "O:SCL_6306"),
+ MTK_FUNCTION(4, "I0:SPIS_CLK"),
+ MTK_FUNCTION(5, "I0:I2S4_DI")
+ ),
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(2, "I0:MD_INT0"),
+ MTK_FUNCTION(3, "B1:SCL0"),
+ MTK_FUNCTION(4, "I1:URXD3"),
+ MTK_FUNCTION(5, "O:PWM1"),
+ MTK_FUNCTION(6, "B1:SCL4")
+ ),
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(2, "B0:MIPI3_SDATA")
+ ),
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "I0:EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "O:I2S6_BCK"),
+ MTK_FUNCTION(4, "O:TDMO_BCK_OUT"),
+ MTK_FUNCTION(5, "I0:IO_JTAG_TCK"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TCK")
+ ),
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "I0:SRCLKENAI1"),
+ MTK_FUNCTION(2, "I0:EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A7")
+ ),
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "I0:SRCLKENAI0"),
+ MTK_FUNCTION(2, "O:I2S6_MCK"),
+ MTK_FUNCTION(3, "I0:MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A8")
+ ),
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "O:I2S4_LRCK"),
+ MTK_FUNCTION(2, "I0:SPI2_A_MI"),
+ MTK_FUNCTION(3, "O:PCM1_DO2"),
+ MTK_FUNCTION(5, "O:I2S5_LRCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B25")
+ ),
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "I0:I2S4_DI"),
+ MTK_FUNCTION(2, "O:SPI2_A_CLK"),
+ MTK_FUNCTION(3, "O:UTXD5"),
+ MTK_FUNCTION(5, "O:I2S5_DO"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B26")
+ ),
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "O:I2S4_BCK"),
+ MTK_FUNCTION(2, "O:SPI2_A_MO"),
+ MTK_FUNCTION(3, "I1:URXD5"),
+ MTK_FUNCTION(5, "O:I2S5_BCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B27")
+ ),
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "I1:URXD0"),
+ MTK_FUNCTION(2, "I1:MD_URXD0"),
+ MTK_FUNCTION(3, "O:UTXD0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B0")
+ ),
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "O:UTXD0"),
+ MTK_FUNCTION(2, "O:MD_UTXD0"),
+ MTK_FUNCTION(3, "I1:URXD0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B1")
+ ),
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "I1:URXD1"),
+ MTK_FUNCTION(2, "I1:MD_URXD1"),
+ MTK_FUNCTION(3, "O:UTXD1"),
+ MTK_FUNCTION(5, "O:UTXD3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B2")
+ ),
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "O:UTXD1"),
+ MTK_FUNCTION(2, "O:MD_UTXD1"),
+ MTK_FUNCTION(3, "I1:URXD1"),
+ MTK_FUNCTION(5, "I1:URXD3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B3")
+ ),
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "B0:PCM1_SYNC"),
+ MTK_FUNCTION(2, "O:MRG_SYNC"),
+ MTK_FUNCTION(3, "O:I2S4_BCK"),
+ MTK_FUNCTION(4, "O:I2S5_BCK"),
+ MTK_FUNCTION(5, "B0:I2S0_BCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B4")
+ ),
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "B0:PCM1_CLK"),
+ MTK_FUNCTION(2, "O:MRG_CLK"),
+ MTK_FUNCTION(3, "O:I2S4_LRCK"),
+ MTK_FUNCTION(4, "O:I2S5_LRCK"),
+ MTK_FUNCTION(5, "B0:I2S0_LRCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B5")
+ ),
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "I0:PCM1_DI"),
+ MTK_FUNCTION(2, "I0:MRG_DI"),
+ MTK_FUNCTION(3, "I0:I2S4_DI"),
+ MTK_FUNCTION(4, "O:I2S5_DO"),
+ MTK_FUNCTION(5, "I0:I2S0_DI"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B6")
+ ),
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "O:PCM1_DO0"),
+ MTK_FUNCTION(2, "O:MRG_DO"),
+ MTK_FUNCTION(3, "O:I2S5_DO"),
+ MTK_FUNCTION(5, "O:I2S0_DO"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B7")
+ ),
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "O:USB_DRVVBUS"),
+ MTK_FUNCTION(2, "I1:UCTS1"),
+ MTK_FUNCTION(3, "I0:SRCLKENAI1"),
+ MTK_FUNCTION(5, "O:I2S0_MCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B10")
+ ),
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "I1:IDDIG"),
+ MTK_FUNCTION(2, "O:URTS1"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B11")
+ ),
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "O:UTXD6"),
+ MTK_FUNCTION(2, "I1:URXD6"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B12")
+ ),
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "I1:URXD6"),
+ MTK_FUNCTION(2, "O:UTXD6"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B13")
+ ),
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "I0:SRCLKENAI0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B14")
+ ),
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "O:AGPS_SYNC")
+ ),
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "I0:MSDC2_DSL"),
+ MTK_FUNCTION(2, "I0:MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(3, "O:SCL_6306"),
+ MTK_FUNCTION(4, "I1:UCTS3")
+ ),
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "B1:MSDC2_CLK"),
+ MTK_FUNCTION(4, "O:URTS3")
+ ),
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "B1:MSDC2_CMD"),
+ MTK_FUNCTION(2, "O:I2S0_MCK"),
+ MTK_FUNCTION(3, "I0:HSM_JTAG_TCK"),
+ MTK_FUNCTION(4, "I0:IO_JTAG_TCK"),
+ MTK_FUNCTION(5, "I0:UDI_TCK"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TCK")
+ ),
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "B1:MSDC2_DAT3"),
+ MTK_FUNCTION(2, "B0:I2S0_BCK"),
+ MTK_FUNCTION(3, "I0:HSM_JTAG_TMS"),
+ MTK_FUNCTION(4, "B1:IO_JTAG_TMS"),
+ MTK_FUNCTION(5, "I0:UDI_TMS"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TMS")
+ ),
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "B1:MSDC2_DAT2"),
+ MTK_FUNCTION(2, "B0:I2S0_LRCK"),
+ MTK_FUNCTION(3, "O:HSM_JTAG_TDO"),
+ MTK_FUNCTION(4, "O:IO_JTAG_TDO"),
+ MTK_FUNCTION(5, "O:UDI_TDO"),
+ MTK_FUNCTION(6, "B1:SPM_JTAG_TDO")
+ ),
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "B1:MSDC2_DAT1"),
+ MTK_FUNCTION(2, "I0:I2S0_DI"),
+ MTK_FUNCTION(3, "I0:HSM_JTAG_TDI"),
+ MTK_FUNCTION(4, "I1:IO_JTAG_TDI"),
+ MTK_FUNCTION(5, "I0:UDI_TDI"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TDI")
+ ),
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "B1:MSDC2_DAT0"),
+ MTK_FUNCTION(2, "O:I2S0_DO"),
+ MTK_FUNCTION(3, "I0:HSM_JTAG_TRSTN_N"),
+ MTK_FUNCTION(4, "I1:IO_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "I0:UDI_NTRST"),
+ MTK_FUNCTION(6, "I0:SPM_JTAG_TRSTN")
+ ),
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "B1:SDA1"),
+ MTK_FUNCTION(2, "O:SPI2_A_CS2B"),
+ MTK_FUNCTION(3, "B0:PCM1_CLK"),
+ MTK_FUNCTION(4, "O:UTXD4"),
+ MTK_FUNCTION(5, "I0:EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "I1:UCTS0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B18")
+ ),
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "B1:SCL1"),
+ MTK_FUNCTION(2, "O:SPI2_A_CS2C"),
+ MTK_FUNCTION(3, "B0:PCM1_SYNC"),
+ MTK_FUNCTION(4, "I1:URXD4"),
+ MTK_FUNCTION(5, "O:AGPS_SYNC"),
+ MTK_FUNCTION(6, "O:URTS0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B19")
+ ),
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "B1:SDA2"),
+ MTK_FUNCTION(2, "B1:SDA1"),
+ MTK_FUNCTION(3, "I0:PCM1_DI"),
+ MTK_FUNCTION(4, "O:UTXD5"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B20")
+ ),
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "B1:SCL2"),
+ MTK_FUNCTION(2, "B1:SCL1"),
+ MTK_FUNCTION(3, "O:PCM1_DO0"),
+ MTK_FUNCTION(4, "I1:URXD5"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B21")
+ ),
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "B1:SDA0"),
+ MTK_FUNCTION(5, "B1:DAP_MD32_SWD"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B22")
+ ),
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "B1:SCL0"),
+ MTK_FUNCTION(5, "I0:DAP_MD32_SWCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B23")
+ ),
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "O:I2S4_MCK"),
+ MTK_FUNCTION(2, "O:SPI2_A_CS2A"),
+ MTK_FUNCTION(3, "O:PCM1_DO1"),
+ MTK_FUNCTION(5, "O:I2S5_MCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B24")
+ ),
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "B0:PCIE_CLKREQ_N")
+ ),
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "B1:PCIE_WAKE_N")
+ ),
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "B1:PCIE_PERST_N")
+ ),
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "O:SPI0_A_CS0A"),
+ MTK_FUNCTION(2, "I1:UCTS2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B28")
+ ),
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "I0:SPI0_A_MI"),
+ MTK_FUNCTION(2, "I1:URXD2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B29")
+ ),
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "O:SPI0_A_CLK"),
+ MTK_FUNCTION(2, "O:URTS2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B30")
+ ),
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "O:SPI0_A_MO"),
+ MTK_FUNCTION(2, "O:UTXD2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B31")
+ ),
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "B1:JTMS_SEL1"),
+ MTK_FUNCTION(2, "I0:SPI0_B_MI"),
+ MTK_FUNCTION(3, "I0:MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(4, "I0:HSM_JTAG_TMS"),
+ MTK_FUNCTION(5, "I0:DFD_TMS"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TMS"),
+ MTK_FUNCTION(7, "JTMS_SEL1")
+ ),
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "I0:JTCK_SEL1"),
+ MTK_FUNCTION(2, "O:SPI0_B_CLK"),
+ MTK_FUNCTION(3, "O:I2S6_MCK"),
+ MTK_FUNCTION(4, "I0:HSM_JTAG_TCK"),
+ MTK_FUNCTION(5, "I0:DFD_TCK_XI"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TCK"),
+ MTK_FUNCTION(7, "JTCK_SEL1")
+ ),
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "I1:JTDI_SEL1"),
+ MTK_FUNCTION(2, "O:SPI0_B_MO"),
+ MTK_FUNCTION(3, "O:I2S6_BCK"),
+ MTK_FUNCTION(4, "I0:HSM_JTAG_TDI"),
+ MTK_FUNCTION(5, "I0:DFD_TDI"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TDI"),
+ MTK_FUNCTION(7, "JTDI_SEL1")
+ ),
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "O:JTDO_SEL1"),
+ MTK_FUNCTION(2, "O:SPI0_B_CS0A"),
+ MTK_FUNCTION(3, "O:I2S6_LRCK"),
+ MTK_FUNCTION(4, "O:HSM_JTAG_TDO"),
+ MTK_FUNCTION(5, "O:DFD_TDO"),
+ MTK_FUNCTION(6, "B1:SPM_JTAG_TDO"),
+ MTK_FUNCTION(7, "JTDO_SEL1")
+ ),
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "I1:JTRSTN_SEL1"),
+ MTK_FUNCTION(2, "O:SPI0_B_CS0B"),
+ MTK_FUNCTION(3, "I0:I2S6_DI"),
+ MTK_FUNCTION(4, "I0:HSM_JTAG_TRSTN_N"),
+ MTK_FUNCTION(6, "I0:SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "JTRSTN_SEL1")
+ ),
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "O:PTA_TXD"),
+ MTK_FUNCTION(2, "O:UTXD3"),
+ MTK_FUNCTION(3, "B1:SDA3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B15")
+ ),
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "I1:PTA_RXD"),
+ MTK_FUNCTION(2, "I1:URXD3"),
+ MTK_FUNCTION(3, "B1:SCL3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_B16")
+ ),
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO58")
+ ),
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "B1:MSDC1_CMD"),
+ MTK_FUNCTION(2, "O:BPI_BUS15_ANT4"),
+ MTK_FUNCTION(7, "I0:DAP_MD32_SWCK")
+ ),
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "B1:MSDC1_DAT3"),
+ MTK_FUNCTION(2, "O:BPI_BUS14_ANT3"),
+ MTK_FUNCTION(7, "B1:DAP_MD32_SWD")
+ ),
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "B1:MSDC1_DAT2"),
+ MTK_FUNCTION(2, "O:BPI_BUS13_ANT2")
+ ),
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "B1:MSDC1_DAT1"),
+ MTK_FUNCTION(2, "O:BPI_BUS12_ANT1")
+ ),
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "B1:MSDC1_DAT0"),
+ MTK_FUNCTION(2, "O:BPI_BUS11_ANT0")
+ ),
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "B1:MSDC1_CLK"),
+ MTK_FUNCTION(2, "O:MIPI3_SCLK")
+ ),
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "O:BPI_BUS10")
+ ),
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "O:BPI_BUS9")
+ ),
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "O:BPI_BUS8")
+ ),
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "B0:RFIC0_BSI_D0")
+ ),
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "B0:RFIC0_BSI_D1")
+ ),
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "B0:RFIC0_BSI_D2")
+ ),
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "O:RFIC0_BSI_CK")
+ ),
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "O:RFIC0_BSI_EN")
+ ),
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "B0:MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "O:MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "B0:MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "O:MIPI0_SCLK")
+ ),
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "O:MIPI2_SCLK")
+ ),
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "B0:MIPI2_SDATA")
+ ),
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "O:BPI_BUS6")
+ ),
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "O:BPI_BUS7")
+ ),
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "O:BPI_BUS5"),
+ MTK_FUNCTION(2, "I1:URXD2"),
+ MTK_FUNCTION(3, "O:CLKM3")
+ ),
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "O:BPI_BUS4"),
+ MTK_FUNCTION(2, "O:UTXD2")
+ ),
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "O:BPI_BUS3")
+ ),
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "O:BPI_BUS2")
+ ),
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "O:BPI_BUS1")
+ ),
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "O:BPI_BUS0")
+ ),
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "O:BPI_PA_VM1"),
+ MTK_FUNCTION(2, "B0:MIPI4_SDATA"),
+ MTK_FUNCTION(3, "O:I2S5_BCK"),
+ MTK_FUNCTION(4, "I1:UCTS2")
+ ),
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "O:BPI_PA_VM0"),
+ MTK_FUNCTION(2, "O:MIPI4_SCLK"),
+ MTK_FUNCTION(3, "O:I2S5_LRCK"),
+ MTK_FUNCTION(4, "O:URTS2")
+ ),
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "O:PWM0"),
+ MTK_FUNCTION(2, "O:UTXD2"),
+ MTK_FUNCTION(3, "O:I2S5_MCK"),
+ MTK_FUNCTION(4, "O:TDMO_SDATA2"),
+ MTK_FUNCTION(5, "B1:SDA1"),
+ MTK_FUNCTION(6, "O:SPI1_B_CS1B")
+ ),
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "O:PWM1"),
+ MTK_FUNCTION(2, "I1:URXD2"),
+ MTK_FUNCTION(3, "O:I2S5_DO"),
+ MTK_FUNCTION(4, "O:TDMO_SDATA3"),
+ MTK_FUNCTION(5, "B1:SCL1"),
+ MTK_FUNCTION(6, "O:SPI1_B_CS1C")
+ ),
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "I0:RTC32K_CK")
+ ),
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "O:WATCHDOG")
+ ),
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "O:SPI1_B_CS1A"),
+ MTK_FUNCTION(2, "O:UTXD1"),
+ MTK_FUNCTION(3, "O:I2S6_MCK"),
+ MTK_FUNCTION(4, "O:TDMO_MCK_OUT"),
+ MTK_FUNCTION(5, "B1:IO_JTAG_TMS"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TMS")
+ ),
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "O:SPI1_B_CLK"),
+ MTK_FUNCTION(2, "I1:URXD1"),
+ MTK_FUNCTION(4, "O:TDMO_SDATA1"),
+ MTK_FUNCTION(5, "I1:IO_JTAG_TDI"),
+ MTK_FUNCTION(6, "I1:SPM_JTAG_TDI")
+ ),
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "I0:SPI1_B_MI"),
+ MTK_FUNCTION(2, "I1:UCTS1"),
+ MTK_FUNCTION(3, "O:I2S6_LRCK"),
+ MTK_FUNCTION(4, "O:TDMO_LRCK"),
+ MTK_FUNCTION(5, "I1:IO_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "I0:SPM_JTAG_TRSTN")
+ ),
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "O:SPI1_B_MO"),
+ MTK_FUNCTION(2, "O:URTS1"),
+ MTK_FUNCTION(3, "I0:I2S6_DI"),
+ MTK_FUNCTION(4, "O:TDMO_SDATA0"),
+ MTK_FUNCTION(5, "O:IO_JTAG_TDO"),
+ MTK_FUNCTION(6, "B1:SPM_JTAG_TDO")
+ ),
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "O:AUD_CLK_MOSI"),
+ MTK_FUNCTION(2, "O:I2S2_MCK"),
+ MTK_FUNCTION(3, "O:I2S1_MCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A0")
+ ),
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "O:AUD_DAT_MOSI0"),
+ MTK_FUNCTION(2, "O:I2S2_BCK"),
+ MTK_FUNCTION(3, "O:I2S1_BCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A1")
+ ),
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "O:AUD_SYNC_MOSI"),
+ MTK_FUNCTION(2, "O:I2S2_LRCK"),
+ MTK_FUNCTION(3, "O:I2S1_LRCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A2")
+ ),
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "I0:AUD_CLK_MISO"),
+ MTK_FUNCTION(2, "I0:I2S2_DI"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A3")
+ ),
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "O:PWRAP_SPI0_CSN")
+ ),
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "I0:AUD_SYNC_MISO"),
+ MTK_FUNCTION(2, "O:I2S1_DO"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A4")
+ ),
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "I0:AUD_DAT_MISO0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A5")
+ ),
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "O:SRCLKENA0")
+ ),
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "O:SRCLKENA1")
+ ),
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "B0:PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "B0:PWRAP_SPI0_MI")
+ ),
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "I0:AUD_DAT_MISO1"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A6")
+ ),
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "O:PWRAP_SPI0_CK")
+ ),
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "B0:PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "B0:PWRAP_SPI0_MO")
+ ),
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "B1:MD1_SIM2_SIO"),
+ MTK_FUNCTION(2, "O:I2S6_BCK"),
+ MTK_FUNCTION(3, "B1:MD1_SIM1_SIO"),
+ MTK_FUNCTION(4, "I0:LVTS_SCF"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A9")
+ ),
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "O:MD1_SIM2_SRST"),
+ MTK_FUNCTION(2, "O:I2S6_LRCK"),
+ MTK_FUNCTION(3, "O:MD1_SIM1_SRST"),
+ MTK_FUNCTION(4, "I0:LVTS_SDI"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A10")
+ ),
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "O:MD1_SIM2_SCLK"),
+ MTK_FUNCTION(2, "I0:I2S6_DI"),
+ MTK_FUNCTION(3, "O:MD1_SIM1_SCLK"),
+ MTK_FUNCTION(4, "I0:LVTS_SCK"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A11")
+ ),
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "B1:MD1_SIM1_SIO"),
+ MTK_FUNCTION(3, "B1:MD1_SIM2_SIO"),
+ MTK_FUNCTION(4, "O:LVTS_FOUT"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A12")
+ ),
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "O:MD1_SIM1_SRST"),
+ MTK_FUNCTION(3, "O:MD1_SIM2_SRST"),
+ MTK_FUNCTION(4, "O:LVTS_SDO"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A13")
+ ),
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "O:MD1_SIM1_SCLK"),
+ MTK_FUNCTION(3, "O:MD1_SIM2_SCLK"),
+ MTK_FUNCTION(4, "I0:LVTS_26M"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A14")
+ ),
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "O:GBE_TXD3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A15")
+ ),
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "O:GBE_TXD2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A16")
+ ),
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "O:GBE_TXD1"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A17")
+ ),
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "O:GBE_TXD0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A18")
+ ),
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "I0:GBE_RXD3"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A19")
+ ),
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "I0:GBE_RXD2"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A20")
+ ),
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "I0:GBE_RXD1"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A21")
+ ),
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "I0:GBE_RXD0"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A22")
+ ),
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "B0:GBE_TXC"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A23")
+ ),
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "I0:GBE_RXC"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A24")
+ ),
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "I0:GBE_RXDV"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A25")
+ ),
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "O:GBE_TXEN"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A26")
+ ),
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "O:GBE_MDC"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A27")
+ ),
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "B0:GBE_MDIO"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A28")
+ ),
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "O:GBE_TXER"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A29")
+ ),
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "I0:GBE_RXER"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A30")
+ ),
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "I0:GBE_COL"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A31")
+ ),
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "I0:GBE_INTR"),
+ MTK_FUNCTION(7, "B0:DBG_MON_A32")
+ ),
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT6"),
+ MTK_FUNCTION(3, "O:I2S4_BCK"),
+ MTK_FUNCTION(4, "I0:SPI2_B_MI"),
+ MTK_FUNCTION(5, "B0:I2S0_BCK")
+ ),
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT5"),
+ MTK_FUNCTION(3, "O:I2S4_LRCK"),
+ MTK_FUNCTION(4, "O:SPI2_B_CLK"),
+ MTK_FUNCTION(5, "B0:I2S0_LRCK")
+ ),
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT7"),
+ MTK_FUNCTION(2, "O:UTXD4"),
+ MTK_FUNCTION(3, "I0:I2S4_DI"),
+ MTK_FUNCTION(4, "O:SPI2_B_MO"),
+ MTK_FUNCTION(5, "I0:I2S0_DI")
+ ),
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "I0:MSDC0_DSL")
+ ),
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "B1:MSDC0_CLK")
+ ),
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT3")
+ ),
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "O:MSDC0_RSTB")
+ ),
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT0")
+ ),
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "B1:MSDC0_CMD")
+ ),
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT2")
+ ),
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT4"),
+ MTK_FUNCTION(2, "I1:URXD4"),
+ MTK_FUNCTION(3, "O:I2S4_MCK"),
+ MTK_FUNCTION(4, "O:SPI2_B_CS2A"),
+ MTK_FUNCTION(5, "O:I2S0_DO")
+ ),
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "B1:MSDC0_DAT1")
+ ),
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "B0:NLD0"),
+ MTK_FUNCTION(2, "I0:SPI1_C_MI")
+ ),
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "B0:NLD1"),
+ MTK_FUNCTION(2, "O:SPI1_C_CLK")
+ ),
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "B0:NLD2"),
+ MTK_FUNCTION(2, "O:SPI1_C_MO")
+ ),
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "B0:NLD3"),
+ MTK_FUNCTION(2, "O:SPI1_C_CS1A")
+ ),
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "B0:NLD4"),
+ MTK_FUNCTION(2, "O:SPI1_C_CS1B"),
+ MTK_FUNCTION(3, "B1:SDA3"),
+ MTK_FUNCTION(4, "O:UTXD1")
+ ),
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "B0:NLD5"),
+ MTK_FUNCTION(2, "O:SPI1_C_CS1C"),
+ MTK_FUNCTION(3, "B1:SCL3"),
+ MTK_FUNCTION(4, "I1:URXD1")
+ ),
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "B0:NLD6"),
+ MTK_FUNCTION(2, "B1:SDA2"),
+ MTK_FUNCTION(3, "O:PWM0"),
+ MTK_FUNCTION(4, "I1:UCTS1")
+ ),
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "B0:NLD7"),
+ MTK_FUNCTION(2, "B1:SCL2"),
+ MTK_FUNCTION(3, "O:PWM2"),
+ MTK_FUNCTION(4, "O:URTS1")
+ ),
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "O:NALE"),
+ MTK_FUNCTION(2, "B0:SNFI_MISO")
+ ),
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "O:NCLE"),
+ MTK_FUNCTION(2, "B0:SNFI_MOSI")
+ ),
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "I1:NRNB"),
+ MTK_FUNCTION(2, "B0:SNFI_WP")
+ ),
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "O:NWEB"),
+ MTK_FUNCTION(2, "O:SNFI_CLK")
+ ),
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "O:NREB"),
+ MTK_FUNCTION(2, "B0:SNFI_HOLD")
+ ),
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "O:NCEB0"),
+ MTK_FUNCTION(2, "O:SNFI_CS")
+ ),
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+};
+
+#ifdef CONFIG_PINCTRL_MTK_DEBUG
+static const struct pin_bi_dir_mapping mtk_bi_dir_mapping_mt2731[] = {
+ {"B1:MD1_SIM2_SIO", 0},
+ {"B1:MD1_SIM1_SIO", 0},
+ {"B1:SDA_6306", 0},
+ {"B1:IO_JTAG_TMS", 0},
+ {"B1:DAP_MD32_SWD", 0},
+ {"B0:RFIC0_BSI_D2", 0},
+ {"B0:RFIC0_BSI_D1", 0},
+ {"B0:RFIC0_BSI_D0", 0},
+ {"B0:MIPI0_SDATA", 0},
+ {"B0:MIPI1_SDATA", 0},
+ {"B0:MIPI2_SDATA", 0},
+ {"B0:MIPI3_SDATA", 0},
+ {"B0:MIPI4_SDATA", 0},
+ {"B1:SPM_JTAG_TDO", 1},
+ {"B1:SDA0", 0},
+ {"B1:SCL0", 0},
+ {"B1:SDA1", 0},
+ {"B1:SCL1", 0},
+ {"B1:SDA2", 0},
+ {"B1:SCL2", 0},
+ {"B1:SDA4", 0},
+ {"B1:SCL4", 0},
+ {"B1:SDA3", 0},
+ {"B1:SCL3", 0},
+ {"B0:PWRAP_SPI0_MO", 0},
+ {"B0:PWRAP_SPI0_MI", 0},
+ {"B0:I2S0_BCK", 1},
+ {"B0:I2S0_LRCK", 1},
+ {"B0:PCM1_CLK", 0},
+ {"B0:PCM1_SYNC", 0},
+ {"B1:MSDC0_DAT7", 0},
+ {"B1:MSDC0_DAT6", 0},
+ {"B1:MSDC0_DAT5", 0},
+ {"B1:MSDC0_DAT4", 0},
+ {"B1:MSDC0_CMD", 0},
+ {"B1:MSDC0_CLK", 1},
+ {"B1:MSDC0_DAT3", 0},
+ {"B1:MSDC0_DAT2", 0},
+ {"B1:MSDC0_DAT1", 0},
+ {"B1:MSDC0_DAT0", 0},
+ {"B1:MSDC1_CMD", 0},
+ {"B1:MSDC1_CLK", 1},
+ {"B1:MSDC1_DAT0", 0},
+ {"B1:MSDC1_DAT1", 0},
+ {"B1:MSDC1_DAT2", 0},
+ {"B1:MSDC1_DAT3", 0},
+ {"B1:MSDC2_CMD", 0},
+ {"B1:MSDC2_CLK", 1},
+ {"B1:MSDC2_DAT0", 0},
+ {"B1:MSDC2_DAT1", 0},
+ {"B1:MSDC2_DAT2", 0},
+ {"B1:MSDC2_DAT3", 0},
+ {"B0:NLD0", 0},
+ {"B0:NLD1", 0},
+ {"B0:NLD2", 0},
+ {"B0:NLD3", 0},
+ {"B0:NLD4", 0},
+ {"B0:NLD5", 0},
+ {"B0:NLD6", 0},
+ {"B0:NLD7", 0},
+ {"B0:SNFI_MOSI", 1},
+ {"B0:SNFI_MISO", 1},
+ {"B0:SNFI_WP", 1},
+ {"B0:SNFI_HOLD", 1},
+ {"B0:GBE_TXC", 1},
+ {"B0:GBE_MDIO", 0},
+ {"B1:JTMS_SEL1", 0},
+ {"B1:JTMS_SEL2", 0},
+ {"B0:DBG_MON_A0", 1},
+ {"B0:DBG_MON_A1", 1},
+ {"B0:DBG_MON_A2", 1},
+ {"B0:DBG_MON_A3", 1},
+ {"B0:DBG_MON_A4", 1},
+ {"B0:DBG_MON_A5", 1},
+ {"B0:DBG_MON_A6", 1},
+ {"B0:DBG_MON_A7", 1},
+ {"B0:DBG_MON_A8", 1},
+ {"B0:DBG_MON_A9", 1},
+ {"B0:DBG_MON_A10", 1},
+ {"B0:DBG_MON_A11", 1},
+ {"B0:DBG_MON_A12", 1},
+ {"B0:DBG_MON_A13", 1},
+ {"B0:DBG_MON_A14", 1},
+ {"B0:DBG_MON_A15", 1},
+ {"B0:DBG_MON_A16", 1},
+ {"B0:DBG_MON_A17", 1},
+ {"B0:DBG_MON_A18", 1},
+ {"B0:DBG_MON_A19", 1},
+ {"B0:DBG_MON_A20", 1},
+ {"B0:DBG_MON_A21", 1},
+ {"B0:DBG_MON_A22", 1},
+ {"B0:DBG_MON_A23", 1},
+ {"B0:DBG_MON_A24", 1},
+ {"B0:DBG_MON_A25", 1},
+ {"B0:DBG_MON_A26", 1},
+ {"B0:DBG_MON_A27", 1},
+ {"B0:DBG_MON_A28", 1},
+ {"B0:DBG_MON_A29", 1},
+ {"B0:DBG_MON_A30", 1},
+ {"B0:DBG_MON_A31", 1},
+ {"B0:DBG_MON_A32", 1},
+ {"B0:DBG_MON_B0", 1},
+ {"B0:DBG_MON_B1", 1},
+ {"B0:DBG_MON_B2", 1},
+ {"B0:DBG_MON_B3", 1},
+ {"B0:DBG_MON_B4", 1},
+ {"B0:DBG_MON_B5", 1},
+ {"B0:DBG_MON_B6", 1},
+ {"B0:DBG_MON_B7", 1},
+ {"B0:DBG_MON_B8", 1},
+ {"B0:DBG_MON_B9", 1},
+ {"B0:DBG_MON_B10", 1},
+ {"B0:DBG_MON_B11", 1},
+ {"B0:DBG_MON_B12", 1},
+ {"B0:DBG_MON_B13", 1},
+ {"B0:DBG_MON_B14", 1},
+ {"B0:DBG_MON_B15", 1},
+ {"B0:DBG_MON_B16", 1},
+ {"B0:DBG_MON_B17", 1},
+ {"B0:DBG_MON_B18", 1},
+ {"B0:DBG_MON_B19", 1},
+ {"B0:DBG_MON_B20", 1},
+ {"B0:DBG_MON_B21", 1},
+ {"B0:DBG_MON_B22", 1},
+ {"B0:DBG_MON_B23", 1},
+ {"B0:DBG_MON_B24", 1},
+ {"B0:DBG_MON_B25", 1},
+ {"B0:DBG_MON_B26", 1},
+ {"B0:DBG_MON_B27", 1},
+ {"B0:DBG_MON_B28", 1},
+ {"B0:DBG_MON_B29", 1},
+ {"B0:DBG_MON_B30", 1},
+ {"B0:DBG_MON_B31", 1},
+ {"B0:PCIE_CLKREQ_N", 0},
+ {"B1:PCIE_WAKE_N", 1},
+ {"B1:PCIE_PERST_N", 0},
+ {"B1:MD1_SIM2_SIO", 0},
+ {"B1:MD1_SIM1_SIO", 0},
+ {"B1:SDA_6306", 0},
+ {"B1:IO_JTAG_TMS", 0},
+ {"B1:DAP_MD32_SWD", 0},
+ {"B0:RFIC0_BSI_D2", 0},
+ {"B0:RFIC0_BSI_D1", 0},
+ {"B0:RFIC0_BSI_D0", 0},
+ {"B0:MIPI0_SDATA", 0},
+ {"B0:MIPI1_SDATA", 0},
+ {"B0:MIPI2_SDATA", 0},
+ {"B0:MIPI3_SDATA", 0},
+ {"B0:MIPI4_SDATA", 0},
+ {"B1:SPM_JTAG_TDO", 1},
+ {"B1:SDA0", 0},
+ {"B1:SCL0", 0},
+ {"B1:SDA1", 0},
+ {"B1:SCL1", 0},
+ {"B1:SDA2", 0},
+ {"B1:SCL2", 0},
+ {"B1:SDA4", 0},
+ {"B1:SCL4", 0},
+ {"B1:SDA3", 0},
+ {"B1:SCL3", 0},
+ {"B0:PWRAP_SPI0_MO", 0},
+ {"B0:PWRAP_SPI0_MI", 0},
+ {"B0:I2S0_BCK", 1},
+ {"B0:I2S0_LRCK", 1},
+ {"B0:PCM1_CLK", 0},
+ {"B0:PCM1_SYNC", 0},
+ {"B1:MSDC0_DAT7", 0},
+ {"B1:MSDC0_DAT6", 0},
+ {"B1:MSDC0_DAT5", 0},
+ {"B1:MSDC0_DAT4", 0},
+ {"B1:MSDC0_CMD", 0},
+ {"B1:MSDC0_CLK", 1},
+ {"B1:MSDC0_DAT3", 0},
+ {"B1:MSDC0_DAT2", 0},
+ {"B1:MSDC0_DAT1", 0},
+ {"B1:MSDC0_DAT0", 0},
+ {"B1:MSDC1_CMD", 0},
+ {"B1:MSDC1_CLK", 1},
+ {"B1:MSDC1_DAT0", 0},
+ {"B1:MSDC1_DAT1", 0},
+ {"B1:MSDC1_DAT2", 0},
+ {"B1:MSDC1_DAT3", 0},
+ {"B1:MSDC2_CMD", 0},
+ {"B1:MSDC2_CLK", 1},
+ {"B1:MSDC2_DAT0", 0},
+ {"B1:MSDC2_DAT1", 0},
+ {"B1:MSDC2_DAT2", 0},
+ {"B1:MSDC2_DAT3", 0},
+ {"B0:NLD0", 0},
+ {"B0:NLD1", 0},
+ {"B0:NLD2", 0},
+ {"B0:NLD3", 0},
+ {"B0:NLD4", 0},
+ {"B0:NLD5", 0},
+ {"B0:NLD6", 0},
+ {"B0:NLD7", 0},
+ {"B0:SNFI_MOSI", 1},
+ {"B0:SNFI_MISO", 1},
+ {"B0:SNFI_WP", 1},
+ {"B0:SNFI_HOLD", 1},
+ {"B0:GBE_TXC", 1},
+ {"B0:GBE_MDIO", 0},
+ {"B1:JTMS_SEL1", 0},
+ {"B1:JTMS_SEL2", 0},
+ {"B0:DBG_MON_A0", 1},
+ {"B0:DBG_MON_A1", 1},
+ {"B0:DBG_MON_A2", 1},
+ {"B0:DBG_MON_A3", 1},
+ {"B0:DBG_MON_A4", 1},
+ {"B0:DBG_MON_A5", 1},
+ {"B0:DBG_MON_A6", 1},
+ {"B0:DBG_MON_A7", 1},
+ {"B0:DBG_MON_A8", 1},
+ {"B0:DBG_MON_A9", 1},
+ {"B0:DBG_MON_A10", 1},
+ {"B0:DBG_MON_A11", 1},
+ {"B0:DBG_MON_A12", 1},
+ {"B0:DBG_MON_A13", 1},
+ {"B0:DBG_MON_A14", 1},
+ {"B0:DBG_MON_A15", 1},
+ {"B0:DBG_MON_A16", 1},
+ {"B0:DBG_MON_A17", 1},
+ {"B0:DBG_MON_A18", 1},
+ {"B0:DBG_MON_A19", 1},
+ {"B0:DBG_MON_A20", 1},
+ {"B0:DBG_MON_A21", 1},
+ {"B0:DBG_MON_A22", 1},
+ {"B0:DBG_MON_A23", 1},
+ {"B0:DBG_MON_A24", 1},
+ {"B0:DBG_MON_A25", 1},
+ {"B0:DBG_MON_A26", 1},
+ {"B0:DBG_MON_A27", 1},
+ {"B0:DBG_MON_A28", 1},
+ {"B0:DBG_MON_A29", 1},
+ {"B0:DBG_MON_A30", 1},
+ {"B0:DBG_MON_A31", 1},
+ {"B0:DBG_MON_A32", 1},
+ {"B0:DBG_MON_B0", 1},
+ {"B0:DBG_MON_B1", 1},
+ {"B0:DBG_MON_B2", 1},
+ {"B0:DBG_MON_B3", 1},
+ {"B0:DBG_MON_B4", 1},
+ {"B0:DBG_MON_B5", 1},
+ {"B0:DBG_MON_B6", 1},
+ {"B0:DBG_MON_B7", 1},
+ {"B0:DBG_MON_B8", 1},
+ {"B0:DBG_MON_B9", 1},
+ {"B0:DBG_MON_B10", 1},
+ {"B0:DBG_MON_B11", 1},
+ {"B0:DBG_MON_B12", 1},
+ {"B0:DBG_MON_B13", 1},
+ {"B0:DBG_MON_B14", 1},
+ {"B0:DBG_MON_B15", 1},
+ {"B0:DBG_MON_B16", 1},
+ {"B0:DBG_MON_B17", 1},
+ {"B0:DBG_MON_B18", 1},
+ {"B0:DBG_MON_B19", 1},
+ {"B0:DBG_MON_B20", 1},
+ {"B0:DBG_MON_B21", 1},
+ {"B0:DBG_MON_B22", 1},
+ {"B0:DBG_MON_B23", 1},
+ {"B0:DBG_MON_B24", 1},
+ {"B0:DBG_MON_B25", 1},
+ {"B0:DBG_MON_B26", 1},
+ {"B0:DBG_MON_B27", 1},
+ {"B0:DBG_MON_B28", 1},
+ {"B0:DBG_MON_B29", 1},
+ {"B0:DBG_MON_B30", 1},
+ {"B0:DBG_MON_B31", 1},
+ {"B0:PCIE_CLKREQ_N", 0},
+ {"B1:PCIE_WAKE_N", 1},
+ {"B1:PCIE_PERST_N", 0},
+};
+#endif /* CONFIG_PINCTRL_MTK_DEBUG */
+
+#endif /* __PINCTRL-MTK-MT2731_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
new file mode 100644
index 0000000..17df4cf
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
@@ -0,0 +1,425 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PINCTRL_MTK_MT6397_H
+#define __PINCTRL_MTK_MT6397_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt6397[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "INT"),
+ "N2", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "SRCVOLTEN"),
+ "M4", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "SRCVOLTEN"),
+ MTK_FUNCTION(6, "TEST_CK1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "SRCLKEN_PERI"),
+ "M2", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "SRCLKEN_PERI"),
+ MTK_FUNCTION(6, "TEST_CK2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "RTC_32K1V8"),
+ "K3", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "RTC_32K1V8"),
+ MTK_FUNCTION(6, "TEST_CK3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "WRAP_EVENT"),
+ "J2", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "WRAP_EVENT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "SPI_CLK"),
+ "L4", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "SPI_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "SPI_CSN"),
+ "J3", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "SPI_CSN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "SPI_MOSI"),
+ "J1", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI_MOSI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "SPI_MISO"),
+ "L3", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "SPI_MISO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "AUD_CLK_MOSI"),
+ "H2", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "AUD_CLK"),
+ MTK_FUNCTION(6, "TEST_IN0"),
+ MTK_FUNCTION(7, "TEST_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "AUD_DAT_MISO"),
+ "H3", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "AUD_MISO"),
+ MTK_FUNCTION(6, "TEST_IN1"),
+ MTK_FUNCTION(7, "TEST_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "AUD_DAT_MOSI"),
+ "H1", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "AUD_MOSI"),
+ MTK_FUNCTION(6, "TEST_IN2"),
+ MTK_FUNCTION(7, "TEST_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "COL0"),
+ "F3", "mt6397",
+ MTK_EINT_FUNCTION(2, 10),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "COL0_USBDL"),
+ MTK_FUNCTION(2, "EINT10_1X"),
+ MTK_FUNCTION(3, "PWM1_3X"),
+ MTK_FUNCTION(6, "TEST_IN3"),
+ MTK_FUNCTION(7, "TEST_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "COL1"),
+ "G8", "mt6397",
+ MTK_EINT_FUNCTION(2, 11),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "COL1"),
+ MTK_FUNCTION(2, "EINT11_1X"),
+ MTK_FUNCTION(3, "SCL0_2X"),
+ MTK_FUNCTION(6, "TEST_IN4"),
+ MTK_FUNCTION(7, "TEST_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "COL2"),
+ "H4", "mt6397",
+ MTK_EINT_FUNCTION(2, 12),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "COL2"),
+ MTK_FUNCTION(2, "EINT12_1X"),
+ MTK_FUNCTION(3, "SDA0_2X"),
+ MTK_FUNCTION(6, "TEST_IN5"),
+ MTK_FUNCTION(7, "TEST_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "COL3"),
+ "G2", "mt6397",
+ MTK_EINT_FUNCTION(2, 13),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "COL3"),
+ MTK_FUNCTION(2, "EINT13_1X"),
+ MTK_FUNCTION(3, "SCL1_2X"),
+ MTK_FUNCTION(6, "TEST_IN6"),
+ MTK_FUNCTION(7, "TEST_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "COL4"),
+ "F2", "mt6397",
+ MTK_EINT_FUNCTION(2, 14),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "COL4"),
+ MTK_FUNCTION(2, "EINT14_1X"),
+ MTK_FUNCTION(3, "SDA1_2X"),
+ MTK_FUNCTION(6, "TEST_IN7"),
+ MTK_FUNCTION(7, "TEST_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "COL5"),
+ "G7", "mt6397",
+ MTK_EINT_FUNCTION(2, 15),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "COL5"),
+ MTK_FUNCTION(2, "EINT15_1X"),
+ MTK_FUNCTION(3, "SCL2_2X"),
+ MTK_FUNCTION(6, "TEST_IN8"),
+ MTK_FUNCTION(7, "TEST_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "COL6"),
+ "J6", "mt6397",
+ MTK_EINT_FUNCTION(2, 16),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "COL6"),
+ MTK_FUNCTION(2, "EINT16_1X"),
+ MTK_FUNCTION(3, "SDA2_2X"),
+ MTK_FUNCTION(4, "GPIO32K_0"),
+ MTK_FUNCTION(5, "GPIO26M_0"),
+ MTK_FUNCTION(6, "TEST_IN9"),
+ MTK_FUNCTION(7, "TEST_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "COL7"),
+ "J5", "mt6397",
+ MTK_EINT_FUNCTION(2, 17),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "COL7"),
+ MTK_FUNCTION(2, "EINT17_1X"),
+ MTK_FUNCTION(3, "PWM2_3X"),
+ MTK_FUNCTION(4, "GPIO32K_1"),
+ MTK_FUNCTION(5, "GPIO26M_1"),
+ MTK_FUNCTION(6, "TEST_IN10"),
+ MTK_FUNCTION(7, "TEST_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "ROW0"),
+ "L7", "mt6397",
+ MTK_EINT_FUNCTION(2, 18),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "ROW0"),
+ MTK_FUNCTION(2, "EINT18_1X"),
+ MTK_FUNCTION(3, "SCL0_3X"),
+ MTK_FUNCTION(6, "TEST_IN11"),
+ MTK_FUNCTION(7, "TEST_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "ROW1"),
+ "P1", "mt6397",
+ MTK_EINT_FUNCTION(2, 19),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "ROW1"),
+ MTK_FUNCTION(2, "EINT19_1X"),
+ MTK_FUNCTION(3, "SDA0_3X"),
+ MTK_FUNCTION(4, "AUD_TSTCK"),
+ MTK_FUNCTION(6, "TEST_IN12"),
+ MTK_FUNCTION(7, "TEST_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "ROW2"),
+ "J8", "mt6397",
+ MTK_EINT_FUNCTION(2, 20),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "ROW2"),
+ MTK_FUNCTION(2, "EINT20_1X"),
+ MTK_FUNCTION(3, "SCL1_3X"),
+ MTK_FUNCTION(6, "TEST_IN13"),
+ MTK_FUNCTION(7, "TEST_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "ROW3"),
+ "J7", "mt6397",
+ MTK_EINT_FUNCTION(2, 21),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "ROW3"),
+ MTK_FUNCTION(2, "EINT21_1X"),
+ MTK_FUNCTION(3, "SDA1_3X"),
+ MTK_FUNCTION(6, "TEST_IN14"),
+ MTK_FUNCTION(7, "TEST_OUT14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "ROW4"),
+ "L5", "mt6397",
+ MTK_EINT_FUNCTION(2, 22),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "ROW4"),
+ MTK_FUNCTION(2, "EINT22_1X"),
+ MTK_FUNCTION(3, "SCL2_3X"),
+ MTK_FUNCTION(6, "TEST_IN15"),
+ MTK_FUNCTION(7, "TEST_OUT15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "ROW5"),
+ "N6", "mt6397",
+ MTK_EINT_FUNCTION(2, 23),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "ROW5"),
+ MTK_FUNCTION(2, "EINT23_1X"),
+ MTK_FUNCTION(3, "SDA2_3X"),
+ MTK_FUNCTION(6, "TEST_IN16"),
+ MTK_FUNCTION(7, "TEST_OUT16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "ROW6"),
+ "L6", "mt6397",
+ MTK_EINT_FUNCTION(2, 24),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "ROW6"),
+ MTK_FUNCTION(2, "EINT24_1X"),
+ MTK_FUNCTION(3, "PWM3_3X"),
+ MTK_FUNCTION(4, "GPIO32K_2"),
+ MTK_FUNCTION(5, "GPIO26M_2"),
+ MTK_FUNCTION(6, "TEST_IN17"),
+ MTK_FUNCTION(7, "TEST_OUT17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "ROW7"),
+ "P2", "mt6397",
+ MTK_EINT_FUNCTION(2, 3),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "ROW7"),
+ MTK_FUNCTION(2, "EINT3_1X"),
+ MTK_FUNCTION(3, "CBUS"),
+ MTK_FUNCTION(4, "GPIO32K_3"),
+ MTK_FUNCTION(5, "GPIO26M_3"),
+ MTK_FUNCTION(6, "TEST_IN18"),
+ MTK_FUNCTION(7, "TEST_OUT18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "PWM1(VMSEL1)"),
+ "J4", "mt6397",
+ MTK_EINT_FUNCTION(2, 4),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "EINT4_1X"),
+ MTK_FUNCTION(4, "GPIO32K_4"),
+ MTK_FUNCTION(5, "GPIO26M_4"),
+ MTK_FUNCTION(6, "TEST_IN19"),
+ MTK_FUNCTION(7, "TEST_OUT19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "PWM2(VMSEL2)"),
+ "N5", "mt6397",
+ MTK_EINT_FUNCTION(2, 5),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "EINT5_1X"),
+ MTK_FUNCTION(4, "GPIO32K_5"),
+ MTK_FUNCTION(5, "GPIO26M_5"),
+ MTK_FUNCTION(6, "TEST_IN20"),
+ MTK_FUNCTION(7, "TEST_OUT20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "PWM3(PWM)"),
+ "R3", "mt6397",
+ MTK_EINT_FUNCTION(2, 6),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION(2, "EINT6_1X"),
+ MTK_FUNCTION(3, "COL0"),
+ MTK_FUNCTION(4, "GPIO32K_6"),
+ MTK_FUNCTION(5, "GPIO26M_6"),
+ MTK_FUNCTION(6, "TEST_IN21"),
+ MTK_FUNCTION(7, "TEST_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "SCL0"),
+ "N1", "mt6397",
+ MTK_EINT_FUNCTION(2, 7),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION(2, "EINT7_1X"),
+ MTK_FUNCTION(3, "PWM1_2X"),
+ MTK_FUNCTION(6, "TEST_IN22"),
+ MTK_FUNCTION(7, "TEST_OUT22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "SDA0"),
+ "N3", "mt6397",
+ MTK_EINT_FUNCTION(2, 8),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION(2, "EINT8_1X"),
+ MTK_FUNCTION(6, "TEST_IN23"),
+ MTK_FUNCTION(7, "TEST_OUT23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "SCL1"),
+ "T1", "mt6397",
+ MTK_EINT_FUNCTION(2, 9),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION(2, "EINT9_1X"),
+ MTK_FUNCTION(3, "PWM2_2X"),
+ MTK_FUNCTION(6, "TEST_IN24"),
+ MTK_FUNCTION(7, "TEST_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "SDA1"),
+ "T2", "mt6397",
+ MTK_EINT_FUNCTION(2, 0),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION(2, "EINT0_1X"),
+ MTK_FUNCTION(6, "TEST_IN25"),
+ MTK_FUNCTION(7, "TEST_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "SCL2"),
+ "T3", "mt6397",
+ MTK_EINT_FUNCTION(2, 1),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION(2, "EINT1_1X"),
+ MTK_FUNCTION(3, "PWM3_2X"),
+ MTK_FUNCTION(6, "TEST_IN26"),
+ MTK_FUNCTION(7, "TEST_OUT26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "SDA2"),
+ "U2", "mt6397",
+ MTK_EINT_FUNCTION(2, 2),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION(2, "EINT2_1X"),
+ MTK_FUNCTION(6, "TEST_IN27"),
+ MTK_FUNCTION(7, "TEST_OUT27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "HDMISD"),
+ "H6", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "HDMISD"),
+ MTK_FUNCTION(6, "TEST_IN28"),
+ MTK_FUNCTION(7, "TEST_OUT28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "HDMISCK"),
+ "H5", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "HDMISCK"),
+ MTK_FUNCTION(6, "TEST_IN29"),
+ MTK_FUNCTION(7, "TEST_OUT29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "HTPLG"),
+ "H7", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "HTPLG"),
+ MTK_FUNCTION(6, "TEST_IN30"),
+ MTK_FUNCTION(7, "TEST_OUT30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "CEC"),
+ "J9", "mt6397",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "CEC"),
+ MTK_FUNCTION(6, "TEST_IN31"),
+ MTK_FUNCTION(7, "TEST_OUT31")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT6397_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
new file mode 100644
index 0000000..850483d
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
@@ -0,0 +1,1319 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PINCTRL_MTK_MT8127_H
+#define __PINCTRL_MTK_MT8127_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt8127[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ "P22", "mt8127",
+ MTK_EINT_FUNCTION(0, 22),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ "M22", "mt8127",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "PWRAP_INT"),
+ "L23", "mt8127",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ "N23", "mt8127",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ "N22", "mt8127",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ "L19", "mt8127",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "VDEC_TEST_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ "M23", "mt8127",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "MM_TEST_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "AUD_CLK_MOSI"),
+ "K23", "mt8127",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "AUD_CLK"),
+ MTK_FUNCTION(2, "ADC_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "AUD_DAT_MISO"),
+ "K24", "mt8127",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "AUD_MISO"),
+ MTK_FUNCTION(2, "ADC_DAT_IN"),
+ MTK_FUNCTION(3, "AUD_MOSI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "AUD_DAT_MOSI"),
+ "K22", "mt8127",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "AUD_MOSI"),
+ MTK_FUNCTION(2, "ADC_WS"),
+ MTK_FUNCTION(3, "AUD_MISO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "RTC32K_CK"),
+ "R21", "mt8127",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "WATCHDOG"),
+ "P24", "mt8127",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "SRCLKENA"),
+ "R22", "mt8127",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "SRCLKENAI"),
+ "P23", "mt8127",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "URXD2"),
+ "U19", "mt8127",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "DPI_D5"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(5, "SRCCLKENAI2"),
+ MTK_FUNCTION(6, "KROW4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "UTXD2"),
+ "U20", "mt8127",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "DPI_HSYNC"),
+ MTK_FUNCTION(3, "URXD2"),
+ MTK_FUNCTION(6, "KROW5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "URXD3"),
+ "U18", "mt8127",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "DPI_DE"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "UCTS2"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "KROW6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "UTXD3"),
+ "R18", "mt8127",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "DPI_VSYNC"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "URTS2"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "KROW7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "PCM_CLK"),
+ "U22", "mt8127",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "PCM_CLK0"),
+ MTK_FUNCTION(2, "DPI_D4"),
+ MTK_FUNCTION(3, "I2SIN1_BCK0"),
+ MTK_FUNCTION(4, "I2SOUT_BCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "IR"),
+ MTK_FUNCTION(7, "DBG_MON_A[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "PCM_SYNC"),
+ "U23", "mt8127",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(2, "DPI_D3"),
+ MTK_FUNCTION(3, "I2SIN1_LRCK"),
+ MTK_FUNCTION(4, "I2SOUT_LRCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "EXT_COL"),
+ MTK_FUNCTION(7, "DBG_MON_A[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "PCM_RX"),
+ "V22", "mt8127",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "PCM_RX"),
+ MTK_FUNCTION(2, "DPI_D1"),
+ MTK_FUNCTION(3, "I2SIN1_DATA_IN"),
+ MTK_FUNCTION(4, "PCM_TX"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "EXT_MDIO"),
+ MTK_FUNCTION(7, "DBG_MON_A[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "PCM_TX"),
+ "U21", "mt8127",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "PCM_TX"),
+ MTK_FUNCTION(2, "DPI_D2"),
+ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(4, "PCM_RX"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "EXT_MDC"),
+ MTK_FUNCTION(7, "DBG_MON_A[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "EINT0"),
+ "AB19", "mt8127",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "DPI_CK"),
+ MTK_FUNCTION(4, "EXT_TXD0"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(7, "DBG_MON_A[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "EINT1"),
+ "AA21", "mt8127",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "DPI_D12"),
+ MTK_FUNCTION(4, "EXT_TXD1"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_A[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "EINT2"),
+ "AA19", "mt8127",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "CLKM0"),
+ MTK_FUNCTION(2, "DPI_D13"),
+ MTK_FUNCTION(4, "EXT_TXD2"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "KCOL4"),
+ MTK_FUNCTION(7, "DBG_MON_A[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "EINT3"),
+ "Y19", "mt8127",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "DPI_D14"),
+ MTK_FUNCTION(3, "SPI_MI"),
+ MTK_FUNCTION(4, "EXT_TXD3"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "KCOL5"),
+ MTK_FUNCTION(7, "DBG_MON_A[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "EINT4"),
+ "V21", "mt8127",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "DPI_D15"),
+ MTK_FUNCTION(3, "SPI_MO"),
+ MTK_FUNCTION(4, "EXT_TXC"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK0"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
+ MTK_FUNCTION(7, "DBG_MON_A[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "EINT5"),
+ "AB22", "mt8127",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "DPI_D16"),
+ MTK_FUNCTION(3, "SPI_CS"),
+ MTK_FUNCTION(4, "EXT_RXER"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "KCOL6"),
+ MTK_FUNCTION(7, "DBG_MON_A[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "EINT6"),
+ "AA23", "mt8127",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "DPI_D17"),
+ MTK_FUNCTION(3, "SPI_CK"),
+ MTK_FUNCTION(4, "EXT_RXC"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "KCOL7"),
+ MTK_FUNCTION(7, "DBG_MON_A[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "EINT7"),
+ "Y23", "mt8127",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "DPI_D6"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "EXT_RXDV"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
+ MTK_FUNCTION(7, "DBG_MON_A[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "EINT8"),
+ "Y24", "mt8127",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "EXT_RXD0"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(6, "DPI_D7"),
+ MTK_FUNCTION(7, "DBG_MON_B[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "EINT9"),
+ "W23", "mt8127",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "CLKM4"),
+ MTK_FUNCTION(2, "SDA2"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "EXT_RXD1"),
+ MTK_FUNCTION(5, "ANT_SEL1"),
+ MTK_FUNCTION(6, "DPI_D8"),
+ MTK_FUNCTION(7, "DBG_MON_B[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "EINT10"),
+ "W24", "mt8127",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "CLKM5"),
+ MTK_FUNCTION(2, "SCL2"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "EXT_RXD2"),
+ MTK_FUNCTION(5, "ANT_SEL2"),
+ MTK_FUNCTION(6, "DPI_D9"),
+ MTK_FUNCTION(7, "DBG_MON_B[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "KPROW0"),
+ "AB24", "mt8127",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "KROW0"),
+ MTK_FUNCTION(4, "IMG_TEST_CK"),
+ MTK_FUNCTION(7, "DBG_MON_A[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "KPROW1"),
+ "AC24", "mt8127",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "KROW1"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "MFG_TEST_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "KPROW2"),
+ "AD24", "mt8127",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "KROW2"),
+ MTK_FUNCTION(2, "DRV_VBUS"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "CONN_TEST_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "KPCOL0"),
+ "AB23", "mt8127",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "KCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_A[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "KPCOL1"),
+ "AC22", "mt8127",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "KCOL1"),
+ MTK_FUNCTION(7, "DBG_MON_B[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "KPCOL2"),
+ "AC23", "mt8127",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "KCOL2"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_B[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "JTMS"),
+ "V18", "mt8127",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "CONN_MCU_TMS"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "JTCK"),
+ "AA18", "mt8127",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "CONN_MCU_TCK1"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "JTDI"),
+ "W18", "mt8127",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "CONN_MCU_TDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "JTDO"),
+ "Y18", "mt8127",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "CONN_MCU_TDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "EINT11"),
+ "W22", "mt8127",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "CLKM4"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "KROW3"),
+ MTK_FUNCTION(4, "ANT_SEL3"),
+ MTK_FUNCTION(5, "DPI_D10"),
+ MTK_FUNCTION(6, "EXT_RXD3"),
+ MTK_FUNCTION(7, "DBG_MON_B[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "EINT12"),
+ "V23", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "CLKM5"),
+ MTK_FUNCTION(2, "PWM0"),
+ MTK_FUNCTION(3, "KCOL3"),
+ MTK_FUNCTION(4, "ANT_SEL4"),
+ MTK_FUNCTION(5, "DPI_D11"),
+ MTK_FUNCTION(6, "EXT_TXEN"),
+ MTK_FUNCTION(7, "DBG_MON_B[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "EINT13"),
+ "Y21", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(4, "ANT_SEL5"),
+ MTK_FUNCTION(5, "DPI_D0"),
+ MTK_FUNCTION(6, "SPDIF"),
+ MTK_FUNCTION(7, "DBG_MON_B[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "EINT14"),
+ "F23", "mt8127",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(2, "DAC_DAT_OUT"),
+ MTK_FUNCTION(4, "ANT_SEL1"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "NCLE"),
+ MTK_FUNCTION(7, "DBG_MON_A[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "EINT15"),
+ "G23", "mt8127",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(2, "DAC_WS"),
+ MTK_FUNCTION(4, "ANT_SEL2"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "NCEB1"),
+ MTK_FUNCTION(7, "DBG_MON_A[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "EINT16"),
+ "H23", "mt8127",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(2, "DAC_CK"),
+ MTK_FUNCTION(4, "ANT_SEL3"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "NCEB0"),
+ MTK_FUNCTION(7, "DBG_MON_A[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "EINT17"),
+ "J22", "mt8127",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "UCTS0"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "IDDIG"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "NREB"),
+ MTK_FUNCTION(7, "DBG_MON_A[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "EINT18"),
+ "AD20", "mt8127",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "URTS0"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "I2SOUT_LRCK"),
+ MTK_FUNCTION(4, "DRV_VBUS"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "ADC_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "EINT19"),
+ "AC21", "mt8127",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION(3, "I2SOUT_BCK"),
+ MTK_FUNCTION(4, "CLKM1"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "ADC_DAT_IN"),
+ MTK_FUNCTION(7, "DBG_MON_B[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "EINT20"),
+ "V20", "mt8127",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION(2, "PCM_TX"),
+ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "ADC_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "SPI_CS"),
+ "AD19", "mt8127",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI_CS"),
+ MTK_FUNCTION(3, "I2SIN1_DATA_IN"),
+ MTK_FUNCTION(4, "ADC_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "SPI_CK"),
+ "AC18", "mt8127",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI_CK"),
+ MTK_FUNCTION(3, "I2SIN1_LRCK"),
+ MTK_FUNCTION(4, "ADC_DAT_IN"),
+ MTK_FUNCTION(7, "DBG_MON_B[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "SPI_MI"),
+ "AC19", "mt8127",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI_MI"),
+ MTK_FUNCTION(2, "SPI_MO"),
+ MTK_FUNCTION(3, "I2SIN1_BCK1"),
+ MTK_FUNCTION(4, "ADC_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "SPI_MO"),
+ "AD18", "mt8127",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SPI_MO"),
+ MTK_FUNCTION(2, "SPI_MI"),
+ MTK_FUNCTION(7, "DBG_MON_B[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "SDA1"),
+ "AE23", "mt8127",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "SCL1"),
+ "AD23", "mt8127",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "DISP_PWM"),
+ "AC20", "mt8127",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_A[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "WB_RSTB"),
+ "AD7", "mt8127",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "WB_RSTB"),
+ MTK_FUNCTION(7, "DBG_MON_A[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "F2W_DATA"),
+ "Y10", "mt8127",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "F2W_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "F2W_CLK"),
+ "W10", "mt8127",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "F2W_CK"),
+ MTK_FUNCTION(7, "DBG_MON_A[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "WB_SCLK"),
+ "AB7", "mt8127",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "WB_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "WB_SDATA"),
+ "AA7", "mt8127",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "WB_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "WB_SEN"),
+ "Y7", "mt8127",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "WB_SEN"),
+ MTK_FUNCTION(7, "DBG_MON_A[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "WB_CRTL0"),
+ "AA1", "mt8127",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "WB_CRTL0"),
+ MTK_FUNCTION(2, "DFD_NTRST_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "WB_CRTL1"),
+ "AA2", "mt8127",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "WB_CRTL1"),
+ MTK_FUNCTION(2, "DFD_TMS_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "WB_CRTL2"),
+ "Y1", "mt8127",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "WB_CRTL2"),
+ MTK_FUNCTION(2, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "WB_CRTL3"),
+ "Y2", "mt8127",
+ MTK_EINT_FUNCTION(0, 70),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "WB_CRTL3"),
+ MTK_FUNCTION(2, "DFD_TDI_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "WB_CRTL4"),
+ "Y3", "mt8127",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "WB_CRTL4"),
+ MTK_FUNCTION(2, "DFD_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_A[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "WB_CRTL5"),
+ "Y4", "mt8127",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "WB_CRTL5"),
+ MTK_FUNCTION(7, "DBG_MON_A[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "I2S_DATA_IN"),
+ "K21", "mt8127",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "I2SIN1_DATA_IN"),
+ MTK_FUNCTION(2, "PCM_RX"),
+ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PWM0"),
+ MTK_FUNCTION(6, "ADC_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "I2S_LRCK"),
+ "L21", "mt8127",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "I2SIN1_LRCK"),
+ MTK_FUNCTION(2, "PCM_SYNC"),
+ MTK_FUNCTION(3, "I2SOUT_LRCK"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "ADC_DAT_IN"),
+ MTK_FUNCTION(7, "DBG_MON_B[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "I2S_BCK"),
+ "L20", "mt8127",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "I2SIN1_BCK2"),
+ MTK_FUNCTION(2, "PCM_CLK1"),
+ MTK_FUNCTION(3, "I2SOUT_BCK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "ADC_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "SDA0"),
+ "W3", "mt8127",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "SCL0"),
+ "W4", "mt8127",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "SDA2"),
+ "K19", "mt8127",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION(2, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "SCL2"),
+ "K20", "mt8127",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION(2, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "URXD0"),
+ "K18", "mt8127",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "UTXD0"),
+ "K17", "mt8127",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "URXD1"),
+ "L17", "mt8127",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "UTXD1"),
+ "L18", "mt8127",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "LCM_RST"),
+ "W5", "mt8127",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "LCM_RST"),
+ MTK_FUNCTION(2, "VDAC_CK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "DSI_TE"),
+ "W6", "mt8127",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "DSI_TE"),
+ MTK_FUNCTION(7, "DBG_MON_A[32]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC2_CMD"),
+ "U7", "mt8127",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC2_CLK"),
+ "T8", "mt8127",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC2_DAT0"),
+ "V3", "mt8127",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_B[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC2_DAT1"),
+ "V4", "mt8127",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_B[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC2_DAT2"),
+ "U5", "mt8127",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2"),
+ MTK_FUNCTION(7, "DBG_MON_B[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC2_DAT3"),
+ "U6", "mt8127",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3"),
+ MTK_FUNCTION(7, "DBG_MON_B[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "TDN3"),
+ "U2", "mt8127",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPI91"),
+ MTK_FUNCTION(1, "TDN3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "TDP3"),
+ "U1", "mt8127",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPI92"),
+ MTK_FUNCTION(1, "TDP3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "TDN2"),
+ "T2", "mt8127",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPI93"),
+ MTK_FUNCTION(1, "TDN2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "TDP2"),
+ "T1", "mt8127",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPI94"),
+ MTK_FUNCTION(1, "TDP2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "TCN"),
+ "R5", "mt8127",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPI95"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "TCP"),
+ "R4", "mt8127",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPI96"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "TDN1"),
+ "R3", "mt8127",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPI97"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "TDP1"),
+ "R2", "mt8127",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPI98"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "TDN0"),
+ "P3", "mt8127",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPI99"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "TDP0"),
+ "P2", "mt8127",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPI100"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "RDN0"),
+ "K1", "mt8127",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPI101"),
+ MTK_FUNCTION(1, "RDN0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "RDP0"),
+ "K2", "mt8127",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPI102"),
+ MTK_FUNCTION(1, "RDP0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "RDN1"),
+ "L2", "mt8127",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPI103"),
+ MTK_FUNCTION(1, "RDN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "RDP1"),
+ "L3", "mt8127",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPI104"),
+ MTK_FUNCTION(1, "RDP1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "RCN"),
+ "M4", "mt8127",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPI105"),
+ MTK_FUNCTION(1, "RCN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "RCP"),
+ "M5", "mt8127",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPI106"),
+ MTK_FUNCTION(1, "RCP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "RDN2"),
+ "M2", "mt8127",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPI107"),
+ MTK_FUNCTION(1, "RDN2"),
+ MTK_FUNCTION(2, "CMDAT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "RDP2"),
+ "M3", "mt8127",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPI108"),
+ MTK_FUNCTION(1, "RDP2"),
+ MTK_FUNCTION(2, "CMDAT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "RDN3"),
+ "N2", "mt8127",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPI109"),
+ MTK_FUNCTION(1, "RDN3"),
+ MTK_FUNCTION(2, "CMDAT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "RDP3"),
+ "N3", "mt8127",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPI110"),
+ MTK_FUNCTION(1, "RDP3"),
+ MTK_FUNCTION(2, "CMDAT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "RCN_A"),
+ "J5", "mt8127",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPI111"),
+ MTK_FUNCTION(1, "RCN_A"),
+ MTK_FUNCTION(2, "CMDAT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "RCP_A"),
+ "J4", "mt8127",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPI112"),
+ MTK_FUNCTION(1, "RCP_A"),
+ MTK_FUNCTION(2, "CMDAT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "RDN1_A"),
+ "J2", "mt8127",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPI113"),
+ MTK_FUNCTION(1, "RDN1_A"),
+ MTK_FUNCTION(2, "CMDAT2"),
+ MTK_FUNCTION(3, "CMCSD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "RDP1_A"),
+ "J3", "mt8127",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPI114"),
+ MTK_FUNCTION(1, "RDP1_A"),
+ MTK_FUNCTION(2, "CMDAT3"),
+ MTK_FUNCTION(3, "CMCSD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "RDN0_A"),
+ "H2", "mt8127",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPI115"),
+ MTK_FUNCTION(1, "RDN0_A"),
+ MTK_FUNCTION(2, "CMHSYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "RDP0_A"),
+ "H3", "mt8127",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPI116"),
+ MTK_FUNCTION(1, "RDP0_A"),
+ MTK_FUNCTION(2, "CMVSYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "CMDAT0"),
+ "G5", "mt8127",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION(2, "CMCSD0"),
+ MTK_FUNCTION(3, "ANT_SEL2"),
+ MTK_FUNCTION(7, "DBG_MON_B[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "CMDAT1"),
+ "G4", "mt8127",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION(2, "CMCSD1"),
+ MTK_FUNCTION(3, "ANT_SEL3"),
+ MTK_FUNCTION(7, "DBG_MON_B[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "CMMCLK"),
+ "F3", "mt8127",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION(3, "ANT_SEL4"),
+ MTK_FUNCTION(7, "DBG_MON_B[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "CMPCLK"),
+ "G6", "mt8127",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION(2, "CMCSK"),
+ MTK_FUNCTION(3, "ANT_SEL5"),
+ MTK_FUNCTION(7, "DBG_MON_B[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "MSDC1_CMD"),
+ "E3", "mt8127",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "MSDC1_CMD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "MSDC1_CLK"),
+ "D1", "mt8127",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "MSDC1_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "MSDC1_DAT0"),
+ "D2", "mt8127",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "MSDC1_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "MSDC1_DAT1"),
+ "D3", "mt8127",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "MSDC1_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "MSDC1_DAT2"),
+ "F2", "mt8127",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "MSDC1_DAT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "MSDC1_DAT3"),
+ "E2", "mt8127",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "MSDC1_DAT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "MSDC0_DAT7"),
+ "C23", "mt8127",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(4, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "MSDC0_DAT6"),
+ "C24", "mt8127",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(4, "NLD6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "MSDC0_DAT5"),
+ "D22", "mt8127",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(4, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "MSDC0_DAT4"),
+ "D24", "mt8127",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(4, "NLD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "MSDC0_RSTB"),
+ "F24", "mt8127",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(4, "NLD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "MSDC0_CMD"),
+ "G20", "mt8127",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(4, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "MSDC0_CLK"),
+ "G21", "mt8127",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(4, "NWEB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "MSDC0_DAT3"),
+ "D23", "mt8127",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(4, "NLD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "MSDC0_DAT2"),
+ "E22", "mt8127",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(4, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "MSDC0_DAT1"),
+ "E23", "mt8127",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(4, "NLD8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "MSDC0_DAT0"),
+ "F22", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(4, "WATCHDOG"),
+ MTK_FUNCTION(5, "NLD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "CEC"),
+ "AE21", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "CEC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "HTPLG"),
+ "AD21", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "HTPLG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "HDMISCK"),
+ "AE22", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "HDMISCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "HDMISD"),
+ "AD22", "mt8127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "HDMISD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "EINT21"),
+ "J23", "mt8127",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(7, "DBG_MON_B[32]")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT8127_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
new file mode 100644
index 0000000..e17aedb
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
@@ -0,0 +1,2114 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT8135_H
+#define __PINCTRL_MTK_MT8135_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt8135[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "MSDC0_DAT7"),
+ "D21", "mt8135",
+ MTK_EINT_FUNCTION(2, 49),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(2, "EINT49"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "SPI1_MO"),
+ MTK_FUNCTION(7, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "MSDC0_DAT6"),
+ "D22", "mt8135",
+ MTK_EINT_FUNCTION(2, 48),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(2, "EINT48"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "SPI1_CSN"),
+ MTK_FUNCTION(7, "NCLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "MSDC0_DAT5"),
+ "E22", "mt8135",
+ MTK_EINT_FUNCTION(2, 47),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(2, "EINT47"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "SPI1_CLK"),
+ MTK_FUNCTION(7, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "MSDC0_DAT4"),
+ "F21", "mt8135",
+ MTK_EINT_FUNCTION(2, 46),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(2, "EINT46"),
+ MTK_FUNCTION(3, "A_FUNC_CK"),
+ MTK_FUNCTION(6, "LSCE1B_2X"),
+ MTK_FUNCTION(7, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "MSDC0_CMD"),
+ "F20", "mt8135",
+ MTK_EINT_FUNCTION(2, 41),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(2, "EINT41"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[0]"),
+ MTK_FUNCTION(5, "USB_TEST_IO[0]"),
+ MTK_FUNCTION(6, "LRSTB_2X"),
+ MTK_FUNCTION(7, "NRNB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "MSDC0_CLK"),
+ "G18", "mt8135",
+ MTK_EINT_FUNCTION(2, 40),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(2, "EINT40"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[1]"),
+ MTK_FUNCTION(5, "USB_TEST_IO[1]"),
+ MTK_FUNCTION(6, "LPTE"),
+ MTK_FUNCTION(7, "NREB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "MSDC0_DAT3"),
+ "G21", "mt8135",
+ MTK_EINT_FUNCTION(2, 45),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(2, "EINT45"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[2]"),
+ MTK_FUNCTION(5, "USB_TEST_IO[2]"),
+ MTK_FUNCTION(6, "LSCE0B_2X"),
+ MTK_FUNCTION(7, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "MSDC0_DAT2"),
+ "E21", "mt8135",
+ MTK_EINT_FUNCTION(2, 44),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(2, "EINT44"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[3]"),
+ MTK_FUNCTION(5, "USB_TEST_IO[3]"),
+ MTK_FUNCTION(6, "LSA0_2X"),
+ MTK_FUNCTION(7, "NLD14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "MSDC0_DAT1"),
+ "E23", "mt8135",
+ MTK_EINT_FUNCTION(2, 43),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(2, "EINT43"),
+ MTK_FUNCTION(5, "USB_TEST_IO[4]"),
+ MTK_FUNCTION(6, "LSCK_2X"),
+ MTK_FUNCTION(7, "NLD11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "MSDC0_DAT0"),
+ "F22", "mt8135",
+ MTK_EINT_FUNCTION(2, 42),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(2, "EINT42"),
+ MTK_FUNCTION(5, "USB_TEST_IO[5]"),
+ MTK_FUNCTION(6, "LSDA_2X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "NCEB0"),
+ "G20", "mt8135",
+ MTK_EINT_FUNCTION(2, 139),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION(2, "EINT139"),
+ MTK_FUNCTION(7, "TESTA_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "NCEB1"),
+ "L17", "mt8135",
+ MTK_EINT_FUNCTION(2, 140),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION(2, "EINT140"),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "TESTA_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "NRNB"),
+ "G19", "mt8135",
+ MTK_EINT_FUNCTION(2, 141),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION(2, "EINT141"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[4]"),
+ MTK_FUNCTION(7, "TESTA_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "NCLE"),
+ "J18", "mt8135",
+ MTK_EINT_FUNCTION(2, 142),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION(2, "EINT142"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[5]"),
+ MTK_FUNCTION(4, "CM2PDN_1X"),
+ MTK_FUNCTION(6, "NALE"),
+ MTK_FUNCTION(7, "TESTA_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "NALE"),
+ "J19", "mt8135",
+ MTK_EINT_FUNCTION(2, 143),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "NALE"),
+ MTK_FUNCTION(2, "EINT143"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[6]"),
+ MTK_FUNCTION(4, "CM2MCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_RXD"),
+ MTK_FUNCTION(6, "NCLE"),
+ MTK_FUNCTION(7, "TESTA_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "NREB"),
+ "L18", "mt8135",
+ MTK_EINT_FUNCTION(2, 144),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION(2, "EINT144"),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[7]"),
+ MTK_FUNCTION(4, "CM2RST_1X"),
+ MTK_FUNCTION(5, "IRDA_TXD"),
+ MTK_FUNCTION(7, "TESTA_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "NWEB"),
+ "J20", "mt8135",
+ MTK_EINT_FUNCTION(2, 145),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "NWEB"),
+ MTK_FUNCTION(2, "EINT145"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[0]"),
+ MTK_FUNCTION(4, "CM2PCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_PDN"),
+ MTK_FUNCTION(7, "TESTA_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "NLD0"),
+ "K21", "mt8135",
+ MTK_EINT_FUNCTION(2, 146),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "NLD0"),
+ MTK_FUNCTION(2, "EINT146"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[1]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[0]"),
+ MTK_FUNCTION(5, "I2SIN_CK"),
+ MTK_FUNCTION(6, "DAC_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "NLD1"),
+ "K22", "mt8135",
+ MTK_EINT_FUNCTION(2, 147),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "NLD1"),
+ MTK_FUNCTION(2, "EINT147"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[2]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[1]"),
+ MTK_FUNCTION(5, "I2SIN_WS"),
+ MTK_FUNCTION(6, "DAC_WS"),
+ MTK_FUNCTION(7, "TESTA_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "NLD2"),
+ "J21", "mt8135",
+ MTK_EINT_FUNCTION(2, 148),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "NLD2"),
+ MTK_FUNCTION(2, "EINT148"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[3]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[2]"),
+ MTK_FUNCTION(5, "I2SOUT_DAT"),
+ MTK_FUNCTION(6, "DAC_DAT_OUT"),
+ MTK_FUNCTION(7, "TESTA_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "NLD3"),
+ "J23", "mt8135",
+ MTK_EINT_FUNCTION(2, 149),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "NLD3"),
+ MTK_FUNCTION(2, "EINT149"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[4]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[3]"),
+ MTK_FUNCTION(7, "TESTA_OUT14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "NLD4"),
+ "J22", "mt8135",
+ MTK_EINT_FUNCTION(2, 150),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "NLD4"),
+ MTK_FUNCTION(2, "EINT150"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[5]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[4]"),
+ MTK_FUNCTION(7, "TESTA_OUT15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "NLD5"),
+ "H21", "mt8135",
+ MTK_EINT_FUNCTION(2, 151),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "NLD5"),
+ MTK_FUNCTION(2, "EINT151"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[6]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[5]"),
+ MTK_FUNCTION(7, "TESTA_OUT16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "NLD6"),
+ "H22", "mt8135",
+ MTK_EINT_FUNCTION(2, 152),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "NLD6"),
+ MTK_FUNCTION(2, "EINT152"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[7]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[6]"),
+ MTK_FUNCTION(7, "TESTA_OUT17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "NLD7"),
+ "H20", "mt8135",
+ MTK_EINT_FUNCTION(2, 153),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "NLD7"),
+ MTK_FUNCTION(2, "EINT153"),
+ MTK_FUNCTION(3, "A_FUNC_DIN[8]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[7]"),
+ MTK_FUNCTION(7, "TESTA_OUT18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "NLD8"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 154),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "NLD8"),
+ MTK_FUNCTION(2, "EINT154"),
+ MTK_FUNCTION(4, "CM2DAT_1X[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "NLD9"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 155),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "NLD9"),
+ MTK_FUNCTION(2, "EINT155"),
+ MTK_FUNCTION(4, "CM2DAT_1X[9]"),
+ MTK_FUNCTION(5, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "NLD10"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 156),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "NLD10"),
+ MTK_FUNCTION(2, "EINT156"),
+ MTK_FUNCTION(4, "CM2VSYNC_1X"),
+ MTK_FUNCTION(5, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "NLD11"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 157),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "NLD11"),
+ MTK_FUNCTION(2, "EINT157"),
+ MTK_FUNCTION(4, "CM2HSYNC_1X"),
+ MTK_FUNCTION(5, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "NLD12"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 158),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "NLD12"),
+ MTK_FUNCTION(2, "EINT158"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "NLD13"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 159),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "NLD13"),
+ MTK_FUNCTION(2, "EINT159"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "NLD14"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 160),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "NLD14"),
+ MTK_FUNCTION(2, "EINT160"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "NLD15"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 161),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "NLD15"),
+ MTK_FUNCTION(2, "EINT161"),
+ MTK_FUNCTION(3, "DISP_PWM"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "PCM1_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "MSDC0_RSTB"),
+ "G22", "mt8135",
+ MTK_EINT_FUNCTION(2, 50),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(2, "EINT50"),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "SPI1_MI"),
+ MTK_FUNCTION(7, "NLD10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "IDDIG"),
+ "N17", "mt8135",
+ MTK_EINT_FUNCTION(2, 34),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "EINT34")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "SCL3"),
+ "L19", "mt8135",
+ MTK_EINT_FUNCTION(2, 96),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(2, "EINT96"),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "PWM6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "SDA3"),
+ "L20", "mt8135",
+ MTK_EINT_FUNCTION(2, 97),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(2, "EINT97")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "AUD_CLK_MOSI"),
+ "L21", "mt8135",
+ MTK_EINT_FUNCTION(4, 19),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "AUD_CLK"),
+ MTK_FUNCTION(2, "ADC_CK"),
+ MTK_FUNCTION(3, " HDMI_SDATA0"),
+ MTK_FUNCTION(4, "EINT19"),
+ MTK_FUNCTION(5, "USB_TEST_IO[6]"),
+ MTK_FUNCTION(7, "TESTA_OUT19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "AUD_DAT_MOSI"),
+ "L23", "mt8135",
+ MTK_EINT_FUNCTION(4, 21),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(2, "ADC_WS"),
+ MTK_FUNCTION(3, "AUD_DAT_MISO"),
+ MTK_FUNCTION(4, "EINT21"),
+ MTK_FUNCTION(5, "USB_TEST_IO[7]"),
+ MTK_FUNCTION(7, "TESTA_OUT20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "AUD_DAT_MISO"),
+ "L22", "mt8135",
+ MTK_EINT_FUNCTION(4, 20),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(2, "ADC_DAT_IN"),
+ MTK_FUNCTION(3, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(4, "EINT20"),
+ MTK_FUNCTION(5, "USB_TEST_IO[8]"),
+ MTK_FUNCTION(7, "TESTA_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "DAC_CLK"),
+ "P21", "mt8135",
+ MTK_EINT_FUNCTION(2, 22),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "DAC_CK"),
+ MTK_FUNCTION(2, "EINT22"),
+ MTK_FUNCTION(3, " HDMI_SDATA1"),
+ MTK_FUNCTION(5, "USB_TEST_IO[9]"),
+ MTK_FUNCTION(7, "TESTA_OUT22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "DAC_WS"),
+ "N18", "mt8135",
+ MTK_EINT_FUNCTION(2, 24),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "DAC_WS"),
+ MTK_FUNCTION(2, "EINT24"),
+ MTK_FUNCTION(3, " HDMI_SDATA2"),
+ MTK_FUNCTION(5, "USB_TEST_IO[10]"),
+ MTK_FUNCTION(7, "TESTA_OUT23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "DAC_DAT_OUT"),
+ "N22", "mt8135",
+ MTK_EINT_FUNCTION(2, 23),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DAC_DAT_OUT"),
+ MTK_FUNCTION(2, "EINT23"),
+ MTK_FUNCTION(3, " HDMI_SDATA3"),
+ MTK_FUNCTION(5, "USB_TEST_IO[11]"),
+ MTK_FUNCTION(7, "TESTA_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
+ "M22", "mt8135",
+ MTK_EINT_FUNCTION(2, 29),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "EINT29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
+ "P23", "mt8135",
+ MTK_EINT_FUNCTION(2, 28),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "EINT28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
+ "M21", "mt8135",
+ MTK_EINT_FUNCTION(2, 27),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I"),
+ MTK_FUNCTION(2, "EINT27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
+ "P22", "mt8135",
+ MTK_EINT_FUNCTION(2, 26),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I"),
+ MTK_FUNCTION(2, "EINT26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "PWRAP_EVENT"),
+ "M23", "mt8135",
+ MTK_EINT_FUNCTION(2, 25),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "PWRAP_EVENT_IN"),
+ MTK_FUNCTION(2, "EINT25"),
+ MTK_FUNCTION(7, "TESTA_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "RTC32K_CK"),
+ "N20", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "WATCHDOG"),
+ "R22", "mt8135",
+ MTK_EINT_FUNCTION(2, 36),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "WATCHDOG"),
+ MTK_FUNCTION(2, "EINT36")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "SRCLKENA"),
+ "T22", "mt8135",
+ MTK_EINT_FUNCTION(2, 38),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SRCLKENA"),
+ MTK_FUNCTION(2, "EINT38")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "SRCVOLTEN"),
+ "T23", "mt8135",
+ MTK_EINT_FUNCTION(2, 37),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SRCVOLTEN"),
+ MTK_FUNCTION(2, "EINT37")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "EINT0"),
+ "T21", "mt8135",
+ MTK_EINT_FUNCTION(1, 0),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "EINT0"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, " SPDIF_OUT"),
+ MTK_FUNCTION(5, "USB_TEST_IO[12]"),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "URXD2"),
+ "R18", "mt8135",
+ MTK_EINT_FUNCTION(2, 83),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "EINT83"),
+ MTK_FUNCTION(4, " HDMI_LRCK"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(7, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "UTXD2"),
+ "R17", "mt8135",
+ MTK_EINT_FUNCTION(2, 82),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "EINT82"),
+ MTK_FUNCTION(4, " HDMI_BCK_OUT"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(7, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "UCTS2"),
+ "R20", "mt8135",
+ MTK_EINT_FUNCTION(2, 84),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "EINT84"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(7, "URTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "URTS2"),
+ "R19", "mt8135",
+ MTK_EINT_FUNCTION(2, 85),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "EINT85"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(7, "UCTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "JTCK"),
+ "V17", "mt8135",
+ MTK_EINT_FUNCTION(2, 188),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "EINT188"),
+ MTK_FUNCTION(3, "DSP1_ICK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "JTDO"),
+ "T16", "mt8135",
+ MTK_EINT_FUNCTION(2, 190),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "EINT190"),
+ MTK_FUNCTION(3, "DSP2_IMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "JTRST_B"),
+ "T19", "mt8135",
+ MTK_EINT_FUNCTION(2, 0),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "JTRST_B"),
+ MTK_FUNCTION(2, "EINT0"),
+ MTK_FUNCTION(3, "DSP2_ICK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "JTDI"),
+ "T18", "mt8135",
+ MTK_EINT_FUNCTION(2, 189),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "EINT189"),
+ MTK_FUNCTION(3, "DSP1_IMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "JRTCK"),
+ "T20", "mt8135",
+ MTK_EINT_FUNCTION(2, 187),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "JRTCK"),
+ MTK_FUNCTION(2, "EINT187"),
+ MTK_FUNCTION(3, "DSP1_ID")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "JTMS"),
+ "T17", "mt8135",
+ MTK_EINT_FUNCTION(2, 191),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "EINT191"),
+ MTK_FUNCTION(3, "DSP2_ID")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "MSDC1_INSI"),
+ "V18", "mt8135",
+ MTK_EINT_FUNCTION(1, 15),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MSDC1_INSI"),
+ MTK_FUNCTION(3, "SCL5"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(7, "TESTB_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "MSDC1_SDWPI"),
+ "W18", "mt8135",
+ MTK_EINT_FUNCTION(2, 58),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MSDC1_SDWPI"),
+ MTK_FUNCTION(2, "EINT58"),
+ MTK_FUNCTION(3, "SDA5"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(5, "CLKM6"),
+ MTK_FUNCTION(7, "TESTB_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "MSDC2_INSI"),
+ "U22", "mt8135",
+ MTK_EINT_FUNCTION(1, 14),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MSDC2_INSI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[27]"),
+ MTK_FUNCTION(7, "TESTA_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "MSDC2_SDWPI"),
+ "U21", "mt8135",
+ MTK_EINT_FUNCTION(2, 66),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MSDC2_SDWPI"),
+ MTK_FUNCTION(2, "EINT66"),
+ MTK_FUNCTION(5, "USB_TEST_IO[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "URXD4"),
+ "V23", "mt8135",
+ MTK_EINT_FUNCTION(2, 89),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "URXD4"),
+ MTK_FUNCTION(2, "EINT89"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(6, "UTXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "UTXD4"),
+ "V22", "mt8135",
+ MTK_EINT_FUNCTION(2, 88),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "UTXD4"),
+ MTK_FUNCTION(2, "EINT88"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(6, "URXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "URXD1"),
+ "W22", "mt8135",
+ MTK_EINT_FUNCTION(2, 79),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "EINT79"),
+ MTK_FUNCTION(3, "URXD4"),
+ MTK_FUNCTION(6, "UTXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "UTXD1"),
+ "V21", "mt8135",
+ MTK_EINT_FUNCTION(2, 78),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "EINT78"),
+ MTK_FUNCTION(3, "UTXD4"),
+ MTK_FUNCTION(6, "URXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "UCTS1"),
+ "V19", "mt8135",
+ MTK_EINT_FUNCTION(2, 80),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION(2, "EINT80"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, "URTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "URTS1"),
+ "V20", "mt8135",
+ MTK_EINT_FUNCTION(2, 81),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION(2, "EINT81"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "UCTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "PWM1"),
+ "W17", "mt8135",
+ MTK_EINT_FUNCTION(2, 73),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "EINT73"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "PWM2"),
+ "Y17", "mt8135",
+ MTK_EINT_FUNCTION(2, 74),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "EINT74"),
+ MTK_FUNCTION(3, "DPI33_CK"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "URXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "PWM3"),
+ "Y19", "mt8135",
+ MTK_EINT_FUNCTION(2, 75),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION(2, "EINT75"),
+ MTK_FUNCTION(3, "DPI33_D0"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "UTXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "PWM4"),
+ "W19", "mt8135",
+ MTK_EINT_FUNCTION(2, 76),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION(2, "EINT76"),
+ MTK_FUNCTION(3, "DPI33_D1"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "MSDC2_DAT2"),
+ "W21", "mt8135",
+ MTK_EINT_FUNCTION(2, 63),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(2, "EINT63"),
+ MTK_FUNCTION(4, "DSP2_IMS"),
+ MTK_FUNCTION(6, "DPI33_D6"),
+ MTK_FUNCTION(7, "TESTA_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "MSDC2_DAT3"),
+ "AA23", "mt8135",
+ MTK_EINT_FUNCTION(2, 64),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(2, "EINT64"),
+ MTK_FUNCTION(4, "DSP2_ID"),
+ MTK_FUNCTION(6, "DPI33_D7"),
+ MTK_FUNCTION(7, "TESTA_OUT26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "MSDC2_CMD"),
+ "Y22", "mt8135",
+ MTK_EINT_FUNCTION(2, 60),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(2, "EINT60"),
+ MTK_FUNCTION(4, "DSP1_IMS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "DPI33_D3"),
+ MTK_FUNCTION(7, "TESTA_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "MSDC2_CLK"),
+ "AA22", "mt8135",
+ MTK_EINT_FUNCTION(2, 59),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(2, "EINT59"),
+ MTK_FUNCTION(4, "DSP1_ICK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "DPI33_D2"),
+ MTK_FUNCTION(7, "TESTA_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "MSDC2_DAT1"),
+ "Y21", "mt8135",
+ MTK_EINT_FUNCTION(2, 62),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(2, "EINT62"),
+ MTK_FUNCTION(4, "DSP2_ICK"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "DPI33_D5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "MSDC2_DAT0"),
+ "AB22", "mt8135",
+ MTK_EINT_FUNCTION(2, 61),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(2, "EINT61"),
+ MTK_FUNCTION(4, "DSP1_ID"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "DPI33_D4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "MSDC1_DAT0"),
+ "AC19", "mt8135",
+ MTK_EINT_FUNCTION(2, 53),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "EINT53"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(7, "TESTB_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "MSDC1_DAT1"),
+ "AA19", "mt8135",
+ MTK_EINT_FUNCTION(2, 54),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "EINT54"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(7, "TESTB_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC1_CMD"),
+ "AA20", "mt8135",
+ MTK_EINT_FUNCTION(2, 52),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "EINT52"),
+ MTK_FUNCTION(3, "SDA0"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(7, "TESTB_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC1_CLK"),
+ "AB19", "mt8135",
+ MTK_EINT_FUNCTION(2, 51),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "EINT51"),
+ MTK_FUNCTION(3, "SCL0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC1_DAT2"),
+ "AA21", "mt8135",
+ MTK_EINT_FUNCTION(2, 55),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "EINT55"),
+ MTK_FUNCTION(3, "SCL4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(7, "TESTB_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC1_DAT3"),
+ "AB20", "mt8135",
+ MTK_EINT_FUNCTION(2, 56),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "EINT56"),
+ MTK_FUNCTION(3, "SDA4"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(7, "TESTB_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC4_DAT0"),
+ "AB8", "mt8135",
+ MTK_EINT_FUNCTION(2, 133),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC4_DAT0"),
+ MTK_FUNCTION(2, "EINT133"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[9]"),
+ MTK_FUNCTION(7, "LPTE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC4_DAT1"),
+ "AB7", "mt8135",
+ MTK_EINT_FUNCTION(2, 134),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC4_DAT1"),
+ MTK_FUNCTION(2, "EINT134"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[10]"),
+ MTK_FUNCTION(7, "LRSTB_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "MSDC4_DAT5"),
+ "AA8", "mt8135",
+ MTK_EINT_FUNCTION(2, 136),
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "MSDC4_DAT5"),
+ MTK_FUNCTION(2, "EINT136"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[11]"),
+ MTK_FUNCTION(7, "SPI1_CSN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "MSDC4_DAT6"),
+ "AC4", "mt8135",
+ MTK_EINT_FUNCTION(2, 137),
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "MSDC4_DAT6"),
+ MTK_FUNCTION(2, "EINT137"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[12]"),
+ MTK_FUNCTION(7, "SPI1_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "MSDC4_DAT7"),
+ "AC6", "mt8135",
+ MTK_EINT_FUNCTION(2, 138),
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "MSDC4_DAT7"),
+ MTK_FUNCTION(2, "EINT138"),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[13]"),
+ MTK_FUNCTION(7, "SPI1_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "MSDC4_DAT4"),
+ "AA7", "mt8135",
+ MTK_EINT_FUNCTION(2, 135),
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "MSDC4_DAT4"),
+ MTK_FUNCTION(2, "EINT135"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[14]"),
+ MTK_FUNCTION(7, "SPI1_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "MSDC4_DAT2"),
+ "AB6", "mt8135",
+ MTK_EINT_FUNCTION(2, 131),
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "MSDC4_DAT2"),
+ MTK_FUNCTION(2, "EINT131"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "CM2PDN_2X"),
+ MTK_FUNCTION(5, "DAC_WS"),
+ MTK_FUNCTION(6, "PCM1_WS"),
+ MTK_FUNCTION(7, "LSCE0B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "MSDC4_CLK"),
+ "AB5", "mt8135",
+ MTK_EINT_FUNCTION(2, 129),
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "MSDC4_CLK"),
+ MTK_FUNCTION(2, "EINT129"),
+ MTK_FUNCTION(3, "DPI1_CK_2X"),
+ MTK_FUNCTION(4, "CM2PCLK_2X"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "LSCK_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "MSDC4_DAT3"),
+ "Y8", "mt8135",
+ MTK_EINT_FUNCTION(2, 132),
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "MSDC4_DAT3"),
+ MTK_FUNCTION(2, "EINT132"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "CM2RST_2X"),
+ MTK_FUNCTION(5, "DAC_DAT_OUT"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "LSCE1B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "MSDC4_CMD"),
+ "AC3", "mt8135",
+ MTK_EINT_FUNCTION(2, 128),
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "MSDC4_CMD"),
+ MTK_FUNCTION(2, "EINT128"),
+ MTK_FUNCTION(3, "DPI1_DE_2X"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(7, "LSDA_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "MSDC4_RSTB"),
+ "AB4", "mt8135",
+ MTK_EINT_FUNCTION(2, 130),
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "MSDC4_RSTB"),
+ MTK_FUNCTION(2, "EINT130"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "CM2MCLK_2X"),
+ MTK_FUNCTION(5, "DAC_CK"),
+ MTK_FUNCTION(6, "PCM1_CK"),
+ MTK_FUNCTION(7, "LSA0_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "SDA0"),
+ "W9", "mt8135",
+ MTK_EINT_FUNCTION(2, 91),
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION(2, "EINT91"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "SCL0"),
+ "W11", "mt8135",
+ MTK_EINT_FUNCTION(2, 90),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION(2, "EINT90"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "EINT10_AUXIN2"),
+ "AA3", "mt8135",
+ MTK_EINT_FUNCTION(1, 10),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "EINT10"),
+ MTK_FUNCTION(5, "USB_TEST_IO[16]"),
+ MTK_FUNCTION(6, "TESTB_OUT16"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "EINT11_AUXIN3"),
+ "AB2", "mt8135",
+ MTK_EINT_FUNCTION(1, 11),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "EINT11"),
+ MTK_FUNCTION(5, "USB_TEST_IO[17]"),
+ MTK_FUNCTION(6, "TESTB_OUT17"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "EINT16_AUXIN4"),
+ "AB3", "mt8135",
+ MTK_EINT_FUNCTION(1, 16),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "EINT16"),
+ MTK_FUNCTION(5, "USB_TEST_IO[18]"),
+ MTK_FUNCTION(6, "TESTB_OUT18"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "I2S_CLK"),
+ "W6", "mt8135",
+ MTK_EINT_FUNCTION(2, 10),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "I2SIN_CK"),
+ MTK_FUNCTION(2, "EINT10"),
+ MTK_FUNCTION(3, "DAC_CK"),
+ MTK_FUNCTION(4, "PCM1_CK"),
+ MTK_FUNCTION(5, "USB_TEST_IO[19]"),
+ MTK_FUNCTION(6, "TESTB_OUT19"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "I2S_WS"),
+ "AA6", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "I2SIN_WS"),
+ MTK_FUNCTION(3, "DAC_WS"),
+ MTK_FUNCTION(4, "PCM1_WS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[20]"),
+ MTK_FUNCTION(6, "TESTB_OUT20"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "I2S_DATA_IN"),
+ "AA5", "mt8135",
+ MTK_EINT_FUNCTION(2, 11),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "I2SIN_DAT"),
+ MTK_FUNCTION(2, "EINT11"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[21]"),
+ MTK_FUNCTION(6, "TESTB_OUT22"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "I2S_DATA_OUT"),
+ "AA4", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "I2SOUT_DAT"),
+ MTK_FUNCTION(3, "DAC_DAT_OUT"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[22]"),
+ MTK_FUNCTION(6, "TESTB_OUT23"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "EINT5"),
+ "W5", "mt8135",
+ MTK_EINT_FUNCTION(1, 5),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "EINT5"),
+ MTK_FUNCTION(2, "PWM5"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "GPU_JTRSTB"),
+ MTK_FUNCTION(5, "USB_TEST_IO[23]"),
+ MTK_FUNCTION(6, "TESTB_OUT26"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "EINT6"),
+ "V5", "mt8135",
+ MTK_EINT_FUNCTION(1, 6),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "EINT6"),
+ MTK_FUNCTION(2, "PWM6"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "GPU_JTMS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[24]"),
+ MTK_FUNCTION(6, "TESTB_OUT27"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "EINT7"),
+ "W3", "mt8135",
+ MTK_EINT_FUNCTION(1, 7),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "EINT7"),
+ MTK_FUNCTION(2, "PWM7"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "GPU_JTDO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[25]"),
+ MTK_FUNCTION(6, "TESTB_OUT28"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "EINT8"),
+ "V6", "mt8135",
+ MTK_EINT_FUNCTION(1, 8),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "EINT8"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "GPU_JTDI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[26]"),
+ MTK_FUNCTION(6, "TESTB_OUT29"),
+ MTK_FUNCTION(7, "EXT_FRAME_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "EINT9"),
+ "W8", "mt8135",
+ MTK_EINT_FUNCTION(1, 9),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "EINT9"),
+ MTK_FUNCTION(4, "GPU_JTCK"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "TESTB_OUT30"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "LPCE1B"),
+ "W4", "mt8135",
+ MTK_EINT_FUNCTION(2, 127),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "LPCE1B"),
+ MTK_FUNCTION(2, "EINT127"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, "TESTB_OUT14"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "LPCE0B"),
+ "T5", "mt8135",
+ MTK_EINT_FUNCTION(2, 126),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "LPCE0B"),
+ MTK_FUNCTION(2, "EINT126"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, "TESTB_OUT15"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "DISP_PWM"),
+ "V4", "mt8135",
+ MTK_EINT_FUNCTION(2, 77),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(2, "EINT77"),
+ MTK_FUNCTION(3, "LSDI"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(7, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "EINT1"),
+ "T6", "mt8135",
+ MTK_EINT_FUNCTION(1, 1),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "EINT1"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(5, "USB_TEST_IO[13]"),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "EINT2"),
+ "T4", "mt8135",
+ MTK_EINT_FUNCTION(1, 2),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "EINT2"),
+ MTK_FUNCTION(2, "PWM3"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(5, "USB_TEST_IO[14]"),
+ MTK_FUNCTION(6, "SRCLKENAI2"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "EINT3"),
+ "R4", "mt8135",
+ MTK_EINT_FUNCTION(1, 3),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "EINT3"),
+ MTK_FUNCTION(5, "USB_TEST_IO[15]"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "EXT_26M_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "EINT4"),
+ "R5", "mt8135",
+ MTK_EINT_FUNCTION(1, 4),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "EINT4"),
+ MTK_FUNCTION(2, "PWM4"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "DPIDE"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 100),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "DPI0_DE"),
+ MTK_FUNCTION(2, "EINT100"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "IRDA_TXD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "DPICK"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 101),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "DPI0_CK"),
+ MTK_FUNCTION(2, "EINT101"),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "IRDA_PDN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "DPIG4"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 114),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "DPI0_G4"),
+ MTK_FUNCTION(2, "EINT114"),
+ MTK_FUNCTION(4, "CM2DAT_2X[0]"),
+ MTK_FUNCTION(5, "DSP2_ID")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "DPIG5"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 115),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "DPI0_G5"),
+ MTK_FUNCTION(2, "EINT115"),
+ MTK_FUNCTION(4, "CM2DAT_2X[1]"),
+ MTK_FUNCTION(5, "DSP2_ICK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "DPIR3"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 121),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "DPI0_R3"),
+ MTK_FUNCTION(2, "EINT121"),
+ MTK_FUNCTION(4, "CM2DAT_2X[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "DPIG1"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 111),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "DPI0_G1"),
+ MTK_FUNCTION(2, "EINT111"),
+ MTK_FUNCTION(5, "DSP1_ICK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "DPIVSYNC"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 98),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "DPI0_VSYNC"),
+ MTK_FUNCTION(2, "EINT98"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "DPIHSYNC"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 99),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "DPI0_HSYNC"),
+ MTK_FUNCTION(2, "EINT99"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "IRDA_RXD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "DPIB0"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 102),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "DPI0_B0"),
+ MTK_FUNCTION(2, "EINT102"),
+ MTK_FUNCTION(4, "SCL0"),
+ MTK_FUNCTION(5, "DISP_PWM")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "DPIB1"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 103),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "DPI0_B1"),
+ MTK_FUNCTION(2, "EINT103"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SDA0"),
+ MTK_FUNCTION(5, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "DPIB2"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 104),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "DPI0_B2"),
+ MTK_FUNCTION(2, "EINT104"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "DPIB3"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 105),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "DPI0_B3"),
+ MTK_FUNCTION(2, "EINT105"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "DPIB4"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 106),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "DPI0_B4"),
+ MTK_FUNCTION(2, "EINT106"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "DPIB5"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 107),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "DPI0_B5"),
+ MTK_FUNCTION(2, "EINT107"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "PWM5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "DPIB6"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 108),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "DPI0_B6"),
+ MTK_FUNCTION(2, "EINT108"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "PWM6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "DPIB7"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 109),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "DPI0_B7"),
+ MTK_FUNCTION(2, "EINT109"),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "PWM7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "DPIG0"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 110),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "DPI0_G0"),
+ MTK_FUNCTION(2, "EINT110"),
+ MTK_FUNCTION(5, "DSP1_ID")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "DPIG2"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 112),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "DPI0_G2"),
+ MTK_FUNCTION(2, "EINT112"),
+ MTK_FUNCTION(5, "DSP1_IMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "DPIG3"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 113),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "DPI0_G3"),
+ MTK_FUNCTION(2, "EINT113"),
+ MTK_FUNCTION(5, "DSP2_IMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "DPIG6"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 116),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "DPI0_G6"),
+ MTK_FUNCTION(2, "EINT116"),
+ MTK_FUNCTION(4, "CM2DAT_2X[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "DPIG7"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 117),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "DPI0_G7"),
+ MTK_FUNCTION(2, "EINT117"),
+ MTK_FUNCTION(4, "CM2DAT_2X[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "DPIR0"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 118),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "DPI0_R0"),
+ MTK_FUNCTION(2, "EINT118"),
+ MTK_FUNCTION(4, "CM2DAT_2X[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "DPIR1"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 119),
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "DPI0_R1"),
+ MTK_FUNCTION(2, "EINT119"),
+ MTK_FUNCTION(4, "CM2DAT_2X[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "DPIR2"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 120),
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "DPI0_R2"),
+ MTK_FUNCTION(2, "EINT120"),
+ MTK_FUNCTION(4, "CM2DAT_2X[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "DPIR4"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 122),
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "DPI0_R4"),
+ MTK_FUNCTION(2, "EINT122"),
+ MTK_FUNCTION(4, "CM2DAT_2X[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "DPIR5"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 123),
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "DPI0_R5"),
+ MTK_FUNCTION(2, "EINT123"),
+ MTK_FUNCTION(4, "CM2DAT_2X[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "DPIR6"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 124),
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "DPI0_R6"),
+ MTK_FUNCTION(2, "EINT124"),
+ MTK_FUNCTION(4, "CM2VSYNC_2X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "DPIR7"),
+ NULL, "mt8135",
+ MTK_EINT_FUNCTION(2, 125),
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "DPI0_R7"),
+ MTK_FUNCTION(2, "EINT125"),
+ MTK_FUNCTION(4, "CM2HSYNC_2X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
+ "AA2", "mt8135",
+ MTK_EINT_FUNCTION(2, 36),
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(2, "EINT36")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
+ "AA1", "mt8135",
+ MTK_EINT_FUNCTION(2, 35),
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(2, "EINT35")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
+ "Y2", "mt8135",
+ MTK_EINT_FUNCTION(2, 169),
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(2, "EINT169")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
+ "Y1", "mt8135",
+ MTK_EINT_FUNCTION(2, 168),
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(2, "EINT168")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
+ "W2", "mt8135",
+ MTK_EINT_FUNCTION(2, 163),
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(2, "EINT163")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
+ "W1", "mt8135",
+ MTK_EINT_FUNCTION(2, 162),
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(2, "EINT162")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
+ "V3", "mt8135",
+ MTK_EINT_FUNCTION(2, 167),
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(2, "EINT167")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
+ "V2", "mt8135",
+ MTK_EINT_FUNCTION(2, 166),
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(2, "EINT166")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
+ "U3", "mt8135",
+ MTK_EINT_FUNCTION(2, 165),
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(2, "EINT165")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
+ "U2", "mt8135",
+ MTK_EINT_FUNCTION(2, 164),
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(2, "EINT164")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "RDN3"),
+ "N5", "mt8135",
+ MTK_EINT_FUNCTION(2, 18),
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(2, "EINT18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "RDP3"),
+ "N4", "mt8135",
+ MTK_EINT_FUNCTION(2, 30),
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(2, "EINT30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "RDN2"),
+ "T2", "mt8135",
+ MTK_EINT_FUNCTION(2, 31),
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(2, "EINT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "RDP2"),
+ "T3", "mt8135",
+ MTK_EINT_FUNCTION(2, 32),
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(2, "EINT32")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "RCN"),
+ "P2", "mt8135",
+ MTK_EINT_FUNCTION(2, 33),
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(2, "EINT33")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "RCP"),
+ "P3", "mt8135",
+ MTK_EINT_FUNCTION(2, 39),
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(2, "EINT39")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "RDN1"),
+ "R3", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO165")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "RDP1"),
+ "R2", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO166")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "RDN0"),
+ "N3", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO167")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "RDP0"),
+ "N2", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO168")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "RDN1_A"),
+ "M4", "mt8135",
+ MTK_EINT_FUNCTION(2, 175),
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "CMDAT6"),
+ MTK_FUNCTION(2, "EINT175")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "RDP1_A"),
+ "M3", "mt8135",
+ MTK_EINT_FUNCTION(2, 174),
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "CMDAT7"),
+ MTK_FUNCTION(2, "EINT174")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "RCN_A"),
+ "L3", "mt8135",
+ MTK_EINT_FUNCTION(2, 171),
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "CMDAT8"),
+ MTK_FUNCTION(2, "EINT171")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "RCP_A"),
+ "L2", "mt8135",
+ MTK_EINT_FUNCTION(2, 170),
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "CMDAT9"),
+ MTK_FUNCTION(2, "EINT170")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "RDN0_A"),
+ "M2", "mt8135",
+ MTK_EINT_FUNCTION(2, 173),
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "CMHSYNC"),
+ MTK_FUNCTION(2, "EINT173")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "RDP0_A"),
+ "M1", "mt8135",
+ MTK_EINT_FUNCTION(2, 172),
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "CMVSYNC"),
+ MTK_FUNCTION(2, "EINT172")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "RDN1_B"),
+ "H2", "mt8135",
+ MTK_EINT_FUNCTION(2, 181),
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "CMDAT2"),
+ MTK_FUNCTION(2, "EINT181"),
+ MTK_FUNCTION(3, "CMCSD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "RDP1_B"),
+ "H1", "mt8135",
+ MTK_EINT_FUNCTION(2, 180),
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "CMDAT3"),
+ MTK_FUNCTION(2, "EINT180"),
+ MTK_FUNCTION(3, "CMCSD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "RCN_B"),
+ "K3", "mt8135",
+ MTK_EINT_FUNCTION(2, 177),
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "CMDAT4"),
+ MTK_FUNCTION(2, "EINT177")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "RCP_B"),
+ "K2", "mt8135",
+ MTK_EINT_FUNCTION(2, 176),
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "CMDAT5"),
+ MTK_FUNCTION(2, "EINT176")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "RDN0_B"),
+ "J3", "mt8135",
+ MTK_EINT_FUNCTION(2, 179),
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION(2, "EINT179"),
+ MTK_FUNCTION(3, "CMCSD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "RDP0_B"),
+ "J2", "mt8135",
+ MTK_EINT_FUNCTION(2, 178),
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION(2, "EINT178"),
+ MTK_FUNCTION(3, "CMCSD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "CMPCLK"),
+ "K4", "mt8135",
+ MTK_EINT_FUNCTION(2, 182),
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION(2, "EINT182"),
+ MTK_FUNCTION(3, "CMCSK"),
+ MTK_FUNCTION(4, "CM2MCLK_4X"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"),
+ MTK_FUNCTION(6, "VENC_TEST_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "CMMCLK"),
+ "J5", "mt8135",
+ MTK_EINT_FUNCTION(2, 183),
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION(2, "EINT183"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"),
+ MTK_FUNCTION(7, "TESTA_OUT28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "CMRST"),
+ "J6", "mt8135",
+ MTK_EINT_FUNCTION(2, 185),
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "CMRST"),
+ MTK_FUNCTION(2, "EINT185"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"),
+ MTK_FUNCTION(7, "TESTA_OUT30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "CMPDN"),
+ "J4", "mt8135",
+ MTK_EINT_FUNCTION(2, 184),
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "CMPDN"),
+ MTK_FUNCTION(2, "EINT184"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"),
+ MTK_FUNCTION(7, "TESTA_OUT29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "CMFLASH"),
+ "G4", "mt8135",
+ MTK_EINT_FUNCTION(2, 186),
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "CMFLASH"),
+ MTK_FUNCTION(2, "EINT186"),
+ MTK_FUNCTION(3, "CM2MCLK_3X"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_1"),
+ MTK_FUNCTION(7, "TESTA_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
+ "F5", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "PCM0_CK"),
+ MTK_FUNCTION(5, "DSP2_ICK"),
+ MTK_FUNCTION(6, "IMG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
+ "G6", "mt8135",
+ MTK_EINT_FUNCTION(2, 16),
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"),
+ MTK_FUNCTION(2, "EINT16"),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "PCM0_WS"),
+ MTK_FUNCTION(6, "DISP_TEST_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
+ "G3", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_RX"),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, "PCM0_DI"),
+ MTK_FUNCTION(5, "DSP2_ID"),
+ MTK_FUNCTION(6, "MFG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
+ "G5", "mt8135",
+ MTK_EINT_FUNCTION(2, 17),
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_TX"),
+ MTK_FUNCTION(2, "EINT17"),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "PCM0_DO"),
+ MTK_FUNCTION(6, "VDEC_TEST_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "SRCLKENAI"),
+ "K5", "mt8135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "URXD3"),
+ "C3", "mt8135",
+ MTK_EINT_FUNCTION(2, 87),
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "EINT87"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(5, "TS_AUX_ST"),
+ MTK_FUNCTION(6, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "UTXD3"),
+ "B2", "mt8135",
+ MTK_EINT_FUNCTION(2, 86),
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "EINT86"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(5, "TS_AUX_CS_B"),
+ MTK_FUNCTION(6, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "SDA2"),
+ "G2", "mt8135",
+ MTK_EINT_FUNCTION(2, 95),
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION(2, "EINT95"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "TS_AUX_PWDB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "SCL2"),
+ "F4", "mt8135",
+ MTK_EINT_FUNCTION(2, 94),
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION(2, "EINT94"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "TS_AUXADC_TEST_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "SDA1"),
+ "F2", "mt8135",
+ MTK_EINT_FUNCTION(2, 93),
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION(2, "EINT93"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "SCL1"),
+ "F3", "mt8135",
+ MTK_EINT_FUNCTION(2, 92),
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION(2, "EINT92"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "TS_AUX_DIN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "MSDC3_DAT2"),
+ "E1", "mt8135",
+ MTK_EINT_FUNCTION(2, 71),
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION(2, "EINT71"),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "MSDC3_DAT3"),
+ "C2", "mt8135",
+ MTK_EINT_FUNCTION(2, 72),
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION(2, "EINT72"),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "MSDC3_CMD"),
+ "D2", "mt8135",
+ MTK_EINT_FUNCTION(2, 68),
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "MSDC3_CMD"),
+ MTK_FUNCTION(2, "EINT68"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "MSDC3_CLK"),
+ "E2", "mt8135",
+ MTK_EINT_FUNCTION(2, 67),
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "MSDC3_CLK"),
+ MTK_FUNCTION(2, "EINT67"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "MSDC3_DAT1"),
+ "D3", "mt8135",
+ MTK_EINT_FUNCTION(2, 70),
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "MSDC3_DAT1"),
+ MTK_FUNCTION(2, "EINT70"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "MSDC3_DAT0"),
+ "E3", "mt8135",
+ MTK_EINT_FUNCTION(2, 69),
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "MSDC3_DAT0"),
+ MTK_FUNCTION(2, "EINT69"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT8135_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
new file mode 100644
index 0000000..9b018fd
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
@@ -0,0 +1,1226 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT8173_H
+#define __PINCTRL_MTK_MT8173_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt8173[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "EINT0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "IRDA_PDN"),
+ MTK_FUNCTION(2, "I2S1_WS"),
+ MTK_FUNCTION(3, "AUD_SPDIF"),
+ MTK_FUNCTION(4, "UTXD0"),
+ MTK_FUNCTION(7, "DBG_MON_A_20_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "EINT1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "IRDA_RXD"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "SDA5"),
+ MTK_FUNCTION(4, "URXD0"),
+ MTK_FUNCTION(7, "DBG_MON_A_21_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "EINT2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "IRDA_TXD"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "SCL5"),
+ MTK_FUNCTION(4, "UTXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A_22_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "EINT3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "DSI1_TE"),
+ MTK_FUNCTION(2, "I2S1_DO_1"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "URXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A_23_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "EINT4"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "DISP_PWM1"),
+ MTK_FUNCTION(2, "I2S1_DO_2"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "UCTS3"),
+ MTK_FUNCTION(6, "SFWP_B")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "EINT5"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PCM1_CLK"),
+ MTK_FUNCTION(2, "I2S2_WS"),
+ MTK_FUNCTION(3, "SPI_CK_3_"),
+ MTK_FUNCTION(4, "URTS3"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
+ MTK_FUNCTION(6, "SFOUT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "EINT6"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PCM1_SYNC"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(3, "SPI_MI_3_"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
+ MTK_FUNCTION(6, "SFCS0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "EINT7"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "PCM1_DI"),
+ MTK_FUNCTION(2, "I2S2_DI_1"),
+ MTK_FUNCTION(3, "SPI_MO_3_"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
+ MTK_FUNCTION(6, "SFHOLD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "EINT8"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "PCM1_DO"),
+ MTK_FUNCTION(2, "I2S2_DI_2"),
+ MTK_FUNCTION(3, "SPI_CS_3_"),
+ MTK_FUNCTION(4, "AUD_SPDIF"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
+ MTK_FUNCTION(6, "SFIN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "EINT9"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(4, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
+ MTK_FUNCTION(6, "SFCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "EINT10"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "CLKM0"),
+ MTK_FUNCTION(2, "DSI1_TE"),
+ MTK_FUNCTION(3, "DISP_PWM1"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "IRDA_RXD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "EINT11"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "I2S3_WS"),
+ MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "IRDA_TXD"),
+ MTK_FUNCTION(6, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(7, "DBG_MON_B_30_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "EINT12"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 12),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(3, "SRCLKENA0"),
+ MTK_FUNCTION(5, "I2S2_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B_32_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "EINT13"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 13),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "CLKM3"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(3, "SRCLKENA0"),
+ MTK_FUNCTION(5, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A_32_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "EINT14"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION(2, "CMCSD0"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(7, "DBG_MON_B_6_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "EINT15"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION(2, "CMCSD1"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(4, "CLKM3"),
+ MTK_FUNCTION(7, "DBG_MON_B_29_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "IDDIG"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(1, 16),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(4, "PWM5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "WATCHDOG"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "WATCHDOG_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "CEC"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "CEC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "HDMISCK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "HDMISCK"),
+ MTK_FUNCTION(2, "HDCP_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "HDMISD"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "HDMISD"),
+ MTK_FUNCTION(2, "HDCP_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "HTPLG"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "HTPLG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "MSDC3_DAT0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 22),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "MSDC3_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "MSDC3_DAT1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "MSDC3_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "MSDC3_DAT2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "MSDC3_DAT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "MSDC3_DAT3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "MSDC3_DAT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "MSDC3_CLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "MSDC3_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "MSDC3_CMD"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "MSDC3_CMD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "MSDC3_DSL"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "MSDC3_DSL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "UCTS2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "UCTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "URTS2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "URTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "URXD2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "UTXD2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "DAICLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, " MRG_CLK"),
+ MTK_FUNCTION(2, "PCM0_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "DAIPCMIN"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, " MRG_DI"),
+ MTK_FUNCTION(2, "PCM0_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "DAIPCMOUT"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, " MRG_DO"),
+ MTK_FUNCTION(2, "PCM0_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "DAISYNC"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, " MRG_SYNC"),
+ MTK_FUNCTION(2, "PCM0_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "EINT16"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(2, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, "CLKM0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "CONN_RST"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(2, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(6, "CLKM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "CM2MCLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "CM2MCLK"),
+ MTK_FUNCTION(2, "CMCSD0"),
+ MTK_FUNCTION(7, "DBG_MON_A_17_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "CMPCLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION(2, "CMCSK"),
+ MTK_FUNCTION(3, "CMCSD2"),
+ MTK_FUNCTION(7, "DBG_MON_A_18_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "CMMCLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A_19_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "DSI_TE"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "SDA2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "SCL2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "SDA0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "SCL0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "RDN0_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "CMDAT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "RDP0_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "CMDAT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "RDN1_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "CMDAT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "RDP1_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "CMDAT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "RCN_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "CMDAT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "RCP_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "CMDAT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "RDN2_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "CMDAT8"),
+ MTK_FUNCTION(2, "CMCSD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "RDP2_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "CMDAT9"),
+ MTK_FUNCTION(2, "CMCSD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "RDN3_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "CMHSYNC"),
+ MTK_FUNCTION(2, "CMCSD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "RDP3_A"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "CMVSYNC"),
+ MTK_FUNCTION(2, "CMCSD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "MSDC0_DAT0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(2, "I2S1_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B_7_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "MSDC0_DAT1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_8_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "MSDC0_DAT2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_9_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "MSDC0_DAT3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(2, "I2S1_DO_1"),
+ MTK_FUNCTION(7, "DBG_MON_B_10_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "MSDC0_DAT4"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(2, "I2S1_DO_2"),
+ MTK_FUNCTION(7, "DBG_MON_B_11_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "MSDC0_DAT5"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(2, "I2S2_WS"),
+ MTK_FUNCTION(7, "DBG_MON_B_12_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "MSDC0_DAT6"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_13_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "MSDC0_DAT7"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(2, "I2S2_DI_1"),
+ MTK_FUNCTION(7, "DBG_MON_B_14_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "MSDC0_CLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B_16_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "MSDC0_CMD"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(2, "I2S2_DI_2"),
+ MTK_FUNCTION(7, "DBG_MON_B_15_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "MSDC0_DSL"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "MSDC0_DSL"),
+ MTK_FUNCTION(7, "DBG_MON_B_17_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "MSDC0_RST_"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_18_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "SPI_CK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "SPI_CK_0_"),
+ MTK_FUNCTION(2, "I2S3_DO_1"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "I2S2_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B_19_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "SPI_MI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 70),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "SPI_MI_0_"),
+ MTK_FUNCTION(2, "I2S3_DO_2"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "SPI_MO_0_"),
+ MTK_FUNCTION(5, "I2S2_DI_1"),
+ MTK_FUNCTION(6, "DSI1_TE"),
+ MTK_FUNCTION(7, "DBG_MON_B_20_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "SPI_MO"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "SPI_MO_0_"),
+ MTK_FUNCTION(2, "I2S3_DO_3"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "SPI_MI_0_"),
+ MTK_FUNCTION(5, "I2S2_DI_2"),
+ MTK_FUNCTION(7, "DBG_MON_B_21_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "SPI_CS"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "SPI_CS_0_"),
+ MTK_FUNCTION(2, "I2S3_DO_4"),
+ MTK_FUNCTION(3, "PWM3"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "DISP_PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_B_22_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "MSDC1_DAT0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(7, "DBG_MON_B_24_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "MSDC1_DAT1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(7, "DBG_MON_B_25_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "MSDC1_DAT2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(7, "DBG_MON_B_26_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "MSDC1_DAT3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(7, "DBG_MON_B_27_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "MSDC1_CLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B_28_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "MSDC1_CMD"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(7, "DBG_MON_B_23_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "PWRAP_SPI0_MI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "PWRAP_SPIMI"),
+ MTK_FUNCTION(2, "PWRAP_SPIMO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "PWRAP_SPI0_MO"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "PWRAP_SPIMO"),
+ MTK_FUNCTION(2, "PWRAP_SPIMI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "PWRAP_SPI0_CK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "PWRAP_SPICK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "PWRAP_SPI0_CSN"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "PWRAP_SPICS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "AUD_CLK_MOSI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "AUD_DAT_MISO"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "AUD_DAT_MOSI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "RTC32K_CK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "DISP_PWM0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "DISP_PWM0"),
+ MTK_FUNCTION(2, "DISP_PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_B_31_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "SRCLKENAI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "SRCLKENAI2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "SRCLKENAI2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "SRCLKENA0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "SRCLKENA1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "PCM_CLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "PCM1_CLK"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A_24_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "PCM_SYNC"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "PCM1_SYNC"),
+ MTK_FUNCTION(2, "I2S0_WS"),
+ MTK_FUNCTION(7, "DBG_MON_A_25_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "PCM_RX"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "PCM1_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A_26_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "PCM_TX"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "PCM1_DO"),
+ MTK_FUNCTION(2, "I2S0_DO"),
+ MTK_FUNCTION(7, "DBG_MON_A_27_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "URXD1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(7, "DBG_MON_A_28_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "UTXD1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(7, "DBG_MON_A_29_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "URTS1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION(2, "UCTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A_30_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "UCTS1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION(2, "URTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A_31_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "MSDC2_DAT0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "SDA5"),
+ MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(7, "DBG_MON_B_0_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "MSDC2_DAT1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(3, "AUD_SPDIF"),
+ MTK_FUNCTION(4, "SCL5"),
+ MTK_FUNCTION(7, "DBG_MON_B_1_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "MSDC2_DAT2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(3, "UTXD0"),
+ MTK_FUNCTION(5, "PWM0"),
+ MTK_FUNCTION(6, "SPI_CK_1_"),
+ MTK_FUNCTION(7, "DBG_MON_B_2_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "MSDC2_DAT3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(3, "URXD0"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, "SPI_MI_1_"),
+ MTK_FUNCTION(7, "DBG_MON_B_3_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "MSDC2_CLK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, "SPI_MO_1_"),
+ MTK_FUNCTION(7, "DBG_MON_B_4_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "MSDC2_CMD"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "SPI_CS_1_"),
+ MTK_FUNCTION(7, "DBG_MON_B_5_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "SDA3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "SDA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "SCL3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "SCL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "JTMS"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, " MFG_JTAG_TMS"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
+ MTK_FUNCTION(6, "DFD_TMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "JTCK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, " MFG_JTAG_TCK"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
+ MTK_FUNCTION(6, "DFD_TCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "JTDI"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, " MFG_JTAG_TDI"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
+ MTK_FUNCTION(6, "DFD_TDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "JTDO"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "MFG_JTAG_TDO"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
+ MTK_FUNCTION(6, "DFD_TDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "JTRST_B"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "JTRST_B"),
+ MTK_FUNCTION(2, " MFG_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
+ MTK_FUNCTION(6, "DFD_NTRST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "URXD0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(6, "I2S2_WS"),
+ MTK_FUNCTION(7, "DBG_MON_A_0_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "UTXD0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(6, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A_1_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "URTS0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "URTS0"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(6, "I2S2_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_A_2_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "UCTS0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "UCTS0"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(6, "I2S2_DI_1"),
+ MTK_FUNCTION(7, "DBG_MON_A_3_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "URXD3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "UTXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A_9_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "UTXD3"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "URXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A_10_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "KPROW0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "KROW0"),
+ MTK_FUNCTION(7, "DBG_MON_A_11_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "KPROW1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "KROW1"),
+ MTK_FUNCTION(3, "PWM6"),
+ MTK_FUNCTION(7, "DBG_MON_A_12_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "KPROW2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "KROW2"),
+ MTK_FUNCTION(2, "IRDA_PDN"),
+ MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(7, "DBG_MON_A_13_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "KPCOL0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "KCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_A_14_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "KPCOL1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "KCOL1"),
+ MTK_FUNCTION(2, "IRDA_RXD"),
+ MTK_FUNCTION(3, "PWM5"),
+ MTK_FUNCTION(7, "DBG_MON_A_15_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "KPCOL2"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "KCOL2"),
+ MTK_FUNCTION(2, "IRDA_TXD"),
+ MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(7, "DBG_MON_A_16_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "SDA1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "SCL1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "LCM_RST"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "I2S0_LRCK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "I2S0_WS"),
+ MTK_FUNCTION(2, "I2S1_WS"),
+ MTK_FUNCTION(3, "I2S2_WS"),
+ MTK_FUNCTION(5, "SPI_CK_2_"),
+ MTK_FUNCTION(7, "DBG_MON_A_4_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "I2S0_BCK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(5, "SPI_MI_2_"),
+ MTK_FUNCTION(7, "DBG_MON_A_5_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "I2S0_MCK"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(5, "SPI_MO_2_"),
+ MTK_FUNCTION(7, "DBG_MON_A_6_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "I2S0_DATA0"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "I2S0_DO"),
+ MTK_FUNCTION(2, "I2S1_DO_1"),
+ MTK_FUNCTION(3, "I2S2_DI_1"),
+ MTK_FUNCTION(5, "SPI_CS_2_"),
+ MTK_FUNCTION(7, "DBG_MON_A_7_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "I2S0_DATA1"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "I2S1_DO_2"),
+ MTK_FUNCTION(3, "I2S2_DI_2"),
+ MTK_FUNCTION(7, "DBG_MON_A_8_")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "SDA4"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "SDA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "SCL4"),
+ NULL, "mt8173",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "SCL4")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT8173_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h
new file mode 100644
index 0000000..402ba92
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h
@@ -0,0 +1,1917 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT8183_H
+#define __PINCTRL_MTK_MT8183_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static struct mtk_desc_pin mtk_pins_mt8183[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "GPIO0"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "MRG_SYNC"),
+ MTK_FUNCTION(2, "PCM0_SYNC"),
+ MTK_FUNCTION(3, "TP_GPIO0_AO"),
+ MTK_FUNCTION(4, "SRCLKENAI0"),
+ MTK_FUNCTION(5, "SCP_SPI2_CS"),
+ MTK_FUNCTION(6, "I2S3_MCK"),
+ MTK_FUNCTION(7, "SPI2_CSB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "GPIO1"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "MRG_CLK"),
+ MTK_FUNCTION(2, "PCM0_CLK"),
+ MTK_FUNCTION(3, "TP_GPIO1_AO"),
+ MTK_FUNCTION(4, "CLKM3"),
+ MTK_FUNCTION(5, "SCP_SPI2_MO"),
+ MTK_FUNCTION(6, "I2S3_BCK"),
+ MTK_FUNCTION(7, "SPI2_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "GPIO2"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "MRG_DO"),
+ MTK_FUNCTION(2, "PCM0_DO"),
+ MTK_FUNCTION(3, "TP_GPIO2_AO"),
+ MTK_FUNCTION(4, "SCL6"),
+ MTK_FUNCTION(5, "SCP_SPI2_CK"),
+ MTK_FUNCTION(6, "I2S3_LRCK"),
+ MTK_FUNCTION(7, "SPI2_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "GPIO3"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "MRG_DI"),
+ MTK_FUNCTION(2, "PCM0_DI"),
+ MTK_FUNCTION(3, "TP_GPIO3_AO"),
+ MTK_FUNCTION(4, "SDA6"),
+ MTK_FUNCTION(5, "TDM_MCK"),
+ MTK_FUNCTION(6, "I2S3_DO"),
+ MTK_FUNCTION(7, "SCP_VREQ_VAO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "GPIO4"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWM_B"),
+ MTK_FUNCTION(2, "I2S0_MCK"),
+ MTK_FUNCTION(3, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "TDM_BCK"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO"),
+ MTK_FUNCTION(7, "DAP_MD32_SWD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "GPIO5"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWM_C"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(3, "SSPM_URXD_AO"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "TDM_LRCK"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO"),
+ MTK_FUNCTION(7, "DAP_MD32_SWCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "GPIO6"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWM_A"),
+ MTK_FUNCTION(2, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(4, "MD_URXD0"),
+ MTK_FUNCTION(5, "TDM_DATA0"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO"),
+ MTK_FUNCTION(7, "CMFLASH")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "GPIO7"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI1_B_MI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "USB_DRVVBUS"),
+ MTK_FUNCTION(4, "MD_UTXD0"),
+ MTK_FUNCTION(5, "TDM_DATA1"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO"),
+ MTK_FUNCTION(7, "DVFSRC_EXT_REQ")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "GPIO8"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "SPI1_B_CSB"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "SCL7"),
+ MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(5, "TDM_DATA2"),
+ MTK_FUNCTION(6, "MD_INT0"),
+ MTK_FUNCTION(7, "JTRSTN_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "GPIO9"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "SPI1_B_MO"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "CMMCLK2"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "IO_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "DBG_MON_B10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "GPIO10"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "SPI1_B_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "CMMCLK3"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(5, "TDM_DATA3"),
+ MTK_FUNCTION(6, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_B11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "GPIO11"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "TP_URXD1_AO"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(5, "UCTS0"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "I2S5_MCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "GPIO12"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 12),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "TP_UTXD1_AO"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(5, "URTS0"),
+ MTK_FUNCTION(6, "I2S2_DI2"),
+ MTK_FUNCTION(7, "I2S5_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "GPIO13"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 13),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "DBPI_D0"),
+ MTK_FUNCTION(2, "SPI5_MI"),
+ MTK_FUNCTION(3, "PCM0_SYNC"),
+ MTK_FUNCTION(4, "MD_URXD0"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "I2S0_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "GPIO14"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "DBPI_D1"),
+ MTK_FUNCTION(2, "SPI5_CSB"),
+ MTK_FUNCTION(3, "PCM0_CLK"),
+ MTK_FUNCTION(4, "MD_UTXD0"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "I2S0_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "GPIO15"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "DBPI_D2"),
+ MTK_FUNCTION(2, "SPI5_MO"),
+ MTK_FUNCTION(3, "PCM0_DO"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "I2S0_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "GPIO16"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "DBPI_D3"),
+ MTK_FUNCTION(2, "SPI5_CLK"),
+ MTK_FUNCTION(3, "PCM0_DI"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "I2S0_DI"),
+ MTK_FUNCTION(7, "DBG_MON_B23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "GPIO17"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "DBPI_D4"),
+ MTK_FUNCTION(2, "SPI4_MI"),
+ MTK_FUNCTION(3, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(4, "MD_INT0"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "I2S3_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_A1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "GPIO18"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "DBPI_D5"),
+ MTK_FUNCTION(2, "SPI4_CSB"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(4, "MD_INT0"),
+ MTK_FUNCTION(5, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(6, "I2S3_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "GPIO19"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "DBPI_D6"),
+ MTK_FUNCTION(2, "SPI4_MO"),
+ MTK_FUNCTION(3, "CONN_MCU_TDO"),
+ MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "I2S3_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_A3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "GPIO20"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "DBPI_D7"),
+ MTK_FUNCTION(2, "SPI4_CLK"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "I2S3_DO"),
+ MTK_FUNCTION(7, "DBG_MON_A19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "GPIO21"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "DBPI_D8"),
+ MTK_FUNCTION(2, "SPI3_MI"),
+ MTK_FUNCTION(3, "CONN_MCU_TMS"),
+ MTK_FUNCTION(4, "DAP_MD32_SWD"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(6, "I2S2_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "GPIO22"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 22),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "DBPI_D9"),
+ MTK_FUNCTION(2, "SPI3_CSB"),
+ MTK_FUNCTION(3, "CONN_MCU_TCK"),
+ MTK_FUNCTION(4, "DAP_MD32_SWCK"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(6, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "GPIO23"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "DBPI_D10"),
+ MTK_FUNCTION(2, "SPI3_MO"),
+ MTK_FUNCTION(3, "CONN_MCU_TDI"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "I2S2_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "GPIO24"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "DBPI_D11"),
+ MTK_FUNCTION(2, "SPI3_CLK"),
+ MTK_FUNCTION(3, "SRCLKENAI0"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(5, "IO_JTAG_TCK"),
+ MTK_FUNCTION(6, "I2S2_DI"),
+ MTK_FUNCTION(7, "DBG_MON_B31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "GPIO25"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "DBPI_HSYNC"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "KPCOL2"),
+ MTK_FUNCTION(5, "IO_JTAG_TMS"),
+ MTK_FUNCTION(6, "I2S1_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_B0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "GPIO26"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "DBPI_VSYNC"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "KPROW2"),
+ MTK_FUNCTION(5, "IO_JTAG_TDI"),
+ MTK_FUNCTION(6, "I2S1_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "GPIO27"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "DBPI_DE"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(3, "SCL7"),
+ MTK_FUNCTION(4, "DMIC_CLK"),
+ MTK_FUNCTION(5, "IO_JTAG_TDO"),
+ MTK_FUNCTION(6, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "GPIO28"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "DBPI_CK"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(3, "SDA7"),
+ MTK_FUNCTION(4, "DMIC_DAT"),
+ MTK_FUNCTION(5, "IO_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "I2S1_DO"),
+ MTK_FUNCTION(7, "DBG_MON_B32")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "GPIO29"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "IO_JTAG_TCK"),
+ MTK_FUNCTION(3, "UDI_TCK"),
+ MTK_FUNCTION(4, "CONN_DSP_JCK"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(6, "PCM1_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_A6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "GPIO30"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "DAP_MD32_SWD"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(4, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "GPIO31"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "IO_JTAG_TMS"),
+ MTK_FUNCTION(3, "UDI_TMS"),
+ MTK_FUNCTION(4, "CONN_DSP_JMS"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(6, "PCM1_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "GPIO32"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "IO_JTAG_TDI"),
+ MTK_FUNCTION(3, "UDI_TDI"),
+ MTK_FUNCTION(4, "CONN_DSP_JDI"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(6, "PCM1_DO0"),
+ MTK_FUNCTION(7, "DBG_MON_A9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "GPIO33"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "IO_JTAG_TRSTN"),
+ MTK_FUNCTION(3, "UDI_NTRST"),
+ MTK_FUNCTION(4, "DAP_MD32_SWCK"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(6, "PCM1_DO2"),
+ MTK_FUNCTION(7, "DBG_MON_A10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "GPIO34"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "IO_JTAG_TDO"),
+ MTK_FUNCTION(3, "UDI_TDO"),
+ MTK_FUNCTION(4, "CONN_DSP_JDO"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(6, "PCM1_DO1"),
+ MTK_FUNCTION(7, "DBG_MON_A11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "GPIO35"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(2, "CCU_JTAG_TDO"),
+ MTK_FUNCTION(3, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "CONN_DSP_JMS"),
+ MTK_FUNCTION(7, "DBG_MON_A28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "GPIO36"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(2, "CCU_JTAG_TMS"),
+ MTK_FUNCTION(3, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(7, "DBG_MON_A29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "GPIO37"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(2, "CCU_JTAG_TDI"),
+ MTK_FUNCTION(3, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "CONN_DSP_JDO"),
+ MTK_FUNCTION(7, "DBG_MON_A30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "GPIO38"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(3, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "DBG_MON_A20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "GPIO39"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(2, "CCU_JTAG_TCK"),
+ MTK_FUNCTION(3, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "CONN_DSP_JCK"),
+ MTK_FUNCTION(7, "DBG_MON_A31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "GPIO40"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(2, "CCU_JTAG_TRST"),
+ MTK_FUNCTION(3, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "CONN_DSP_JDI"),
+ MTK_FUNCTION(7, "DBG_MON_A32")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "GPIO41"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "UCTS0"),
+ MTK_FUNCTION(4, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "DMIC_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "GPIO42"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "USB_DRVVBUS"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "URTS0"),
+ MTK_FUNCTION(4, "SSPM_URXD_AO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "DMIC_DAT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "GPIO43"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "DISP_PWM")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "GPIO44"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "GPIO45"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "GPIO46"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "CCU_UTXD_AO"),
+ MTK_FUNCTION(5, "TP_UCTS1_AO"),
+ MTK_FUNCTION(6, "IDDIG"),
+ MTK_FUNCTION(7, "I2S5_LRCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "GPIO47"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "CCU_URXD_AO"),
+ MTK_FUNCTION(5, "TP_URTS1_AO"),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "I2S5_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "GPIO48"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SCL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "GPIO49"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SDA5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "GPIO50"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SCL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "GPIO51"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SDA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "GPIO52"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "BPI_ANT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "GPIO53"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "BPI_ANT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "GPIO54"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "BPI_OLAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "GPIO55"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "BPI_BUS8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "GPIO56"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "BPI_BUS9"),
+ MTK_FUNCTION(2, "SCL_6306")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "GPIO57"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "BPI_BUS10"),
+ MTK_FUNCTION(2, "SDA_6306")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "GPIO58"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D2"),
+ MTK_FUNCTION(2, "SPM_BSI_D2"),
+ MTK_FUNCTION(3, "PWM_B")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "GPIO59"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D1"),
+ MTK_FUNCTION(2, "SPM_BSI_D1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "GPIO60"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D0"),
+ MTK_FUNCTION(2, "SPM_BSI_D0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "GPIO61"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "GPIO62"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "GPIO63"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "GPIO64"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MIPI0_SCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "GPIO65"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MIPI3_SDATA"),
+ MTK_FUNCTION(2, "BPI_OLAT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "GPIO66"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MIPI3_SCLK"),
+ MTK_FUNCTION(2, "BPI_OLAT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "GPIO67"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "MIPI2_SDATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "GPIO68"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "MIPI2_SCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "GPIO69"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "BPI_BUS7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "GPIO70"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 70),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "BPI_BUS6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "GPIO71"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "BPI_BUS5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "GPIO72"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "BPI_BUS4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "GPIO73"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "BPI_BUS3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "GPIO74"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "BPI_BUS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "GPIO75"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "BPI_BUS1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "GPIO76"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "BPI_BUS0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "GPIO77"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "BPI_ANT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "GPIO78"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "BPI_OLAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "GPIO79"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "BPI_PA_VM1"),
+ MTK_FUNCTION(2, "MIPI4_SDATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "GPIO80"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "BPI_PA_VM0"),
+ MTK_FUNCTION(2, "MIPI4_SCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "GPIO81"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "GPIO82"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "GPIO83"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "GPIO84"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "GPIO85"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "SPI0_MI"),
+ MTK_FUNCTION(2, "SCP_SPI0_MI"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "I2S1_BCK"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDO"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "JTDO_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "GPIO86"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "SPI0_CSB"),
+ MTK_FUNCTION(2, "SCP_SPI0_CS"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "I2S1_LRCK"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TMS"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "JTMS_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "GPIO87"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "SPI0_MO"),
+ MTK_FUNCTION(2, "SCP_SPI0_MO"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDI"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "JTDI_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "GPIO88"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "SPI0_CLK"),
+ MTK_FUNCTION(2, "SCP_SPI0_CK"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "I2S1_MCK"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TCK"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "JTCK_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "GPIO89"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "SRCLKENAI0"),
+ MTK_FUNCTION(2, "PWM_C"),
+ MTK_FUNCTION(3, "I2S5_BCK"),
+ MTK_FUNCTION(4, "ANT_SEL6"),
+ MTK_FUNCTION(5, "SDA8"),
+ MTK_FUNCTION(6, "CMVREF0"),
+ MTK_FUNCTION(7, "DBG_MON_A21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "GPIO90"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "PWM_A"),
+ MTK_FUNCTION(2, "CMMCLK2"),
+ MTK_FUNCTION(3, "I2S5_LRCK"),
+ MTK_FUNCTION(4, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(5, "SCL8"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "DBG_MON_A22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "GPIO91"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "KPROW1"),
+ MTK_FUNCTION(2, "PWM_B"),
+ MTK_FUNCTION(3, "I2S5_DO"),
+ MTK_FUNCTION(4, "ANT_SEL7"),
+ MTK_FUNCTION(5, "CMMCLK3"),
+ MTK_FUNCTION(6, "PTA_TXD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "GPIO92"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "KPROW0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "GPIO93"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "KPCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_B27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "GPIO94"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "KPCOL1"),
+ MTK_FUNCTION(2, "I2S2_DI2"),
+ MTK_FUNCTION(3, "I2S5_MCK"),
+ MTK_FUNCTION(4, "CMMCLK2"),
+ MTK_FUNCTION(5, "SCP_SPI2_MI"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "SPI2_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "GPIO95"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "MD_URXD0"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
+ MTK_FUNCTION(6, "CCU_URXD_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "GPIO96"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "MD_UTXD0"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(6, "CCU_UTXD_AO"),
+ MTK_FUNCTION(7, "DBG_MON_B2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "GPIO97"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "UCTS0"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(4, "CONN_MCU_TDO"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(6, "IO_JTAG_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_B3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "GPIO98"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "URTS0"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(3, "USB_DRVVBUS"),
+ MTK_FUNCTION(4, "CONN_MCU_TMS"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(6, "IO_JTAG_TMS"),
+ MTK_FUNCTION(7, "DBG_MON_B4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "GPIO99"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(7, "DBG_MON_B28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "GPIO100"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "PWM_C"),
+ MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "DBG_MON_B29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "GPIO101"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "CMVREF1"),
+ MTK_FUNCTION(4, "CONN_MCU_TCK"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(6, "IO_JTAG_TCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "GPIO102"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(4, "CONN_MCU_TDI"),
+ MTK_FUNCTION(5, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(6, "IO_JTAG_TDI"),
+ MTK_FUNCTION(7, "DBG_MON_B8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "GPIO103"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "GPIO104"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "GPIO105"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "SCL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "GPIO106"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "SDA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "GPIO107"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "DMIC_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SDA7"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "PWM_A"),
+ MTK_FUNCTION(7, "DBG_MON_B12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "GPIO108"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "CMMCLK2"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "SCL8"),
+ MTK_FUNCTION(5, "DAP_MD32_SWD"),
+ MTK_FUNCTION(6, "PWM_B"),
+ MTK_FUNCTION(7, "DBG_MON_B13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "GPIO109"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "DMIC_DAT"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "SDA8"),
+ MTK_FUNCTION(5, "DAP_MD32_SWCK"),
+ MTK_FUNCTION(6, "PWM_C"),
+ MTK_FUNCTION(7, "DBG_MON_B14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "GPIO110"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "SCL7"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "TP_URXD1_AO"),
+ MTK_FUNCTION(4, "USB_DRVVBUS"),
+ MTK_FUNCTION(5, "SRCLKENAI1"),
+ MTK_FUNCTION(6, "KPCOL2"),
+ MTK_FUNCTION(7, "URXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "GPIO111"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "CMMCLK3"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SRCLKENAI0"),
+ MTK_FUNCTION(4, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(7, "DVFSRC_EXT_REQ")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "GPIO112"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "SDA7"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(3, "TP_UTXD1_AO"),
+ MTK_FUNCTION(4, "IDDIG"),
+ MTK_FUNCTION(5, "AGPS_SYNC"),
+ MTK_FUNCTION(6, "KPROW2"),
+ MTK_FUNCTION(7, "UTXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "GPIO113"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "AUXIF_CLK0"),
+ MTK_FUNCTION(6, "TP_UCTS1_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "GPIO114"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "AUXIF_ST0"),
+ MTK_FUNCTION(6, "TP_URTS1_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "GPIO115"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "CONN_BT_CLK"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "PTA_TXD"),
+ MTK_FUNCTION(4, "AUXIF_CLK1"),
+ MTK_FUNCTION(5, "DAP_MD32_SWD"),
+ MTK_FUNCTION(6, "TP_UTXD1_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "GPIO116"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "CONN_BT_DATA"),
+ MTK_FUNCTION(2, "IPU_JTAG_TRST"),
+ MTK_FUNCTION(4, "AUXIF_ST1"),
+ MTK_FUNCTION(5, "DAP_MD32_SWCK"),
+ MTK_FUNCTION(6, "TP_URXD2_AO"),
+ MTK_FUNCTION(7, "DBG_MON_A0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "GPIO117"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "CONN_WF_HB0"),
+ MTK_FUNCTION(2, "IPU_JTAG_TDO"),
+ MTK_FUNCTION(6, "TP_UTXD2_AO"),
+ MTK_FUNCTION(7, "DBG_MON_A4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "GPIO118"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "CONN_WF_HB1"),
+ MTK_FUNCTION(2, "IPU_JTAG_TDI"),
+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
+ MTK_FUNCTION(6, "TP_UCTS2_AO"),
+ MTK_FUNCTION(7, "DBG_MON_A5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "GPIO119"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "CONN_WF_HB2"),
+ MTK_FUNCTION(2, "IPU_JTAG_TCK"),
+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(6, "TP_URTS2_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "GPIO120"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "CONN_WB_PTA"),
+ MTK_FUNCTION(2, "IPU_JTAG_TMS"),
+ MTK_FUNCTION(5, "CCU_URXD_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "GPIO121"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "CONN_HRST_B"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "PTA_RXD"),
+ MTK_FUNCTION(5, "CCU_UTXD_AO"),
+ MTK_FUNCTION(6, "TP_URXD1_AO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "GPIO122"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(2, "SSPM_URXD2_AO"),
+ MTK_FUNCTION(3, "ANT_SEL1"),
+ MTK_FUNCTION(7, "DBG_MON_A12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "GPIO123"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(3, "ANT_SEL0"),
+ MTK_FUNCTION(7, "DBG_MON_A13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "GPIO124"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_A14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "GPIO125"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(3, "MRG_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_A15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "GPIO126"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(3, "ANT_SEL5"),
+ MTK_FUNCTION(6, "UFS_MPHY_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "GPIO127"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(3, "ANT_SEL4"),
+ MTK_FUNCTION(6, "UFS_MPHY_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "GPIO128"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(3, "ANT_SEL2"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "GPIO129"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(3, "ANT_SEL3"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "GPIO130"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(3, "MRG_DO"),
+ MTK_FUNCTION(7, "DBG_MON_A24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "GPIO131"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "MSDC0_DSL"),
+ MTK_FUNCTION(3, "MRG_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "GPIO132"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(3, "MRG_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "GPIO133"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(3, "AGPS_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "GPIO134"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "GPIO135"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "GPIO136"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(2, "AUD_CLK_MISO"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "GPIO137"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(2, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(3, "I2S1_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "GPIO138"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 138),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "GPIO139"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 139),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(6, "UFS_MPHY_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "GPIO140"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 140),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "AUD_CLK_MISO"),
+ MTK_FUNCTION(2, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(3, "I2S0_MCK"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "GPIO141"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 141),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(3, "I2S0_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "GPIO142"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 142),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(3, "I2S0_LRCK"),
+ MTK_FUNCTION(4, "VOW_DAT_MISO"),
+ MTK_FUNCTION(7, "DBG_MON_B25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "GPIO143"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 143),
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(3, "I2S0_DI"),
+ MTK_FUNCTION(4, "VOW_CLK_MISO"),
+ MTK_FUNCTION(6, "UFS_MPHY_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_B26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "GPIO144"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 144),
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "GPIO145"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 145),
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "GPIO146"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 146),
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "GPIO147"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 147),
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "GPIO148"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 148),
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "GPIO149"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 149),
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "GPIO150"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 150),
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "PWM_A"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(7, "DBG_MON_B30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "GPIO151"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 151),
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "PWM_B"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(7, "DBG_MON_B20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "GPIO152"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 152),
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "PWM_C"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(7, "DBG_MON_B21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "GPIO153"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 153),
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "PWM_A"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(7, "DBG_MON_B22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "GPIO154"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 154),
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(7, "DBG_MON_B18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "GPIO155"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 155),
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(3, "CMVREF1"),
+ MTK_FUNCTION(7, "SCP_JTAG_TDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "GPIO156"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 156),
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "ANT_SEL1"),
+ MTK_FUNCTION(2, "SRCLKENAI0"),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "KPCOL2"),
+ MTK_FUNCTION(5, "IDDIG"),
+ MTK_FUNCTION(7, "SCP_JTAG_TCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "GPIO157"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 157),
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "SRCLKENAI1"),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "KPROW2"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "SCP_JTAG_TRSTN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "GPIO158"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 158),
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "GPIO159"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 159),
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "GPIO160"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 160),
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "ANT_SEL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "GPIO161"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 161),
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "SPI1_A_MI"),
+ MTK_FUNCTION(2, "SCP_SPI1_MI"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(4, "ANT_SEL6"),
+ MTK_FUNCTION(5, "KPCOL2"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "DBG_MON_B19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "GPIO162"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 162),
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "SPI1_A_CSB"),
+ MTK_FUNCTION(2, "SCP_SPI1_CS"),
+ MTK_FUNCTION(3, "USB_DRVVBUS"),
+ MTK_FUNCTION(4, "ANT_SEL5"),
+ MTK_FUNCTION(5, "KPROW2"),
+ MTK_FUNCTION(6, "PTA_TXD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "GPIO163"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 163),
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "SPI1_A_MO"),
+ MTK_FUNCTION(2, "SCP_SPI1_MO"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "ANT_SEL4"),
+ MTK_FUNCTION(5, "CMMCLK2"),
+ MTK_FUNCTION(6, "DMIC_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "GPIO164"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 164),
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "SPI1_A_CLK"),
+ MTK_FUNCTION(2, "SCP_SPI1_CK"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "ANT_SEL3"),
+ MTK_FUNCTION(5, "CMMCLK3"),
+ MTK_FUNCTION(6, "DMIC_DAT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "GPIO165"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 165),
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "PWM_B"),
+ MTK_FUNCTION(2, "CMMCLK2"),
+ MTK_FUNCTION(3, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(6, "TDM_MCK_2ND"),
+ MTK_FUNCTION(7, "SCP_JTAG_TDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "GPIO166"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 166),
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "ANT_SEL6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "GPIO167"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 167),
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "RFIC0_BSI_EN"),
+ MTK_FUNCTION(2, "SPM_BSI_EN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "GPIO168"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 168),
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "RFIC0_BSI_CK"),
+ MTK_FUNCTION(2, "SPM_BSI_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "GPIO169"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 169),
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "PWM_C"),
+ MTK_FUNCTION(2, "CMMCLK3"),
+ MTK_FUNCTION(3, "CMVREF1"),
+ MTK_FUNCTION(4, "ANT_SEL7"),
+ MTK_FUNCTION(5, "AGPS_SYNC"),
+ MTK_FUNCTION(6, "TDM_BCK_2ND"),
+ MTK_FUNCTION(7, "SCP_JTAG_TMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "GPIO170"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 170),
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(3, "SCL7"),
+ MTK_FUNCTION(4, "I2S5_BCK"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "TDM_LRCK_2ND"),
+ MTK_FUNCTION(7, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "GPIO171"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 184),
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(2, "I2S3_LRCK"),
+ MTK_FUNCTION(3, "SDA7"),
+ MTK_FUNCTION(4, "I2S5_LRCK"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "TDM_DATA0_2ND"),
+ MTK_FUNCTION(7, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "GPIO172"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 185),
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "I2S1_DO"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(3, "SCL8"),
+ MTK_FUNCTION(4, "I2S5_DO"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "TDM_DATA1_2ND"),
+ MTK_FUNCTION(7, "ANT_SEL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "GPIO173"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 186),
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "I2S1_MCK"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(3, "SDA8"),
+ MTK_FUNCTION(4, "I2S5_MCK"),
+ MTK_FUNCTION(5, "UCTS0"),
+ MTK_FUNCTION(6, "TDM_DATA2_2ND"),
+ MTK_FUNCTION(7, "ANT_SEL6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "GPIO174"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 187),
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "I2S2_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(4, "I2S2_DI2"),
+ MTK_FUNCTION(5, "URTS0"),
+ MTK_FUNCTION(6, "TDM_DATA3_2ND"),
+ MTK_FUNCTION(7, "ANT_SEL7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "GPIO175"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 188),
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "ANT_SEL7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "GPIO176"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 189),
+ MTK_FUNCTION(0, "GPIO176")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "GPIO177"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 190),
+ MTK_FUNCTION(0, "GPIO177")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "GPIO178"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 191),
+ MTK_FUNCTION(0, "GPIO178")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "GPIO179"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 192),
+ MTK_FUNCTION(0, "GPIO179")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "GPIO180"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 171),
+ MTK_FUNCTION(0, "GPIO180")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "GPIO181"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 172),
+ MTK_FUNCTION(0, "GPIO181")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "GPIO182"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 173),
+ MTK_FUNCTION(0, "GPIO182")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "GPIO183"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 174),
+ MTK_FUNCTION(0, "GPIO183")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "GPIO184"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 175),
+ MTK_FUNCTION(0, "GPIO184")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "GPIO185"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 177),
+ MTK_FUNCTION(0, "GPIO185")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "GPIO186"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 178),
+ MTK_FUNCTION(0, "GPIO186")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "GPIO187"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 179),
+ MTK_FUNCTION(0, "GPIO187")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "GPIO188"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 180),
+ MTK_FUNCTION(0, "GPIO188")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "GPIO189"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 181),
+ MTK_FUNCTION(0, "GPIO189")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "GPIO190"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 182),
+ MTK_FUNCTION(0, "GPIO190")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "GPIO191"),
+ NULL, "mt8183",
+ MTK_EINT_FUNCTION(0, 183),
+ MTK_FUNCTION(0, "GPIO191")
+ ),
+};
+
+
+#endif /* __PINCTRL-MTK-MT8183_H */
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.c b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.c
new file mode 100644
index 0000000..7104c7f
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -0,0 +1,1018 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
+ * bindings for MediaTek SoC.
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ * Zhiyong Tao <zhiyong.tao@mediatek.com>
+ * Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ */
+
+#include <linux/gpio/driver.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include "pinctrl-paris.h"
+
+#include "pinctrl-mtk-common-v2_debug.h"
+
+#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
+
+/* Custom pinconf parameters */
+#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
+#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
+#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
+#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
+
+static const struct pinconf_generic_params mtk_custom_bindings[] = {
+ {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
+ {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
+ {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
+ {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item mtk_conf_items[] = {
+ PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
+ PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
+ PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
+ PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
+};
+#endif
+
+static const char * const mtk_gpio_functions[] = {
+ "func0", "func1", "func2", "func3",
+ "func4", "func5", "func6", "func7",
+ "func8", "func9", "func10", "func11",
+ "func12", "func13", "func14", "func15",
+};
+
+static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ const struct mtk_pin_desc *desc;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+ hw->soc->gpio_m);
+}
+
+static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ const struct mtk_pin_desc *desc;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+ /* hardware would take 0 as input direction */
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
+}
+
+static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ u32 param = pinconf_to_config_param(*config);
+ int val, val2, err, reg, ret = 1;
+ const struct mtk_pin_desc *desc;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (hw->soc->bias_disable_get) {
+ err = hw->soc->bias_disable_get(hw, desc, &ret);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (hw->soc->bias_get) {
+ err = hw->soc->bias_get(hw, desc, 1, &ret);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (hw->soc->bias_get) {
+ err = hw->soc->bias_get(hw, desc, 0, &ret);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
+ if (err)
+ return err;
+
+ if (!val)
+ return -EINVAL;
+
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
+ if (err)
+ return err;
+
+ /* HW takes input mode as zero; output mode as non-zero */
+ if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
+ (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
+ return -EINVAL;
+
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
+ if (err)
+ return err;
+
+ if (val || !val2)
+ return -EINVAL;
+
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (hw->soc->drive_get) {
+ err = hw->soc->drive_get(hw, desc, &ret);
+ if (err)
+ return err;
+ } else {
+ err = -ENOTSUPP;
+ }
+ break;
+ case MTK_PIN_CONFIG_TDSEL:
+ case MTK_PIN_CONFIG_RDSEL:
+ reg = (param == MTK_PIN_CONFIG_TDSEL) ?
+ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
+
+ err = mtk_hw_get_value(hw, desc, reg, &val);
+ if (err)
+ return err;
+
+ ret = val;
+
+ break;
+ case MTK_PIN_CONFIG_PU_ADV:
+ case MTK_PIN_CONFIG_PD_ADV:
+ if (hw->soc->adv_pull_get) {
+ bool pullup;
+
+ pullup = param == MTK_PIN_CONFIG_PU_ADV;
+ err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, ret);
+
+ return 0;
+}
+
+static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ const struct mtk_pin_desc *desc;
+ int err = 0;
+ u32 reg;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+ switch ((u32)param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (hw->soc->bias_disable_set) {
+ err = hw->soc->bias_disable_set(hw, desc);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (hw->soc->bias_set) {
+ err = hw->soc->bias_set(hw, desc, 1);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (hw->soc->bias_set) {
+ err = hw->soc->bias_set(hw, desc, 0);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
+ MTK_DISABLE);
+ if (err)
+ goto err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+ MTK_OUTPUT);
+ if (err)
+ goto err;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (hw->soc->ies_present) {
+ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
+ MTK_ENABLE);
+ }
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+ MTK_INPUT);
+ if (err)
+ goto err;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
+ arg);
+ if (err)
+ goto err;
+
+ break;
+ case PIN_CONFIG_OUTPUT:
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+ MTK_OUTPUT);
+ if (err)
+ goto err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
+ arg);
+ if (err)
+ goto err;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ /* arg = 1: Input mode & SMT enable ;
+ * arg = 0: Output mode & SMT disable
+ */
+ arg = arg ? 2 : 1;
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+ arg & 1);
+ if (err)
+ goto err;
+
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
+ !!(arg & 2));
+ if (err)
+ goto err;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (hw->soc->drive_set) {
+ err = hw->soc->drive_set(hw, desc, arg);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case MTK_PIN_CONFIG_TDSEL:
+ case MTK_PIN_CONFIG_RDSEL:
+ reg = (param == MTK_PIN_CONFIG_TDSEL) ?
+ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
+
+ err = mtk_hw_set_value(hw, desc, reg, arg);
+ if (err)
+ goto err;
+ break;
+ case MTK_PIN_CONFIG_PU_ADV:
+ case MTK_PIN_CONFIG_PD_ADV:
+ if (hw->soc->adv_pull_set) {
+ bool pullup;
+
+ pullup = param == MTK_PIN_CONFIG_PU_ADV;
+ err = hw->soc->adv_pull_set(hw, desc, pullup,
+ arg);
+ if (err)
+ return err;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ default:
+ err = -ENOTSUPP;
+ }
+
+err:
+ return err;
+}
+
+static struct mtk_pinctrl_group *
+mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < hw->soc->ngrps; i++) {
+ struct mtk_pinctrl_group *grp = hw->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static const struct mtk_func_desc *
+mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
+{
+ const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
+ const struct mtk_func_desc *func = pin->funcs;
+
+ while (func && func->name) {
+ if (func->muxval == fnum)
+ return func;
+ func++;
+ }
+
+ return NULL;
+}
+
+static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
+ u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < hw->soc->npins; i++) {
+ const struct mtk_pin_desc *pin = hw->soc->pins + i;
+
+ if (pin->number == pin_num) {
+ const struct mtk_func_desc *func = pin->funcs;
+
+ while (func && func->name) {
+ if (func->muxval == fnum)
+ return true;
+ func++;
+ }
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
+ u32 pin, u32 fnum,
+ struct mtk_pinctrl_group *grp,
+ struct pinctrl_map **map,
+ unsigned int *reserved_maps,
+ unsigned int *num_maps)
+{
+ bool ret;
+
+ if (*num_maps == *reserved_maps)
+ return -ENOSPC;
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned int *reserved_maps,
+ unsigned int *num_maps)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ int num_pins, num_funcs, maps_per_pin, i, err;
+ struct mtk_pinctrl_group *grp;
+ unsigned int num_configs;
+ bool has_config = false;
+ unsigned long *configs;
+ u32 pinfunc, pin, func;
+ struct property *pins;
+ unsigned int reserve = 0;
+
+ pins = of_find_property(node, "pinmux", NULL);
+ if (!pins) {
+ dev_err(hw->dev, "missing pins property in node %pOFn .\n",
+ node);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
+ &num_configs);
+ if (err)
+ return err;
+
+ if (num_configs)
+ has_config = true;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ reserve = num_pins * maps_per_pin;
+
+ err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
+ reserve);
+ if (err < 0)
+ goto exit;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
+ if (err)
+ goto exit;
+
+ pin = MTK_GET_PIN_NO(pinfunc);
+ func = MTK_GET_PIN_FUNC(pinfunc);
+
+ if (pin >= hw->soc->npins ||
+ func >= ARRAY_SIZE(mtk_gpio_functions)) {
+ dev_err(hw->dev, "invalid pins value.\n");
+ err = -EINVAL;
+ goto exit;
+ }
+
+ grp = mtk_pctrl_find_group_by_pin(hw, pin);
+ if (!grp) {
+ dev_err(hw->dev, "unable to match pin %d to group\n",
+ pin);
+ err = -EINVAL;
+ goto exit;
+ }
+
+ err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
+ reserved_maps, num_maps);
+ if (err < 0)
+ goto exit;
+
+ if (has_config) {
+ err = pinctrl_utils_add_map_configs(pctldev, map,
+ reserved_maps,
+ num_maps,
+ grp->name,
+ configs,
+ num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (err < 0)
+ goto exit;
+ }
+ }
+
+ err = 0;
+
+exit:
+ kfree(configs);
+ return err;
+}
+
+static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct device_node *np;
+ unsigned int reserved_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ reserved_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
+ &reserved_maps,
+ num_maps);
+ if (ret < 0) {
+ pinctrl_utils_free_map(pctldev, *map, *num_maps);
+ of_node_put(np);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+
+ return hw->soc->ngrps;
+}
+
+static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+
+ return hw->groups[group].name;
+}
+
+static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group, const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned int *)&hw->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
+{
+ const struct mtk_pin_desc *desc;
+ int value, err;
+
+ if (gpio > hw->soc->npins)
+ return -EINVAL;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+ err = mtk_hw_get_value(hw, desc, field, &value);
+ if (err)
+ return err;
+
+ return value;
+}
+
+ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
+ unsigned int gpio, char *buf, unsigned int bufLen)
+{
+ const struct mtk_pin_desc *desc;
+ int pinmux, pullup = -1, pullen = -1, r1 = -1, r0 = -1, len = 0;
+
+ if (gpio > hw->soc->npins)
+ return -EINVAL;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+ pinmux = mtk_pctrl_get_pinmux(hw, gpio);
+ if (pinmux >= hw->soc->nfuncs)
+ pinmux -= hw->soc->nfuncs;
+
+ mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
+ if (pullen == MTK_PUPD_SET_R1R0_00) {
+ pullen = 0;
+ r1 = 0;
+ r0 = 0;
+ } else if (pullen == MTK_PUPD_SET_R1R0_01) {
+ pullen = 1;
+ r1 = 0;
+ r0 = 1;
+ } else if (pullen == MTK_PUPD_SET_R1R0_10) {
+ pullen = 1;
+ r1 = 1;
+ r0 = 0;
+ } else if (pullen == MTK_PUPD_SET_R1R0_11) {
+ pullen = 1;
+ r1 = 1;
+ r0 = 1;
+ } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
+ pullen = 0;
+ }
+ len += snprintf(buf + len, bufLen - len,
+ "%03d: %1d%1d%1d%1d-%02d-%1d%1d-%1d%1d",
+ gpio,
+ pinmux,
+ mtk_pctrl_get_direction(hw, gpio),
+ mtk_pctrl_get_out(hw, gpio),
+ mtk_pctrl_get_in(hw, gpio),
+ mtk_pctrl_get_driving(hw, gpio),
+ mtk_pctrl_get_smt(hw, gpio),
+ mtk_pctrl_get_ies(hw, gpio),
+ pullen,
+ pullup);
+
+ if (r1 != -1) {
+ len += snprintf(buf + len, bufLen - len, " [%1d %1d]\n",
+ r1, r0);
+ } else {
+ len += snprintf(buf + len, bufLen - len, "\n");
+ }
+
+ return len;
+}
+
+#define PIN_DBG_BUF_SZ 96
+static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned int gpio)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ char buf[PIN_DBG_BUF_SZ];
+
+ (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
+
+ seq_printf(s, "%s", buf);
+}
+
+static const struct pinctrl_ops mtk_pctlops = {
+ .dt_node_to_map = mtk_pctrl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
+ .get_groups_count = mtk_pctrl_get_groups_count,
+ .get_group_name = mtk_pctrl_get_group_name,
+ .get_group_pins = mtk_pctrl_get_group_pins,
+ .pin_dbg_show = mtk_pctrl_dbg_show,
+};
+
+static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mtk_gpio_functions);
+}
+
+static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return mtk_gpio_functions[selector];
+}
+
+static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = hw->grp_names;
+ *num_groups = hw->soc->ngrps;
+
+ return 0;
+}
+
+static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *grp = hw->groups + group;
+ const struct mtk_func_desc *desc_func;
+ const struct mtk_pin_desc *desc;
+ bool ret;
+
+ ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
+ if (!ret) {
+ dev_err(hw->dev, "invalid function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
+ if (!desc_func)
+ return -EINVAL;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
+ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
+
+ return 0;
+}
+
+static const struct pinmux_ops mtk_pmxops = {
+ .get_functions_count = mtk_pmx_get_funcs_cnt,
+ .get_function_name = mtk_pmx_get_func_name,
+ .get_function_groups = mtk_pmx_get_func_groups,
+ .set_mux = mtk_pmx_set_mux,
+ .gpio_set_direction = mtk_pinmux_gpio_set_direction,
+ .gpio_request_enable = mtk_pinmux_gpio_request_enable,
+};
+
+static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned int group,
+ unsigned long *config)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = hw->groups[group].config;
+
+ return 0;
+}
+
+static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int group,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *grp = &hw->groups[group];
+ int i, ret;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = mtk_pinconf_set(pctldev, grp->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+
+ grp->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops mtk_confops = {
+ .pin_config_get = mtk_pinconf_get,
+ .pin_config_group_get = mtk_pconf_group_get,
+ .pin_config_group_set = mtk_pconf_group_set,
+ .is_generic = true,
+};
+
+static struct pinctrl_desc mtk_desc = {
+ .name = PINCTRL_PINCTRL_DEV,
+ .pctlops = &mtk_pctlops,
+ .pmxops = &mtk_pmxops,
+ .confops = &mtk_confops,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+ int value, err;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
+ if (err)
+ return err;
+
+ return !value;
+}
+
+static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+ int value, err;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
+ if (err)
+ return err;
+
+ return !!value;
+}
+
+static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
+}
+
+static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
+{
+ return pinctrl_gpio_direction_input(chip->base + gpio);
+}
+
+static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
+ int value)
+{
+ mtk_gpio_set(chip, gpio, value);
+
+ return pinctrl_gpio_direction_output(chip->base + gpio);
+}
+
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+
+ if (!hw->eint)
+ return -ENOTSUPP;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+
+ if (desc->eint.eint_n == EINT_NA)
+ return -ENOTSUPP;
+
+ return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
+}
+
+static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+ const struct mtk_pin_desc *desc;
+ u32 debounce;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+
+ if (!hw->eint ||
+ pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
+ desc->eint.eint_n == EINT_NA)
+ return -ENOTSUPP;
+
+ debounce = pinconf_to_config_argument(config);
+
+ return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
+}
+
+static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
+{
+ struct gpio_chip *chip = &hw->chip;
+ int ret;
+
+ chip->label = PINCTRL_PINCTRL_DEV;
+ chip->parent = hw->dev;
+ chip->request = gpiochip_generic_request;
+ chip->free = gpiochip_generic_free;
+ chip->get_direction = mtk_gpio_get_direction;
+ chip->direction_input = mtk_gpio_direction_input;
+ chip->direction_output = mtk_gpio_direction_output;
+ chip->get = mtk_gpio_get;
+ chip->set = mtk_gpio_set;
+ chip->to_irq = mtk_gpio_to_irq,
+ chip->set_config = mtk_gpio_set_config,
+ chip->base = -1;
+ chip->ngpio = hw->soc->npins;
+ chip->of_node = np;
+ chip->of_gpio_n_cells = 2;
+
+ ret = gpiochip_add_data(chip, hw);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int mtk_pctrl_build_state(struct platform_device *pdev)
+{
+ struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
+ int i;
+
+ /* Allocate groups */
+ hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
+ sizeof(*hw->groups), GFP_KERNEL);
+ if (!hw->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
+ sizeof(*hw->grp_names), GFP_KERNEL);
+ if (!hw->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < hw->soc->npins; i++) {
+ const struct mtk_pin_desc *pin = hw->soc->pins + i;
+ struct mtk_pinctrl_group *group = hw->groups + i;
+
+ group->name = pin->name;
+ group->pin = pin->number;
+
+ hw->grp_names[i] = pin->name;
+ }
+
+ return 0;
+}
+
+//tianyan@2021.10.20 modify for RI gpio start
+void mtk_paris_pinctrl_init_kernel(struct mtk_pinctrl *hw)
+{
+ const struct mtk_pin_desc *desc;
+
+ printk("mtk_paris_pinctrl_init_kernel\n");
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[63];
+ mtk_hw_set_value(hw, desc, 0, 0);
+}
+//tianyan@2021.10.20 modify for RI gpio end
+
+int mtk_paris_pinctrl_probe(struct platform_device *pdev,
+ const struct mtk_pin_soc *soc)
+{
+ struct pinctrl_pin_desc *pins;
+ struct mtk_pinctrl *hw;
+ struct resource *res;
+ int err, i;
+
+ hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
+ if (!hw)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, hw);
+ hw->soc = soc;
+ hw->dev = &pdev->dev;
+
+ if (!hw->soc->nbase_names) {
+ dev_err(&pdev->dev,
+ "SoC should be assigned at least one register base\n");
+ return -EINVAL;
+ }
+
+ hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
+ sizeof(*hw->base), GFP_KERNEL);
+ if (!hw->base)
+ return -ENOMEM;
+
+ for (i = 0; i < hw->soc->nbase_names; i++) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ hw->soc->base_names[i]);
+ if (!res) {
+ dev_err(&pdev->dev, "missing IO resource\n");
+ return -ENXIO;
+ }
+
+ hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hw->base[i]))
+ return PTR_ERR(hw->base[i]);
+ }
+
+ hw->nbase = hw->soc->nbase_names;
+
+ err = mtk_pctrl_build_state(pdev);
+ if (err) {
+ dev_err(&pdev->dev, "build state failed: %d\n", err);
+ return -EINVAL;
+ }
+
+ /* Copy from internal struct mtk_pin_desc to register to the core */
+ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < hw->soc->npins; i++) {
+ pins[i].number = hw->soc->pins[i].number;
+ pins[i].name = hw->soc->pins[i].name;
+ }
+
+ /* Setup pins descriptions per SoC types */
+ mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
+ mtk_desc.npins = hw->soc->npins;
+ mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
+ mtk_desc.custom_params = mtk_custom_bindings;
+#ifdef CONFIG_DEBUG_FS
+ mtk_desc.custom_conf_items = mtk_conf_items;
+#endif
+
+ err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
+ &hw->pctrl);
+ if (err)
+ return err;
+
+ err = pinctrl_enable(hw->pctrl);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DEBUG_FS
+ if (mtk_gpio_create_attr(&pdev->dev))
+ pr_info("[pinctrl]mtk_gpio create attribute error\n");
+#endif
+
+ err = mtk_build_eint(hw, pdev);
+ if (err)
+ dev_warn(&pdev->dev,
+ "Failed to add EINT, but pinctrl still can work\n");
+
+ /* Build gpiochip should be after pinctrl_enable is done */
+ err = mtk_build_gpiochip(hw, pdev->dev.of_node);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to add gpio_chip\n");
+ return err;
+ }
+
+ platform_set_drvdata(pdev, hw);
+
+//tianyan@2021.10.20 modify for RI gpio start
+ mtk_paris_pinctrl_init_kernel(hw);
+//tianyan@2021.10.20 modify for RI gpio end
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.h b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.h
new file mode 100644
index 0000000..5abde00
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/pinctrl/mediatek/pinctrl-paris.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ * Zhiyong Tao <zhiyong.tao@mediatek.com>
+ * Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ */
+#ifndef __PINCTRL_PARIS_H
+#define __PINCTRL_PARIS_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "mtk-eint.h"
+#include "pinctrl-mtk-common-v2.h"
+
+#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
+
+#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \
+ { \
+ .eint_m = _eintmux, \
+ .eint_n = _eintnum, \
+ }
+
+#define MTK_FUNCTION(_val, _name) \
+ { \
+ .muxval = _val, \
+ .name = _name, \
+ }
+
+#define MTK_PIN(_number, _name, _eint, _drv_n, ...) { \
+ .number = _number, \
+ .name = _name, \
+ .eint = _eint, \
+ .drv_n = _drv_n, \
+ .funcs = (struct mtk_func_desc[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define PINCTRL_PIN_GROUP(name, id) \
+ { \
+ name, \
+ id##_pins, \
+ ARRAY_SIZE(id##_pins), \
+ id##_funcs, \
+ }
+
+int mtk_paris_pinctrl_probe(struct platform_device *pdev,
+ const struct mtk_pin_soc *soc);
+
+int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field);
+
+#define mtk_pctrl_get_pinmux(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
+
+/* MTK HW use 0 as input, 1 for output
+ * This interface is for get direct register value,
+ * so don't reverse
+ */
+#define mtk_pctrl_get_direction(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
+
+#define mtk_pctrl_get_out(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
+
+#define mtk_pctrl_get_in(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
+
+#define mtk_pctrl_get_smt(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
+
+#define mtk_pctrl_get_ies(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
+
+#define mtk_pctrl_get_driving(hw, gpio) \
+ mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
+
+ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
+ unsigned int gpio, char *buf, unsigned int bufLen);
+
+#endif /* __PINCTRL_PARIS_H */