[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/Kconfig b/src/kernel/linux/v4.14/drivers/soc/mediatek/Kconfig
new file mode 100644
index 0000000..dedd4e7
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,43 @@
+#
+# MediaTek SoC drivers
+#
+config MTK_CMDQ
+ tristate "MediaTek CMDQ Support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select MAILBOX
+ select MTK_CMDQ_MBOX
+ select MTK_INFRACFG
+ help
+ Say yes here to add support for the MediaTek Command Queue (CMDQ)
+ driver. The CMDQ is used to help read/write registers with critical
+ time limitation, such as updating display configuration during the
+ vblank.
+
+config MTK_INFRACFG
+ bool "MediaTek INFRACFG Support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select REGMAP
+ help
+ Say yes here to add support for the MediaTek INFRACFG controller. The
+ INFRACFG controller contains various infrastructure registers not
+ directly associated to any device.
+
+config MTK_PMIC_WRAP
+ tristate "MediaTek PMIC Wrapper Support"
+ select RESET_CONTROLLER
+ select REGMAP
+ help
+ Say yes here to add support for MediaTek PMIC Wrapper found
+ on different MediaTek SoCs. The PMIC wrapper is a proprietary
+ hardware to connect the PMIC.
+
+config MTK_SCPSYS
+ bool "MediaTek SCPSYS Support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ default ARCH_MEDIATEK
+ select REGMAP
+ select MTK_INFRACFG
+ select PM_GENERIC_DOMAINS if PM
+ help
+ Say yes here to add support for the MediaTek SCPSYS power domain
+ driver.
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/Makefile b/src/kernel/linux/v4.14/drivers/soc/mediatek/Makefile
new file mode 100644
index 0000000..3145865
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/Makefile
@@ -0,0 +1,9 @@
+obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
+obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
+obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap-legacy.o
+ifeq ($(CONFIG_MACH_MT2731), y)
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys-variant.o
+else
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
+endif
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-cmdq-helper.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-cmdq-helper.c
new file mode 100644
index 0000000..46b48ae
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+
+#include <linux/completion.h>
+#include <linux/errno.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mailbox_controller.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define CMDQ_GET_ARG_B(arg) (((arg) & GENMASK(31, 16)) >> 16)
+#define CMDQ_GET_ARG_C(arg) ((arg) & GENMASK(15, 0))
+/** conbine the argument b and c to a 32bits balue */
+#define CMDQ_GET_32B_VALUE(arg_b, arg_c) ((u32)((arg_b) << 16) | (arg_c))
+/** get the register index prefix from type */
+#define CMDQ_REG_IDX_PREFIX(type) ((type) ? "" : "Reg Index ")
+/** get operand index or value */
+#define CMDQ_OPERAND_GET_IDX_VALUE(operand) ((operand)->reg ? \
+ (operand)->idx : \
+ (operand)->value)
+#define CMDQ_WRITE_ENABLE_MASK BIT(0)
+#define CMDQ_EOC_IRQ_EN BIT(0)
+#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
+ << 32 | CMDQ_EOC_IRQ_EN)
+#define CMDQ_IMMEDIATE_VALUE 0
+#define CMDQ_REG_TYPE 1
+
+struct cmdq_instruction {
+ s16 arg_c:16;
+ s16 arg_b:16;
+ s16 arg_a:16;
+ u8 s_op:5;
+ u8 arg_c_type:1;
+ u8 arg_b_type:1;
+ u8 arg_a_type:1;
+ u8 op:8;
+};
+
+static void cmdq_pkt_instr_encoder(struct cmdq_pkt *pkt, s16 arg_c, s16 arg_b,
+ s16 arg_a, u8 s_op, u8 arg_c_type,
+ u8 arg_b_type, u8 arg_a_type, u8 op)
+{
+ struct cmdq_instruction *cmdq_inst;
+
+ cmdq_inst = pkt->va_base + pkt->cmd_buf_size;
+ cmdq_inst->op = op;
+ cmdq_inst->arg_a_type = arg_a_type;
+ cmdq_inst->arg_b_type = arg_b_type;
+ cmdq_inst->arg_c_type = arg_c_type;
+ cmdq_inst->s_op = s_op;
+ cmdq_inst->arg_a = arg_a;
+ cmdq_inst->arg_b = arg_b;
+ cmdq_inst->arg_c = arg_c;
+ pkt->cmd_buf_size += CMDQ_INST_SIZE;
+}
+
+static void cmdq_client_timeout(struct timer_list *t)
+{
+ struct cmdq_client *client = from_timer(client, t, timer);
+
+ dev_err(client->client.dev, "cmdq timeout!\n");
+}
+
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout)
+{
+ struct cmdq_client *client;
+
+ client = kzalloc(sizeof(*client), GFP_KERNEL);
+ if (!client)
+ return (struct cmdq_client *)-ENOMEM;
+
+ client->timeout_ms = timeout;
+ if (timeout != CMDQ_NO_TIMEOUT) {
+ spin_lock_init(&client->lock);
+ timer_setup(&client->timer, cmdq_client_timeout, 0);
+ }
+ client->pkt_cnt = 0;
+ client->client.dev = dev;
+ client->client.tx_block = false;
+ client->chan = mbox_request_channel(&client->client, index);
+
+ if (IS_ERR(client->chan)) {
+ long err;
+
+ dev_err(dev, "failed to request channel\n");
+ err = PTR_ERR(client->chan);
+ kfree(client);
+
+ return ERR_PTR(err);
+ }
+
+ return client;
+}
+EXPORT_SYMBOL(cmdq_mbox_create);
+
+void cmdq_mbox_destroy(struct cmdq_client *client)
+{
+ if (client->timeout_ms != CMDQ_NO_TIMEOUT) {
+ spin_lock(&client->lock);
+ del_timer_sync(&client->timer);
+ spin_unlock(&client->lock);
+ }
+ mbox_free_channel(client->chan);
+ kfree(client);
+}
+EXPORT_SYMBOL(cmdq_mbox_destroy);
+
+struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size)
+{
+ struct cmdq_pkt *pkt;
+ struct device *dev;
+ dma_addr_t dma_addr;
+
+ pkt = kzalloc(sizeof(*pkt), GFP_KERNEL);
+ if (!pkt)
+ return ERR_PTR(-ENOMEM);
+ pkt->va_base = kzalloc(size, GFP_KERNEL);
+ if (!pkt->va_base) {
+ kfree(pkt);
+ return ERR_PTR(-ENOMEM);
+ }
+ pkt->buf_size = size;
+ pkt->cl = (void *)client;
+
+ dev = client->chan->mbox->dev;
+ dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, dma_addr)) {
+ dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
+ kfree(pkt->va_base);
+ kfree(pkt);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ pkt->pa_base = dma_addr;
+
+ return pkt;
+}
+EXPORT_SYMBOL(cmdq_pkt_create);
+
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
+{
+ struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
+
+ dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
+ DMA_TO_DEVICE);
+ kfree(pkt->va_base);
+ kfree(pkt);
+}
+EXPORT_SYMBOL(cmdq_pkt_destroy);
+
+static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, s16 arg_c, s16 arg_b,
+ s16 arg_a, u8 s_op, u8 arg_c_type,
+ u8 arg_b_type, u8 arg_a_type,
+ enum cmdq_code code)
+{
+
+ if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
+ /*
+ * In the case of allocated buffer size (pkt->buf_size) is used
+ * up, the real required size (pkt->cmdq_buf_size) is still
+ * increased, so that the user knows how much memory should be
+ * ultimately allocated after appending all commands and
+ * flushing the command packet. Therefor, the user can call
+ * cmdq_pkt_create() again with the real required buffer size.
+ */
+ pkt->cmd_buf_size += CMDQ_INST_SIZE;
+ WARN_ONCE(1, "%s: buffer size %u is too small !\n",
+ __func__, (u32)pkt->buf_size);
+ return -ENOMEM;
+ }
+ cmdq_pkt_instr_encoder(pkt, arg_c, arg_b, arg_a, s_op, arg_c_type,
+ arg_b_type, arg_a_type, code);
+
+ return 0;
+}
+
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
+{
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value),
+ CMDQ_GET_ARG_B(value), offset, subsys,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE, CMDQ_CODE_WRITE);
+}
+EXPORT_SYMBOL(cmdq_pkt_write);
+
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
+ u32 value, u32 mask)
+{
+ u32 offset_mask = offset;
+ int err = 0;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask),
+ CMDQ_GET_ARG_B(~mask),
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_MASK);
+ offset_mask |= CMDQ_WRITE_ENABLE_MASK;
+ }
+ err |= cmdq_pkt_write(pkt, subsys, offset_mask, value);
+
+ return err;
+}
+EXPORT_SYMBOL(cmdq_pkt_write_mask);
+
+int cmdq_pkt_load(struct cmdq_pkt *pkt, u16 dst_reg_idx,
+ u16 indirect_src_reg_idx)
+{
+ return cmdq_pkt_append_command(pkt, 0, indirect_src_reg_idx,
+ dst_reg_idx, 0, CMDQ_IMMEDIATE_VALUE,
+ CMDQ_REG_TYPE, CMDQ_REG_TYPE,
+ CMDQ_CODE_READ_S);
+}
+EXPORT_SYMBOL(cmdq_pkt_load);
+
+int cmdq_pkt_store_reg(struct cmdq_pkt *pkt, u16 indirect_dst_reg_idx,
+ u16 src_reg_idx, u32 mask)
+{
+ int err = 0;
+ enum cmdq_code op = CMDQ_CODE_WRITE_S;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask),
+ CMDQ_GET_ARG_B(~mask), 0, 0, 0, 0,
+ 0, CMDQ_CODE_MASK);
+ if (err != 0)
+ return err;
+
+ op = CMDQ_CODE_WRITE_S_W_MASK;
+ }
+
+ return cmdq_pkt_append_command(pkt, 0, src_reg_idx,
+ indirect_dst_reg_idx, 0,
+ CMDQ_IMMEDIATE_VALUE, CMDQ_REG_TYPE,
+ CMDQ_REG_TYPE, op);
+}
+EXPORT_SYMBOL(cmdq_pkt_store_reg);
+
+int cmdq_pkt_store_value(struct cmdq_pkt *pkt, u16 indirect_dst_reg_idx,
+ u32 value, u32 mask)
+{
+ int err = 0;
+ enum cmdq_code op = CMDQ_CODE_WRITE_S;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask),
+ CMDQ_GET_ARG_B(~mask), 0, 0, 0, 0,
+ 0, CMDQ_CODE_MASK);
+ if (err != 0)
+ return err;
+
+ op = CMDQ_CODE_WRITE_S_W_MASK;
+ }
+
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value),
+ CMDQ_GET_ARG_B(value),
+ indirect_dst_reg_idx, 0,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE, CMDQ_REG_TYPE, op);
+}
+EXPORT_SYMBOL(cmdq_pkt_store_value);
+
+int cmdq_pkt_assign_command(struct cmdq_pkt *pkt, u16 reg_idx, s32 value)
+{
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value),
+ CMDQ_GET_ARG_B(value), reg_idx,
+ CMDQ_LOGIC_ASSIGN, CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE, CMDQ_REG_TYPE,
+ CMDQ_CODE_LOGIC);
+}
+EXPORT_SYMBOL(cmdq_pkt_assign_command);
+
+int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, enum CMDQ_LOGIC_ENUM s_op,
+ u16 result_reg_idx,
+ struct cmdq_operand *left_operand,
+ struct cmdq_operand *right_operand)
+{
+ u32 left_idx_value;
+ u32 right_idx_value;
+
+ if (!left_operand || !right_operand)
+ return -EINVAL;
+
+ left_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(left_operand);
+ right_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(right_operand);
+
+ return cmdq_pkt_append_command(pkt, right_idx_value, left_idx_value,
+ result_reg_idx, s_op, right_operand->reg,
+ left_operand->reg, CMDQ_REG_TYPE,
+ CMDQ_CODE_LOGIC);
+}
+EXPORT_SYMBOL(cmdq_pkt_logic_command);
+
+int cmdq_pkt_jump(struct cmdq_pkt *pkt, s32 addr_offset)
+{
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(addr_offset),
+ CMDQ_GET_ARG_B(addr_offset), 0, 0, 0, 0,
+ 0, CMDQ_CODE_JUMP);
+}
+EXPORT_SYMBOL(cmdq_pkt_jump);
+
+int cmdq_pkt_cond_jump(struct cmdq_pkt *pkt,
+ u16 offset_reg_idx,
+ struct cmdq_operand *left_operand,
+ struct cmdq_operand *right_operand,
+ enum CMDQ_CONDITION_ENUM condition_operator)
+{
+ u32 left_idx_value;
+ u32 right_idx_value;
+
+ if (!left_operand || !right_operand)
+ return -EINVAL;
+
+ left_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(left_operand);
+ right_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(right_operand);
+
+ return cmdq_pkt_append_command(pkt, right_idx_value, left_idx_value,
+ offset_reg_idx, condition_operator,
+ right_operand->reg, left_operand->reg,
+ CMDQ_REG_TYPE,
+ CMDQ_CODE_JUMP_C_RELATIVE);
+}
+EXPORT_SYMBOL(cmdq_pkt_cond_jump);
+
+struct cmdq_operand *cmdq_operand_immediate(struct cmdq_operand *operand,
+ u16 value)
+{
+ if (!operand)
+ return (struct cmdq_operand *)ERR_PTR(-EINVAL);
+
+ operand->reg = false;
+ operand->value = value;
+
+ return operand;
+}
+EXPORT_SYMBOL(cmdq_operand_immediate);
+
+struct cmdq_operand *cmdq_operand_reg(struct cmdq_operand *operand, u16 idx)
+{
+ if (!operand)
+ return (struct cmdq_operand *)ERR_PTR(-EINVAL);
+
+ operand->reg = true;
+ operand->idx = idx;
+
+ return operand;
+}
+EXPORT_SYMBOL(cmdq_operand_reg);
+
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
+{
+ if (event >= CMDQ_MAX_EVENT)
+ return -EINVAL;
+
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_WFE_OPTION),
+ CMDQ_GET_ARG_B(CMDQ_WFE_OPTION), event,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_WFE);
+}
+EXPORT_SYMBOL(cmdq_pkt_wfe);
+
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
+{
+ if (event >= CMDQ_MAX_EVENT)
+ return -EINVAL;
+
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_WFE_UPDATE),
+ CMDQ_GET_ARG_B(CMDQ_WFE_UPDATE), event,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_WFE);
+}
+EXPORT_SYMBOL(cmdq_pkt_clear_event);
+
+int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
+ u16 offset, u32 value, u32 mask)
+{
+ int err;
+
+ if (mask != 0xffffffff) {
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask),
+ CMDQ_GET_ARG_B(~mask),
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_MASK);
+
+ if (err != 0)
+ return err;
+ }
+ offset = offset | 0x1;
+
+ return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value),
+ CMDQ_GET_ARG_B(value),
+ offset, subsys,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_POLL);
+}
+EXPORT_SYMBOL(cmdq_pkt_poll);
+
+static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
+{
+ int err;
+
+ /* insert EOC and generate IRQ for each command iteration */
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_EOC_IRQ_EN),
+ CMDQ_GET_ARG_B(CMDQ_EOC_IRQ_EN),
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_EOC);
+ if (err < 0)
+ return err;
+ /* JUMP to end */
+ err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_JUMP_PASS),
+ CMDQ_GET_ARG_B(CMDQ_JUMP_PASS),
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_IMMEDIATE_VALUE,
+ CMDQ_CODE_JUMP);
+
+ return err;
+}
+
+static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data)
+{
+ struct cmdq_pkt *pkt = (struct cmdq_pkt *)data.data;
+ struct cmdq_task_cb *cb = &pkt->cb;
+ struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
+
+ if (client->timeout_ms != CMDQ_NO_TIMEOUT) {
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(&client->lock, flags);
+ if (--client->pkt_cnt == 0)
+ del_timer(&client->timer);
+ else
+ mod_timer(&client->timer, jiffies +
+ msecs_to_jiffies(client->timeout_ms));
+ spin_unlock_irqrestore(&client->lock, flags);
+ }
+
+ dma_sync_single_for_cpu(client->chan->mbox->dev, pkt->pa_base,
+ pkt->cmd_buf_size, DMA_TO_DEVICE);
+ if (cb->cb) {
+ data.data = cb->data;
+ cb->cb(data);
+ }
+}
+
+int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
+ void *data)
+{
+ int err;
+ unsigned long flags = 0;
+ struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
+
+ err = cmdq_pkt_finalize(pkt);
+ if (err < 0)
+ return err;
+
+ pkt->cb.cb = cb;
+ pkt->cb.data = data;
+ pkt->async_cb.cb = cmdq_pkt_flush_async_cb;
+ pkt->async_cb.data = pkt;
+
+ dma_sync_single_for_device(client->chan->mbox->dev, pkt->pa_base,
+ pkt->cmd_buf_size, DMA_TO_DEVICE);
+
+ if (client->timeout_ms != CMDQ_NO_TIMEOUT) {
+ spin_lock_irqsave(&client->lock, flags);
+ if (client->pkt_cnt++ == 0)
+ mod_timer(&client->timer, jiffies +
+ msecs_to_jiffies(client->timeout_ms));
+ spin_unlock_irqrestore(&client->lock, flags);
+ }
+
+ mbox_send_message(client->chan, pkt);
+ /* We can send next packet immediately, so just call txdone. */
+ mbox_client_txdone(client->chan, 0);
+
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush_async);
+
+struct cmdq_flush_completion {
+ struct completion cmplt;
+ bool err;
+};
+
+static void cmdq_pkt_flush_cb(struct cmdq_cb_data data)
+{
+ struct cmdq_flush_completion *cmplt;
+
+ cmplt = (struct cmdq_flush_completion *)data.data;
+ if (data.sta != CMDQ_CB_NORMAL)
+ cmplt->err = true;
+ else
+ cmplt->err = false;
+ complete(&cmplt->cmplt);
+}
+
+int cmdq_pkt_flush(struct cmdq_pkt *pkt)
+{
+ struct cmdq_flush_completion cmplt;
+ int err;
+
+ init_completion(&cmplt.cmplt);
+ err = cmdq_pkt_flush_async(pkt, cmdq_pkt_flush_cb, &cmplt);
+ if (err < 0)
+ return err;
+ wait_for_completion(&cmplt.cmplt);
+
+ return cmplt.err ? -EFAULT : 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_flush);
+
+MODULE_LICENSE("GPL v2");
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-infracfg.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-infracfg.c
new file mode 100644
index 0000000..dba3055
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-infracfg.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/infracfg.h>
+#include <asm/processor.h>
+
+#define INFRA_TOPAXI_PROTECTEN 0x0220
+#define INFRA_TOPAXI_PROTECTSTA1 0x0228
+
+/**
+ * mtk_infracfg_set_bus_protection - enable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be enabled.
+ *
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
+{
+ unsigned long expired;
+ u32 val;
+ int ret;
+
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
+
+ expired = jiffies + HZ;
+
+ while (1) {
+ ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+ if (ret)
+ return ret;
+
+ if ((val & mask) == mask)
+ break;
+
+ cpu_relax();
+ if (time_after(jiffies, expired))
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * mtk_infracfg_clear_bus_protection - disable bus protection
+ * @regmap: The infracfg regmap
+ * @mask: The mask containing the protection bits to be disabled.
+ *
+ * This function disables the bus protection bits previously enabled with
+ * mtk_infracfg_set_bus_protection.
+ */
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
+{
+ unsigned long expired;
+ int ret;
+
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+
+ expired = jiffies + HZ;
+
+ while (1) {
+ u32 val;
+
+ ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
+ if (ret)
+ return ret;
+
+ if (!(val & mask))
+ break;
+
+ cpu_relax();
+ if (time_after(jiffies, expired))
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap-legacy.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap-legacy.c
new file mode 100644
index 0000000..73d81da
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap-legacy.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/******************************************************************************
+ * pmic_wrapper.c - Linux pmic_wrapper Driver
+ *
+ *
+ * DESCRIPTION:
+ * This file provid the other drivers PMIC wrapper relative functions
+ *
+ ******************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+/*#include <mach/mt_typedefs.h>*/
+#include <linux/timer.h>
+//#include <mtk_pmic_wrap.h>
+#include <linux/syscore_ops.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/pmic_wrap.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+static struct regmap *pmic_regmap;
+static spinlock_t wrp_lock = __SPIN_LOCK_UNLOCKED(lock);
+
+s32 pwrap_read(u32 adr, u32 *rdata)
+{
+ int ret = 0;
+ unsigned long flags = 0;
+
+ if (pmic_regmap) {
+ spin_lock_irqsave(&wrp_lock, flags);
+ ret = regmap_read(pmic_regmap, adr, rdata);
+ spin_unlock_irqrestore(&wrp_lock, flags);
+ } else
+ pr_notice("%s %d rec.\n", __func__, __LINE__);
+ return ret;
+}
+EXPORT_SYMBOL(pwrap_read);
+
+s32 pwrap_write(u32 adr, u32 wdata)
+{
+ int ret = 0;
+ unsigned long flags = 0;
+
+ if (pmic_regmap) {
+ spin_lock_irqsave(&wrp_lock, flags);
+ ret = regmap_write(pmic_regmap, adr, wdata);
+ spin_unlock_irqrestore(&wrp_lock, flags);
+ } else
+ pr_notice("%s %d Error.\n", __func__, __LINE__);
+ return ret;
+}
+EXPORT_SYMBOL(pwrap_write);
+
+static int __init mt_pwrap_init(void)
+{
+ struct device_node *node, *pwrap_node;
+
+ pr_info("%s\n", __func__);
+ node = of_find_compatible_node(NULL, NULL, "mediatek,pwraph");
+ pwrap_node = of_parse_phandle(node, "mediatek,pwrap-regmap", 0);
+ if (pwrap_node) {
+ pmic_regmap = pwrap_node_to_regmap(pwrap_node);
+ if (IS_ERR(pmic_regmap)) {
+ pr_notice("%s %d Error.\n", __func__, __LINE__);
+ return PTR_ERR(pmic_regmap);
+ }
+ } else {
+ pr_notice("%s %d Error.\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ return 0;
+}
+subsys_initcall(mt_pwrap_init);
+
+MODULE_AUTHOR("mediatek");
+MODULE_DESCRIPTION("pmic_wrapper Driver Revision");
+MODULE_LICENSE("GPL");
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap.c
new file mode 100644
index 0000000..d14f13b
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -0,0 +1,2873 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu, MediaTek
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sched/clock.h>
+/* TBD #include <mt-plat/aee.h> */
+
+#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
+#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
+#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
+#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
+#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
+#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
+#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
+#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
+#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
+
+/* macro for wrapper status */
+#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
+#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
+#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
+#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
+/* MT3967 and later should be (1 << 22) */
+#define PWRAP_STATE_INIT_DONE0 (1 << 21)
+
+/* macro for WACS FSM */
+#define PWRAP_WACS_FSM_IDLE 0x00
+#define PWRAP_WACS_FSM_REQ 0x02
+#define PWRAP_WACS_FSM_WFDLE 0x04
+#define PWRAP_WACS_FSM_WFVLDCLR 0x06
+#define PWRAP_WACS_INIT_DONE 0x01
+#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
+#define PWRAP_WACS_SYNC_BUSY 0x00
+
+/* macro for device wrapper default value */
+#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
+#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
+
+/* macro for manual command */
+#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
+#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
+#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
+#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
+#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
+#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
+#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
+#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
+
+/* macro for Watch Dog Timer Source */
+#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
+#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
+#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
+#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
+#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
+ PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
+ PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
+
+/* Group of bits used for shown slave capability */
+#define PWRAP_SLV_CAP_SPI BIT(0)
+#define PWRAP_SLV_CAP_DUALIO BIT(1)
+#define PWRAP_SLV_CAP_SECURITY BIT(2)
+#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
+
+/* Group of bits used for shown pwrap capability */
+#define PWRAP_CAP_BRIDGE BIT(0)
+#define PWRAP_CAP_RESET BIT(1)
+#define PWRAP_CAP_DCM BIT(2)
+#define PWRAP_CAP_PRIORITY_SEL BIT(3)
+#define PWRAP_CAP_INT1_EN BIT(4)
+#define PWRAP_CAP_WDT_SRC1 BIT(5)
+#define PWRAP_CAP_MON_V1 BIT(6)
+#define PWRAP_CAP_MON_V2 BIT(7)
+
+static char pwrap_log_buf[1280];
+
+/* defines for slave device wrapper registers */
+enum dew_regs {
+ PWRAP_DEW_BASE,
+ PWRAP_DEW_DIO_EN,
+ PWRAP_DEW_READ_TEST,
+ PWRAP_DEW_WRITE_TEST,
+ PWRAP_DEW_CRC_EN,
+ PWRAP_DEW_CRC_VAL,
+ PWRAP_DEW_MON_GRP_SEL,
+ PWRAP_DEW_CIPHER_KEY_SEL,
+ PWRAP_DEW_CIPHER_IV_SEL,
+ PWRAP_DEW_CIPHER_RDY,
+ PWRAP_DEW_CIPHER_MODE,
+ PWRAP_DEW_CIPHER_SWRST,
+
+ /* MT6397 only regs */
+ PWRAP_DEW_EVENT_OUT_EN,
+ PWRAP_DEW_EVENT_SRC_EN,
+ PWRAP_DEW_EVENT_SRC,
+ PWRAP_DEW_EVENT_FLAG,
+ PWRAP_DEW_MON_FLAG_SEL,
+ PWRAP_DEW_EVENT_TEST,
+ PWRAP_DEW_CIPHER_LOAD,
+ PWRAP_DEW_CIPHER_START,
+
+ /* MT6323 only regs */
+ PWRAP_DEW_CIPHER_EN,
+ PWRAP_DEW_RDDMY_NO,
+
+ /* MT6358 only regs */
+ PWRAP_SMT_CON1,
+ PWRAP_DRV_CON1,
+ PWRAP_FILTER_CON0,
+ PWRAP_GPIO_PULLEN0_CLR,
+ PWRAP_RG_SPI_CON0,
+ PWRAP_RG_SPI_RECORD0,
+ PWRAP_RG_SPI_CON2,
+ PWRAP_RG_SPI_CON3,
+ PWRAP_RG_SPI_CON4,
+ PWRAP_RG_SPI_CON5,
+ PWRAP_RG_SPI_CON6,
+ PWRAP_RG_SPI_CON7,
+ PWRAP_RG_SPI_CON8,
+ PWRAP_RG_SPI_CON13,
+ PWRAP_SPISLV_KEY,
+
+ PWRAP_DEW_CRC_SWRST,
+ PWRAP_DEW_RG_EN_RECORD,
+ PWRAP_DEW_RECORD_CMD0,
+ PWRAP_DEW_RECORD_CMD1,
+ PWRAP_DEW_RECORD_CMD2,
+ PWRAP_DEW_RECORD_CMD3,
+ PWRAP_DEW_RECORD_CMD4,
+ PWRAP_DEW_RECORD_CMD5,
+ PWRAP_DEW_RECORD_WDATA0,
+ PWRAP_DEW_RECORD_WDATA1,
+ PWRAP_DEW_RECORD_WDATA2,
+ PWRAP_DEW_RECORD_WDATA3,
+ PWRAP_DEW_RECORD_WDATA4,
+ PWRAP_DEW_RECORD_WDATA5,
+ PWRAP_DEW_RG_ADDR_TARGET,
+ PWRAP_DEW_RG_ADDR_MASK,
+ PWRAP_DEW_RG_WDATA_TARGET,
+ PWRAP_DEW_RG_WDATA_MASK,
+ PWRAP_DEW_RG_SPI_RECORD_CLR,
+ PWRAP_DEW_RG_CMD_ALERT_CLR,
+ PWRAP_DEW_SPISLV_KEY,
+};
+
+static const u32 mt6323_regs[] = {
+ [PWRAP_DEW_BASE] = 0x0000,
+ [PWRAP_DEW_DIO_EN] = 0x018a,
+ [PWRAP_DEW_READ_TEST] = 0x018c,
+ [PWRAP_DEW_WRITE_TEST] = 0x018e,
+ [PWRAP_DEW_CRC_EN] = 0x0192,
+ [PWRAP_DEW_CRC_VAL] = 0x0194,
+ [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
+ [PWRAP_DEW_CIPHER_EN] = 0x019c,
+ [PWRAP_DEW_CIPHER_RDY] = 0x019e,
+ [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
+ [PWRAP_DEW_RDDMY_NO] = 0x01a4,
+};
+
+static const u32 mt6356_regs[] = {
+ [PWRAP_SMT_CON1] = 0x002e,
+ [PWRAP_DRV_CON1] = 0x0036,
+ [PWRAP_FILTER_CON0] = 0x003c,
+ [PWRAP_GPIO_PULLEN0_CLR] = 0x0056,
+ [PWRAP_DEW_RG_EN_RECORD] = 0x0246,
+ [PWRAP_DEW_DIO_EN] = 0x0248,
+ [PWRAP_DEW_READ_TEST] = 0x024a,
+ [PWRAP_DEW_WRITE_TEST] = 0x024c,
+ [PWRAP_DEW_CRC_EN] = 0x0250,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0256,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x0258,
+ [PWRAP_DEW_CIPHER_EN] = 0x025a,
+ [PWRAP_DEW_CIPHER_RDY] = 0x025c,
+ [PWRAP_DEW_CIPHER_MODE] = 0x025e,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x0260,
+ [PWRAP_RG_SPI_CON2] = 0x0292,
+ [PWRAP_DEW_RECORD_CMD0] = 0x0294,
+ [PWRAP_DEW_RECORD_CMD1] = 0x0296,
+ [PWRAP_DEW_RECORD_CMD2] = 0x0298,
+ [PWRAP_DEW_RECORD_WDATA0] = 0x029a,
+ [PWRAP_DEW_RECORD_WDATA1] = 0x029c,
+ [PWRAP_DEW_RECORD_WDATA2] = 0x029e,
+ [PWRAP_DEW_RG_ADDR_TARGET] = 0x02a0,
+ [PWRAP_DEW_RG_ADDR_MASK] = 0x02a2,
+ [PWRAP_DEW_RG_WDATA_TARGET] = 0x02a4,
+ [PWRAP_DEW_RG_WDATA_MASK] = 0x02a6,
+ [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x02a8,
+ [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x02a8,
+};
+
+static const u32 mt6358_regs[] = {
+ [PWRAP_SMT_CON1] = 0x0030,
+ [PWRAP_DRV_CON1] = 0x0038,
+ [PWRAP_FILTER_CON0] = 0x0040,
+ [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
+ [PWRAP_RG_SPI_CON0] = 0x0408,
+ [PWRAP_RG_SPI_RECORD0] = 0x040a,
+ [PWRAP_DEW_DIO_EN] = 0x040c,
+ [PWRAP_DEW_READ_TEST] = 0x040e,
+ [PWRAP_DEW_WRITE_TEST] = 0x0410,
+ [PWRAP_DEW_CRC_EN] = 0x0414,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
+ [PWRAP_DEW_CIPHER_EN] = 0x041e,
+ [PWRAP_DEW_CIPHER_RDY] = 0x0420,
+ [PWRAP_DEW_CIPHER_MODE] = 0x0422,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
+ [PWRAP_RG_SPI_CON2] = 0x0432,
+ [PWRAP_RG_SPI_CON3] = 0x0434,
+ [PWRAP_RG_SPI_CON4] = 0x0436,
+ [PWRAP_RG_SPI_CON5] = 0x0438,
+ [PWRAP_RG_SPI_CON6] = 0x043a,
+ [PWRAP_RG_SPI_CON7] = 0x043c,
+ [PWRAP_RG_SPI_CON8] = 0x043e,
+ [PWRAP_RG_SPI_CON13] = 0x0448,
+ [PWRAP_SPISLV_KEY] = 0x044a,
+};
+
+static const u32 mt6389_regs[] = {
+ [PWRAP_SMT_CON1] = 0x0032,
+ [PWRAP_DRV_CON1] = 0x003a,
+ [PWRAP_FILTER_CON0] = 0x0042,
+ [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
+ [PWRAP_DEW_RG_EN_RECORD] = 0x040a,
+ [PWRAP_DEW_DIO_EN] = 0x040c,
+ [PWRAP_DEW_READ_TEST] = 0x040e,
+ [PWRAP_DEW_WRITE_TEST] = 0x0410,
+ [PWRAP_DEW_CRC_EN] = 0x0414,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
+ [PWRAP_DEW_CIPHER_EN] = 0x041c,
+ [PWRAP_DEW_CIPHER_RDY] = 0x041e,
+ [PWRAP_DEW_CIPHER_MODE] = 0x0420,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
+ [PWRAP_RG_SPI_CON2] = 0x0426,
+ [PWRAP_DEW_RECORD_CMD0] = 0x0428,
+ [PWRAP_DEW_RECORD_CMD1] = 0x042a,
+ [PWRAP_DEW_RECORD_CMD2] = 0x042c,
+ [PWRAP_DEW_RECORD_WDATA0] = 0x0434,
+ [PWRAP_DEW_RECORD_WDATA1] = 0x0436,
+ [PWRAP_DEW_RECORD_WDATA2] = 0x0438,
+ [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
+ [PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
+ [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
+ [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
+ [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
+ [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
+};
+
+static const u32 mt6397_regs[] = {
+ [PWRAP_DEW_BASE] = 0xbc00,
+ [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
+ [PWRAP_DEW_DIO_EN] = 0xbc02,
+ [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
+ [PWRAP_DEW_EVENT_SRC] = 0xbc06,
+ [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
+ [PWRAP_DEW_READ_TEST] = 0xbc0a,
+ [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
+ [PWRAP_DEW_CRC_EN] = 0xbc0e,
+ [PWRAP_DEW_CRC_VAL] = 0xbc10,
+ [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
+ [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
+ [PWRAP_DEW_EVENT_TEST] = 0xbc16,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
+ [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
+ [PWRAP_DEW_CIPHER_START] = 0xbc1e,
+ [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
+ [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
+ [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
+};
+
+enum pwrap_regs {
+ PWRAP_MUX_SEL,
+ PWRAP_WRAP_EN,
+ PWRAP_DIO_EN,
+ PWRAP_SIDLY,
+ PWRAP_CSHEXT_WRITE,
+ PWRAP_CSHEXT_READ,
+ PWRAP_CSLEXT_START,
+ PWRAP_CSLEXT_END,
+ PWRAP_STAUPD_PRD,
+ PWRAP_STAUPD_GRPEN,
+ PWRAP_STAUPD_MAN_TRIG,
+ PWRAP_STAUPD_STA,
+ PWRAP_WRAP_STA,
+ PWRAP_HARB_INIT,
+ PWRAP_HARB_HPRIO,
+ PWRAP_HIPRIO_ARB_EN,
+ PWRAP_HARB_STA0,
+ PWRAP_HARB_STA1,
+ PWRAP_MAN_EN,
+ PWRAP_MAN_CMD,
+ PWRAP_MAN_RDATA,
+ PWRAP_MAN_VLDCLR,
+ PWRAP_WACS0_EN,
+ PWRAP_INIT_DONE0,
+ PWRAP_WACS0_CMD,
+ PWRAP_WACS0_RDATA,
+ PWRAP_WACS0_VLDCLR,
+ PWRAP_WACS1_EN,
+ PWRAP_INIT_DONE1,
+ PWRAP_WACS1_CMD,
+ PWRAP_WACS1_RDATA,
+ PWRAP_WACS1_VLDCLR,
+ PWRAP_WACS2_EN,
+ PWRAP_INIT_DONE2,
+ PWRAP_WACS2_CMD,
+ PWRAP_WACS2_RDATA,
+ PWRAP_WACS2_VLDCLR,
+ PWRAP_WACS3_EN,
+ PWRAP_INIT_DONE3,
+ PWRAP_WACS3_CMD,
+ PWRAP_WACS3_RDATA,
+ PWRAP_WACS3_VLDCLR,
+ PWRAP_INT_EN,
+ PWRAP_INT_FLG_RAW,
+ PWRAP_INT_FLG,
+ PWRAP_INT_CLR,
+ PWRAP_SIG_ADR,
+ PWRAP_SIG_MODE,
+ PWRAP_SIG_VALUE,
+ PWRAP_SIG_ERRVAL,
+ PWRAP_CRC_EN,
+ PWRAP_TIMER_EN,
+ PWRAP_TIMER_STA,
+ PWRAP_WDT_UNIT,
+ PWRAP_WDT_SRC_EN,
+ PWRAP_WDT_FLG,
+ PWRAP_DEBUG_INT_SEL,
+ PWRAP_CIPHER_KEY_SEL,
+ PWRAP_CIPHER_IV_SEL,
+ PWRAP_CIPHER_RDY,
+ PWRAP_CIPHER_MODE,
+ PWRAP_CIPHER_SWRST,
+ PWRAP_DCM_EN,
+ PWRAP_DCM_DBC_PRD,
+
+ /* MT2701 only regs */
+ PWRAP_ADC_CMD_ADDR,
+ PWRAP_PWRAP_ADC_CMD,
+ PWRAP_ADC_RDY_ADDR,
+ PWRAP_ADC_RDATA_ADDR1,
+ PWRAP_ADC_RDATA_ADDR2,
+
+ /* MT7622 only regs */
+ PWRAP_STA,
+ PWRAP_CLR,
+ PWRAP_DVFS_ADR8,
+ PWRAP_DVFS_WDATA8,
+ PWRAP_DVFS_ADR9,
+ PWRAP_DVFS_WDATA9,
+ PWRAP_DVFS_ADR10,
+ PWRAP_DVFS_WDATA10,
+ PWRAP_DVFS_ADR11,
+ PWRAP_DVFS_WDATA11,
+ PWRAP_DVFS_ADR12,
+ PWRAP_DVFS_WDATA12,
+ PWRAP_DVFS_ADR13,
+ PWRAP_DVFS_WDATA13,
+ PWRAP_DVFS_ADR14,
+ PWRAP_DVFS_WDATA14,
+ PWRAP_DVFS_ADR15,
+ PWRAP_DVFS_WDATA15,
+ PWRAP_EXT_CK,
+ PWRAP_ADC_RDATA_ADDR,
+ PWRAP_GPS_STA,
+ PWRAP_SW_RST,
+ PWRAP_DVFS_STEP_CTRL0,
+ PWRAP_DVFS_STEP_CTRL1,
+ PWRAP_DVFS_STEP_CTRL2,
+ PWRAP_SPI2_CTRL,
+
+ /* MT8135 only regs */
+ PWRAP_CSHEXT,
+ PWRAP_EVENT_IN_EN,
+ PWRAP_EVENT_DST_EN,
+ PWRAP_RRARB_INIT,
+ PWRAP_RRARB_EN,
+ PWRAP_RRARB_STA0,
+ PWRAP_RRARB_STA1,
+ PWRAP_EVENT_STA,
+ PWRAP_EVENT_STACLR,
+ PWRAP_CIPHER_LOAD,
+ PWRAP_CIPHER_START,
+
+ /* MT8173 only regs */
+ PWRAP_RDDMY,
+ PWRAP_SI_CK_CON,
+ PWRAP_DVFS_ADR0,
+ PWRAP_DVFS_WDATA0,
+ PWRAP_DVFS_ADR1,
+ PWRAP_DVFS_WDATA1,
+ PWRAP_DVFS_ADR2,
+ PWRAP_DVFS_WDATA2,
+ PWRAP_DVFS_ADR3,
+ PWRAP_DVFS_WDATA3,
+ PWRAP_DVFS_ADR4,
+ PWRAP_DVFS_WDATA4,
+ PWRAP_DVFS_ADR5,
+ PWRAP_DVFS_WDATA5,
+ PWRAP_DVFS_ADR6,
+ PWRAP_DVFS_WDATA6,
+ PWRAP_DVFS_ADR7,
+ PWRAP_DVFS_WDATA7,
+ PWRAP_SPMINF_STA,
+ PWRAP_CIPHER_EN,
+
+ /* MT8183 only regs */
+ PWRAP_SI_SAMPLE_CTRL,
+ PWRAP_CSLEXT_WRITE,
+ PWRAP_CSLEXT_READ,
+ PWRAP_EXT_CK_WRITE,
+ PWRAP_STAUPD_CTRL,
+ PWRAP_WACS_P2P_EN,
+ PWRAP_INIT_DONE_P2P,
+ PWRAP_WACS_MD32_EN,
+ PWRAP_INIT_DONE_MD32,
+ PWRAP_INT0_EN,
+ PWRAP_INT0_FLG_RAW,
+ PWRAP_INT0_FLG,
+ PWRAP_INT0_CLR,
+ PWRAP_INT1_EN,
+ PWRAP_INT1_FLG_RAW,
+ PWRAP_INT1_FLG,
+ PWRAP_INT1_CLR,
+ PWRAP_EINT_STA0_ADR,
+ PWRAP_EINT_STA1_ADR,
+
+ PWRAP_EINT_STA,
+ PWRAP_EINT_CLR,
+ PWRAP_HPRIO_ARB_EN,
+ PWRAP_WDT_SRC_EN_1,
+ PWRAP_WDT_FLG_1,
+ PWRAP_INT_GPS_AUXADC_CMD_ADDR,
+ PWRAP_INT_GPS_AUXADC_CMD,
+ PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
+ PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
+ PWRAP_DCXO_CONN_ADR0,
+ PWRAP_DCXO_CONN_WDATA0,
+ PWRAP_DCXO_CONN_ADR1,
+ PWRAP_DCXO_CONN_WDATA1,
+ PWRAP_DCXO_NFC_ADR0,
+ PWRAP_DCXO_NFC_WDATA0,
+ PWRAP_DCXO_NFC_ADR1,
+ PWRAP_DCXO_NFC_WDATA1,
+ PWRAP_SPMINF_STA_1,
+ PWRAP_SPMINF_BACKUP_STA,
+ PWRAP_SCPINF_STA,
+ PWRAP_SRCLKEN_RCINF_STA_0,
+ PWRAP_SRCLKEN_RCINF_STA_1,
+ PWRAP_CONNINF_STA_0,
+ PWRAP_CONNINF_STA_1,
+ PWRAP_MCU_PMINF_STA_0,
+ PWRAP_MCU_PMINF_STA_1,
+ PWRAP_GPSINF_0_STA,
+ PWRAP_GPSINF_1_STA,
+ PWRAP_MD_ADCINF_0_STA_0,
+ PWRAP_MD_ADCINF_0_STA_1,
+ PWRAP_MD_ADCINF_1_STA_0,
+ PWRAP_MD_ADCINF_1_STA_1,
+ PWRAP_BUSY_STA,
+ PWRAP_BUSY_STA_LATCHED_WDT,
+ PWRAP_PRIORITY_USER_SEL_0,
+ PWRAP_PRIORITY_USER_SEL_1,
+ PWRAP_ARBITER_OUT_SEL_0,
+ PWRAP_ARBITER_OUT_SEL_1,
+ PWRAP_MD_AUXADC_RDATA_LATEST_ADDR,
+ PWRAP_MD_AUXADC_RDATA_WP_ADDR,
+ PWRAP_MD_AUXADC_RDATA_0_ADDR,
+ PWRAP_MD_AUXADC_RDATA_1_ADDR,
+ PWRAP_MD_AUXADC_RDATA_2_ADDR,
+ PWRAP_MD_AUXADC_RDATA_3_ADDR,
+ PWRAP_MD_AUXADC_RDATA_4_ADDR,
+ PWRAP_MD_AUXADC_RDATA_5_ADDR,
+ PWRAP_MD_AUXADC_RDATA_6_ADDR,
+ PWRAP_MD_AUXADC_RDATA_7_ADDR,
+ PWRAP_MD_AUXADC_RDATA_8_ADDR,
+ PWRAP_MD_AUXADC_RDATA_9_ADDR,
+ PWRAP_MD_AUXADC_RDATA_10_ADDR,
+ PWRAP_MD_AUXADC_RDATA_11_ADDR,
+ PWRAP_MD_AUXADC_RDATA_12_ADDR,
+ PWRAP_MD_AUXADC_RDATA_13_ADDR,
+ PWRAP_MD_AUXADC_RDATA_14_ADDR,
+ PWRAP_MD_AUXADC_RDATA_15_ADDR,
+ PWRAP_MD_AUXADC_RDATA_16_ADDR,
+ PWRAP_MD_AUXADC_RDATA_17_ADDR,
+ PWRAP_MD_AUXADC_RDATA_18_ADDR,
+ PWRAP_MD_AUXADC_RDATA_19_ADDR,
+ PWRAP_MD_AUXADC_RDATA_20_ADDR,
+ PWRAP_MD_AUXADC_RDATA_21_ADDR,
+ PWRAP_MD_AUXADC_RDATA_22_ADDR,
+ PWRAP_MD_AUXADC_RDATA_23_ADDR,
+ PWRAP_MD_AUXADC_RDATA_24_ADDR,
+ PWRAP_MD_AUXADC_RDATA_25_ADDR,
+ PWRAP_MD_AUXADC_RDATA_26_ADDR,
+ PWRAP_MD_AUXADC_RDATA_27_ADDR,
+ PWRAP_MD_AUXADC_RDATA_28_ADDR,
+ PWRAP_MD_AUXADC_RDATA_29_ADDR,
+ PWRAP_MD_AUXADC_RDATA_30_ADDR,
+ PWRAP_MD_AUXADC_RDATA_31_ADDR,
+ PWRAP_PRIORITY_USER_SEL_2,
+ PWRAP_ARBITER_OUT_SEL_2,
+ PWRAP_STARV_COUNTER_0,
+ PWRAP_STARV_COUNTER_1,
+ PWRAP_STARV_COUNTER_2,
+ PWRAP_STARV_COUNTER_3,
+ PWRAP_STARV_COUNTER_4,
+ PWRAP_STARV_COUNTER_5,
+ PWRAP_STARV_COUNTER_6,
+ PWRAP_STARV_COUNTER_7,
+ PWRAP_STARV_COUNTER_8,
+ PWRAP_STARV_COUNTER_9,
+ PWRAP_STARV_COUNTER_10,
+ PWRAP_STARV_COUNTER_11,
+ PWRAP_STARV_COUNTER_12,
+ PWRAP_STARV_COUNTER_13,
+ PWRAP_STARV_COUNTER_14,
+ PWRAP_STARV_COUNTER_15,
+ PWRAP_STARV_COUNTER_16,
+ PWRAP_MONITOR_CTRL_0,
+ PWRAP_MONITOR_CTRL_1,
+ PWRAP_MONITOR_CTRL_2,
+ PWRAP_MONITOR_CTRL_3,
+ PWRAP_CHANNEL_SEQUENCE_0,
+ PWRAP_CHANNEL_SEQUENCE_1,
+ PWRAP_CHANNEL_SEQUENCE_2,
+ PWRAP_CHANNEL_SEQUENCE_3,
+ PWRAP_CHANNEL_SEQUENCE_4,
+ PWRAP_CHANNEL_SEQUENCE_5,
+ PWRAP_CHANNEL_SEQUENCE_6,
+ PWRAP_CHANNEL_SEQUENCE_7,
+ PWRAP_WRITE_SEQUENCE,
+ PWRAP_CMD_SEQUENCE_0,
+ PWRAP_CMD_SEQUENCE_1,
+ PWRAP_CMD_SEQUENCE_2,
+ PWRAP_CMD_SEQUENCE_3,
+ PWRAP_CMD_SEQUENCE_4,
+ PWRAP_CMD_SEQUENCE_5,
+ PWRAP_CMD_SEQUENCE_6,
+ PWRAP_CMD_SEQUENCE_7,
+ PWRAP_CMD_SEQUENCE_8,
+ PWRAP_CMD_SEQUENCE_9,
+ PWRAP_CMD_SEQUENCE_10,
+ PWRAP_CMD_SEQUENCE_11,
+ PWRAP_CMD_SEQUENCE_12,
+ PWRAP_CMD_SEQUENCE_13,
+ PWRAP_CMD_SEQUENCE_14,
+ PWRAP_CMD_SEQUENCE_15,
+ PWRAP_WDATA_SEQUENCE_0,
+ PWRAP_WDATA_SEQUENCE_1,
+ PWRAP_WDATA_SEQUENCE_2,
+ PWRAP_WDATA_SEQUENCE_3,
+ PWRAP_WDATA_SEQUENCE_4,
+ PWRAP_WDATA_SEQUENCE_5,
+ PWRAP_WDATA_SEQUENCE_6,
+ PWRAP_WDATA_SEQUENCE_7,
+ PWRAP_WDATA_SEQUENCE_8,
+ PWRAP_WDATA_SEQUENCE_9,
+ PWRAP_WDATA_SEQUENCE_10,
+ PWRAP_WDATA_SEQUENCE_11,
+ PWRAP_WDATA_SEQUENCE_12,
+ PWRAP_WDATA_SEQUENCE_13,
+ PWRAP_WDATA_SEQUENCE_14,
+ PWRAP_WDATA_SEQUENCE_15,
+
+ /* MPU regs */
+ PWRAP_MPU_PMIC_ACC_VIO_INFO_0,
+ PWRAP_MPU_PMIC_ACC_VIO_INFO_1,
+ PWRAP_MPU_PMIC_ACC_VIO_INFO_2,
+ PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0,
+ PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1,
+ PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2,
+ PWRAP_MPU_PWRAP_ACC_VIO_INFO_0,
+ PWRAP_MPU_PWRAP_ACC_VIO_INFO_1,
+
+};
+
+static int mt2701_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xc,
+ [PWRAP_RDDMY] = 0x18,
+ [PWRAP_SI_CK_CON] = 0x1c,
+ [PWRAP_CSHEXT_WRITE] = 0x20,
+ [PWRAP_CSHEXT_READ] = 0x24,
+ [PWRAP_CSLEXT_START] = 0x28,
+ [PWRAP_CSLEXT_END] = 0x2c,
+ [PWRAP_STAUPD_PRD] = 0x30,
+ [PWRAP_STAUPD_GRPEN] = 0x34,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x38,
+ [PWRAP_STAUPD_STA] = 0x3c,
+ [PWRAP_WRAP_STA] = 0x44,
+ [PWRAP_HARB_INIT] = 0x48,
+ [PWRAP_HARB_HPRIO] = 0x4c,
+ [PWRAP_HIPRIO_ARB_EN] = 0x50,
+ [PWRAP_HARB_STA0] = 0x54,
+ [PWRAP_HARB_STA1] = 0x58,
+ [PWRAP_MAN_EN] = 0x5c,
+ [PWRAP_MAN_CMD] = 0x60,
+ [PWRAP_MAN_RDATA] = 0x64,
+ [PWRAP_MAN_VLDCLR] = 0x68,
+ [PWRAP_WACS0_EN] = 0x6c,
+ [PWRAP_INIT_DONE0] = 0x70,
+ [PWRAP_WACS0_CMD] = 0x74,
+ [PWRAP_WACS0_RDATA] = 0x78,
+ [PWRAP_WACS0_VLDCLR] = 0x7c,
+ [PWRAP_WACS1_EN] = 0x80,
+ [PWRAP_INIT_DONE1] = 0x84,
+ [PWRAP_WACS1_CMD] = 0x88,
+ [PWRAP_WACS1_RDATA] = 0x8c,
+ [PWRAP_WACS1_VLDCLR] = 0x90,
+ [PWRAP_WACS2_EN] = 0x94,
+ [PWRAP_INIT_DONE2] = 0x98,
+ [PWRAP_WACS2_CMD] = 0x9c,
+ [PWRAP_WACS2_RDATA] = 0xa0,
+ [PWRAP_WACS2_VLDCLR] = 0xa4,
+ [PWRAP_INT_EN] = 0xa8,
+ [PWRAP_INT_FLG_RAW] = 0xac,
+ [PWRAP_INT_FLG] = 0xb0,
+ [PWRAP_INT_CLR] = 0xb4,
+ [PWRAP_SIG_ADR] = 0xb8,
+ [PWRAP_SIG_MODE] = 0xbc,
+ [PWRAP_SIG_VALUE] = 0xc0,
+ [PWRAP_SIG_ERRVAL] = 0xc4,
+ [PWRAP_CRC_EN] = 0xc8,
+ [PWRAP_TIMER_EN] = 0xcc,
+ [PWRAP_TIMER_STA] = 0xd0,
+ [PWRAP_WDT_UNIT] = 0xd4,
+ [PWRAP_WDT_SRC_EN] = 0xd8,
+ [PWRAP_WDT_FLG] = 0xdc,
+ [PWRAP_DEBUG_INT_SEL] = 0xe0,
+ [PWRAP_DVFS_ADR0] = 0xe4,
+ [PWRAP_DVFS_WDATA0] = 0xe8,
+ [PWRAP_DVFS_ADR1] = 0xec,
+ [PWRAP_DVFS_WDATA1] = 0xf0,
+ [PWRAP_DVFS_ADR2] = 0xf4,
+ [PWRAP_DVFS_WDATA2] = 0xf8,
+ [PWRAP_DVFS_ADR3] = 0xfc,
+ [PWRAP_DVFS_WDATA3] = 0x100,
+ [PWRAP_DVFS_ADR4] = 0x104,
+ [PWRAP_DVFS_WDATA4] = 0x108,
+ [PWRAP_DVFS_ADR5] = 0x10c,
+ [PWRAP_DVFS_WDATA5] = 0x110,
+ [PWRAP_DVFS_ADR6] = 0x114,
+ [PWRAP_DVFS_WDATA6] = 0x118,
+ [PWRAP_DVFS_ADR7] = 0x11c,
+ [PWRAP_DVFS_WDATA7] = 0x120,
+ [PWRAP_CIPHER_KEY_SEL] = 0x124,
+ [PWRAP_CIPHER_IV_SEL] = 0x128,
+ [PWRAP_CIPHER_EN] = 0x12c,
+ [PWRAP_CIPHER_RDY] = 0x130,
+ [PWRAP_CIPHER_MODE] = 0x134,
+ [PWRAP_CIPHER_SWRST] = 0x138,
+ [PWRAP_DCM_EN] = 0x13c,
+ [PWRAP_DCM_DBC_PRD] = 0x140,
+ [PWRAP_ADC_CMD_ADDR] = 0x144,
+ [PWRAP_PWRAP_ADC_CMD] = 0x148,
+ [PWRAP_ADC_RDY_ADDR] = 0x14c,
+ [PWRAP_ADC_RDATA_ADDR1] = 0x150,
+ [PWRAP_ADC_RDATA_ADDR2] = 0x154,
+};
+
+static int mt2731_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SI_SAMPLE_CTRL] = 0xC,
+ [PWRAP_RDDMY] = 0x20,
+ [PWRAP_CSHEXT_WRITE] = 0x24,
+ [PWRAP_CSHEXT_READ] = 0x28,
+ [PWRAP_CSLEXT_WRITE] = 0x2C,
+ [PWRAP_CSLEXT_READ] = 0x30,
+ [PWRAP_EXT_CK_WRITE] = 0x34,
+ [PWRAP_STAUPD_CTRL] = 0x3C,
+ [PWRAP_STAUPD_GRPEN] = 0x40,
+ [PWRAP_EINT_STA0_ADR] = 0x44,
+ [PWRAP_HARB_HPRIO] = 0x68,
+ [PWRAP_HIPRIO_ARB_EN] = 0x6C,
+ [PWRAP_MAN_EN] = 0x7C,
+ [PWRAP_MAN_CMD] = 0x80,
+ [PWRAP_WACS0_EN] = 0x8C,
+ [PWRAP_INIT_DONE0] = 0x90,
+ [PWRAP_WACS1_EN] = 0x94,
+ [PWRAP_INIT_DONE1] = 0x98,
+ [PWRAP_WACS2_EN] = 0x9C,
+ [PWRAP_INIT_DONE2] = 0xA0,
+ [PWRAP_WACS_P2P_EN] = 0xA4,
+ [PWRAP_INIT_DONE_P2P] = 0xA8,
+ [PWRAP_WACS_MD32_EN] = 0xAC,
+ [PWRAP_INIT_DONE_MD32] = 0xB0,
+ [PWRAP_INT_EN] = 0xB4,
+ [PWRAP_INT_FLG] = 0xBC,
+ [PWRAP_INT_CLR] = 0xC0,
+ [PWRAP_INT0_EN] = 0xB4,
+ [PWRAP_INT0_FLG] = 0xBC,
+ [PWRAP_INT0_CLR] = 0xC0,
+ [PWRAP_INT1_EN] = 0xC4,
+ [PWRAP_INT1_FLG] = 0xCC,
+ [PWRAP_INT1_CLR] = 0xD0,
+ [PWRAP_SIG_ADR] = 0xD4,
+ [PWRAP_CRC_EN] = 0xE4,
+ [PWRAP_TIMER_EN] = 0xE8,
+ [PWRAP_WDT_UNIT] = 0xF0,
+ [PWRAP_WDT_SRC_EN] = 0xF4,
+ [PWRAP_WDT_SRC_EN_1] = 0xF8,
+ [PWRAP_DCXO_CONN_ADR0] = 0x18C,
+ [PWRAP_DCXO_CONN_WDATA0] = 0x190,
+ [PWRAP_DCXO_CONN_ADR1] = 0x194,
+ [PWRAP_DCXO_CONN_WDATA1] = 0x198,
+ [PWRAP_DCXO_NFC_ADR0] = 0x19C,
+ [PWRAP_DCXO_NFC_WDATA0] = 0x1A0,
+ [PWRAP_DCXO_NFC_ADR1] = 0x1A4,
+ [PWRAP_DCXO_NFC_WDATA1] = 0x1A8,
+ [PWRAP_SPMINF_STA] = 0x1AC,
+ [PWRAP_SPMINF_STA_1] = 0x1B0,
+ [PWRAP_SPMINF_BACKUP_STA] = 0x1B4,
+ [PWRAP_MCU_PMINF_STA_0] = 0x1B8,
+ [PWRAP_MCU_PMINF_STA_1] = 0x1BC,
+ [PWRAP_SCPINF_STA] = 0x1C0,
+ [PWRAP_DCM_EN] = 0x1DC,
+ [PWRAP_DCM_DBC_PRD] = 0x1E0,
+ [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1E4,
+ [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E8,
+ [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1EC,
+ [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1F0,
+ [PWRAP_GPSINF_0_STA] = 0x1F4,
+ [PWRAP_GPSINF_1_STA] = 0x1F8,
+ [PWRAP_MD_AUXADC_RDATA_LATEST_ADDR] = 0x200,
+ [PWRAP_MD_AUXADC_RDATA_WP_ADDR] = 0x204,
+ [PWRAP_MD_AUXADC_RDATA_0_ADDR] = 0x208,
+ [PWRAP_MD_AUXADC_RDATA_1_ADDR] = 0x20C,
+ [PWRAP_MD_AUXADC_RDATA_2_ADDR] = 0x210,
+ [PWRAP_MD_AUXADC_RDATA_3_ADDR] = 0x214,
+ [PWRAP_MD_AUXADC_RDATA_4_ADDR] = 0x218,
+ [PWRAP_MD_AUXADC_RDATA_5_ADDR] = 0x21C,
+ [PWRAP_MD_AUXADC_RDATA_6_ADDR] = 0x220,
+ [PWRAP_MD_AUXADC_RDATA_7_ADDR] = 0x224,
+ [PWRAP_MD_AUXADC_RDATA_8_ADDR] = 0x228,
+ [PWRAP_MD_AUXADC_RDATA_9_ADDR] = 0x22C,
+ [PWRAP_MD_AUXADC_RDATA_10_ADDR] = 0x230,
+ [PWRAP_MD_AUXADC_RDATA_11_ADDR] = 0x234,
+ [PWRAP_MD_AUXADC_RDATA_12_ADDR] = 0x238,
+ [PWRAP_MD_AUXADC_RDATA_13_ADDR] = 0x23C,
+ [PWRAP_MD_AUXADC_RDATA_14_ADDR] = 0x240,
+ [PWRAP_MD_AUXADC_RDATA_15_ADDR] = 0x244,
+ [PWRAP_MD_AUXADC_RDATA_16_ADDR] = 0x248,
+ [PWRAP_MD_AUXADC_RDATA_17_ADDR] = 0x24C,
+ [PWRAP_MD_AUXADC_RDATA_18_ADDR] = 0x250,
+ [PWRAP_MD_AUXADC_RDATA_19_ADDR] = 0x254,
+ [PWRAP_MD_AUXADC_RDATA_20_ADDR] = 0x258,
+ [PWRAP_MD_AUXADC_RDATA_21_ADDR] = 0x25C,
+ [PWRAP_MD_AUXADC_RDATA_22_ADDR] = 0x260,
+ [PWRAP_MD_AUXADC_RDATA_23_ADDR] = 0x264,
+ [PWRAP_MD_AUXADC_RDATA_24_ADDR] = 0x268,
+ [PWRAP_MD_AUXADC_RDATA_25_ADDR] = 0x26C,
+ [PWRAP_MD_AUXADC_RDATA_26_ADDR] = 0x270,
+ [PWRAP_MD_AUXADC_RDATA_27_ADDR] = 0x274,
+ [PWRAP_MD_AUXADC_RDATA_28_ADDR] = 0x278,
+ [PWRAP_MD_AUXADC_RDATA_29_ADDR] = 0x27C,
+ [PWRAP_MD_AUXADC_RDATA_30_ADDR] = 0x280,
+ [PWRAP_MD_AUXADC_RDATA_31_ADDR] = 0x284,
+ [PWRAP_MD_ADCINF_0_STA_0] = 0x288,
+ [PWRAP_MD_ADCINF_0_STA_1] = 0x28C,
+ [PWRAP_MD_ADCINF_1_STA_0] = 0x290,
+ [PWRAP_MD_ADCINF_1_STA_1] = 0x294,
+ [PWRAP_PRIORITY_USER_SEL_2] = 0x2B0,
+ [PWRAP_ARBITER_OUT_SEL_2] = 0x2C4,
+ [PWRAP_STARV_COUNTER_0] = 0x2D0,
+ [PWRAP_STARV_COUNTER_1] = 0x2D4,
+ [PWRAP_STARV_COUNTER_2] = 0x2D8,
+ [PWRAP_STARV_COUNTER_3] = 0x2DC,
+ [PWRAP_STARV_COUNTER_4] = 0x2E0,
+ [PWRAP_STARV_COUNTER_5] = 0x2E4,
+ [PWRAP_STARV_COUNTER_6] = 0x2E8,
+ [PWRAP_STARV_COUNTER_7] = 0x2EC,
+ [PWRAP_STARV_COUNTER_8] = 0x2F0,
+ [PWRAP_STARV_COUNTER_9] = 0x2F4,
+ [PWRAP_STARV_COUNTER_10] = 0x2F8,
+ [PWRAP_STARV_COUNTER_11] = 0x2FC,
+ [PWRAP_STARV_COUNTER_12] = 0x300,
+ [PWRAP_STARV_COUNTER_13] = 0x304,
+ [PWRAP_STARV_COUNTER_14] = 0x308,
+ [PWRAP_STARV_COUNTER_15] = 0x30C,
+ [PWRAP_STARV_COUNTER_16] = 0x310,
+ [PWRAP_MONITOR_CTRL_0] = 0x364,
+ [PWRAP_MONITOR_CTRL_1] = 0x368,
+ [PWRAP_MONITOR_CTRL_2] = 0x36C,
+ [PWRAP_MONITOR_CTRL_3] = 0x370,
+ [PWRAP_CHANNEL_SEQUENCE_0] = 0x374,
+ [PWRAP_CHANNEL_SEQUENCE_1] = 0x378,
+ [PWRAP_CHANNEL_SEQUENCE_2] = 0x37C,
+ [PWRAP_CHANNEL_SEQUENCE_3] = 0x380,
+ [PWRAP_CMD_SEQUENCE_0] = 0x384,
+ [PWRAP_CMD_SEQUENCE_1] = 0x388,
+ [PWRAP_CMD_SEQUENCE_2] = 0x38C,
+ [PWRAP_CMD_SEQUENCE_3] = 0x390,
+ [PWRAP_CMD_SEQUENCE_4] = 0x394,
+ [PWRAP_CMD_SEQUENCE_5] = 0x398,
+ [PWRAP_CMD_SEQUENCE_6] = 0x39C,
+ [PWRAP_CMD_SEQUENCE_7] = 0x3A0,
+ [PWRAP_WDATA_SEQUENCE_0] = 0x3A4,
+ [PWRAP_WDATA_SEQUENCE_1] = 0x3A8,
+ [PWRAP_WDATA_SEQUENCE_2] = 0x3AC,
+ [PWRAP_WDATA_SEQUENCE_3] = 0x3B0,
+ [PWRAP_WDATA_SEQUENCE_4] = 0x3B4,
+ [PWRAP_WDATA_SEQUENCE_5] = 0x3B8,
+ [PWRAP_WDATA_SEQUENCE_6] = 0x3BC,
+ [PWRAP_WDATA_SEQUENCE_7] = 0x3C0,
+ [PWRAP_WACS2_CMD] = 0xC20,
+ [PWRAP_WACS2_RDATA] = 0xC24,
+ [PWRAP_WACS2_VLDCLR] = 0xC28,
+ [PWRAP_MPU_PMIC_ACC_VIO_INFO_0] = 0xF44,
+ [PWRAP_MPU_PMIC_ACC_VIO_INFO_1] = 0xF48,
+ [PWRAP_MPU_PMIC_ACC_VIO_INFO_2] = 0xF4C,
+ [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0] = 0xF50,
+ [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1] = 0xF54,
+ [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2] = 0xF58,
+ [PWRAP_MPU_PWRAP_ACC_VIO_INFO_0] = 0xF5C,
+ [PWRAP_MPU_PWRAP_ACC_VIO_INFO_1] = 0xF60,
+};
+
+static int mt7622_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xC,
+ [PWRAP_RDDMY] = 0x10,
+ [PWRAP_SI_CK_CON] = 0x14,
+ [PWRAP_CSHEXT_WRITE] = 0x18,
+ [PWRAP_CSHEXT_READ] = 0x1C,
+ [PWRAP_CSLEXT_START] = 0x20,
+ [PWRAP_CSLEXT_END] = 0x24,
+ [PWRAP_STAUPD_PRD] = 0x28,
+ [PWRAP_STAUPD_GRPEN] = 0x2C,
+ [PWRAP_EINT_STA0_ADR] = 0x30,
+ [PWRAP_EINT_STA1_ADR] = 0x34,
+ [PWRAP_STA] = 0x38,
+ [PWRAP_CLR] = 0x3C,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
+ [PWRAP_STAUPD_STA] = 0x44,
+ [PWRAP_WRAP_STA] = 0x48,
+ [PWRAP_HARB_INIT] = 0x4C,
+ [PWRAP_HARB_HPRIO] = 0x50,
+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
+ [PWRAP_HARB_STA0] = 0x58,
+ [PWRAP_HARB_STA1] = 0x5C,
+ [PWRAP_MAN_EN] = 0x60,
+ [PWRAP_MAN_CMD] = 0x64,
+ [PWRAP_MAN_RDATA] = 0x68,
+ [PWRAP_MAN_VLDCLR] = 0x6C,
+ [PWRAP_WACS0_EN] = 0x70,
+ [PWRAP_INIT_DONE0] = 0x74,
+ [PWRAP_WACS0_CMD] = 0x78,
+ [PWRAP_WACS0_RDATA] = 0x7C,
+ [PWRAP_WACS0_VLDCLR] = 0x80,
+ [PWRAP_WACS1_EN] = 0x84,
+ [PWRAP_INIT_DONE1] = 0x88,
+ [PWRAP_WACS1_CMD] = 0x8C,
+ [PWRAP_WACS1_RDATA] = 0x90,
+ [PWRAP_WACS1_VLDCLR] = 0x94,
+ [PWRAP_WACS2_EN] = 0x98,
+ [PWRAP_INIT_DONE2] = 0x9C,
+ [PWRAP_WACS2_CMD] = 0xA0,
+ [PWRAP_WACS2_RDATA] = 0xA4,
+ [PWRAP_WACS2_VLDCLR] = 0xA8,
+ [PWRAP_INT_EN] = 0xAC,
+ [PWRAP_INT_FLG_RAW] = 0xB0,
+ [PWRAP_INT_FLG] = 0xB4,
+ [PWRAP_INT_CLR] = 0xB8,
+ [PWRAP_SIG_ADR] = 0xBC,
+ [PWRAP_SIG_MODE] = 0xC0,
+ [PWRAP_SIG_VALUE] = 0xC4,
+ [PWRAP_SIG_ERRVAL] = 0xC8,
+ [PWRAP_CRC_EN] = 0xCC,
+ [PWRAP_TIMER_EN] = 0xD0,
+ [PWRAP_TIMER_STA] = 0xD4,
+ [PWRAP_WDT_UNIT] = 0xD8,
+ [PWRAP_WDT_SRC_EN] = 0xDC,
+ [PWRAP_WDT_FLG] = 0xE0,
+ [PWRAP_DEBUG_INT_SEL] = 0xE4,
+ [PWRAP_DVFS_ADR0] = 0xE8,
+ [PWRAP_DVFS_WDATA0] = 0xEC,
+ [PWRAP_DVFS_ADR1] = 0xF0,
+ [PWRAP_DVFS_WDATA1] = 0xF4,
+ [PWRAP_DVFS_ADR2] = 0xF8,
+ [PWRAP_DVFS_WDATA2] = 0xFC,
+ [PWRAP_DVFS_ADR3] = 0x100,
+ [PWRAP_DVFS_WDATA3] = 0x104,
+ [PWRAP_DVFS_ADR4] = 0x108,
+ [PWRAP_DVFS_WDATA4] = 0x10C,
+ [PWRAP_DVFS_ADR5] = 0x110,
+ [PWRAP_DVFS_WDATA5] = 0x114,
+ [PWRAP_DVFS_ADR6] = 0x118,
+ [PWRAP_DVFS_WDATA6] = 0x11C,
+ [PWRAP_DVFS_ADR7] = 0x120,
+ [PWRAP_DVFS_WDATA7] = 0x124,
+ [PWRAP_DVFS_ADR8] = 0x128,
+ [PWRAP_DVFS_WDATA8] = 0x12C,
+ [PWRAP_DVFS_ADR9] = 0x130,
+ [PWRAP_DVFS_WDATA9] = 0x134,
+ [PWRAP_DVFS_ADR10] = 0x138,
+ [PWRAP_DVFS_WDATA10] = 0x13C,
+ [PWRAP_DVFS_ADR11] = 0x140,
+ [PWRAP_DVFS_WDATA11] = 0x144,
+ [PWRAP_DVFS_ADR12] = 0x148,
+ [PWRAP_DVFS_WDATA12] = 0x14C,
+ [PWRAP_DVFS_ADR13] = 0x150,
+ [PWRAP_DVFS_WDATA13] = 0x154,
+ [PWRAP_DVFS_ADR14] = 0x158,
+ [PWRAP_DVFS_WDATA14] = 0x15C,
+ [PWRAP_DVFS_ADR15] = 0x160,
+ [PWRAP_DVFS_WDATA15] = 0x164,
+ [PWRAP_SPMINF_STA] = 0x168,
+ [PWRAP_CIPHER_KEY_SEL] = 0x16C,
+ [PWRAP_CIPHER_IV_SEL] = 0x170,
+ [PWRAP_CIPHER_EN] = 0x174,
+ [PWRAP_CIPHER_RDY] = 0x178,
+ [PWRAP_CIPHER_MODE] = 0x17C,
+ [PWRAP_CIPHER_SWRST] = 0x180,
+ [PWRAP_DCM_EN] = 0x184,
+ [PWRAP_DCM_DBC_PRD] = 0x188,
+ [PWRAP_EXT_CK] = 0x18C,
+ [PWRAP_ADC_CMD_ADDR] = 0x190,
+ [PWRAP_PWRAP_ADC_CMD] = 0x194,
+ [PWRAP_ADC_RDATA_ADDR] = 0x198,
+ [PWRAP_GPS_STA] = 0x19C,
+ [PWRAP_SW_RST] = 0x1A0,
+ [PWRAP_DVFS_STEP_CTRL0] = 0x238,
+ [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
+ [PWRAP_DVFS_STEP_CTRL2] = 0x240,
+ [PWRAP_SPI2_CTRL] = 0x244,
+};
+
+static int mt8183_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SI_SAMPLE_CTRL] = 0xC,
+ [PWRAP_RDDMY] = 0x14,
+ [PWRAP_CSHEXT_WRITE] = 0x18,
+ [PWRAP_CSHEXT_READ] = 0x1C,
+ [PWRAP_CSLEXT_WRITE] = 0x20,
+ [PWRAP_CSLEXT_READ] = 0x24,
+ [PWRAP_EXT_CK_WRITE] = 0x28,
+ [PWRAP_STAUPD_CTRL] = 0x30,
+ [PWRAP_STAUPD_GRPEN] = 0x34,
+ [PWRAP_EINT_STA0_ADR] = 0x38,
+ [PWRAP_HARB_HPRIO] = 0x5C,
+ [PWRAP_HIPRIO_ARB_EN] = 0x60,
+ [PWRAP_MAN_EN] = 0x70,
+ [PWRAP_MAN_CMD] = 0x74,
+ [PWRAP_WACS0_EN] = 0x80,
+ [PWRAP_INIT_DONE0] = 0x84,
+ [PWRAP_WACS1_EN] = 0x88,
+ [PWRAP_INIT_DONE1] = 0x8C,
+ [PWRAP_WACS2_EN] = 0x90,
+ [PWRAP_INIT_DONE2] = 0x94,
+ [PWRAP_WACS_P2P_EN] = 0xA0,
+ [PWRAP_INIT_DONE_P2P] = 0xA4,
+ [PWRAP_WACS_MD32_EN] = 0xA8,
+ [PWRAP_INIT_DONE_MD32] = 0xAC,
+ [PWRAP_INT_EN] = 0xB0,
+ [PWRAP_INT_FLG] = 0xB8,
+ [PWRAP_INT_CLR] = 0xBC,
+ [PWRAP_INT1_EN] = 0xC0,
+ [PWRAP_INT1_FLG] = 0xC8,
+ [PWRAP_INT1_CLR] = 0xCC,
+ [PWRAP_SIG_ADR] = 0xD0,
+ [PWRAP_CRC_EN] = 0xE0,
+ [PWRAP_TIMER_EN] = 0xE4,
+ [PWRAP_WDT_UNIT] = 0xEC,
+ [PWRAP_WDT_SRC_EN] = 0xF0,
+ [PWRAP_WDT_SRC_EN_1] = 0xF4,
+ [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
+ [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
+ [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
+ [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
+ [PWRAP_GPSINF_0_STA] = 0x1EC,
+ [PWRAP_GPSINF_1_STA] = 0x1F0,
+ [PWRAP_MD_AUXADC_RDATA_LATEST_ADDR] = 0x1F8,
+ [PWRAP_MD_AUXADC_RDATA_WP_ADDR] = 0x1FC,
+ [PWRAP_MD_AUXADC_RDATA_0_ADDR] = 0x200,
+ [PWRAP_MD_AUXADC_RDATA_1_ADDR] = 0x204,
+ [PWRAP_MD_AUXADC_RDATA_2_ADDR] = 0x208,
+ [PWRAP_MD_AUXADC_RDATA_3_ADDR] = 0x20C,
+ [PWRAP_MD_AUXADC_RDATA_4_ADDR] = 0x210,
+ [PWRAP_MD_AUXADC_RDATA_5_ADDR] = 0x214,
+ [PWRAP_MD_AUXADC_RDATA_6_ADDR] = 0x218,
+ [PWRAP_MD_AUXADC_RDATA_7_ADDR] = 0x21C,
+ [PWRAP_MD_AUXADC_RDATA_8_ADDR] = 0x220,
+ [PWRAP_MD_AUXADC_RDATA_9_ADDR] = 0x224,
+ [PWRAP_MD_AUXADC_RDATA_10_ADDR] = 0x228,
+ [PWRAP_MD_AUXADC_RDATA_11_ADDR] = 0x22C,
+ [PWRAP_MD_AUXADC_RDATA_12_ADDR] = 0x230,
+ [PWRAP_MD_AUXADC_RDATA_13_ADDR] = 0x234,
+ [PWRAP_MD_AUXADC_RDATA_14_ADDR] = 0x238,
+ [PWRAP_MD_AUXADC_RDATA_15_ADDR] = 0x23C,
+ [PWRAP_MD_AUXADC_RDATA_16_ADDR] = 0x240,
+ [PWRAP_MD_AUXADC_RDATA_17_ADDR] = 0x244,
+ [PWRAP_MD_AUXADC_RDATA_18_ADDR] = 0x248,
+ [PWRAP_MD_AUXADC_RDATA_19_ADDR] = 0x24C,
+ [PWRAP_MD_AUXADC_RDATA_20_ADDR] = 0x250,
+ [PWRAP_MD_AUXADC_RDATA_21_ADDR] = 0x254,
+ [PWRAP_MD_AUXADC_RDATA_22_ADDR] = 0x258,
+ [PWRAP_MD_AUXADC_RDATA_23_ADDR] = 0x25C,
+ [PWRAP_MD_AUXADC_RDATA_24_ADDR] = 0x260,
+ [PWRAP_MD_AUXADC_RDATA_25_ADDR] = 0x264,
+ [PWRAP_MD_AUXADC_RDATA_26_ADDR] = 0x268,
+ [PWRAP_MD_AUXADC_RDATA_27_ADDR] = 0x26C,
+ [PWRAP_MD_AUXADC_RDATA_28_ADDR] = 0x270,
+ [PWRAP_MD_AUXADC_RDATA_29_ADDR] = 0x274,
+ [PWRAP_MD_AUXADC_RDATA_30_ADDR] = 0x278,
+ [PWRAP_MD_AUXADC_RDATA_31_ADDR] = 0x27C,
+ [PWRAP_PRIORITY_USER_SEL_2] = 0x2A4,
+ [PWRAP_ARBITER_OUT_SEL_2] = 0x2B8,
+ [PWRAP_STARV_COUNTER_0] = 0x2C4,
+ [PWRAP_STARV_COUNTER_1] = 0x2C8,
+ [PWRAP_STARV_COUNTER_2] = 0x2CC,
+ [PWRAP_STARV_COUNTER_3] = 0x2D0,
+ [PWRAP_STARV_COUNTER_4] = 0x2D4,
+ [PWRAP_STARV_COUNTER_5] = 0x2D8,
+ [PWRAP_STARV_COUNTER_6] = 0x2DC,
+ [PWRAP_STARV_COUNTER_7] = 0x2E0,
+ [PWRAP_STARV_COUNTER_8] = 0x2E4,
+ [PWRAP_STARV_COUNTER_9] = 0x2E8,
+ [PWRAP_STARV_COUNTER_10] = 0x2EC,
+ [PWRAP_STARV_COUNTER_11] = 0x2F0,
+ [PWRAP_STARV_COUNTER_12] = 0x2F4,
+ [PWRAP_STARV_COUNTER_13] = 0x2F8,
+ [PWRAP_STARV_COUNTER_16] = 0x304,
+ [PWRAP_WACS2_CMD] = 0xC20,
+ [PWRAP_WACS2_RDATA] = 0xC24,
+ [PWRAP_WACS2_VLDCLR] = 0xC28,
+};
+
+static int mt8173_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xc,
+ [PWRAP_RDDMY] = 0x10,
+ [PWRAP_SI_CK_CON] = 0x14,
+ [PWRAP_CSHEXT_WRITE] = 0x18,
+ [PWRAP_CSHEXT_READ] = 0x1c,
+ [PWRAP_CSLEXT_START] = 0x20,
+ [PWRAP_CSLEXT_END] = 0x24,
+ [PWRAP_STAUPD_PRD] = 0x28,
+ [PWRAP_STAUPD_GRPEN] = 0x2c,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
+ [PWRAP_STAUPD_STA] = 0x44,
+ [PWRAP_WRAP_STA] = 0x48,
+ [PWRAP_HARB_INIT] = 0x4c,
+ [PWRAP_HARB_HPRIO] = 0x50,
+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
+ [PWRAP_HARB_STA0] = 0x58,
+ [PWRAP_HARB_STA1] = 0x5c,
+ [PWRAP_MAN_EN] = 0x60,
+ [PWRAP_MAN_CMD] = 0x64,
+ [PWRAP_MAN_RDATA] = 0x68,
+ [PWRAP_MAN_VLDCLR] = 0x6c,
+ [PWRAP_WACS0_EN] = 0x70,
+ [PWRAP_INIT_DONE0] = 0x74,
+ [PWRAP_WACS0_CMD] = 0x78,
+ [PWRAP_WACS0_RDATA] = 0x7c,
+ [PWRAP_WACS0_VLDCLR] = 0x80,
+ [PWRAP_WACS1_EN] = 0x84,
+ [PWRAP_INIT_DONE1] = 0x88,
+ [PWRAP_WACS1_CMD] = 0x8c,
+ [PWRAP_WACS1_RDATA] = 0x90,
+ [PWRAP_WACS1_VLDCLR] = 0x94,
+ [PWRAP_WACS2_EN] = 0x98,
+ [PWRAP_INIT_DONE2] = 0x9c,
+ [PWRAP_WACS2_CMD] = 0xa0,
+ [PWRAP_WACS2_RDATA] = 0xa4,
+ [PWRAP_WACS2_VLDCLR] = 0xa8,
+ [PWRAP_INT_EN] = 0xac,
+ [PWRAP_INT_FLG_RAW] = 0xb0,
+ [PWRAP_INT_FLG] = 0xb4,
+ [PWRAP_INT_CLR] = 0xb8,
+ [PWRAP_SIG_ADR] = 0xbc,
+ [PWRAP_SIG_MODE] = 0xc0,
+ [PWRAP_SIG_VALUE] = 0xc4,
+ [PWRAP_SIG_ERRVAL] = 0xc8,
+ [PWRAP_CRC_EN] = 0xcc,
+ [PWRAP_TIMER_EN] = 0xd0,
+ [PWRAP_TIMER_STA] = 0xd4,
+ [PWRAP_WDT_UNIT] = 0xd8,
+ [PWRAP_WDT_SRC_EN] = 0xdc,
+ [PWRAP_WDT_FLG] = 0xe0,
+ [PWRAP_DEBUG_INT_SEL] = 0xe4,
+ [PWRAP_DVFS_ADR0] = 0xe8,
+ [PWRAP_DVFS_WDATA0] = 0xec,
+ [PWRAP_DVFS_ADR1] = 0xf0,
+ [PWRAP_DVFS_WDATA1] = 0xf4,
+ [PWRAP_DVFS_ADR2] = 0xf8,
+ [PWRAP_DVFS_WDATA2] = 0xfc,
+ [PWRAP_DVFS_ADR3] = 0x100,
+ [PWRAP_DVFS_WDATA3] = 0x104,
+ [PWRAP_DVFS_ADR4] = 0x108,
+ [PWRAP_DVFS_WDATA4] = 0x10c,
+ [PWRAP_DVFS_ADR5] = 0x110,
+ [PWRAP_DVFS_WDATA5] = 0x114,
+ [PWRAP_DVFS_ADR6] = 0x118,
+ [PWRAP_DVFS_WDATA6] = 0x11c,
+ [PWRAP_DVFS_ADR7] = 0x120,
+ [PWRAP_DVFS_WDATA7] = 0x124,
+ [PWRAP_SPMINF_STA] = 0x128,
+ [PWRAP_CIPHER_KEY_SEL] = 0x12c,
+ [PWRAP_CIPHER_IV_SEL] = 0x130,
+ [PWRAP_CIPHER_EN] = 0x134,
+ [PWRAP_CIPHER_RDY] = 0x138,
+ [PWRAP_CIPHER_MODE] = 0x13c,
+ [PWRAP_CIPHER_SWRST] = 0x140,
+ [PWRAP_DCM_EN] = 0x144,
+ [PWRAP_DCM_DBC_PRD] = 0x148,
+};
+
+static int mt8135_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xc,
+ [PWRAP_CSHEXT] = 0x10,
+ [PWRAP_CSHEXT_WRITE] = 0x14,
+ [PWRAP_CSHEXT_READ] = 0x18,
+ [PWRAP_CSLEXT_START] = 0x1c,
+ [PWRAP_CSLEXT_END] = 0x20,
+ [PWRAP_STAUPD_PRD] = 0x24,
+ [PWRAP_STAUPD_GRPEN] = 0x28,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
+ [PWRAP_STAUPD_STA] = 0x30,
+ [PWRAP_EVENT_IN_EN] = 0x34,
+ [PWRAP_EVENT_DST_EN] = 0x38,
+ [PWRAP_WRAP_STA] = 0x3c,
+ [PWRAP_RRARB_INIT] = 0x40,
+ [PWRAP_RRARB_EN] = 0x44,
+ [PWRAP_RRARB_STA0] = 0x48,
+ [PWRAP_RRARB_STA1] = 0x4c,
+ [PWRAP_HARB_INIT] = 0x50,
+ [PWRAP_HARB_HPRIO] = 0x54,
+ [PWRAP_HIPRIO_ARB_EN] = 0x58,
+ [PWRAP_HARB_STA0] = 0x5c,
+ [PWRAP_HARB_STA1] = 0x60,
+ [PWRAP_MAN_EN] = 0x64,
+ [PWRAP_MAN_CMD] = 0x68,
+ [PWRAP_MAN_RDATA] = 0x6c,
+ [PWRAP_MAN_VLDCLR] = 0x70,
+ [PWRAP_WACS0_EN] = 0x74,
+ [PWRAP_INIT_DONE0] = 0x78,
+ [PWRAP_WACS0_CMD] = 0x7c,
+ [PWRAP_WACS0_RDATA] = 0x80,
+ [PWRAP_WACS0_VLDCLR] = 0x84,
+ [PWRAP_WACS1_EN] = 0x88,
+ [PWRAP_INIT_DONE1] = 0x8c,
+ [PWRAP_WACS1_CMD] = 0x90,
+ [PWRAP_WACS1_RDATA] = 0x94,
+ [PWRAP_WACS1_VLDCLR] = 0x98,
+ [PWRAP_WACS2_EN] = 0x9c,
+ [PWRAP_INIT_DONE2] = 0xa0,
+ [PWRAP_WACS2_CMD] = 0xa4,
+ [PWRAP_WACS2_RDATA] = 0xa8,
+ [PWRAP_WACS2_VLDCLR] = 0xac,
+ [PWRAP_INT_EN] = 0xb0,
+ [PWRAP_INT_FLG_RAW] = 0xb4,
+ [PWRAP_INT_FLG] = 0xb8,
+ [PWRAP_INT_CLR] = 0xbc,
+ [PWRAP_SIG_ADR] = 0xc0,
+ [PWRAP_SIG_MODE] = 0xc4,
+ [PWRAP_SIG_VALUE] = 0xc8,
+ [PWRAP_SIG_ERRVAL] = 0xcc,
+ [PWRAP_CRC_EN] = 0xd0,
+ [PWRAP_EVENT_STA] = 0xd4,
+ [PWRAP_EVENT_STACLR] = 0xd8,
+ [PWRAP_TIMER_EN] = 0xdc,
+ [PWRAP_TIMER_STA] = 0xe0,
+ [PWRAP_WDT_UNIT] = 0xe4,
+ [PWRAP_WDT_SRC_EN] = 0xe8,
+ [PWRAP_WDT_FLG] = 0xec,
+ [PWRAP_DEBUG_INT_SEL] = 0xf0,
+ [PWRAP_CIPHER_KEY_SEL] = 0x134,
+ [PWRAP_CIPHER_IV_SEL] = 0x138,
+ [PWRAP_CIPHER_LOAD] = 0x13c,
+ [PWRAP_CIPHER_START] = 0x140,
+ [PWRAP_CIPHER_RDY] = 0x144,
+ [PWRAP_CIPHER_MODE] = 0x148,
+ [PWRAP_CIPHER_SWRST] = 0x14c,
+ [PWRAP_DCM_EN] = 0x15c,
+ [PWRAP_DCM_DBC_PRD] = 0x160,
+};
+
+enum pmic_type {
+ PMIC_MT6323,
+ PMIC_MT6356,
+ PMIC_MT6358,
+ PMIC_MT6380,
+ PMIC_MT6389,
+ PMIC_MT6397,
+};
+
+enum pwrap_type {
+ PWRAP_MT2701,
+ PWRAP_MT2731,
+ PWRAP_MT7622,
+ PWRAP_MT8135,
+ PWRAP_MT8173,
+ PWRAP_MT8183,
+};
+
+struct pmic_wrapper;
+struct pwrap_slv_type {
+ const u32 *dew_regs;
+ enum pmic_type type;
+ const struct regmap_config *regmap;
+ /* Flags indicating the capability for the target slave */
+ u32 caps;
+ /*
+ * pwrap operations are highly associated with the PMIC types,
+ * so the pointers added increases flexibility allowing determination
+ * which type is used by the detection through device tree.
+ */
+ int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
+ int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
+};
+
+struct pmic_wrapper {
+ struct device *dev;
+ void __iomem *base;
+ struct regmap *regmap;
+ const struct pmic_wrapper_type *master;
+ const struct pwrap_slv_type *slave;
+ struct clk *clk_spi;
+ struct clk *clk_wrap;
+ struct reset_control *rstc;
+
+ struct reset_control *rstc_bridge;
+ void __iomem *bridge_base;
+};
+
+struct pmic_wrapper_type {
+ int *regs;
+ enum pwrap_type type;
+ u32 arb_en_all;
+ u32 int_en_all;
+ u32 int1_en_all;
+ u32 spi_w;
+ u32 wdt_src;
+ unsigned int has_bridge:1;
+ /* Flags indicating the capability for the target pwrap */
+ u32 caps;
+ int (*init_reg_clock)(struct pmic_wrapper *wrp);
+ int (*init_soc_specific)(struct pmic_wrapper *wrp);
+};
+
+static struct pmic_wrapper *wrp;
+
+static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg);
+static void pwrap_writel(struct pmic_wrapper *wrp, u32 val,
+ enum pwrap_regs reg);
+static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
+static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
+
+inline void pwrap_dump_ap_cmd_logging_register(void)
+{
+ unsigned int i = 0, offset = 0, log_size = 0;
+ unsigned int ch[16] = {0}, rw[16] = {0}, cmd[16] = {0}, dat[16] = {0};
+ unsigned int j = 0, s = 0, e = 0, tmp_dat = 0;
+ unsigned int *reg_addr;
+
+ log_size += sprintf(pwrap_log_buf, "\npwrap ");
+ s = wrp->master->regs[PWRAP_CHANNEL_SEQUENCE_0]/4;
+ e = wrp->master->regs[PWRAP_CHANNEL_SEQUENCE_3]/4;
+ for (i = s; i <= e; i++) {
+ reg_addr = wrp->base + (i * 4);
+ tmp_dat = readl(reg_addr);
+ ch[j] = tmp_dat & 0xff;
+ ch[j+1] = (tmp_dat & 0xff00) >> 8;
+ ch[j+2] = (tmp_dat & 0xff0000) >> 16;
+ ch[j+3] = (tmp_dat & 0xff000000) >> 24;
+ j += 4;
+ }
+ j = 0;
+ s = wrp->master->regs[PWRAP_CMD_SEQUENCE_0]/4;
+ e = wrp->master->regs[PWRAP_CMD_SEQUENCE_7]/4;
+ for (i = s; i <= e; i++) {
+ reg_addr = wrp->base + (i * 4);
+ tmp_dat = readl(reg_addr);
+ rw[j] = (tmp_dat >> 15) & 0x1;
+ cmd[j] = (tmp_dat & 0x7fff) << 1;
+ rw[j+1] = (tmp_dat >> 31);
+ cmd[j+1] = ((tmp_dat & 0x7fff0000) >> 16) << 1;
+ j += 2;
+ }
+ j = 0;
+ s = wrp->master->regs[PWRAP_WDATA_SEQUENCE_0]/4;
+ e = wrp->master->regs[PWRAP_WDATA_SEQUENCE_7]/4;
+ for (i = s; i <= e; i++) {
+ reg_addr = wrp->base + (i * 4);
+ tmp_dat = readl(reg_addr);
+ dat[j] = tmp_dat & 0xffff;
+ dat[j+1] = (tmp_dat & 0xffff0000) >> 16;
+ j += 2;
+ }
+ for (i = 0; i < 16; i++) {
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "[ch:%x, w:%d, adr:0x%04x, dat:0x%04x]",
+ ch[i], rw[i], cmd[i], dat[i]);
+ if (i == 0)
+ continue;
+
+ if (i % 2 == 0) {
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "log_size:%d\npwrap ", log_size);
+ }
+ }
+ dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
+ log_size = 0;
+ for (i = 0; i <= 14; i++) {
+ offset = 0xc00 + i * 4;
+ reg_addr = wrp->base + offset;
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x) = 0x%x ", offset, readl(reg_addr));
+ }
+ dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1)) {
+ pwrap_writel(wrp, 0x8, PWRAP_MONITOR_CTRL_0);
+ pwrap_writel(wrp, 0x5, PWRAP_MONITOR_CTRL_0);
+ } else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V2)) {
+ pwrap_writel(wrp, 0x800, PWRAP_MONITOR_CTRL_0);
+ pwrap_writel(wrp, 0x5, PWRAP_MONITOR_CTRL_0);
+ }
+}
+static inline void pwrap_dump_sta_register(unsigned int st, unsigned int nd)
+{
+ unsigned int i = 0, log_size = 0, start = 0, end = 0;
+ unsigned int *reg_addr;
+
+ start = st/4;
+ end = nd/4;
+
+ for (i = start; i <= end; i++) {
+ reg_addr = wrp->base + (i * 4);
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x ", i * 4, readl(reg_addr));
+
+ if (i == 0)
+ continue;
+ if (i % 8 == 0) {
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "log_size:%d\npwrap ", log_size);
+ }
+ if (i % 0x28 == 0) {
+ dev_dbg(wrp->dev, "\npwrap %s %d\n",
+ pwrap_log_buf, log_size);
+ log_size = 0;
+ }
+ }
+ dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
+ log_size = 0;
+ pwrap_dump_ap_cmd_logging_register();
+}
+
+static inline void pwrap_dump_busy_register(void)
+{
+ unsigned int log_size = 0;
+
+ log_size += sprintf(pwrap_log_buf,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
+ wrp->master->regs[PWRAP_DCXO_CONN_ADR0],
+ pwrap_readl(wrp, PWRAP_DCXO_CONN_ADR0),
+ wrp->master->regs[PWRAP_DCXO_CONN_WDATA0],
+ pwrap_readl(wrp, PWRAP_DCXO_CONN_WDATA0),
+ wrp->master->regs[PWRAP_DCXO_CONN_ADR1],
+ pwrap_readl(wrp, PWRAP_DCXO_CONN_ADR1),
+ wrp->master->regs[PWRAP_DCXO_CONN_WDATA1],
+ pwrap_readl(wrp, PWRAP_DCXO_CONN_WDATA1));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
+ wrp->master->regs[PWRAP_DCXO_NFC_ADR0],
+ pwrap_readl(wrp, PWRAP_DCXO_NFC_ADR0),
+ wrp->master->regs[PWRAP_DCXO_NFC_WDATA0],
+ pwrap_readl(wrp, PWRAP_DCXO_NFC_WDATA0),
+ wrp->master->regs[PWRAP_DCXO_NFC_ADR1],
+ pwrap_readl(wrp, PWRAP_DCXO_NFC_ADR1),
+ wrp->master->regs[PWRAP_DCXO_NFC_WDATA1],
+ pwrap_readl(wrp, PWRAP_DCXO_NFC_WDATA1));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
+ wrp->master->regs[PWRAP_SPMINF_STA],
+ pwrap_readl(wrp, PWRAP_SPMINF_STA),
+ wrp->master->regs[PWRAP_SPMINF_STA_1],
+ pwrap_readl(wrp, PWRAP_SPMINF_STA_1),
+ wrp->master->regs[PWRAP_SPMINF_BACKUP_STA],
+ pwrap_readl(wrp, PWRAP_SPMINF_BACKUP_STA),
+ wrp->master->regs[PWRAP_SCPINF_STA],
+ pwrap_readl(wrp, PWRAP_SCPINF_STA));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "pwrap (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
+ wrp->master->regs[PWRAP_CONNINF_STA_0],
+ pwrap_readl(wrp, PWRAP_CONNINF_STA_0),
+ wrp->master->regs[PWRAP_CONNINF_STA_1],
+ pwrap_readl(wrp, PWRAP_CONNINF_STA_1),
+ wrp->master->regs[PWRAP_MCU_PMINF_STA_0],
+ pwrap_readl(wrp, PWRAP_MCU_PMINF_STA_0),
+ wrp->master->regs[PWRAP_MCU_PMINF_STA_1],
+ pwrap_readl(wrp, PWRAP_MCU_PMINF_STA_1));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
+ wrp->master->regs[PWRAP_GPSINF_0_STA],
+ pwrap_readl(wrp, PWRAP_GPSINF_0_STA),
+ wrp->master->regs[PWRAP_GPSINF_1_STA],
+ pwrap_readl(wrp, PWRAP_GPSINF_1_STA),
+ wrp->master->regs[PWRAP_MD_ADCINF_0_STA_0],
+ pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_0),
+ wrp->master->regs[PWRAP_MD_ADCINF_0_STA_1],
+ pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_1));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "pwrap (0x%x)=0x%x (0x%x)=0x%x",
+ wrp->master->regs[PWRAP_MD_ADCINF_1_STA_0],
+ pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_0),
+ wrp->master->regs[PWRAP_MD_ADCINF_1_STA_1],
+ pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_1));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
+ wrp->master->regs[PWRAP_WACS2_CMD],
+ pwrap_readl(wrp, PWRAP_WACS2_CMD),
+ wrp->master->regs[PWRAP_WACS2_RDATA],
+ pwrap_readl(wrp, PWRAP_WACS2_RDATA),
+ wrp->master->regs[PWRAP_WACS2_VLDCLR],
+ pwrap_readl(wrp, PWRAP_WACS2_VLDCLR),
+ wrp->master->regs[PWRAP_WACS0_RDATA],
+ pwrap_readl(wrp, PWRAP_WACS0_RDATA));
+
+ dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
+ log_size = 0;
+
+ pwrap_dump_sta_register(wrp->master->regs[PWRAP_STARV_COUNTER_0],
+ wrp->master->regs[PWRAP_MONITOR_CTRL_3]);
+}
+
+static inline void pwrap_dump_ap_register(void)
+{
+ pwrap_dump_sta_register(0x0, 0x48c);
+}
+
+static inline void pwrap_dump_pmic_register(void)
+{
+ unsigned int rdata = 0;
+
+ dev_dbg(wrp->dev, "dump PMIC register\n");
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], &rdata);
+ dev_dbg(wrp->dev, "[REG]0x%x=0x%x\n",
+ wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], rdata);
+ /* Write Test */
+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ PWRAP_DEW_WRITE_TEST_VAL) ||
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ &rdata) ||
+ (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
+ dev_dbg(wrp->dev, "pwrap rdata=0x%04X\n", rdata);
+ }
+}
+
+static void pwrap_mpu_info(void)
+{
+ unsigned int log_size = 0;
+
+ log_size += sprintf(pwrap_log_buf,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_0],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_0),
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_1],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_1),
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_2],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_2),
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0));
+
+ log_size += sprintf(pwrap_log_buf + log_size,
+ "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1),
+ wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2],
+ pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2),
+ wrp->master->regs[PWRAP_MPU_PWRAP_ACC_VIO_INFO_0],
+ pwrap_readl(wrp, PWRAP_MPU_PWRAP_ACC_VIO_INFO_0),
+ wrp->master->regs[PWRAP_MPU_PWRAP_ACC_VIO_INFO_1],
+ pwrap_readl(wrp, PWRAP_MPU_PWRAP_ACC_VIO_INFO_1));
+
+ dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
+}
+
+static void pwrap_dump_pmic_cmd_logging_register(void)
+{
+ unsigned int rdata = 0, sub_return = 0;
+
+ /* Read Last three command */
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD0], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_CMD0:0x%x (The last cmd addr)\n", rdata & 0x3fff);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA0], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_WDATA0:0x%x (The last cmd wdata)\n", rdata);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD1], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_CMD1:0x%x (The sec-last cmd addr)\n", rdata & 0x3fff);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA1], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_WDATA1:0x%x (The second-last cmd wdata)\n", rdata);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD2], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_CMD2:0x%x (The third cmd addr)\n", rdata & 0x3fff);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA2], &rdata);
+ dev_dbg(wrp->dev,
+ "REC_WDATA2:0x%x (The third-last cmd wdata)\n", rdata);
+
+ /* Enable Command Recording */
+ sub_return = pwrap_write(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_RG_EN_RECORD], 0x3);
+ if (sub_return != 0)
+ dev_dbg(wrp->dev, "en spi debug fail, ret=%x\n", sub_return);
+ dev_dbg(wrp->dev, "enable spi debug ok\n");
+
+ /* Clear Last three command */
+ sub_return = pwrap_write(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_RG_SPI_RECORD_CLR], 0x1);
+ if (sub_return != 0)
+ dev_dbg(wrp->dev, "clr rec cmd fail, ret=%x\n", sub_return);
+ sub_return = pwrap_write(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_RG_SPI_RECORD_CLR], 0x0);
+ if (sub_return != 0)
+ dev_dbg(wrp->dev, "clr rec cmd fail, ret=%x\n", sub_return);
+ dev_dbg(wrp->dev, "clear record command ok\n");
+
+}
+
+void pwrap_dump_all_register(void)
+{
+ unsigned int rdata = 0;
+
+ /* add tsx/dcxo temperture log support */
+ rdata = pwrap_readl(wrp, PWRAP_SPMINF_STA);
+ dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
+ wrp->master->regs[PWRAP_SPMINF_STA], rdata);
+ rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_0);
+ dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
+ wrp->master->regs[PWRAP_MD_ADCINF_0_STA_0], rdata);
+ rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_1);
+ dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
+ wrp->master->regs[PWRAP_MD_ADCINF_0_STA_1], rdata);
+ rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_0);
+ dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
+ wrp->master->regs[PWRAP_MD_ADCINF_1_STA_0], rdata);
+ rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_1);
+ dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
+ wrp->master->regs[PWRAP_MD_ADCINF_1_STA_1], rdata);
+}
+
+void pwrap_dump_and_recovery(void)
+{
+ pwrap_dump_sta_register(0x0, 0x48c);
+ pwrap_dump_pmic_register();
+
+ pwrap_writel(wrp, 0x0, PWRAP_WACS2_EN);
+ pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
+}
+static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
+{
+ return readl(wrp->base + wrp->master->regs[reg]);
+}
+
+static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
+{
+ writel(val, wrp->base + wrp->master->regs[reg]);
+}
+
+static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
+{
+ u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
+
+ return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
+}
+
+static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
+{
+ u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
+
+ return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
+}
+
+/*
+ * Timeout issue sometimes caused by the last read command
+ * failed because pmic wrap could not got the FSM_VLDCLR
+ * in time after finishing WACS2_CMD. It made state machine
+ * still on FSM_VLDCLR and timeout next time.
+ * Check the status of FSM and clear the vldclr to recovery the
+ * error.
+ */
+static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
+{
+ if (pwrap_is_fsm_vldclr(wrp))
+ pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
+}
+
+static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
+{
+ return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
+}
+
+static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
+{
+ u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
+
+ return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
+ (val & PWRAP_STATE_SYNC_IDLE0);
+}
+
+static int pwrap_timeout_ns(unsigned long long start_time_ns,
+ unsigned long long timeout_time_ns)
+{
+ unsigned long long cur_time = 0;
+ unsigned long long elapse_time = 0;
+
+ /* get current tick */
+ cur_time = sched_clock(); /* ns */
+
+ /* avoid timer over flow exiting in FPGA env */
+ if (cur_time < start_time_ns)
+ start_time_ns = cur_time;
+
+ elapse_time = cur_time - start_time_ns;
+
+ /* check if timeout */
+ if (timeout_time_ns <= elapse_time) {
+ dev_notice(wrp->dev,
+ "[PWRAP] Timeout start time: %lld\n", start_time_ns);
+ dev_notice(wrp->dev,
+ "[PWRAP] Timeout cur time: %lld\n", cur_time);
+ dev_notice(wrp->dev,
+ "[PWRAP] Timeout elapse time: %lld\n", elapse_time);
+ dev_notice(wrp->dev,
+ "[PWRAP] Timeout set timeout: %lld\n", timeout_time_ns);
+ return 1;
+ }
+ return 0;
+}
+
+static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
+ bool (*fp)(struct pmic_wrapper *))
+{
+ unsigned long long start_time_ns = 0, timeout_ns = 0;
+
+ start_time_ns = sched_clock();
+ timeout_ns = 10000 * 1000; /* 10000us */
+
+ do {
+ if (pwrap_timeout_ns(start_time_ns, timeout_ns)) {
+ if (fp(wrp))
+ return 0;
+ else if ((pwrap_readl(wrp,
+ PWRAP_MPU_PMIC_ACC_VIO_INFO_0)
+ & 0x20000000) != 0) {
+ /* check if timeout is caused by mpu vio */
+ dev_dbg(wrp->dev,
+ "[PWRAP] FSM Timeout MPU Violation\n");
+ return 1;
+ } else if (fp(wrp) == 0) {
+ dev_notice(wrp->dev, "[PWRAP] FSM Timeout\n");
+ pwrap_dump_busy_register();
+ /* TBD
+ * aee_kernel_warning("PWRAP:FSM Timeout",
+ * "PWRAP");
+ */
+ return -ETIMEDOUT;
+ }
+ }
+ if (fp(wrp))
+ return 0;
+ } while (1);
+}
+
+static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+{
+ int ret = 0;
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
+ if (ret)
+ return ret;
+
+ *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
+
+ pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
+
+ return 0;
+}
+
+static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+{
+ int ret, msb;
+
+ *rdata = 0;
+ for (msb = 0; msb < 2; msb++) {
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
+ PWRAP_WACS2_CMD);
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
+ if (ret)
+ return ret;
+
+ *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
+ PWRAP_WACS2_RDATA)) << (16 * msb));
+
+ pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
+ }
+
+ return 0;
+}
+
+static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+{
+ return wrp->slave->pwrap_read(wrp, adr, rdata);
+}
+
+static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ int ret = 0;
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
+ PWRAP_WACS2_CMD);
+
+ return 0;
+}
+
+static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ int ret, msb, rdata;
+
+ for (msb = 0; msb < 2; msb++) {
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+ if (ret) {
+ pwrap_leave_fsm_vldclr(wrp);
+ return ret;
+ }
+
+ pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
+ ((wdata >> (msb * 16)) & 0xffff),
+ PWRAP_WACS2_CMD);
+
+ /*
+ * The pwrap_read operation is the requirement of hardware used
+ * for the synchronization between two successive 16-bit
+ * pwrap_writel operations composing one 32-bit bus writing.
+ * Otherwise, we'll find the result fails on the lower 16-bit
+ * pwrap writing.
+ */
+ if (!msb)
+ pwrap_read(wrp, adr, &rdata);
+ }
+
+ return 0;
+}
+
+static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+{
+ return wrp->slave->pwrap_write(wrp, adr, wdata);
+}
+
+static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
+{
+ return pwrap_read(context, adr, rdata);
+}
+
+static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
+{
+ return pwrap_write(context, adr, wdata);
+}
+
+static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
+{
+ int ret = 0, i = 0;
+
+ pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
+ pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
+ pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
+ pwrap_writel(wrp, 1, PWRAP_MAN_EN);
+ pwrap_writel(wrp, 0, PWRAP_DIO_EN);
+
+ pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
+ PWRAP_MAN_CMD);
+ pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
+ PWRAP_MAN_CMD);
+ pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
+ PWRAP_MAN_CMD);
+
+ for (i = 0; i < 4; i++)
+ pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
+ PWRAP_MAN_CMD);
+
+ ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
+ if (ret) {
+ dev_dbg(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ pwrap_writel(wrp, 0, PWRAP_MAN_EN);
+ pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
+
+ return 0;
+}
+
+/*
+ * pwrap_init_sidly - configure serial input delay
+ *
+ * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
+ * delay. Do a read test with all possible values and chose the best delay.
+ */
+static int pwrap_init_sidly(struct pmic_wrapper *wrp)
+{
+ u32 rdata = 0;
+ u32 i = 0;
+ u32 pass = 0;
+ signed char dly[16] = {
+ -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
+ };
+
+ for (i = 0; i < 4; i++) {
+ pwrap_writel(wrp, i, PWRAP_SIDLY);
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
+ &rdata);
+ if (rdata == PWRAP_DEW_READ_TEST_VAL) {
+ dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
+ pass |= 1 << i;
+ }
+ }
+
+ if (dly[pass] < 0) {
+ dev_dbg(wrp->dev, "sidly pass range 0x%x not continuous\n",
+ pass);
+ return -EIO;
+ }
+
+ pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
+
+ return 0;
+}
+
+static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
+{
+ int ret = 0;
+ u32 rdata = 0;
+
+ /* Enable dual IO mode */
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
+
+ /* Check IDLE & INIT_DONE in advance */
+ ret = pwrap_wait_for_state(wrp,
+ pwrap_is_fsm_idle_and_sync_idle);
+ if (ret) {
+ dev_dbg(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ pwrap_writel(wrp, 1, PWRAP_DIO_EN);
+
+ /* Read Test */
+ pwrap_read(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
+ if (rdata != PWRAP_DEW_READ_TEST_VAL) {
+ dev_dbg(wrp->dev,
+ "Read failed on DIO mode: 0x%04x!=0x%04x\n",
+ PWRAP_DEW_READ_TEST_VAL, rdata);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+/*
+ * pwrap_init_chip_select_ext is used to configure CS extension time for each
+ * phase during data transactions on the pwrap bus.
+ */
+static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
+ u8 hext_read, u8 lext_start,
+ u8 lext_end)
+{
+ /*
+ * After finishing a write and read transaction, extends CS high time
+ * to be at least xT of BUS CLK as hext_write and hext_read specifies
+ * respectively.
+ */
+ pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
+ pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
+
+ /*
+ * Extends CS low time after CSL and before CSH command to be at
+ * least xT of BUS CLK as lext_start and lext_end specifies
+ * respectively.
+ */
+ pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
+ pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
+}
+
+static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
+{
+ switch (wrp->master->type) {
+
+ case PWRAP_MT2731:
+ pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
+ pwrap_init_chip_select_ext(wrp, 0x88, 0x55, 3, 0);
+ break;
+ case PWRAP_MT8173:
+ pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
+ break;
+ case PWRAP_MT8135:
+ pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
+ pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
+{
+ switch (wrp->slave->type) {
+ case PMIC_MT6397:
+ pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
+ pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
+ break;
+
+ case PMIC_MT6323:
+ pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
+ pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
+{
+ return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
+}
+
+static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
+{
+ u32 rdata = 0;
+ int ret = 0;
+
+ ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
+ &rdata);
+ if (ret)
+ return 0;
+
+ return rdata == 1;
+}
+
+static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+{
+ int ret = 0;
+ u32 rdata = 0;
+
+ pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
+ pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
+ pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
+ pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
+
+ switch (wrp->master->type) {
+ case PWRAP_MT8135:
+ pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
+ pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
+ break;
+ case PWRAP_MT2701:
+ case PWRAP_MT2731:
+ case PWRAP_MT8173:
+ pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
+ break;
+ case PWRAP_MT7622:
+ pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
+ break;
+ default:
+ break;
+ }
+
+ /* Config cipher mode @PMIC */
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
+
+ switch (wrp->slave->type) {
+ case PMIC_MT6397:
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
+ 0x1);
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
+ 0x1);
+ break;
+ case PMIC_MT6323:
+ case PMIC_MT6356:
+ case PMIC_MT6389:
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
+ 0x1);
+ break;
+ default:
+ break;
+ }
+
+ /* wait for cipher data ready@AP */
+ ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
+ if (ret) {
+ dev_dbg(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
+ return ret;
+ }
+
+ /* wait for cipher data ready@PMIC */
+ ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
+ if (ret) {
+ dev_dbg(wrp->dev,
+ "timeout waiting for cipher data ready@PMIC\n");
+ return ret;
+ }
+
+ /* wait for cipher mode idle */
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
+ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
+ if (ret) {
+ dev_dbg(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
+ return ret;
+ }
+
+ pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
+
+ /* Write Test */
+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ PWRAP_DEW_WRITE_TEST_VAL) ||
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ &rdata) ||
+ (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
+ dev_dbg(wrp->dev, "rdata=0x%04X\n", rdata);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int pwrap_init_security(struct pmic_wrapper *wrp)
+{
+ int ret = 0;
+
+ /* Enable encryption */
+ ret = pwrap_init_cipher(wrp);
+ if (ret)
+ return ret;
+
+ /* Signature checking - using CRC */
+ if (pwrap_write(wrp,
+ wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
+ return -EFAULT;
+
+ pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
+ pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
+ pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
+ PWRAP_SIG_ADR);
+ pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
+
+ return 0;
+}
+
+static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ /* enable pwrap events and pwrap bridge in AP side */
+ pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
+ pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
+ writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
+ writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
+ writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
+ writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
+ writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
+ writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
+ writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
+
+ /* enable PMIC event out and sources */
+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
+ 0x1) ||
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
+ 0xffff)) {
+ dev_dbg(wrp->dev, "enable dewrap fail\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ /* PMIC_DEWRAP enables */
+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
+ 0x1) ||
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
+ 0xffff)) {
+ dev_dbg(wrp->dev, "enable dewrap fail\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ /* GPS_INTF initialization */
+ switch (wrp->slave->type) {
+ case PMIC_MT6323:
+ pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
+ pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
+ pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
+ pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
+ pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
+ /* enable 2wire SPI master */
+ pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
+
+ return 0;
+}
+
+static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
+{
+ pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
+
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
+ pwrap_writel(wrp, 1, PWRAP_CRC_EN);
+ pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
+ pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
+
+ pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
+ pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
+ pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
+ pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
+
+ return 0;
+}
+
+/*
+ * pwrap_set_starvation is used to configure starvation counter for dynamic
+ * adjust channel arbiter priority.
+ */
+static int pwrap_set_starvation(struct pmic_wrapper *wrp)
+{
+ pwrap_writel(wrp, 0xf, PWRAP_HARB_HPRIO);
+ pwrap_writel(wrp, 0x402, PWRAP_STARV_COUNTER_0);
+ pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_1);
+ pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_2);
+ pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_3);
+ pwrap_writel(wrp, 0x40f, PWRAP_STARV_COUNTER_4);
+ pwrap_writel(wrp, 0x420, PWRAP_STARV_COUNTER_5);
+ pwrap_writel(wrp, 0x428, PWRAP_STARV_COUNTER_6);
+ pwrap_writel(wrp, 0x428, PWRAP_STARV_COUNTER_7);
+ pwrap_writel(wrp, 0x413, PWRAP_STARV_COUNTER_8);
+ pwrap_writel(wrp, 0x417, PWRAP_STARV_COUNTER_9);
+ pwrap_writel(wrp, 0x417, PWRAP_STARV_COUNTER_10);
+ pwrap_writel(wrp, 0x47c, PWRAP_STARV_COUNTER_11);
+ pwrap_writel(wrp, 0x47c, PWRAP_STARV_COUNTER_12);
+ pwrap_writel(wrp, 0x740, PWRAP_STARV_COUNTER_13);
+ pwrap_writel(wrp, 0x740, PWRAP_STARV_COUNTER_16);
+
+ return 0;
+}
+
+static int pwrap_init(struct pmic_wrapper *wrp)
+{
+ int ret;
+
+ reset_control_reset(wrp->rstc);
+ if (wrp->rstc_bridge)
+ reset_control_reset(wrp->rstc_bridge);
+
+ if (wrp->master->type == PWRAP_MT8173) {
+ /* Enable DCM */
+ pwrap_writel(wrp, 3, PWRAP_DCM_EN);
+ pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+ }
+
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
+ /* Reset SPI slave */
+ ret = pwrap_reset_spislave(wrp);
+ if (ret)
+ return ret;
+ }
+
+ pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
+
+ pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
+
+ pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
+
+ ret = wrp->master->init_reg_clock(wrp);
+ if (ret)
+ return ret;
+
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
+ /* Setup serial input delay */
+ ret = pwrap_init_sidly(wrp);
+ if (ret)
+ return ret;
+ }
+
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
+ /* Enable dual I/O mode */
+ ret = pwrap_init_dual_io(wrp);
+ if (ret)
+ return ret;
+ }
+
+ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
+ /* Enable security on bus */
+ ret = pwrap_init_security(wrp);
+ if (ret)
+ return ret;
+ }
+
+ if (wrp->master->type == PWRAP_MT8135)
+ pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
+
+ /* Add priority adjust setting, it used to avoid starvation */
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_PRIORITY_SEL)) {
+ pwrap_writel(wrp, 0x0b09080a, PWRAP_PRIORITY_USER_SEL_2);
+ pwrap_writel(wrp, 0x0b080a09, PWRAP_ARBITER_OUT_SEL_2);
+ pwrap_set_starvation(wrp);
+ }
+
+ pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
+ pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
+ pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
+ pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
+ pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
+
+ if (wrp->master->init_soc_specific) {
+ ret = wrp->master->init_soc_specific(wrp);
+ if (ret)
+ return ret;
+ }
+
+ /* Setup the init done registers */
+ pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
+ pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
+ pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
+ writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
+ writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
+ }
+
+ return 0;
+}
+
+static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
+{
+ u32 rdata = 0, int0_flg = 0, int1_flg = 0, ret = 0;
+ u32 wdt0_src_en = 0, wdt0_flg = 0, wdt1_src_en = 0, wdt1_flg = 0;
+ struct pmic_wrapper *wrp = dev_id;
+ const struct pwrap_slv_type *slv = wrp->slave;
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
+ int0_flg = pwrap_readl(wrp, PWRAP_INT0_FLG);
+ if ((int0_flg & 0xffffffff) != 0) {
+ dev_notice(wrp->dev,
+ "[PWRAP] INT0 error:0x%x\n", int0_flg);
+ pwrap_writel(wrp, int0_flg, PWRAP_INT0_CLR);
+ /* need to enable after SQC debug
+ *if ((int0_flg & 0x02) == 0x02)
+ * exec_ccci_kern_func_by_md_id
+ * (MD_SYS1, ID_FORCE_MD_ASSERT, NULL, 0);
+ */
+ }
+ int1_flg = pwrap_readl(wrp, PWRAP_INT1_FLG);
+ if ((int1_flg & 0xffffffff) != 0) {
+ dev_notice(wrp->dev,
+ "[PWRAP] INT1 error:0x%x\n", int1_flg);
+
+ if ((int1_flg & (0x3 << 11)) != 0) {
+ dev_dbg(wrp->dev,
+ "[PWRAP] MPU Access Violation\n");
+ pwrap_mpu_info();
+ pwrap_dump_ap_cmd_logging_register();
+ pwrap_dump_pmic_cmd_logging_register();
+ /* TBD
+ * aee_kernel_warning("PWRAP:MPU Violation",
+ * "PWRAP");
+ */
+ pwrap_writel(wrp, int1_flg, PWRAP_INT1_CLR);
+ } else {
+ pwrap_dump_busy_register();
+ pwrap_writel(wrp, 0xffffe7ff, PWRAP_INT1_CLR);
+ }
+ }
+
+ if ((int0_flg & 0x01) == 0x01) {
+ wdt0_src_en = pwrap_readl(wrp, PWRAP_WDT_SRC_EN);
+ wdt1_src_en = pwrap_readl(wrp, PWRAP_WDT_SRC_EN_1);
+ wdt0_flg = pwrap_readl(wrp, PWRAP_WDT_FLG);
+ wdt1_flg = pwrap_readl(wrp, PWRAP_WDT_FLG_1);
+ dev_notice(wrp->dev, "[PWRAP] WDT Timeout\n");
+ dev_notice(wrp->dev,
+ "[PWRAP] WDT_SRC_EN_0=0x%x\n", wdt0_src_en);
+ dev_notice(wrp->dev,
+ "[PWRAP] WDT_SRC_EN_1=0x%x\n", wdt1_src_en);
+ dev_notice(wrp->dev,
+ "[PWRAP] WDT_FLG_0=0x%x\n", wdt0_flg);
+ dev_notice(wrp->dev,
+ "[PWRAP] WDT_FLG_1=0x%x\n", wdt1_flg);
+ if ((wdt0_flg & 0x4000) == 0x4000) {
+ dev_notice(wrp->dev,
+ "[PWRAP] MD DVFS HW Timeout\n");
+ pwrap_dump_ap_register();
+ pwrap_dump_pmic_cmd_logging_register();
+ /* TBD
+ * aee_kernel_warning("PWRAP:WDT MD DVFS HW Timeout",
+ * "PWRAP:WDT MD DVFS HW Timeout");
+ */
+ }
+ } else if ((int0_flg & 0x02) == 0x02) {
+ dev_dbg(wrp->dev, "[PWRAP] CRC Error\n");
+ pwrap_dump_ap_cmd_logging_register();
+ pwrap_dump_pmic_cmd_logging_register();
+ /* TBD
+ *snprintf(str, 50, "PWRAP CRC=0x%x",
+ * pwrap_readl(wrp, PWRAP_SIG_ERRVAL));
+ *aee_kernel_warning(str, str);
+ */
+ pwrap_writel(wrp, wrp->master->int_en_all,
+ PWRAP_INT_EN);
+ /* Clear spislv CRC sta */
+ ret = pwrap_write(wrp,
+ slv->dew_regs[PWRAP_DEW_CRC_SWRST], 0x1);
+ if (ret != 0)
+ dev_dbg(wrp->dev, "clr fail, ret=%x\n", ret);
+ ret = pwrap_write(wrp,
+ slv->dew_regs[PWRAP_DEW_CRC_SWRST], 0x0);
+ if (ret != 0)
+ dev_dbg(wrp->dev, "clr fail, ret=%x\n", ret);
+ pwrap_write(wrp, slv->dew_regs[PWRAP_DEW_CRC_EN], 0x0);
+ pwrap_writel(wrp, 0x0, PWRAP_CRC_EN);
+ pwrap_writel(wrp,
+ pwrap_readl(wrp, PWRAP_STAUPD_GRPEN) & 0x1fe,
+ PWRAP_STAUPD_GRPEN);
+ }
+ } else {
+ rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
+
+ dev_dbg(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
+
+ pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
+ }
+ return IRQ_HANDLED;
+}
+
+static const struct regmap_config pwrap_regmap_config16 = {
+ .reg_bits = 16,
+ .val_bits = 16,
+ .reg_stride = 2,
+ .reg_read = pwrap_regmap_read,
+ .reg_write = pwrap_regmap_write,
+ .max_register = 0xffff,
+ .fast_io = true,
+};
+
+static const struct regmap_config pwrap_regmap_config32 = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .reg_read = pwrap_regmap_read,
+ .reg_write = pwrap_regmap_write,
+ .max_register = 0xffff,
+ .fast_io = true,
+};
+
+static const struct pwrap_slv_type pmic_mt6323 = {
+ .dew_regs = mt6323_regs,
+ .type = PMIC_MT6323,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+ PWRAP_SLV_CAP_SECURITY,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct pwrap_slv_type pmic_mt6356 = {
+ .dew_regs = mt6356_regs,
+ .type = PMIC_MT6356,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct pwrap_slv_type pmic_mt6358 = {
+ .dew_regs = mt6358_regs,
+ .type = PMIC_MT6358,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct pwrap_slv_type pmic_mt6380 = {
+ .dew_regs = NULL,
+ .type = PMIC_MT6380,
+ .regmap = &pwrap_regmap_config32,
+ .caps = 0,
+ .pwrap_read = pwrap_read32,
+ .pwrap_write = pwrap_write32,
+};
+
+static const struct pwrap_slv_type pmic_mt6389 = {
+ .dew_regs = mt6389_regs,
+ .type = PMIC_MT6389,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct pwrap_slv_type pmic_mt6397 = {
+ .dew_regs = mt6397_regs,
+ .type = PMIC_MT6397,
+ .regmap = &pwrap_regmap_config16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+ PWRAP_SLV_CAP_SECURITY,
+ .pwrap_read = pwrap_read16,
+ .pwrap_write = pwrap_write16,
+};
+
+static const struct of_device_id of_slave_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt6323",
+ .data = &pmic_mt6323,
+ }, {
+ .compatible = "mediatek,mt6356-pmic",
+ .data = &pmic_mt6356,
+ }, {
+ .compatible = "mediatek,mt6358-pmic",
+ .data = &pmic_mt6358,
+ }, {
+ /* The MT6380 PMIC only implements a regulator, so we bind it
+ * directly instead of using a MFD.
+ */
+ .compatible = "mediatek,mt6380-regulator",
+ .data = &pmic_mt6380,
+ }, {
+ .compatible = "mediatek,mt6389-pmic",
+ .data = &pmic_mt6389,
+ }, {
+ .compatible = "mediatek,mt6397",
+ .data = &pmic_mt6397,
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
+
+static const struct pmic_wrapper_type pwrap_mt2701 = {
+ .regs = mt2701_regs,
+ .type = PWRAP_MT2701,
+ .arb_en_all = 0x3f,
+ .int_en_all = ~(u32)(BIT(31) | BIT(2)),
+ .int1_en_all = 0,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .has_bridge = 0,
+ .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+ .init_reg_clock = pwrap_mt2701_init_reg_clock,
+ .init_soc_specific = pwrap_mt2701_init_soc_specific,
+};
+
+static const struct pmic_wrapper_type pwrap_mt2731 = {
+ .regs = mt2731_regs,
+ .type = PWRAP_MT2731,
+ .arb_en_all = 0x67D37,
+ .int_en_all = 0xffffffff,
+ .int1_en_all = 0x000017ff,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = 0x00000000,
+ .has_bridge = 0,
+ .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_MON_V1,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = NULL,
+};
+
+static const struct pmic_wrapper_type pwrap_mt7622 = {
+ .regs = mt7622_regs,
+ .type = PWRAP_MT7622,
+ .arb_en_all = 0xff,
+ .int_en_all = ~(u32)BIT(31),
+ .int1_en_all = 0,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .has_bridge = 0,
+ .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = pwrap_mt7622_init_soc_specific,
+};
+
+static const struct pmic_wrapper_type pwrap_mt8135 = {
+ .regs = mt8135_regs,
+ .type = PWRAP_MT8135,
+ .arb_en_all = 0x1ff,
+ .int_en_all = ~(u32)(BIT(31) | BIT(1)),
+ .int1_en_all = 0,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .has_bridge = 1,
+ .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = pwrap_mt8135_init_soc_specific,
+};
+
+static const struct pmic_wrapper_type pwrap_mt8173 = {
+ .regs = mt8173_regs,
+ .type = PWRAP_MT8173,
+ .arb_en_all = 0x3f,
+ .int_en_all = ~(u32)(BIT(31) | BIT(1)),
+ .int1_en_all = 0,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
+ .has_bridge = 0,
+ .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = pwrap_mt8173_init_soc_specific,
+};
+
+static const struct pmic_wrapper_type pwrap_mt8183 = {
+ .regs = mt8183_regs,
+ .type = PWRAP_MT8183,
+ .arb_en_all = 0x3fa75,
+ .int_en_all = 0xffffffff,
+ .int1_en_all = 0xeef7ffff,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .has_bridge = 0,
+ .caps = PWRAP_CAP_PRIORITY_SEL | PWRAP_CAP_INT1_EN |
+ PWRAP_CAP_WDT_SRC1,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = pwrap_mt8183_init_soc_specific,
+};
+
+static const struct of_device_id of_pwrap_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt2701-pwrap",
+ .data = &pwrap_mt2701,
+ }, {
+ .compatible = "mediatek,mt2731-pwrap",
+ .data = &pwrap_mt2731,
+ }, {
+ .compatible = "mediatek,mt7622-pwrap",
+ .data = &pwrap_mt7622,
+ }, {
+ .compatible = "mediatek,mt8135-pwrap",
+ .data = &pwrap_mt8135,
+ }, {
+ .compatible = "mediatek,mt8173-pwrap",
+ .data = &pwrap_mt8173,
+ }, {
+ .compatible = "mediatek,mt8183-pwrap",
+ .data = &pwrap_mt8183,
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
+
+struct regmap *pwrap_node_to_regmap(struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct pmic_wrapper *wrp;
+
+ pdev = of_find_device_by_node(np);
+
+ if (!pdev)
+ return ERR_PTR(-ENODEV);
+
+ wrp = platform_get_drvdata(pdev);
+
+ if (!wrp)
+ return ERR_PTR(-ENODEV);
+
+ return wrp->regmap;
+}
+EXPORT_SYMBOL_GPL(pwrap_node_to_regmap);
+
+/********************************************************************/
+/* return value : EINT_STA: [0]: CPU IRQ status in PMIC1 */
+/* [1]: MD32 IRQ status in PMIC1 */
+/* [2]: CPU IRQ status in PMIC2 */
+/* [3]: RESERVED */
+/********************************************************************/
+u32 pmic_wrap_eint_status(void)
+{
+ dev_dbg(wrp->dev,
+ "%s:0x%x\n", __func__,
+ pwrap_readl(wrp, PWRAP_EINT_STA));
+ return pwrap_readl(wrp, PWRAP_EINT_STA);
+}
+EXPORT_SYMBOL(pmic_wrap_eint_status);
+
+/********************************************************************/
+/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in PMIC1 */
+/* [1]: MD32 IRQ status in PMIC1 */
+/* [2]: CPU IRQ status in PMIC2 */
+/* [3]: RESERVED */
+/* para: offset is shift of clear bit which needs to clear */
+/********************************************************************/
+void pmic_wrap_eint_clr(int offset)
+{
+ dev_dbg(wrp->dev, "%s\n", __func__);
+ pwrap_writel(wrp, offset, PWRAP_EINT_CLR);
+}
+EXPORT_SYMBOL(pmic_wrap_eint_clr);
+static int pwrap_probe(struct platform_device *pdev)
+{
+ int ret = 0, irq = 0;
+ u32 rdata = 0;
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *of_slave_id = NULL;
+ struct resource *res;
+
+ if (np->child)
+ of_slave_id = of_match_node(of_slave_match_tbl, np->child);
+
+ if (!of_slave_id) {
+ dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
+ return -EINVAL;
+ }
+
+ wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
+ if (!wrp)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, wrp);
+
+ wrp->master = of_device_get_match_data(&pdev->dev);
+ wrp->slave = of_slave_id->data;
+ wrp->dev = &pdev->dev;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+ wrp->base = devm_ioremap_resource(wrp->dev, res);
+ if (IS_ERR(wrp->base))
+ return PTR_ERR(wrp->base);
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
+ wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
+ if (IS_ERR(wrp->rstc)) {
+ ret = PTR_ERR(wrp->rstc);
+ dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pwrap-bridge");
+ wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
+ if (IS_ERR(wrp->bridge_base))
+ return PTR_ERR(wrp->bridge_base);
+
+ wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
+ "pwrap-bridge");
+ if (IS_ERR(wrp->rstc_bridge)) {
+ ret = PTR_ERR(wrp->rstc_bridge);
+ dev_dbg(wrp->dev,
+ "cannot get pwrap-bridge reset: %d\n", ret);
+ return ret;
+ }
+ }
+
+ wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
+ if (IS_ERR(wrp->clk_spi)) {
+ dev_dbg(wrp->dev, "failed to get clock: %ld\n",
+ PTR_ERR(wrp->clk_spi));
+ return PTR_ERR(wrp->clk_spi);
+ }
+
+ wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
+ if (IS_ERR(wrp->clk_wrap)) {
+ dev_dbg(wrp->dev, "failed to get clock: %ld\n",
+ PTR_ERR(wrp->clk_wrap));
+ return PTR_ERR(wrp->clk_wrap);
+ }
+
+ ret = clk_prepare_enable(wrp->clk_spi);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(wrp->clk_wrap);
+ if (ret)
+ goto err_out1;
+
+ /*
+ * add dcm capability check
+ */
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
+ pwrap_writel(wrp, 1, PWRAP_DCM_EN);
+ pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+ }
+
+ /*
+ * The PMIC could already be initialized by the bootloader.
+ * Skip initialization here in this case.
+ */
+ if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
+ ret = pwrap_init(wrp);
+ if (ret) {
+ dev_dbg(wrp->dev, "init failed with %d\n", ret);
+ goto err_out2;
+ }
+ }
+
+ if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
+ dev_dbg(wrp->dev, "initialization isn't finished\n");
+ ret = -ENODEV;
+ goto err_out2;
+ }
+
+ /* Initialize watchdog, may not be done by the bootloader */
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1))
+ pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
+ /*
+ * Since STAUPD was not used on mt8173 platform,
+ * so STAUPD of WDT_SRC which should be turned off
+ */
+ pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
+
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1))
+ pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
+ pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
+ /*
+ * We add INT1 interrupt to handle starvation and request exception
+ * If we support it, we should enable them here.
+ */
+ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
+ pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
+
+ irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
+ IRQF_TRIGGER_HIGH, "mt-pmic-pwrap", wrp);
+ if (ret)
+ goto err_out2;
+
+ wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
+ if (IS_ERR(wrp->regmap)) {
+ ret = PTR_ERR(wrp->regmap);
+ goto err_out2;
+ }
+
+ ret = of_platform_populate(np, NULL, NULL, wrp->dev);
+ if (ret) {
+ dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
+ np);
+ goto err_out2;
+ }
+
+ /* Write Test */
+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ PWRAP_DEW_WRITE_TEST_VAL) ||
+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
+ &rdata) ||
+ (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
+ dev_dbg(wrp->dev, "pwrap rdata=0x%04X\n", rdata);
+ goto err_out2;
+ } else {
+ dev_dbg(wrp->dev, "[PWRAP] R/W PASS rdata=0x%04X\n", rdata);
+ }
+
+
+ return 0;
+
+err_out2:
+ clk_disable_unprepare(wrp->clk_wrap);
+err_out1:
+ clk_disable_unprepare(wrp->clk_spi);
+
+ return ret;
+}
+
+static int pwrap_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver pwrap_drv = {
+ .driver = {
+ .name = "mt-pmic-pwrap",
+ .of_match_table = of_match_ptr(of_pwrap_match_tbl),
+ },
+ .probe = pwrap_probe,
+ .remove = pwrap_remove,
+};
+
+static int __init pwrap_soc_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&pwrap_drv);
+ if (ret)
+ return -ENODEV;
+ return 0;
+}
+postcore_initcall(pwrap_soc_init);
+
+MODULE_AUTHOR("Flora Fu, MediaTek");
+MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c
new file mode 100644
index 0000000..1dc05a4
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ *
+ * Based on drivers/soc/mediatek/mtk-scpsys.c
+ *
+ * All the mtcmos enable/disable code is from DE. More closer to DE.
+ */
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+
+#include <dt-bindings/power/mt2731-power.h>
+
+static void __iomem *spm_base; /* spm */
+static void __iomem *infra_base; /* infra_ao */
+
+#define SPM_BASE spm_base
+#define INFRACFG_BASE infra_base
+
+#define spm_read(addr) readl(addr)
+#define spm_write(addr, val) writel((val), (addr))
+
+typedef int (*mtcmos_ops)(struct device *dev, int state);
+
+/* SPM Register. should be auto-gened. */
+#define POWERON_CONFIG_EN (SPM_BASE + 0x0000)
+#define PWR_STATUS (SPM_BASE + 0x0160)
+#define PWR_STATUS_2ND (SPM_BASE + 0x0164)
+#define MD1_PWR_CON (SPM_BASE + 0x0318)
+#define MD1_SRAM_ISOINT_B (SPM_BASE + 0x0320)
+#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x03B0)
+#define MD_EXTRA_PWR_CON (SPM_BASE + 0x03F0)
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+
+/* INFRASYS Register */
+#define INFRA_TOPAXI_PROTECTEN (INFRACFG_BASE + 0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA1 (INFRACFG_BASE + 0x0228)
+#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_BASE + 0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_BASE + 0x0258)
+#define INFRA_TOPAXI_PROTECTEN_SET (INFRACFG_BASE + 0x02A0)
+#define INFRA_TOPAXI_PROTECTEN_CLR (INFRACFG_BASE + 0x02A4)
+#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_BASE + 0x02A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_BASE + 0x02AC)
+#define VDNR_CON (INFRACFG_BASE + 0x71C)
+
+#define STA_POWER_DOWN 0
+#define STA_POWER_ON 1
+
+#define SRAM_ISOINT_B (1U << 6)
+#define SRAM_CKISO (1U << 5)
+#define PWR_CLK_DIS (1U << 4)
+#define PWR_ON_2ND (1U << 3)
+#define PWR_ON (1U << 2)
+#define PWR_ISO (1U << 1)
+#define PWR_RST_B (1U << 0)
+
+/* Kernel readl_poll wait-ack support timeout. */
+#define READL_POLL_SUPPORT 1
+
+/**************************************
+ * for NON-CPU MTCMOS
+ **************************************/
+/* Define MTCMOS Power Status Mask */
+#define MD1_PWR_STA_MASK (0x1 << 0)
+
+/* Define MTCMOS Bus Protect Mask */
+#define MD1_PROT_STEP1_0_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP1_0_ACK_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP2_0_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+#define MD1_PROT_STEP2_0_ACK_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+static int spm_mtcmos_ctrl_md1(struct device *dev, int state)
+{
+ int err = 0, tmp, ret;
+
+ /* TINFO="enable SPM register control" */
+ spm_write(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | (0x1 << 0));
+
+ if (state == STA_POWER_DOWN) {
+ /* TINFO="Start to turn off MD1" */
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Set bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP1_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ INFRA_TOPAXI_PROTECTEN_STA1, tmp,
+ (tmp & MD1_PROT_STEP1_0_ACK_MASK) ==
+ MD1_PROT_STEP1_0_ACK_MASK /* out */,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "MD1 step1_0 ack fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) &
+ MD1_PROT_STEP1_0_ACK_MASK) !=
+ MD1_PROT_STEP1_0_ACK_MASK) {
+ }
+ #endif
+#endif
+ /* TINFO="Set bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP2_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ INFRA_TOPAXI_PROTECTEN_STA1, tmp,
+ (tmp & MD1_PROT_STEP2_0_ACK_MASK) ==
+ MD1_PROT_STEP2_0_ACK_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "MD1 step2_0 ack fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) &
+ MD1_PROT_STEP2_0_ACK_MASK) !=
+ MD1_PROT_STEP2_0_ACK_MASK) {
+ }
+ #endif
+#endif
+ /* TINFO="MD_EXTRA_PWR_CON[0]=1"*/
+ spm_write(MD_EXTRA_PWR_CON,
+ spm_read(MD_EXTRA_PWR_CON) | (0x1 << 0));
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+ /* TINFO="Set PWR_ISO = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ISO);
+ /* TINFO="MD_SRAM_ISO_CON[0]=0"*/
+ spm_write(MD1_SRAM_ISOINT_B,
+ spm_read(MD1_SRAM_ISOINT_B) & ~(0x1 << 0));
+ /* TINFO="Set SRAM_PDN = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | (0x1 << 8));
+#ifndef IGNORE_MTCMOS_CHECK
+#endif
+ /* TINFO="Set PWR_ON = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS, tmp,
+ !(tmp & MD1_PWR_STA_MASK),
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWR STATUS MASK fail\n");
+ return ret;
+ }
+ #else
+ /* TINFO="Wait until MD1_PWR_STA_MASK = 0" */
+ while (spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) {
+ /* No logic between pwr_on and pwr_ack.
+ * Print SRAM / MTCMOS control and PWR_ACK for debug.
+ */
+ }
+ #endif
+#endif
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 3));
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Finish to turn off MD1" */
+ } else { /* STA_POWER_ON */
+ /* TINFO="Start to turn on MD1" */
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Set PWR_ON = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS, tmp,
+ (tmp & MD1_PWR_STA_MASK) == MD1_PWR_STA_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON STS1 ON MASK fail\n");
+ return ret;
+ }
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS_2ND, tmp,
+ (tmp & MD1_PWR_STA_MASK) == MD1_PWR_STA_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON STS2 ON MASK fail\n");
+ return ret;
+ }
+ #else
+ /* TINFO="Wait until PWR_STATUS = 1 and PWR_STATUS_2ND = 1" */
+ while (((spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) !=
+ MD1_PWR_STA_MASK) ||
+ ((spm_read(PWR_STATUS_2ND) & MD1_PWR_STA_MASK) !=
+ MD1_PWR_STA_MASK)) {
+ /* No logic between pwr_on and pwr_ack.
+ * Print SRAM / MTCMOS control and PWR_ACK for
+ * debug.
+ */
+ }
+ #endif
+#endif
+ /* TINFO="Set SRAM_PDN = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~(0x1 << 8));
+ /* TINFO="MD_SRAM_ISO_CON[0]=1"*/
+ spm_write(MD1_SRAM_ISOINT_B,
+ spm_read(MD1_SRAM_ISOINT_B) | (0x1 << 0));
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ MD1_PWR_CON, tmp,
+ (tmp & PWR_CLK_DIS) != PWR_CLK_DIS,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON CLK DIS fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(MD1_PWR_CON) & PWR_CLK_DIS) == PWR_CLK_DIS)
+ ;
+ #endif
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+
+ /* TINFO="Set PWR_ISO = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ISO);
+
+ /* TINFO="Set PWR_RST_B = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B);
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ /* TINFO="Set PWR_RST_B = 1" */
+ /* spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B); */
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 3));
+ /* TINFO="MD_EXTRA_PWR_CON[0]=0"*/
+ spm_write(MD_EXTRA_PWR_CON,
+ spm_read(MD_EXTRA_PWR_CON) & ~(0x1 << 0));
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Release bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP2_0_MASK);
+ /* TINFO="Release bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP1_0_MASK);
+ /* TINFO="Finish to turn on MD1" */
+
+ /* From DE, the 93MD need a delay after power-on...*/
+ udelay(250);
+ }
+ return err;
+}
+
+struct scp_domain_data {
+ const char *name;
+ mtcmos_ops mtcmos_enable_func;
+ bool active_wakeup;
+};
+
+struct scp {
+ struct scp_domain *domains;
+ struct genpd_onecell_data pd_data;
+ struct device *dev;
+};
+
+struct scp_domain {
+ struct generic_pm_domain genpd;
+ struct scp *scp;
+ const struct scp_domain_data *data;
+};
+
+struct scp_soc_data {
+ const struct scp_domain_data *domains;
+ int num_domains;
+};
+
+static const struct scp_domain_data scp_domain_data_mt2731[] = {
+ [MT2731_POWER_DOMAIN_MD] = {
+ .name = "MD",
+ .mtcmos_enable_func = spm_mtcmos_ctrl_md1,
+ .active_wakeup = true,
+ }
+};
+
+static const struct scp_soc_data mt2731_data = {
+ .domains = scp_domain_data_mt2731,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt2731),
+};
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ const struct scp_domain_data *data = scpd->data;
+ int ret;
+
+ ret = data->mtcmos_enable_func(scpd->scp->dev, STA_POWER_ON);
+
+ pr_info("mtcmos(%s) power on ret:%d.\n", data->name, ret);
+ return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ const struct scp_domain_data *data = scpd->data;
+ int ret;
+
+ ret = data->mtcmos_enable_func(scpd->scp->dev, STA_POWER_DOWN);
+
+ pr_info("mtcmos(%s) power off ret:%d\n", data->name, ret);
+ return 0;
+}
+
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ scpd = container_of(genpd, struct scp_domain, genpd);
+
+ return scpd->data->active_wakeup;
+}
+
+static struct scp *init_scp(struct platform_device *pdev,
+ const struct scp_domain_data *scp_domain_data,
+ int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i;
+ struct scp *scp;
+
+ scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+ if (!scp)
+ return ERR_PTR(-ENOMEM);
+
+ scp->dev = &pdev->dev;
+ scp->domains = devm_kcalloc(&pdev->dev,
+ num, sizeof(*scp->domains), GFP_KERNEL);
+ if (!scp->domains)
+ return ERR_PTR(-ENOMEM);
+
+ pd_data = &scp->pd_data;
+
+ pd_data->domains = devm_kcalloc(&pdev->dev,
+ num, sizeof(*pd_data->domains), GFP_KERNEL);
+ if (!pd_data->domains)
+ return ERR_PTR(-ENOMEM);
+
+ pd_data->num_domains = num;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+ const struct scp_domain_data *data = &scp_domain_data[i];
+
+ pd_data->domains[i] = genpd;
+ scpd->scp = scp;
+
+ scpd->data = data;
+
+ genpd->name = data->name;
+ genpd->power_off = scpsys_power_off;
+ genpd->power_on = scpsys_power_on;
+ genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
+ }
+ return scp;
+}
+
+static void mtk_register_power_domains(struct platform_device *pdev,
+ struct scp *scp, int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i, ret;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+
+ /*
+ * Initially turn on all domains to make the domains usable
+ * with !CONFIG_PM and to get the hardware in sync with the
+ * software. The unused domains will be switched off during
+ * late_init time.
+ */
+ genpd->power_on(genpd);
+
+ pm_genpd_init(genpd, NULL, false);
+ }
+
+ /*
+ * We are not allowed to fail here since there is no way to unregister
+ * a power domain. Once registered above we have to keep the domains
+ * valid.
+ */
+ pd_data = &scp->pd_data;
+
+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+}
+
+static int scpsys_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ const struct scp_soc_data *soc;
+ struct scp *scp;
+
+ soc = of_device_get_match_data(dev);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ spm_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(spm_base))
+ return PTR_ERR(spm_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ infra_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(infra_base))
+ return PTR_ERR(infra_base);
+
+ scp = init_scp(pdev, soc->domains, soc->num_domains);
+ if (IS_ERR(scp)) {
+ dev_err(dev, "scp init fail(%lx).\n", PTR_ERR(scp));
+ return PTR_ERR(scp);
+ }
+
+ mtk_register_power_domains(pdev, scp, soc->num_domains);
+
+ dev_dbg(dev, "probe done. %p-%p.nr %d\n",
+ spm_base, infra_base, soc->num_domains);
+ return 0;
+}
+
+static const struct of_device_id of_scpsys_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt2731-scpsys",
+ .data = &mt2731_data,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver scpsys_drv = {
+ .probe = scpsys_probe,
+ .driver = {
+ .name = "mtk-scpsys-variant",
+ .suppress_bind_attrs = true,
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(of_scpsys_match_tbl),
+ },
+};
+builtin_platform_driver(scpsys_drv);
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys.c
new file mode 100644
index 0000000..36a9b89
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys.c
@@ -0,0 +1,1083 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
+#include <linux/soc/mediatek/infracfg.h>
+
+#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/power/mt6797-power.h>
+#include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
+
+#define SPM_VDE_PWR_CON 0x0210
+#define SPM_MFG_PWR_CON 0x0214
+#define SPM_VEN_PWR_CON 0x0230
+#define SPM_ISP_PWR_CON 0x0238
+#define SPM_DIS_PWR_CON 0x023c
+#define SPM_CONN_PWR_CON 0x0280
+#define SPM_VEN2_PWR_CON 0x0298
+#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
+#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
+#define SPM_ETH_PWR_CON 0x02a0
+#define SPM_HIF_PWR_CON 0x02a4
+#define SPM_IFR_MSC_PWR_CON 0x02a8
+#define SPM_MFG_2D_PWR_CON 0x02c0
+#define SPM_MFG_ASYNC_PWR_CON 0x02c4
+#define SPM_USB_PWR_CON 0x02cc
+#define SPM_ETHSYS_PWR_CON 0x02e0 /* MT7622 */
+#define SPM_HIF0_PWR_CON 0x02e4 /* MT7622 */
+#define SPM_HIF1_PWR_CON 0x02e8 /* MT7622 */
+#define SPM_WB_PWR_CON 0x02ec /* MT7622 */
+
+
+#define SPM_PWR_STATUS 0x060c
+#define SPM_PWR_STATUS_2ND 0x0610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BIT BIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BIT BIT(4)
+
+#define PWR_STATUS_CONN BIT(1)
+#define PWR_STATUS_DISP BIT(3)
+#define PWR_STATUS_MFG BIT(4)
+#define PWR_STATUS_ISP BIT(5)
+#define PWR_STATUS_VDEC BIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
+#define PWR_STATUS_VENC_LT BIT(20)
+#define PWR_STATUS_VENC BIT(21)
+#define PWR_STATUS_MFG_2D BIT(22)
+#define PWR_STATUS_MFG_ASYNC BIT(23)
+#define PWR_STATUS_AUDIO BIT(24)
+#define PWR_STATUS_USB BIT(25)
+#define PWR_STATUS_ETHSYS BIT(24) /* MT7622 */
+#define PWR_STATUS_HIF0 BIT(25) /* MT7622 */
+#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
+#define PWR_STATUS_WB BIT(27) /* MT7622 */
+
+enum clk_id {
+ CLK_NONE,
+ CLK_MM,
+ CLK_MFG,
+ CLK_VENC,
+ CLK_VENC_LT,
+ CLK_ETHIF,
+ CLK_VDEC,
+ CLK_HIFSEL,
+ CLK_ISP,
+ CLK_AUDIO,
+ CLK_CAM,
+ CLK_VPU,
+ CLK_VPU1,
+ CLK_VPU2,
+ CLK_VPU3,
+ CLK_MAX,
+};
+
+static const char * const clk_names[] = {
+ NULL,
+ "mm",
+ "mfg",
+ "venc",
+ "venc_lt",
+ "ethif",
+ "vdec",
+ "hif_sel",
+ "isp",
+ "audio",
+ "cam",
+ "vpu",
+ "vpu1",
+ "vpu2",
+ "vpu3",
+ NULL,
+};
+
+#define MAX_CLKS 2
+
+struct scp_domain_data {
+ const char *name;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+ enum clk_id clk_id[MAX_CLKS];
+ bool active_wakeup;
+};
+
+struct scp;
+
+struct scp_domain {
+ struct generic_pm_domain genpd;
+ struct scp *scp;
+ struct clk *clk[MAX_CLKS];
+ const struct scp_domain_data *data;
+ struct regulator *supply;
+};
+
+struct scp_ctrl_reg {
+ int pwr_sta_offs;
+ int pwr_sta2nd_offs;
+};
+
+struct scp {
+ struct scp_domain *domains;
+ struct genpd_onecell_data pd_data;
+ struct device *dev;
+ void __iomem *base;
+ struct regmap *infracfg;
+ struct scp_ctrl_reg ctrl_reg;
+};
+
+struct scp_subdomain {
+ int origin;
+ int subdomain;
+};
+
+struct scp_soc_data {
+ const struct scp_domain_data *domains;
+ int num_domains;
+ const struct scp_subdomain *subdomains;
+ int num_subdomains;
+ const struct scp_ctrl_reg regs;
+};
+
+static int scpsys_domain_is_on(struct scp_domain *scpd)
+{
+ struct scp *scp = scpd->scp;
+
+ u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &
+ scpd->data->sta_mask;
+ u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &
+ scpd->data->sta_mask;
+
+ /*
+ * A domain is on when both status bits are set. If only one is set
+ * return an error. This happens while powering up a domain
+ */
+
+ if (status && status2)
+ return true;
+ if (!status && !status2)
+ return false;
+
+ return -EINVAL;
+}
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ struct scp *scp = scpd->scp;
+ unsigned long timeout;
+ bool expired;
+ void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
+ u32 sram_pdn_ack = scpd->data->sram_pdn_ack_bits;
+ u32 val;
+ int ret;
+ int i;
+
+ if (scpd->supply) {
+ ret = regulator_enable(scpd->supply);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
+ ret = clk_prepare_enable(scpd->clk[i]);
+ if (ret) {
+ for (--i; i >= 0; i--)
+ clk_disable_unprepare(scpd->clk[i]);
+
+ goto err_clk;
+ }
+ }
+
+ val = readl(ctl_addr);
+ val |= PWR_ON_BIT;
+ writel(val, ctl_addr);
+ val |= PWR_ON_2ND_BIT;
+ writel(val, ctl_addr);
+
+ /* wait until PWR_ACK = 1 */
+ timeout = jiffies + HZ;
+ expired = false;
+ while (1) {
+ ret = scpsys_domain_is_on(scpd);
+ if (ret > 0)
+ break;
+
+ if (expired) {
+ ret = -ETIMEDOUT;
+ goto err_pwr_ack;
+ }
+
+ cpu_relax();
+
+ if (time_after(jiffies, timeout))
+ expired = true;
+ }
+
+ val &= ~PWR_CLK_DIS_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ISO_BIT;
+ writel(val, ctl_addr);
+
+ val |= PWR_RST_B_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~scpd->data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* wait until SRAM_PDN_ACK all 0 */
+ timeout = jiffies + HZ;
+ expired = false;
+ while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
+
+ if (expired) {
+ ret = -ETIMEDOUT;
+ goto err_pwr_ack;
+ }
+
+ cpu_relax();
+
+ if (time_after(jiffies, timeout))
+ expired = true;
+ }
+
+ if (scpd->data->bus_prot_mask) {
+ ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask);
+ if (ret)
+ goto err_pwr_ack;
+ }
+
+ return 0;
+
+err_pwr_ack:
+ for (i = MAX_CLKS - 1; i >= 0; i--) {
+ if (scpd->clk[i])
+ clk_disable_unprepare(scpd->clk[i]);
+ }
+err_clk:
+ if (scpd->supply)
+ regulator_disable(scpd->supply);
+
+ dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
+
+ return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ struct scp *scp = scpd->scp;
+ unsigned long timeout;
+ bool expired;
+ void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
+ u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
+ u32 val;
+ int ret;
+ int i;
+
+ if (scpd->data->bus_prot_mask) {
+ ret = mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask);
+ if (ret)
+ goto out;
+ }
+
+ val = readl(ctl_addr);
+ val |= scpd->data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* wait until SRAM_PDN_ACK all 1 */
+ timeout = jiffies + HZ;
+ expired = false;
+ while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
+ if (expired) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ cpu_relax();
+
+ if (time_after(jiffies, timeout))
+ expired = true;
+ }
+
+ val |= PWR_ISO_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_RST_B_BIT;
+ writel(val, ctl_addr);
+
+ val |= PWR_CLK_DIS_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ON_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ON_2ND_BIT;
+ writel(val, ctl_addr);
+
+ /* wait until PWR_ACK = 0 */
+ timeout = jiffies + HZ;
+ expired = false;
+ while (1) {
+ ret = scpsys_domain_is_on(scpd);
+ if (ret == 0)
+ break;
+
+ if (expired) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ cpu_relax();
+
+ if (time_after(jiffies, timeout))
+ expired = true;
+ }
+
+ for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
+ clk_disable_unprepare(scpd->clk[i]);
+
+ if (scpd->supply)
+ regulator_disable(scpd->supply);
+
+ return 0;
+
+out:
+ dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
+
+ return ret;
+}
+
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ scpd = container_of(genpd, struct scp_domain, genpd);
+
+ return scpd->data->active_wakeup;
+}
+
+static void init_clks(struct platform_device *pdev, struct clk **clk)
+{
+ int i;
+
+ for (i = CLK_NONE + 1; i < CLK_MAX; i++)
+ clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
+}
+
+static struct scp *init_scp(struct platform_device *pdev,
+ const struct scp_domain_data *scp_domain_data, int num,
+ const struct scp_ctrl_reg *scp_ctrl_reg)
+{
+ struct genpd_onecell_data *pd_data;
+ struct resource *res;
+ int i, j;
+ struct scp *scp;
+ struct clk *clk[CLK_MAX];
+
+ scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+ if (!scp)
+ return ERR_PTR(-ENOMEM);
+
+ scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
+ scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
+
+ scp->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ scp->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(scp->base))
+ return ERR_CAST(scp->base);
+
+ scp->domains = devm_kzalloc(&pdev->dev,
+ sizeof(*scp->domains) * num, GFP_KERNEL);
+ if (!scp->domains)
+ return ERR_PTR(-ENOMEM);
+
+ pd_data = &scp->pd_data;
+
+ pd_data->domains = devm_kzalloc(&pdev->dev,
+ sizeof(*pd_data->domains) * num, GFP_KERNEL);
+ if (!pd_data->domains)
+ return ERR_PTR(-ENOMEM);
+
+ scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "infracfg");
+ if (IS_ERR(scp->infracfg)) {
+ dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
+ PTR_ERR(scp->infracfg));
+ return ERR_CAST(scp->infracfg);
+ }
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ const struct scp_domain_data *data = &scp_domain_data[i];
+
+ scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
+ if (IS_ERR(scpd->supply)) {
+ if (PTR_ERR(scpd->supply) == -ENODEV)
+ scpd->supply = NULL;
+ else
+ return ERR_CAST(scpd->supply);
+ }
+ }
+
+ pd_data->num_domains = num;
+
+ init_clks(pdev, clk);
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+ const struct scp_domain_data *data = &scp_domain_data[i];
+
+ pd_data->domains[i] = genpd;
+ scpd->scp = scp;
+
+ scpd->data = data;
+
+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
+ struct clk *c = clk[data->clk_id[j]];
+
+ if (IS_ERR(c)) {
+ dev_err(&pdev->dev, "%s: clk unavailable\n",
+ data->name);
+ return ERR_CAST(c);
+ }
+
+ scpd->clk[j] = c;
+ }
+
+ genpd->name = data->name;
+ genpd->power_off = scpsys_power_off;
+ genpd->power_on = scpsys_power_on;
+ genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
+ }
+
+ return scp;
+}
+
+static void mtk_register_power_domains(struct platform_device *pdev,
+ struct scp *scp, int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i, ret;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+
+ /*
+ * Initially turn on all domains to make the domains usable
+ * with !CONFIG_PM and to get the hardware in sync with the
+ * software. The unused domains will be switched off during
+ * late_init time.
+ */
+ genpd->power_on(genpd);
+
+ pm_genpd_init(genpd, NULL, false);
+ }
+
+ /*
+ * We are not allowed to fail here since there is no way to unregister
+ * a power domain. Once registered above we have to keep the domains
+ * valid.
+ */
+
+ pd_data = &scp->pd_data;
+
+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+}
+
+/*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+ [MT2701_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = 0x0104,
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .clk_id = {CLK_MM},
+ .bus_prot_mask = 0x0002,
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MFG},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_BDP] = {
+ .name = "bdp",
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_ETH] = {
+ .name = "eth",
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_ETHIF},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_HIF] = {
+ .name = "hif",
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_ETHIF},
+ .active_wakeup = true,
+ },
+ [MT2701_POWER_DOMAIN_IFR_MSC] = {
+ .name = "ifr_msc",
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+};
+
+/*
+ * MT6797 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt6797[] = {
+ [MT6797_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_VDEC},
+ },
+ [MT6797_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = BIT(21),
+ .ctl_offs = 0x304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT6797_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT6797_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x30C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .bus_prot_mask = (BIT(1) | BIT(2)),
+ },
+ [MT6797_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = BIT(24),
+ .ctl_offs = 0x314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = BIT(13),
+ .ctl_offs = 0x334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT6797_POWER_DOMAIN_MJC] = {
+ .name = "mjc",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+};
+
+#define SPM_PWR_STATUS_MT6797 0x0180
+#define SPM_PWR_STATUS_2ND_MT6797 0x0184
+
+static const struct scp_subdomain scp_subdomain_mt6797[] = {
+ {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VDEC},
+ {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_ISP},
+ {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VENC},
+ {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_MJC},
+};
+
+/*
+ * MT7622 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt7622[] = {
+ [MT7622_POWER_DOMAIN_ETHSYS] = {
+ .name = "ethsys",
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
+ .active_wakeup = true,
+ },
+ [MT7622_POWER_DOMAIN_HIF0] = {
+ .name = "hif0",
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_HIFSEL},
+ .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
+ .active_wakeup = true,
+ },
+ [MT7622_POWER_DOMAIN_HIF1] = {
+ .name = "hif1",
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_HIFSEL},
+ .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
+ .active_wakeup = true,
+ },
+ [MT7622_POWER_DOMAIN_WB] = {
+ .name = "wb",
+ .sta_mask = PWR_STATUS_WB,
+ .ctl_offs = SPM_WB_PWR_CON,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_NONE},
+ .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
+ .active_wakeup = true,
+ },
+};
+
+/*
+ * MT8173 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8173[] = {
+ [MT8173_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT8173_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = SPM_VEN_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_MM, CLK_VENC},
+ },
+ [MT8173_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT8173_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1,
+ },
+ [MT8173_POWER_DOMAIN_VENC_LT] = {
+ .name = "venc_lt",
+ .sta_mask = PWR_STATUS_VENC_LT,
+ .ctl_offs = SPM_VEN2_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_MM, CLK_VENC_LT},
+ },
+ [MT8173_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = SPM_AUDIO_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8173_POWER_DOMAIN_USB] = {
+ .name = "usb",
+ .sta_mask = PWR_STATUS_USB,
+ .ctl_offs = SPM_USB_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT8173_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8173_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(13, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 16),
+ .clk_id = {CLK_NONE},
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8173[] = {
+ {MT8173_POWER_DOMAIN_MFG_ASYNC, MT8173_POWER_DOMAIN_MFG_2D},
+ {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
+};
+
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_AUDIO},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_CAM},
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_ISP},
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_VPU, CLK_VPU1},
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_VPU2},
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_VPU3},
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
+static const struct scp_soc_data mt2701_data = {
+ .domains = scp_domain_data_mt2701,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ }
+};
+
+static const struct scp_soc_data mt6797_data = {
+ .domains = scp_domain_data_mt6797,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
+ .subdomains = scp_subdomain_mt6797,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
+ }
+};
+
+static const struct scp_soc_data mt7622_data = {
+ .domains = scp_domain_data_mt7622,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ }
+};
+
+static const struct scp_soc_data mt8173_data = {
+ .domains = scp_domain_data_mt8173,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8173),
+ .subdomains = scp_subdomain_mt8173,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ }
+};
+
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184
+ }
+};
+
+/*
+ * scpsys driver init
+ */
+
+static const struct of_device_id of_scpsys_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt2701-scpsys",
+ .data = &mt2701_data,
+ }, {
+ .compatible = "mediatek,mt6797-scpsys",
+ .data = &mt6797_data,
+ }, {
+ .compatible = "mediatek,mt7622-scpsys",
+ .data = &mt7622_data,
+ }, {
+ .compatible = "mediatek,mt8173-scpsys",
+ .data = &mt8173_data,
+ }, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int scpsys_probe(struct platform_device *pdev)
+{
+ const struct scp_subdomain *sd;
+ const struct scp_soc_data *soc;
+ struct scp *scp;
+ struct genpd_onecell_data *pd_data;
+ int i, ret;
+
+ soc = of_device_get_match_data(&pdev->dev);
+
+ scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
+ if (IS_ERR(scp))
+ return PTR_ERR(scp);
+
+ mtk_register_power_domains(pdev, scp, soc->num_domains);
+
+ pd_data = &scp->pd_data;
+
+ for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
+ ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
+ pd_data->domains[sd->subdomain]);
+ if (ret && IS_ENABLED(CONFIG_PM))
+ dev_err(&pdev->dev, "Failed to add subdomain: %d\n",
+ ret);
+ }
+
+ return 0;
+}
+
+static struct platform_driver scpsys_drv = {
+ .probe = scpsys_probe,
+ .driver = {
+ .name = "mtk-scpsys",
+ .suppress_bind_attrs = true,
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(of_scpsys_match_tbl),
+ },
+};
+builtin_platform_driver(scpsys_drv);