[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c
new file mode 100644
index 0000000..1dc05a4
--- /dev/null
+++ b/src/kernel/linux/v4.14/drivers/soc/mediatek/mtk-scpsys-variant.c
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ *
+ * Based on drivers/soc/mediatek/mtk-scpsys.c
+ *
+ * All the mtcmos enable/disable code is from DE. More closer to DE.
+ */
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+
+#include <dt-bindings/power/mt2731-power.h>
+
+static void __iomem *spm_base; /* spm */
+static void __iomem *infra_base; /* infra_ao */
+
+#define SPM_BASE spm_base
+#define INFRACFG_BASE infra_base
+
+#define spm_read(addr) readl(addr)
+#define spm_write(addr, val) writel((val), (addr))
+
+typedef int (*mtcmos_ops)(struct device *dev, int state);
+
+/* SPM Register. should be auto-gened. */
+#define POWERON_CONFIG_EN (SPM_BASE + 0x0000)
+#define PWR_STATUS (SPM_BASE + 0x0160)
+#define PWR_STATUS_2ND (SPM_BASE + 0x0164)
+#define MD1_PWR_CON (SPM_BASE + 0x0318)
+#define MD1_SRAM_ISOINT_B (SPM_BASE + 0x0320)
+#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x03B0)
+#define MD_EXTRA_PWR_CON (SPM_BASE + 0x03F0)
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+
+/* INFRASYS Register */
+#define INFRA_TOPAXI_PROTECTEN (INFRACFG_BASE + 0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA1 (INFRACFG_BASE + 0x0228)
+#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_BASE + 0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_BASE + 0x0258)
+#define INFRA_TOPAXI_PROTECTEN_SET (INFRACFG_BASE + 0x02A0)
+#define INFRA_TOPAXI_PROTECTEN_CLR (INFRACFG_BASE + 0x02A4)
+#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_BASE + 0x02A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_BASE + 0x02AC)
+#define VDNR_CON (INFRACFG_BASE + 0x71C)
+
+#define STA_POWER_DOWN 0
+#define STA_POWER_ON 1
+
+#define SRAM_ISOINT_B (1U << 6)
+#define SRAM_CKISO (1U << 5)
+#define PWR_CLK_DIS (1U << 4)
+#define PWR_ON_2ND (1U << 3)
+#define PWR_ON (1U << 2)
+#define PWR_ISO (1U << 1)
+#define PWR_RST_B (1U << 0)
+
+/* Kernel readl_poll wait-ack support timeout. */
+#define READL_POLL_SUPPORT 1
+
+/**************************************
+ * for NON-CPU MTCMOS
+ **************************************/
+/* Define MTCMOS Power Status Mask */
+#define MD1_PWR_STA_MASK (0x1 << 0)
+
+/* Define MTCMOS Bus Protect Mask */
+#define MD1_PROT_STEP1_0_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP1_0_ACK_MASK ((0x1 << 6) \
+ |(0x1 << 7))
+#define MD1_PROT_STEP2_0_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+#define MD1_PROT_STEP2_0_ACK_MASK ((0x1 << 3) \
+ |(0x1 << 4))
+static int spm_mtcmos_ctrl_md1(struct device *dev, int state)
+{
+ int err = 0, tmp, ret;
+
+ /* TINFO="enable SPM register control" */
+ spm_write(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | (0x1 << 0));
+
+ if (state == STA_POWER_DOWN) {
+ /* TINFO="Start to turn off MD1" */
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Set bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP1_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ INFRA_TOPAXI_PROTECTEN_STA1, tmp,
+ (tmp & MD1_PROT_STEP1_0_ACK_MASK) ==
+ MD1_PROT_STEP1_0_ACK_MASK /* out */,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "MD1 step1_0 ack fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) &
+ MD1_PROT_STEP1_0_ACK_MASK) !=
+ MD1_PROT_STEP1_0_ACK_MASK) {
+ }
+ #endif
+#endif
+ /* TINFO="Set bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_SET, MD1_PROT_STEP2_0_MASK);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ INFRA_TOPAXI_PROTECTEN_STA1, tmp,
+ (tmp & MD1_PROT_STEP2_0_ACK_MASK) ==
+ MD1_PROT_STEP2_0_ACK_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "MD1 step2_0 ack fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(INFRA_TOPAXI_PROTECTEN_STA1) &
+ MD1_PROT_STEP2_0_ACK_MASK) !=
+ MD1_PROT_STEP2_0_ACK_MASK) {
+ }
+ #endif
+#endif
+ /* TINFO="MD_EXTRA_PWR_CON[0]=1"*/
+ spm_write(MD_EXTRA_PWR_CON,
+ spm_read(MD_EXTRA_PWR_CON) | (0x1 << 0));
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+ /* TINFO="Set PWR_ISO = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ISO);
+ /* TINFO="MD_SRAM_ISO_CON[0]=0"*/
+ spm_write(MD1_SRAM_ISOINT_B,
+ spm_read(MD1_SRAM_ISOINT_B) & ~(0x1 << 0));
+ /* TINFO="Set SRAM_PDN = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | (0x1 << 8));
+#ifndef IGNORE_MTCMOS_CHECK
+#endif
+ /* TINFO="Set PWR_ON = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS, tmp,
+ !(tmp & MD1_PWR_STA_MASK),
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWR STATUS MASK fail\n");
+ return ret;
+ }
+ #else
+ /* TINFO="Wait until MD1_PWR_STA_MASK = 0" */
+ while (spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) {
+ /* No logic between pwr_on and pwr_ack.
+ * Print SRAM / MTCMOS control and PWR_ACK for debug.
+ */
+ }
+ #endif
+#endif
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=1"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) | (0x1 << 3));
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Finish to turn off MD1" */
+ } else { /* STA_POWER_ON */
+ /* TINFO="Start to turn on MD1" */
+ /* TINFO="Set PWR_RST_B = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_RST_B);
+ /* TINFO="Set PWR_ON = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON);
+ /* TINFO="Set PWR_ON_2ND = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_ON_2ND);
+#ifndef IGNORE_MTCMOS_CHECK
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS, tmp,
+ (tmp & MD1_PWR_STA_MASK) == MD1_PWR_STA_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON STS1 ON MASK fail\n");
+ return ret;
+ }
+ ret = readl_poll_timeout_atomic(
+ PWR_STATUS_2ND, tmp,
+ (tmp & MD1_PWR_STA_MASK) == MD1_PWR_STA_MASK,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON STS2 ON MASK fail\n");
+ return ret;
+ }
+ #else
+ /* TINFO="Wait until PWR_STATUS = 1 and PWR_STATUS_2ND = 1" */
+ while (((spm_read(PWR_STATUS) & MD1_PWR_STA_MASK) !=
+ MD1_PWR_STA_MASK) ||
+ ((spm_read(PWR_STATUS_2ND) & MD1_PWR_STA_MASK) !=
+ MD1_PWR_STA_MASK)) {
+ /* No logic between pwr_on and pwr_ack.
+ * Print SRAM / MTCMOS control and PWR_ACK for
+ * debug.
+ */
+ }
+ #endif
+#endif
+ /* TINFO="Set SRAM_PDN = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~(0x1 << 8));
+ /* TINFO="MD_SRAM_ISO_CON[0]=1"*/
+ spm_write(MD1_SRAM_ISOINT_B,
+ spm_read(MD1_SRAM_ISOINT_B) | (0x1 << 0));
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ #if READL_POLL_SUPPORT
+ ret = readl_poll_timeout_atomic(
+ MD1_PWR_CON, tmp,
+ (tmp & PWR_CLK_DIS) != PWR_CLK_DIS,
+ 10, 100000);
+ if (ret) {
+ dev_warn(dev, "PWRON CLK DIS fail\n");
+ return ret;
+ }
+ #else
+ while ((spm_read(MD1_PWR_CON) & PWR_CLK_DIS) == PWR_CLK_DIS)
+ ;
+ #endif
+ /* TINFO="Set PWR_CLK_DIS = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_CLK_DIS);
+
+ /* TINFO="Set PWR_ISO = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_ISO);
+
+ /* TINFO="Set PWR_RST_B = 1" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B);
+
+ /* TINFO="Set PWR_CLK_DIS = 0" */
+ spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) & ~PWR_CLK_DIS);
+ /* TINFO="Set PWR_RST_B = 1" */
+ /* spm_write(MD1_PWR_CON, spm_read(MD1_PWR_CON) | PWR_RST_B); */
+ /* TINFO="MD_EXT_BUCK_ISO_CON[0]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 0));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[1]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 1));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[2]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 2));
+ /* TINFO="MD_EXT_BUCK_ISO_CON[3]=0"*/
+ spm_write(MD_EXT_BUCK_ISO_CON,
+ spm_read(MD_EXT_BUCK_ISO_CON) & ~(0x1 << 3));
+ /* TINFO="MD_EXTRA_PWR_CON[0]=0"*/
+ spm_write(MD_EXTRA_PWR_CON,
+ spm_read(MD_EXTRA_PWR_CON) & ~(0x1 << 0));
+ /* TINFO="Switch to original protect control path" */
+ spm_write(VDNR_CON, spm_read(VDNR_CON) | 0x7F);
+ /* TINFO="Release bus protect - step2 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP2_0_MASK);
+ /* TINFO="Release bus protect - step1 : 0" */
+ spm_write(INFRA_TOPAXI_PROTECTEN_CLR, MD1_PROT_STEP1_0_MASK);
+ /* TINFO="Finish to turn on MD1" */
+
+ /* From DE, the 93MD need a delay after power-on...*/
+ udelay(250);
+ }
+ return err;
+}
+
+struct scp_domain_data {
+ const char *name;
+ mtcmos_ops mtcmos_enable_func;
+ bool active_wakeup;
+};
+
+struct scp {
+ struct scp_domain *domains;
+ struct genpd_onecell_data pd_data;
+ struct device *dev;
+};
+
+struct scp_domain {
+ struct generic_pm_domain genpd;
+ struct scp *scp;
+ const struct scp_domain_data *data;
+};
+
+struct scp_soc_data {
+ const struct scp_domain_data *domains;
+ int num_domains;
+};
+
+static const struct scp_domain_data scp_domain_data_mt2731[] = {
+ [MT2731_POWER_DOMAIN_MD] = {
+ .name = "MD",
+ .mtcmos_enable_func = spm_mtcmos_ctrl_md1,
+ .active_wakeup = true,
+ }
+};
+
+static const struct scp_soc_data mt2731_data = {
+ .domains = scp_domain_data_mt2731,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt2731),
+};
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ const struct scp_domain_data *data = scpd->data;
+ int ret;
+
+ ret = data->mtcmos_enable_func(scpd->scp->dev, STA_POWER_ON);
+
+ pr_info("mtcmos(%s) power on ret:%d.\n", data->name, ret);
+ return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
+ const struct scp_domain_data *data = scpd->data;
+ int ret;
+
+ ret = data->mtcmos_enable_func(scpd->scp->dev, STA_POWER_DOWN);
+
+ pr_info("mtcmos(%s) power off ret:%d\n", data->name, ret);
+ return 0;
+}
+
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ scpd = container_of(genpd, struct scp_domain, genpd);
+
+ return scpd->data->active_wakeup;
+}
+
+static struct scp *init_scp(struct platform_device *pdev,
+ const struct scp_domain_data *scp_domain_data,
+ int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i;
+ struct scp *scp;
+
+ scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+ if (!scp)
+ return ERR_PTR(-ENOMEM);
+
+ scp->dev = &pdev->dev;
+ scp->domains = devm_kcalloc(&pdev->dev,
+ num, sizeof(*scp->domains), GFP_KERNEL);
+ if (!scp->domains)
+ return ERR_PTR(-ENOMEM);
+
+ pd_data = &scp->pd_data;
+
+ pd_data->domains = devm_kcalloc(&pdev->dev,
+ num, sizeof(*pd_data->domains), GFP_KERNEL);
+ if (!pd_data->domains)
+ return ERR_PTR(-ENOMEM);
+
+ pd_data->num_domains = num;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+ const struct scp_domain_data *data = &scp_domain_data[i];
+
+ pd_data->domains[i] = genpd;
+ scpd->scp = scp;
+
+ scpd->data = data;
+
+ genpd->name = data->name;
+ genpd->power_off = scpsys_power_off;
+ genpd->power_on = scpsys_power_on;
+ genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
+ }
+ return scp;
+}
+
+static void mtk_register_power_domains(struct platform_device *pdev,
+ struct scp *scp, int num)
+{
+ struct genpd_onecell_data *pd_data;
+ int i, ret;
+
+ for (i = 0; i < num; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *genpd = &scpd->genpd;
+
+ /*
+ * Initially turn on all domains to make the domains usable
+ * with !CONFIG_PM and to get the hardware in sync with the
+ * software. The unused domains will be switched off during
+ * late_init time.
+ */
+ genpd->power_on(genpd);
+
+ pm_genpd_init(genpd, NULL, false);
+ }
+
+ /*
+ * We are not allowed to fail here since there is no way to unregister
+ * a power domain. Once registered above we have to keep the domains
+ * valid.
+ */
+ pd_data = &scp->pd_data;
+
+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
+}
+
+static int scpsys_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ const struct scp_soc_data *soc;
+ struct scp *scp;
+
+ soc = of_device_get_match_data(dev);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ spm_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(spm_base))
+ return PTR_ERR(spm_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ infra_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(infra_base))
+ return PTR_ERR(infra_base);
+
+ scp = init_scp(pdev, soc->domains, soc->num_domains);
+ if (IS_ERR(scp)) {
+ dev_err(dev, "scp init fail(%lx).\n", PTR_ERR(scp));
+ return PTR_ERR(scp);
+ }
+
+ mtk_register_power_domains(pdev, scp, soc->num_domains);
+
+ dev_dbg(dev, "probe done. %p-%p.nr %d\n",
+ spm_base, infra_base, soc->num_domains);
+ return 0;
+}
+
+static const struct of_device_id of_scpsys_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt2731-scpsys",
+ .data = &mt2731_data,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver scpsys_drv = {
+ .probe = scpsys_probe,
+ .driver = {
+ .name = "mtk-scpsys-variant",
+ .suppress_bind_attrs = true,
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(of_scpsys_match_tbl),
+ },
+};
+builtin_platform_driver(scpsys_drv);