[Feature]add MT2731_MP2_MR2_SVN388 baseline version
Change-Id: Ief04314834b31e27effab435d3ca8ba33b499059
diff --git a/src/kernel/linux/v4.14/include/dt-bindings/mfd/mt6389-irq.h b/src/kernel/linux/v4.14/include/dt-bindings/mfd/mt6389-irq.h
new file mode 100644
index 0000000..9d25926
--- /dev/null
+++ b/src/kernel/linux/v4.14/include/dt-bindings/mfd/mt6389-irq.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MT6389_IRQ_H
+#define _DT_BINDINGS_MT6389_IRQ_H
+
+#define SP_BUCK 0
+#define SP_LDO 1
+#define SP_PSC 2
+#define SP_SCK 3
+#define SP_HK 4
+#define SP_AUD 5
+#define SP_MISC 6
+
+// BUCK
+#define INT_VPROC_OC 0
+#define INT_VCORE_OC 1
+#define INT_VSRAM_OTHERS_OC 2
+#define INT_VMODEM_OC 3
+#define INT_VDRAM1_OC 4
+#define INT_VS1_OC 5
+#define INT_VS2_OC 6
+#define INT_VPA_OC 7
+// LDO
+#define INT_VFE28_OC 16
+#define INT_VRF18_OC 17
+#define INT_VRF12_OC 18
+#define INT_VGP3_OC 19
+#define INT_VCN33_OC 20
+#define INT_VCN18_OC 21
+#define INT_VA12_OC 22
+#define INT_VA09_OC 23
+#define INT_VAUX18_OC 24
+#define INT_VAUD28_OC 25
+#define INT_VIO18_OC 26
+#define INT_VIO33_OC 27
+#define INT_VGP1_OC 28
+#define INT_VGP2_OC 29
+#define INT_VSRAM_PROC_OC 30
+#define INT_VDRAM2_OC 31
+#define INT_VMCH_OC 32
+#define INT_VEMC_OC 33
+#define INT_VSIM1_OC 34
+#define INT_VSIM2_OC 35
+#define INT_VUSB_OC 36
+#define INT_VXO22_OC 37
+#define INT_VRFCK_OC 38
+#define INT_VBBCK_OC 39
+// PSC
+#define INT_ENB_R 48
+#define INT_PMIC_RESET_B_H2L 49
+#define INT_NI_LBAT_INT 50
+#define INT_CHRDET 51
+#define INT_CHRDET_EDGE 52
+// SCK
+#define INT_RTC 64
+// HK
+#define INT_THR_H 86
+#define INT_THR_L 87
+#define INT_INTER1_DET_DIV_H 96
+#define INT_INTER1_DET_DIV_L 97
+#define INT_INTER2_DET_DIV_H 98
+#define INT_INTER2_DET_DIV_L 99
+#define INT_INTER3_DET_DIV_H 100
+#define INT_INTER3_DET_DIV_L 101
+#define INT_INTER4_DET_DIV_H 102
+#define INT_INTER4_DET_DIV_L 103
+#define INT_INTER5_DET_DIV_H 104
+#define INT_INTER5_DET_DIV_L 105
+#define INT_INTER6_DET_DIV_H 106
+#define INT_INTER6_DET_DIV_L 107
+#define INT_INTER7_DET_DIV_H 108
+#define INT_INTER7_DET_DIV_L 109
+#define INT_INTER8_DET_DIV_H 110
+#define INT_INTER8_DET_DIV_L 111
+#define INT_INTER9_DET_DIV_H 112
+#define INT_INTER9_DET_DIV_L 113
+#define INT_INTER10_DET_DIV_H 114
+#define INT_INTER10_DET_DIV_L 115
+#define INT_INTER11_DET_DIV_H 116
+#define INT_INTER11_DET_DIV_L 117
+#define INT_INTER12_DET_DIV_H 118
+#define INT_INTER12_DET_DIV_L 119
+#define INT_INTER13_DET_DIV_H 120
+#define INT_INTER13_DET_DIV_L 121
+#define INT_INTER14_DET_DIV_H 122
+#define INT_INTER14_DET_DIV_L 123
+#define INT_INTER1_DET_H 124
+#define INT_INTER1_DET_L 125
+#define INT_INTER2_DET_H 128
+#define INT_INTER2_DET_L 129
+#define INT_INTER3_DET_H 130
+#define INT_INTER3_DET_L 131
+#define INT_INTER4_DET_H 132
+#define INT_INTER4_DET_L 133
+#define INT_INTER5_DET_H 134
+#define INT_INTER5_DET_L 135
+#define INT_INTER6_DET_H 136
+#define INT_INTER6_DET_L 137
+#define INT_INTER7_DET_H 138
+#define INT_INTER7_DET_L 139
+#define INT_INTER8_DET_H 140
+#define INT_INTER8_DET_L 141
+#define INT_INTER9_DET_H 142
+#define INT_INTER9_DET_L 143
+// AUDIO
+#define INT_AUDIO 144
+// MISC
+#define INT_SPI_CMD_ALERT 160
+
+#endif /* _DT_BINDINGS_MT6389_IRQ_H */