src/bsp/lk/platform/mt2635/platform.c

/*
 * Copyright (c) 2016 MediaTek Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files
 * (the "Software"), to deal in the Software without restriction,
 * including without limitation the rights to use, copy, modify, merge,
 * publish, distribute, sublicense, and/or sell copies of the Software,
 * and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

#include <arch.h>
#include <arch/arm64/mmu.h>
#include <arch/ops.h>
#include <assert.h>
#include <debug.h>
#include <dev/interrupt/arm_gic.h>
#include <dev/timer/arm_generic.h>
#include <dev/uart.h>
#include <err.h>
#include <kernel/vm.h>
#include <platform.h>
#include <platform/emi.h>
#include <platform/memory.h>
#include <platform/mmc_core.h>
#include <platform/mt2635.h>
#include <platform/mtk_timer.h>
#include <platform/mtk_wdt.h>
#include <platform/pll.h>
#include <platform/pmic.h>
#include <lib/bio.h>
#include <lib/mempool.h>

#if WITH_KERNEL_VM
#define L2C_MAPPING_IDX 0
#define PERIPHERAL_MAPPING_IDX 1
#define SRAM_MAPPING_IDX 2
#define DRAM_MAPPING_IDX 3

/* initial memory mappings. parsed by start.S */
struct mmu_initial_mapping mmu_initial_mappings[] = {
    {
        .phys = MEMORY_BASE_PHYS,
        .virt = MEMORY_BASE_VIRT,
        .size = MEMORY_APERTURE_SIZE,
        .flags = 0,
        .name = "l2c"
    },
    {
        .phys = PERIPHERAL_BASE_PHYS,
        .virt = PERIPHERAL_BASE_VIRT,
        .size = PERIPHERAL_BASE_SIZE,
        .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
        .name = "peripherals"
    },
    /* reserved for internal sram */
    { 0 },
    /* reserved for dram */
    { 0 },
    /* null entry to terminate the list */
    { 0 }
};

static pmm_arena_t arena = {
    .name = "sdram",
    .base = SRAM_BASE_PHYS,
    .size = SRAM_BASE_SIZE,
    .flags = PMM_ARENA_FLAG_KMAP,
};

/* only enable el1 dcache */
static void dcache_enable(void)
{
    uint32_t sctlr;

    asm volatile("mrs %0, sctlr_el1" : "=r" (sctlr) : : "cc");
    asm volatile("msr sctlr_el1, %0" : : "r" (sctlr | (1 << 2)) : "cc");
    asm volatile("isb");
}

#endif /* WITH_KERNEL_VM */

void platform_early_init(void)
{
    uart_init_early();

    /* initialize the interrupt controller */
    arm_gic_init();

    /* initialize the timer block */
    mtk_timer_init();

    mtk_wdt_init();
    arm_generic_timer_init(ARM_GENERIC_TIMER_PHYSICAL_INT, 13000000);

#if WITH_KERNEL_VM
    arch_disable_cache(DCACHE);
#endif
    mt_pll_init();

    mt_pmic_init();

    /*
      * mt_init_mempll() and mt_pll_post_init() should be invoked
      * after pmic_ini
      */
    mt_init_mempll();
    mt_pll_post_init();
    /* dram calibration, mapping and test */
    mt_mem_init();

#if WITH_KERNEL_VM
    dcache_enable();

    /* add DRAM to mmu_initial_mappings for physical-to-virtual translation */
    mmu_initial_mappings[DRAM_MAPPING_IDX].phys = DRAM_BASE_PHY;
    mmu_initial_mappings[DRAM_MAPPING_IDX].virt = DRAM_BASE_VIRT;
    mmu_initial_mappings[DRAM_MAPPING_IDX].size = get_dram_size();
    mmu_initial_mappings[DRAM_MAPPING_IDX].flags = 0;
    mmu_initial_mappings[DRAM_MAPPING_IDX].name = "dram";

    /* mapping internel sram to cacheable memory */
    arch_mmu_map(SRAM_BASE_VIRT, SRAM_BASE_PHYS,  SRAM_BASE_SIZE >> PAGE_SIZE_SHIFT, 0);
    /* add intrenal sram to mmu_initial_mappings for heap */
    mmu_initial_mappings[SRAM_MAPPING_IDX].phys = SRAM_BASE_PHYS;
    mmu_initial_mappings[SRAM_MAPPING_IDX].virt = SRAM_BASE_VIRT;
    mmu_initial_mappings[SRAM_MAPPING_IDX].size = SRAM_BASE_SIZE;
    mmu_initial_mappings[SRAM_MAPPING_IDX].flags = 0;
    mmu_initial_mappings[SRAM_MAPPING_IDX].name = "sram";

    pmm_add_arena(&arena);
#endif
}

void platform_init(void)
{
    int ret;
    bdev_t *rpdev;
    unsigned int *rpmb_size;

    ret = mempool_init((void *)CACHED_MEMPOOL_ADDR, CACHED_MEMPOOL_SIZE,
                       MEMPOOL_CACHE);
    if (ret != NO_ERROR)
        platform_halt(HALT_ACTION_REBOOT, HALT_REASON_SW_PANIC);

    emmc_init();

    rpdev = bio_open("mmc0rpmb");
    if (rpdev != NULL) {
        rpmb_size = (unsigned int *)(readl(SRAMROM_BASE + 0x3c) + 0x8fc + KERNEL_ASPACE_BASE);
        *rpmb_size = rpdev->total_size;
        bio_close(rpdev);
    }
}