src/bsp/trustzone/teeloader/mt6771/include/tz_dapc.h

/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
 * the prior written permission of MediaTek inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of MediaTek Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * MediaTek Inc. (C) 2017. All rights reserved.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
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 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
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 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
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 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
 * any receiver's applicable license agreements with MediaTek Inc.
 */

#ifndef DEVICE_APC_H
#define DEVICE_APC_H

#include "typedefs.h"

#define DEVAPC_AO_INFRA_BASE        0x1000E000  // for INFRA/PERI
#define DEVAPC_AO_MD_BASE           0x10019000  // for MD
#define DEVAPC_AO_MM_BASE           0x1001C000  // for MM

/*******************************************************************************
 * REGISTER ADDRESS DEFINATION
 ******************************************************************************/
/* Device APC AO for INFRA/PERI */

#define DEVAPC_AO_INFRA_MAS_DOM_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A00))
#define DEVAPC_AO_INFRA_MAS_DOM_1   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A04))
#define DEVAPC_AO_INFRA_MAS_DOM_2   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A08))
#define DEVAPC_AO_INFRA_MAS_DOM_3   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0A0C))

#define DEVAPC_AO_INFRA_MAS_SEC_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0B00))

#define DEVAPC_AO_INFRA_DOM_RMP_0   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0D00))
#define DEVAPC_AO_INFRA_DOM_RMP_1   ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0D04))

#define DEVAPC_AO_INFRA_APC_CON     ((volatile unsigned int*)(DEVAPC_AO_INFRA_BASE+0x0F00))

/* ---------------------------------------------------------------------------------------- */
/* Device APC AO for MD */

#define DEVAPC_AO_MD_DOM_RMP_0      ((volatile unsigned int*)(DEVAPC_AO_MD_BASE+0x0D00))

#define DEVAPC_AO_MD_APC_CON        ((volatile unsigned int*)(DEVAPC_AO_MD_BASE+0x0F00))

/* ---------------------------------------------------------------------------------------- */
/* Device APC AO for MM */

#define DEVAPC_AO_MM_DOM_RMP_0      ((volatile unsigned int*)(DEVAPC_AO_MM_BASE+0x0D00))

#define DEVAPC_AO_MM_APC_CON        ((volatile unsigned int*)(DEVAPC_AO_MM_BASE+0x0F00))

/* ---------------------------------------------------------------------------------------- */

#define MOD_NO_IN_1_DEVAPC          16
#define MASTER_NUM_INFRA            30

typedef enum {
    NON_SECURE_TRAN = 0,
    SECURE_TRAN
} E_TRANSACTION;

typedef enum {
    MASTER_TYPE_INFRA = 0,
} E_MASTER_TYPE;

typedef enum {
    DOMAIN_0 = 0,
    DOMAIN_1,
    DOMAIN_2,
    DOMAIN_3,
    DOMAIN_4,
    DOMAIN_5,
    DOMAIN_6,
    DOMAIN_7,
    DOMAIN_8,
    DOMAIN_9,
    DOMAIN_10,
    DOMAIN_11,
    DOMAIN_12,
    DOMAIN_13,
    DOMAIN_14,
    DOMAIN_15,
    DOMAIN_MAX,
} E_DOMAIN;

/* Masks for Domain Control for DEVAPC */
#define CONN2AP        (0xF << 24)



static inline unsigned int uffs(unsigned int x)
{
    unsigned int r = 1;

    if (!x)
        return 0;
    if (!(x & 0xffff)) {
        x >>= 16;
        r += 16;
    }
    if (!(x & 0xff)) {
        x >>= 8;
        r += 8;
    }
    if (!(x & 0xf)) {
        x >>= 4;
        r += 4;
    }
    if (!(x & 3)) {
        x >>= 2;
        r += 2;
    }
    if (!(x & 1)) {
        x >>= 1;
        r += 1;
    }
    return r;
}

#define reg_read32(reg)        (*(volatile u32* const)(reg))
#define reg_write32(reg,val)   ((*(volatile u32* const)(reg)) = (val))

#define reg_set_bits(reg,bs)   ((*(volatile u32*)(reg)) |= (u32)(bs))
#define reg_clr_bits(reg,bs)   ((*(volatile u32*)(reg)) &= ~((u32)(bs)))

#define reg_set_field(reg,field,val) \
    do {    \
        volatile unsigned int tv = reg_read32(reg); \
        tv &= ~(field); \
        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
        reg_write32(reg,tv); \
    } while(0)

#define reg_get_field(reg,field,val) \
    do {    \
        volatile unsigned int tv = reg_read32(reg); \
        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
    } while(0)


void tz_dapc_sec_init(void);
void tz_dapc_sec_postinit(void);
#endif