src/devtools/met-driver/4.19/mt2712/mtk_dramc.h - T103 - Gitiles

 /* Copyright Statement:
  *
  * This software/firmware and related documentation ("MediaTek Software") are
  * protected under relevant copyright laws. The information contained herein
  * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  * Without the prior written permission of MediaTek inc. and/or its licensors,
  * any reproduction, modification, use or disclosure of MediaTek Software,
  * and information contained herein, in whole or in part, shall be strictly prohibited.
  */
 /* MediaTek Inc. (C) 2012. All rights reserved.
  *
  * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  *
  * The following software/firmware and/or related documentation ("MediaTek Software")
  * have been modified by MediaTek Inc. All revisions are subject to any receiver's
  * applicable license agreements with MediaTek Inc.
  */

 #ifndef __MT_DRAMC_H__
 #define __MT_DRAMC_H__
 #include <linux/types.h>
 //#include "x_hal_io.h"

 /* define BM function base address */
 #define MET_DRAMC0_BASE                         (0xF0006000)
 #define MET_DRAMC1_BASE                         (0xF0010000)
 #define MET_DRAMC2_BASE                         (0xF0011000)
 #define TCM_DRAM_FLAGS_ADDR                     (0xF00080F8)
 #define DRAM_CLOCK_MASK                         (0x00000FFF)

 #define BASE_DDR_CLK                            1000000
 #define TCMGET_DDR_CLK(p)                       ((p & DRAM_CLOCK_MASK) * BASE_DDR_CLK)

 /* define BM function offset */
 #define DRAMC_MON_BM(i)                         (i + 0x80)
 #define DRAMC_MON_BMCYC(i)                      (i + 0x8C) /* Bus monitor cycle number, BMCYC */
 #define DRAMC_MON_ROBM0(i)                      (i + 0x90) /* Bus monitor counter for group 1,BMLENGP1_CNT */
 #define DRAMC_MON_ROBM1(i)                      (i + 0x94) /* Bus monitor counter for group 2,BMLENGP2_CNT */
 #define DRAMC_MON_ROBM2(i)                      (i + 0x98) /* Bus monitor counter for group 3,BMLENGP3_CNT */
 #define DRAMC_MON_ROBM3(i)                      (i + 0x9C) /* bus monitor cycle counter,BM_CYC_CNT */
 #define DRAMC_MON_ROBM4(i)                      (i + 0xA0) /* Maximum burst length, 16'h0000, MAX_BSTCNT */

 /* define BM function shift */
 #define DRAMC_BM_PACNTEN                        (31) /* Bus monitor function select for number of precharge and active */
 #define DRAMC_BM_REQCNTEN                       (30) /* Bus monitor function select for number of REQ='1'&ALE='1' */
 #define DRAMC_BM_CHGPRIEN                       (29) /* On-line change agent priority enabling */
 #define DRAMC_BM_FREEZE_SHIFT                   (28) /* Bus monitor freeze */
 #define DRAMC_BM_DMBW32B_SHIFT                  (27) /* 1:External 32Bit data bus, 0:External 16Bit data bus */
 #define DRAMC_BM_WREN_SHIFT                     (25) /* Bus monitor only monitor write cycle enabling */
 #define DRAMC_BM_RDEN_SHIFT                     (24) /* Bus monitor only monitor read cycle enabling */
 #define DRAMC_BM_GROUP3_ENABLE_SHIFT            (23) /* Bus monitor for Group 3 agents enabling */
 #define DRAMC_BM_GROUP3_AGENT_ID_SHIFT          (20) /* Bus monitor for Group 3 agent-ID */
 #define DRAMC_BM_GROUP3_AGENT_ID_LEN            (3)
 #define DRAMC_BM_GROUP2_ENABLE_SHIFT            (19) /* Bus monitor for Group 2 agents enabling */
 #define DRAMC_BM_GROUP2_AGENT_ID_SHIFT          (16) /* Bus monitor for Group 2 agent-ID */
 #define DRAMC_BM_GROUP2_AGENT_ID_LEN            (3)
 #define DRAMC_BM_GROUP1_ENABLE_SHIFT            (15) /* Bus monitor for Group 1 agents enabling */
 #define DRAMC_BM_GROUP1_AGENT_ID_SHIFT          (8) /* Bus monitor for Group 1 agent-ID or */
 #define DRAMC_BM_GROUP1_AGENT_ID_LEN            (5)
 #define DRAMC_BM_BSTCNTEN                       (7) /* Monitor burst length enable */
 #define DRAMC_BM_R_DMBSTCNT_SEL                 (6) /* Latency mode select */
 #define DRAMC_BM_R_DMLATRECEN                   (5) /* Agent latency record enable */
 #define DRAMC_BM_BSTCNT                         (0) /* Agent-ID of the burst length monitored agent */
 #define DRAMC_BM_BSTCNT_LEN                     (4)

 /* define TCM function base address */
 #ifndef IO_VIRT
 #define IO_VIRT                                 (0xF0000000)
 #endif

 #define REG_RW_GPRB6                            (0x00f8) /* RISC Byte General Purpose Register 6 */
 #define TCM_SRAM_ADDR                           (IO_VIRT + 0x8000)

 #ifdef CONFIG_64BIT
 #define TCM_DRAM_FLAGS                          (*((volatile unsigned long*)(OFFSET_64BIT + TCM_SRAM_ADDR + REG_RW_GPRB6)))
 #else
 #define TCM_DRAM_FLAGS                          (*((volatile unsigned long*)(TCM_SRAM_ADDR + REG_RW_GPRB6)))
 #endif

 #define CHA_FORCE32_SHIFT                       (22)
 #define DRAM_CHA_FORCE32                        (1U << CHA_FORCE32_SHIFT)
 #define CHB_FORCE32_SHIFT                       (23)
 #define DRAM_CHB_FORCE32                        (1U << CHB_FORCE32_SHIFT)
 #define CHC_FORCE32_SHIFT                       (31)
 #define DRAM_CHC_FORCE32                        (1U << CHC_FORCE32_SHIFT)


 /* to check dramc is ext 32 bit or not*/
 #define DRMAC_IS_FORCE32(p)                     ((TCM_DRAM_FLAGS & p) ? 0 : 1)

 /* generate random cycle to return fake report */
 /* #define DRAMC_FAKE_REPORT */

 /* define dramc spec */
 #define DRAMC_MX_CHANNUM                        (1)
 #define DRAMC_MX_GRPNUM                         (3)
 #define DRAMC_MX_NUM_IN_AGRP                    (32)
 #define DRAMC_MX_AGENT_NAMEBUF                  (96)

 /* define all group id */
 #define DRAMC_ALL_GROUP_AGENT_ID                (0x20)
 #define DRAMC_MX_LATENCY                        (0x21)

 /* efuse bit[15:14]
 00:4G
 01:3G
 10:2G
 11:1G */
 #define DRAMC_EFUSE_BIT_ADDRESS                 (0xF0008664)
 #define DRAMC_EFUSE_BIT_MASK                    (0x0000C000)
 #define DRAMC_EFUSE_BIT_1G                      (0x0000C000)
 #define DRAMC_EFUSE_BIT_2G                      (0x00008000)
 #define DRAMC_EFUSE_BIT_3G                      (0x00004000)
 #define DRAMC_EFUSE_BIT_4G                      (0x00000000)

 #define DRAM_DDRPHY_CHA_BANK                    (IO_VIRT + 0x7A000)
 #define DRAM_DDRPHY_CHB_BANK                    (IO_VIRT + 0x7B000)
 #define DRAM_DDRPHY_CHC_BANK                    (IO_VIRT + 0x7C000)

 #define DRAM_BASE                               (IO_VIRT + 0x07000)
 #define DRAM_CHB_BASE                           (IO_VIRT + 0x0F000)
 #define DRAM_CHC_BASE                           (IO_VIRT + 0x15000)

 /* Bandwidth counter for agent0-15 */
 #define DRAMC_MON_AGENT_NUM                     (16)
 #define DRAMC_MON_AGENT_BASE(i)                 (i + 0x2C0)
 #define DRAMC_MON_AGENT0(i)                     (i + 0x2C0)
 #define DRAMC_MON_AGENT1(i)                     (i + 0x2C4)
 #define DRAMC_MON_AGENT2(i)                     (i + 0x2C8)
 #define DRAMC_MON_AGENT3(i)                     (i + 0x2CC)
 #define DRAMC_MON_AGENT4(i)                     (i + 0x2D0)
 #define DRAMC_MON_AGENT5(i)                     (i + 0x2D4)
 #define DRAMC_MON_AGENT6(i)                     (i + 0x2D8)
 #define DRAMC_MON_AGENT7(i)                     (i + 0x2DC)
 #define DRAMC_MON_AGENT8(i)                     (i + 0x2E0)
 #define DRAMC_MON_AGENT9(i)                     (i + 0x2E4)
 #define DRAMC_MON_AGENT10(i)                    (i + 0x2E8)
 #define DRAMC_MON_AGENT11(i)                    (i + 0x2EC)
 #define DRAMC_MON_AGENT12(i)                    (i + 0x2F0)
 #define DRAMC_MON_AGENT13(i)                    (i + 0x2F4)
 #define DRAMC_MON_AGENT14(i)                    (i + 0x2F8)
 #define DRAMC_MON_AGENT15(i)                    (i + 0x2FC)

 /* total latency counter for agent0-15 */
 #define DRAMC_MON_LTY_AGENT_NUM                 (16)
 #define DRAMC_MON_LTY_AGENT_BASE(i)             (i + 0x300)
 #define DRAMC_MON_LTY_AGENT0(i)                 (i + 0x300)
 #define DRAMC_MON_LTY_AGENT1(i)                 (i + 0x304)
 #define DRAMC_MON_LTY_AGENT2(i)                 (i + 0x308)
 #define DRAMC_MON_LTY_AGENT3(i)                 (i + 0x30C)
 #define DRAMC_MON_LTY_AGENT4(i)                 (i + 0x310)
 #define DRAMC_MON_LTY_AGENT5(i)                 (i + 0x314)
 #define DRAMC_MON_LTY_AGENT6(i)                 (i + 0x318)
 #define DRAMC_MON_LTY_AGENT7(i)                 (i + 0x31C)
 #define DRAMC_MON_LTY_AGENT8(i)                 (i + 0x320)
 #define DRAMC_MON_LTY_AGENT9(i)                 (i + 0x324)
 #define DRAMC_MON_LTY_AGENT10(i)                (i + 0x328)
 #define DRAMC_MON_LTY_AGENT11(i)                (i + 0x32C)
 #define DRAMC_MON_LTY_AGENT12(i)                (i + 0x330)
 #define DRAMC_MON_LTY_AGENT13(i)                (i + 0x334)
 #define DRAMC_MON_LTY_AGENT14(i)                (i + 0x338)
 #define DRAMC_MON_LTY_AGENT15(i)                (i + 0x33C)

 /* max latency counter for agent0-15 */
 #define DRAMC_MON_MAX_LTY_AGENT_NUM             (16)
 #define DRAMC_MON_MAX_LTY_AGENT_BASE(i)         (i + 0x340)
 #define DRAMC_MON_MAX_LTY_AGENT0(i)             (i + 0x340)
 #define DRAMC_MON_MAX_LTY_AGENT1(i)             (i + 0x340)
 #define DRAMC_MON_MAX_LTY_AGENT2(i)             (i + 0x344)
 #define DRAMC_MON_MAX_LTY_AGENT3(i)             (i + 0x344)
 #define DRAMC_MON_MAX_LTY_AGENT4(i)             (i + 0x348)
 #define DRAMC_MON_MAX_LTY_AGENT5(i)             (i + 0x348)
 #define DRAMC_MON_MAX_LTY_AGENT6(i)             (i + 0x34C)
 #define DRAMC_MON_MAX_LTY_AGENT7(i)             (i + 0x34C)
 #define DRAMC_MON_MAX_LTY_AGENT8(i)             (i + 0x350)
 #define DRAMC_MON_MAX_LTY_AGENT9(i)             (i + 0x350)
 #define DRAMC_MON_MAX_LTY_AGENT10(i)            (i + 0x354)
 #define DRAMC_MON_MAX_LTY_AGENT11(i)            (i + 0x354)
 #define DRAMC_MON_MAX_LTY_AGENT12(i)            (i + 0x358)
 #define DRAMC_MON_MAX_LTY_AGENT13(i)            (i + 0x358)
 #define DRAMC_MON_MAX_LTY_AGENT14(i)            (i + 0x35C)
 #define DRAMC_MON_MAX_LTY_AGENT15(i)            (i + 0x35C)

 struct dramc_desc_t {
     int agent_id;
     char name[DRAMC_MX_AGENT_NAMEBUF];
 };

 #define DRAMC_AGENT_TABLE \
 { \
 	/* define channel A releationship between group and name */ \
 	{ \
 		{ \
 			/* GRP 1 */ \
 			{0, 	"00_audio"}, \
 			{1, 	"01_demux/gcpu/ddi"}, \
 			{2, 	"02_vbi/3d/tve"}, \
 			{3, 	"03_xpscaler_ip/tddc"}, \
 			{4, 	"04_none"}, \
 			{5, 	"05_audio_dsp_low1"}, \
 			{6, 	"06_2d_graph/2dgraph_cmd/irt_dma"}, \
 			{7, 	"07_ether/ci-spi/rs232"}, \
 			{8,	"08_demod_isdbt"}, \
 			{9, 	"09_usb2"}, \
 			{10, 	"10_usb3_d"}, \
 			{11,	"11_mmu"}, \
 			{12,	"12_arm11"}, \
 			{13,	"13_msdc/emmc"}, \
 			{14,	"14_gdma"}, \
 			{15,	"15_test0/audio_dsp0"}, \
 			{-1,	""} \
 		}, \
 		{ \
 			/* GRP 2 */ \
 			{16,	"16_nfi_dma/sfalsh_dma/lzhs/ci_spi"}, \
 			{17,	"17_ufozip"}, \
 			{18,	"18_usb3_c"}, \
 			{19,	"19_none"}, \
 			{20,	"20_none"}, \
 			{21,	"21_none"}, \
 			{22,	"22_none"}, \
 			{30,	"30_none"}, \
 			{-1,	""} \
 		}, \
 		{ \
 			/* GRP 3 */ \
 			{23,	"23_none"}, \
 			{24,	"24_none"}, \
 			{25,	"25_none"}, \
 			{26,	"26_none"}, \
 			{27,	"27_none"}, \
 			{28,	"28_none"}, \
 			{29,	"29_none"}, \
 			{31,	"31_none"}, \
 			{-1,	""} \
 		} \
 	} \
 }

 /* some marco and static inline function define */
 static inline int FIND_NEXT_AGENT(u64 mask, int agent)
 {
     int idx = 0;
     int mx_cnt = sizeof(u64)*8;
     int temp_agent = agent + 1;

     for (idx = 0 ; idx < mx_cnt; idx++,temp_agent++) {
         if (mx_cnt == temp_agent)
             temp_agent = 0;
         if ((1ULL<<temp_agent) & mask)
             break;
     }
     if (idx == mx_cnt)
         return -1;
     return temp_agent;
 }

 #define GROUP_ID(agent) ((agent <= 0xF)?1:((agent<=0x17)?2:3))
 #define GROUP1_MASK     (0xFFFF)


 /* function prototype */
 extern void DRAMC_Init(int chan);
 extern void DRAMC_MaxLtcyMode(int chan, int enable);
 extern void DRAMC_Enable(int chan, int group, int agent);
 extern void DRAMC_Disable(int chan);
 extern void DRAMC_Freeze(int chan);
 extern void DRAMC_ConfigTargetCount(int chan, u32 count);
 extern u32 DRAMC_GetMaxLtcy(int chan);
 extern u32 DRAMC_GetCycleCount(int chan, int group);
 extern u32 DRAMC_GetTotalCycleCount(int chan);
 extern u32 DRAMC_GetDramcFreq(void);
 extern int DRAMC_CheckCntIsOverFlow(u32 count);

 extern void DRAMC_WriteMode(int chan, int enable);
 extern void DRAMC_ReadMode(int chan, int enable);
 extern unsigned int DRAMC_GetEfuseValue(void);

 extern void DRAMC_GetGroup1AgentCounter(int chan, unsigned int* counter);
 extern void DRAMC_GetGroup1Latency(int chan, unsigned int* latency);
 extern void DRAMC_GetGroup1MaxLatency(int chan, unsigned int* max_ltcy);

 #endif
	/* Copyright Statement:
	*
	* This software/firmware and related documentation ("MediaTek Software") are
	* protected under relevant copyright laws. The information contained herein
	* is confidential and proprietary to MediaTek Inc. and/or its licensors.
	* Without the prior written permission of MediaTek inc. and/or its licensors,
	* any reproduction, modification, use or disclosure of MediaTek Software,
	* and information contained herein, in whole or in part, shall be strictly prohibited.
	*/
	/* MediaTek Inc. (C) 2012. All rights reserved.
	*
	* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
	* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
	* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
	* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
	* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
	* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
	* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
	* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
	* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
	* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
	* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
	* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
	* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
	* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
	* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
	* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
	*
	* The following software/firmware and/or related documentation ("MediaTek Software")
	* have been modified by MediaTek Inc. All revisions are subject to any receiver's
	* applicable license agreements with MediaTek Inc.
	*/

	#ifndef __MT_DRAMC_H__
	#define __MT_DRAMC_H__
	#include <linux/types.h>
	//#include "x_hal_io.h"

	/* define BM function base address */
	#define MET_DRAMC0_BASE (0xF0006000)
	#define MET_DRAMC1_BASE (0xF0010000)
	#define MET_DRAMC2_BASE (0xF0011000)
	#define TCM_DRAM_FLAGS_ADDR (0xF00080F8)
	#define DRAM_CLOCK_MASK (0x00000FFF)

	#define BASE_DDR_CLK 1000000
	#define TCMGET_DDR_CLK(p) ((p & DRAM_CLOCK_MASK) * BASE_DDR_CLK)

	/* define BM function offset */
	#define DRAMC_MON_BM(i) (i + 0x80)
	#define DRAMC_MON_BMCYC(i) (i + 0x8C) /* Bus monitor cycle number, BMCYC */
	#define DRAMC_MON_ROBM0(i) (i + 0x90) /* Bus monitor counter for group 1,BMLENGP1_CNT */
	#define DRAMC_MON_ROBM1(i) (i + 0x94) /* Bus monitor counter for group 2,BMLENGP2_CNT */
	#define DRAMC_MON_ROBM2(i) (i + 0x98) /* Bus monitor counter for group 3,BMLENGP3_CNT */
	#define DRAMC_MON_ROBM3(i) (i + 0x9C) /* bus monitor cycle counter,BM_CYC_CNT */
	#define DRAMC_MON_ROBM4(i) (i + 0xA0) /* Maximum burst length, 16'h0000, MAX_BSTCNT */

	/* define BM function shift */
	#define DRAMC_BM_PACNTEN (31) /* Bus monitor function select for number of precharge and active */
	#define DRAMC_BM_REQCNTEN (30) /* Bus monitor function select for number of REQ='1'&ALE='1' */
	#define DRAMC_BM_CHGPRIEN (29) /* On-line change agent priority enabling */
	#define DRAMC_BM_FREEZE_SHIFT (28) /* Bus monitor freeze */
	#define DRAMC_BM_DMBW32B_SHIFT (27) /* 1:External 32Bit data bus, 0:External 16Bit data bus */
	#define DRAMC_BM_WREN_SHIFT (25) /* Bus monitor only monitor write cycle enabling */
	#define DRAMC_BM_RDEN_SHIFT (24) /* Bus monitor only monitor read cycle enabling */
	#define DRAMC_BM_GROUP3_ENABLE_SHIFT (23) /* Bus monitor for Group 3 agents enabling */
	#define DRAMC_BM_GROUP3_AGENT_ID_SHIFT (20) /* Bus monitor for Group 3 agent-ID */
	#define DRAMC_BM_GROUP3_AGENT_ID_LEN (3)
	#define DRAMC_BM_GROUP2_ENABLE_SHIFT (19) /* Bus monitor for Group 2 agents enabling */
	#define DRAMC_BM_GROUP2_AGENT_ID_SHIFT (16) /* Bus monitor for Group 2 agent-ID */
	#define DRAMC_BM_GROUP2_AGENT_ID_LEN (3)
	#define DRAMC_BM_GROUP1_ENABLE_SHIFT (15) /* Bus monitor for Group 1 agents enabling */
	#define DRAMC_BM_GROUP1_AGENT_ID_SHIFT (8) /* Bus monitor for Group 1 agent-ID or */
	#define DRAMC_BM_GROUP1_AGENT_ID_LEN (5)
	#define DRAMC_BM_BSTCNTEN (7) /* Monitor burst length enable */
	#define DRAMC_BM_R_DMBSTCNT_SEL (6) /* Latency mode select */
	#define DRAMC_BM_R_DMLATRECEN (5) /* Agent latency record enable */
	#define DRAMC_BM_BSTCNT (0) /* Agent-ID of the burst length monitored agent */
	#define DRAMC_BM_BSTCNT_LEN (4)

	/* define TCM function base address */
	#ifndef IO_VIRT
	#define IO_VIRT (0xF0000000)
	#endif

	#define REG_RW_GPRB6 (0x00f8) /* RISC Byte General Purpose Register 6 */
	#define TCM_SRAM_ADDR (IO_VIRT + 0x8000)

	#ifdef CONFIG_64BIT
	#define TCM_DRAM_FLAGS (((volatile unsigned long)(OFFSET_64BIT + TCM_SRAM_ADDR + REG_RW_GPRB6)))
	#else
	#define TCM_DRAM_FLAGS (((volatile unsigned long)(TCM_SRAM_ADDR + REG_RW_GPRB6)))
	#endif

	#define CHA_FORCE32_SHIFT (22)
	#define DRAM_CHA_FORCE32 (1U << CHA_FORCE32_SHIFT)
	#define CHB_FORCE32_SHIFT (23)
	#define DRAM_CHB_FORCE32 (1U << CHB_FORCE32_SHIFT)
	#define CHC_FORCE32_SHIFT (31)
	#define DRAM_CHC_FORCE32 (1U << CHC_FORCE32_SHIFT)


	/* to check dramc is ext 32 bit or not*/
	#define DRMAC_IS_FORCE32(p) ((TCM_DRAM_FLAGS & p) ? 0 : 1)

	/* generate random cycle to return fake report */
	/* #define DRAMC_FAKE_REPORT */

	/* define dramc spec */
	#define DRAMC_MX_CHANNUM (1)
	#define DRAMC_MX_GRPNUM (3)
	#define DRAMC_MX_NUM_IN_AGRP (32)
	#define DRAMC_MX_AGENT_NAMEBUF (96)

	/* define all group id */
	#define DRAMC_ALL_GROUP_AGENT_ID (0x20)
	#define DRAMC_MX_LATENCY (0x21)

	/* efuse bit[15:14]
	00:4G
	01:3G
	10:2G
	11:1G */
	#define DRAMC_EFUSE_BIT_ADDRESS (0xF0008664)
	#define DRAMC_EFUSE_BIT_MASK (0x0000C000)
	#define DRAMC_EFUSE_BIT_1G (0x0000C000)
	#define DRAMC_EFUSE_BIT_2G (0x00008000)
	#define DRAMC_EFUSE_BIT_3G (0x00004000)
	#define DRAMC_EFUSE_BIT_4G (0x00000000)

	#define DRAM_DDRPHY_CHA_BANK (IO_VIRT + 0x7A000)
	#define DRAM_DDRPHY_CHB_BANK (IO_VIRT + 0x7B000)
	#define DRAM_DDRPHY_CHC_BANK (IO_VIRT + 0x7C000)

	#define DRAM_BASE (IO_VIRT + 0x07000)
	#define DRAM_CHB_BASE (IO_VIRT + 0x0F000)
	#define DRAM_CHC_BASE (IO_VIRT + 0x15000)

	/* Bandwidth counter for agent0-15 */
	#define DRAMC_MON_AGENT_NUM (16)
	#define DRAMC_MON_AGENT_BASE(i) (i + 0x2C0)
	#define DRAMC_MON_AGENT0(i) (i + 0x2C0)
	#define DRAMC_MON_AGENT1(i) (i + 0x2C4)
	#define DRAMC_MON_AGENT2(i) (i + 0x2C8)
	#define DRAMC_MON_AGENT3(i) (i + 0x2CC)
	#define DRAMC_MON_AGENT4(i) (i + 0x2D0)
	#define DRAMC_MON_AGENT5(i) (i + 0x2D4)
	#define DRAMC_MON_AGENT6(i) (i + 0x2D8)
	#define DRAMC_MON_AGENT7(i) (i + 0x2DC)
	#define DRAMC_MON_AGENT8(i) (i + 0x2E0)
	#define DRAMC_MON_AGENT9(i) (i + 0x2E4)
	#define DRAMC_MON_AGENT10(i) (i + 0x2E8)
	#define DRAMC_MON_AGENT11(i) (i + 0x2EC)
	#define DRAMC_MON_AGENT12(i) (i + 0x2F0)
	#define DRAMC_MON_AGENT13(i) (i + 0x2F4)
	#define DRAMC_MON_AGENT14(i) (i + 0x2F8)
	#define DRAMC_MON_AGENT15(i) (i + 0x2FC)

	/* total latency counter for agent0-15 */
	#define DRAMC_MON_LTY_AGENT_NUM (16)
	#define DRAMC_MON_LTY_AGENT_BASE(i) (i + 0x300)
	#define DRAMC_MON_LTY_AGENT0(i) (i + 0x300)
	#define DRAMC_MON_LTY_AGENT1(i) (i + 0x304)
	#define DRAMC_MON_LTY_AGENT2(i) (i + 0x308)
	#define DRAMC_MON_LTY_AGENT3(i) (i + 0x30C)
	#define DRAMC_MON_LTY_AGENT4(i) (i + 0x310)
	#define DRAMC_MON_LTY_AGENT5(i) (i + 0x314)
	#define DRAMC_MON_LTY_AGENT6(i) (i + 0x318)
	#define DRAMC_MON_LTY_AGENT7(i) (i + 0x31C)
	#define DRAMC_MON_LTY_AGENT8(i) (i + 0x320)
	#define DRAMC_MON_LTY_AGENT9(i) (i + 0x324)
	#define DRAMC_MON_LTY_AGENT10(i) (i + 0x328)
	#define DRAMC_MON_LTY_AGENT11(i) (i + 0x32C)
	#define DRAMC_MON_LTY_AGENT12(i) (i + 0x330)
	#define DRAMC_MON_LTY_AGENT13(i) (i + 0x334)
	#define DRAMC_MON_LTY_AGENT14(i) (i + 0x338)
	#define DRAMC_MON_LTY_AGENT15(i) (i + 0x33C)

	/* max latency counter for agent0-15 */
	#define DRAMC_MON_MAX_LTY_AGENT_NUM (16)
	#define DRAMC_MON_MAX_LTY_AGENT_BASE(i) (i + 0x340)
	#define DRAMC_MON_MAX_LTY_AGENT0(i) (i + 0x340)
	#define DRAMC_MON_MAX_LTY_AGENT1(i) (i + 0x340)
	#define DRAMC_MON_MAX_LTY_AGENT2(i) (i + 0x344)
	#define DRAMC_MON_MAX_LTY_AGENT3(i) (i + 0x344)
	#define DRAMC_MON_MAX_LTY_AGENT4(i) (i + 0x348)
	#define DRAMC_MON_MAX_LTY_AGENT5(i) (i + 0x348)
	#define DRAMC_MON_MAX_LTY_AGENT6(i) (i + 0x34C)
	#define DRAMC_MON_MAX_LTY_AGENT7(i) (i + 0x34C)
	#define DRAMC_MON_MAX_LTY_AGENT8(i) (i + 0x350)
	#define DRAMC_MON_MAX_LTY_AGENT9(i) (i + 0x350)
	#define DRAMC_MON_MAX_LTY_AGENT10(i) (i + 0x354)
	#define DRAMC_MON_MAX_LTY_AGENT11(i) (i + 0x354)
	#define DRAMC_MON_MAX_LTY_AGENT12(i) (i + 0x358)
	#define DRAMC_MON_MAX_LTY_AGENT13(i) (i + 0x358)
	#define DRAMC_MON_MAX_LTY_AGENT14(i) (i + 0x35C)
	#define DRAMC_MON_MAX_LTY_AGENT15(i) (i + 0x35C)

	struct dramc_desc_t {
	int agent_id;
	char name[DRAMC_MX_AGENT_NAMEBUF];
	};

	#define DRAMC_AGENT_TABLE \
	{ \
	/* define channel A releationship between group and name */ \
	{ \
	{ \
	/* GRP 1 */ \
	{0, "00_audio"}, \
	{1, "01_demux/gcpu/ddi"}, \
	{2, "02_vbi/3d/tve"}, \
	{3, "03_xpscaler_ip/tddc"}, \
	{4, "04_none"}, \
	{5, "05_audio_dsp_low1"}, \
	{6, "06_2d_graph/2dgraph_cmd/irt_dma"}, \
	{7, "07_ether/ci-spi/rs232"}, \
	{8, "08_demod_isdbt"}, \
	{9, "09_usb2"}, \
	{10, "10_usb3_d"}, \
	{11, "11_mmu"}, \
	{12, "12_arm11"}, \
	{13, "13_msdc/emmc"}, \
	{14, "14_gdma"}, \
	{15, "15_test0/audio_dsp0"}, \
	{-1, ""} \
	}, \
	{ \
	/* GRP 2 */ \
	{16, "16_nfi_dma/sfalsh_dma/lzhs/ci_spi"}, \
	{17, "17_ufozip"}, \
	{18, "18_usb3_c"}, \
	{19, "19_none"}, \
	{20, "20_none"}, \
	{21, "21_none"}, \
	{22, "22_none"}, \
	{30, "30_none"}, \
	{-1, ""} \
	}, \
	{ \
	/* GRP 3 */ \
	{23, "23_none"}, \
	{24, "24_none"}, \
	{25, "25_none"}, \
	{26, "26_none"}, \
	{27, "27_none"}, \
	{28, "28_none"}, \
	{29, "29_none"}, \
	{31, "31_none"}, \
	{-1, ""} \
	} \
	} \
	}

	/* some marco and static inline function define */
	static inline int FIND_NEXT_AGENT(u64 mask, int agent)
	{
	int idx = 0;
	int mx_cnt = sizeof(u64)*8;
	int temp_agent = agent + 1;

	for (idx = 0 ; idx < mx_cnt; idx++,temp_agent++) {
	if (mx_cnt == temp_agent)
	temp_agent = 0;
	if ((1ULL<<temp_agent) & mask)
	break;
	}
	if (idx == mx_cnt)
	return -1;
	return temp_agent;
	}

	#define GROUP_ID(agent) ((agent <= 0xF)?1:((agent<=0x17)?2:3))
	#define GROUP1_MASK (0xFFFF)


	/* function prototype */
	extern void DRAMC_Init(int chan);
	extern void DRAMC_MaxLtcyMode(int chan, int enable);
	extern void DRAMC_Enable(int chan, int group, int agent);
	extern void DRAMC_Disable(int chan);
	extern void DRAMC_Freeze(int chan);
	extern void DRAMC_ConfigTargetCount(int chan, u32 count);
	extern u32 DRAMC_GetMaxLtcy(int chan);
	extern u32 DRAMC_GetCycleCount(int chan, int group);
	extern u32 DRAMC_GetTotalCycleCount(int chan);
	extern u32 DRAMC_GetDramcFreq(void);
	extern int DRAMC_CheckCntIsOverFlow(u32 count);

	extern void DRAMC_WriteMode(int chan, int enable);
	extern void DRAMC_ReadMode(int chan, int enable);
	extern unsigned int DRAMC_GetEfuseValue(void);

	extern void DRAMC_GetGroup1AgentCounter(int chan, unsigned int* counter);
	extern void DRAMC_GetGroup1Latency(int chan, unsigned int* latency);
	extern void DRAMC_GetGroup1MaxLatency(int chan, unsigned int* max_ltcy);

	#endif