| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2018 MediaTek Inc. |
| * Author: Yong Wu <yong.wu@mediatek.com> |
| */ |
| |
| #include <linux/module.h> |
| #include "clkchk.h" |
| |
| static const char * const off_pll_names[] = { |
| "armpll", |
| "mainpll", |
| "univpll", |
| "msdcpll", |
| "apll1", |
| "apll2", |
| "mpll", |
| "etherpll", |
| NULL |
| }; |
| |
| static const char * const all_clk_names[] = { |
| "armpll", |
| "mainpll", |
| "univpll", |
| "msdcpll", |
| "apll1", |
| "apll2", |
| "mpll", |
| "etherpll", |
| "syspll_ck", |
| "syspll_d2", |
| "syspll1_d2", |
| "syspll1_d4", |
| "syspll1_d8", |
| "syspll1_d16", |
| "syspll_d3", |
| "syspll2_d2", |
| "syspll2_d4", |
| "syspll2_d8", |
| "syspll_d5", |
| "syspll3_d2", |
| "syspll3_d4", |
| "syspll_d7", |
| "syspll4_d2", |
| "syspll4_d4", |
| "usb20_192m_ck", |
| "usb20_192m_d2", |
| "usb20_192m_d4", |
| "univpll_d2", |
| "univpll1_d2", |
| "univpll1_d4", |
| "univpll1_d8", |
| "univpll_d3", |
| "univpll2_d2", |
| "univpll2_d4", |
| "univpll2_d8", |
| "univpll2_d16", |
| "univpll_d5", |
| "univpll3_d2", |
| "univpll3_d4", |
| "msdcpll_ck", |
| "msdcpll_d2", |
| "apll1_ck", |
| "apll1_d2", |
| "apll1_d4", |
| "apll1_d8", |
| "apll2_ck", |
| "apll2_d2", |
| "apll2_d4", |
| "apll2_d8", |
| "etherpll_ck", |
| "etherpll_d4", |
| "etherpll_d10", |
| "hd_faxi_ck", |
| "f_fuart_ck", |
| "spi_ck", |
| "msdc50_0_ck", |
| "msdc30_1_ck", |
| "audio_ck", |
| "aud_1_ck", |
| "aud_engen1_ck", |
| "aud_engen2_ck", |
| "hsm_crypto_ck", |
| "i2c_ck", |
| "msdc5_2hclk_ck", |
| "msdc30_2_ck", |
| "nfi1x_bclk_ck", |
| "pcie_mac_ck", |
| "f_fssusb_top_ck", |
| "spislv_ck", |
| "ether_125m_ck", |
| "pwm_ck", |
| "arm_div_pll1", |
| "arm_div_pll2", |
| |
| /* CLK_CFG_0 */ |
| "axi_sel", |
| "uart_sel", |
| "spi_sel", |
| "msdc5_0hclk", |
| |
| /* CLK_CFG_1 */ |
| "msdc50_0_sel", |
| "msdc30_1_sel", |
| "audio_sel", |
| "aud_intbus_sel", |
| "aud_1_sel", |
| "aud_2_sel", |
| "aud_engen1_sel", |
| "aud_engen2_sel", |
| |
| /* CLK_CFG_3 */ |
| "dxcc_sel", |
| "hsm_crypto_sel", |
| "hsm_arc_sel", |
| "gcpu_sel", |
| |
| /* CLK_CFG_4 */ |
| "ecc_sel", |
| "usb_top_sel", |
| "spm_sel", |
| "i2c_sel", |
| |
| /* CLK_CFG_5 */ |
| "ulposc_sel", |
| "msdc5_2hclk_sel", |
| "msdc30_2_sel", |
| "nfi1x_bclk_sel", |
| |
| /* CLK_CFG_6 */ |
| "spinfi_bclk_sel", |
| "pcie_mac_sel", |
| "ssusb_top_sel", |
| "spislv_sel", |
| |
| /* CLK_CFG_7 */ |
| "ether_125m_sel", |
| "ether_50_sel", |
| "ether_62p4m_sel", |
| "pwm_sel", |
| |
| "i2s0_m_ck_sel", |
| "i2s1_m_ck_sel", |
| "i2s2_m_ck_sel", |
| "i2s3_m_ck_sel", |
| "i2s4_m_ck_sel", |
| |
| "apll12_div0", |
| "apll12_div1", |
| "apll12_div2", |
| "apll12_div3", |
| "apll12_div4", |
| "apll12_divb", |
| |
| "arm_div_pll1_en", |
| "arm_div_pll2_en", |
| |
| /* IFR0 */ |
| "ifr_apxgpt", |
| "ifr_icusb", |
| "ifr_gce", |
| "ifr_therm", |
| "ifr_i2c_ap", |
| "ifr_i2c_ccu", |
| "ifr_i2c_sspm", |
| "ifr_i2c_rsv", |
| "ifr_pwm_hclk", |
| "ifr_pwm1", |
| "ifr_pwm2", |
| "ifr_pwm3", |
| "ifr_pwm4", |
| "ifr_pwm5", |
| "ifr_pwm", |
| "ifr_uart0", |
| "ifr_uart1", |
| "ifr_uart2", |
| "ifr_uart3", |
| "ifr_gce_26m", |
| "ifr_dma", |
| /* IFR1 */ |
| "ifr_spi0", |
| "ifr_msdc0", |
| "ifr_msdc1", |
| "ifr_msdc2", |
| "ifr_trng", |
| "ifr_ccif1_ap", |
| "ifr_ccif1_md", |
| "ifr_pcie", |
| "ifr_nfi", |
| "ifr_ap_dma", |
| "ifr_dapc", |
| "ifr_ccif_ap", |
| "ifr_debugsys", |
| "ifr_ccif_md", |
| "ifr_hsm", |
| "ifr_hsm_ao", |
| "ifr_ether", |
| "ifr_spi_slave", |
| /* IFR2 */ |
| "ifr_pwmfb", |
| "ifr_ssusb", |
| "ifr_cldmabclk", |
| "ifr_audio26m", |
| "ifr_spi1", |
| "ifr_spi2", |
| "ifr_spi3", |
| "ifr_spi4", |
| "ifr_spi5", |
| "ifr_cq_dma", |
| /* IFR3 */ |
| "ifr_i2c6", |
| "ifr_msdc0_clk", |
| "ifr_msdc1_clk", |
| "ifr_msdc2_clk", |
| "ifr_mcu_pm_bclk", |
| "ifr_ccif2_ap", |
| "ifr_ccif2_md", |
| "ifr_uart4", |
| "ifr_uart5", |
| "ifr_uart6", |
| /* end */ |
| NULL |
| }; |
| |
| static const char * const compatible[] = {"mediatek,mt2731", NULL}; |
| |
| static struct clkchk_cfg_t cfg = { |
| .aee_excp_on_fail = false, |
| .warn_on_fail = false, |
| .compatible = compatible, |
| .off_pll_names = off_pll_names, |
| .all_clk_names = all_clk_names, |
| }; |
| |
| static int __init clkchk_platform_init(void) |
| { |
| return clkchk_init(&cfg); |
| } |
| late_initcall(clkchk_platform_init); |
| |