| /* |
| * Copyright (c) 2018 MediaTek Inc. |
| * Author: Yong Wu <yong.wu@mediatek.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <linux/clk-provider.h> |
| #include <linux/io.h> |
| |
| #include "clkdbg.h" |
| |
| #define DUMP_INIT_STATE 0 |
| |
| /* |
| * clkdbg dump_regs |
| */ |
| |
| enum { |
| topckgen, |
| infracfg, |
| scpsys, |
| apmixedsys, |
| audiosys, |
| }; |
| |
| #define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name } |
| |
| /* |
| * checkpatch.pl ERROR:COMPLEX_MACRO |
| * |
| * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name) |
| */ |
| |
| static struct regbase rb[] = { |
| [topckgen] = REGBASE_V(0x10000000, topckgen), |
| [infracfg] = REGBASE_V(0x10001000, infracfg), |
| [scpsys] = REGBASE_V(0x10006000, scpsys), |
| [apmixedsys] = REGBASE_V(0x1000c000, apmixedsys), |
| [audiosys] = REGBASE_V(0x11220000, audiosys), |
| }; |
| |
| #define REGNAME(_base, _ofs, _name) \ |
| { .base = &rb[_base], .ofs = _ofs, .name = #_name } |
| |
| static struct regname rn[] = { |
| REGNAME(topckgen, 0x040, CLK_CFG_0), |
| REGNAME(topckgen, 0x050, CLK_CFG_1), |
| REGNAME(topckgen, 0x060, CLK_CFG_2), |
| REGNAME(topckgen, 0x070, CLK_CFG_3), |
| REGNAME(topckgen, 0x080, CLK_CFG_4), |
| REGNAME(topckgen, 0x090, CLK_CFG_5), |
| REGNAME(topckgen, 0x0a0, CLK_CFG_6), |
| REGNAME(topckgen, 0x0b0, CLK_CFG_7), |
| /* audsys reg need special clk to access */ |
| /* REGNAME(audiosys, 0x000, AUDIO_TOP_CON0), |
| * REGNAME(audiosys, 0x004, AUDIO_TOP_CON1), |
| */ |
| REGNAME(infracfg, 0x090, MODULE_SW_CG_0), |
| REGNAME(infracfg, 0x094, MODULE_SW_CG_1), |
| REGNAME(infracfg, 0x0ac, MODULE_SW_CG_2), |
| REGNAME(infracfg, 0x0c8, MODULE_SW_CG_3), |
| |
| REGNAME(apmixedsys, 0x204, ARMPLL_CON0), |
| REGNAME(apmixedsys, 0x208, ARMPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x210, ARMPLL_CON3_PWR), |
| REGNAME(apmixedsys, 0x214, MAINPLL_CON0), |
| REGNAME(apmixedsys, 0x218, MAINPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x220, MAINPLL_CON3_PWR), |
| REGNAME(apmixedsys, 0x224, UNIVPLL_CON0), |
| REGNAME(apmixedsys, 0x228, UNIVPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x230, UNIVPLL_CON3_PWR), |
| REGNAME(apmixedsys, 0x234, MSDCPLL_CON0), |
| REGNAME(apmixedsys, 0x238, MSDCPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x240, MSDCPLL_CON3_PWR), |
| REGNAME(apmixedsys, 0x244, APLL1_CON0), |
| REGNAME(apmixedsys, 0xC, APLL1_TUNER_EN), |
| /* If tuner enable, use 0x40. */ |
| REGNAME(apmixedsys, 0x40, APLL1_PCW_TUREN), |
| REGNAME(apmixedsys, 0x248, APLL1_CON1_PD), |
| REGNAME(apmixedsys, 0x24C, APLL1_CON1_PCW), |
| REGNAME(apmixedsys, 0x250, APLL1_CON3_PWR), |
| REGNAME(apmixedsys, 0x258, APLL2_CON0), |
| REGNAME(apmixedsys, 0x260, APLL2_CON1_PCW), |
| REGNAME(apmixedsys, 0x264, APLL2_CON3_PWR), |
| REGNAME(apmixedsys, 0x26C, MPLL_CON0), |
| REGNAME(apmixedsys, 0x270, MPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x278, MPLL_CON3_PWR), |
| REGNAME(apmixedsys, 0x27C, ETHERPLL_CON0), |
| REGNAME(apmixedsys, 0x280, ETHERPLL_CON1_PCW), |
| REGNAME(apmixedsys, 0x288, ETHERPLL_CON3_PWR), |
| |
| REGNAME(scpsys, 0x0160, PWR_STATUS), |
| REGNAME(scpsys, 0x0164, PWR_STATUS_2ND), |
| REGNAME(scpsys, 0x0318, MD1_PWR_CON), |
| {} |
| }; |
| |
| static const struct regname *get_all_regnames(void) |
| { |
| return rn; |
| } |
| |
| static void __init init_regbase(void) |
| { |
| size_t i; |
| |
| for (i = 0; i < ARRAY_SIZE(rb); i++) |
| rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE); |
| } |
| |
| /* |
| * clkdbg fmeter |
| */ |
| |
| #include <linux/delay.h> |
| |
| #define clk_readl(addr) readl(addr) |
| #define clk_writel(addr, val) \ |
| do { writel(val, addr); wmb(); } while (0) /* sync write */ |
| |
| #define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n } |
| |
| static const struct fmeter_clk fclks[] = { |
| FMCLK(CKGEN, 1, "hf_faxi_ck"), |
| FMCLK(CKGEN, 2, "f_fuart_ck"), |
| FMCLK(CKGEN, 3, "hf_fspi_ck"), |
| FMCLK(CKGEN, 4, "hf_fmsdc50_0_hclk_ck"), |
| FMCLK(CKGEN, 5, "hf_fmsdc50_0_ck"), |
| FMCLK(CKGEN, 6, "hf_fmsdc30_1_ck"), |
| FMCLK(CKGEN, 7, "hf_faudio_ck"), |
| FMCLK(CKGEN, 8, "hf_faud_intbus_ck"), |
| FMCLK(CKGEN, 9, "hf_faud_1_ck"), |
| FMCLK(CKGEN, 10, "hf_faud_2_ck"), |
| FMCLK(CKGEN, 11, "hf_faud_engen1_ck"), |
| FMCLK(CKGEN, 12, "hf_faud_engen2_ck"), |
| FMCLK(CKGEN, 13, "hf_fdxcc_ck"), |
| FMCLK(CKGEN, 14, "hf_fhsm_crypto_ck"), |
| FMCLK(CKGEN, 15, "hf_fhsm_arc_ck"), |
| FMCLK(CKGEN, 16, "hf_fgcpu_ck"), |
| FMCLK(CKGEN, 17, "hf_fecc_ck"), |
| FMCLK(CKGEN, 18, "f_fusb_top_ck"), |
| FMCLK(CKGEN, 19, "hf_fspm_ck"), |
| FMCLK(CKGEN, 20, "hf_fi2c_ck"), |
| FMCLK(CKGEN, 21, "f_fpwrap_ulposc_ck"), |
| FMCLK(CKGEN, 22, "hf_fmsdc50_2_hclk_ck"), |
| FMCLK(CKGEN, 23, "hf_fmsdc30_2_ck"), |
| FMCLK(CKGEN, 24, "hf_fnfi1x_bclk_ck"), |
| FMCLK(CKGEN, 25, "hf_fspinfi_bclk_ck"), |
| FMCLK(CKGEN, 26, "hf_fpcie_mac_ck"), |
| FMCLK(CKGEN, 27, "f_fssusb_top_ck"), |
| FMCLK(CKGEN, 28, "hf_fspislv_ck"), |
| FMCLK(CKGEN, 29, "hf_fether_125m_ck"), |
| FMCLK(CKGEN, 30, "hf_fether_50m_rmii_ck"), |
| FMCLK(CKGEN, 31, "hf_fether_62p4m_ck"), |
| FMCLK(CKGEN, 32, "hf_fpwm_ck"), |
| FMCLK(CKGEN, 50, "hd_faxi_east_ck"), |
| FMCLK(CKGEN, 51, "hd_faxi_west_ck"), |
| FMCLK(CKGEN, 52, "hd_faxi_north_ck"), |
| FMCLK(CKGEN, 53, "hd_faxi_south_ck"), |
| FMCLK(CKGEN, 55, "fmem_ck_bfe_dcm_ch0"), |
| FMCLK(CKGEN, 56, "fmem_ck_aft_dcm_ch0"), |
| FMCLK(CKGEN, 57, "fmem_ck_bfe_dcm_ch1"), |
| FMCLK(CKGEN, 58, "fmem_ck_aft_dcm_ch1"), |
| |
| FMCLK(ABIST, 1, "AD_ARMPLL_CK"), |
| FMCLK(ABIST, 2, "AD_MAINPLL_1092M_CK"), |
| FMCLK(ABIST, 3, "AD_MDBPIPLL_DIV3_CK"), |
| FMCLK(ABIST, 4, "AD_MDBPIPLL_DIV7_CK"), |
| FMCLK(ABIST, 5, "AD_MDBRPPLL_DIV6_CK"), |
| FMCLK(ABIST, 6, "AD_MAIN_H546M_CK"), |
| FMCLK(ABIST, 7, "AD_MAIN_H364M_CK"), |
| FMCLK(ABIST, 8, "AD_MAIN_H218P4M_CK"), |
| FMCLK(ABIST, 9, "AD_MAIN_H156M_CK"), |
| FMCLK(ABIST, 10, "AD_UNIVPLL_1248M_CK"), |
| FMCLK(ABIST, 11, "AD_USB20_192M_CK"), |
| FMCLK(ABIST, 12, "AD_UNIV_624M_CK"), |
| FMCLK(ABIST, 13, "AD_UNIV_416M_CK"), |
| FMCLK(ABIST, 14, "AD_UNIV_249P6M_CK"), |
| FMCLK(ABIST, 15, "AD_UNIV_178P3M_CK"), |
| FMCLK(ABIST, 16, "AD_MDPLL1_FS26M_CK"), |
| FMCLK(ABIST, 17, "rtc32k_ck_i"), |
| FMCLK(ABIST, 18, "AD_MSDCPLL_416M_CK"), |
| FMCLK(ABIST, 19, "AD_APLLGP_TST_CK"), |
| FMCLK(ABIST, 20, "AD_APLL1_196P608M_CK"), |
| FMCLK(ABIST, 21, "AD_APLL2_180P6336M_CK"), |
| FMCLK(ABIST, 22, "AD_MPLL_208M_CK"), |
| FMCLK(ABIST, 23, "mcusys_arm_clk_out_all"), |
| FMCLK(ABIST, 24, "msdc01_in_ck"), |
| FMCLK(ABIST, 25, "msdc02_in_ck"), |
| FMCLK(ABIST, 26, "msdc11_in_ck"), |
| FMCLK(ABIST, 27, "msdc12_in_ck"), |
| FMCLK(ABIST, 28, "DA_USB20_48M_DIV_CK"), |
| FMCLK(ABIST, 29, "DA_UNIV_48M_DIV_CK"), |
| FMCLK(ABIST, 30, "DA_MPLL_104M_DIV_CK"), |
| FMCLK(ABIST, 31, "DA_MPLL_52M_DIV_CK"), |
| FMCLK(ABIST, 32, "DA_ARMCPU_MON_CK"), |
| FMCLK(ABIST, 33, "AD_ETHERPLL_500M_CK"), |
| FMCLK(ABIST, 34, "msdc21_in_ck"), |
| FMCLK(ABIST, 35, "msdc22_in_ck"), |
| FMCLK(ABIST, 60, "clkmon1_ck"), |
| FMCLK(ABIST, 61, "clkmon2_ck"), |
| FMCLK(ABIST, 62, "clkmon3_ck"), |
| FMCLK(ABIST, 63, "clkmon4_ck"), |
| {} |
| }; |
| |
| #define CLK_MISC_CFG_0 (rb[topckgen].virt + 0x104) |
| #define CLK_DBG_CFG (rb[topckgen].virt + 0x10C) |
| #define CLK26CALI_0 (rb[topckgen].virt + 0x220) |
| #define CLK26CALI_1 (rb[topckgen].virt + 0x224) |
| |
| static unsigned int mt_get_abist_freq(unsigned int ID) |
| { |
| int output = 0, i = 0; |
| unsigned int temp, clk26cali_0, clk_dbg_cfg; |
| unsigned int clk_misc_cfg_0, clk26cali_1; |
| |
| clk_dbg_cfg = clk_readl(CLK_DBG_CFG); |
| /* sel abist_cksw and enable freq meter sel abist */ |
| clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16)); |
| clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0); |
| /* select divider, WAIT CONFIRM, div 3, then output *4. */ |
| clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (0x3 << 24)); |
| clk26cali_0 = clk_readl(CLK26CALI_0); |
| clk26cali_1 = clk_readl(CLK26CALI_1); |
| clk_writel(CLK26CALI_0, 0x1000); |
| clk_writel(CLK26CALI_0, 0x1010); |
| |
| /* wait frequency meter finish */ |
| while (clk_readl(CLK26CALI_0) & 0x10) { |
| mdelay(10); |
| i++; |
| if (i > 10) { |
| /* pr_err("<freqmeter>abist(%d), timeout\n", ID); */ |
| break; |
| } |
| } |
| |
| temp = clk_readl(CLK26CALI_1) & 0xFFFF; |
| |
| output = ((temp * 26000)) / 1024; /* Khz */ |
| |
| clk_writel(CLK_DBG_CFG, clk_dbg_cfg); |
| clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0); |
| clk_writel(CLK26CALI_0, clk26cali_0); |
| clk_writel(CLK26CALI_1, clk26cali_1); |
| |
| return output * 4; |
| } |
| |
| static unsigned int mt_get_ckgen_freq(unsigned int ID) |
| { |
| int output = 0, i = 0; |
| unsigned int temp, clk26cali_0, clk_dbg_cfg; |
| unsigned int clk_misc_cfg_0, clk26cali_1; |
| |
| clk_dbg_cfg = clk_readl(CLK_DBG_CFG); |
| /* sel ckgen_cksw[22] and enable freq meter sel ckgen[21:16], |
| * 01:hd_faxi_ck |
| */ |
| clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1)); |
| clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0); |
| /* select divider dvt set zero */ |
| clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF)); |
| clk26cali_0 = clk_readl(CLK26CALI_0); |
| clk26cali_1 = clk_readl(CLK26CALI_1); |
| clk_writel(CLK26CALI_0, 0x1000); |
| clk_writel(CLK26CALI_0, 0x1010); |
| |
| /* wait frequency meter finish */ |
| while (clk_readl(CLK26CALI_0) & 0x10) { |
| mdelay(10); |
| i++; |
| if (i > 10) { |
| /* pr_err("<freqmeter>ckgen(%d), timeout\n", ID); */ |
| break; |
| } |
| } |
| |
| temp = clk_readl(CLK26CALI_1) & 0xFFFF; |
| |
| output = ((temp * 26000)) / 1024; /* Khz */ |
| |
| clk_writel(CLK_DBG_CFG, clk_dbg_cfg); |
| clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0); |
| clk_writel(CLK26CALI_0, clk26cali_0); |
| clk_writel(CLK26CALI_1, clk26cali_1); |
| |
| return output; |
| } |
| |
| static u32 fmeter_freq_op(const struct fmeter_clk *fclk) |
| { |
| if (fclk->type == ABIST) |
| return mt_get_abist_freq(fclk->id); |
| else if (fclk->type == CKGEN) |
| return mt_get_ckgen_freq(fclk->id); |
| return 0; |
| } |
| |
| static const struct fmeter_clk *get_all_fmeter_clks(void) |
| { |
| return fclks; |
| } |
| |
| /* |
| * clkdbg dump_state |
| */ |
| |
| static const char * const *get_all_clk_names(void) |
| { |
| static const char * const clks[] = { |
| "armpll", |
| "mainpll", |
| "univpll", |
| "msdcpll", |
| "apll1", |
| "apll2", |
| "mpll", |
| "etherpll", |
| "syspll_ck", |
| "syspll_d2", |
| "syspll1_d2", |
| "syspll1_d4", |
| "syspll1_d8", |
| "syspll1_d16", |
| "syspll_d3", |
| "syspll2_d2", |
| "syspll2_d4", |
| "syspll2_d8", |
| "syspll_d5", |
| "syspll3_d2", |
| "syspll3_d4", |
| "syspll_d7", |
| "syspll4_d2", |
| "syspll4_d4", |
| "usb20_192m_ck", |
| "usb20_192m_d2", |
| "usb20_192m_d4", |
| "univpll_d2", |
| "univpll1_d2", |
| "univpll1_d4", |
| "univpll1_d8", |
| "univpll_d3", |
| "univpll2_d2", |
| "univpll2_d4", |
| "univpll2_d8", |
| "univpll2_d16", |
| "univpll_d5", |
| "univpll3_d2", |
| "univpll3_d4", |
| "msdcpll_ck", |
| "msdcpll_d2", |
| "apll1_ck", |
| "apll1_d2", |
| "apll1_d4", |
| "apll1_d8", |
| "apll2_ck", |
| "apll2_d2", |
| "apll2_d4", |
| "apll2_d8", |
| "etherpll_ck", |
| "etherpll_d4", |
| "etherpll_d10", |
| "hd_faxi_ck", |
| "f_fuart_ck", |
| "spi_ck", |
| "msdc50_0_ck", |
| "msdc30_1_ck", |
| "audio_ck", |
| "aud_1_ck", |
| "aud_engen1_ck", |
| "aud_engen2_ck", |
| "hsm_crypto_ck", |
| "i2c_ck", |
| "msdc5_2hclk_ck", |
| "msdc30_2_ck", |
| "nfi1x_bclk_ck", |
| "pcie_mac_ck", |
| "f_fssusb_top_ck", |
| "spislv_ck", |
| "ether_125m_ck", |
| "pwm_ck", |
| "arm_div_pll1", |
| "arm_div_pll2", |
| |
| /* CLK_CFG_0 */ |
| "axi_sel", |
| "uart_sel", |
| "spi_sel", |
| "msdc5_0hclk", |
| |
| /* CLK_CFG_1 */ |
| "msdc50_0_sel", |
| "msdc30_1_sel", |
| "audio_sel", |
| "aud_intbus_sel", |
| "aud_1_sel", |
| "aud_2_sel", |
| "aud_engen1_sel", |
| "aud_engen2_sel", |
| |
| /* CLK_CFG_3 */ |
| "dxcc_sel", |
| "hsm_crypto_sel", |
| "hsm_arc_sel", |
| "gcpu_sel", |
| |
| /* CLK_CFG_4 */ |
| "ecc_sel", |
| "usb_top_sel", |
| "spm_sel", |
| "i2c_sel", |
| |
| /* CLK_CFG_5 */ |
| "ulposc_sel", |
| "msdc5_2hclk_sel", |
| "msdc30_2_sel", |
| "nfi1x_bclk_sel", |
| |
| /* CLK_CFG_6 */ |
| "spinfi_bclk_sel", |
| "pcie_mac_sel", |
| "ssusb_top_sel", |
| "spislv_sel", |
| |
| /* CLK_CFG_7 */ |
| "ether_125m_sel", |
| "ether_50_sel", |
| "ether_62p4m_sel", |
| "pwm_sel", |
| |
| "i2s0_m_ck_sel", |
| "i2s1_m_ck_sel", |
| "i2s2_m_ck_sel", |
| "i2s3_m_ck_sel", |
| "i2s4_m_ck_sel", |
| |
| "apll12_div0", |
| "apll12_div1", |
| "apll12_div2", |
| "apll12_div3", |
| "apll12_div4", |
| "apll12_divb", |
| |
| "arm_div_pll1_en", |
| "arm_div_pll2_en", |
| |
| /* IFR0 */ |
| "ifr_apxgpt", |
| "ifr_icusb", |
| "ifr_gce", |
| "ifr_therm", |
| "ifr_i2c_ap", |
| "ifr_i2c_ccu", |
| "ifr_i2c_sspm", |
| "ifr_i2c_rsv", |
| "ifr_pwm_hclk", |
| "ifr_pwm1", |
| "ifr_pwm2", |
| "ifr_pwm3", |
| "ifr_pwm4", |
| "ifr_pwm5", |
| "ifr_pwm", |
| "ifr_uart0", |
| "ifr_uart1", |
| "ifr_uart2", |
| "ifr_uart3", |
| "ifr_gce_26m", |
| "ifr_dma", |
| /* IFR1 */ |
| "ifr_spi0", |
| "ifr_msdc0", |
| "ifr_msdc1", |
| "ifr_msdc2", |
| "ifr_trng", |
| "ifr_ccif1_ap", |
| "ifr_ccif1_md", |
| "ifr_pcie", |
| "ifr_nfi", |
| "ifr_ap_dma", |
| "ifr_dapc", |
| "ifr_ccif_ap", |
| "ifr_debugsys", |
| "ifr_ccif_md", |
| "ifr_hsm", |
| "ifr_hsm_ao", |
| "ifr_ether", |
| "ifr_spi_slave", |
| /* IFR2 */ |
| "ifr_pwmfb", |
| "ifr_ssusb", |
| "ifr_cldmabclk", |
| "ifr_audio26m", |
| "ifr_spi1", |
| "ifr_spi2", |
| "ifr_spi3", |
| "ifr_spi4", |
| "ifr_spi5", |
| "ifr_cq_dma", |
| /* IFR3 */ |
| "ifr_i2c6", |
| "ifr_msdc0_clk", |
| "ifr_msdc1_clk", |
| "ifr_msdc2_clk", |
| "ifr_mcu_pm_bclk", |
| "ifr_ccif2_ap", |
| "ifr_ccif2_md", |
| "ifr_uart4", |
| "ifr_uart5", |
| "ifr_uart6", |
| /* end */ |
| NULL |
| }; |
| |
| return clks; |
| } |
| |
| /* |
| * clkdbg pwr_status |
| */ |
| |
| static const char * const *get_pwr_names(void) |
| { |
| static const char * const pwr_names[] = { |
| [0] = "MD1", |
| }; |
| |
| return pwr_names; |
| } |
| |
| u32 get_spm_pwr_status(void) |
| { |
| static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd; |
| |
| if (scpsys_base == NULL || pwr_sta == NULL || pwr_sta_2nd == NULL) { |
| scpsys_base = ioremap(0x10006000, PAGE_SIZE); |
| pwr_sta = scpsys_base + 0x180; |
| pwr_sta_2nd = scpsys_base + 0x184; |
| } |
| |
| return clk_readl(pwr_sta) & clk_readl(pwr_sta_2nd); |
| } |
| |
| /* |
| * clkdbg dump_clks |
| */ |
| |
| static void setup_provider_clk(struct provider_clk *pvdck) |
| { |
| static const struct { |
| const char *pvdname; |
| u32 pwr_mask; |
| } pvd_pwr_mask[] = { |
| }; |
| |
| size_t i; |
| const char *pvdname = pvdck->provider_name; |
| |
| if (pvdname == NULL) |
| return; |
| |
| for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) { |
| if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) { |
| pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask; |
| return; |
| } |
| } |
| } |
| |
| /* |
| * init functions |
| */ |
| |
| static const struct clkdbg_ops clkdbg_mt2731_ops = { |
| .get_all_fmeter_clks = get_all_fmeter_clks, |
| .fmeter_freq = fmeter_freq_op, |
| .get_all_regnames = get_all_regnames, |
| .get_all_clk_names = get_all_clk_names, |
| .get_pwr_names = get_pwr_names, |
| .setup_provider_clk = setup_provider_clk, |
| .get_spm_pwr_status = get_spm_pwr_status, |
| }; |
| |
| static void __init init_custom_cmds(void) |
| { |
| static const struct cmd_fn cmds[] = { |
| {} |
| }; |
| |
| set_custom_cmds(cmds); |
| } |
| |
| static int __init clkdbg_mt2731_init(void) |
| { |
| if (of_machine_is_compatible("mediatek,mt2731") == 0) |
| return -ENODEV; |
| |
| init_regbase(); |
| |
| init_custom_cmds(); |
| set_clkdbg_ops(&clkdbg_mt2731_ops); |
| |
| #if DUMP_INIT_STATE |
| print_regs(); |
| print_fmeter_all(); |
| #endif /* DUMP_INIT_STATE */ |
| |
| return 0; |
| } |
| late_initcall(clkdbg_mt2731_init); |