src/kernel/linux/v4.14/sound/soc/codecs/mt6389.c

// SPDX-License-Identifier: GPL-2.0
//
// MT6389.c  --  MT6389 ALSA SoC audio codec driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/delay.h>
#include <linux/debugfs.h>
#include <linux/kthread.h>
#include <linux/sched.h>

#include <sound/soc.h>
#ifndef CONFIG_MTK_PMIC_WRAP	/* y: use regmap, else use legacy api */
#ifdef CONFIG_MTK_PMIC_WRAP_HAL	/* y: legacy api is defined */
#include <mach/mtk_pmic_wrap.h>
#endif
#endif
#ifdef CONFIG_MTK_PMIC_WRAP
#include <linux/soc/mediatek/pmic_wrap.h>
#endif
#include <sound/tlv.h>

#include "mt6389.h"

enum {
	AUDIO_ANALOG_VOLUME_HSOUTL,
	AUDIO_ANALOG_VOLUME_HSOUTR,
	AUDIO_ANALOG_VOLUME_HPOUTL,
	AUDIO_ANALOG_VOLUME_HPOUTR,
	AUDIO_ANALOG_VOLUME_LINEOUTL,
	AUDIO_ANALOG_VOLUME_LINEOUTR,
	AUDIO_ANALOG_VOLUME_MICAMP1,
	AUDIO_ANALOG_VOLUME_MICAMP2,
	AUDIO_ANALOG_VOLUME_TYPE_MAX
};

enum {
	MUX_ADC_L,
	MUX_ADC_R,
	MUX_PGA_L,
	MUX_PGA_R,
	MUX_MIC_TYPE,
	MUX_HP_L,
	MUX_HP_R,
	MUX_NUM,
};

enum {
	DEVICE_HP,
	DEVICE_LO,
	DEVICE_RCV,
	DEVICE_MIC1,
	DEVICE_MIC2,
	DEVICE_NUM
};

/* Supply widget subseq */
enum {
	/* common */
	SUPPLY_SEQ_LDO_VAUD28,
	SUPPLY_SEQ_AUD_GLB,
	SUPPLY_SEQ_CLK_BUF,
	SUPPLY_SEQ_CLKSQ,
	SUPPLY_SEQ_VOW_AUD_LPW,
	SUPPLY_SEQ_AUD_VOW,
	SUPPLY_SEQ_VOW_CLK,
	SUPPLY_SEQ_VOW_LDO,
	SUPPLY_SEQ_TOP_CK,
	SUPPLY_SEQ_TOP_CK_LAST,
	SUPPLY_SEQ_AUD_TOP,
	SUPPLY_SEQ_AUD_TOP_LAST,
	SUPPLY_SEQ_AFE,
	/* capture */
	SUPPLY_SEQ_ADC_SUPPLY,
};

enum {
	CH_L = 0,
	CH_R,
	NUM_CH,
};

#define REG_STRIDE 2

struct mt6389_priv {
	struct device *dev;
	struct regmap *regmap;

	unsigned int dl_rate;
	unsigned int ul_rate;

	int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
	unsigned int mux_select[MUX_NUM];

	int dev_counter[DEVICE_NUM];

	struct mt6389_codec_ops ops;
	int mtkaif_protocol;

	struct dentry *debugfs;	// TODO: remove
	unsigned int debug_flag;
};

int mt6389_set_codec_ops(struct snd_soc_component *cmpnt,
			 struct mt6389_codec_ops *ops)
{
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	priv->ops.enable_dc_compensation = ops->enable_dc_compensation;
	priv->ops.set_lch_dc_compensation = ops->set_lch_dc_compensation;
	priv->ops.set_rch_dc_compensation = ops->set_rch_dc_compensation;
	priv->ops.adda_dl_gain_control = ops->adda_dl_gain_control;
	return 0;
}
int mt6389_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
			       int mtkaif_protocol)
{
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	priv->mtkaif_protocol = mtkaif_protocol;
	return 0;
}

static void gpio_smt_set(struct mt6389_priv *priv)
{
	/* set gpio SMT mode */
	regmap_update_bits(priv->regmap, MT6389_SMT_CON1,
			   0x3ff0, 0x3ff0);
}

static void playback_gpio_set(struct mt6389_priv *priv)
{
	/* set gpio mosi mode */
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_CLR,
			   0x01f8, 0x01f8);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_SET,
			   0xffff, 0x0249);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2,
			   0xffff, 0x0249);
}

static void playback_gpio_reset(struct mt6389_priv *priv)
{
	/* set pad_aud_*_mosi to GPIO mode and dir input
	 * reason:
	 * pad_aud_dat_mosi*, because the pin is used as boot strap
	 * don't clean clk/sync, for mtkaif protocol 2
	 */
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_CLR,
			   0x01f8, 0x01f8);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2,
			   0x01f8, 0x0000);
	regmap_update_bits(priv->regmap, MT6389_GPIO_DIR0,
			   0xf << 8, 0x0);
}

static void capture_gpio_set(struct mt6389_priv *priv)
{
	/* set gpio miso mode */
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_CLR,
			   0xffff, 0xffff);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_SET,
			   0xffff, 0x0249);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3,
			   0xffff, 0x0249);
}

static void capture_gpio_reset(struct mt6389_priv *priv)
{
	/* set pad_aud_*_miso to GPIO mode and dir input
	 * reason:
	 * pad_aud_clk_miso, because when playback only the miso_clk
	 * will also have 26m, so will have power leak
	 * pad_aud_dat_miso*, because the pin is used as boot strap
	 */
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_CLR,
			   0xffff, 0xffff);
	regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3,
			   0xffff, 0x0000);
	regmap_update_bits(priv->regmap, MT6389_GPIO_DIR0,
			   0xf << 12, 0x0);
}

/* use only when not govern by DAPM */
static int mt6389_set_dcxo(struct mt6389_priv *priv, bool enable)
{
	regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
			   0x1 << RG_XO_AUDIO_EN_M_SFT,
			   (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
	return 0;
}

/* use only when not govern by DAPM */
static int mt6389_set_clksq(struct mt6389_priv *priv, bool enable)
{
	/* Enable/disable CLKSQ 26MHz */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_IN_SEL_MASK_SFT,
				0 << RG_CLKSQ_IN_SEL_SFT);
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_EN_MASK_SFT,
				enable << RG_CLKSQ_EN_SFT);

	return 0;
}

/* use only when not govern by DAPM */
static int mt6389_set_aud_global_bias(struct mt6389_priv *priv, bool enable)
{
	regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
			   RG_AUDGLB_PWRDN_VA28_MASK_SFT,
			   (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
	return 0;
}

/* use only when not govern by DAPM */
static int mt6389_set_topck(struct mt6389_priv *priv, bool enable)
{
	regmap_update_bits(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0,
			   0x0066, enable ? 0x0 : 0x66);
	return 0;
}

static int mt6389_mtkaif_tx_enable(struct mt6389_priv *priv)
{
	switch (priv->mtkaif_protocol) {
	case MT6389_MTKAIF_PROTOCOL_2_CLK_P2:
		/* MTKAIF TX format setting */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_ADDA_MTKAIF_CFG0,
				   0xffff, 0x0010);
		/* enable aud_pad TX fifos */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0xff00, 0x3800);
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0xff00, 0x3900);
		break;
	case MT6389_MTKAIF_PROTOCOL_2:
		/* MTKAIF TX format setting */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_ADDA_MTKAIF_CFG0,
				   0xffff, 0x0010);
		/* enable aud_pad TX fifos */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0xff00, 0x3100);
		break;
	case MT6389_MTKAIF_PROTOCOL_1:
	default:
		/* MTKAIF TX format setting */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_ADDA_MTKAIF_CFG0,
				   0xff00, 0x0000);
		/* enable aud_pad TX fifos */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0xff00, 0x3100);
		break;
	}
	return 0;
}

static int mt6389_mtkaif_tx_disable(struct mt6389_priv *priv)
{
	/* disable aud_pad TX fifos */
	regmap_update_bits(priv->regmap, MT6389_AFE_AUD_PAD_TOP,
			   0xff00, 0x3000);
	return 0;
}

int mt6389_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
{
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	playback_gpio_set(priv);
	capture_gpio_set(priv);
	mt6389_mtkaif_tx_enable(priv);

	mt6389_set_dcxo(priv, true);
	mt6389_set_aud_global_bias(priv, true);
	mt6389_set_clksq(priv, true);
	mt6389_set_topck(priv, true);
	/* no use in Mt6389 */
	return 0;
}

int mt6389_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
{
	/* no use in Mt6389 */
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	mt6389_set_topck(priv, false);
	mt6389_set_clksq(priv, false);
	mt6389_set_aud_global_bias(priv, false);
	mt6389_set_dcxo(priv, false);

	mt6389_mtkaif_tx_disable(priv);
	playback_gpio_reset(priv);
	capture_gpio_reset(priv);
	return 0;
}

/* dl pga gain */
enum {
	DL_GAIN_8DB = 0,
	DL_GAIN_0DB = 8,
	DL_GAIN_N_1DB = 9,
	DL_GAIN_N_10DB = 18,
	DL_GAIN_N_40DB = 0x1f,
};
#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
#define DL_GAIN_REG_MASK 0x0f9f

/* reg idx for -40dB*/
#define PGA_MINUS_40_DB_REG_VAL 0x1f
#define HP_PGA_MINUS_40_DB_REG_VAL 0x3f
static const char *const dl_pga_gain[] = {
	"8Db", "7Db", "6Db", "5Db", "4Db",
	"3Db", "2Db", "1Db", "0Db", "-1Db",
	"-2Db", "-3Db",	"-4Db", "-5Db", "-6Db",
	"-7Db", "-8Db", "-9Db", "-10Db", "-40Db"
};

static void hp_zcd_disable(struct mt6389_priv *priv)
{
	regmap_write(priv->regmap, MT6389_ZCD_CON0, 0x0000);
}

static int dl_pga_get(struct snd_kcontrol *kcontrol,
		      struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int id = kcontrol->id.device;
	int array_size, reg_minus_40db;

	array_size = ARRAY_SIZE(dl_pga_gain);
	reg_minus_40db = PGA_MINUS_40_DB_REG_VAL;

	ucontrol->value.integer.value[0] = priv->ana_gain[id];

	if (ucontrol->value.integer.value[0] == reg_minus_40db)
		ucontrol->value.integer.value[0] = array_size - 1;

	return 0;
}

static int dl_pga_set(struct snd_kcontrol *kcontrol,
		      struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	int index = ucontrol->value.integer.value[0];
	unsigned int id = kcontrol->id.device;
	int array_size, reg_minus_40db;

	dev_info(priv->dev, "%s(), id %d, index %d\n", __func__, id, index);

	array_size = ARRAY_SIZE(dl_pga_gain);
	reg_minus_40db = PGA_MINUS_40_DB_REG_VAL;

	if (index >= array_size) {
		dev_warn(priv->dev, "return -EINVAL\n");
		return -EINVAL;
	}

	if (index == (array_size - 1))
		index = reg_minus_40db;	/* reg idx for -40dB*/

	switch (id) {
	case AUDIO_ANALOG_VOLUME_HPOUTL:
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON2,
				   RG_AUDHPLGAIN_MASK_SFT,
				   index << RG_AUDHPLGAIN_SFT);
		break;
	case AUDIO_ANALOG_VOLUME_HPOUTR:
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON2,
				   RG_AUDHPRGAIN_MASK_SFT,
				   index << RG_AUDHPRGAIN_SFT);
		break;
	case AUDIO_ANALOG_VOLUME_HSOUTL:
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
				   RG_AUDHSGAIN_MASK_SFT,
				   index << RG_AUDHSGAIN_SFT);
		break;
	case AUDIO_ANALOG_VOLUME_LINEOUTL:
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
				   RG_AUDLOLGAIN_MASK_SFT,
				   index << RG_AUDLOLGAIN_SFT);
		break;
	case AUDIO_ANALOG_VOLUME_LINEOUTR:
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
				   RG_AUDLORGAIN_MASK_SFT,
				   index << RG_AUDLORGAIN_SFT);
		break;
	default:
		return 0;
	}

	priv->ana_gain[id] = index;
	return 0;
}

static const struct soc_enum dl_pga_enum[] = {
	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dl_pga_gain), dl_pga_gain),
};

#define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
	.info = snd_soc_info_enum_double, \
	.get = xhandler_get, .put = xhandler_put, \
	.private_value = (unsigned long)&xenum }

static const struct snd_kcontrol_new mt6389_snd_controls[] = {
	MT_SOC_ENUM_EXT_ID("Headset_PGAL_GAIN", dl_pga_enum[0],
			   dl_pga_get, dl_pga_set,
			   AUDIO_ANALOG_VOLUME_HPOUTL),
	MT_SOC_ENUM_EXT_ID("Headset_PGAR_GAIN", dl_pga_enum[0],
			   dl_pga_get, dl_pga_set,
			   AUDIO_ANALOG_VOLUME_HPOUTR),
	MT_SOC_ENUM_EXT_ID("Handset_PGA_GAIN", dl_pga_enum[0],
			   dl_pga_get, dl_pga_set,
			   AUDIO_ANALOG_VOLUME_HSOUTL),
	MT_SOC_ENUM_EXT_ID("Lineout_PGAL_GAIN", dl_pga_enum[0],
			   dl_pga_get, dl_pga_set,
			   AUDIO_ANALOG_VOLUME_LINEOUTL),
	MT_SOC_ENUM_EXT_ID("Lineout_PGAR_GAIN", dl_pga_enum[0],
			   dl_pga_get, dl_pga_set,
			   AUDIO_ANALOG_VOLUME_LINEOUTR),
};

/* ul pga gain */
static const char *const ul_pga_gain[] = {
	"0Db", "6Db", "12Db", "18Db", "24Db"
};

static const struct soc_enum ul_pga_enum[] = {
	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ul_pga_gain), ul_pga_gain),
};

static int ul_pga_get(struct snd_kcontrol *kcontrol,
		      struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	ucontrol->value.integer.value[0] =
		priv->ana_gain[kcontrol->id.device];
	return 0;
}

static int ul_pga_set(struct snd_kcontrol *kcontrol,
		      struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	int index = ucontrol->value.integer.value[0];
	unsigned int id = kcontrol->id.device;

	dev_info(priv->dev, "%s(), id %d, index %d\n", __func__, id, index);
	if (index > ARRAY_SIZE(ul_pga_gain)) {
		dev_warn(priv->dev, "return -EINVAL\n");
		return -EINVAL;
	}

	switch (id) {
	case AUDIO_ANALOG_VOLUME_MICAMP1:
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   RG_AUDPREAMPLGAIN_MASK_SFT,
				   index << RG_AUDPREAMPLGAIN_SFT);
		break;
	case AUDIO_ANALOG_VOLUME_MICAMP2:
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   RG_AUDPREAMPRGAIN_MASK_SFT,
				   index << RG_AUDPREAMPRGAIN_SFT);
		break;
	default:
		return 0;
	}

	priv->ana_gain[id] = index;
	return 0;
}

static const struct snd_kcontrol_new mt6389_snd_ul_controls[] = {
	MT_SOC_ENUM_EXT_ID("Audio_PGA1_Setting", ul_pga_enum[0],
			   ul_pga_get, ul_pga_set,
			   AUDIO_ANALOG_VOLUME_MICAMP1),
	MT_SOC_ENUM_EXT_ID("Audio_PGA2_Setting", ul_pga_enum[0],
			   ul_pga_get, ul_pga_set,
			   AUDIO_ANALOG_VOLUME_MICAMP2),
};
/* MUX */
/* LOL MUX */
static const char * const lo_in_mux_map[] = {
	"Open", "Mute", "Playback", "Test Mode"
};

static int lo_in_mux_map_value[] = {
	0x0, 0x1, 0x2, 0x3,
};

static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
				  MT6389_AUDDEC_ANA_CON5,
				  RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
				  RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
				  lo_in_mux_map,
				  lo_in_mux_map_value);

static const struct snd_kcontrol_new lo_in_mux_control =
	SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);

/*HP MUX */
enum {
	HP_MUX_OPEN = 0,
	HP_MUX_HPSPK,
	HP_MUX_HP,
	HP_MUX_TEST_MODE,
	HP_MUX_HP_IMPEDANCE,
	HP_MUX_MASK = 0x7,
};

static const char * const hp_in_mux_map[] = {
	"Open",
	"LoudSPK Playback",
	"Audio Playback",
	"Test Mode",
	"HP Impedance",
	"undefined1",
	"undefined2",
	"undefined3",
};

static int hp_in_mux_map_value[] = {
	HP_MUX_OPEN,
	HP_MUX_HPSPK,
	HP_MUX_HP,
	HP_MUX_TEST_MODE,
	HP_MUX_HP_IMPEDANCE,
	HP_MUX_OPEN,
	HP_MUX_OPEN,
	HP_MUX_OPEN,
};

static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  HP_MUX_MASK,
				  hp_in_mux_map,
				  hp_in_mux_map_value);

static const struct snd_kcontrol_new hpl_in_mux_control =
	SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);

static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  HP_MUX_MASK,
				  hp_in_mux_map,
				  hp_in_mux_map_value);

static const struct snd_kcontrol_new hpr_in_mux_control =
	SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);

/* RCV MUX */
enum {
	RCV_MUX_OPEN = 0,
	RCV_MUX_MUTE,
	RCV_MUX_VOICE_PLAYBACK,
	RCV_MUX_TEST_MODE,
	RCV_MUX_MASK = 0x3,
};

static const char * const rcv_in_mux_map[] = {
	"Open", "Mute", "Voice Playback", "Test Mode"
};

static int rcv_in_mux_map_value[] = {
	RCV_MUX_OPEN,
	RCV_MUX_MUTE,
	RCV_MUX_VOICE_PLAYBACK,
	RCV_MUX_TEST_MODE,
};

static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  RCV_MUX_MASK,
				  rcv_in_mux_map,
				  rcv_in_mux_map_value);

static const struct snd_kcontrol_new rcv_in_mux_control =
	SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);

/* Direct MUX */
enum {
	DIR_MUX_OPEN = 0,
	DIR_MUX_MUTE,
	DIR_MUX_PLAYBACK,
	DIR_MUX_TEST_MODE,
	DIR_MUX_MASK = 0x3,
};

static const char * const direct_in_mux_map[] = {
	"Open", "Mute", "Playback", "Test Mode"
};

static int direct_in_mux_map_value[] = {
	DIR_MUX_OPEN,
	DIR_MUX_MUTE,
	DIR_MUX_PLAYBACK,
	DIR_MUX_TEST_MODE,
};

static SOC_VALUE_ENUM_SINGLE_DECL(direct_in_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  DIR_MUX_MASK,
				  direct_in_mux_map,
				  direct_in_mux_map_value);

static const struct snd_kcontrol_new direct_in_mux_control =
	SOC_DAPM_ENUM("DIRECT Select", direct_in_mux_map_enum);

/* Direct_lo MUX */
enum {
	DIR_LO_MUX_OPEN = 0,
	DIR_LO_MUX_MUTE,
	DIR_LO_MUX_PLAYBACK,
	DIR_LO_MUX_TEST_MODE,
	DIR_LO_MUX_MASK = 0x3,
};

static const char * const direct_lo_in_mux_map[] = {
	"Open", "Mute", "Playback", "Test Mode"
};

static int direct_lo_in_mux_map_value[] = {
	DIR_LO_MUX_OPEN,
	DIR_LO_MUX_MUTE,
	DIR_LO_MUX_PLAYBACK,
	DIR_LO_MUX_TEST_MODE,
};

static SOC_VALUE_ENUM_SINGLE_DECL(direct_lo_in_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  DIR_LO_MUX_MASK,
				  direct_lo_in_mux_map,
				  direct_lo_in_mux_map_value);

static const struct snd_kcontrol_new direct_lo_in_mux_control =
	SOC_DAPM_ENUM("DIRECT_LO Select", direct_lo_in_mux_map_enum);

/* DAC In MUX */
static const char * const dac_in_mux_map[] = {
	"Normal Path", "Sgen"
};

static int dac_in_mux_map_value[] = {
	0x0, 0x1,
};

static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
				  MT6389_AFE_TOP_CON0,
				  DL_SINE_ON_SFT,
				  DL_SINE_ON_MASK,
				  dac_in_mux_map,
				  dac_in_mux_map_value);

static const struct snd_kcontrol_new dac_in_mux_control =
	SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);

/* AIF Out MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
				  MT6389_AFE_TOP_CON0,
				  UL_SINE_ON_SFT,
				  UL_SINE_ON_MASK,
				  dac_in_mux_map,
				  dac_in_mux_map_value);

static const struct snd_kcontrol_new aif_out_mux_control =
	SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);

/* Mic Type MUX */
enum {
	MIC_TYPE_MUX_IDLE = 0,
	MIC_TYPE_MUX_ACC,
	MIC_TYPE_MUX_DMIC,
	MIC_TYPE_MUX_DCC,
	MIC_TYPE_MUX_DCC_ECM_DIFF,
	MIC_TYPE_MUX_DCC_ECM_SINGLE,
	MIC_TYPE_MUX_ACCDIFF,
	MIC_TYPE_MUX_MASK = 0x7,
};

#define IS_DCC_BASE(x) (x == MIC_TYPE_MUX_DCC || \
			x == MIC_TYPE_MUX_DCC_ECM_DIFF || \
			x == MIC_TYPE_MUX_DCC_ECM_SINGLE)

static const char * const mic_type_mux_map[] = {
	"Idle",
	"ACC",
	"DMIC",
	"DCC",
	"DCC_ECM_DIFF",
	"DCC_ECM_SINGLE",
	"ACCDIFF",
};

static int mic_type_mux_map_value[] = {
	MIC_TYPE_MUX_IDLE,
	MIC_TYPE_MUX_ACC,
	MIC_TYPE_MUX_DMIC,
	MIC_TYPE_MUX_DCC,
	MIC_TYPE_MUX_DCC_ECM_DIFF,
	MIC_TYPE_MUX_DCC_ECM_SINGLE,
	MIC_TYPE_MUX_ACCDIFF,
};

static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  MIC_TYPE_MUX_MASK,
				  mic_type_mux_map,
				  mic_type_mux_map_value);

static const struct snd_kcontrol_new mic_type_mux_control =
	SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);

/* ADC L MUX */
enum {
	ADC_MUX_IDLE = 0,
	ADC_MUX_AIN0,
	ADC_MUX_PREAMPLIFIER,
	ADC_MUX_IDLE1,
	ADC_MUX_MASK = 0x3,
};

static const char * const adc_left_mux_map[] = {
	"Idle", "AIN0", "Left Preamplifier", "Idle_1"
};

static int adc_mux_map_value[] = {
	ADC_MUX_IDLE,
	ADC_MUX_AIN0,
	ADC_MUX_PREAMPLIFIER,
	ADC_MUX_IDLE1,
};

static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  ADC_MUX_MASK,
				  adc_left_mux_map,
				  adc_mux_map_value);

static const struct snd_kcontrol_new adc_left_mux_control =
	SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);

/* ADC R MUX */
static const char * const adc_right_mux_map[] = {
	"Idle", "AIN0", "Right Preamplifier", "Idle_1"
};

static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  ADC_MUX_MASK,
				  adc_right_mux_map,
				  adc_mux_map_value);

static const struct snd_kcontrol_new adc_right_mux_control =
	SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);

/* PGA L MUX */
enum {
	PGA_MUX_NONE = 0,
	PGA_MUX_AIN0,
	PGA_MUX_AIN1,
	PGA_MUX_AIN2,
	PGA_MUX_MASK = 0x3,
};

static const char * const pga_mux_map[] = {
	"None", "AIN0", "AIN1", "AIN2"
};

static int pga_mux_map_value[] = {
	PGA_MUX_NONE,
	PGA_MUX_AIN0,
	PGA_MUX_AIN1,
	PGA_MUX_AIN2,
};

static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  PGA_MUX_MASK,
				  pga_mux_map,
				  pga_mux_map_value);

static const struct snd_kcontrol_new pga_left_mux_control =
	SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);

/* PGA R MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
				  SND_SOC_NOPM,
				  0,
				  PGA_MUX_MASK,
				  pga_mux_map,
				  pga_mux_map_value);

static const struct snd_kcontrol_new pga_right_mux_control =
	SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);

static int mt_clksq_event(struct snd_soc_dapm_widget *w,
			  struct snd_kcontrol *kcontrol,
			  int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int value;

	dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);

	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_IN_SEL_MASK_SFT,
				0 << RG_CLKSQ_IN_SEL_SFT);

	switch (event) {
	case SND_SOC_DAPM_POST_PMU:
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
			   RG_CLKSQ_EN_MASK_SFT,
			   1 << RG_CLKSQ_EN_SFT);
		break;
	case SND_SOC_DAPM_PRE_PMD:
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
			   RG_CLKSQ_EN_MASK_SFT,
			   0 << RG_CLKSQ_EN_SFT);
		break;
	default:
		break;
	}
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);

	dev_info(priv->dev, "%s(), MT6389_AUDENC_ANA_CON5 = 0x%x\n",
			 __func__, value);

	return 0;
}

static int mt_sgen_event(struct snd_soc_dapm_widget *w,
			 struct snd_kcontrol *kcontrol,
			 int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* sdm audio fifo clock power on */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0006);
		/* scrambler clock on enable */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xCBA1);
		/* sdm power on */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0003);
		/* sdm fifo enable */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x000B);

		regmap_update_bits(priv->regmap, MT6389_AFE_SGEN_CFG0,
				   0xff3f,
				   0x0000);
		regmap_update_bits(priv->regmap, MT6389_AFE_SGEN_CFG1,
				   0xffff,
				   0x0001);
		break;
	case SND_SOC_DAPM_POST_PMD:
		/* DL scrambler disabling sequence */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0000);
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xcba0);
		break;
	default:
		break;
	}

	return 0;
}

static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
			   struct snd_kcontrol *kcontrol,
			   int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
		 __func__, event, priv->dl_rate);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		playback_gpio_set(priv);
		/* enable aud_pad TX fifos */
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0x00ff, 0x0031);
		/* sdm audio fifo clock power on */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0006);
		/* scrambler clock on enable */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xCBA1);
		/* sdm power on */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0003);
		/* sdm fifo enable */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x000B);
		break;
	case SND_SOC_DAPM_POST_PMD:
		/* DL scrambler disabling sequence */
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0000);
		regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xcba0);
		regmap_update_bits(priv->regmap,
				   MT6389_AFE_AUD_PAD_TOP,
				   0x00ff, 0x0000);
		playback_gpio_reset(priv);
		break;
	default:
		break;
	}

	return 0;
}

static int mtk_hp_enable(struct mt6389_priv *priv)
{
	/* mt6389 not support HP path */
	return 0;
}

static int mtk_hp_disable(struct mt6389_priv *priv)
{
	/* mt6389 not support HP path */
	return 0;
}

static int mtk_hp_spk_enable(struct mt6389_priv *priv)
{
	/* mt6389 not support HP path */
	return 0;
}


static int mtk_hp_spk_disable(struct mt6389_priv *priv)
{
	/* mt6389 not support HP path */
	return 0;
}

static int mt_hp_event(struct snd_soc_dapm_widget *w,
		       struct snd_kcontrol *kcontrol,
		       int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
	int device = DEVICE_HP;

	dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
		 __func__,
		 event,
		 priv->dev_counter[device],
		 mux);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		priv->dev_counter[device]++;
		if (priv->dev_counter[device] > 1)
			break;	/* already enabled, do nothing */
		else if (priv->dev_counter[device] <= 0)
			dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
				 __func__,
				 priv->dev_counter[device]);

		priv->mux_select[MUX_HP_L] = mux;

		if (mux == HP_MUX_HP)
			mtk_hp_enable(priv);
		else if (mux == HP_MUX_HPSPK)
			mtk_hp_spk_enable(priv);
		break;
	case SND_SOC_DAPM_PRE_PMD:
		priv->dev_counter[device]--;
		if (priv->dev_counter[device] > 0) {
			break;	/* still being used, don't close */
		} else if (priv->dev_counter[device] < 0) {
			dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
				 __func__,
				 priv->dev_counter[device]);
			priv->dev_counter[device] = 0;
			break;
		}

		if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
			mtk_hp_disable(priv);
		else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
			mtk_hp_spk_disable(priv);

		priv->mux_select[MUX_HP_L] = mux;
		break;
	default:
		break;
	}

	return 0;
}

static void set_speaker_gain(struct mt6389_priv *priv, int spk_gain)
{
	dev_info(priv->dev, "%s(), spk_gain = %d\n", __func__, spk_gain);
	regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
			DL_GAIN_REG_MASK, (spk_gain << 7) | spk_gain);
}

static int mt_lo_event(struct snd_soc_dapm_widget *w,
			struct snd_kcontrol *kcontrol,
			int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
		 __func__,
		 event,
		 dapm_kcontrol_get_value(w->kcontrols[0]));

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* reset LOL output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 10, 0x1 << 10);
		/* reset HS output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 10, 0x1 << 10);
		/* Reduce ESD resistance of AU_REFN */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON2, 0x4000);
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0x10, 0x10);
		/* Turn on DA_600K_NCP_VA18 */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
		/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
		/* Toggle RG_DIVCKS_CHG */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
		/* Set NCP soft start mode as default mode: 100us */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
		/* Enable NCP */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
		usleep_range(250, 270);

		/* Enable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
					0x1055, 0x1055);
		/* Enable NV regulator (-1.2V) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
		usleep_range(100, 120);

		/* Disable AUD_ZCD */
		hp_zcd_disable(priv);

		/* Disable lineout short-ckt protection */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 4, 0x1 << 4);
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 4, 0x1 << 4);

		/* Enable IBIST */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
		/* Set HP DR bias current optimization, 010: 6uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
		/* Set HP & ZCD bias current optimization */
		/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);

		/* Set HS STB enhance circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 7, 0x1 << 7);

		/* Set LO STB enhance circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 8, 0x1 << 8);

		/* Release HS output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 10, 0x0 << 10);
		/* Release LOL output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 10, 0x0 << 10);

		/* Enable HS/LOL CMFB circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0xC000);

		/* Select CMFB resistor bulk to AC mode */
		/* Selec HS/LO cap size (6.5pF default) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);

		/* Enable HS/LOL offset trim circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
					0x3fc0, 0x2040);

		/* Set OUT2 output select HS amp (100)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x7000, 0x4000);
		/* Set OUT1 output select LOL amp (011)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x0700, 0x0300);

		/* Enable HS driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 1, 0x1 << 1);

		/* Enable HS driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1, 0x1);

		/* Enable LO driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 1, 0x1 << 1);
		/* Enable LO driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1, 0x1);

		/* Set HS gain to normal gain step by step */
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
				   RG_AUDHSGAIN_MASK_SFT,
				   priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] <<
				   RG_AUDHSGAIN_SFT);
		/* Set LO gain to normal gain step by step */
		set_speaker_gain(priv,
				 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);

		/* Enable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
					0x1, 0x1);

		/* Enable Audio DACL/R  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x000f, 0x000f);
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
	    /* Switch HS MUX to audio DAC L */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x3 << 2, 0x1 << 2);
	    /* Switch LOL MUX to audio DAC R*/
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x3 << 2, 0x2 << 2);

		break;
	case SND_SOC_DAPM_PRE_PMD:
		/* Switch HS MUX to open */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				   0x3 << 2, 0x0 << 2);

		/* Switch LOL MUX to open */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
				   0x3 << 2, 0x0 << 2);

		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);

		/* Disable Audio DAC */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
				   0x000f, 0x0000);

		/* Disable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1, 0x0);

		/* decrease HS gain to minimum gain step by step */
		regmap_write(priv->regmap, MT6389_ZCD_CON3,
			     DL_GAIN_N_40DB_REG);

		/* decrease LO gain to minimum gain step by step */
		regmap_write(priv->regmap, MT6389_ZCD_CON1,
			     DL_GAIN_N_40DB_REG);

		/* Disable HS driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				   0x1, 0x0);
		/* Disable LO driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
				   0x1 << 1, 0x0 << 1);

		/* Disable HS driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				   0x1 << 1, 0x0 << 1);

		/* Disable LO driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
				   0x1, 0x0);
		/* Disable HS STB enhance circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 7, 0x0 << 7);

		/* Disable LO STB enhance circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 8, 0x0 << 8);

		/* Disable LOL offset trim circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
				   0x3f80, 0x0000);

		/* Disable LOL CMFB circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
				   0xff00, 0x0000);
		/* reset LOL output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 10, 0x1 << 10);
		/* reset HS output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					0x1 << 10, 0x1 << 10);

		/* Reset OUT1 output select none */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
				   0x0700, 0x0000);
		/* Reset OUT2 output select none */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
				   0x7000, 0x0000);

		/* Disable IBIST */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
				   0x1 << 8, 0x1 << 8);
		/* Release ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0x10, 0x0);

		/* Disable NV regulator (-1.2V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
				   0x1, 0x0);
		/* Disable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x1055, 0x0);
		/* Disable NCP */
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
				   0x1, 0x1);
		/* Turn off DA_600K_NCP_VA18 */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0);
		break;
	default:
		break;
	}
	return 0;
}

static int mt_rcv_event(struct snd_soc_dapm_widget *w,
			struct snd_kcontrol *kcontrol,
			int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
		 __func__,
		 event,
		 dapm_kcontrol_get_value(w->kcontrols[0]));

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* Reduce ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
						   0x10, 0x10);
		/* Turn on DA_600K_NCP_VA18 */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
		/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
		/* Toggle RG_DIVCKS_CHG */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
		/* Set NCP soft start mode as default mode: 100us */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
		/* Enable NCP */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
		usleep_range(250, 270);

		/* Enable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x1055, 0x1055);
		/* Enable NV regulator (-1.2V) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
		usleep_range(100, 120);

		/* Disable AUD_ZCD */
		hp_zcd_disable(priv);

		/* Disable handset short-circuit protection */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
						   0x1 << 4, 0x1 << 4);
		/* Enable IBIST */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
		/* Set HP DR bias current optimization, 010: 6uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
		/* Set HP & ZCD bias current optimization */
		/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
		/* Set HS STB enhance circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
						   0x1 << 7, 0x1 << 7);
		/* Enable HS CMFB circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x4000);

		/* Disable HP main CMFB loop */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);
		/* Select CMFB resistor bulk to AC mode */
		/* Selec HS/LO cap size (6.5pF default) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);

		/* Enable HS offset trim circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
					0x3f80, 0x0040);
		/* Set OUT2 output select HS amp (100)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x7000, 0x4000);

		/* Enable HS driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1 << 1, 0x1 << 1);

		/* Enable HS driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1, 0x1);

		/* Set HS gain to normal gain step by step */
		regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
				   RG_AUDHSGAIN_MASK_SFT,
				   priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] <<
				   RG_AUDHSGAIN_SFT);

		/* Enable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1, 0x1);
		/* Enable Audio DACL  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x0009, 0x0009);

		/* Enable low-noise mode of DAC */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
		/* Switch HS MUX to audio DACL */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x3 << 2, 0x2 << 2);

		break;
	case SND_SOC_DAPM_PRE_PMD:
		/* HS mux to open */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				    RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
				    RCV_MUX_OPEN);

		/* Disable Audio DAC */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
				   0x000f, 0x0000);

		/* Disable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1, 0x0);

		/* decrease HS gain to minimum gain step by step */
		regmap_write(priv->regmap, MT6389_ZCD_CON3, DL_GAIN_N_40DB);

		/* Disable HS driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				   0x1, 0x0);

		/* Disable HS driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				   0x1 << 1, 0x0 << 1);


		/* Disable HP aux CMFB loop */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON7,
				   0xff << 8, 0x0);

		/* Enable HP main CMFB Switch */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON7,
				   0xff << 8, 0x2 << 8);

		/* Disable IBIST */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
				   0x1 << 8, 0x1 << 8);

		/* Disable NV regulator (-1.2V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
				   0x1, 0x0);
		/* Disable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x1055, 0x0);
		/* Disable NCP */
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
				   0x1, 0x1);
		break;
	default:
		break;
	}

	return 0;
}

static int mt_direct_event(struct snd_soc_dapm_widget *w,
			struct snd_kcontrol *kcontrol,
			int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
		 __func__,
		 event,
		 dapm_kcontrol_get_value(w->kcontrols[0]));

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* Reduce ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0x10, 0x10);
		/* Turn on DA_600K_NCP_VA18 */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
		/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
		/* Toggle RG_DIVCKS_CHG */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
		/* Set NCP soft start mode as default mode: 100us */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
		/* Enable NCP */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
		usleep_range(250, 270);

		/* Enable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
					0x1055, 0x1055);
		usleep_range(100, 120);

		/* Enable VCM buffer */
		/* Set VCM output level = 0.75V */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
				   0x0071, 0x0041);

		/* Set LO gain to normal gain step by step */
		set_speaker_gain(priv,
				 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);

		/* Set LOL input reset for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
					0x1 << RG_LOINPUTRESET0_VAUDP15_SFT);
		/* Disable LO STB enhance circuits for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
					0x0 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);

		/* Set OUT0 output select UL VIN0 (001)  */
		/* Set OUT1 output select UL VIN1 (010)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x0770, 0x0210);

		/* Pre-charge VIN0&VIN1 input cap (1uF) to VCM */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0xf);
		/* Pre-charge OUT0&OUT1 output cap (1uF) to VCM with 2Kohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0x33);
		/* OUT0&OUT1 ADP SW change to source-tied */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x0300);
		/* Precharge settle time 100ms */
		usleep_range(100, 120);

		/* Enable OUT0/1 to VCM path SW with 50K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
				   0x0f00, 0x0f00);
		/* Disable Pre-charge VIN0&VIN1 input */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0x0);
		/* Disable pre-charge OUT0&OUT1 output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0x0);
		break;
	case SND_SOC_DAPM_PRE_PMD:

		/* Disable ADP source-tied, disable HS&LO CMFB path */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x0000);

		/* Disable OUT0/1 to VCM path SW with 50K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
					0x0f00, 0x0000);
		/* VIN0&VIN1 to VCM path SW */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0x0);
		/* OUT0&OUT1&VIN0&VIN1 discharge to AVSS with 2K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0xcc);
		/* Disable VCM buffer */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
					RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT,
					0x0 << RG_AUDVCMBUF_EN_VAUDP28_SFT);
		/* Discharge settle time 100ms */
		usleep_range(100, 120);

		/* Disable pre-charge OUT0&OUT1 output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0xcc);
		/* Set OUT0/1/2 output select open (000)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x7770, 0x0000);

		/* Release LOL input reset */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
					0x0 << RG_LOINPUTRESET0_VAUDP15_SFT);
		/* Disable LO STB enhance circuits for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
					0x1 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);

		/* Disable IBIST */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
				   RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT,
				   0x1 << RG_AUDIBIASPWRDN_VAUDP15_SFT);

		/* Release ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT,
					0x0 << RG_AUDREFN_DERES_EN_VAUDP28_SFT);

		/* Set LOL gain to mute */
		regmap_write(priv->regmap, MT6389_ZCD_CON1, DL_GAIN_N_40DB);

		/* Disable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
					0x1055, 0x0);
		/* Disable NCP */
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
					0x1, 0x1);

		/* Turn off DA_600K_NCP_VA18*/
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1,
					RG_DIVCKS_ON_MASK_SFT,
					0x0 << RG_DIVCKS_ON_SFT);

		break;
	default:
		break;
	}

	return 0;
}

static int mt_direct_lo_event(struct snd_soc_dapm_widget *w,
			struct snd_kcontrol *kcontrol,
			int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
		 __func__,
		 event,
		 dapm_kcontrol_get_value(w->kcontrols[0]));

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* Reduce ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0x10, 0x10);
		/* Turn on DA_600K_NCP_VA18 */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
		/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
		/* Toggle RG_DIVCKS_CHG */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
		/* Set NCP soft start mode as default mode: 100us */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
		/* Enable NCP */
		regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
		usleep_range(250, 270);

		/* Enable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
					0x1055, 0x1055);
		/* Enable NV regulator (-1.2V) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
		usleep_range(100, 120);

		/* Enable VCM buffer */
		/* Set VCM output level = 0.75V */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
				   0x0071, 0x0041);

		/* Disable AUD_ZCD */
		hp_zcd_disable(priv);

		/* Set LO gain to normal gain step by step */
		set_speaker_gain(priv,
				 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);

		/* Set LOL input reset for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
					0x1 << RG_LOINPUTRESET0_VAUDP15_SFT);
		/* Disable LO STB enhance circuits for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
					0x0 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);

		/* Set OUT0 output select UL VIN0 (001)  */
		/* Set OUT1 output select UL VIN1 (010)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x0770, 0x0210);

		/* Pre-charge VIN0&VIN1 input cap (1uF) to VCM */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0xf);
		/* Pre-charge OUT0&OUT1 output cap (1uF) to VCM with 2Kohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0x33);
		/* OUT0&OUT1 ADP SW change to source-tied */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x0300);
		/* Precharge settle time 100ms */
		usleep_range(100, 120);

		/* Enable OUT0/1 to VCM path SW with 50K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
				   0x0f00, 0x0f00);
		/* Disable Pre-charge VIN0&VIN1 input */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0x0);
		/* Disable pre-charge OUT0&OUT1 output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0x0);
		/* Disable handset short-ckt protection. */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x10, 0x10);

		/* Enable IBIST */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
		/* Set HP DR bias current optimization, 010: 6uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
		/* Set HP & ZCD bias current optimization */
		/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);

		/* Set HS STB enhance circuits */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0090);

		/* Enable HS CMFB circuit for normal operation */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x4300);

		/* Select CMFB resistor bulk to AC mode */
		/* Selec HS/LO cap size (6.5pF default) */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);


		/* Enable HS offset trim circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
					0x7f, 0x40);

		/* Set OUT2 output select HS amp (100)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x7000, 0x4000);
		/* Enable HS driver bias circuits */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0092);
		/* Enable HS driver core circuits */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0093);

		/* Set HS gain to normal gain step by step */
		regmap_write(priv->regmap, MT6389_ZCD_CON3,
			     priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);

		/* Enable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1, 0x1);

		/* Enable Audio DACL  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
				   0x9, 0x9);

		/* Enable low-noise mode of DAC */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
		/* Switch HS MUX to audio DAC */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x009b);

		break;
	case SND_SOC_DAPM_PRE_PMD:

		/* decrease HS gain to minimum gain step by step */
		regmap_write(priv->regmap, MT6389_ZCD_CON3, DL_GAIN_N_40DB);

		/* Disable AUD_ZCD */
		hp_zcd_disable(priv);

		/* HS mux to open */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
				    RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
				    RCV_MUX_OPEN);

		/* Enable low-noise mode of DAC */
		regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);

		/* Disable Audio DAC */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x9, 0x0);

		/* Disable AUD_CLK */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
					0x1, 0x0);

		/* Disable HS driver core circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x1, 0x0);

		/* Disable HS driver bias circuits */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x2, 0x0);

		/* Disable HS offset trim circuit */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
					0x7f, 0x0);

		/* Disable ADP source-tied, disable HS&LO CMFB path */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xff00, 0x0000);

		/* Disable handset short-ckt protection. */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
					0x400, 0x400);

		/* Release LOL input reset */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
					0x0 << RG_LOINPUTRESET0_VAUDP15_SFT);
		/* Disable LO STB enhance circuits for ADP mode */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
					RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
					0x1 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);

		/* Disable IBIST */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
				   RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT,
				   0x1 << RG_AUDIBIASPWRDN_VAUDP15_SFT);

		/* Release ESD resistance of AU_REFN */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT,
					0x0 << RG_AUDREFN_DERES_EN_VAUDP28_SFT);

		/* Disable OUT0/1 to VCM path SW with 50K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
					0x0f00, 0x0000);
		/* VIN0&VIN1 to VCM path SW */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
					0xf, 0x0);
		/* OUT0&OUT1&VIN0&VIN1 discharge to AVSS with 2K ohm */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0xcc);
		/* Disable VCM buffer */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
					RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT,
					0x0 << RG_AUDVCMBUF_EN_VAUDP28_SFT);
		/* Discharge settle time 100ms */
		usleep_range(100, 120);

		/* Disable pre-charge OUT0&OUT1 output */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
					0xff, 0xcc);
		/* Set OUT0/1/2 output select open (000)  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
					0x7770, 0x0000);

		/* Disable NV regulator (-1.2V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
					0x1, 0x0);
		/* Set LOL gain to mute */
		regmap_write(priv->regmap, MT6389_ZCD_CON1, DL_GAIN_N_40DB);

		/* Disable cap-less LDOs (1.5V) */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
					0x1055, 0x0);
		/* Disable NCP */
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
					0x1, 0x1);

		/* Turn off DA_600K_NCP_VA18*/
		regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1,
					RG_DIVCKS_ON_MASK_SFT,
					0x0 << RG_DIVCKS_ON_SFT);

		break;
	default:
		break;
	}

	return 0;
}

static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
			    struct snd_kcontrol *kcontrol,
			    int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
		__func__, event, priv->ul_rate);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		capture_gpio_set(priv);
		break;
	case SND_SOC_DAPM_POST_PMD:
		capture_gpio_reset(priv);
		break;
	default:
		break;
	}

	return 0;
}

static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
			       struct snd_kcontrol *kcontrol,
			       int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	dev_dbg(priv->dev, "%s(), event 0x%x\n",
		__func__, event);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* Enable audio ADC CLKGEN  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1 << 5, 0x1 << 5);
		/* ADC CLK from CLKGEN (13MHz) */
		regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON3,
			     0x0000);
		/* Enable  LCLDO_ENC 1P8V */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x2500, 0x0100);
		/* LCLDO_ENC remote sense */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x2500, 0x2500);
		break;
	case SND_SOC_DAPM_POST_PMD:
		/* LCLDO_ENC remote sense off */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x2500, 0x0100);
		/* disable LCLDO_ENC 1P8V */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
				   0x2500, 0x0000);

		/* ADC CLK from CLKGEN (13MHz) */
		regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON3, 0x0000);
		/* disable audio ADC CLKGEN  */
		regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
				   0x1 << 5, 0x0 << 5);
		break;
	default:
		break;
	}

	return 0;
}

static int mt6389_amic_enable(struct mt6389_priv *priv)
{
	unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
	unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
	unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
	int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
	int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];

	dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u, mic_gain l %d, r %d\n",
		 __func__, mic_type, mux_pga_l, mux_pga_r,
		 mic_gain_l, mic_gain_r);

	if (IS_DCC_BASE(mic_type)) {
		/* DCC 50k CLK (from 26M) */
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2060);
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2061);
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG1, 0x0100);
	}

	/* mic bias 0 */
	if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
	    mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
		switch (mic_type) {
		case MIC_TYPE_MUX_DCC_ECM_DIFF:
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
					   0xff00, 0x7700);
			break;
		case MIC_TYPE_MUX_DCC_ECM_SINGLE:
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
					   0xff00, 0x1100);
			break;
		default:
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
					   0xff00, 0x0000);
			break;
		}
		/* Enable MICBIAS0, MISBIAS0 = 1P9V */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
				   0xff, 0x21);
	}

	/* mic bias 1 */
	if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
		/* Enable MICBIAS1, MISBIAS1 = 2P6V */
		if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
			regmap_write(priv->regmap,
				     MT6389_AUDENC_ANA_CON10, 0x0161);
		else
			regmap_write(priv->regmap,
				     MT6389_AUDENC_ANA_CON10, 0x0061);
	}

	/* set mic pga gain */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
			   RG_AUDPREAMPLGAIN_MASK_SFT,
			   mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
			   RG_AUDPREAMPRGAIN_MASK_SFT,
			   mic_gain_r << RG_AUDPREAMPRGAIN_SFT);

	if (IS_DCC_BASE(mic_type)) {
		/* Audio L/R preamplifier DCC precharge */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   0xf8ff, 0x0004);
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   0xf8ff, 0x0004);
	} else {
		/* reset reg */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   0xf8ff, 0x0000);
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   0xf8ff, 0x0000);
	}

	if (mux_pga_l != PGA_MUX_NONE) {
		/* L preamplifier input sel */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   RG_AUDPREAMPLINPUTSEL_MASK_SFT,
				   mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);

		/* L preamplifier enable */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   RG_AUDPREAMPLON_MASK_SFT,
				   0x1 << RG_AUDPREAMPLON_SFT);

		if (IS_DCC_BASE(mic_type)) {
			/* L preamplifier DCCEN */
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
					   RG_AUDPREAMPLDCCEN_MASK_SFT,
					   0x1 << RG_AUDPREAMPLDCCEN_SFT);
		}

		/* L ADC input sel : L PGA. Enable audio L ADC */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   RG_AUDADCLINPUTSEL_MASK_SFT,
				   ADC_MUX_PREAMPLIFIER <<
				   RG_AUDADCLINPUTSEL_SFT);
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
				   RG_AUDADCLPWRUP_MASK_SFT,
				   0x1 << RG_AUDADCLPWRUP_SFT);

		if (mic_type == MIC_TYPE_MUX_ACC) {
			/* ACC single mode */
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
					   RG_AUDPREAMPLSE_MASK_SFT,
					   0x1 << RG_AUDPREAMPLSE_SFT);
		}
	}

	if (mux_pga_r != PGA_MUX_NONE) {
		/* R preamplifier input sel */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   RG_AUDPREAMPRINPUTSEL_MASK_SFT,
				   mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);

		/* R preamplifier enable */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   RG_AUDPREAMPRON_MASK_SFT,
				   0x1 << RG_AUDPREAMPRON_SFT);

		if (IS_DCC_BASE(mic_type)) {
			/* R preamplifier DCCEN */
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
					   RG_AUDPREAMPRDCCEN_MASK_SFT,
					   0x1 << RG_AUDPREAMPRDCCEN_SFT);
		}

		/* R ADC input sel : R PGA. Enable audio R ADC */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   RG_AUDADCRINPUTSEL_MASK_SFT,
				   ADC_MUX_PREAMPLIFIER <<
				   RG_AUDADCRINPUTSEL_SFT);
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
				   RG_AUDADCRPWRUP_MASK_SFT,
				   0x1 << RG_AUDADCRPWRUP_SFT);

		if (mic_type == MIC_TYPE_MUX_ACC) {
			/* ACC single mode */
			regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
					   RG_AUDPREAMPLSE_MASK_SFT,
					   0x1 << RG_AUDPREAMPLSE_SFT);
		}
	}

	if (IS_DCC_BASE(mic_type)) {
		usleep_range(100, 150);
		/* Short body to ground in PGA */
		regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON3,
				   0x1 << 12, 0x0);
	}

	/* here to set digital part */
	mt6389_mtkaif_tx_enable(priv);

	/* UL dmic setting off */
	regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, 0x0000);

	/* UL turn on */
	regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, 0x0001);

	return 0;
}

static void mt6389_amic_disable(struct mt6389_priv *priv)
{
	unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
	unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
	unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
	int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
	int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];

	dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u, mic_gain l %d, r %d\n",
		 __func__, mic_type, mux_pga_l, mux_pga_r,
		 mic_gain_l, mic_gain_r);

	/* UL turn off */
	regmap_update_bits(priv->regmap, MT6389_AFE_UL_SRC_CON0_L,
			   0x0001, 0x0000);

	/* disable aud_pad TX fifos */
	mt6389_mtkaif_tx_disable(priv);

	/* L ADC input sel : off, disable L ADC */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
			   0xf000, 0x0000);
	/* L preamplifier DCCEN */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
			   0x1 << 1, 0x0);
	/* L preamplifier input sel : off, L PGA 0 dB gain */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
			   0xfffb, 0x0000);

	/* disable L preamplifier DCC precharge */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
			   0x1 << 2, 0x0);

	/* R ADC input sel : off, disable R ADC */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
			   0xf000, 0x0000);
	/* R preamplifier DCCEN */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
			   0x1 << 1, 0x0);
	/* R preamplifier input sel : off, R PGA 0 dB gain */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
			   0x0ffb, 0x0000);

	/* disable R preamplifier DCC precharge */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
			   0x1 << 2, 0x0);

	/* mic bias */
	/* Disable MICBIAS0, MISBIAS0 = 1P7V */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0000);

	/* Disable MICBIAS1 */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
			   0x0001, 0x0000);

	if (IS_DCC_BASE(mic_type)) {
		/* dcclk_gen_on=1'b0 */
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2060);
		/* dcclk_pdn=1'b1 */
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
		/* dcclk_ref_ck_sel=2'b00 */
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
		/* dcclk_div=11'b00100000011 */
		regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
	}
}

static int mt6389_dmic_enable(struct mt6389_priv *priv)
{
	dev_info(priv->dev, "%s()\n", __func__);

	/* mic bias */
	/* Enable MICBIAS0, MISBIAS0 = 1P9V */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0021);

	/* RG_BANDGAPGEN=1'b0 */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
			   0x1 << 12, 0x0);

	/* DMIC enable */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON8, 0x0005);

	/* here to set digital part */
	mt6389_mtkaif_tx_enable(priv);

	/* UL dmic setting */
	regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, 0x0080);

	/* UL turn on */
	regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, 0x0003);
	return 0;
}

static void mt6389_dmic_disable(struct mt6389_priv *priv)
{
	dev_info(priv->dev, "%s()\n", __func__);

	/* UL turn off */
	regmap_update_bits(priv->regmap, MT6389_AFE_UL_SRC_CON0_L,
			   0x0003, 0x0000);

	/* disable aud_pad TX fifos */
	mt6389_mtkaif_tx_disable(priv);

	/* DMIC disable */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON8, 0x0000);

	/* mic bias */
	/* MISBIAS0 = 1P7V */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0001);

	/* RG_BANDGAPGEN=1'b0 */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
			   0x1 << 12, 0x0);

	/* MICBIA0 disable */
	regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0000);
}

static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
			     struct snd_kcontrol *kcontrol,
			     int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);

	dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
		__func__, event, mux);

	switch (event) {
	case SND_SOC_DAPM_WILL_PMU:
		priv->mux_select[MUX_MIC_TYPE] = mux;
		break;
	case SND_SOC_DAPM_PRE_PMU:
		switch (mux) {
		case MIC_TYPE_MUX_DMIC:
			mt6389_dmic_enable(priv);
			break;
		default:
			mt6389_amic_enable(priv);
			break;
		}

		break;
	case SND_SOC_DAPM_POST_PMD:
		switch (priv->mux_select[MUX_MIC_TYPE]) {
		case MIC_TYPE_MUX_DMIC:
			mt6389_dmic_disable(priv);
			break;
		default:
			mt6389_amic_disable(priv);
			break;
		}

		priv->mux_select[MUX_MIC_TYPE] = mux;
		break;
	default:
		break;
	}

	return 0;
}

static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
			  struct snd_kcontrol *kcontrol,
			  int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);

	dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
		__func__, event, mux);

	priv->mux_select[MUX_ADC_L] = mux;

	return 0;
}

static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
			  struct snd_kcontrol *kcontrol,
			  int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);

	dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
		__func__, event, mux);

	priv->mux_select[MUX_ADC_R] = mux;

	return 0;
}

static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
			     struct snd_kcontrol *kcontrol,
			     int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);

	dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
		__func__, event, mux);

	priv->mux_select[MUX_PGA_L] = mux;

	return 0;
}

static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
			      struct snd_kcontrol *kcontrol,
			      int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);

	dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
		__func__, event, mux);

	priv->mux_select[MUX_PGA_R] = mux;

	return 0;
}

static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
			      struct snd_kcontrol *kcontrol,
			      int event)
{
	switch (event) {
	case SND_SOC_DAPM_POST_PMU:
		usleep_range(250, 270);
		break;
	case SND_SOC_DAPM_PRE_PMD:
		usleep_range(250, 270);
		break;
	default:
		break;
	}

	return 0;
}

/* DAPM Widgets */
static const struct snd_soc_dapm_widget mt6389_dapm_widgets[] = {
	/* Global Supply*/
	SND_SOC_DAPM_SUPPLY_S("LDO_VAUD28", SUPPLY_SEQ_LDO_VAUD28,
			      MT6389_LDO_VAUD28_CON0,
			      RG_LDO_VAUD28_EN_SFT, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
			      MT6389_AUDDEC_ANA_CON11,
			      RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
			      MT6389_DCXO_CW12,
			      RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
			      MT6389_AUDENC_ANA_CON5,
			      RG_CLKSQ_EN_MASK_SFT, 0,
			      mt_clksq_event,
			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
	SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
			      MT6389_AUD_TOP_CKPDN_CON0,
			      RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
			      MT6389_AUD_TOP_CKPDN_CON0,
			      RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
			      MT6389_AUD_TOP_CKPDN_CON0,
			      RG_AUD_CK_PDN_SFT, 1,
			      mt_delay_250_event,
			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
	SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
			      MT6389_AUD_TOP_CKPDN_CON0,
			      RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),

	/* Digital Clock */
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_AFE_CTL_SFT, 1,
			      mt_delay_250_event,
			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_DAC_CTL_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_ADC_CTL_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
			      MT6389_AUDIO_TOP_CON0,
			      PDN_AFE_DL_PREDIST_CTL_SFT, 1, NULL, 0),

	SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
			    0, 0, NULL, 0),

	/* AFE ON */
	SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
			      MT6389_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
			      NULL, 0),

	/* AIF Rx*/
	SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
			      MT6389_AFE_DL_SRC2_CON0_L,
			      DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
			      mt_aif_in_event,
			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

	/* DL Supply */
	SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
			    0, 0, NULL, 0),

	/* DAC */
	SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),

	SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),

	/* LOL */
	SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
			   &lo_in_mux_control,
			   mt_lo_event,
			   SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6389_AUDDEC_ANA_CON5,
			    RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),

	SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6389_AUDDEC_ANA_CON5,
			     RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),

	/* Headphone */
	SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
			   &hpl_in_mux_control,
			   mt_hp_event,
			   SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
			   &hpr_in_mux_control,
			   mt_hp_event,
			   SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_PRE_PMD),

	/* Receiver */
	SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
			   &rcv_in_mux_control,
			   mt_rcv_event,
			   SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_PRE_PMD),

	/* Direct output */
	SND_SOC_DAPM_MUX_E("DIRECT Mux", SND_SOC_NOPM, 0, 0,
			   &direct_in_mux_control,
			   mt_direct_event,
			   SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_PRE_PMD),

	/* Direct + LO output */
	SND_SOC_DAPM_MUX_E("DIRECT_LO Mux", SND_SOC_NOPM, 0, 0,
				&direct_lo_in_mux_control,
				mt_direct_lo_event,
				SND_SOC_DAPM_PRE_PMU |
				SND_SOC_DAPM_PRE_PMD),

	/* Outputs */
	SND_SOC_DAPM_OUTPUT("Receiver"),
	SND_SOC_DAPM_OUTPUT("Headphone L"),
	SND_SOC_DAPM_OUTPUT("Headphone R"),
	SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
	SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
	SND_SOC_DAPM_OUTPUT("LINEOUT L"),
	SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
	SND_SOC_DAPM_OUTPUT("Direct"),
	SND_SOC_DAPM_OUTPUT("Direct_LO"),

	/* SGEN */
	SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6389_AFE_SGEN_CFG0,
			    SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6389_AFE_SGEN_CFG0,
			    SGEN_MUTE_SW_CTL_SFT, 1,
			    mt_sgen_event,
			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6389_AFE_DL_SRC2_CON0_L,
			    DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
			/* tricky, same reg/bit as "AIF_RX", reconsider */

	SND_SOC_DAPM_INPUT("SGEN DL"),

	/* Uplinks */
	SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
			SND_SOC_NOPM, 0, 0,
			mt_aif_out_event,
			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
			SND_SOC_NOPM, 0, 0,
			mt_adc_supply_event,
			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

	/* Uplinks MUX */
	SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
			&aif_out_mux_control),

	SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
			&mic_type_mux_control,
			mt_mic_type_event,
			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
			SND_SOC_DAPM_WILL_PMU),

	SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
			&adc_left_mux_control,
			mt_adc_l_event,
			SND_SOC_DAPM_WILL_PMU),
	SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
			&adc_right_mux_control,
			mt_adc_r_event,
			SND_SOC_DAPM_WILL_PMU),

	SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
	SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
		   &pga_left_mux_control,
		   mt_pga_left_event,
		   SND_SOC_DAPM_WILL_PMU),
	SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
		   &pga_right_mux_control,
		   mt_pga_right_event,
		   SND_SOC_DAPM_WILL_PMU),

	SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),

	/* UL input */
	SND_SOC_DAPM_INPUT("AIN0"),
	SND_SOC_DAPM_INPUT("AIN1"),
	SND_SOC_DAPM_INPUT("AIN2"),
};

static const struct snd_soc_dapm_route mt6389_dapm_routes[] = {
	/* Capture */
	{"AIF1TX", NULL, "AIF Out Mux"},
	{"AIF1TX", NULL, "LDO_VAUD28"},
	{"AIF1TX", NULL, "AUDGLB"},
	{"AIF1TX", NULL, "CLK_BUF"},
	{"AIF1TX", NULL, "CLKSQ Audio"},

	{"AIF1TX", NULL, "AUD_CK"},
	{"AIF1TX", NULL, "AUDIF_CK"},

	{"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
	{"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
	{"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
	{"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
	{"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},

	{"AIF1TX", NULL, "AFE_ON"},

	{"AIF Out Mux", NULL, "Mic Type Mux"},

	{"Mic Type Mux", "ACC", "ADC L"},
	{"Mic Type Mux", "ACC", "ADC R"},
	{"Mic Type Mux", "DCC", "ADC L"},
	{"Mic Type Mux", "DCC", "ADC R"},
	{"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
	{"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
	{"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
	{"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
	{"Mic Type Mux", "DMIC", "AIN0"},
	{"Mic Type Mux", "DMIC", "AIN2"},

	{"ADC L", NULL, "ADC L Mux"},
	{"ADC L", NULL, "ADC Supply"},
	{"ADC R", NULL, "ADC R Mux"},
	{"ADC R", NULL, "ADC Supply"},

	{"ADC L Mux", "Left Preamplifier", "PGA L"},
	{"ADC R Mux", "Right Preamplifier", "PGA R"},

	{"PGA L", NULL, "PGA L Mux"},
	{"PGA R", NULL, "PGA R Mux"},

	{"PGA L Mux", "AIN0", "AIN0"},
	{"PGA L Mux", "AIN1", "AIN1"},
	{"PGA L Mux", "AIN2", "AIN2"},

	{"PGA R Mux", "AIN0", "AIN0"},
	{"PGA R Mux", "AIN1", "AIN1"},
	{"PGA R Mux", "AIN2", "AIN2"},

	/* DL Supply */

	{"DL Power Supply", NULL, "LDO_VAUD28"},
	{"DL Power Supply", NULL, "AUDGLB"},
	{"DL Power Supply", NULL, "CLK_BUF"},
	{"DL Power Supply", NULL, "CLKSQ Audio"},

	{"DL Power Supply", NULL, "AUDNCP_CK"},
	{"DL Power Supply", NULL, "ZCD13M_CK"},
	{"DL Power Supply", NULL, "AUD_CK"},
	{"DL Power Supply", NULL, "AUDIF_CK"},

	/* DL Digital Supply */
	{"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
	{"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
	{"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},

	{"DL Digital Clock", NULL, "AFE_ON"},

	{"AIF_RX", NULL, "DL Digital Clock"},

	/* DL Path */
	{"DAC In Mux", "Normal Path", "AIF_RX"},

	{"DAC In Mux", "Sgen", "SGEN DL"},
	{"SGEN DL", NULL, "SGEN DL SRC"},
	{"SGEN DL", NULL, "SGEN MUTE"},
	{"SGEN DL", NULL, "SGEN DL Enable"},
	{"SGEN DL", NULL, "DL Digital Clock"},
	{"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},

	{"DACL", NULL, "DAC In Mux"},
	{"DACL", NULL, "DL Power Supply"},

	{"DACR", NULL, "DAC In Mux"},
	{"DACR", NULL, "DL Power Supply"},

	/* Lineout Path */
	{"LOL Mux", "Playback", "DACL"},

	{"LOL Buffer", NULL, "LOL Mux"},
	{"LOL Buffer", NULL, "LO Stability Enh"},

	{"LINEOUT L", NULL, "LOL Buffer"},

	/* Headphone Path */
	{"HPL Mux", "Audio Playback", "DACL"},
	{"HPR Mux", "Audio Playback", "DACR"},
	{"HPL Mux", "HP Impedance", "DACL"},
	{"HPR Mux", "HP Impedance", "DACR"},
	{"HPL Mux", "LoudSPK Playback", "DACL"},
	{"HPR Mux", "LoudSPK Playback", "DACR"},

	{"Headphone L", NULL, "HPL Mux"},
	{"Headphone R", NULL, "HPR Mux"},
	{"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
	{"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
	{"LINEOUT L HSSPK", NULL, "HPL Mux"},

	/* Receiver Path */
	{"RCV Mux", "Voice Playback", "DACL"},
	{"Receiver", NULL, "RCV Mux"},

	/* Direct Path */
	{"DIRECT Mux", "Playback", "DACL"},
	{"Direct", NULL, "DIRECT Mux"},

	/* Direct_lo Path */
	{"DIRECT_LO Mux", "Playback", "DACL"},
	{"Direct_LO", NULL, "DIRECT_LO Mux"},
};

static int mt6389_codec_dai_hw_params(struct snd_pcm_substream *substream,
				      struct snd_pcm_hw_params *params,
				      struct snd_soc_dai *dai)
{
	struct snd_soc_component *cmpnt = dai->component;
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
	unsigned int rate = params_rate(params);


	dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
		 __func__,
		 substream->stream,
		 rate,
		 substream->number);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		priv->dl_rate = rate;
	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		priv->ul_rate = rate;

	return 0;
}

static const struct snd_soc_dai_ops mt6389_codec_dai_ops = {
	.hw_params = mt6389_codec_dai_hw_params,
};

#define MT6389_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
			SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
			SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
			SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
			SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)

static struct snd_soc_dai_driver mt6389_dai_driver[] = {
	{
		.name = "mt6389-snd-codec-aif1",
		.playback = {
			.stream_name = "AIF1 Playback",
			.channels_min = 1,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_48000 |
				 SNDRV_PCM_RATE_96000 |
				 SNDRV_PCM_RATE_192000,
			.formats = MT6389_FORMATS,
		},
		.capture = {
			.stream_name = "AIF1 Capture",
			.channels_min = 1,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000 |
				 SNDRV_PCM_RATE_16000 |
				 SNDRV_PCM_RATE_32000 |
				 SNDRV_PCM_RATE_48000,
			.formats = MT6389_FORMATS,
		},
		.ops = &mt6389_codec_dai_ops,
	},
};

static int mt6389_codec_init_reg(struct mt6389_priv *priv)
{
	int ret = 0;
	unsigned int value;

	/* enable LDO_VAUD28 */
	regmap_update_bits(priv->regmap, MT6389_LDO_VAUD28_CON0,
				   0x1 << RG_LDO_VAUD28_EN_SFT,
				   0x1 << RG_LDO_VAUD28_EN_SFT);

	/* enable clk buf */
	regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
			   0x1 << RG_XO_AUDIO_EN_M_SFT,
			   0x1 << RG_XO_AUDIO_EN_M_SFT);

	/* set those not controlled by dapm widget */

	/* audio clk source from internal dcxo */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_IN_SEL_MASK_SFT,
				0 << RG_CLKSQ_IN_SEL_SFT);
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_EN_MASK_SFT,
				1 << RG_CLKSQ_EN_SFT);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);

	/* Reset OUT1 output select none */
	regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
			   0x0700, 0x0000);
	/* Disable voice short circuit protection */
	regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
			   RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
			   0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
	/* disable LO buffer left short circuit protection */
	regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
			   RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
			   0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);

	/* gpio miso driving set to 4mA */
	regmap_write(priv->regmap, MT6389_DRV_CON3, 0xcccc);

	/* set gpio smt */
	gpio_smt_set(priv);

	/* set gpio */
	playback_gpio_reset(priv);
	capture_gpio_reset(priv);

	/* disable clk buf */
	regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
				RG_CLKSQ_EN_MASK_SFT,
				0 << RG_CLKSQ_EN_SFT);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);

	/* disable clk buf */
	regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
			   0x1 << RG_XO_AUDIO_EN_M_SFT,
			   0x0 << RG_XO_AUDIO_EN_M_SFT);

	/* disable LDO_VAUD28 */
	regmap_update_bits(priv->regmap, MT6389_LDO_VAUD28_CON0,
				   0x1 << RG_LDO_VAUD28_EN_SFT,
				   0x0 << RG_LDO_VAUD28_EN_SFT);

	return ret;
}

static int mt6389_codec_probe(struct snd_soc_codec *codec)
{
	struct snd_soc_component *cmpnt = &codec->component;
	struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);

	snd_soc_component_init_regmap(cmpnt, priv->regmap);

	/* add codec controls */
	snd_soc_add_component_controls(cmpnt,
				       mt6389_snd_controls,
				       ARRAY_SIZE(mt6389_snd_controls));
	snd_soc_add_component_controls(cmpnt,
				       mt6389_snd_ul_controls,
				       ARRAY_SIZE(mt6389_snd_ul_controls));

	mt6389_codec_init_reg(priv);
	priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 8;
	priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
	priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 0;
	priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 0;
	priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 3;
	priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 3;
	return 0;
}

static struct snd_soc_codec_driver mt6389_soc_codec_driver = {
	.probe = mt6389_codec_probe,
	.component_driver = {
		.dapm_widgets = mt6389_dapm_widgets,
		.num_dapm_widgets = ARRAY_SIZE(mt6389_dapm_widgets),
		.dapm_routes = mt6389_dapm_routes,
		.num_dapm_routes = ARRAY_SIZE(mt6389_dapm_routes),
	},
};

static void debug_write_reg(struct file *file, void *arg)
{
	struct mt6389_priv *priv = file->private_data;
	char *token1 = NULL;
	char *token2 = NULL;
	char *temp = arg;
	char delim[] = " ,";
	unsigned int reg_addr = 0;
	unsigned int reg_value = 0;
	int ret = 0;

	token1 = strsep(&temp, delim);
	token2 = strsep(&temp, delim);
	dev_info(priv->dev, "%s(), token1 = %s, token2 = %s, temp = %s\n",
		 __func__, token1, token2, temp);

	if ((token1 != NULL) && (token2 != NULL)) {
		ret = kstrtouint(token1, 16, &reg_addr);
		ret = kstrtouint(token2, 16, &reg_value);
		dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
			 __func__,
			 reg_addr, reg_value);
		regmap_write(priv->regmap, reg_addr, reg_value);
		regmap_read(priv->regmap, reg_addr, &reg_value);
		dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
			 __func__,
			 reg_addr, reg_value);
	} else {
		dev_info(priv->dev, "token1 or token2 is NULL!\n");
	}
}

static void debug_set_debug_flag(struct file *file, void *arg)
{
	struct mt6389_priv *priv = file->private_data;
	char *token1 = NULL;
	char *temp = arg;
	char delim[] = " ,";
	int ret = 0;
	unsigned int value;

	token1 = strsep(&temp, delim);
	dev_info(priv->dev, "%s(), token1 = %s, temp = %s\n",
		 __func__, token1, temp);

	if (token1 != NULL) {
		ret = kstrtouint(token1, 16, &value);
		priv->debug_flag = value;
	} else {
		dev_info(priv->dev, "%s(), token1 is NULL!\n", __func__);
	}
}

struct command_function {
	const char *cmd;
	void (*fn)(struct file *, void *);
};

#define CMD_FN(_cmd, _fn) {	\
	.cmd = _cmd,		\
	.fn = _fn,		\
}

static const struct command_function debug_cmds[] = {
	CMD_FN("write_reg", debug_write_reg),
	CMD_FN("set_debug_flag", debug_set_debug_flag),
	{}
};

static int mt6389_debugfs_open(struct inode *inode, struct file *file)
{
	file->private_data = inode->i_private;
	return 0;
}

static ssize_t mt6389_debugfs_read(struct file *file, char __user *buf,
				     size_t count, loff_t *pos)
{
	struct mt6389_priv *priv = file->private_data;
	const int size = 12288;
	char *buffer = NULL; /* for reduce kernel stack */
	int n = 0;
	unsigned int value;
	int ret = 0;

	buffer = kmalloc(size, GFP_KERNEL);
	if (!buffer)
		return -ENOMEM;

	n += scnprintf(buffer + n, size - n, "mtkaif_protocol = %d\n",
		       priv->mtkaif_protocol);

	n += scnprintf(buffer + n, size - n, "debug_flag = 0x%x\n",
		       priv->debug_flag);

	regmap_read(priv->regmap, MT6389_DRV_CON3, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_DRV_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_GPIO_DIR0, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_GPIO_DIR0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_GPIO_MODE2, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_GPIO_MODE2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_GPIO_MODE3, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_GPIO_MODE3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_DCXO_CW12, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_DCXO_CW12 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_LDO_VAUD28_CON0, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_LDO_VAUD28_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUXADC_CON10, &value);
	n += scnprintf(buffer + n, size - n,
		       "MT6389_AUXADC_CON10 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_ID, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_ID = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_REV0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_REV0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_DBI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_DBI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_DXI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_DXI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_TPM0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKPDN_TPM0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_TPM1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKPDN_TPM1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKPDN_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKPDN_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKPDN_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKSEL_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKSEL_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKSEL_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CKTST_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CKTST_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CLK_HWEN_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CLK_HWEN_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_CLK_HWEN_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_RST_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_RST_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_RST_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_RST_BANK_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_RST_BANK_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_MASK_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0_SET, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_MASK_CON0_SET = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0_CLR, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_MASK_CON0_CLR = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_STATUS0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_STATUS0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_RAW_STATUS0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_RAW_STATUS0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MISC_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_INT_MISC_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDNCP_CLKDIV_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDNCP_CLKDIV_CON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDNCP_CLKDIV_CON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDNCP_CLKDIV_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDNCP_CLKDIV_CON4 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUD_TOP_MON_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUD_TOP_MON_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_ID, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_DIG_DSN_ID = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_REV0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_DIG_DSN_REV0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_DBI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_DIG_DSN_DBI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_DXI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_DIG_DSN_DXI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_UL_DL_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_UL_DL_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_DL_SRC2_CON0_L, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_DL_SRC2_CON0_L = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_UL_SRC_CON0_H = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_UL_SRC_CON0_L = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_TOP_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_TOP_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_TOP_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_TOP_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_MON_DEBUG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_MON_DEBUG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON4, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON4 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON5, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON5 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON6, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_CON6 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFUNC_AUD_MON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFUNC_AUD_MON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDRC_TUNE_MON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDRC_TUNE_MON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 = 0x%x\n",
			   value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_MON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_MON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_MON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_MON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_CFG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_CFG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_RX_CFG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_RX_CFG1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_RX_CFG2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_RX_CFG3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_TX_CFG1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADDA_MTKAIF_TX_CFG1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_SGEN_CFG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_SGEN_CFG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_SGEN_CFG1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_SGEN_CFG1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_ADC_ASYNC_FIFO_CFG, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_ADC_ASYNC_FIFO_CFG = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_DCCLK_CFG0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_DCCLK_CFG0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_DCCLK_CFG1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_DCCLK_CFG1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDIO_DIG_CFG, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDIO_DIG_CFG = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_AUD_PAD_TOP = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP_MON, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_AUD_PAD_TOP_MON = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP_MON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_AUD_PAD_TOP_MON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AFE_CG_EN_MON, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AFE_CG_EN_MON = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_DSN_ID, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_DSN_ID = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_DSN_REV0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_DSN_REV0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_DSN_DBI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_DSN_DBI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_DSN_FPI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_DSN_FPI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON4, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON4 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON5 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON6, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON6 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON7, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON7 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON8, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON8 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON9, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON9 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON10, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON10 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON11, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON11 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON12, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDENC_ANA_CON12 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_DSN_ID, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_DSN_ID = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_DSN_REV0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_DSN_REV0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_DSN_DBI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_DSN_DBI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_DSN_FPI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_DSN_FPI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON4, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON4 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON5, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON5 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON6, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON6 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON7, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON7 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON8, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON8 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON9, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON9 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON10, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON10 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON11, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON11 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON12, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON12 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON13, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ANA_CON13 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ELR_NUM, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ELR_NUM = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDDEC_ELR_0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDDEC_ELR_0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDZCD_DSN_ID, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDZCD_DSN_ID = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDZCD_DSN_REV0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDZCD_DSN_REV0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDZCD_DSN_DBI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDZCD_DSN_DBI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_AUDZCD_DSN_FPI, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_AUDZCD_DSN_FPI = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON0, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON0 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON1 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON2, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON2 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON3, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON3 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON4, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON4 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_ZCD_CON5, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6389_ZCD_CON5 = 0x%x\n", value);
	regmap_read(priv->regmap, MT6389_SMT_CON1, &value);
	n += scnprintf(buffer + n, size - n,
			   "MT6359_SMT_CON1 = 0x%x\n", value);

	ret = simple_read_from_buffer(buf, count, pos, buffer, n);
	kfree(buffer);
	return ret;
}

static ssize_t mt6389_debugfs_write(struct file *f, const char __user *buf,
				    size_t count, loff_t *offset)
{
#define MAX_DEBUG_WRITE_INPUT 256
	struct mt6389_priv *priv = f->private_data;
	char input[MAX_DEBUG_WRITE_INPUT];
	char *temp = NULL;
	char *command = NULL;
	char *str_begin = NULL;
	char delim[] = " ,";
	const struct command_function *cf;

	if (!count) {
		dev_info(priv->dev, "%s(), count is 0, return directly\n",
			 __func__);
		goto exit;
	}

	if (count > MAX_DEBUG_WRITE_INPUT)
		count = MAX_DEBUG_WRITE_INPUT;

	memset((void *)input, 0, MAX_DEBUG_WRITE_INPUT);

	if (copy_from_user(input, buf, count))
		dev_info(priv->dev, "%s(), copy_from_user fail, count = %zu\n",
			 __func__, count);

	str_begin = kstrndup(input, MAX_DEBUG_WRITE_INPUT - 1,
			     GFP_KERNEL);
	if (!str_begin) {
		dev_info(priv->dev, "%s(), kstrdup fail\n", __func__);
		goto exit;
	}
	temp = str_begin;

	command = strsep(&temp, delim);

	dev_info(priv->dev, "%s(), command %s, content %s\n",
			 __func__, command, temp);

	for (cf = debug_cmds; cf->cmd; cf++) {
		if (strcmp(cf->cmd, command) == 0) {
			cf->fn(f, temp);
			break;
		}
	}

	kfree(str_begin);
exit:

	return count;
}

// TODO: remove debug fs
static const struct file_operations mt6389_debugfs_ops = {
	.open = mt6389_debugfs_open,
	.write = mt6389_debugfs_write,
	.read = mt6389_debugfs_read,
};

#ifndef CONFIG_MTK_PMIC_WRAP
#ifdef CONFIG_MTK_PMIC_WRAP_HAL
static DEFINE_SPINLOCK(codec_set_reg_lock);
#endif
static unsigned int codec_get_reg(unsigned int offset)
{
#ifdef CONFIG_MTK_PMIC_WRAP_HAL
	int ret = 0;
	unsigned int data = 0;
#ifdef DEBUG_PMIC_WRAP
	pr_info("%s(), call pwrap_read, offset = 0x%x\n",
			__func__, offset);
#endif
	ret = pwrap_read(offset, &data);

	return data;
#else
	return 0;
#endif
}

static void codec_set_reg(unsigned int offset,
			unsigned int value,
			unsigned int mask)
{
	int ret = 0;
	unsigned int reg_value;
	unsigned long flags = 0;

#ifdef CONFIG_MTK_PMIC_WRAP_HAL
	spin_lock_irqsave(&codec_set_reg_lock, flags);
	reg_value = codec_get_reg(offset);
	reg_value &= (~mask);
	reg_value |= (value & mask);
#ifdef DEBUG_PMIC_WRAP
	pr_info("%s(), call pwrap_write, offset = 0x%x, value = 0x%x, mask = 0x%x\n",
			__func__, offset, value, mask);
#endif
	ret = pwrap_write(offset, reg_value);
	spin_unlock_irqrestore(&codec_set_reg_lock, flags);

	reg_value = codec_get_reg(offset);
	if ((reg_value & mask) != (value & mask))
		pr_warn("%s(), offset = 0x%x, mask = 0x%x, ret = %d, reg_value = 0x%x\n",
				__func__, offset, mask, ret, reg_value);
#endif
}

static bool is_writeable_reg(struct device *dev, unsigned int reg)
{
	return true;
}

static bool is_volatile_reg(struct device *dev, unsigned int reg)
{
	return true;
}

static bool is_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case MT6389_DRV_CON3:
	case MT6389_SMT_CON1:
	case MT6389_GPIO_DIR0:
	case MT6389_GPIO_MODE2:
	case MT6389_GPIO_MODE3:
	case MT6389_DCXO_CW12:
	case MT6389_LDO_VAUD28_CON0:
	case MT6389_AUXADC_CON10:
		return true;
	default:
		break;
	};

	if (reg >= MT6389_AUD_TOP_ID && reg <= MT6389_ZCD_CON5)
		return true;

	return false;
}

static int reg_read(void *context, unsigned int reg, unsigned int *val)
{
	*val = codec_get_reg(reg);
	return 0;
}

static int reg_write(void *context, unsigned int reg, unsigned int val)
{
	codec_set_reg(reg, val, 0xffff);
	return 0;
}

#define REG_STRIDE 2
static const struct regmap_config mt6389_regmap = {
	.reg_bits = 16,
	.val_bits = 16,
	.reg_stride = REG_STRIDE,

	.max_register = MT6389_MAX_REGISTER,
	.writeable_reg = is_writeable_reg,
	.volatile_reg = is_volatile_reg,
	.readable_reg = is_readable_reg,

	.reg_read = reg_read,
	.reg_write = reg_write,

	.cache_type = REGCACHE_NONE,
};
#endif

//tianyan@2021.10.19 modify for add audio hardware check start
static int mt6389_audio_hw_debugfs_open(struct inode *inode, struct file *file)
{
	file->private_data = inode->i_private;
	return 0;
}

static ssize_t mt6389_audio_hw_debugfs_read(struct file *file, char __user *buf,
				     size_t count, loff_t *pos)
{
	struct mt6389_priv *priv = file->private_data;
	const int size = 128;
	char *buffer = NULL; /* for reduce kernel stack */
	int n = 0;
	unsigned int value;
	int ret = 0;

	buffer = kmalloc(size, GFP_KERNEL);
	if (!buffer || !buf)
		return -ENOMEM;

	if(regmap_read(priv->regmap, MT6389_LDO_VAUD28_CON0, &value))
		n += scnprintf(buffer + n, size - n, "audio hw status: Not Ok!\n");
	else
		n += scnprintf(buffer + n, size - n, "audio hw status: Ok!\n");
	
	if(value)
		n += scnprintf(buffer + n, size - n, "whether play: playing!\n");
	else
		n += scnprintf(buffer + n, size - n, "whether play: not playing!\n");

	ret = simple_read_from_buffer(buf, count, pos, buffer, n);
	kfree(buffer);
	return ret;
}

static const struct file_operations mt6389_audio_hw_debugfs_ops = {
	.open = mt6389_audio_hw_debugfs_open,
	.read = mt6389_audio_hw_debugfs_read,
};
//tianyan@2021.10.19 modify for add audio hardware check end

static int mt6389_platform_driver_probe(struct platform_device *pdev)
{
	struct mt6389_priv *priv;
#ifdef CONFIG_MTK_PMIC_WRAP
	struct device_node *pwrap_node;
#endif

	priv = devm_kzalloc(&pdev->dev,
			    sizeof(struct mt6389_priv),
			    GFP_KERNEL);
	dev_info(priv->dev, "+%s() ,dev_name %s mt6389_priv %p\n",
		__func__, dev_name(&pdev->dev), priv);
	if (priv == NULL)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, priv);

	priv->dev = &pdev->dev;

#ifndef CONFIG_MTK_PMIC_WRAP
	priv->regmap = devm_regmap_init(&pdev->dev, NULL, NULL, &mt6389_regmap);
#else
	pwrap_node = of_parse_phandle(pdev->dev.of_node,
					  "mediatek,pwrap-regmap", 0);
	if (pwrap_node) {
		priv->regmap = pwrap_node_to_regmap(pwrap_node);
		if (IS_ERR(priv->regmap))
			return PTR_ERR(priv->regmap);
	} else {
		dev_err(&pdev->dev, "get pwrap node fail\n");
		return -EINVAL;
	}
#endif
	if (IS_ERR(priv->regmap))
		return PTR_ERR(priv->regmap);

	/* create debugfs file */
	priv->debugfs = debugfs_create_file("mtksocanaaudio",
					    S_IFREG | 0444, NULL,
					    priv, &mt6389_debugfs_ops);
						
//tianyan@2021.10.19 modify for add audio hardware check start
	(void*)debugfs_create_file("audio_hw",
					    S_IFREG | 0444, NULL,
					    priv, &mt6389_audio_hw_debugfs_ops);
//tianyan@2021.10.19 modify for add audio hardware check end

	dev_info(priv->dev, "%s(), dev name %s\n",
		__func__, dev_name(&pdev->dev));

	return snd_soc_register_codec(&pdev->dev,
				      &mt6389_soc_codec_driver,
				      mt6389_dai_driver,
				      ARRAY_SIZE(mt6389_dai_driver));
}

static int mt6389_platform_driver_remove(struct platform_device *pdev)
{
	struct mt6389_priv *priv = dev_get_drvdata(&pdev->dev);

	dev_info(&pdev->dev, "%s()\n", __func__);

	debugfs_remove(priv->debugfs);

	snd_soc_unregister_codec(&pdev->dev);
	return 0;
}

static const struct of_device_id mt6389_of_match[] = {
	{.compatible = "mediatek,mt6389-sound",},
	{}
};
MODULE_DEVICE_TABLE(of, mt6389_of_match);

static struct platform_driver mt6389_platform_driver = {
	.driver = {
		.name = "mt6389-sound",
		.of_match_table = mt6389_of_match,
	},
	.probe = mt6389_platform_driver_probe,
	.remove = mt6389_platform_driver_remove,
};

module_platform_driver(mt6389_platform_driver)

/* Module information */
MODULE_DESCRIPTION("MT6389 ALSA SoC codec driver");
MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
MODULE_LICENSE("GPL v2");