| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * MT6389.h -- MT6389 ALSA SoC audio codec driver |
| * |
| * Copyright (c) 2017 MediaTek Inc. |
| * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> |
| */ |
| |
| #ifndef __MT6389_H__ |
| #define __MT6389_H__ |
| |
| /* Reg bit define */ |
| /* MT6389_DCXO_CW12 */ |
| #define RG_XO_AUDIO_EN_M_SFT 13 |
| |
| /* LDO_VAUD28_CON0 */ |
| #define RG_LDO_VAUD28_EN_SFT 0 |
| #define RG_LDO_VAUD28_EN_MASK 0x1 |
| #define RG_LDO_VAUD28_EN_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD28_LP_SFT 1 |
| #define RG_LDO_VAUD28_LP_MASK 0x1 |
| #define RG_LDO_VAUD28_LP_MASK_SFT (0x1 << 1) |
| |
| /* AUD_TOP_CKPDN_CON0 */ |
| #define RG_AUDNCP_CK_PDN_SFT 6 |
| #define RG_AUDNCP_CK_PDN_MASK 0x1 |
| #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6) |
| #define RG_ZCD13M_CK_PDN_SFT 5 |
| #define RG_ZCD13M_CK_PDN_MASK 0x1 |
| #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5) |
| #define RG_AUD_INTRP_CK_PDN_SFT 3 |
| #define RG_AUD_INTRP_CK_PDN_MASK 0x1 |
| #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 3) |
| #define RG_AUDIF_CK_PDN_SFT 2 |
| #define RG_AUDIF_CK_PDN_MASK 0x1 |
| #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2) |
| #define RG_AUD_CK_PDN_SFT 1 |
| #define RG_AUD_CK_PDN_MASK 0x1 |
| #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1) |
| |
| /* AUD_TOP_CKPDN_CON0_SET */ |
| #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x7f |
| #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x7f << 0) |
| |
| /* AUD_TOP_CKPDN_CON0_CLR */ |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x7f |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x7f << 0) |
| |
| /* AUD_TOP_CKSEL_CON0 */ |
| #define RG_AUDIF_CK_CKSEL_SFT 3 |
| #define RG_AUDIF_CK_CKSEL_MASK 0x1 |
| #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3) |
| #define RG_AUD_CK_CKSEL_SFT 2 |
| #define RG_AUD_CK_CKSEL_MASK 0x1 |
| #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2) |
| |
| /* AUD_TOP_CKSEL_CON0_SET */ |
| #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf |
| #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_CKSEL_CON0_CLR */ |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_CKTST_CON0 */ |
| #define RG_AUD26M_CK_TSTSEL_SFT 4 |
| #define RG_AUD26M_CK_TSTSEL_MASK 0x1 |
| #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4) |
| #define RG_AUDIF_CK_TSTSEL_SFT 3 |
| #define RG_AUDIF_CK_TSTSEL_MASK 0x1 |
| #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3) |
| #define RG_AUD_CK_TSTSEL_SFT 2 |
| #define RG_AUD_CK_TSTSEL_MASK 0x1 |
| #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2) |
| #define RG_AUD26M_CK_TST_DIS_SFT 0 |
| #define RG_AUD26M_CK_TST_DIS_MASK 0x1 |
| #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_CLK_HWEN_CON0 */ |
| #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0 |
| #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1 |
| #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_CLK_HWEN_CON0_SET */ |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0 |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_CLK_HWEN_CON0_CLR */ |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0 |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_RST_CON0 */ |
| #define RG_AUDNCP_RST_SFT 3 |
| #define RG_AUDNCP_RST_MASK 0x1 |
| #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3) |
| #define RG_ZCD_RST_SFT 2 |
| #define RG_ZCD_RST_MASK 0x1 |
| #define RG_ZCD_RST_MASK_SFT (0x1 << 2) |
| #define RG_AUDIO_RST_SFT 0 |
| #define RG_AUDIO_RST_MASK 0x1 |
| #define RG_AUDIO_RST_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_RST_CON0_SET */ |
| #define RG_AUD_TOP_RST_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf |
| #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_RST_CON0_CLR */ |
| #define RG_AUD_TOP_RST_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf |
| #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_RST_BANK_CON0 */ |
| #define BANK_AUDZCD_SWRST_SFT 2 |
| #define BANK_AUDZCD_SWRST_MASK 0x1 |
| #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2) |
| #define BANK_AUDIO_SWRST_SFT 1 |
| #define BANK_AUDIO_SWRST_MASK 0x1 |
| #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1) |
| |
| /* AUD_TOP_INT_CON0 */ |
| #define RG_INT_EN_AUDIO_SFT 0 |
| #define RG_INT_EN_AUDIO_MASK 0x1 |
| #define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_INT_CON0_SET */ |
| #define RG_AUD_INT_CON0_SET_SFT 0 |
| #define RG_AUD_INT_CON0_SET_MASK 0xffff |
| #define RG_AUD_INT_CON0_SET_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_INT_CON0_CLR */ |
| #define RG_AUD_INT_CON0_CLR_SFT 0 |
| #define RG_AUD_INT_CON0_CLR_MASK 0xffff |
| #define RG_AUD_INT_CON0_CLR_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_INT_MASK_CON0 */ |
| #define RG_INT_MASK_AUDIO_SFT 0 |
| #define RG_INT_MASK_AUDIO_MASK 0x1 |
| #define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_INT_MASK_CON0_SET */ |
| #define RG_AUD_INT_MASK_CON0_SET_SFT 0 |
| #define RG_AUD_INT_MASK_CON0_SET_MASK 0xffff |
| #define RG_AUD_INT_MASK_CON0_SET_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_INT_MASK_CON0_CLR */ |
| #define RG_AUD_INT_MASK_CON0_CLR_SFT 0 |
| #define RG_AUD_INT_MASK_CON0_CLR_MASK 0xffff |
| #define RG_AUD_INT_MASK_CON0_CLR_MASK_SFT (0xffff << 0) |
| |
| /* AUD_TOP_INT_STATUS0 */ |
| #define RG_INT_STATUS_AUDIO_SFT 0 |
| #define RG_INT_STATUS_AUDIO_MASK 0x1 |
| #define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_INT_RAW_STATUS0 */ |
| #define RG_INT_RAW_STATUS_AUDIO_SFT 0 |
| #define RG_INT_RAW_STATUS_AUDIO_MASK 0x1 |
| #define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_INT_MISC_CON0 */ |
| #define RG_AUD_TOP_INT_POLARITY_SFT 0 |
| #define RG_AUD_TOP_INT_POLARITY_MASK 0x1 |
| #define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0) |
| |
| /* AUDNCP_CLKDIV_CON0 */ |
| #define RG_DIVCKS_CHG_SFT 0 |
| #define RG_DIVCKS_CHG_MASK 0x1 |
| #define RG_DIVCKS_CHG_MASK_SFT (0x1 << 0) |
| |
| /* AUDNCP_CLKDIV_CON1 */ |
| #define RG_DIVCKS_ON_SFT 0 |
| #define RG_DIVCKS_ON_MASK 0x1 |
| #define RG_DIVCKS_ON_MASK_SFT (0x1 << 0) |
| |
| /* AUDNCP_CLKDIV_CON2 */ |
| #define RG_DIVCKS_PRG_SFT 0 |
| #define RG_DIVCKS_PRG_MASK 0x1ff |
| #define RG_DIVCKS_PRG_MASK_SFT (0x1ff << 0) |
| |
| /* AUDNCP_CLKDIV_CON3 */ |
| #define RG_DIVCKS_PWD_NCP_SFT 0 |
| #define RG_DIVCKS_PWD_NCP_MASK 0x1 |
| #define RG_DIVCKS_PWD_NCP_MASK_SFT (0x1 << 0) |
| |
| /* AUDNCP_CLKDIV_CON4 */ |
| #define RG_DIVCKS_PWD_NCP_ST_SEL_SFT 0 |
| #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3 |
| #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AUD_TOP_MON_CON0 */ |
| #define RG_AUD_TOP_MON_SEL_SFT 0 |
| #define RG_AUD_TOP_MON_SEL_MASK 0x7 |
| #define RG_AUD_TOP_MON_SEL_MASK_SFT (0x7 << 0) |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_SFT 3 |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xff |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT (0xff << 3) |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_SFT 11 |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1 |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 11) |
| |
| /* AUDIO_DIG_DSN_ID */ |
| #define AUDIO_DIG_ANA_ID_SFT 0 |
| #define AUDIO_DIG_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_ANA_ID_MASK_SFT (0xff << 0) |
| #define AUDIO_DIG_DIG_ID_SFT 8 |
| #define AUDIO_DIG_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 8) |
| |
| /* AUDIO_DIG_DSN_REV0 */ |
| #define AUDIO_DIG_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| #define AUDIO_DIG_DIG_MINOR_REV_SFT 8 |
| #define AUDIO_DIG_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 8) |
| #define AUDIO_DIG_DIG_MAJOR_REV_SFT 12 |
| #define AUDIO_DIG_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT (0xf << 12) |
| |
| /* AUDIO_DIG_DSN_DBI */ |
| #define AUDIO_DIG_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2) |
| #define AUDIO_DIG_ESP_SFT 8 |
| #define AUDIO_DIG_ESP_MASK 0xff |
| #define AUDIO_DIG_ESP_MASK_SFT (0xff << 8) |
| |
| /* AUDIO_DIG_DSN_DXI */ |
| #define AUDIO_DIG_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_UL_DL_CON0 */ |
| #define AFE_UL_LR_SWAP_SFT 15 |
| #define AFE_UL_LR_SWAP_MASK 0x1 |
| #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15) |
| #define AFE_DL_LR_SWAP_SFT 14 |
| #define AFE_DL_LR_SWAP_MASK 0x1 |
| #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14) |
| #define AFE_ON_SFT 0 |
| #define AFE_ON_MASK 0x1 |
| #define AFE_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DL_SRC2_CON0_L */ |
| #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 |
| #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 |
| #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) |
| |
| /* AFE_UL_SRC_CON0_H */ |
| #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11 |
| #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7 |
| #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11) |
| #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8 |
| #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7 |
| #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8) |
| #define C_TWO_DIGITAL_MIC_CTL_SFT 7 |
| #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1 |
| #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7) |
| |
| /* AFE_UL_SRC_CON0_L */ |
| #define DMIC_LOW_POWER_MODE_CTL_SFT 14 |
| #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 |
| #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) |
| #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 |
| #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 |
| #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) |
| #define UL_LOOP_BACK_MODE_CTL_SFT 2 |
| #define UL_LOOP_BACK_MODE_CTL_MASK 0x1 |
| #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) |
| #define UL_SDM_3_LEVEL_CTL_SFT 1 |
| #define UL_SDM_3_LEVEL_CTL_MASK 0x1 |
| #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) |
| #define UL_SRC_ON_TMP_CTL_SFT 0 |
| #define UL_SRC_ON_TMP_CTL_MASK 0x1 |
| #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_TOP_CON0 */ |
| #define MTKAIF_SINE_ON_SFT 2 |
| #define MTKAIF_SINE_ON_MASK 0x1 |
| #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2) |
| #define UL_SINE_ON_SFT 1 |
| #define UL_SINE_ON_MASK 0x1 |
| #define UL_SINE_ON_MASK_SFT (0x1 << 1) |
| #define DL_SINE_ON_SFT 0 |
| #define DL_SINE_ON_MASK 0x1 |
| #define DL_SINE_ON_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_TOP_CON0 */ |
| #define PDN_AFE_CTL_SFT 7 |
| #define PDN_AFE_CTL_MASK 0x1 |
| #define PDN_AFE_CTL_MASK_SFT (0x1 << 7) |
| #define PDN_DAC_CTL_SFT 6 |
| #define PDN_DAC_CTL_MASK 0x1 |
| #define PDN_DAC_CTL_MASK_SFT (0x1 << 6) |
| #define PDN_ADC_CTL_SFT 5 |
| #define PDN_ADC_CTL_MASK 0x1 |
| #define PDN_ADC_CTL_MASK_SFT (0x1 << 5) |
| #define PDN_I2S_DL_CTL_SFT 3 |
| #define PDN_I2S_DL_CTL_MASK 0x1 |
| #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3) |
| #define PWR_CLK_DIS_CTL_SFT 2 |
| #define PWR_CLK_DIS_CTL_MASK 0x1 |
| #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2) |
| #define PDN_AFE_TESTMODEL_CTL_SFT 1 |
| #define PDN_AFE_TESTMODEL_CTL_MASK 0x1 |
| #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1) |
| #define PDN_AFE_DL_PREDIST_CTL_SFT 0 |
| #define PDN_AFE_DL_PREDIST_CTL_MASK 0x1 |
| #define PDN_AFE_DL_PREDIST_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_MON_DEBUG0 */ |
| #define AUDIO_SYS_TOP_MON_SWAP_SFT 14 |
| #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3 |
| #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14) |
| #define AUDIO_SYS_TOP_MON_SEL_SFT 8 |
| #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f |
| #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8) |
| #define AFE_MON_SEL_SFT 0 |
| #define AFE_MON_SEL_MASK 0xf |
| #define AFE_MON_SEL_MASK_SFT (0xf << 0) |
| |
| /* AFUNC_AUD_CON0 */ |
| #define CCI_AUD_ANACK_SEL_SFT 15 |
| #define CCI_AUD_ANACK_SEL_MASK 0x1 |
| #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15) |
| #define CCI_AUDIO_FIFO_WPTR_SFT 12 |
| #define CCI_AUDIO_FIFO_WPTR_MASK 0x7 |
| #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12) |
| #define CCI_SCRAMBLER_CG_EN_SFT 11 |
| #define CCI_SCRAMBLER_CG_EN_MASK 0x1 |
| #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11) |
| #define CCI_LCH_INV_SFT 10 |
| #define CCI_LCH_INV_MASK 0x1 |
| #define CCI_LCH_INV_MASK_SFT (0x1 << 10) |
| #define CCI_RAND_EN_SFT 9 |
| #define CCI_RAND_EN_MASK 0x1 |
| #define CCI_RAND_EN_MASK_SFT (0x1 << 9) |
| #define CCI_SPLT_SCRMB_CLK_ON_SFT 8 |
| #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1 |
| #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8) |
| #define CCI_SPLT_SCRMB_ON_SFT 7 |
| #define CCI_SPLT_SCRMB_ON_MASK 0x1 |
| #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_IDAC_TEST_EN_SFT 6 |
| #define CCI_AUD_IDAC_TEST_EN_MASK 0x1 |
| #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6) |
| #define CCI_ZERO_PAD_DISABLE_SFT 5 |
| #define CCI_ZERO_PAD_DISABLE_MASK 0x1 |
| #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5) |
| #define CCI_AUD_SPLIT_TEST_EN_SFT 4 |
| #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1 |
| #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4) |
| #define CCI_AUD_SDM_MUTEL_SFT 3 |
| #define CCI_AUD_SDM_MUTEL_MASK 0x1 |
| #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3) |
| #define CCI_AUD_SDM_MUTER_SFT 2 |
| #define CCI_AUD_SDM_MUTER_MASK 0x1 |
| #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2) |
| #define CCI_AUD_SDM_7BIT_SEL_SFT 1 |
| #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1 |
| #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1) |
| #define CCI_SCRAMBLER_EN_SFT 0 |
| #define CCI_SCRAMBLER_EN_MASK 0x1 |
| #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON1 */ |
| #define AUD_SDM_TEST_L_SFT 8 |
| #define AUD_SDM_TEST_L_MASK 0xff |
| #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8) |
| #define AUD_SDM_TEST_R_SFT 0 |
| #define AUD_SDM_TEST_R_MASK 0xff |
| #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON2 */ |
| #define CCI_AUD_DAC_ANA_MUTE_SFT 7 |
| #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6) |
| #define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4) |
| #define CCI_AUDIO_FIFO_ENABLE_SFT 3 |
| #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1 |
| #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3) |
| #define CCI_ACD_MODE_SFT 2 |
| #define CCI_ACD_MODE_MASK 0x1 |
| #define CCI_ACD_MODE_MASK_SFT (0x1 << 2) |
| #define CCI_AFIFO_CLK_PWDB_SFT 1 |
| #define CCI_AFIFO_CLK_PWDB_MASK 0x1 |
| #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1) |
| #define CCI_ACD_FUNC_RSTB_SFT 0 |
| #define CCI_ACD_FUNC_RSTB_MASK 0x1 |
| #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON3 */ |
| #define SDM_ANA13M_TESTCK_SEL_SFT 15 |
| #define SDM_ANA13M_TESTCK_SEL_MASK 0x1 |
| #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15) |
| #define SDM_ANA13M_TESTCK_SRC_SEL_SFT 12 |
| #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7 |
| #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12) |
| #define SDM_TESTCK_SRC_SEL_SFT 8 |
| #define SDM_TESTCK_SRC_SEL_MASK 0x7 |
| #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8) |
| #define DIGMIC_TESTCK_SRC_SEL_SFT 4 |
| #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7 |
| #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4) |
| #define DIGMIC_TESTCK_SEL_SFT 0 |
| #define DIGMIC_TESTCK_SEL_MASK 0x1 |
| #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON4 */ |
| #define UL_FIFO_WCLK_INV_SFT 8 |
| #define UL_FIFO_WCLK_INV_MASK 0x1 |
| #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8) |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6 |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6) |
| #define UL_FIFO_WDATA_TESTEN_SFT 5 |
| #define UL_FIFO_WDATA_TESTEN_MASK 0x1 |
| #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5) |
| #define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4 |
| #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4) |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3) |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFUNC_AUD_CON5 */ |
| #define R_AUD_DAC_POS_LARGE_MONO_SFT 8 |
| #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff |
| #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8) |
| #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0 |
| #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff |
| #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON6 */ |
| #define R_AUD_DAC_POS_SMALL_MONO_SFT 12 |
| #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf |
| #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12) |
| #define R_AUD_DAC_NEG_SMALL_MONO_SFT 8 |
| #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf |
| #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8) |
| #define R_AUD_DAC_POS_TINY_MONO_SFT 6 |
| #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3 |
| #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6) |
| #define R_AUD_DAC_NEG_TINY_MONO_SFT 4 |
| #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3 |
| #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4) |
| #define R_AUD_DAC_MONO_SEL_SFT 3 |
| #define R_AUD_DAC_MONO_SEL_MASK 0x1 |
| #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3) |
| #define R_AUD_DAC_SGEN_SW_RSTB_SFT 0 |
| #define R_AUD_DAC_SGEN_SW_RSTB_MASK 0x1 |
| #define R_AUD_DAC_SGEN_SW_RSTB_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_MON0 */ |
| #define AUD_SCR_OUT_L_SFT 8 |
| #define AUD_SCR_OUT_L_MASK 0xff |
| #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8) |
| #define AUD_SCR_OUT_R_SFT 0 |
| #define AUD_SCR_OUT_R_MASK 0xff |
| #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0) |
| |
| /* AUDRC_TUNE_MON0 */ |
| #define ASYNC_TEST_OUT_BCK_SFT 15 |
| #define ASYNC_TEST_OUT_BCK_MASK 0x1 |
| #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15) |
| #define RGS_AUDRCTUNE1READ_SFT 8 |
| #define RGS_AUDRCTUNE1READ_MASK 0x1f |
| #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8) |
| #define RGS_AUDRCTUNE0READ_SFT 0 |
| #define RGS_AUDRCTUNE0READ_MASK 0x1f |
| #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA_MTKAIF_FIFO_CFG0 */ |
| #define AFE_RESERVED_SFT 1 |
| #define AFE_RESERVED_MASK 0x7fff |
| #define AFE_RESERVED_MASK_SFT (0x7fff << 1) |
| #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0 |
| #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1 |
| #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */ |
| #define MTKAIF_RXIF_WR_FULL_STATUS_SFT 1 |
| #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1 |
| #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1) |
| #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0 |
| #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1 |
| #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_MTKAIF_MON0 */ |
| #define MTKAIFTX_V3_SYNC_OUT_SFT 14 |
| #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1 |
| #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 14) |
| #define MTKAIFTX_V3_SDATA_OUT2_SFT 13 |
| #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1 |
| #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13) |
| #define MTKAIFTX_V3_SDATA_OUT1_SFT 12 |
| #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1 |
| #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12) |
| #define MTKAIF_RXIF_FIFO_STATUS_SFT 0 |
| #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff |
| #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0) |
| |
| /* AFE_ADDA_MTKAIF_MON1 */ |
| #define MTKAIFRX_V3_SYNC_IN_SFT 14 |
| #define MTKAIFRX_V3_SYNC_IN_MASK 0x1 |
| #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 14) |
| #define MTKAIFRX_V3_SDATA_IN2_SFT 13 |
| #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1 |
| #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13) |
| #define MTKAIFRX_V3_SDATA_IN1_SFT 12 |
| #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1 |
| #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12) |
| #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 11 |
| #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1 |
| #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11) |
| #define MTKAIF_RXIF_INVALID_FLAG_SFT 8 |
| #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1 |
| #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8) |
| #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0 |
| #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff |
| #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIF_MON2 */ |
| #define MTKAIF_TXIF_IN_CH2_SFT 8 |
| #define MTKAIF_TXIF_IN_CH2_MASK 0xff |
| #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8) |
| #define MTKAIF_TXIF_IN_CH1_SFT 0 |
| #define MTKAIF_TXIF_IN_CH1_MASK 0xff |
| #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIF_MON3 */ |
| #define MTKAIF_RXIF_OUT_CH2_SFT 8 |
| #define MTKAIF_RXIF_OUT_CH2_MASK 0xff |
| #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8) |
| #define MTKAIF_RXIF_OUT_CH1_SFT 0 |
| #define MTKAIF_RXIF_OUT_CH1_MASK 0xff |
| #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIF_CFG0 */ |
| #define RG_MTKAIF_RXIF_CLKINV_SFT 15 |
| #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1 |
| #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15) |
| #define RG_MTKAIF_RXIF_PROTOCOL2_SFT 8 |
| #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1 |
| #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8) |
| #define RG_MTKAIF_BYPASS_SRC_MODE_SFT 6 |
| #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3 |
| #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6) |
| #define RG_MTKAIF_BYPASS_SRC_TEST_SFT 5 |
| #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1 |
| #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5) |
| #define RG_MTKAIF_TXIF_PROTOCOL2_SFT 4 |
| #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1 |
| #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4) |
| #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 2 |
| #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1 |
| #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2) |
| #define RG_MTKAIF_LOOPBACK_TEST2_SFT 1 |
| #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1 |
| #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1) |
| #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0 |
| #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1 |
| #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_MTKAIF_RX_CFG0 */ |
| #define RG_MTKAIF_RXIF_VOICE_MODE_SFT 12 |
| #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf |
| #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12) |
| #define RG_MTKAIF_RXIF_DATA_BIT_SFT 8 |
| #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7 |
| #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8) |
| #define RG_MTKAIF_RXIF_FIFO_RSP_SFT 4 |
| #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7 |
| #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4) |
| #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3 |
| #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1 |
| #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3) |
| #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0 |
| #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1 |
| #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_MTKAIF_RX_CFG1 */ |
| #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 12 |
| #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf |
| #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12) |
| #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8 |
| #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf |
| #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8) |
| #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 4 |
| #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf |
| #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) |
| #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0 |
| #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf |
| #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_MTKAIF_RX_CFG2 */ |
| #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 12 |
| #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1 |
| #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12) |
| #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0 |
| #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff |
| #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0) |
| |
| /* AFE_ADDA_MTKAIF_RX_CFG3 */ |
| #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4 |
| #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7 |
| #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4) |
| #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3 |
| #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1 |
| #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3) |
| |
| /* AFE_ADDA_MTKAIF_TX_CFG1 */ |
| #define RG_MTKAIF_SYNC_WORD2_SFT 4 |
| #define RG_MTKAIF_SYNC_WORD2_MASK 0x7 |
| #define RG_MTKAIF_SYNC_WORD2_MASK_SFT (0x7 << 4) |
| #define RG_MTKAIF_SYNC_WORD1_SFT 0 |
| #define RG_MTKAIF_SYNC_WORD1_MASK 0x7 |
| #define RG_MTKAIF_SYNC_WORD1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_SGEN_CFG0 */ |
| #define SGEN_AMP_DIV_CH1_CTL_SFT 12 |
| #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf |
| #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12) |
| #define SGEN_DAC_EN_CTL_SFT 7 |
| #define SGEN_DAC_EN_CTL_MASK 0x1 |
| #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7) |
| #define SGEN_MUTE_SW_CTL_SFT 6 |
| #define SGEN_MUTE_SW_CTL_MASK 0x1 |
| #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6) |
| #define R_AUD_SDM_MUTE_L_SFT 5 |
| #define R_AUD_SDM_MUTE_L_MASK 0x1 |
| #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5) |
| #define R_AUD_SDM_MUTE_R_SFT 4 |
| #define R_AUD_SDM_MUTE_R_MASK 0x1 |
| #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4) |
| |
| /* AFE_SGEN_CFG1 */ |
| #define C_SGEN_RCH_INV_5BIT_SFT 15 |
| #define C_SGEN_RCH_INV_5BIT_MASK 0x1 |
| #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15) |
| #define C_SGEN_RCH_INV_8BIT_SFT 14 |
| #define C_SGEN_RCH_INV_8BIT_MASK 0x1 |
| #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14) |
| #define SGEN_FREQ_DIV_CH1_CTL_SFT 0 |
| #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f |
| #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADC_ASYNC_FIFO_CFG */ |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5) |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4) |
| #define RG_AMIC_UL_ADC_CLK_SEL_SFT 1 |
| #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1 |
| #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1) |
| |
| /* AFE_DCCLK_CFG0 */ |
| #define DCCLK_DIV_SFT 5 |
| #define DCCLK_DIV_MASK 0x7ff |
| #define DCCLK_DIV_MASK_SFT (0x7ff << 5) |
| #define DCCLK_INV_SFT 4 |
| #define DCCLK_INV_MASK 0x1 |
| #define DCCLK_INV_MASK_SFT (0x1 << 4) |
| #define DCCLK_PDN_SFT 1 |
| #define DCCLK_PDN_MASK 0x1 |
| #define DCCLK_PDN_MASK_SFT (0x1 << 1) |
| #define DCCLK_GEN_ON_SFT 0 |
| #define DCCLK_GEN_ON_MASK 0x1 |
| #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DCCLK_CFG1 */ |
| #define RESYNC_SRC_SEL_SFT 10 |
| #define RESYNC_SRC_SEL_MASK 0x3 |
| #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10) |
| #define RESYNC_SRC_CK_INV_SFT 9 |
| #define RESYNC_SRC_CK_INV_MASK 0x1 |
| #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9) |
| #define DCCLK_RESYNC_BYPASS_SFT 8 |
| #define DCCLK_RESYNC_BYPASS_MASK 0x1 |
| #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8) |
| #define DCCLK_PHASE_SEL_SFT 4 |
| #define DCCLK_PHASE_SEL_MASK 0xf |
| #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_CFG */ |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 15 |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1 |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15) |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 8 |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8) |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7 |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1 |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7) |
| #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0 |
| #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f |
| #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0) |
| |
| /* AFE_AUD_PAD_TOP */ |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 12 |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7 |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12) |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 11 |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1 |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11) |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 8 |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1 |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8) |
| |
| /* AFE_AUD_PAD_TOP_MON */ |
| #define ADDA_AUD_PAD_TOP_MON_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff |
| #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0) |
| |
| /* AFE_AUD_PAD_TOP_MON1 */ |
| #define ADDA_AUD_PAD_TOP_MON1_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff |
| #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0) |
| |
| /* AFE_CG_EN_MON */ |
| #define AFE_CG_EN_MON_SFT 0 |
| #define AFE_CG_EN_MON_MASK 0x3f |
| #define AFE_CG_EN_MON_MASK_SFT (0x3f << 0) |
| |
| /* AUDENC_DSN_ID */ |
| #define AUDENC_ANA_ID_SFT 0 |
| #define AUDENC_ANA_ID_MASK 0xff |
| #define AUDENC_ANA_ID_MASK_SFT (0xff << 0) |
| #define AUDENC_DIG_ID_SFT 8 |
| #define AUDENC_DIG_ID_MASK 0xff |
| #define AUDENC_DIG_ID_MASK_SFT (0xff << 8) |
| |
| /* AUDENC_DSN_REV0 */ |
| #define AUDENC_ANA_MINOR_REV_SFT 0 |
| #define AUDENC_ANA_MINOR_REV_MASK 0xf |
| #define AUDENC_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDENC_ANA_MAJOR_REV_SFT 4 |
| #define AUDENC_ANA_MAJOR_REV_MASK 0xf |
| #define AUDENC_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| #define AUDENC_DIG_MINOR_REV_SFT 8 |
| #define AUDENC_DIG_MINOR_REV_MASK 0xf |
| #define AUDENC_DIG_MINOR_REV_MASK_SFT (0xf << 8) |
| #define AUDENC_DIG_MAJOR_REV_SFT 12 |
| #define AUDENC_DIG_MAJOR_REV_MASK 0xf |
| #define AUDENC_DIG_MAJOR_REV_MASK_SFT (0xf << 12) |
| |
| /* AUDENC_DSN_DBI */ |
| #define AUDENC_DSN_CBS_SFT 0 |
| #define AUDENC_DSN_CBS_MASK 0x3 |
| #define AUDENC_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDENC_DSN_BIX_SFT 2 |
| #define AUDENC_DSN_BIX_MASK 0x3 |
| #define AUDENC_DSN_BIX_MASK_SFT (0x3 << 2) |
| #define AUDENC_DSN_ESP_SFT 8 |
| #define AUDENC_DSN_ESP_MASK 0xff |
| #define AUDENC_DSN_ESP_MASK_SFT (0xff << 8) |
| |
| /* AUDENC_DSN_FPI */ |
| #define AUDENC_DSN_FPI_SFT 0 |
| #define AUDENC_DSN_FPI_MASK 0xff |
| #define AUDENC_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_ANA_CON0 */ |
| #define RG_AUDPREAMPLON_SFT 0 |
| #define RG_AUDPREAMPLON_MASK 0x1 |
| #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPLDCCEN_SFT 1 |
| #define RG_AUDPREAMPLDCCEN_MASK 0x1 |
| #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPLDCRPECHARGE_SFT 2 |
| #define RG_AUDPREAMPLDCRPECHARGE_MASK 0x1 |
| #define RG_AUDPREAMPLDCRPECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMPLPGATEST_SFT 3 |
| #define RG_AUDPREAMPLPGATEST_MASK 0x1 |
| #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMPLVSCALE_SFT 4 |
| #define RG_AUDPREAMPLVSCALE_MASK 0x3 |
| #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMPLINPUTSEL_SFT 6 |
| #define RG_AUDPREAMPLINPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6) |
| #define RG_AUDPREAMPLGAIN_SFT 8 |
| #define RG_AUDPREAMPLGAIN_MASK 0x7 |
| #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8) |
| #define RG_AUDADCLPWRUP_SFT 12 |
| #define RG_AUDADCLPWRUP_MASK 0x1 |
| #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12) |
| #define RG_AUDADCLINPUTSEL_SFT 13 |
| #define RG_AUDADCLINPUTSEL_MASK 0x3 |
| #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13) |
| #define RG_AUDPREAMPLSE_SFT 15 |
| #define RG_AUDPREAMPLSE_MASK 0x1 |
| #define RG_AUDPREAMPLSE_MASK_SFT (0x1 << 15) |
| |
| /* AUDENC_ANA_CON1 */ |
| #define RG_AUDPREAMPRON_SFT 0 |
| #define RG_AUDPREAMPRON_MASK 0x1 |
| #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPRDCCEN_SFT 1 |
| #define RG_AUDPREAMPRDCCEN_MASK 0x1 |
| #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPRDCRPECHARGE_SFT 2 |
| #define RG_AUDPREAMPRDCRPECHARGE_MASK 0x1 |
| #define RG_AUDPREAMPRDCRPECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMPRPGATEST_SFT 3 |
| #define RG_AUDPREAMPRPGATEST_MASK 0x1 |
| #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMPRVSCALE_SFT 4 |
| #define RG_AUDPREAMPRVSCALE_MASK 0x3 |
| #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMPRINPUTSEL_SFT 6 |
| #define RG_AUDPREAMPRINPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6) |
| #define RG_AUDPREAMPRGAIN_SFT 8 |
| #define RG_AUDPREAMPRGAIN_MASK 0x7 |
| #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8) |
| #define RG_AUDADCRPWRUP_SFT 12 |
| #define RG_AUDADCRPWRUP_MASK 0x1 |
| #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12) |
| #define RG_AUDADCRINPUTSEL_SFT 13 |
| #define RG_AUDADCRINPUTSEL_MASK 0x3 |
| #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13) |
| #define RG_AUDPREAMPRSE_SFT 15 |
| #define RG_AUDPREAMPRSE_MASK 0x1 |
| #define RG_AUDPREAMPRSE_MASK_SFT (0x1 << 15) |
| |
| /* AUDENC_ANA_CON2 */ |
| #define RG_AUDULHALFBIAS_SFT 0 |
| #define RG_AUDULHALFBIAS_MASK 0x1 |
| #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0) |
| #define RG_AUDGLBMADLPWEN_SFT 1 |
| #define RG_AUDGLBMADLPWEN_MASK 0x1 |
| #define RG_AUDGLBMADLPWEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPLPEN_SFT 2 |
| #define RG_AUDPREAMPLPEN_MASK 0x1 |
| #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDADC1STSTAGELPEN_SFT 3 |
| #define RG_AUDADC1STSTAGELPEN_MASK 0x1 |
| #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDADC2NDSTAGELPEN_SFT 4 |
| #define RG_AUDADC2NDSTAGELPEN_MASK 0x1 |
| #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCFLASHLPEN_SFT 5 |
| #define RG_AUDADCFLASHLPEN_MASK 0x1 |
| #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5) |
| #define RG_AUDPREAMPIDDTEST_SFT 6 |
| #define RG_AUDPREAMPIDDTEST_MASK 0x3 |
| #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6) |
| #define RG_AUDADC1STSTAGEIDDTEST_SFT 8 |
| #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8) |
| #define RG_AUDADC2NDSTAGEIDDTEST_SFT 10 |
| #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10) |
| #define RG_AUDADCREFBUFIDDTEST_SFT 12 |
| #define RG_AUDADCREFBUFIDDTEST_MASK 0x3 |
| #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12) |
| #define RG_AUDADCFLASHIDDTEST_SFT 14 |
| #define RG_AUDADCFLASHIDDTEST_MASK 0x3 |
| #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14) |
| |
| /* AUDENC_ANA_CON3 */ |
| #define RG_AUDADCDAC0P25FS_SFT 0 |
| #define RG_AUDADCDAC0P25FS_MASK 0x1 |
| #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCCLKSEL_SFT 1 |
| #define RG_AUDADCCLKSEL_MASK 0x1 |
| #define RG_AUDADCCLKSEL_MASK_SFT (0x1 << 1) |
| #define RG_AUDADCCLKSOURCE_SFT 2 |
| #define RG_AUDADCCLKSOURCE_MASK 0x3 |
| #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 2) |
| #define RG_AUDPREAMPAAFEN_SFT 8 |
| #define RG_AUDPREAMPAAFEN_MASK 0x1 |
| #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8) |
| #define RG_DCCVCMBUFLPMODSEL_SFT 9 |
| #define RG_DCCVCMBUFLPMODSEL_MASK 0x1 |
| #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9) |
| #define RG_DCCVCMBUFLPSWEN_SFT 10 |
| #define RG_DCCVCMBUFLPSWEN_MASK 0x1 |
| #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10) |
| #define RG_AUDSPAREPGA_SFT 11 |
| #define RG_AUDSPAREPGA_MASK 0x1 |
| #define RG_AUDSPAREPGA_MASK_SFT (0x1 << 11) |
| |
| /* AUDENC_ANA_CON4 */ |
| #define RG_AUDADC1STSTAGESDENB_SFT 0 |
| #define RG_AUDADC1STSTAGESDENB_MASK 0x1 |
| #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADC2NDSTAGERESET_SFT 1 |
| #define RG_AUDADC2NDSTAGERESET_MASK 0x1 |
| #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1) |
| #define RG_AUDADC3RDSTAGERESET_SFT 2 |
| #define RG_AUDADC3RDSTAGERESET_MASK 0x1 |
| #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2) |
| #define RG_AUDADCFSRESET_SFT 3 |
| #define RG_AUDADCFSRESET_MASK 0x1 |
| #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3) |
| #define RG_AUDADCWIDECM_SFT 4 |
| #define RG_AUDADCWIDECM_MASK 0x1 |
| #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCNOPATEST_SFT 5 |
| #define RG_AUDADCNOPATEST_MASK 0x1 |
| #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5) |
| #define RG_AUDADCBYPASS_SFT 6 |
| #define RG_AUDADCBYPASS_MASK 0x1 |
| #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6) |
| #define RG_AUDADCFFBYPASS_SFT 7 |
| #define RG_AUDADCFFBYPASS_MASK 0x1 |
| #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7) |
| #define RG_AUDADCDACFBCURRENT_SFT 8 |
| #define RG_AUDADCDACFBCURRENT_MASK 0x1 |
| #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8) |
| #define RG_AUDADCDACIDDTEST_SFT 9 |
| #define RG_AUDADCDACIDDTEST_MASK 0x3 |
| #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9) |
| #define RG_AUDADCDACNRZ_SFT 11 |
| #define RG_AUDADCDACNRZ_MASK 0x1 |
| #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11) |
| #define RG_AUDADCNODEM_SFT 12 |
| #define RG_AUDADCNODEM_MASK 0x1 |
| #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12) |
| #define RG_AUDADCDACTEST_SFT 13 |
| #define RG_AUDADCDACTEST_MASK 0x1 |
| #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13) |
| |
| /* AUDENC_ANA_CON5 */ |
| #define RG_CLKSQ_EN_SFT 0 |
| #define RG_CLKSQ_EN_MASK 0x1 |
| #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0) |
| #define RG_CLKSQ_IN_SEL_SFT 1 |
| #define RG_CLKSQ_IN_SEL_MASK 0x1 |
| #define RG_CLKSQ_IN_SEL_MASK_SFT (0x1 << 1) |
| #define RG_AUDSPARE2VA28_SFT 2 |
| #define RG_AUDSPARE2VA28_MASK 0x3fff |
| #define RG_AUDSPARE2VA28_MASK_SFT (0x3fff << 2) |
| |
| /* AUDENC_ANA_CON6 */ |
| #define RG_AUDRCTUNEL_SFT 0 |
| #define RG_AUDRCTUNEL_MASK 0x1f |
| #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0) |
| #define RG_AUDRCTUNELSEL_SFT 5 |
| #define RG_AUDRCTUNELSEL_MASK 0x1 |
| #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5) |
| #define RG_AUDRCTUNER_SFT 8 |
| #define RG_AUDRCTUNER_MASK 0x1f |
| #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8) |
| #define RG_AUDRCTUNERSEL_SFT 13 |
| #define RG_AUDRCTUNERSEL_MASK 0x1 |
| #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13) |
| |
| /* AUDENC_ANA_CON7 */ |
| #define RG_AUDSPAREVA28_SFT 0 |
| #define RG_AUDSPAREVA28_MASK 0xf |
| #define RG_AUDSPAREVA28_MASK_SFT (0xf << 0) |
| #define RG_AUDSPAREVA18_SFT 4 |
| #define RG_AUDSPAREVA18_MASK 0xf |
| #define RG_AUDSPAREVA18_MASK_SFT (0xf << 4) |
| #define RG_AUDENCSPAREVA28_SFT 8 |
| #define RG_AUDENCSPAREVA28_MASK 0xf |
| #define RG_AUDENCSPAREVA28_MASK_SFT (0xf << 8) |
| #define RG_AUDENCSPAREVA18_SFT 12 |
| #define RG_AUDENCSPAREVA18_MASK 0xf |
| #define RG_AUDENCSPAREVA18_MASK_SFT (0xf << 12) |
| |
| /* AUDENC_ANA_CON8 */ |
| #define RG_AUDDIGMICEN_SFT 0 |
| #define RG_AUDDIGMICEN_MASK 0x1 |
| #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0) |
| #define RG_AUDDIGMICBIAS_SFT 1 |
| #define RG_AUDDIGMICBIAS_MASK 0x3 |
| #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1) |
| #define RG_DMICHPCLKEN_SFT 3 |
| #define RG_DMICHPCLKEN_MASK 0x1 |
| #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDDIGMICPDUTY_SFT 4 |
| #define RG_AUDDIGMICPDUTY_MASK 0x3 |
| #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4) |
| #define RG_AUDDIGMICNDUTY_SFT 6 |
| #define RG_AUDDIGMICNDUTY_MASK 0x3 |
| #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6) |
| #define RG_DMICMONEN_SFT 8 |
| #define RG_DMICMONEN_MASK 0x1 |
| #define RG_DMICMONEN_MASK_SFT (0x1 << 8) |
| #define RG_DMICMONSEL_SFT 9 |
| #define RG_DMICMONSEL_MASK 0x7 |
| #define RG_DMICMONSEL_MASK_SFT (0x7 << 9) |
| #define RG_AUDSPAREVMIC_SFT 12 |
| #define RG_AUDSPAREVMIC_MASK 0xf |
| #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12) |
| |
| /* AUDENC_ANA_CON9 */ |
| #define RG_AUDPWDBMICBIAS0_SFT 0 |
| #define RG_AUDPWDBMICBIAS0_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS0BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS0LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS0LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS0VREF_SFT 4 |
| #define RG_AUDMICBIAS0VREF_MASK 0x7 |
| #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4) |
| #define RG_AUDMICBIAS0DCSW0P1EN_SFT 8 |
| #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8) |
| #define RG_AUDMICBIAS0DCSW0P2EN_SFT 9 |
| #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9) |
| #define RG_AUDMICBIAS0DCSW0NEN_SFT 10 |
| #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10) |
| #define RG_AUDMICBIAS0DCSW2P1EN_SFT 12 |
| #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12) |
| #define RG_AUDMICBIAS0DCSW2P2EN_SFT 13 |
| #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13) |
| #define RG_AUDMICBIAS0DCSW2NEN_SFT 14 |
| #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14) |
| |
| /* AUDENC_ANA_CON10 */ |
| #define RG_AUDPWDBMICBIAS1_SFT 0 |
| #define RG_AUDPWDBMICBIAS1_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS1BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS1LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS1LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS1VREF_SFT 4 |
| #define RG_AUDMICBIAS1VREF_MASK 0x7 |
| #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4) |
| #define RG_AUDMICBIAS1DCSW1PEN_SFT 8 |
| #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1 |
| #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8) |
| #define RG_AUDMICBIAS1DCSW1NEN_SFT 9 |
| #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1 |
| #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9) |
| #define RG_BANDGAPGEN_SFT 12 |
| #define RG_BANDGAPGEN_MASK 0x1 |
| #define RG_BANDGAPGEN_MASK_SFT (0x1 << 12) |
| |
| /* AUDENC_ANA_CON11 */ |
| #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0 |
| #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0) |
| #define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1 |
| #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1) |
| #define RG_AUDACCDETVIN1PULLLOW_SFT 2 |
| #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 2) |
| #define RG_AUDACCDETVTHACAL_SFT 4 |
| #define RG_AUDACCDETVTHACAL_MASK 0x1 |
| #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4) |
| #define RG_AUDACCDETVTHBCAL_SFT 5 |
| #define RG_AUDACCDETVTHBCAL_MASK 0x1 |
| #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5) |
| #define RG_AUDACCDETTVDET_SFT 6 |
| #define RG_AUDACCDETTVDET_MASK 0x1 |
| #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6) |
| #define RG_ACCDETSEL_SFT 7 |
| #define RG_ACCDETSEL_MASK 0x1 |
| #define RG_ACCDETSEL_MASK_SFT (0x1 << 7) |
| #define RG_SWBUFMODSEL_SFT 8 |
| #define RG_SWBUFMODSEL_MASK 0x1 |
| #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8) |
| #define RG_SWBUFSWEN_SFT 9 |
| #define RG_SWBUFSWEN_MASK 0x1 |
| #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9) |
| #define RG_EINTCOMPVTH_SFT 10 |
| #define RG_EINTCOMPVTH_MASK 0x1 |
| #define RG_EINTCOMPVTH_MASK_SFT (0x1 << 10) |
| #define RG_EINTCONFIGACCDET_SFT 11 |
| #define RG_EINTCONFIGACCDET_MASK 0x1 |
| #define RG_EINTCONFIGACCDET_MASK_SFT (0x1 << 11) |
| #define RG_EINTHIRENB_SFT 12 |
| #define RG_EINTHIRENB_MASK 0x1 |
| #define RG_EINTHIRENB_MASK_SFT (0x1 << 12) |
| #define RG_ACCDETSPAREVA28_SFT 13 |
| #define RG_ACCDETSPAREVA28_MASK 0x7 |
| #define RG_ACCDETSPAREVA28_MASK_SFT (0x7 << 13) |
| |
| /* AUDENC_ANA_CON12 */ |
| #define RGS_AUDRCTUNELREAD_SFT 0 |
| #define RGS_AUDRCTUNELREAD_MASK 0x1f |
| #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0) |
| #define RGS_AUDRCTUNERREAD_SFT 8 |
| #define RGS_AUDRCTUNERREAD_MASK 0x1f |
| #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8) |
| |
| /* AUDDEC_DSN_ID */ |
| #define AUDDEC_ANA_ID_SFT 0 |
| #define AUDDEC_ANA_ID_MASK 0xff |
| #define AUDDEC_ANA_ID_MASK_SFT (0xff << 0) |
| #define AUDDEC_DIG_ID_SFT 8 |
| #define AUDDEC_DIG_ID_MASK 0xff |
| #define AUDDEC_DIG_ID_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_DSN_REV0 */ |
| #define AUDDEC_ANA_MINOR_REV_SFT 0 |
| #define AUDDEC_ANA_MINOR_REV_MASK 0xf |
| #define AUDDEC_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDDEC_ANA_MAJOR_REV_SFT 4 |
| #define AUDDEC_ANA_MAJOR_REV_MASK 0xf |
| #define AUDDEC_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| #define AUDDEC_DIG_MINOR_REV_SFT 8 |
| #define AUDDEC_DIG_MINOR_REV_MASK 0xf |
| #define AUDDEC_DIG_MINOR_REV_MASK_SFT (0xf << 8) |
| #define AUDDEC_DIG_MAJOR_REV_SFT 12 |
| #define AUDDEC_DIG_MAJOR_REV_MASK 0xf |
| #define AUDDEC_DIG_MAJOR_REV_MASK_SFT (0xf << 12) |
| |
| /* AUDDEC_DSN_DBI */ |
| #define AUDDEC_DSN_CBS_SFT 0 |
| #define AUDDEC_DSN_CBS_MASK 0x3 |
| #define AUDDEC_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDDEC_DSN_BIX_SFT 2 |
| #define AUDDEC_DSN_BIX_MASK 0x3 |
| #define AUDDEC_DSN_BIX_MASK_SFT (0x3 << 2) |
| #define AUDDEC_DSN_ESP_SFT 8 |
| #define AUDDEC_DSN_ESP_MASK 0xff |
| #define AUDDEC_DSN_ESP_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_DSN_FPI */ |
| #define AUDDEC_DSN_FPI_SFT 0 |
| #define AUDDEC_DSN_FPI_MASK 0xff |
| #define AUDDEC_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_ANA_CON0 */ |
| #define RG_AUDDACLPWRUP_VAUDP15_SFT 0 |
| #define RG_AUDDACLPWRUP_VAUDP15_MASK 0x1 |
| #define RG_AUDDACLPWRUP_VAUDP15_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACRPWRUP_VAUDP15_SFT 1 |
| #define RG_AUDDACRPWRUP_VAUDP15_MASK 0x1 |
| #define RG_AUDDACRPWRUP_VAUDP15_MASK_SFT (0x1 << 1) |
| #define RG_AUD_DAC_PWR_UP_VA28_SFT 2 |
| #define RG_AUD_DAC_PWR_UP_VA28_MASK 0x1 |
| #define RG_AUD_DAC_PWR_UP_VA28_MASK_SFT (0x1 << 2) |
| #define RG_AUD_DAC_PWL_UP_VA28_SFT 3 |
| #define RG_AUD_DAC_PWL_UP_VA28_MASK 0x1 |
| #define RG_AUD_DAC_PWL_UP_VA28_MASK_SFT (0x1 << 3) |
| #define RG_AUDOUT0_MUX_VAUDP28_SFT 4 |
| #define RG_AUDOUT0_MUX_VAUDP28_MASK 0x7 |
| #define RG_AUDOUT0_MUX_VAUDP28_MASK_SFT (0x7 << 4) |
| #define RG_AUDOUT1_MUX_VAUDP28_SFT 8 |
| #define RG_AUDOUT1_MUX_VAUDP28_MASK 0x7 |
| #define RG_AUDOUT1_MUX_VAUDP28_MASK_SFT (0x7 << 8) |
| #define RG_AUDOUT2_MUX_VAUDP28_SFT 12 |
| #define RG_AUDOUT2_MUX_VAUDP28_MASK 0x7 |
| #define RG_AUDOUT2_MUX_VAUDP28_MASK_SFT (0x7 << 12) |
| |
| /* AUDDEC_ANA_CON1 */ |
| #define RG_AUDVCMBUF_EN_VAUDP28_SFT 0 |
| #define RG_AUDVCMBUF_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT (0x1 << 0) |
| #define RG_AUDVCMBUF_VOSEL_VAUDP28_SFT 4 |
| #define RG_AUDVCMBUF_VOSEL_VAUDP28_MASK 0x7 |
| #define RG_AUDVCMBUF_VOSEL_VAUDP28_MASK_SFT (0x7 << 4) |
| #define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_SFT 8 |
| #define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_MASK_SFT (0x1 << 8) |
| #define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_SFT 9 |
| #define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_MASK_SFT (0x1 << 9) |
| #define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_SFT 10 |
| #define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_MASK_SFT (0x1 << 10) |
| #define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_SFT 11 |
| #define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_MASK_SFT (0x1 << 11) |
| #define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_SFT 12 |
| #define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_MASK_SFT (0x1 << 12) |
| #define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_SFT 13 |
| #define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_MASK_SFT (0x1 << 13) |
| |
| /* AUDDEC_ANA_CON2 */ |
| #define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_SFT 0 |
| #define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_MASK_SFT (0x1 << 0) |
| #define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_SFT 1 |
| #define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_MASK_SFT (0x1 << 1) |
| #define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_SFT 2 |
| #define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_MASK_SFT (0x1 << 2) |
| #define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_SFT 3 |
| #define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_MASK_SFT (0x1 << 3) |
| #define RG_AUDREFN_DERES_EN_VAUDP28_SFT 4 |
| #define RG_AUDREFN_DERES_EN_VAUDP28_MASK 0x1 |
| #define RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT (0x1 << 4) |
| #define RG_ABIDEC_RSVD0_VAUDP28_SFT 8 |
| #define RG_ABIDEC_RSVD0_VAUDP28_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VAUDP28_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_ANA_CON3 */ |
| #define RG_ABIDEC_RSVD1_VAUDP28_SFT 0 |
| #define RG_ABIDEC_RSVD1_VAUDP28_MASK 0xff |
| #define RG_ABIDEC_RSVD1_VAUDP28_MASK_SFT (0xff << 0) |
| #define RG_ABIDEC_RSVD2_VAUDP28_SFT 8 |
| #define RG_ABIDEC_RSVD2_VAUDP28_MASK 0xff |
| #define RG_ABIDEC_RSVD2_VAUDP28_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_ANA_CON4 */ |
| #define RG_AUDHSPWRUP_VAUDP15_SFT 0 |
| #define RG_AUDHSPWRUP_VAUDP15_MASK 0x1 |
| #define RG_AUDHSPWRUP_VAUDP15_MASK_SFT (0x1 << 0) |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP15_SFT 1 |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1 |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1) |
| #define RG_AUDHSMUXINPUTSEL_VAUDP15_SFT 2 |
| #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3 |
| #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2) |
| #define RG_AUDHSSCDISABLE_VAUDP15_SFT 4 |
| #define RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1 |
| #define RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4) |
| #define RG_AUDHSBSCCURRENT_VAUDP15_SFT 5 |
| #define RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1 |
| #define RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5) |
| #define RG_AUDHSSTARTUP_VAUDP15_SFT 6 |
| #define RG_AUDHSSTARTUP_VAUDP15_MASK 0x1 |
| #define RG_AUDHSSTARTUP_VAUDP15_MASK_SFT (0x1 << 6) |
| #define RG_HSOUTPUTSTBENH_VAUDP15_SFT 7 |
| #define RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1 |
| #define RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7) |
| #define RG_HSINPUTSTBENH_VAUDP15_SFT 8 |
| #define RG_HSINPUTSTBENH_VAUDP15_MASK 0x1 |
| #define RG_HSINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8) |
| #define RG_HSINPUTRESET0_VAUDP15_SFT 9 |
| #define RG_HSINPUTRESET0_VAUDP15_MASK 0x1 |
| #define RG_HSINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9) |
| #define RG_HSOUTPUTRESET0_VAUDP15_SFT 10 |
| #define RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1 |
| #define RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10) |
| #define RG_HSOUT_SHORTVCM_VAUDP15_SFT 11 |
| #define RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1 |
| #define RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11) |
| |
| /* AUDDEC_ANA_CON5 */ |
| #define RG_AUDLOLPWRUP_VAUDP15_SFT 0 |
| #define RG_AUDLOLPWRUP_VAUDP15_MASK 0x1 |
| #define RG_AUDLOLPWRUP_VAUDP15_MASK_SFT (0x1 << 0) |
| #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_SFT 1 |
| #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1 |
| #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1) |
| #define RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT 2 |
| #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK 0x3 |
| #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2) |
| #define RG_AUDLOLSCDISABLE_VAUDP15_SFT 4 |
| #define RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1 |
| #define RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4) |
| #define RG_AUDLOLBSCCURRENT_VAUDP15_SFT 5 |
| #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1 |
| #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5) |
| #define RG_AUDLOSTARTUP_VAUDP15_SFT 6 |
| #define RG_AUDLOSTARTUP_VAUDP15_MASK 0x1 |
| #define RG_AUDLOSTARTUP_VAUDP15_MASK_SFT (0x1 << 6) |
| #define RG_LOINPUTSTBENH_VAUDP15_SFT 7 |
| #define RG_LOINPUTSTBENH_VAUDP15_MASK 0x1 |
| #define RG_LOINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7) |
| #define RG_LOOUTPUTSTBENH_VAUDP15_SFT 8 |
| #define RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1 |
| #define RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8) |
| #define RG_LOINPUTRESET0_VAUDP15_SFT 9 |
| #define RG_LOINPUTRESET0_VAUDP15_MASK 0x1 |
| #define RG_LOINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9) |
| #define RG_LOOUTPUTRESET0_VAUDP15_SFT 10 |
| #define RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1 |
| #define RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10) |
| #define RG_LOOUT_SHORTVCM_VAUDP15_SFT 11 |
| #define RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1 |
| #define RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11) |
| |
| /* AUDDEC_ANA_CON6 */ |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SFT 0 |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xf |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK_SFT (0xf << 0) |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_SFT 4 |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3 |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK_SFT (0x3 << 4) |
| #define RG_AUDTRIMBUF_EN_VAUDP15_SFT 6 |
| #define RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1 |
| #define RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT (0x1 << 6) |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SFT 8 |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3 |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 8) |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SFT 10 |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3 |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 10) |
| #define RG_AUDHPSPKDET_EN_VAUDP15_SFT 12 |
| #define RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1 |
| #define RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT (0x1 << 12) |
| |
| /* AUDDEC_ANA_CON7 */ |
| #define RG_ABIDEC_RSVD0_VA28_SFT 0 |
| #define RG_ABIDEC_RSVD0_VA28_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VA28_MASK_SFT (0xff << 0) |
| #define RG_ABIDEC_RSVD0_VAUDP15_SFT 8 |
| #define RG_ABIDEC_RSVD0_VAUDP15_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VAUDP15_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_ANA_CON8 */ |
| #define RG_ABIDEC_RSVD1_VAUDP15_SFT 0 |
| #define RG_ABIDEC_RSVD1_VAUDP15_MASK 0xff |
| #define RG_ABIDEC_RSVD1_VAUDP15_MASK_SFT (0xff << 0) |
| #define RG_ABIDEC_RSVD2_VAUDP15_SFT 8 |
| #define RG_ABIDEC_RSVD2_VAUDP15_MASK 0xff |
| #define RG_ABIDEC_RSVD2_VAUDP15_MASK_SFT (0xff << 8) |
| |
| /* AUDDEC_ANA_CON9 */ |
| #define RG_AUDZCDMUXSEL_VAUDP15_SFT 0 |
| #define RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7 |
| #define RG_AUDZCDMUXSEL_VAUDP15_MASK_SFT (0x7 << 0) |
| #define RG_AUDZCDCLKSEL_VAUDP15_SFT 3 |
| #define RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1 |
| #define RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT (0x1 << 3) |
| #define RG_AUDBIASADJ_0_VAUDP15_SFT 7 |
| #define RG_AUDBIASADJ_0_VAUDP15_MASK 0x1ff |
| #define RG_AUDBIASADJ_0_VAUDP15_MASK_SFT (0x1ff << 7) |
| |
| /* AUDDEC_ANA_CON10 */ |
| #define RG_AUDBIASADJ_1_VAUDP15_SFT 0 |
| #define RG_AUDBIASADJ_1_VAUDP15_MASK 0xff |
| #define RG_AUDBIASADJ_1_VAUDP15_MASK_SFT (0xff << 0) |
| #define RG_AUDIBIASPWRDN_VAUDP15_SFT 8 |
| #define RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1 |
| #define RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT (0x1 << 8) |
| |
| /* AUDDEC_ANA_CON11 */ |
| #define RG_RSTB_DECODER_VA28_SFT 0 |
| #define RG_RSTB_DECODER_VA28_MASK 0x1 |
| #define RG_RSTB_DECODER_VA28_MASK_SFT (0x1 << 0) |
| #define RG_SEL_DECODER_96K_VA28_SFT 1 |
| #define RG_SEL_DECODER_96K_VA28_MASK 0x1 |
| #define RG_SEL_DECODER_96K_VA28_MASK_SFT (0x1 << 1) |
| #define RG_SEL_DELAY_VCORE_SFT 2 |
| #define RG_SEL_DELAY_VCORE_MASK 0x1 |
| #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2) |
| #define RG_AUDGLB_PWRDN_VA28_SFT 4 |
| #define RG_AUDGLB_PWRDN_VA28_MASK 0x1 |
| #define RG_AUDGLB_PWRDN_VA28_MASK_SFT (0x1 << 4) |
| #define RG_RSTB_ENCODER_VA28_SFT 5 |
| #define RG_RSTB_ENCODER_VA28_MASK 0x1 |
| #define RG_RSTB_ENCODER_VA28_MASK_SFT (0x1 << 5) |
| #define RG_SEL_ENCODER_96K_VA28_SFT 6 |
| #define RG_SEL_ENCODER_96K_VA28_MASK 0x1 |
| #define RG_SEL_ENCODER_96K_VA28_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_ANA_CON12 */ |
| #define RG_HCLDO_EN_VA18_SFT 0 |
| #define RG_HCLDO_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_EN_VA18_MASK_SFT (0x1 << 0) |
| #define RG_HCLDO_PDDIS_EN_VA18_SFT 1 |
| #define RG_HCLDO_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 1) |
| #define RG_HCLDO_REMOTE_SENSE_VA18_SFT 2 |
| #define RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2) |
| #define RG_LCLDO_EN_VA18_SFT 4 |
| #define RG_LCLDO_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_EN_VA18_MASK_SFT (0x1 << 4) |
| #define RG_LCLDO_PDDIS_EN_VA18_SFT 5 |
| #define RG_LCLDO_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 5) |
| #define RG_LCLDO_REMOTE_SENSE_VA18_SFT 6 |
| #define RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 6) |
| #define RG_LCLDO_ENC_EN_VA28_SFT 8 |
| #define RG_LCLDO_ENC_EN_VA28_MASK 0x1 |
| #define RG_LCLDO_ENC_EN_VA28_MASK_SFT (0x1 << 8) |
| #define RG_LCLDO_ENC_PDDIS_EN_VA28_SFT 9 |
| #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1 |
| #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT (0x1 << 9) |
| #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_SFT 10 |
| #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1 |
| #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT (0x1 << 10) |
| #define RG_VA33REFGEN_EN_VA18_SFT 12 |
| #define RG_VA33REFGEN_EN_VA18_MASK 0x1 |
| #define RG_VA33REFGEN_EN_VA18_MASK_SFT (0x1 << 12) |
| #define RG_VA28REFGEN_EN_VA28_SFT 13 |
| #define RG_VA28REFGEN_EN_VA28_MASK 0x1 |
| #define RG_VA28REFGEN_EN_VA28_MASK_SFT (0x1 << 13) |
| #define RG_HCLDO_VOSEL_VA18_SFT 14 |
| #define RG_HCLDO_VOSEL_VA18_MASK 0x1 |
| #define RG_HCLDO_VOSEL_VA18_MASK_SFT (0x1 << 14) |
| #define RG_LCLDO_VOSEL_VA18_SFT 15 |
| #define RG_LCLDO_VOSEL_VA18_MASK 0x1 |
| #define RG_LCLDO_VOSEL_VA18_MASK_SFT (0x1 << 15) |
| |
| /* AUDDEC_ANA_CON13 */ |
| #define RG_NVREG_EN_VAUDP15_SFT 0 |
| #define RG_NVREG_EN_VAUDP15_MASK 0x1 |
| #define RG_NVREG_EN_VAUDP15_MASK_SFT (0x1 << 0) |
| #define RG_NVREG_PULL0V_VAUDP15_SFT 1 |
| #define RG_NVREG_PULL0V_VAUDP15_MASK 0x1 |
| #define RG_NVREG_PULL0V_VAUDP15_MASK_SFT (0x1 << 1) |
| #define RG_AUDPMU_RSD0_VAUDP15_SFT 4 |
| #define RG_AUDPMU_RSD0_VAUDP15_MASK 0xf |
| #define RG_AUDPMU_RSD0_VAUDP15_MASK_SFT (0xf << 4) |
| #define RG_AUDPMU_RSD0_VA18_SFT 8 |
| #define RG_AUDPMU_RSD0_VA18_MASK 0xf |
| #define RG_AUDPMU_RSD0_VA18_MASK_SFT (0xf << 8) |
| #define RG_AUDPMU_RSD0_VA28_SFT 12 |
| #define RG_AUDPMU_RSD0_VA28_MASK 0xf |
| #define RG_AUDPMU_RSD0_VA28_MASK_SFT (0xf << 12) |
| |
| /* AUDDEC_ELR_NUM */ |
| #define AUDDEC_ELR_LEN_SFT 0 |
| #define AUDDEC_ELR_LEN_MASK 0xff |
| #define AUDDEC_ELR_LEN_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_ELR_0 */ |
| #define RG_AUDHSTRIM_VAUDP15_SFT 0 |
| #define RG_AUDHSTRIM_VAUDP15_MASK 0xf |
| #define RG_AUDHSTRIM_VAUDP15_MASK_SFT (0xf << 0) |
| #define RG_AUDHSFINETRIM_VAUDP15_SFT 4 |
| #define RG_AUDHSFINETRIM_VAUDP15_MASK 0x3 |
| #define RG_AUDHSFINETRIM_VAUDP15_MASK_SFT (0x3 << 4) |
| #define RG_AUDHSTRIM_EN_VAUDP15_SFT 6 |
| #define RG_AUDHSTRIM_EN_VAUDP15_MASK 0x1 |
| #define RG_AUDHSTRIM_EN_VAUDP15_MASK_SFT (0x1 << 6) |
| #define RG_AUDLOLTRIM_VAUDP15_SFT 7 |
| #define RG_AUDLOLTRIM_VAUDP15_MASK 0xf |
| #define RG_AUDLOLTRIM_VAUDP15_MASK_SFT (0xf << 7) |
| #define RG_AUDLOLFINETRIM_VAUDP15_SFT 11 |
| #define RG_AUDLOLFINETRIM_VAUDP15_MASK 0x3 |
| #define RG_AUDLOLFINETRIM_VAUDP15_MASK_SFT (0x3 << 11) |
| #define RG_AUDLOLTRIM_EN_VAUDP15_SFT 13 |
| #define RG_AUDLOLTRIM_EN_VAUDP15_MASK 0x1 |
| #define RG_AUDLOLTRIM_EN_VAUDP15_MASK_SFT (0x1 << 13) |
| |
| /* AUDZCD_DSN_ID */ |
| #define AUDZCD_ANA_ID_SFT 0 |
| #define AUDZCD_ANA_ID_MASK 0xff |
| #define AUDZCD_ANA_ID_MASK_SFT (0xff << 0) |
| #define AUDZCD_DIG_ID_SFT 8 |
| #define AUDZCD_DIG_ID_MASK 0xff |
| #define AUDZCD_DIG_ID_MASK_SFT (0xff << 8) |
| |
| /* AUDZCD_DSN_REV0 */ |
| #define AUDZCD_ANA_MINOR_REV_SFT 0 |
| #define AUDZCD_ANA_MINOR_REV_MASK 0xf |
| #define AUDZCD_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDZCD_ANA_MAJOR_REV_SFT 4 |
| #define AUDZCD_ANA_MAJOR_REV_MASK 0xf |
| #define AUDZCD_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| #define AUDZCD_DIG_MINOR_REV_SFT 8 |
| #define AUDZCD_DIG_MINOR_REV_MASK 0xf |
| #define AUDZCD_DIG_MINOR_REV_MASK_SFT (0xf << 8) |
| #define AUDZCD_DIG_MAJOR_REV_SFT 12 |
| #define AUDZCD_DIG_MAJOR_REV_MASK 0xf |
| #define AUDZCD_DIG_MAJOR_REV_MASK_SFT (0xf << 12) |
| |
| /* AUDZCD_DSN_DBI */ |
| #define AUDZCD_DSN_CBS_SFT 0 |
| #define AUDZCD_DSN_CBS_MASK 0x3 |
| #define AUDZCD_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDZCD_DSN_BIX_SFT 2 |
| #define AUDZCD_DSN_BIX_MASK 0x3 |
| #define AUDZCD_DSN_BIX_MASK_SFT (0x3 << 2) |
| #define AUDZCD_DSN_ESP_SFT 8 |
| #define AUDZCD_DSN_ESP_MASK 0xff |
| #define AUDZCD_DSN_ESP_MASK_SFT (0xff << 8) |
| |
| /* AUDZCD_DSN_FPI */ |
| #define AUDZCD_DSN_FPI_SFT 0 |
| #define AUDZCD_DSN_FPI_MASK 0xff |
| #define AUDZCD_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* ZCD_CON0 */ |
| #define RG_AUDZCDENABLE_SFT 0 |
| #define RG_AUDZCDENABLE_MASK 0x1 |
| #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0) |
| #define RG_AUDZCDGAINSTEPTIME_SFT 1 |
| #define RG_AUDZCDGAINSTEPTIME_MASK 0x7 |
| #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1) |
| #define RG_AUDZCDGAINSTEPSIZE_SFT 4 |
| #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3 |
| #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4) |
| #define RG_AUDZCDTIMEOUTMODESEL_SFT 6 |
| #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1 |
| #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6) |
| |
| /* ZCD_CON1 */ |
| #define RG_AUDLOLGAIN_SFT 0 |
| #define RG_AUDLOLGAIN_MASK 0x1f |
| #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0) |
| #define RG_AUDLORGAIN_SFT 7 |
| #define RG_AUDLORGAIN_MASK 0x1f |
| #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7) |
| |
| /* ZCD_CON2 */ |
| #define RG_AUDHPLGAIN_SFT 0 |
| #define RG_AUDHPLGAIN_MASK 0x1f |
| #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0) |
| #define RG_AUDHPRGAIN_SFT 7 |
| #define RG_AUDHPRGAIN_MASK 0x1f |
| #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7) |
| |
| /* ZCD_CON3 */ |
| #define RG_AUDHSGAIN_SFT 0 |
| #define RG_AUDHSGAIN_MASK 0x1f |
| #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON4 */ |
| #define RG_AUDIVLGAIN_SFT 0 |
| #define RG_AUDIVLGAIN_MASK 0x7 |
| #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0) |
| #define RG_AUDIVRGAIN_SFT 8 |
| #define RG_AUDIVRGAIN_MASK 0x7 |
| #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8) |
| |
| /* ZCD_CON5 */ |
| #define RG_AUDINTGAIN1_SFT 0 |
| #define RG_AUDINTGAIN1_MASK 0x3f |
| #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0) |
| #define RG_AUDINTGAIN2_SFT 8 |
| #define RG_AUDINTGAIN2_MASK 0x3f |
| #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8) |
| |
| /* audio register */ |
| #define MT6389_DRV_CON3 0x3c |
| #define MT6389_GPIO_DIR0 0x88 |
| |
| #define MT6389_GPIO_MODE2 0xd8 /* mosi */ |
| #define MT6389_GPIO_MODE2_SET 0xda |
| #define MT6389_GPIO_MODE2_CLR 0xdc |
| |
| #define MT6389_GPIO_MODE3 0xde /* miso */ |
| #define MT6389_GPIO_MODE3_SET 0xe0 |
| #define MT6389_GPIO_MODE3_CLR 0xe2 |
| |
| #define MT6389_DCXO_CW12 0x7a8 |
| |
| #define MT6389_AUXADC_CON10 0x11a0 |
| #define MT6389_SMT_CON1 0x32 |
| #define MT6389_LDO_VAUD28_CON0 0x1dbe |
| |
| /* audio register */ |
| #define MT6389_AUD_TOP_ID 0x2480 |
| #define MT6389_AUD_TOP_REV0 0x2482 |
| #define MT6389_AUD_TOP_DBI 0x2484 |
| #define MT6389_AUD_TOP_DXI 0x2486 |
| #define MT6389_AUD_TOP_CKPDN_TPM0 0x2488 |
| #define MT6389_AUD_TOP_CKPDN_TPM1 0x248a |
| #define MT6389_AUD_TOP_CKPDN_CON0 0x248c |
| #define MT6389_AUD_TOP_CKPDN_CON0_SET 0x248e |
| #define MT6389_AUD_TOP_CKPDN_CON0_CLR 0x2490 |
| #define MT6389_AUD_TOP_CKSEL_CON0 0x2492 |
| #define MT6389_AUD_TOP_CKSEL_CON0_SET 0x2494 |
| #define MT6389_AUD_TOP_CKSEL_CON0_CLR 0x2496 |
| #define MT6389_AUD_TOP_CKTST_CON0 0x2498 |
| #define MT6389_AUD_TOP_CLK_HWEN_CON0 0x249a |
| #define MT6389_AUD_TOP_CLK_HWEN_CON0_SET 0x249c |
| #define MT6389_AUD_TOP_CLK_HWEN_CON0_CLR 0x249e |
| #define MT6389_AUD_TOP_RST_CON0 0x24a0 |
| #define MT6389_AUD_TOP_RST_CON0_SET 0x24a2 |
| #define MT6389_AUD_TOP_RST_CON0_CLR 0x24a4 |
| #define MT6389_AUD_TOP_RST_BANK_CON0 0x24a6 |
| #define MT6389_AUD_TOP_INT_CON0 0x24a8 |
| #define MT6389_AUD_TOP_INT_CON0_SET 0x24aa |
| #define MT6389_AUD_TOP_INT_CON0_CLR 0x24ac |
| #define MT6389_AUD_TOP_INT_MASK_CON0 0x24ae |
| #define MT6389_AUD_TOP_INT_MASK_CON0_SET 0x24b0 |
| #define MT6389_AUD_TOP_INT_MASK_CON0_CLR 0x24b2 |
| #define MT6389_AUD_TOP_INT_STATUS0 0x24b4 |
| #define MT6389_AUD_TOP_INT_RAW_STATUS0 0x24b6 |
| #define MT6389_AUD_TOP_INT_MISC_CON0 0x24b8 |
| #define MT6389_AUDNCP_CLKDIV_CON0 0x24ba |
| #define MT6389_AUDNCP_CLKDIV_CON1 0x24bc |
| #define MT6389_AUDNCP_CLKDIV_CON2 0x24be |
| #define MT6389_AUDNCP_CLKDIV_CON3 0x24c0 |
| #define MT6389_AUDNCP_CLKDIV_CON4 0x24c2 |
| #define MT6389_AUD_TOP_MON_CON0 0x24c4 |
| #define MT6389_AUDIO_DIG_DSN_ID 0x2500 |
| #define MT6389_AUDIO_DIG_DSN_REV0 0x2502 |
| #define MT6389_AUDIO_DIG_DSN_DBI 0x2504 |
| #define MT6389_AUDIO_DIG_DSN_DXI 0x2506 |
| #define MT6389_AFE_UL_DL_CON0 0x2508 |
| #define MT6389_AFE_DL_SRC2_CON0_L 0x250a |
| #define MT6389_AFE_UL_SRC_CON0_H 0x250c |
| #define MT6389_AFE_UL_SRC_CON0_L 0x250e |
| #define MT6389_AFE_TOP_CON0 0x2510 |
| #define MT6389_AUDIO_TOP_CON0 0x2512 |
| #define MT6389_AFE_MON_DEBUG0 0x2514 |
| #define MT6389_AFUNC_AUD_CON0 0x2516 |
| #define MT6389_AFUNC_AUD_CON1 0x2518 |
| #define MT6389_AFUNC_AUD_CON2 0x251a |
| #define MT6389_AFUNC_AUD_CON3 0x251c |
| #define MT6389_AFUNC_AUD_CON4 0x251e |
| #define MT6389_AFUNC_AUD_CON5 0x2520 |
| #define MT6389_AFUNC_AUD_CON6 0x2522 |
| #define MT6389_AFUNC_AUD_MON0 0x2524 |
| #define MT6389_AUDRC_TUNE_MON0 0x2526 |
| #define MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0 0x2528 |
| #define MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x252a |
| #define MT6389_AFE_ADDA_MTKAIF_MON0 0x252c |
| #define MT6389_AFE_ADDA_MTKAIF_MON1 0x252e |
| #define MT6389_AFE_ADDA_MTKAIF_MON2 0x2530 |
| #define MT6389_AFE_ADDA_MTKAIF_MON3 0x2532 |
| #define MT6389_AFE_ADDA_MTKAIF_CFG0 0x2534 |
| #define MT6389_AFE_ADDA_MTKAIF_RX_CFG0 0x2536 |
| #define MT6389_AFE_ADDA_MTKAIF_RX_CFG1 0x2538 |
| #define MT6389_AFE_ADDA_MTKAIF_RX_CFG2 0x253a |
| #define MT6389_AFE_ADDA_MTKAIF_RX_CFG3 0x253c |
| #define MT6389_AFE_ADDA_MTKAIF_TX_CFG1 0x253e |
| #define MT6389_AFE_SGEN_CFG0 0x2540 |
| #define MT6389_AFE_SGEN_CFG1 0x2542 |
| #define MT6389_AFE_ADC_ASYNC_FIFO_CFG 0x2544 |
| #define MT6389_AFE_DCCLK_CFG0 0x2546 |
| #define MT6389_AFE_DCCLK_CFG1 0x2548 |
| #define MT6389_AUDIO_DIG_CFG 0x254a |
| #define MT6389_AFE_AUD_PAD_TOP 0x254c |
| #define MT6389_AFE_AUD_PAD_TOP_MON 0x254e |
| #define MT6389_AFE_AUD_PAD_TOP_MON1 0x2550 |
| #define MT6389_AFE_CG_EN_MON 0x2552 |
| #define MT6389_AUDENC_DSN_ID 0x2580 |
| #define MT6389_AUDENC_DSN_REV0 0x2582 |
| #define MT6389_AUDENC_DSN_DBI 0x2584 |
| #define MT6389_AUDENC_DSN_FPI 0x2586 |
| #define MT6389_AUDENC_ANA_CON0 0x2588 |
| #define MT6389_AUDENC_ANA_CON1 0x258a |
| #define MT6389_AUDENC_ANA_CON2 0x258c |
| #define MT6389_AUDENC_ANA_CON3 0x258e |
| #define MT6389_AUDENC_ANA_CON4 0x2590 |
| #define MT6389_AUDENC_ANA_CON5 0x2592 |
| #define MT6389_AUDENC_ANA_CON6 0x2594 |
| #define MT6389_AUDENC_ANA_CON7 0x2596 |
| #define MT6389_AUDENC_ANA_CON8 0x2598 |
| #define MT6389_AUDENC_ANA_CON9 0x259a |
| #define MT6389_AUDENC_ANA_CON10 0x259c |
| #define MT6389_AUDENC_ANA_CON11 0x259e |
| #define MT6389_AUDENC_ANA_CON12 0x25a0 |
| #define MT6389_AUDDEC_DSN_ID 0x2600 |
| #define MT6389_AUDDEC_DSN_REV0 0x2602 |
| #define MT6389_AUDDEC_DSN_DBI 0x2604 |
| #define MT6389_AUDDEC_DSN_FPI 0x2606 |
| #define MT6389_AUDDEC_ANA_CON0 0x2608 |
| #define MT6389_AUDDEC_ANA_CON1 0x260a |
| #define MT6389_AUDDEC_ANA_CON2 0x260c |
| #define MT6389_AUDDEC_ANA_CON3 0x260e |
| #define MT6389_AUDDEC_ANA_CON4 0x2610 |
| #define MT6389_AUDDEC_ANA_CON5 0x2612 |
| #define MT6389_AUDDEC_ANA_CON6 0x2614 |
| #define MT6389_AUDDEC_ANA_CON7 0x2616 |
| #define MT6389_AUDDEC_ANA_CON8 0x2618 |
| #define MT6389_AUDDEC_ANA_CON9 0x261a |
| #define MT6389_AUDDEC_ANA_CON10 0x261c |
| #define MT6389_AUDDEC_ANA_CON11 0x261e |
| #define MT6389_AUDDEC_ANA_CON12 0x2620 |
| #define MT6389_AUDDEC_ANA_CON13 0x2622 |
| #define MT6389_AUDDEC_ELR_NUM 0x2624 |
| #define MT6389_AUDDEC_ELR_0 0x2626 |
| #define MT6389_AUDZCD_DSN_ID 0x2680 |
| #define MT6389_AUDZCD_DSN_REV0 0x2682 |
| #define MT6389_AUDZCD_DSN_DBI 0x2684 |
| #define MT6389_AUDZCD_DSN_FPI 0x2686 |
| #define MT6389_ZCD_CON0 0x2688 |
| #define MT6389_ZCD_CON1 0x268a |
| #define MT6389_ZCD_CON2 0x268c |
| #define MT6389_ZCD_CON3 0x268e |
| #define MT6389_ZCD_CON4 0x2690 |
| #define MT6389_ZCD_CON5 0x2692 |
| |
| #define MT6389_MAX_REGISTER MT6389_ZCD_CON5 |
| |
| enum { |
| MT6389_MTKAIF_PROTOCOL_1 = 0, |
| MT6389_MTKAIF_PROTOCOL_2, |
| MT6389_MTKAIF_PROTOCOL_2_CLK_P2, |
| }; |
| |
| /* set only during init */ |
| struct mt6389_codec_ops { |
| int (*enable_dc_compensation)(bool enable); |
| int (*set_lch_dc_compensation)(int value); |
| int (*set_rch_dc_compensation)(int value); |
| int (*adda_dl_gain_control)(bool mute); |
| }; |
| |
| int mt6389_set_codec_ops(struct snd_soc_component *cmpnt, |
| struct mt6389_codec_ops *ops); |
| int mt6389_set_mtkaif_protocol(struct snd_soc_component *cmpnt, |
| int mtkaif_protocol); |
| int mt6389_mtkaif_calibration_enable(struct snd_soc_component *cmpnt); |
| int mt6389_mtkaif_calibration_disable(struct snd_soc_component *cmpnt); |
| int mt6389_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, |
| int phase_1, int phase_2); |
| |
| #endif /* __MT6389_H__ */ |
| |