Gitiles
Code Review Sign In
192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / dramk_2731 / dramc_pi_ddr_reserve.c
blob: 6429779f91a522fe04927c242830e3ee232aa720 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1#include "emi.h"
2#include "dramc_common.h"
3#include "dramc_pi_api.h"
4#include "x_hal_io.h"
5//#define DDR_RESERVE_MODE
6//#define USE_TA2_IN_DDR_RESERVE_MODE
7//#include "platform.h"
8//#include "wdt.h"
9//#endif
10
11#ifdef DDR_RESERVE_MODE
12#define LP3_CKE_FIX_ON_TO_LEAVE_SR_WITH_LVDRAM 0
13
14extern DRAMC_CTX_T *psCurrDramCtx;
15extern DRAMC_CTX_T DramCtx_LPDDR4;
16extern DRAMC_CTX_T DramCtx_LPDDR3;
17static U32 u4ReserveRegBackupAddress[] =
18{
19 (DRAMC_REG_SPCMDCTRL),
20 (DRAMC_REG_SPCMDCTRL + SHIFT_TO_CHB_ADDR),
21 (DRAMC_REG_SHU_SCINTV),
22 (DRAMC_REG_SHU_SCINTV + SHIFT_TO_CHB_ADDR),
23 (DRAMC_REG_DQSOSCR),
24 (DRAMC_REG_DQSOSCR + SHIFT_TO_CHB_ADDR),
25 (DRAMC_REG_DUMMY_RD),
26 (DRAMC_REG_DUMMY_RD + SHIFT_TO_CHB_ADDR),
27 (DRAMC_REG_DRAMC_PD_CTRL),
28 (DRAMC_REG_DRAMC_PD_CTRL + SHIFT_TO_CHB_ADDR),
29 (DDRPHY_MISC_SPM_CTRL1)
30};
31static U32 u4DramType = 0;
32
33#if LP3_CKE_FIX_ON_TO_LEAVE_SR_WITH_LVDRAM
34#if ENABLE_LP3_SW
35static U32 u4Cha_cke_backup = 0;
36static U32 u4Chb_cke_backup = 0;
37#endif
38#endif
39
40static int Reserve_Sync_Writel(unsigned long addr, unsigned int val)
41{
42 mt_reg_sync_writel(val, (volatile unsigned int *) addr);
43 return 0;
44}
45
46static unsigned int Reserve_Reg_Readl(unsigned long addr)
47{
48 return (*(volatile unsigned int *)(addr));
49}
50
51#define RE_POWERON_CONFIG_EN (0x10006000)
52#define RE_PCM_PWR_IO_EN (0x1000602C)
53#define RE_DRAMC_DPY_CLK_SW_CON_SEL (0x10006460)
54#define RE_DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006470)
55#define RE_SPM_S1_MODE_CH (0x10006468)
56void Set_Spm_Poweron_Config_En(DRAMC_CTX_T * p)
57{
58 U32 u4value = 0;
59
60 Reserve_Sync_Writel(RE_POWERON_CONFIG_EN, 0x0B160001);
61 Reserve_Sync_Writel(RE_PCM_PWR_IO_EN, 0);
62 u4value = (u1IsLP4Family(p->dram_type)) ? (0x00ffffff) : (0xaaffffff);
63 Reserve_Sync_Writel(RE_DRAMC_DPY_CLK_SW_CON_SEL, u4value);
64 Reserve_Sync_Writel(RE_DRAMC_DPY_CLK_SW_CON_SEL2, 0xffffffff);
65 u4value = Reserve_Reg_Readl(SPM_POWER_ON_VAL0);
66 u4value |= ((0x1 << 8) | (0x1 << 12) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15));
67 Reserve_Sync_Writel(SPM_POWER_ON_VAL0, u4value);
68 //u4value = Reserve_Reg_Readl(RE_SPM_S1_MODE_CH);
69 //u4value |= 0x3;
70 //Reserve_Sync_Writel(SPM_S1_MODE_CH, u4value);
71
72 return;
73}
74
75void dump_SR(DRAMC_CTX_T * p)//use after set correct u1ChannelSet
76{
77 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
78 U32 u4value = 0;
79 U8 u1ChIdx = CHANNEL_A;
80
81 for(u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
82 {
83 vSetPHY2ChannelMapping(p, u1ChannelSet[u1ChIdx]);
84 u4value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
85 mcSHOW_ERR_MSG(("###DDR reserve CH%d SREF_STATE[0x%X]\n", u1ChannelSet[u1ChIdx], u4value));
86 }
87
88 vSetPHY2ChannelMapping(p, (U8)eOriChannel);
89 return;
90}
91
92void dump_gating_error_rg(DRAMC_CTX_T * p)//use after set correct u1ChannelSet
93{
94 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
95 U32 u4value = 0;
96 U8 u1ChIdx = CHANNEL_A;
97
98 for(u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
99 {
100 vSetPHY2ChannelMapping(p, u1ChannelSet[u1ChIdx]);
101 u4value = u4IO32Read4B(DDRPHY_MISC_STBERR_RK0_R);
102 mcSHOW_ERR_MSG(("###DDR reserve CH%d Gating error[0x%X]\n", u1ChannelSet[u1ChIdx], u4value));
103
104 u4value = u4IO32Read4B(DRAMC_REG_WDT_DBG_SIGNAL);
105 mcSHOW_ERR_MSG(("###DDR reserve CH%d last DRAMC[0x%X]\n", u1ChannelSet[u1ChIdx], u4value));
106 }
107
108 vSetPHY2ChannelMapping(p, (U8)eOriChannel);
109 return;
110}
111
112#if 0//ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION
113/* Only use while CDC option is 1 originally. But we use the patch for gating/tx/rx delay reload from AO to NAO in M17 since CDC_OPTION is 0*/
114static void DDR_Reserved_Mode_Cdc_Option_Patch(DRAMC_CTX_T *p)
115{
116 U32 backup_broadcast = GetDramcBroadcast();
117 U32 u4RegBackupAddress[] =
118 {
119 (DRAMC_REG_DRAMC_PD_CTRL),
120 (DRAMC_REG_DRAMC_PD_CTRL + SHIFT_TO_CHB_ADDR),
121 (DDRPHY_MISC_CG_CTRL5),
122 (DDRPHY_MISC_CG_CTRL5 + SHIFT_TO_CHB_ADDR),
123 (DRAMC_REG_PRE_TDQSCK1),
124 (DRAMC_REG_PRE_TDQSCK1 + SHIFT_TO_CHB_ADDR),
125 (DRAMC_REG_STBCAL),
126 (DRAMC_REG_STBCAL + SHIFT_TO_CHB_ADDR),
127 (DDRPHY_MISC_CTRL1),
128 (DDRPHY_MISC_CTRL1 + SHIFT_TO_CHB_ADDR),
129 (DDRPHY_B0_RXDVS0),
130 (DDRPHY_B0_RXDVS0 + SHIFT_TO_CHB_ADDR),
131 (DDRPHY_B1_RXDVS0),
132 (DDRPHY_B1_RXDVS0 + SHIFT_TO_CHB_ADDR),
133 (DDRPHY_R0_B0_RXDVS2),
134 (DDRPHY_R0_B0_RXDVS2 + SHIFT_TO_CHB_ADDR),
135 (DDRPHY_R1_B0_RXDVS2),
136 (DDRPHY_R1_B0_RXDVS2 + SHIFT_TO_CHB_ADDR),
137 (DDRPHY_R0_B1_RXDVS2),
138 (DDRPHY_R0_B1_RXDVS2 + SHIFT_TO_CHB_ADDR),
139 (DDRPHY_R1_B1_RXDVS2),
140 (DDRPHY_R1_B1_RXDVS2 + SHIFT_TO_CHB_ADDR)
141 };
142 mcSHOW_DBG_MSG(("Apply DDR_Reserved_Mode_Cdc_Option_Patch\n"));
143
144 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
145 //Backup regs
146 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
147 //1. Toggle for shuffle level reset
148 vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL2, 0, SHUCTRL2_R_DVFS_CDC_OPTION);//Lynx: Need to toggle this bit to toggle shuffle level from spm side band to conf AO
149 mcDELAY_US(1);//delay 20NS
150 vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL2, 1, SHUCTRL2_R_DVFS_CDC_OPTION);
151 //2. DQ DCM OFF
152 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0, DRAMC_PD_CTRL_COMBCLKCTRL);
153 //3. TX DLY/PI DCM OFF
154 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL5, P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN)
155 | P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN)
156 | P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN)
157 | P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN)
158 | P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN)
159 | P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN));
160 //4. Dramc_idle OFF
161 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0, DRAMC_PD_CTRL_DCMEN2);
162 //5. TX tracking DCM disable
163 vIO32WriteFldAlign_All(DRAMC_REG_PRE_TDQSCK1, 1, PRE_TDQSCK1_TXUIPI_CAL_CGAR);
164 //6. Gating tracking disable
165 vIO32WriteFldMulti_All(DRAMC_REG_STBCAL, P_Fld(0x0, STBCAL_STBCALEN)
166 | P_Fld(0x0, STBCAL_STB_SELPHYCALEN));
167 //Gating tracking Enable
168 vIO32WriteFldMulti_All(DRAMC_REG_STBCAL, P_Fld(0x1, STBCAL_STBCALEN)
169 | P_Fld(0x1, STBCAL_STB_SELPHYCALEN));
170 //7. Load TX PI from conf to tx tracking
171 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW);
172 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMARPIDQ_SW);
173 //8. TX tracking DCM Enable
174 vIO32WriteFldAlign_All(DRAMC_REG_PRE_TDQSCK1, 0, PRE_TDQSCK1_TXUIPI_CAL_CGAR);
175 //9. RX delay reload from conf to RX DLY tracking
176 vIO32WriteFldAlign_All(DDRPHY_B0_RXDVS0, 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
177 vIO32WriteFldAlign_All(DDRPHY_B1_RXDVS0, 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
178 vIO32WriteFldAlign_All(DDRPHY_B0_RXDVS0, 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
179 vIO32WriteFldAlign_All(DDRPHY_B1_RXDVS0, 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
180 vIO32WriteFldAlign_All(DDRPHY_R0_B0_RXDVS2, 0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0);
181 vIO32WriteFldAlign_All(DDRPHY_R1_B0_RXDVS2, 0, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0);
182 vIO32WriteFldAlign_All(DDRPHY_R0_B1_RXDVS2, 0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1);
183 vIO32WriteFldAlign_All(DDRPHY_R1_B1_RXDVS2, 0, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1);
184 vIO32WriteFldAlign_All(DDRPHY_R0_B0_RXDVS2, 2, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0);
185 vIO32WriteFldAlign_All(DDRPHY_R1_B0_RXDVS2, 2, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0);
186 vIO32WriteFldAlign_All(DDRPHY_R0_B1_RXDVS2, 2, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1);
187 vIO32WriteFldAlign_All(DDRPHY_R1_B1_RXDVS2, 2, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1);
188 //10. DQ DCM ON
189 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 1, DRAMC_PD_CTRL_COMBCLKCTRL);
190 //11. Dramc_idle ON
191 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 1, DRAMC_PD_CTRL_DCMEN2);
192 //12. TX DLY/PI DCM ON
193 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL5, P_Fld(0x1, MISC_CG_CTRL5_R_CA_PI_DCM_EN)
194 | P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN)
195 | P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN)
196 | P_Fld(0x1, MISC_CG_CTRL5_R_CA_DLY_DCM_EN)
197 | P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN)
198 | P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN));
199 //Restore regs
200 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
201 DramcBroadcastOnOff(backup_broadcast);
202 return;
203}
204#endif
205
206#define RESERVE_PDEF_SPM_PLL_CON (0x1000644C)
207void Dramc_DDR_Reserved_Mode_setting(void)
208{
209 U32 u4value = 0;
210 U32 backup_broadcast = GetDramcBroadcast();
211 DRAMC_CTX_T * p;
212
213 mcSHOW_DBG_MSG(("Enter Dramc_DDR_Reserved_Mode_setting \n"));
214 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
215 u4DramType = (*((volatile unsigned int *)(0x1022A010)) >> 10 & 0x7);
216 mcSHOW_DBG_MSG(("Dram type =%x \n", u4DramType));
217 if(u4DramType == 1)
218 {
219 psCurrDramCtx = &DramCtx_LPDDR3;
220 }
221 else if((u4DramType == 2) || (u4DramType == 3))
222 { // LPDDR4
223 psCurrDramCtx = &DramCtx_LPDDR4;
224 }
225 p = psCurrDramCtx;
226 Set_Spm_Poweron_Config_En(p);
227 //dump_gating_error_rg(p);
228 u4value = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
229 mcSHOW_ERR_MSG(("### shuffle level[%d]\n", u4value));
230#if 0//ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION
231 if(u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL2, SHUCTRL2_R_DVFS_CDC_OPTION))
232 {
233 DDR_Reserved_Mode_Cdc_Option_Patch(p);
234 }
235#endif
236#ifdef HW_GATING
237 DramcHWGatingOnOff(p, 0);//Disable HW Gating tracking for gating tracking fifo mode
238#endif
239 u4DramType = u4IO32ReadFldAlign(DRAMC_REG_ARBCTL, ARBCTL_RSV_DRAM_TYPE);
240 mcSHOW_DBG_MSG(("Dramc_DDR_Reserved_Mode_setting dram type =%x \n", u4DramType));
241
242 //Backup regs
243 DramcBackupRegisters(p, u4ReserveRegBackupAddress, sizeof(u4ReserveRegBackupAddress)/sizeof(U32));
244
245 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);//Use PHY PLL, should set before SPM_DVFS_CONTROL_SEL
246 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL);//change DVFS to RG mode
247
248 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_SHU_EN);//toggle shu_en to sync shu_level, need MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL = 1
249 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_SHU_EN);//toggle shu_en to sync shu_level
250 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_SHU_EN);//toggle shu_en to sync shu_level
251 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_SHU_EN);//toggle shu_en to sync shu_level
252 //vIO32WriteFldMulti(SPM_POWER_ON_VAL0, P_Fld(1, SPM_POWER_ON_VAL0_SC_PHYPLL_SHU_EN_PCM)
253 // | P_Fld(1, SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM));//Set spm shuffle enable to 1
254 //mcDELAY_US(1);
255 //vIO32WriteFldMulti(SPM_POWER_ON_VAL0, P_Fld(0, SPM_POWER_ON_VAL0_SC_PHYPLL_SHU_EN_PCM)
256 // | P_Fld(0, SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM));//Set spm shuffle enable to 0
257
258 mcDELAY_US(1);
259 //! toggle hsu restore
260 vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL2, 1, SHUCTRL2_R_SHU_RESTORE);
261 mcDELAY_US(1);
262 vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL2, 0, SHUCTRL2_R_SHU_RESTORE);
263 mcDELAY_US(1);
264
265 if(u4DramType == 1)//LPDDR3
266 {
267 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0 + SHIFT_TO_CHB_ADDR, 0, MISC_CG_CTRL0_RG_CG_DRAMC_CHB_CK_OFF);//Open CHB controller clk
268 }
269
270#ifdef IMPEDANCE_TRACKING_ENABLE
271 if((u4DramType == 2) || (u4DramType == 3))
272 {
273 //Disable IMP tracking
274 vIO32WriteFldAlign_All(DRAMC_REG_IMPCAL, 0, IMPCAL_IMPCAL_HW);
275 }
276#endif
277 //Disable MR4
278 vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 1, SPCMDCTRL_REFRDIS);
279 //Disable DQSOSC en
280 vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 1, SHU_SCINTV_DQSOSCENDIS);
281 //Disable DQSOSC rd
282 vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 1, DQSOSCR_DQSOSCRDIS);
283 //Disable Dummy Read
284 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DQSG_DMYWR_EN)
285 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
286 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
287 | P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
288 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)
289 | P_Fld(0x0, DUMMY_RD_DMY_WR_DBG));
290 //Disable DDRPHY dynamic clock gating
291 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);//disable DDRPHY dynamic clock gating
292
293 //To 26MHz
294 if((u4DramType == 2) || (u4DramType == 3))
295 {
296 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
297 | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b00: 26MHz, [0]: change memory clock
298 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq
299 mcDELAY_US(1);
300 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
301 }
302 else//LP3
303 {
304#if LP3_CKE_FIX_ON_TO_LEAVE_SR_WITH_LVDRAM
305#if ENABLE_LP3_SW
306 //Dram clock free run
307 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 1, DRAMC_PD_CTRL_MIOCKCTRLOFF);//disable DDRPHY dynamic clock gating
308
309 //CKE control
310 u4Cha_cke_backup = u4IO32Read4B(DRAMC_REG_CKECTRL);
311 u4Chb_cke_backup = u4IO32Read4B(DRAMC_REG_CKECTRL + SHIFT_TO_CHB_ADDR);
312 //CKE fix on
313 vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(0x0, CKECTRL_CKE1FIXOFF) |
314 P_Fld(0x0, CKECTRL_CKEFIXOFF) |
315 P_Fld(0x1, CKECTRL_CKE1FIXON) |
316 P_Fld(0x1, CKECTRL_CKEFIXON));
317#endif
318#endif
319 vIO32WriteFldMulti(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
320 | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b00: 26MHz, [0]: change memory clock
321 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq
322 mcDELAY_US(1);
323 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
324 }
325
326 //RG_*PHDET_EN=0 (DLL)
327 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
328 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
329 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
330
331 //*PI_CG=1, RG_*MPDIV_CG=1
332 vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
333 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
334 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
335 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
336 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
337 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
338 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
339 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
340 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
341 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
342 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
343 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
344 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
345 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
346 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
347 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
348 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
349 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
350 vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
351 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
352 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
353 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
354 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CS)
355 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
356 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
357 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
358 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
359
360 //RG_*BIAS_EN=0
361 //vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0);
362 //vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1);
363 //vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_BIAS_EN);
364
365 //RG_*VREF_EN=0
366 vIO32WriteFldAlign_All(DDRPHY_B0_DQ5, 0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
367 vIO32WriteFldAlign_All(DDRPHY_B1_DQ5, 0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
368 vIO32WriteFldAlign_All(DDRPHY_CA_CMD5, 0x0, CA_CMD5_RG_RX_ARCMD_VREF_EN);
369
370 ///TODO: only CHA?
371 //RG_*MCK8X_EN=0
372 vIO32WriteFldMulti(DDRPHY_PLL4, P_Fld(0, PLL4_RG_RPHYPLL_ADA_MCK8X_EN)
373 | P_Fld(0, PLL4_RG_RPHYPLL_AD_MCK8X_EN));//RG_*MCK8X_EN=0; Since there is only 1 PLL, only to control CHA
374 //RG_*MIDPI_EN=0 RG_*MIDPI_CKDIV4_EN=0
375 vIO32WriteFldMulti(DDRPHY_SHU1_B0_DQ6, P_Fld(0, SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0) | P_Fld(0, SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
376 vIO32WriteFldMulti(DDRPHY_SHU1_B1_DQ6, P_Fld(0, SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1) | P_Fld(0, SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
377 vIO32WriteFldMulti(DDRPHY_SHU1_CA_CMD6, P_Fld(0, SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA) | P_Fld(0, SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
378 //vIO32WriteFldAlign_All(DDRPHY_SHU1_B0_DQ6, 0x0, SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0);
379 //vIO32WriteFldAlign_All(DDRPHY_SHU1_B1_DQ6, 0x0, SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1);
380 //vIO32WriteFldAlign_All(DDRPHY_SHU1_CA_CMD6, 0x0, SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA);
381
382 vIO32WriteFldAlign(DDRPHY_PLL1, 0x0, PLL1_RG_RPHYPLL_EN); //RG_*PLL_EN=0; Since there is only 1 PLL, only control CHA
383 vIO32WriteFldAlign(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN); //RG_*PLL_EN=0; Since there is only 1 PLL, only control CHA
384
385 //!set sc_mpll to SPM register //Chen-Hsiang modify @20170316
386 //u4value = Reserve_Reg_Readl(RESERVE_PDEF_SPM_PLL_CON);
387 //Reserve_Sync_Writel(RESERVE_PDEF_SPM_PLL_CON, u4value | (0x1 << 8) | (0x1 << 4));//set sc_mpll_off=1 , sc_mpll_s_off=1
388 //TBD
389 //*((UINT32P)(0x1000631c )) |= (0x1 << 1); //ddrphy_pwr_iso=1 //Lewis@20160621: Fix LP3 Hang from S0 suspend into reserve mode
390 //*((UINT32P)(0x100063b8 )) |= (0x1 << 1);
391
392 //RG_*RESETB=0
393 vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_ARDQ_RESETB_B0);
394 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
395 vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_ARDQ_RESETB_B1);
396 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
397 vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x0, CA_CMD3_RG_ARCMD_RESETB);
398 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
399 vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA
400 //Lewis@20160628: Fix LP3 enter S0 then into reserve mode fail due to CHB PHY not reset(LP3 PHY use 2 channels)
401
402 MPLLInit();
403
404 //marked by kaihsin on May 7th, not necessary to PDN DDRPHY
405 //*((UINT32P)(0x1000631c )) &= ~(0x1 << 2); //ddrphy_pwr_on=0
406 //*((UINT32P)(0x100063b8 )) &= ~(0x1 << 2);
407
408 // wait 1us
409 mcDELAY_US(1);
410
411 //marked by kaihsin on May 7th, not necessary to PDN DDRPHY
412 //*((UINT32P)(0x1000631c )) |= (0x1 << 2); //ddrphy_pwr_on=1
413 //*((UINT32P)(0x100063b8 )) |= (0x1 << 2);
414 // wait 1us
415 //mcDELAY_US(1);
416
417 //RG_*RESETB=1
418 vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0);
419 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
420 vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1);
421 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
422 vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_ARCMD_RESETB);
423 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
424 vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA
425
426 //TBD
427 //*((UINT32P)(0x1000631c )) &= ~(0x1 << 1); //ddrphy_pwr_iso=0 //Lewis@20160621: Fix LP3 Hang from S0 suspend into reserve mode
428 //*((UINT32P)(0x100063b8 )) &= ~(0x1 << 1);
429
430 u4value = Reserve_Reg_Readl(RESERVE_PDEF_SPM_PLL_CON);
431 Reserve_Sync_Writel(RESERVE_PDEF_SPM_PLL_CON, u4value & ~((0x1 << 8) | (0x1 << 4)));//set sc_mpll_off=0 , sc_mpll_s_off=0
432 mcDELAY_US(20);
433
434 //RG_*PLL_EN=1
435 vIO32WriteFldAlign(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_EN); //RG_*PLL_EN=1; Since there is only 1 PLL, only control CHA
436 vIO32WriteFldAlign(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_EN); //RG_*PLL_EN=1; Since there is only 1 PLL, only control CHA
437
438 //Wait 20us for MEMPLL
439 mcDELAY_US(20);
440
441 //RG_*VREF_EN=1 (Vref is only used in read, DQ(B0, B1)is use for RX)
442 if((u4DramType == 2) || (u4DramType == 3))
443 {
444 vIO32WriteFldAlign_All(DDRPHY_B0_DQ5, 0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
445 vIO32WriteFldAlign_All(DDRPHY_B1_DQ5, 0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
446 }
447 else
448 {
449 vIO32WriteFldAlign_All(DDRPHY_B1_DQ5, 0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
450 vIO32WriteFldAlign(DDRPHY_B0_DQ5 + SHIFT_TO_CHB_ADDR, 0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
451 vIO32WriteFldAlign(DDRPHY_CA_CMD5 + SHIFT_TO_CHB_ADDR, 0x1, CA_CMD5_RG_RX_ARCMD_VREF_EN);
452 }
453 //RG_*MCK8X_EN=1
454 vIO32WriteFldAlign(DDRPHY_PLL4, 1, PLL4_RG_RPHYPLL_ADA_MCK8X_EN);//RG_*MCK8X_EN=1; Since there is only 1 PLL, only to control CHA
455
456 //wait 1us
457 mcDELAY_US(1);
458
459 if((u4DramType == 2) || (u4DramType == 3))
460 {
461 vIO32WriteFldAlign_All(DDRPHY_SHU1_B0_DQ6, 0x1, SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0);
462 vIO32WriteFldAlign_All(DDRPHY_SHU1_B1_DQ6, 0x1, SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1);
463 vIO32WriteFldAlign_All(DDRPHY_SHU1_CA_CMD6, 0x1, SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA);
464
465 //wait 1us
466 mcDELAY_US(1);
467
468 //*PI_CG=0, RG_*MPDIV_CG=0
469 vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
470 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
471 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
472 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
473 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
474 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
475 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
476 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
477 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
478 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
479 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
480 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
481 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
482 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
483 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
484 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
485 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
486 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
487 vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)//not include 11th bit(CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
488 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
489 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
490 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
491 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CS)
492 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
493 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
494 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
495 }
496 else
497 {
498 vIO32WriteFldAlign_All(DDRPHY_SHU1_B0_DQ6, 0x1, SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0);
499 vIO32WriteFldAlign_All(DDRPHY_SHU1_B1_DQ6, 0x1, SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1);
500 vIO32WriteFldAlign_All(DDRPHY_SHU1_CA_CMD6, 0x1, SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA);
501
502 //wait 1us
503 mcDELAY_US(1);
504
505 //*PI_CG=0, RG_*MPDIV_CG=0
506 vIO32WriteFldMulti(DDRPHY_B0_DLL_ARPI2, P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
507 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
508 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
509 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
510 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
511 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
512 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
513 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
514 vIO32WriteFldMulti(DDRPHY_B0_DLL_ARPI2 + SHIFT_TO_CHB_ADDR, P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
515 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
516 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
517 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
518 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
519 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
520 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
521 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
522 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
523 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
524 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
525 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
526 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
527 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
528 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
529 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
530 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
531 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
532
533 vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI2, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)//not include 11th bit(CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
534 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
535 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
536 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
537 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CS)
538 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
539 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
540 // | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)//11th
541 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
542 vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI2 + SHIFT_TO_CHB_ADDR, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)//not include 11th bit(CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
543 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
544 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
545 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
546 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CS)
547 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
548 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
549 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)//11th
550 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
551 }
552
553 //RG_*BIAS_EN=1
554 //vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0);//Chen-Hsiang modify @20170316
555 //vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1);//Chen-Hsiang modify @20170316
556
557 // wait 1us
558 mcDELAY_US(1);
559
560 if((u4DramType == 2) || (u4DramType == 3))
561 {
562 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
563 | P_Fld(1, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b01: memory clock, [0]: change memory clock
564 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq
565 mcDELAY_US(1);
566 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
567 }
568 else
569 {
570 vIO32WriteFldMulti(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
571 | P_Fld(1, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b01: memory clock, [0]: change memory clock
572 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq
573 mcDELAY_US(1);
574 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
575 }
576
577 //force top feedback MCK not divide
578 //rg_ddrphy_fb_ck_force_en = 1 -- TBD
579 //*CLK_MEM_DFS_CFG |= (0x1 << 8); //rg_ddrphy_fb_ck_force_en = 1
580 //u4value = Reserve_Reg_Readl(0x10060464);
581 //Reserve_Sync_Writel(0x10060464, u4value | (0x3 << 20)); //set sc_ddrphy_fb_ck_ch*_en = 1
582 //u4value = Reserve_Reg_Readl(0x10060004);
583 //Reserve_Sync_Writel(0x10060004, u4value | (0x1 << 16)); //set sc_ddrphy_fb_ck_ch*_en = 1
584 //*DRAMC_WBR = 0x3;
585 vIO32WriteFldMulti(DDRPHY_MISC_SPM_CTRL1, P_Fld(1, MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH1_EN)
586 | P_Fld(1, MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH0_EN));//clock freerun
587
588 //1st DLL enable
589 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);//Since CHA CA is DLL master
590 // wait 1us
591 mcDELAY_US(1);
592 //2nd DLL enable
593 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI2+ SHIFT_TO_CHB_ADDR, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
594 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x1, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);//Chen-Hsiang modify @20170316
595 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x1, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);//Chen-Hsiang modify @20170316
596 // wait 1us
597 mcDELAY_US(1);
598
599 vIO32WriteFldMulti(DDRPHY_MISC_SPM_CTRL1, P_Fld(0, MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH1_EN)
600 | P_Fld(0, MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH0_EN));//disable clock freerun
601 //top feedback MCK to divided frequency -- TBD
602 //*CLK_MEM_DFS_CFG &= ~(0x1 << 8); //rg_ddrphy_fb_ck_force_en = 0
603 //u4value = Reserve_Reg_Readl(0x10060464);
604 //Reserve_Sync_Writel(0x10060464, u4value & ~(0x3 << 20)); //set sc_ddrphy_fb_ck_ch*_en = 0
605 //u4value = Reserve_Reg_Readl(0x10060004);
606 //Reserve_Sync_Writel(0x10060004, u4value & ~(0x1 << 16)); //set sc_ddrphy_fb_ck_ch*_en = 0
607
608 vIO32WriteFldAlign_All(DRAMC_REG_DDRCONF0, 1, DDRCONF0_RDATRST);//R_DMRDATRST = 1
609 vIO32WriteFldAlign_All(DRAMC_REG_DDRCONF0, 0, DDRCONF0_RDATRST);//R_DMRDATRST = 0
610
611 //! set SPM to control PLL enable and disable PLL enable from ddrphy conf
612 /*TINFO ="Switching PHYPLL enable path from DDRPHY to SPM control by setting SPM SW" */
613 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL);//change DVFS to SPM mode^M
614 mcDELAY_US(1);
615
616 vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_PHYPLL_MODE_SW_PCM);
617 u4value = Reserve_Reg_Readl(SPM_DRAMC_DPY_CLK_SW_CON2);
618 Reserve_Sync_Writel(SPM_DRAMC_DPY_CLK_SW_CON2, u4value | (0x1 << 2));
619 mcDELAY_US(1);
620 //RG_*PLL_EN=1
621 vIO32WriteFldAlign(DDRPHY_PLL1, 0x0, PLL1_RG_RPHYPLL_EN); //disable DDRPHY PHYPLL enable, RG_*PLL_EN=0; Since there is only 1 PLL, only control CHA
622 vIO32WriteFldAlign(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN); //disable DDRPHY CLRPLL enable, RG_*PLL_EN=0; Since there is only 1 PLL, only control CHA
623 /*TINFO ="Setting RX input delay tracking enable from SPM side(un-paused)" */
624 //! speed >= 3200 need enable RX input delay tracking
625 if((u4DramType == 2) || (u4DramType == 3))
626 {
627 //u4value = Reserve_Reg_Readl(SPM_DRAMC_DPY_CLK_SW_CON2);
628 //Reserve_Sync_Writel(SPM_DRAMC_DPY_CLK_SW_CON2, u4value & ~(0x3 << 16));
629 vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN);
630 }
631 DramcBroadcastOnOff(backup_broadcast);
632 //DDRPhyFreqMeter();
633 //dump_gating_error_rg(p);
634 //dump_SR(p);
635}
636
637void Dramc_DDR_Reserved_Mode_AfterSR(void)
638{
639 DRAMC_CTX_T * p = psCurrDramCtx; //done in ddr reserve mode setting
640 U32 u4LP3_MR2RLWL = 0;
641 U32 u4LP4_MR13FSP = 0;
642 U32 u4LP4_MR2RLWL = 0;
643 U32 backup_broadcast = GetDramcBroadcast();
644 U8 u1channel = CHANNEL_A;
645 BOOL bSupport2Rank = (u4IO32ReadFldAlign(DRAMC_REG_RSTMASK, RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM) == 0) ? TRUE : FALSE;
646
647#if MRW_CHECK_ONLY
648 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
649#endif
650
651 vSetChannelNumber(p);
652 vSetRankNumber(p);
653 p->channel = u1ChannelSet[0];
654 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
655 mcSHOW_DBG_MSG(("Dramc_DDR_Reserved_Mode_AfterSR dram type =%x \n", u4DramType));
656 if(u4DramType == 1)
657 { //LPDDR3
658 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0 + SHIFT_TO_CHB_ADDR, 1, MISC_CG_CTRL0_RG_CG_DRAMC_CHB_CK_OFF);//Close CHB controller clk
659
660 //Since we do MR2 with (RG of Mr13) first while DVFS, we use (RG of MR13) to apply OP of MR2
661 u4LP3_MR2RLWL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
662 p->channel = u1ChannelSet[u1channel];
663 DramcModeRegWriteByRank(p, 0, 2, u4LP3_MR2RLWL);
664 DramcModeRegWriteByRank(p, 0, 17, 0);//R1 lost data WA, set R0 R1 both for safe{On charging mode, system may issue MR17=0xFF in R1}
665 if(bSupport2Rank == TRUE)//DRAM is dual rank
666 {
667 DramcModeRegWriteByRank(p, 1, 2, u4LP3_MR2RLWL);
668 DramcModeRegWriteByRank(p, 1, 17, 0);//R1 lost data WA, set R0 R1 both for safe{On charging mode, system may issue MR17=0xFF in R1}
669 }
670 }
671 else if((u4DramType == 2) || (u4DramType == 3))
672 { //LPDDR4
673 u4LP4_MR13FSP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
674 u4LP4_MR2RLWL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2), SHU_HWSET_MR2_HWSET_MR2_OP);
675
676 for(u1channel = CHANNEL_A; u1channel < p->support_channel_num; u1channel++)
677 {
678 p->channel = u1ChannelSet[u1channel];
679 DramcModeRegWriteByRank(p, 0, 13, u4LP4_MR13FSP);
680 DramcModeRegWriteByRank(p, 0, 2, u4LP4_MR2RLWL);
681 DramcModeRegWriteByRank(p, 0, 17, 0);//R1 lost data WA, set R0 R1 both for safe{On charging mode, system may issue MR17=0xFF in R1}
682
683 if(bSupport2Rank == TRUE)//DRAM is dual rank
684 {
685 DramcModeRegWriteByRank(p, 1, 13, u4LP4_MR13FSP);
686 DramcModeRegWriteByRank(p, 1, 2, u4LP4_MR2RLWL);
687 DramcModeRegWriteByRank(p, 1, 17, 0);//R1 lost data WA, set R0 R1 both for safe{On charging mode, system may issue MR17=0xFF in R1}
688 }
689 }
690 }
691
692 //Restore regs
693 DramcRestoreRegisters(p, u4ReserveRegBackupAddress, sizeof(u4ReserveRegBackupAddress)/sizeof(U32));
694#if LP3_CKE_FIX_ON_TO_LEAVE_SR_WITH_LVDRAM
695#if ENABLE_LP3_SW
696 if(u4DramType == 1)
697 {
698 vIO32Write4B(DRAMC_REG_CKECTRL, u4Cha_cke_backup);
699 vIO32Write4B(DRAMC_REG_CKECTRL + SHIFT_TO_CHB_ADDR, u4Chb_cke_backup);
700 }
701#endif
702#endif
703
704#ifdef HW_GATING
705 DramcHWGatingOnOff(p,1);//Enable HW Gating tracking for gating tracking fifo mode
706#if GATING_ONLY_FOR_DEBUG
707 DramcHWGatingDebugOnOff(p, 1);
708#endif
709#endif
710#ifdef IMPEDANCE_TRACKING_ENABLE
711 if((u4DramType == 2) || (u4DramType == 3))
712 {
713 //Enable IMP tracking,
714 //SPM only handle CHA IMPCAL_IMPCAL_HW, DDR2400 into DDR reserve mode(IMPCAL_IMPCAL_HW CHA = 0 CHB = 1)
715 //CHB NAO have been reset to 0, need do hand shake with CHA, but CHA IMP tracking is off --> dead lock
716 vIO32WriteFldAlign_All(DRAMC_REG_IMPCAL, 1, IMPCAL_IMPCAL_HW);
717 }
718#endif
719 DramcBroadcastOnOff(backup_broadcast);
720 dump_gating_error_rg(p);
721 //DramcRegDump(p);
722
723#ifdef USE_TA2_IN_DDR_RESERVE_MODE
724 {
725 int i = 0;
726 for(i = 0; i < 10; i++)
727 {
728 TA2_Test_Run_Time_HW(p);
729 }
730 }
731#endif
732
733 return;
734}
735
736void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type)
737{
738 DRAMC_CTX_T * p;
739 mcSHOW_DBG_MSG(("\n\tReserve mode fail\tBefore_Init_DRAM_While_Reserve_Mode_fail\n"));
740 if(u1IsLP4Family(dram_type))
741 {
742 psCurrDramCtx = &DramCtx_LPDDR4;
743 }
744 else
745 {
746#if (!__ETT__ && ENABLE_LP3_SW==0)
747#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
748// Preloader which does not support LP3
749// scy: reduce code size by removing unused LPDDR3 structure
750 mcSHOW_DBG_MSG(("LPDDR3 not supported\n"));
751 ASSERT(0);
752#endif
753#else
754 psCurrDramCtx = &DramCtx_LPDDR3;
755#endif
756 }
757 p = psCurrDramCtx;
758
759#if (SW_CHANGE_FOR_SIMULATION==0)
760 EnableDramcPhyDCM(p, 0);
761#endif
762 Switch26MHzDisableDummyReadRefreshAllBank(p);
763 *((volatile unsigned int *)SPM_DRAMC_DPY_CLK_SW_CON2) &= ~(0x1 << 2);//20170210: confirmed by chen-Hsiang
764 *((volatile unsigned int *)SPM_POWER_ON_VAL0) &= ~(0x1 << 28);//20170210: confirmed by chen-Hsiang
765}
766
767#if __ETT__
768void Func_Emi_On(DRAMC_CTX_T *p);
769void Func_Emi_Off(DRAMC_CTX_T *p);
770void ETT_DRM(DRAMC_CTX_T *p)
771{
772 Func_Emi_Off(p);
773 vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_DMSUS_OFF_PCM);//DMSUS set 1
774 Dramc_DDR_Reserved_Mode_setting();
775 vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DMSUS_OFF_PCM);//DMSUS set 0
776 Func_Emi_On(p);
777 Dramc_DDR_Reserved_Mode_AfterSR();
778
779#ifdef USE_TA2_IN_DDR_RESERVE_MODE
780 {
781 int i = 0;
782 for(i = 0; i < 10; i++)
783 {
784 TA2_Test_Run_Time_HW(p);
785 }
786 }
787#endif
788}
789#endif
790#endif
791