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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / dramk_2731 / dramc_pi_main.c
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*----------------------------------------------------------------------------*
2 * Copyright Statement: *
3 * *
4 * This software/firmware and related documentation ("MediaTek Software") *
5 * are protected under international and related jurisdictions'copyright laws *
6 * as unpublished works. The information contained herein is confidential and *
7 * proprietary to MediaTek Inc. Without the prior written permission of *
8 * MediaTek Inc., any reproduction, modification, use or disclosure of *
9 * MediaTek Software, and information contained herein, in whole or in part, *
10 * shall be strictly prohibited. *
11 * MediaTek Inc. Copyright (C) 2010. All rights reserved. *
12 * *
13 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND *
14 * AGREES TO THE FOLLOWING: *
15 * *
16 * 1)Any and all intellectual property rights (including without *
17 * limitation, patent, copyright, and trade secrets) in and to this *
18 * Software/firmware and related documentation ("MediaTek Software") shall *
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22 * Software, whoever made, shall also remain the exclusive property of *
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25 * *
26 * 2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
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74 *---------------------------------------------------------------------------*/
75
76//=============================================================================
77// Include Files
78//=============================================================================
79#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
80#if __ETT__
81#include <common.h>
82#include <ett_common.h>
83#include <api.h>
84#endif
85#endif
86
87//#if (FOR_DV_SIMULATION_USED==0)
88#include "emi.h"
89//#endif
90#include "dramc_common.h"
91#include "dramc_pi_api.h"
92#include "x_hal_io.h"
93
94//=============================================================================
95// Definition
96//=============================================================================
97
98//=============================================================================
99// Global Variables
100//=============================================================================
101#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
102 SAVE_TIME_FOR_CALIBRATION_T SavetimeData;
103#endif
104
105DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
106 {LP4_HIGHEST_FREQSEL, LP4_HIGHEST_FREQ, DRAM_DFS_SHUFFLE_1},
107};
108
109DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl_LP3[DRAM_DFS_SHUFFLE_MAX] = {
110 {LP3_DDR1066, 533, DRAM_DFS_SHUFFLE_1},
111};
112
113DRAMC_CTX_T *psCurrDramCtx;
114
115#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
116DRAMC_CTX_T gTimeProfilingDramCtx;
117U8 gtime_profiling_flag = 0;
118#endif
119
120#if (!__ETT__ && ENABLE_LP3_SW==0)
121// Preloader which does not support LP3
122// scy: reduce code size by removing unused LPDDR3 structure
123#else
124DRAMC_CTX_T DramCtx_LPDDR3 =
125{
126 CHANNEL_SINGLE, // Channel number
127 CHANNEL_A, // DRAM_CHANNEL
128 RANK_DUAL, //DRAM_RANK_NUMBER_T
129 RANK_0, //DRAM_RANK_T
130#if DUAL_FREQ_K
131 LP3_DDR1066,
132#else
133#if __FLASH_TOOL_DA__
134 LP3_DDR1066,
135#else
136 //LP3_DDR1333, //LP3_DDR1866,
137 LP3_DDR1066,
138#endif
139#endif
140 DRAM_DFS_SHUFFLE_1,
141 TYPE_LPDDR3, // DRAM_DRAM_TYPE_T
142 FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3
143 ODT_OFF,
144 {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, //only for LP4, useless in LP3
145 {DBI_OFF,DBI_OFF},
146 {DBI_OFF,DBI_OFF},
147 DATA_WIDTH_32BIT, // DRAM_DATA_WIDTH_T
148 DEFAULT_TEST2_1_CAL, // test2_1;
149 DEFAULT_TEST2_2_CAL, // test2_2;
150 TEST_XTALK_PATTERN, // test_pattern;
151 533, // frequency
152 533, // freqGroup
153 0x88, //vendor_id initial value
154 REVISION_ID_MAGIC, //revision id
155 0xff, //density
156 {0,0},
157 0, // ucnum_dlycell_perT;
158 0, // u2DelayCellTimex100;
159
160 DISABLE_VREF_SCAN, // enable_cbt_scan_vref;
161 DISABLE_VREF_SCAN, // enable_rx_scan_vref;
162 DISABLE_VREF_SCAN, // enable_tx_scan_vref;
163#if PRINT_CALIBRATION_SUMMARY
164 //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX]
165 {{0,0}, {0,0}},
166 //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]
167 {{0,0}, {0,0}},
168#endif
169#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK
170 {{0,0}, {0,0}}, //BOOL arfgWriteLevelingInitShif;
171#endif
172#if TX_PERBIT_INIT_FLOW_CONTROL
173 {{FALSE, FALSE}, {FALSE, FALSE}},//BOOL fgTXPerbifInit;
174#endif
175#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
176 FALSE, //femmc_Ready
177 0,
178 0,
179 0,
180 &SavetimeData,
181#endif
182#if (fcFOR_CHIP_ID == fcLaurel)
183 0, //bDLP3
184#endif
185#if defined(SLT) || (FT_DSIM_USED)
186 0, //shuffle_index
187#endif
188 TRUE, //u1PHYPLLEn
189};
190#endif
191
192DRAMC_CTX_T DramCtx_LPDDR4 =
193{
194 CHANNEL_DUAL, // Channel number
195 CHANNEL_A, // DRAM_CHANNEL
196 RANK_DUAL, //DRAM_RANK_NUMBER_T
197 RANK_0, //DRAM_RANK_T
198
199#ifdef MTK_FIXDDR1600_SUPPORT
200 LP4_DDR1600,
201#else
202#if DUAL_FREQ_K
203 LP4_LOWEST_FREQSEL, // Darren: it will be overwritten by gFreqTbl[DRAM_DFS_SHUFFLE_3].freq_sel (Init_DRAM)
204#else
205#if __FLASH_TOOL_DA__
206 LP4_DDR1600,
207#else
208
209#if EMI_LPBK_USE_THROUGH_IO
210 LP4_DDR1600,
211#else
212 LP4_DDR3200,
213#endif
214
215
216#endif
217#endif
218#endif
219 DRAM_DFS_SHUFFLE_1,
220 TYPE_LPDDR4X, // DRAM_DRAM_TYPE_T
221 FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3
222 ODT_OFF,
223 {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, // bring up LP4X rank0 & rank1 use normal mode
224#if ENABLE_READ_DBI
225 {DBI_OFF,DBI_ON}, //read DBI
226#else
227 {DBI_OFF,DBI_OFF}, //read DBI
228#endif
229#if ENABLE_WRITE_DBI
230 {DBI_OFF,DBI_ON}, // write DBI
231#else
232 {DBI_OFF,DBI_OFF}, // write DBI
233#endif
234 DATA_WIDTH_16BIT, // DRAM_DATA_WIDTH_T
235 DEFAULT_TEST2_1_CAL, // test2_1;
236 DEFAULT_TEST2_2_CAL, // test2_2;
237 TEST_XTALK_PATTERN, // test_pattern;
238 1600, // frequency
239 1600, // freqGroup
240 0x88, //vendor_id initial value
241 REVISION_ID_MAGIC, //revision id
242 0xff, //density
243 {0,0},
244 0, // ucnum_dlycell_perT;
245 0, // u2DelayCellTimex100;
246
247 ENABLE, // enable_cbt_scan_vref;
248 ENABLE, // enable_rx_scan_vref;
249 ENABLE, // enable_tx_scan_vref;
250
251#if PRINT_CALIBRATION_SUMMARY
252 //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX]
253 {{0,0,}, {0,0}},
254 //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]
255 {{0,0,}, {0,0}},
256#endif
257#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK
258 {{0,0}, {0,0}}, //BOOL arfgWriteLevelingInitShif;
259#endif
260#if TX_PERBIT_INIT_FLOW_CONTROL
261 {{FALSE, FALSE}, {FALSE, FALSE}},//BOOL fgTXPerbifInit;
262#endif
263#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
264 FALSE, //femmc_Ready
265 0,
266 0,
267 0,
268 &SavetimeData,
269#endif
270#if (fcFOR_CHIP_ID == fcLaurel)
271 0, //bDLP3
272#endif
273#if defined(SLT) || (FT_DSIM_USED)
274 0, //shuffle_index
275#endif
276 TRUE, //u1PHYPLLEn
277};
278
279U8 gfirst_init_flag = 0;
280//=============================================================================
281// External references
282//=============================================================================
283#if __ETT__
284extern int global_which_test;
285#endif
286
287#if !__ETT__ && defined(DDR_RESERVE_MODE)
288extern u32 g_ddr_reserve_ta_err;
289#endif
290
291extern U8 gu1MR23Done;
292extern U8 ucg_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];
293extern U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];
294
295extern int complex_mem_test(unsigned long start, unsigned int len);
296extern void EMI_Init(DRAMC_CTX_T *p);
297extern void EMI_Init2(void);
298
299extern U16 gu2MR0_Value[RANK_MAX]; /*read only mode register*/
300
301/*
302 * LP4 table
303 * [0] 3200
304 * [1] 3200
305 * [2] 2400
306 * [3] 1600
307 * LP3 table
308 * [0] 1866
309 * [1] 1600
310 * [2] 1600
311 * [3] 1200
312 */
313#define STD_LP4_VCORE_KOPP0 800000
314#define STD_LP4_VCORE_KOPP1 750000
315#define STD_LP4_VCORE_KOPP2 700000
316#define STD_LP4_VCORE_KOPP3 700000
317#define STD_LP3_VCORE_KOPP0 800000
318#define STD_LP3_VCORE_KOPP1 750000
319#define STD_LP3_VCORE_KOPP2 750000
320#define STD_LP3_VCORE_KOPP3 700000
321#ifdef DRAM_HQA
322#if __ETT__
323extern unsigned int hqa_LP4_vcore_kopp0;
324extern unsigned int hqa_LP4_vcore_kopp1;
325extern unsigned int hqa_LP4_vcore_kopp2;
326extern unsigned int hqa_LP4_vcore_kopp3;
327extern unsigned int hqa_LP3_vcore_kopp0;
328extern unsigned int hqa_LP3_vcore_kopp1;
329extern unsigned int hqa_LP3_vcore_kopp2;
330extern unsigned int hqa_LP3_vcore_kopp3;
331#define VCORE_KOPP_BY_FREQ(F, D) hqa_##D##_vcore_kopp##F
332#else
333#define VCORE_KOPP_BY_FREQ(F, D) HQA_VCORE_KOPP(F, D)
334#endif
335#else
336#define VCORE_KOPP_BY_FREQ(F, D) STD_##D##_VCORE_KOPP##F
337#endif
338
339void vSetVcoreByFreq(DRAMC_CTX_T *p)
340{
341#ifndef MT2731_FPGA
342#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
343#if __FLASH_TOOL_DA__
344 dramc_set_vcore_voltage(800000);
345#else
346 unsigned int vcore, vdram, vddq;
347#ifdef DRAM_HQA
348 unsigned int vio18;
349 vio18 = HQA_VIO18;
350#endif
351
352 vcore = vdram = vddq = 0;
353
354#if defined(DRAM_HQA) && defined(__ETT__)
355 hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq);
356#else
357#ifdef VCORE_BIN
358 vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1;
359#else
360 if(u1IsLP4Family(p->dram_type))
361 // LP4X
362 vcore = (SEL_PREFIX_VCORE(LP4, KOPP0) + SEL_PREFIX_VCORE(LP4, KOPP1)) >> 1;
363 else
364 // LP2
365 vcore = (SEL_PREFIX_VCORE(LP2, KOPP0) + SEL_PREFIX_VCORE(LP2, KOPP1)) >> 1;
366#endif
367#endif
368
369#ifdef LAST_DRAMC
370 update_last_dramc_k_voltage(p, vcore);
371#endif
372
373#if defined(DRAM_HQA)
374 if (vio18)
375 dramc_set_vdd1_voltage(p->dram_type, vio18);
376#endif
377
378 if (vcore)
379 dramc_set_vcore_voltage(vcore);
380
381#if defined(DRAM_HQA)
382 if (vdram)
383 dramc_set_vdd2_voltage(p->dram_type, vdram);
384
385 if (u1IsLP4Family(p->dram_type)) {
386 if (vddq)
387 dramc_set_vddq_voltage(p->dram_type, vddq);
388 }
389#endif
390
391#ifndef DDR_INIT_TIME_PROFILING
392 printf("Read voltage for %d\n", p->frequency);
393 printf("Vio18 = %d\n", dramc_get_vdd1_voltage());
394 printf("Vcore = %d\n", dramc_get_vcore_voltage());
395 printf("Vdram = %d\n", dramc_get_vdd2_voltage(p->dram_type));
396
397 if (u1IsLP4Family(p->dram_type))
398 printf("Vddq = %d\n", dramc_get_vddq_voltage(p->dram_type));
399#endif
400#endif
401#endif
402#endif
403}
404
405U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type)
406{
407#if (defined(DRAM_HQA) || defined(__ETT__)) && (FOR_DV_SIMULATION_USED == 0)
408 if (get_voltage_type==0)
409 return dramc_get_vcore_voltage();
410
411 if (get_voltage_type==1)
412 return dramc_get_vdd2_voltage(p->dram_type);
413
414 if (get_voltage_type==2)
415 return dramc_get_vddq_voltage(p->dram_type);
416
417 if (get_voltage_type==3)
418 return dramc_get_vdd1_voltage();
419#endif
420
421 return 0;
422}
423
424#ifdef FOR_HQA_TEST_USED
425VCORE_DELAYCELL_T gVcoreDelayCellTable[42]={ {606250, 1071},
426 {612500, 1032},
427 {618750, 1019},
428 {625000, 1007},
429 {631250, 995},
430 {637500, 983},
431 {643750, 972},
432 {650000, 960},
433 {656250, 946},
434 {662500, 932},
435 {668750, 919},
436 {675000, 905},
437 {681250, 892},
438 {687500, 886},
439 {693750, 880},
440 {700000, 868},
441 {706250, 856},
442 {712500, 850},
443 {718750, 844},
444 {725000, 833},
445 {731250, 822},
446 {737500, 817},
447 {743750, 811},
448 {750000, 801},
449 {756250, 791},
450 {762500, 781},
451 {768750, 776},
452 {775000, 771},
453 {781250, 767},
454 {787500, 762},
455 {793750, 753},
456 {800000, 749},
457 {806250, 744},
458 {812500, 735},
459 {818750, 731},
460 {825000, 726},
461 {831250, 722},
462 {837500, 718},
463 {843750, 714},
464 {850000, 710},
465 {856250, 702},
466 {862500, 694} };
467
468void GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p)
469{
470 U32 channel_i, i;
471 U32 get_vcore = 0;
472 U16 u2gdelay_cell_ps = 0;
473 U8 u1delay_cell_cnt = 0;
474 VCORE_DELAYCELL_T *pVcoreDelayCellTable;
475
476#if (defined(DRAM_HQA) || defined(__ETT__)) && (FOR_DV_SIMULATION_USED == 0)
477 get_vcore = dramc_get_vcore_voltage();
478#endif
479
480 pVcoreDelayCellTable = (VCORE_DELAYCELL_T *)gVcoreDelayCellTable;
481 u1delay_cell_cnt = sizeof(gVcoreDelayCellTable)/sizeof(gVcoreDelayCellTable[0]);
482
483 for(i=0; i<u1delay_cell_cnt; i++)
484 {
485 if (get_vcore >= pVcoreDelayCellTable[i].u2Vcore) u2gdelay_cell_ps = pVcoreDelayCellTable[i].u2DelayCell;
486 }
487
488 mcSHOW_DBG_MSG(("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, u2gdelay_cell_ps));
489
490 for(channel_i=CHANNEL_A; channel_i < p->support_channel_num; channel_i++)
491 {
492 u2gdelay_cell_ps_all[get_shuffleIndex_by_Freq(p)][u1ChannelSet[channel_i]] = u2gdelay_cell_ps;
493 }
494}
495
496#endif
497
498void mem_test_address_calculation(DRAMC_CTX_T * p, unsigned long uiSrcAddr, unsigned long *pu4Dest)
499{
500#if __ETT__
501 *pu4Dest = uiSrcAddr - RANK0_START_VA + RANK1_START_VA;
502#else
503 *pu4Dest = uiSrcAddr + p->ranksize[RANK_0];
504#endif
505}
506
507
508#if CPU_RW_TEST_AFTER_K || ENABLE_SLT
509void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p)
510{
511 U8 u1DumpInfo=0, u1RankIdx;
512 unsigned long uiLen, count, uiFixedAddr, uiRankdAddr[RANK_MAX];
513 U32 pass_count, err_count;
514#if EMI_LPBK_DRAM_USED==1
515 uiLen = 0xffff;
516#else
517 uiLen = 0x44000; //saint 0xffff;
518#endif
519
520#if GATING_ONLY_FOR_DEBUG
521 DramcGatingDebugInit(p);
522#endif
523
524 uiRankdAddr[0] = DDR_BASE;
525 mem_test_address_calculation(p, DDR_BASE, &uiRankdAddr[1]);
526
527 for(u1RankIdx =0; u1RankIdx< p->support_rank_num; u1RankIdx++)
528 {
529 u1DumpInfo=0;
530 err_count=0;
531 pass_count=0;
532
533#if !__ETT__
534 // scy: not to test rank1 (wrong addr 0x0000_0000)
535 if (u1RankIdx >= 1)
536 continue;
537#endif
538
539 #if GATING_ONLY_FOR_DEBUG
540 DramcGatingDebugRankSel(p, u1RankIdx);
541 #endif
542
543 uiFixedAddr = uiRankdAddr[u1RankIdx];
544
545 for (count= 0; count<uiLen; count+=4)
546 {
547 *(volatile unsigned int *)(count +uiFixedAddr) = count + (0x5a5a <<16);
548 }
549
550 for (count=0; count<uiLen; count+=4)
551 {
552 if (*(volatile unsigned int *)(count +uiFixedAddr) != count + (0x5a5a <<16))
553 {
554 //mcSHOW_DBG_MSG(("[Fail] Addr %xh = %xh\n",count, *(volatile unsigned int *)(count)));
555 err_count++;
556 }
557 else
558 pass_count ++;
559 }
560
561#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
562 if (err_count==0)
563 {
564#if __ETT__
565 mcSHOW_ERR_MSG(("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n",
566 p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B',
567 p->pSavetimeData->Runtime_Shmoo_para.TX_Rank,
568 p->pSavetimeData->Runtime_Shmoo_para.TX_Byte,
569 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range,
570 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
571 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
572#else
573 mcSHOW_ERR_MSG(("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n",
574 p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B',
575 p->pSavetimeData->Runtime_Shmoo_para.TX_Rank,
576 p->pSavetimeData->Runtime_Shmoo_para.TX_Byte,
577 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range,
578 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
579 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
580#endif
581 }
582#else
583 if(err_count)
584 {
585 mcSHOW_DBG_MSG(("[MEM_TEST] Rank %d Fail.", u1RankIdx));
586 u1DumpInfo =1;
587#if defined(SLT) || (ENABLE_SLT == 1)
588 while(1);
589#endif
590 }
591 else
592 {
593 mcSHOW_DBG_MSG(("[MEM_TEST] Rank %d OK.", u1RankIdx));
594 }
595 mcSHOW_DBG_MSG(("(uiFixedAddr 0x%x, Pass count =%d, Fail count =%d)\n",
596 (unsigned int)(uiFixedAddr & 0xFFFFFFFF), pass_count, err_count));
597#endif
598 }
599
600 if(u1DumpInfo)
601 {
602 // Read gating error flag
603 #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
604 DramcDumpDebugInfo(p);
605 #endif
606 }
607
608 #if GATING_ONLY_FOR_DEBUG
609 DramcGatingDebugExit(p);
610 #endif
611}
612#endif
613
614
615#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
616#if !EMMC_READY
617u32 g_dram_save_time_init_done[DRAM_DFS_SHUFFLE_MAX]={0};
618SAVE_TIME_FOR_CALIBRATION_T SaveTimeDataByShuffle[DRAM_DFS_SHUFFLE_MAX];
619#endif
620
621DRAM_STATUS_T DramcSave_Time_For_Cal_End(DRAMC_CTX_T *p)
622{
623 if(!u1IsLP4Family(p->dram_type))
624 return DRAM_FAIL;
625
626 if(u1IsLP4Family(p->dram_type) && (p->femmc_Ready==0))
627 {
628 #if EMMC_READY
629 write_offline_dram_calibration_data(p->shu_type, p->pSavetimeData);
630 mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to emmc\n"));
631 #else
632 g_dram_save_time_init_done[p->shu_type] =1;
633 memcpy(&(SaveTimeDataByShuffle[p->shu_type]), p->pSavetimeData, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
634 mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to SW memory\n"));
635 #endif
636 }
637 else
638 {
639 mcSHOW_DBG_MSG(("[FAST_K] Bypass saving calibration result to emmc\n"));
640 }
641
642 return DRAM_OK;
643}
644
645DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p)
646{
647 if(!u1IsLP4Family(p->dram_type))
648 return DRAM_FAIL;
649
650 // Parepare fask k data
651 #if EMMC_READY
652 // scy: only need to read emmc one time for each boot-up
653 //if (g_dram_save_time_init_done == 1)
654 // return DRAM_OK;
655 //else
656 // g_dram_save_time_init_done = 1;
657 if(read_offline_dram_calibration_data(p->shu_type, p->pSavetimeData)<0)
658 {
659 p->femmc_Ready=0;
660 memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
661 }
662 else
663 {
664 p->femmc_Ready=1;
665 }
666
667 #else //EMMC is not avaliable, load off-line data
668
669 if(g_dram_save_time_init_done[p->shu_type] ==0)
670 {
671 p->femmc_Ready=0;
672 memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
673 }
674 else
675 {
676 memcpy(p->pSavetimeData, &(SaveTimeDataByShuffle[p->shu_type]), sizeof(SAVE_TIME_FOR_CALIBRATION_T));
677 p->femmc_Ready=1;
678 }
679 #endif
680
681 if(p->femmc_Ready==1)
682 {
683 if(p->frequency < 1600)
684 { // freq < 1600, TX and RX tracking are disable. Therefore, bypass calibration.
685 p->Bypass_RDDQC=1;
686 p->Bypass_RXWINDOW=1;
687 p->Bypass_TXWINDOW=1;
688 }
689 else
690 {
691 p->Bypass_RDDQC=0;
692 p->Bypass_RXWINDOW=0;
693 p->Bypass_TXWINDOW=0;
694 }
695
696#if RUNTIME_SHMOO_RELEATED_FUNCTION
697 p->Bypass_RDDQC=1;
698 p->Bypass_RXWINDOW=1;
699 p->Bypass_TXWINDOW=1;
700#endif
701 }
702
703#if EMMC_READY
704 mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, femmc_Ready=%d\n", p->shu_type, p->femmc_Ready));
705#else
706 mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, Init_done=%d, femmc_Ready=%d\n", p->shu_type, g_dram_save_time_init_done[p->shu_type], p->femmc_Ready));
707#endif
708 mcSHOW_DBG_MSG(("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW));
709
710 return DRAM_OK;
711}
712
713
714#endif
715
716U8 gGet_MDL_Used_Flag=0;
717void Set_MDL_Used_Flag(U8 value)
718{
719 gGet_MDL_Used_Flag = value;
720}
721
722U8 Get_MDL_Used_Flag(void)
723{
724 return gGet_MDL_Used_Flag;
725}
726
727#if TX_K_DQM_WITH_WDBI
728void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff)
729{
730 S8 u1TXShiftUI;
731
732 u1TXShiftUI = (u1OnOff) ? -8 : 8;
733 DramcWriteMinus1MCKForWriteDBI(p, u1TXShiftUI); //Tx DQ/DQM -1 MCK for write DBI ON
734
735 SetDramModeRegForWriteDBIOnOff(p, u1OnOff);
736 DramcWriteDBIOnOff(p, u1OnOff);
737}
738#endif
739
740static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
741{
742 U8 u1RankMax;
743 S8 s1RankIdx;
744 //DRAM_STATUS_T VrefStatus;
745
746#ifdef DDR_INIT_TIME_PROFILING
747 U32 CPU_Cycle;
748 TimeProfileBegin();
749#endif
750
751#if ENABLE_PHY_RX_INPUT_OFFSET // skip when bring up
752 ///TODO: no shuffle, only need to do once under highest freq.
753 if(p->frequency == u2DFSGetHighestFreq(p))
754 DramcRXInputBufferOffsetCal(p);
755
756#ifdef DDR_INIT_TIME_PROFILING
757 CPU_Cycle=TimeProfileEnd();
758 mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle));
759 TimeProfileBegin();
760#endif
761#endif
762
763
764#if GATING_ADJUST_TXDLY_FOR_TRACKING
765 DramcRxdqsGatingPreProcess(p);
766#endif
767
768 if (p->support_rank_num==RANK_DUAL)
769 u1RankMax = RANK_MAX;
770 else
771 u1RankMax = RANK_1;
772
773 //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP4_DramcSetting, so don't need to disable again
774
775#if ENABLE_CA_TRAINING
776 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
777 {
778 vSetRank(p, s1RankIdx);
779 #if PINMUX_AUTO_TEST_PER_BIT_CA
780 CheckCAPinMux(p);
781 #endif
782 CmdBusTrainingLP4(p);
783
784#if EYESCAN_LOG
785 print_EYESCAN_LOG_message(p, 0); //draw CBT eyescan
786#endif
787#ifdef DDR_INIT_TIME_PROFILING
788 CPU_Cycle=TimeProfileEnd();
789 mcSHOW_TIME_MSG(("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle));
790 TimeProfileBegin();
791#endif
792 }
793
794 vSetRank(p, RANK_0);
795
796#if DUAL_FREQ_K
797 No_Parking_On_CLRPLL(p);
798#endif
799#endif //ENABLE_CA_TRAINING
800
801 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
802 {
803 vSetRank(p, s1RankIdx);
804
805#ifdef DEVIATION
806 {
807 U16 u2RXVrefDefault;
808 u2RXVrefDefault = vGetRXVrefDefault(p);
809 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_B0_DQ5), u2RXVrefDefault, SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); // LP4 and LP4x with term: 0xe
810 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_B1_DQ5), u2RXVrefDefault, SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1); // LP4 and LP4x with term: 0xe
811 }
812#endif
813
814//#if ENABLE_LP4_ZQ_CAL
815 //DramcZQCalibration(p); //ZQ calibration should be done before CBT and operated at low frequency, so it is moved to mode register init
816//#endif
817
818 #if ENABLE_WRITE_LEVELING
819 DramcWriteLeveling((DRAMC_CTX_T *) p);//Dram will be reset when finish write leveling
820
821 #ifdef DDR_INIT_TIME_PROFILING
822 CPU_Cycle=TimeProfileEnd();
823 mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
824 TimeProfileBegin();
825 #endif
826 #endif
827
828 #if LJPLL_FREQ_DEBUG_LOG
829 DDRPhyFreqMeter();
830 #endif
831
832 vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable
833
834 DramcRxdqsGatingCal(p);
835
836 #ifdef DDR_INIT_TIME_PROFILING
837 CPU_Cycle=TimeProfileEnd();
838 mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle));
839 TimeProfileBegin();
840 #endif
841
842 #if LJPLL_FREQ_DEBUG_LOG
843 DDRPhyFreqMeter();
844 #endif
845
846 #if PINMUX_AUTO_TEST_PER_BIT_RX
847 CheckRxPinMux(p);
848 #endif
849 DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 0);
850
851 #ifdef DDR_INIT_TIME_PROFILING
852 CPU_Cycle=TimeProfileEnd();
853 mcSHOW_TIME_MSG(("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle));
854 TimeProfileBegin();
855 #endif
856
857 #if LJPLL_FREQ_DEBUG_LOG
858 DDRPhyFreqMeter();
859 #endif
860
861#if MRW_CHECK_ONLY
862 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
863#endif
864#if TX_K_DQM_WITH_WDBI
865 //DramcWriteDBIOnOff() control both rank, need to recover for rank1 tx calibration
866 DramcWriteDBIOnOff(p, 0);
867#endif
868 DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQ_DQM, DISABLE_VREF_SCAN); //Vref scan disable
869 {
870 DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQ_ONLY, p->enable_tx_scan_vref);
871 }
872 #if PINMUX_AUTO_TEST_PER_BIT_TX
873 CheckTxPinMux(p);
874 #endif
875 DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQ_ONLY, DISABLE_VREF_SCAN);
876
877#if TX_K_DQM_WITH_WDBI
878 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
879 if(p->Bypass_TXWINDOW==0) //if bypass TX K, DQM will be calculate form DQ. (no need to K DQM)
880 #endif
881 {
882 if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON))
883 {
884 // K DQM with DBI_ON, and check DQM window spec.
885 //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"));
886 vSwitchWriteDBISettings(p, DBI_ON);
887 DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, DISABLE_VREF_SCAN);
888 vSwitchWriteDBISettings(p, DBI_OFF);
889 }
890 }
891#endif
892
893#if EYESCAN_LOG
894 Dramc_K_TX_EyeScan_Log(p);
895 print_EYESCAN_LOG_message(p, 2); //draw TX eyescan
896#endif
897
898 #ifdef DDR_INIT_TIME_PROFILING
899 CPU_Cycle=TimeProfileEnd();
900 mcSHOW_TIME_MSG(("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
901 TimeProfileBegin();
902 #endif
903
904 #if LJPLL_FREQ_DEBUG_LOG
905 DDRPhyFreqMeter();
906 #endif
907
908 DramcRxdatlatCal((DRAMC_CTX_T *) p);
909
910 #ifdef DDR_INIT_TIME_PROFILING
911 CPU_Cycle=TimeProfileEnd();
912 mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle));
913 TimeProfileBegin();
914 #endif
915
916 #if LJPLL_FREQ_DEBUG_LOG
917 DDRPhyFreqMeter();
918 #endif
919
920 DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 1);
921
922 #ifdef DDR_INIT_TIME_PROFILING
923 CPU_Cycle=TimeProfileEnd();
924 mcSHOW_TIME_MSG(("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
925 TimeProfileBegin();
926 #endif
927 // DramcRxdqsGatingCal(p);
928
929#if EYESCAN_LOG
930 print_EYESCAN_LOG_message(p, 1); //draw RX eyescan
931#endif
932
933#if TX_OE_CALIBATION
934 DramcTxOECalibration(p);
935#endif
936
937 vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
938
939 #if ENABLE_TX_TRACKING
940 #if 0 /* Starting from Vinson, no need to pre-calculate MR23 for different freqs */
941 if(gu1MR23Done==FALSE)
942 {
943 DramcDQSOSCAuto(p);
944 }
945 #endif
946 DramcDQSOSCAuto(p);
947 DramcDQSOSCMR23(p);
948 DramcDQSOSCSetMR18MR19(p);
949 #endif
950 }
951 vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate())
952
953 #if ENABLE_TX_TRACKING
954 DramcDQSOSCShuSettings(p);
955 #endif
956
957#if GATING_ADJUST_TXDLY_FOR_TRACKING
958 DramcRxdqsGatingPostProcess(p);
959#endif
960
961 if (p->support_rank_num==RANK_DUAL)
962 {
963 DramcDualRankRxdatlatCal(p);
964 }
965
966#if LJPLL_FREQ_DEBUG_LOG
967 DDRPhyFreqMeter();
968#endif
969
970 #ifdef DDR_INIT_TIME_PROFILING
971 CPU_Cycle=TimeProfileEnd();
972 mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle));
973 #endif
974}
975
976#if ENABLE_LP3_SW
977DRAM_STATUS_T CATrainingLP3(DRAMC_CTX_T *p);
978static void vCalibration_Flow_LP3(DRAMC_CTX_T *p)
979{
980 U8 u1RankMax;
981 S8 s1RankIdx;
982
983#ifdef DDR_INIT_TIME_PROFILING
984 U32 CPU_Cycle;
985 TimeProfileBegin();
986#endif
987
988 //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP3_DramcSetting, so don't need to disable again
989#if (fcFOR_CHIP_ID == fcLaurel)
990#if 0
991#if ENABLE_CA_TRAINING // skip when bring up
992 vSetRank(p, RANK_0);
993#if PINMUX_AUTO_TEST_PER_BIT_CA
994 CheckCAPinMux_LP3(p);
995#endif
996 CATrainingLP3(p);
997 #if CA_TRAINING_K_RANK1_ENABLE //if dual rank K is enable, rank 0 and 1 both should do CA training
998 if (p->support_rank_num==RANK_DUAL)
999 {
1000 vSetRank(p, RANK_1);
1001 #if PINMUX_AUTO_TEST_PER_BIT_CA
1002 CheckCAPinMux_LP3(p);
1003 #endif
1004 CATrainingLP3(p);
1005 vSetRank(p, RANK_0);
1006 //CATrainingLP3PostProcess(p); //set final CLK and CA delay as the result of averge delay of rank0 and rank1
1007 }
1008 #endif
1009#endif // end of ENABLE_CA_TRAINING
1010
1011#if LP3_MR_INIT_AFTER_CA_TRAIN
1012 u1PrintModeRegWrite =1;
1013 DramcModeRegInit_LP3(p, FALSE); // set mode register without reset dram.
1014 u1PrintModeRegWrite =0;
1015#endif
1016#endif
1017#endif
1018
1019#ifdef DDR_INIT_TIME_PROFILING
1020 CPU_Cycle=TimeProfileEnd();
1021 mcSHOW_TIME_MSG(("\tDRAMC CA train takes %d us\n", CPU_Cycle));
1022 TimeProfileBegin();
1023#endif
1024
1025#if GATING_ADJUST_TXDLY_FOR_TRACKING
1026 DramcRxdqsGatingPreProcess(p);
1027#endif
1028
1029 if (p->support_rank_num==RANK_DUAL)
1030 u1RankMax = RANK_MAX;
1031 else
1032 u1RankMax = RANK_1;
1033
1034 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
1035 {
1036 vSetRank(p, s1RankIdx);
1037
1038 vAutoRefreshSwitch(p, DISABLE); //If auto refresh don't disable at begin, auto refresh will be enable when K rank1 CAtraining and write leveling
1039
1040 #if (fcFOR_CHIP_ID == fcLaurel)
1041 #if 0
1042 if((p->support_rank_num==RANK_SINGLE) || ((p->support_rank_num==RANK_DUAL) && (s1RankIdx == RANK_0)))
1043 {
1044 #if ENABLE_WRITE_LEVELING
1045 DramcWriteLeveling((DRAMC_CTX_T *) p);//Dram will be reset when finish write leveling
1046 #endif
1047
1048 #ifdef DDR_INIT_TIME_PROFILING
1049 CPU_Cycle=TimeProfileEnd();
1050 mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
1051 TimeProfileBegin();
1052 #endif
1053 }
1054 #endif
1055 #endif
1056
1057 vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable
1058
1059 #if LJPLL_FREQ_DEBUG_LOG
1060 DDRPhyFreqMeter();
1061 #endif
1062
1063 DramcRxdqsGatingCal(p);
1064
1065 #ifdef DDR_INIT_TIME_PROFILING
1066 CPU_Cycle=TimeProfileEnd();
1067 mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle));
1068 TimeProfileBegin();
1069 #endif
1070
1071 #if LJPLL_FREQ_DEBUG_LOG
1072 DDRPhyFreqMeter();
1073 #endif
1074
1075 DramcRxdatlatCal((DRAMC_CTX_T *) p);
1076
1077 #ifdef DDR_INIT_TIME_PROFILING
1078 CPU_Cycle=TimeProfileEnd();
1079 mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n\r", s1RankIdx, CPU_Cycle));
1080 TimeProfileBegin();
1081 #endif
1082
1083 #if LJPLL_FREQ_DEBUG_LOG
1084 DDRPhyFreqMeter();
1085 #endif
1086
1087 #ifndef LP3_DUAL_RANK_RX_K
1088 if(s1RankIdx == RANK_0)
1089 #endif
1090 {
1091 #if PINMUX_AUTO_TEST_PER_BIT_RX_LP3
1092 CheckRxPinMux(p);
1093 #endif
1094 DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 1);
1095
1096 #ifdef DDR_INIT_TIME_PROFILING
1097 CPU_Cycle=TimeProfileEnd();
1098 mcSHOW_TIME_MSG(("\tRank %d RX takes %d us\n", s1RankIdx, CPU_Cycle));
1099 TimeProfileBegin();
1100 #endif
1101 }
1102
1103 #ifndef LP3_DUAL_RANK_TX_K
1104 if(s1RankIdx==RANK_0)
1105 #endif
1106 {
1107 DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQ_DQM, DISABLE_VREF_SCAN);
1108 #ifdef DDR_INIT_TIME_PROFILING
1109 CPU_Cycle=TimeProfileEnd();
1110 mcSHOW_TIME_MSG(("\tRank %d TX takes %d us\n", s1RankIdx, CPU_Cycle));
1111 TimeProfileBegin();
1112 #endif
1113 }
1114 }
1115
1116 vSetRank(p, RANK_0);
1117
1118 #if GATING_ADJUST_TXDLY_FOR_TRACKING
1119 DramcRxdqsGatingPostProcess(p);
1120 #endif
1121
1122 if (p->support_rank_num==RANK_DUAL)
1123 {
1124 DramcDualRankRxdatlatCal(p);
1125 }
1126
1127#if LJPLL_FREQ_DEBUG_LOG
1128 DDRPhyFreqMeter();
1129#endif
1130
1131 vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
1132
1133#ifdef DDR_INIT_TIME_PROFILING
1134 CPU_Cycle=TimeProfileEnd();
1135 mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle));
1136#endif
1137}
1138#endif
1139
1140
1141static void vDramCalibrationSingleChannel(DRAMC_CTX_T *p)
1142{
1143#if 0 //!__ETT__
1144 /*
1145 * Since DRAM calibration will cost much time,
1146 * kick wdt here to prevent watchdog timeout.
1147 * Sagy: Mask for the fcLaurel at the beginning
1148 */
1149#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
1150 mtk_wdt_restart();
1151#endif
1152#endif
1153
1154 if(u1IsLP4Family(p->dram_type))
1155 vCalibration_Flow_LP4(p);
1156#if ENABLE_LP3_SW
1157 else
1158 vCalibration_Flow_LP3(p);
1159#endif
1160}
1161
1162static void vDramCalibrationAllChannel(DRAMC_CTX_T *p)
1163{
1164 U8 channel_idx, rank_idx;
1165
1166#ifdef DDR_INIT_TIME_PROFILING
1167 U32 u4low_tick0, u4high_tick0, u4low_tick1, u4high_tick1;
1168#if __ETT__
1169 u4low_tick0 = GPT_GetTickCount(&u4high_tick0);
1170#else
1171 u4low_tick0 = get_timer(0);
1172#endif
1173#endif
1174
1175 for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++)
1176 {
1177 vSetPHY2ChannelMapping(p, u1ChannelSet[channel_idx]);// when switching channel, must update PHY to Channel Mapping
1178 vDramCalibrationSingleChannel(p);
1179 }
1180
1181 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1182
1183#if PRINT_CALIBRATION_SUMMARY
1184 vPrintCalibrationResult(p);
1185#endif
1186
1187#ifdef FOR_HQA_TEST_USED
1188 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1189 if(p->femmc_Ready==1)
1190 {
1191 mcSHOW_DBG_MSG(("\nCalibration fast K is enable, cannot show HQA measurement information\n"));
1192 }
1193 else
1194 #endif
1195 print_HQA_measure_message(p);
1196#endif
1197
1198#ifdef DEVIATION
1199 if(p->frequency == u2DFSGetHighestFreq(p))
1200 {
1201 vSetDeviationVariable();
1202 }
1203#endif
1204
1205 /* Enable/Disable calibrated rank's DBI function accordingly */
1206#if ENABLE_READ_DBI
1207 //Read DBI ON
1208 vSetRank(p, RANK_0);
1209 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1210
1211 DramcReadDBIOnOff(p, p->DBI_R_onoff[p->dram_fsp]);
1212#endif
1213
1214#if ENABLE_WRITE_DBI
1215 //Write DBI ON
1216 for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++)
1217 {
1218 vSetPHY2ChannelMapping(p, u1ChannelSet[channel_idx]);
1219
1220 for(rank_idx=RANK_0; rank_idx<RANK_MAX; rank_idx++)
1221 {
1222 vSetRank(p, rank_idx);
1223 DramcWriteMinus1MCKForWriteDBI(p, -8); //Tx DQ/DQM -1 MCK for write DBI ON
1224 }
1225 vSetRank(p, RANK_0);
1226 }
1227 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1228
1229 DramcWriteDBIOnOff(p, p->DBI_W_onoff[p->dram_fsp]);
1230
1231 // Improve Write DBI Power
1232 ApplyWriteDBIPowerImprove(p, ENABLE);
1233
1234 #if ENABLE_WRITE_DBI_Protect
1235 ApplyWriteDBIProtect(p, ENABLE);
1236 #endif
1237#endif
1238
1239#ifdef DDR_INIT_TIME_PROFILING
1240#if __ETT__
1241 u4low_tick1 = GPT_GetTickCount(&u4high_tick1);
1242 mcSHOW_TIME_MSG((" (4) vDramCalibrationAllChannel() take %d ms\n\r",((u4low_tick1-u4low_tick0)*76)/1000000));
1243#else
1244 u4low_tick1 = get_timer(u4low_tick0);
1245 mcSHOW_TIME_MSG((" (4) vDramCalibrationAllChannel() take %d ms\n\r",u4low_tick1));
1246#endif
1247#endif
1248}
1249
1250
1251static void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p)
1252{
1253 U8 u1RankMax;
1254 S8 s1RankIdx;
1255
1256 if(u1IsLP4Family(p->dram_type))
1257 {
1258#if GATING_ADJUST_TXDLY_FOR_TRACKING
1259 DramcRxdqsGatingPreProcess(p);
1260#endif
1261
1262 if (p->support_rank_num==RANK_DUAL)
1263 u1RankMax = RANK_MAX;
1264 else
1265 u1RankMax = RANK_1;
1266
1267 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
1268 {
1269 vSetRank(p, s1RankIdx);
1270
1271 vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable
1272 DramcRxdqsGatingCal(p);
1273 DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 0);
1274
1275#if MRW_CHECK_ONLY
1276 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
1277#endif
1278 vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
1279 }
1280
1281 vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate())
1282
1283#if GATING_ADJUST_TXDLY_FOR_TRACKING
1284 DramcRxdqsGatingPostProcess(p);
1285#endif
1286 }
1287 else // LP3
1288 {
1289 vDramCalibrationSingleChannel(p); ///TODO: vCalibration_Flow_For_MDL for LP3
1290 }
1291}
1292
1293
1294int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInfo)
1295{
1296 U8 u1ChannelIdx, u1RankIdx, u1DieNumber=0;
1297 U16 u2Density;
1298 U64 u8Size = 0, u8Size_backup = 0;
1299 U64 u8ChannelSize;
1300 U32 u4ChannelNumber=1, u4RankNumber=1;
1301
1302 if (p->revision_id != REVISION_ID_MAGIC)
1303 return 0;
1304
1305 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1306
1307 // Read MR5 for Vendor ID
1308 DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die.
1309 p->vendor_id &= 0xFF;
1310 mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id));
1311 // Read MR6 for Revision ID
1312 DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die.
1313 mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id));
1314
1315 if(DramInfo != NULL)
1316 {
1317 DramInfo->u2MR5VendorID = p->vendor_id;
1318 DramInfo->u2MR6RevisionID = p->revision_id;
1319#ifdef DRAM_ADAPTIVE
1320 DramInfo->u4RankNum = p->support_rank_num;
1321#endif
1322 for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
1323 for(u1RankIdx =0; u1RankIdx<RANK_MAX; u1RankIdx++)
1324 DramInfo->u8MR8Density[u1ChannelSet[u1ChannelIdx]][u1RankIdx] =0;
1325 }
1326
1327 // Read MR8 for dram density
1328 for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
1329 for(u1RankIdx =0; u1RankIdx<(p->support_rank_num); u1RankIdx++)
1330 {
1331 #if 0//PRINT_CALIBRATION_SUMMARY
1332 if((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] !=0) && \
1333 (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx]==0))
1334 #endif
1335 {
1336 vSetPHY2ChannelMapping(p, u1ChannelSet[u1ChannelIdx]);
1337 DramcModeRegReadByRank(p, u1RankIdx, 0, &(gu2MR0_Value[u1RankIdx]));
1338 mcSHOW_DBG_MSG(("MR0 0x%x\n", gu2MR0_Value[u1RankIdx]));
1339 DramcModeRegReadByRank(p, u1RankIdx, 8, &u2Density);
1340 mcSHOW_DBG_MSG(("MR8 %x\n", u2Density));
1341#ifdef DRAM_ADAPTIVE
1342 if ((u2Density & 0x1) && !u1IsLP4Family(p->dram_type))
1343 DramInfo->u4BankMode = BANK_TYPE_S2;
1344 else
1345 DramInfo->u4BankMode = BANK_TYPE_S4;
1346#endif
1347 u1DieNumber =1;
1348 if(p->dram_type == TYPE_LPDDR3)
1349 {
1350 if(((u2Density >> 6) & 0x3)==1) //OP[7:6] =0, x16 (2 die)
1351 u1DieNumber =2;
1352 } else if (u1IsLP4Family(p->dram_type)) {
1353 if(((u2Density >> 6) & 0x3) == 1) //OP[7:6] =0, x16 (normal mode)
1354 u1DieNumber =2;
1355 }
1356#ifdef DRAM_ADAPTIVE
1357 if (DramInfo != NULL)
1358 DramInfo->u1DieNum[u1RankIdx] = u1DieNumber;
1359#endif
1360 u2Density = (u2Density>>2)&0xf;
1361
1362 if (u1IsLP4Family(p->dram_type))
1363 {
1364 switch(u2Density)
1365 {
1366 ///TODO: Darren, please check the value of u8Size.
1367 case 0x0:
1368 u8Size = 0x20000000; //4Gb
1369 //DBG_MSG("[EMI]DRAM density = 4Gb\n");
1370 break;
1371 case 0x1:
1372 u8Size = 0x30000000; //6Gb
1373 //DBG_MSG("[EMI]DRAM density = 6Gb\n");
1374 break;
1375 case 0x2:
1376 u8Size = 0x40000000; //8Gb
1377 //DBG_MSG("[EMI]DRAM density = 8Gb\n");
1378 break;
1379 case 0x3:
1380 u8Size = 0x60000000; //12Gb
1381 //DBG_MSG("[EMI]DRAM density = 12Gb\n");
1382 break;
1383 case 0x4:
1384 u8Size = 0x80000000; //16Gb
1385 //DBG_MSG("[EMI]DRAM density = 16Gb\n");
1386 break;
1387 case 0x5:
1388 u8Size = 0xc0000000; //24Gb
1389 //DBG_MSG("[EMI]DRAM density = 24Gb\n");
1390 break;
1391 case 0x6:
1392 u8Size = 0x100000000L; //32Gb
1393 //DBG_MSG("[EMI]DRAM density = 32Gb\n");
1394 break;
1395 default:
1396 u8Size = 0; //reserved
1397 }
1398 }
1399#if ENABLE_LP3_SW
1400 else
1401 {
1402 switch(u2Density)
1403 {
1404 case 0x0:
1405 u8Size = 0x800000; //64Mb
1406 //DBG_MSG("[EMI]DRAM density = 64Mb\n");
1407 break;
1408 case 0x1:
1409 u8Size = 0x1000000; //128Mb
1410 //DBG_MSG("[EMI]DRAM density = 128Mb\n");
1411 break;
1412 case 0x2:
1413 u8Size = 0x2000000; //256Mb
1414 //DBG_MSG("[EMI]DRAM density = 256Mb\n");
1415 break;
1416 case 0x3:
1417 u8Size = 0x4000000; //512Mb
1418 //DBG_MSG("[EMI]DRAM density = 512Mb\n");
1419 break;
1420 case 0x4:
1421 u8Size = 0x8000000; //1Gb
1422 //DBG_MSG("[EMI]DRAM density = 1Gb\n");
1423 break;
1424 case 0x5:
1425 u8Size = 0x10000000; //2Gb
1426 //DBG_MSG("[EMI]DRAM density = 2Gb\n");
1427 break;
1428 case 0x6:
1429 u8Size = 0x20000000; //4Gb
1430 //DBG_MSG("[EMI]DRAM density = 4Gb\n");
1431 break;
1432 case 0xE:
1433 u8Size = 0x30000000; //6Gb
1434 //DBG_MSG("[EMI]DRAM density = 6Gb\n");
1435 break;
1436 case 0x7:
1437 u8Size = 0x40000000; //8Gb
1438 //DBG_MSG("[EMI]DRAM density = 8Gb\n");
1439 break;
1440 case 0xD:
1441 u8Size = 0x60000000; //12Gb
1442 //DBG_MSG("[EMI]DRAM density = 12Gb\n");
1443 break;
1444 case 0x8:
1445 u8Size = 0x80000000; //16Gb
1446 //DBG_MSG("[EMI]DRAM density = 16Gb\n");
1447 break;
1448 //case 0x9:
1449 //u8Size = 0x100000000L; //32Gb
1450 //DBG_MSG("[EMI]DRAM density = 32Gb\n");
1451 //break;
1452 default:
1453 u8Size = 0; //reserved
1454 }
1455 }
1456#endif /* ENABLE_LP3_SW */
1457 if (u8Size_backup < u8Size) // find max dram size for vDramcACTimingOptimize
1458 {
1459 u8Size_backup = u8Size;
1460 p->density = u2Density;
1461 }
1462
1463 u8Size *= u1DieNumber;
1464 u8ChannelSize = u8Size;
1465 u4ChannelNumber = p->support_channel_num;
1466
1467 if (p->support_rank_num==RANK_DUAL)
1468 {
1469 u4RankNumber = 2;
1470 }
1471
1472 p->ranksize[u1RankIdx] = (u8ChannelSize/u4RankNumber)*u4ChannelNumber;
1473
1474 if(DramInfo != NULL)
1475 DramInfo->u8MR8Density[u1ChannelSet[u1ChannelIdx]][u1RankIdx] = u8Size;
1476 }
1477 mcSHOW_DBG_MSG(("BankMode = %s\n", DramInfo->u4BankMode == BANK_TYPE_S2 ? "S2" : "S4" ));
1478 mcSHOW_DBG_MSG(("CH%d, RK%d, DieNum %d, Density %llx, RKsize %llx.\n", u1ChannelSet[u1ChannelIdx], u1RankIdx, u1DieNumber, u8Size, p->ranksize[u1RankIdx]));
1479 }
1480
1481 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1482
1483 return 0;
1484}
1485
1486#if ENABLE_RANK_NUMBER_AUTO_DETECTION
1487void DramRankNumberDetection(DRAMC_CTX_T *p)
1488{
1489 U8 u1RankBak;
1490
1491 u1RankBak = u1GetRank(p); // backup current rank setting
1492
1493 vSetPHY2ChannelMapping(p, u1ChannelSet[0]); // when switching channel, must update PHY to Channel Mapping
1494 vSetRank(p, RANK_1);
1495
1496 if(DramcWriteLeveling((DRAMC_CTX_T *) p) == DRAM_OK)//Dram will be reset when finish write leveling
1497 {
1498 p->support_rank_num = RANK_DUAL;
1499 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), 0, RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM); //keep support_rank_num to reserved rg
1500 }
1501 else
1502 {
1503 p->support_rank_num = RANK_SINGLE;
1504 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), 1, RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM); //keep support_rank_num to reserved rg
1505 }
1506 mcSHOW_DBG_MSG(("[RankNumberDetection] %d\n", p->support_rank_num));
1507
1508 vSetRank(p, u1RankBak); // restore rank setting
1509}
1510#endif
1511
1512U8 gPRE_MIOCK_JMETER_HQA_USED_flag=0;
1513void Set_PRE_MIOCK_JMETER_HQA_USED_flag(U8 value)
1514{
1515 gPRE_MIOCK_JMETER_HQA_USED_flag = value;
1516}
1517U8 Get_PRE_MIOCK_JMETER_HQA_USED_flag(void)
1518{
1519 return gPRE_MIOCK_JMETER_HQA_USED_flag;
1520}
1521
1522#ifdef ENABLE_MIOCK_JMETER
1523void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p)
1524{
1525 U32 backup_freq_sel, backup_channel;
1526
1527#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1528 U32 channel_idx;
1529
1530 if(p->femmc_Ready==1)
1531 {
1532 for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++)
1533 {
1534 //for (shuffleIdx = DRAM_DFS_SHUFFLE_1; shuffleIdx < DRAM_DFS_SHUFFLE_MAX; shuffleIdx++)
1535 {
1536 ucg_num_dlycell_perT_all[p->shu_type][u1ChannelSet[channel_idx]] = p->pSavetimeData->ucnum_dlycell_perT;
1537 u2gdelay_cell_ps_all[p->shu_type][u1ChannelSet[channel_idx]] = p->pSavetimeData->u2DelayCellTimex100;
1538 }
1539 }
1540
1541 p->ucnum_dlycell_perT = p->pSavetimeData->ucnum_dlycell_perT;
1542 p->u2DelayCellTimex100 = p->pSavetimeData->u2DelayCellTimex100;
1543 return;
1544 }
1545#endif
1546
1547
1548 backup_freq_sel = p->freq_sel;
1549 backup_channel = p->channel;
1550
1551 mcSHOW_DBG_MSG3(("[JMETER_HQA]\n"));
1552 Set_PRE_MIOCK_JMETER_HQA_USED_flag(1);
1553
1554 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
1555 DramcMiockJmeterHQA(p);
1556#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1557 if(p->femmc_Ready==0)
1558 {
1559 #if 0
1560 for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++)
1561 {
1562 for (shuffleIdx = DRAM_DFS_SHUFFLE_1; shuffleIdx < DRAM_DFS_SHUFFLE_MAX; shuffleIdx++)
1563 {
1564 p->pSavetimeData->ucg_num_dlycell_perT_all[channel_idx] = ucg_num_dlycell_perT_all[p->shu_type][channel_idx];
1565 p->pSavetimeData->u2gdelay_cell_ps_all[channel_idx] = u2gdelay_cell_ps_all[p->shu_type][channel_idx];
1566 }
1567 }
1568 #endif
1569 p->pSavetimeData->ucnum_dlycell_perT = p->ucnum_dlycell_perT;
1570 p->pSavetimeData->u2DelayCellTimex100 = p->u2DelayCellTimex100;
1571 }
1572#endif
1573 vSetPHY2ChannelMapping(p, backup_channel);
1574
1575 #if 0
1576 p->freq_sel = LP4_DDR2667;
1577 DDRPhyFreqSel(p, p->freq_sel);
1578 vSetVcoreByFreq(p);
1579 DramcInit((DRAMC_CTX_T *) p);
1580 for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++)
1581 {
1582 vSetPHY2ChannelMapping(p, channel_idx);
1583 DramcMiockJmeterHQA(p);
1584 }
1585 vSetPHY2ChannelMapping(p, backup_channel);
1586 #endif
1587
1588 Set_PRE_MIOCK_JMETER_HQA_USED_flag(0);
1589
1590 p->freq_sel = backup_freq_sel;
1591}
1592#endif
1593
1594#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
1595void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p)
1596{
1597
1598 U8 backup_channel, backup_rank;
1599 U16 tx_pi_delay, tx_dqm_pi_delay;
1600 U8 ui_large_value, ui_small_value, pi_value;
1601 U8 ui_dqm_large_value, ui_dqm_small_value, pi_dqm_value;
1602#if 0
1603 U8 ui_oen_large_value, ui_oen_small_value, pi_oen_value;
1604 U8 ui_dqm_oen_large_value, ui_dqm_oen_small_value, pi_dqm_oen_value;
1605#endif
1606
1607 backup_channel = p->channel;
1608 backup_rank = p->rank;
1609
1610 p->channel = RUNTIME_SHMOO_TEST_CHANNEL;
1611 p->rank = RUNTIME_SHMOO_TEST_RANK;
1612
1613 if (RUNTIME_SHMOO_TEST_BYTE == 0)
1614 {
1615 tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), SHURK0_SELPH_DQ0_TXDLY_DQ0) * 256 +
1616 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), SHURK0_SELPH_DQ2_DLY_DQ0) * 32 +
1617 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0);
1618
1619 tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), SHURK0_SELPH_DQ1_TXDLY_DQM0) * 256 +
1620 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), SHURK0_SELPH_DQ3_DLY_DQM0) * 32 +
1621 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0);
1622 }
1623 else
1624 {
1625 tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), SHURK0_SELPH_DQ0_TXDLY_DQ1) * 256 +
1626 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), SHURK0_SELPH_DQ2_DLY_DQ1) * 32 +
1627 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1);
1628
1629 tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), SHURK0_SELPH_DQ1_TXDLY_DQM1) * 256 +
1630 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), SHURK0_SELPH_DQ3_DLY_DQM1) * 32 +
1631 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1);
1632 }
1633
1634 mcSHOW_ERR_MSG(("fra femmc_Ready = %d ==\n",p->femmc_Ready));
1635
1636 if (p->femmc_Ready==0 ||
1637 ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) //first K
1638 {
1639 p->pSavetimeData->Runtime_Shmoo_para.flag= 0; //on going
1640 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = tx_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START;
1641 p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay;
1642 p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = tx_dqm_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START;
1643 p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay;
1644 if (RUNTIME_SHMOO_TEST_VREF_START<51)
1645 {
1646 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0;
1647 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START;
1648 }
1649 else
1650 {
1651 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
1652 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START-51+21;
1653 }
1654 p->pSavetimeData->Runtime_Shmoo_para.TX_Channel = RUNTIME_SHMOO_TEST_CHANNEL;
1655 p->pSavetimeData->Runtime_Shmoo_para.TX_Rank = RUNTIME_SHMOO_TEST_RANK;
1656 p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE;
1657 }
1658 else if (dramc_get_rshmoo_step())
1659 {
1660 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
1661 if (p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END)
1662 {
1663 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay;
1664 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
1665
1666 if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END)
1667 {
1668 p->pSavetimeData->Runtime_Shmoo_para.flag= 0xff; //test finish
1669 }
1670 else
1671 {
1672 if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0)
1673 {
1674 if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50)
1675 {
1676 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
1677 p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30;
1678 }
1679 }
1680 }
1681 }
1682
1683 p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
1684 if (p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END)
1685 {
1686 p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay;
1687 }
1688 }
1689
1690 mcSHOW_ERR_MSG(("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE ));
1691
1692 if (p->pSavetimeData->Runtime_Shmoo_para.flag != 0xff)
1693 {
1694#if __ETT__
1695 mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f));
1696 mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START));
1697
1698 mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value));
1699 mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
1700#else
1701 mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f));
1702 mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START));
1703
1704 mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value));
1705 mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
1706#endif
1707
1708 TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay, 1, &ui_large_value, &ui_small_value, &pi_value);
1709 TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay, 1, &ui_dqm_large_value, &ui_dqm_small_value, &pi_dqm_value);
1710#if 0
1711 TxWinTransferDelayToUIPI(p, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-TX_DQ_OE_SHIFT*32, 0, 0, &ui_oen_large_value, &ui_oen_small_value, &pi_oen_value);
1712 TxWinTransferDelayToUIPI(p, p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay-TX_DQ_OE_SHIFT*32, 0, 0, &ui_dqm_oen_large_value, &ui_dqm_oen_small_value, &pi_dqm_oen_value);
1713
1714 if (RUNTIME_SHMOO_TEST_BYTE == 0)
1715 {
1716 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), P_Fld(ui_large_value, SHURK0_SELPH_DQ0_TXDLY_DQ0) | \
1717 P_Fld(ui_oen_large_value, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0));
1718 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), P_Fld(ui_small_value, SHURK0_SELPH_DQ2_DLY_DQ0) | \
1719 P_Fld(ui_oen_small_value, SHURK0_SELPH_DQ2_DLY_OEN_DQ0));
1720 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), pi_value, SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0);
1721
1722#if 1 //DQM move together
1723 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), P_Fld(ui_dqm_large_value, SHURK0_SELPH_DQ1_TXDLY_DQM0) | \
1724 P_Fld(ui_dqm_oen_large_value, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0));
1725 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), P_Fld(ui_dqm_small_value, SHURK0_SELPH_DQ3_DLY_DQM0) | \
1726 P_Fld(ui_dqm_oen_small_value, SHURK0_SELPH_DQ3_DLY_OEN_DQM0));
1727 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), pi_dqm_value, SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0);
1728#endif
1729 }
1730 else
1731 {
1732 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), P_Fld(ui_large_value, SHURK0_SELPH_DQ0_TXDLY_DQ1) | \
1733 P_Fld(ui_oen_large_value, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1));
1734 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), P_Fld(ui_small_value, SHURK0_SELPH_DQ2_DLY_DQ1) | \
1735 P_Fld(ui_oen_small_value, SHURK0_SELPH_DQ2_DLY_OEN_DQ1));
1736 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), pi_value, SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1);
1737
1738#if 1 //DQM move together
1739 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), P_Fld(ui_dqm_large_value, SHURK0_SELPH_DQ1_TXDLY_DQM1) | \
1740 P_Fld(ui_dqm_oen_large_value, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1));
1741 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), P_Fld(ui_dqm_small_value, SHURK0_SELPH_DQ3_DLY_DQM1) | \
1742 P_Fld(ui_dqm_oen_small_value, SHURK0_SELPH_DQ3_DLY_OEN_DQM1));
1743 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), pi_dqm_value, SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1);
1744#endif
1745 }
1746#else
1747 if (RUNTIME_SHMOO_TEST_BYTE == 0)
1748 {
1749 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), ui_large_value, SHURK0_SELPH_DQ0_TXDLY_DQ0);
1750 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), ui_small_value, SHURK0_SELPH_DQ2_DLY_DQ0);
1751 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), pi_value, SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0);
1752
1753 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), ui_dqm_large_value, SHURK0_SELPH_DQ1_TXDLY_DQM0);
1754 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), ui_dqm_small_value, SHURK0_SELPH_DQ3_DLY_DQM0);
1755 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ7), pi_dqm_value, SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0);
1756 }
1757 else
1758 {
1759 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ0), ui_large_value, SHURK0_SELPH_DQ0_TXDLY_DQ1);
1760 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ2), ui_small_value, SHURK0_SELPH_DQ2_DLY_DQ1);
1761 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), pi_value, SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1);
1762
1763 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ1), ui_dqm_large_value, SHURK0_SELPH_DQ1_TXDLY_DQM1);
1764 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQ3), ui_dqm_small_value, SHURK0_SELPH_DQ3_DLY_DQM1);
1765 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B1_DQ7), pi_dqm_value, SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1);
1766 }
1767#endif
1768 DramcTXSetVref(p, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value);
1769 }
1770
1771 //save parameters to eMMC
1772#if EMMC_READY
1773 write_offline_dram_calibration_data(p->shu_type, p->pSavetimeData);
1774#endif
1775 mcSHOW_ERR_MSG(("Fra Save calibration result to emmc\n"));
1776
1777 //copy parameters to memory for kernel test script used
1778 //wait for YiRong's SRAM copy function
1779 dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel,
1780 p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
1781 p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay, 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == 0xff) ? 1 : 0);
1782
1783
1784 //DLL all off from Justin
1785 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_CA_DLL_ARPI2), 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
1786 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B0_DLL_ARPI2), 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
1787 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B1_DLL_ARPI2), 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
1788
1789 p->channel = backup_channel;
1790 p->rank = backup_rank;
1791}
1792#endif
1793
1794#ifdef FIRST_BRING_UP
1795void Test_Broadcast_Feature(DRAMC_CTX_T *p)
1796{
1797 U32 u4RegBackupAddress[] =
1798 {
1799 (DRAMC_REG_SHURK0_DQSIEN),
1800 (DRAMC_REG_SHURK0_DQSIEN+SHIFT_TO_CHB_ADDR),
1801
1802 (DDRPHY_B0_DQ0),
1803 (DDRPHY_B0_DQ0+SHIFT_TO_CHB_ADDR),
1804 };
1805 U32 read_value;
1806 U8 backup_broadcast;
1807
1808 backup_broadcast = GetDramcBroadcast();
1809
1810 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
1811
1812 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
1813
1814 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
1815
1816 vIO32Write4B(DRAMC_REG_SHURK0_DQSIEN, 0xA55A00FF);
1817 vIO32Write4B(DDRPHY_B0_DQ0, 0xA55A00FF);
1818
1819 read_value = u4IO32Read4B(DRAMC_REG_SHURK0_DQSIEN+SHIFT_TO_CHB_ADDR);
1820 if (read_value != 0xA55A00FF)
1821 {
1822 mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
1823 while(1);
1824 }
1825
1826 read_value = u4IO32Read4B(DDRPHY_B0_DQ0+SHIFT_TO_CHB_ADDR);
1827 if (read_value != 0xA55A00FF)
1828 {
1829 mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
1830 while(1);
1831 }
1832
1833 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
1834
1835 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
1836
1837 DramcBroadcastOnOff(backup_broadcast);
1838}
1839#endif
1840
1841U8 u1TestLLL=0;
1842
1843#if ENABLE_SLT
1844#define SLT_MEM_TEST_LOOP 10
1845
1846static void do_dram_test_after_k(DRAMC_CTX_T *p)
1847{
1848 U8 loop = 0;
1849
1850 while (loop < SLT_MEM_TEST_LOOP) {
1851 mcSHOW_DBG_MSG(("\n[SLT][TA2_TEST] #%d\n", loop + 1));
1852 TA2_Test_Run_Time_HW(p);
1853
1854 mcSHOW_DBG_MSG(("\n[SLT][MEM_TEST] #%d\n", loop + 1));
1855 vDramCPUReadWriteTestAfterCalibration(p);
1856
1857 loop++;
1858 }
1859}
1860#endif
1861
1862int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used)
1863{
1864 #if !SW_CHANGE_FOR_SIMULATION
1865
1866 DRAMC_CTX_T * p;
1867
1868#ifdef DDR_INIT_TIME_PROFILING
1869 U32 CPU_Cycle;
1870 TimeProfileBegin();
1871#endif
1872
1873 if(u1IsLP4Family(dram_type))
1874 {
1875 psCurrDramCtx = &DramCtx_LPDDR4;
1876 }
1877 else
1878 {
1879#if (!__ETT__ && ENABLE_LP3_SW==0)
1880#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
1881// Preloader which does not support LP3
1882// scy: reduce code size by removing unused LPDDR3 structure
1883 mcSHOW_DBG_MSG(("[Init_DRAM] LPDDR3 not supported\n"));
1884 ASSERT(0);
1885#endif
1886#else
1887 psCurrDramCtx = &DramCtx_LPDDR3;
1888#endif
1889 }
1890
1891#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
1892 if (gtime_profiling_flag == 0)
1893 {
1894 memcpy(&gTimeProfilingDramCtx, psCurrDramCtx, sizeof(DRAMC_CTX_T));
1895 gtime_profiling_flag = 1;
1896 }
1897
1898 p = &gTimeProfilingDramCtx;
1899 gfirst_init_flag = 0;
1900
1901 if(u1IsLP4Family(p->dram_type))
1902 DramcConfInfraReset(p);
1903#else
1904 p = psCurrDramCtx;
1905#endif
1906
1907 Set_MDL_Used_Flag(get_mdl_used);
1908
1909 #if 0//__ETT__
1910 if(u1IsLP4Family(p->dram_type)) //ETT, LPDDR4 and 4x
1911 {
1912 p->dram_type = LP4_DRAM_TYPE_SELECT;
1913 p->dram_cbt_mode[RANK_0] = LP4_CBT_MODE;
1914 p->dram_cbt_mode[RANK_1] = LP4_CBT_MODE;
1915 }
1916 else //Preloader & ETTLPDDR3
1917 #endif
1918 {
1919 p->dram_type = dram_type;
1920
1921 /* Convert DRAM_CBT_MODE_EXTERN_T to DRAM_CBT_MODE_T */
1922 switch ((int)dram_cbt_mode_extern)
1923 {
1924 case CBT_R0_R1_NORMAL:
1925 p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
1926 p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
1927 break;
1928 case CBT_R0_R1_BYTE:
1929 p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1;
1930 p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
1931 break;
1932 case CBT_R0_NORMAL_R1_BYTE:
1933 p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
1934 p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
1935 break;
1936 case CBT_R0_BYTE_R1_NORMAL:
1937 p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1;
1938 p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
1939 break;
1940 default:
1941 mcSHOW_ERR_MSG(("Error!"));
1942 break;
1943 }
1944
1945 mcSHOW_DBG_MSG2(("dram_cbt_mode_extern: %d\n"
1946 "dram_cbt_mode [RK0]: %d, [RK1]: %d\n",
1947 (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1]));
1948 }
1949
1950 if(u1IsLP4Family(p->dram_type))
1951 {
1952 DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on
1953 }
1954 else
1955 {
1956 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //LP3 broadcast off
1957 }
1958
1959 if (gfirst_init_flag == 0)
1960 {
1961 MPLLInit();
1962 Global_Option_Init(p);
1963 gfirst_init_flag = 1;
1964 }
1965 Global_Option_Init2(p); // setting according to emi_settings
1966
1967#ifdef FIRST_BRING_UP
1968 Test_Broadcast_Feature(p);
1969#endif
1970
1971#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
1972 {
1973 U8 backup_broadcast;
1974 backup_broadcast = GetDramcBroadcast();
1975 EMI_Init(p);
1976 DramcBroadcastOnOff(backup_broadcast);
1977 }
1978#endif
1979
1980
1981 mcSHOW_DBG_MSG(("\n\n[Bianco] ETT version 0.0.0.1\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id));
1982
1983 vDramcInit_PreSettings(p);
1984
1985 // DramC & PHY init for all channels
1986 #if DUAL_FREQ_K
1987 SPM_Pinmux_Setting(p);
1988 if(u1IsLP4Family(p->dram_type))
1989 p->freq_sel = gFreqTbl[DRAM_DFS_SHUFFLE_1].freq_sel;
1990 #endif
1991
1992 //=== First frequency ======
1993 DDRPhyFreqSel(p, p->freq_sel);
1994 vSetVcoreByFreq(p);
1995
1996#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1997 DramcSave_Time_For_Cal_Init(p);
1998#endif
1999#ifndef LOOPBACK_TEST
2000#if EMI_LPBK_DRAM_USED //saint remove sw imp cal
2001 if (p->dram_type == TYPE_LPDDR4)
2002 {
2003 DramcSwImpedanceCal(p,1, 1); //within term
2004 }
2005 else if (p->dram_type == TYPE_LPDDR4X)
2006 {
2007 DramcSwImpedanceCal(p,1, 0); //without term
2008 DramcSwImpedanceCal(p,1, 1); //within term
2009 }
2010 else
2011 {
2012 //TYPE_LPDDR4P, TYPE_LPDDR3
2013 DramcSwImpedanceCal(p,1, 0); //without term
2014 }
2015
2016 //update ODTP/ODTN of term to unterm
2017 DramcUpdateImpedanceTerm2UnTerm(p);
2018#endif
2019#endif
2020#ifdef DDR_INIT_TIME_PROFILING
2021 CPU_Cycle=TimeProfileEnd();
2022 mcSHOW_TIME_MSG(("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle/1000));
2023#endif
2024
2025#ifdef DUMP_INIT_RG_LOG_TO_DE
2026 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
2027#endif
2028
2029 DFSInitForCalibration(p);
2030
2031#if defined(SLT)
2032 O1Path_Test(p);
2033#endif
2034
2035#ifdef TEST_MODE_MRS
2036 if(global_which_test == 0)
2037 TestModeTestMenu();
2038#endif
2039
2040#ifdef ENABLE_POST_PACKAGE_REPAIR
2041#ifdef SKH_POST_PACKAGE_REPAIR_LP3 //LP3
2042 PostPackageRepair();
2043#endif
2044#endif
2045
2046#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2047 if (p->femmc_Ready==1)
2048 {
2049 p->support_rank_num = p->pSavetimeData->support_rank_num;
2050 }
2051 else
2052#endif
2053 {
2054#if ENABLE_RANK_NUMBER_AUTO_DETECTION // only need to do this when DUAL_RANK_ENABLE is 1
2055 if (Get_MDL_Used_Flag()==GET_MDL_USED)
2056 {
2057 DramRankNumberDetection(p);
2058 DFSInitForCalibration(p); // Restore setting after rank dection (especially DQ= DQS+16)
2059 }
2060#endif
2061
2062#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2063 p->pSavetimeData->support_rank_num = p->support_rank_num;
2064#endif
2065 }
2066
2067 #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
2068 U8 backup_broadcast;
2069 backup_broadcast = GetDramcBroadcast();
2070 EMI_Init2();
2071 DramcBroadcastOnOff(backup_broadcast);
2072 #endif
2073
2074#if defined(SLT) && (EMI_LPBK_DRAM_USED == 0)
2075 EMI_LPBK_memory_test(p);
2076#endif
2077
2078 if (Get_MDL_Used_Flag()==GET_MDL_USED)
2079 {
2080 // only K CHA to save time
2081 vSetPHY2ChannelMapping(p, u1ChannelSet[0]);
2082 vCalibration_Flow_For_MDL(p); // currently for LP4
2083 GetDramInforAfterCalByMRR(p, DramInfo);
2084 return 0;
2085 }
2086 else //NORMAL_USED
2087 {
2088 vDramCalibrationAllChannel(p);
2089 GetDramInforAfterCalByMRR(p, DramInfo);
2090 vDramcACTimingOptimize(p);
2091 }
2092
2093#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2094 DramcSave_Time_For_Cal_End(p);
2095#endif
2096
2097#if (ENABLE_SLT == 1)
2098 vApplyConfigAfterCalibration(p);
2099 do_dram_test_after_k(p);
2100
2101 /* cal 2400 */
2102 DDRPhyFreqSel(p, LP4_MIDDLE_FREQSEL);
2103 vSetVcoreByFreq(p);
2104 DFSInitForCalibration(p);
2105 vDramCalibrationAllChannel(p);
2106 vDramcACTimingOptimize(p);
2107#endif
2108
2109#if DUAL_FREQ_K
2110 if(u1IsLP4Family(p->dram_type))
2111 {
2112 #ifdef MTK_FIXDDR1600_SUPPORT
2113 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_2);
2114 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3);
2115 #else
2116 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); //Darren NOTE: Please take care of gFreqTbl table when you update SHUFFLE_X
2117
2118 //=== Second frequency ======
2119 DDRPhyFreqSel(p, gFreqTbl[DRAM_DFS_SHUFFLE_2].freq_sel);
2120 vSetVcoreByFreq(p);
2121 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2122 DramcSave_Time_For_Cal_Init(p);
2123 #endif
2124 DFSInitForCalibration(p);
2125 vDramCalibrationAllChannel(p);
2126 vDramcACTimingOptimize(p);
2127 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_2); //Darren NOTE: Please take care of gFreqTbl table when you update SHUFFLE_X
2128 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2129 DramcSave_Time_For_Cal_End(p);
2130 #endif
2131
2132 //=== Third frequency ======
2133 DDRPhyFreqSel(p, gFreqTbl[DRAM_DFS_SHUFFLE_1].freq_sel);
2134 vSetVcoreByFreq(p);
2135 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2136 DramcSave_Time_For_Cal_Init(p);
2137 #endif
2138 DFSInitForCalibration(p);
2139 vDramCalibrationAllChannel(p);
2140 vDramcACTimingOptimize(p);
2141 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2142 DramcSave_Time_For_Cal_End(p);
2143 #endif
2144 #endif
2145 }
2146 else
2147 {
2148 #if 0
2149 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3);
2150 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_2);
2151 #else
2152 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); //save 1333 0.74V shuffle_2
2153
2154 DDRPhyFreqSel(p, LP3_DDR1600);
2155 vSetVcoreByFreq(p);
2156 DFSInitForCalibration(p);
2157 vDramCalibrationAllChannel(p);
2158 DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_2); //save 1333 0.74V shuffle_3
2159
2160 DDRPhyFreqSel(p, LP3_DDR1866);
2161 vSetVcoreByFreq(p);
2162 DFSInitForCalibration(p);
2163 vDramCalibrationAllChannel(p);
2164 #endif
2165 }
2166#endif
2167
2168#ifdef DDR_INIT_TIME_PROFILING
2169 TimeProfileBegin();
2170#endif
2171
2172 vApplyConfigAfterCalibration(p);
2173
2174#ifdef DUMP_INIT_AND_K_RG_LOG_TO_DE
2175 while (1) ;
2176#endif
2177
2178#ifdef ENABLE_POST_PACKAGE_REPAIR //LP4
2179#ifdef POST_PACKAGE_REPAIR_LP4
2180 PostPackageRepair();
2181#endif
2182#endif
2183
2184#if 0//TX_OE_CALIBATION, for DMA test
2185 U8 u1ChannelIdx, u1RankIdx;
2186 for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
2187 for(u1RankIdx =0; u1RankIdx<(p->support_rank_num); u1RankIdx++)
2188 {
2189 vSetPHY2ChannelMapping(p, u1ChannelIdx);
2190 vSetRank(p, u1RankIdx);
2191 DramcTxOECalibration(p);
2192 }
2193
2194 vSetPHY2ChannelMapping(p, CHANNEL_A);
2195 vSetRank(p,RANK_0);
2196
2197 U32 u4err_value;
2198 DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_PREPARE_DATA_ONLY, p->support_channel_num);
2199 u4err_value= DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_CHECK_DATA_ACCESS_AND_COMPARE, p->support_channel_num);
2200 mcSHOW_DBG_MSG(("DramC_TX_OE_Calibration 0x%X\n", u4err_value));
2201#endif
2202
2203#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
2204 DramcRunTimeShmooRG_BackupRestore(p);
2205#endif
2206
2207#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
2208 RunTime_Shmoo_update_parameters(p);
2209#endif
2210
2211#if !LCPLL_IC_SCAN
2212#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
2213 print_DBG_info(p);
2214 Dump_EMIRegisters(p);
2215#endif
2216#endif
2217
2218#if 0
2219 DramcRegDump(p);
2220#endif
2221
2222// ETT_NO_DRAM #endif
2223
2224#if ETT_NO_DRAM
2225 //NoDramDramcRegDump(p);
2226 NoDramRegFill();
2227#endif
2228
2229#if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING))
2230 DramcDummyReadForTrackingEnable(p);
2231 mcSHOW_DBG_MSG(("DUMMY_READ_FOR_TRACKING: ON\n"));
2232
2233 //Disable auto refresh: set R_DMREFDIS=1
2234 vAutoRefreshSwitch(p, DISABLE);
2235
2236 while(1)
2237 {
2238 mcSHOW_DBG_MSG(("\ndummy read is 1us ===\n"));
2239 DVS_DMY_RD_ENTR(p);
2240 mcDELAY_MS(5000);
2241 mcSHOW_DBG_MSG(("\ndummy read is 4us ===\n"));
2242 DVS_DMY_RD_EXIT(p);
2243 mcDELAY_MS(5000);
2244 }
2245#endif
2246
2247 #if DRAMC_MODEREG_CHECK
2248 DramcModeReg_Check(p);
2249 #endif
2250
2251 #if TA2_RW_TEST_AFTER_K
2252 mcSHOW_DBG_MSG(("\n[TA2_TEST]\n"));
2253 TA2_Test_Run_Time_HW(p);
2254 #endif
2255
2256 #if CPU_RW_TEST_AFTER_K
2257 mcSHOW_DBG_MSG(("\n[MEM_TEST] 02: After DFS, before run time config\n"));
2258 vDramCPUReadWriteTestAfterCalibration(p);
2259 #endif
2260
2261
2262 // when time profiling multi times, SW impedance tracking will fail when trakcing enable.
2263 // ignor SW impedance tracking when doing time profling
2264#if __ETT__
2265#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2266 if(!(u1IsLP4Family(p->dram_type) && (p->femmc_Ready==0)))
2267#elif defined(DDR_INIT_TIME_PROFILING)
2268 if(u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT-1)) //last time of loop
2269#endif
2270#endif
2271 {
2272 mcSHOW_DBG_MSG(("\n\nSettings after calibration\n\n"));
2273 DramcRunTimeConfig(p);
2274 }
2275
2276 #if TA2_RW_TEST_AFTER_K
2277 mcSHOW_DBG_MSG(("\n[TA2_TEST]\n"));
2278 TA2_Test_Run_Time_HW(p);
2279 #endif
2280
2281 #if CPU_RW_TEST_AFTER_K
2282 mcSHOW_DBG_MSG(("\n[MEM_TEST] 03: After run time config\n"));
2283 vDramCPUReadWriteTestAfterCalibration(p);
2284 #endif
2285
2286#if (ENABLE_SLT == 1)
2287 do_dram_test_after_k(p);
2288#endif
2289
2290#if (__ETT__ && CPU_RW_TEST_AFTER_K)
2291 /* 0x46000000 is LK base addr */
2292//while(1)
2293{
2294 int s4value;
2295 //if ((s4value = complex_mem_test (0x46000000, 0x2000)) == 0)
2296 if ((s4value = complex_mem_test (0x40024000, 0x20000)) == 0)
2297 {
2298 mcSHOW_DBG_MSG(("1st complex R/W mem test pass\n"));
2299 }
2300 else
2301 {
2302 mcSHOW_DBG_MSG(("1st complex R/W mem test fail :-%d\n", -s4value));
2303#if defined(SLT)
2304 while(1);
2305#endif
2306 }
2307}
2308#endif
2309
2310#if MRW_CHECK_ONLY
2311 vPrintFinalModeRegisterSetting(p);
2312#endif
2313
2314#ifdef DDR_INIT_TIME_PROFILING
2315 CPU_Cycle=TimeProfileEnd();
2316 mcSHOW_TIME_MSG(("(5) After calibration takes %d ms\n\r", CPU_Cycle/1000));
2317#endif // end of DDR_INIT_TIME_PROFILING
2318
2319#if defined(SLT)
2320 SLT_Test_DFS_Freq_Meter_Memory_Test(p);
2321#endif
2322
2323/* cc add. For FASTK, psCurrDramCtx and p are different Sync data back in case mismatch */
2324#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
2325 if (gtime_profiling_flag == 1)
2326 {
2327 memcpy(psCurrDramCtx, p, sizeof(DRAMC_CTX_T));
2328 }
2329#endif
2330
2331#endif//SW_CHANGE_FOR_SIMULATION
2332 return 0;
2333}
2334
2335
2336#if (FOR_DV_SIMULATION_USED!=0)
2337void DPI_main(void)
2338{
2339 DRAMC_CTX_T DramConfig;
2340
2341 DramConfig.channel = CHANNEL_A;
2342 DramConfig.support_rank_num = RANK_DUAL;
2343 // DramRank
2344 DramConfig.rank = RANK_0;
2345 // DRAM type
2346 DramConfig.dram_type = TYPE_LPDDR3;
2347 // DRAM Fast switch point type, only for LP4, useless in LP3
2348 DramConfig.dram_fsp = FSP_0;
2349 // IC and DRAM read DBI
2350 DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2351 DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3
2352 // IC and DRAM write DBI
2353 DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2354 DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3
2355 // bus width
2356 DramConfig.data_width = DATA_WIDTH_32BIT;
2357 // DRAMC internal test engine-2 parameters in calibration
2358 DramConfig.test2_1 = DEFAULT_TEST2_1_CAL;
2359 DramConfig.test2_2 = DEFAULT_TEST2_2_CAL;
2360 // DRAMC test pattern in calibration
2361 DramConfig.test_pattern = TEST_XTALK_PATTERN;
2362 // DRAMC operation clock frequency in MHz
2363 DramConfig.frequency = 800;
2364 // Switch to ENABLE or DISABLE low frequency write and high frequency read
2365 DramConfig.u2DelayCellTimex100 = 0;
2366
2367 DramConfig.enable_rx_scan_vref =DISABLE_VREF_SCAN;
2368 DramConfig.enable_tx_scan_vref =DISABLE_VREF_SCAN;
2369 //DramConfig.dynamicODT = DISABLE;
2370
2371 printf("main functino start!\n");
2372
2373 Init_DRAM(DramConfig.dram_type, CBT_R0_R1_NORMAL, NULL, NORMAL_USED);
2374}
2375
2376#define DV_SIMULATION_INIT_C 1
2377#define DV_SIMULATION_BEFORE_K 1
2378#define DV_SIMULATION_MIOCKJMETER 0
2379#define DV_SIMULATION_SW_IMPED 0
2380#define DV_SIMULATION_LP4_ZQ 0
2381#define DV_SIMULATION_CA_TRAINING 0
2382#define DV_SIMULATION_WRITE_LEVELING 0
2383#define DV_SIMULATION_GATING 0
2384#define DV_SIMULATION_DATLAT 0
2385#define DV_SIMULATION_RX_PERBIT 0
2386#define DV_SIMULATION_TX_PERBIT 0 // Please enable with write leveling
2387#define DV_SIMULATION_AFTER_K 1
2388#define DV_SIMULATION_DBI_ON 0
2389#define DV_SIMULATION_RUNTIME_CONFIG 0
2390#define DV_SIMULATION_RUN_TIME_MRW 0
2391U8 gu1BroadcastIsLP4 = TRUE;
2392
2393#if ENABLE_LP3_SW
2394void DPI_SW_main_LP3(DRAMC_CTX_T *DramConfig)
2395{
2396 int ii;
2397
2398 U8 gu1BroadcastIsLP4 = FALSE;
2399 DramConfig->channel = CHANNEL_A;
2400 DramConfig->support_rank_num = RANK_DUAL;
2401 // DramRank
2402 DramConfig->rank = RANK_0;
2403 DramConfig->freq_sel = LP3_DDR1066;
2404 // DRAM type
2405 DramConfig->dram_type = TYPE_LPDDR3;
2406 // DRAM Fast switch point type, only for LP4, useless in LP3
2407 DramConfig->dram_fsp = FSP_0;
2408 // DRAM CBT mode, only for LP4, useless in LP3
2409 DramConfig->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
2410 DramConfig->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
2411 // IC and DRAM read DBI
2412 DramConfig->DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2413 DramConfig->DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2414 // IC and DRAM write DBI
2415 DramConfig->DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2416 DramConfig->DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2417 // bus width
2418 DramConfig->data_width = DATA_WIDTH_32BIT;
2419 // DRAMC internal test engine-2 parameters in calibration
2420 DramConfig->test2_1 = DEFAULT_TEST2_1_CAL;
2421 DramConfig->test2_2 = DEFAULT_TEST2_2_CAL;
2422 // DRAMC test pattern in calibration
2423 DramConfig->test_pattern = TEST_XTALK_PATTERN;
2424 // DRAMC operation clock frequency in MHz
2425 DramConfig->frequency = 533;
2426 // Switch to ENABLE or DISABLE low frequency write and high frequency read
2427 DramConfig->u2DelayCellTimex100 = 0;
2428
2429 DramConfig->enable_rx_scan_vref =DISABLE_VREF_SCAN;
2430 DramConfig->enable_tx_scan_vref =DISABLE_VREF_SCAN;
2431 //Cervino and Merlot have DLP3, need to give it initial value
2432 DramConfig->bDLP3 = 0;
2433
2434 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //LP3 broadcast off
2435
2436 Global_Option_Init(DramConfig);
2437 Global_Option_Init2(DramConfig);
2438
2439 vDramcInit_PreSettings(DramConfig);
2440
2441 DDRPhyFreqSel(DramConfig, DramConfig->freq_sel);
2442
2443 vSetPHY2ChannelMapping(DramConfig, DramConfig->channel);
2444
2445 #if DV_SIMULATION_SW_IMPED
2446 //TYPE_LPDDR4P, TYPE_LPDDR3
2447 DramcSwImpedanceCal(DramConfig, 1, 0); //without term
2448 //update ODTP/ODTN of term to unterm
2449 DramcUpdateImpedanceTerm2UnTerm(DramConfig);
2450 #endif
2451
2452
2453#if DV_SIMULATION_INIT_C
2454 DramcInit(DramConfig);
2455 #if DV_SIMULATION_MIOCKJMETER
2456 #ifdef ENABLE_MIOCK_JMETER
2457 DramcMiockJmeter(DramConfig);
2458 #endif
2459 #endif
2460#endif
2461
2462#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK
2463 memset(DramConfig->arfgWriteLevelingInitShif, FALSE, sizeof(DramConfig->arfgWriteLevelingInitShif));
2464 //>fgWriteLevelingInitShif= FALSE;
2465#endif
2466#if TX_PERBIT_INIT_FLOW_CONTROL
2467 memset(DramConfig->fgTXPerbifInit, FALSE, sizeof(DramConfig->fgTXPerbifInit));
2468#endif
2469
2470#if DV_SIMULATION_BEFORE_K
2471 vApplyConfigBeforeCalibration(DramConfig);
2472 //vMR2InitForSimulationTest(DramConfig);
2473#endif
2474
2475 vAutoRefreshSwitch(DramConfig, DISABLE);
2476
2477#if DV_SIMULATION_CA_TRAINING
2478 vSetRank(DramConfig, RANK_0);
2479 CATrainingLP3(DramConfig);
2480#endif
2481
2482#if DV_SIMULATION_GATING
2483 DramcRxdqsGatingPreProcess(DramConfig);
2484#endif
2485
2486 for(ii=RANK_0; ii<RANK_MAX; ii++)
2487 {
2488 vSetRank(DramConfig, ii);
2489
2490 vAutoRefreshSwitch(DramConfig, DISABLE);
2491
2492 #if DV_SIMULATION_WRITE_LEVELING
2493 if(ii==RANK_0)
2494 DramcWriteLeveling(DramConfig);
2495 #endif
2496
2497 vAutoRefreshSwitch(DramConfig, ENABLE);
2498
2499
2500 #if DV_SIMULATION_GATING
2501 DramcRxdqsGatingCal(DramConfig);
2502 #endif
2503
2504 #if DV_SIMULATION_DATLAT
2505 // RX Datlat calibration of single rank
2506 DramcRxdatlatCal(DramConfig);
2507 #endif
2508
2509 #if DV_SIMULATION_RX_PERBIT
2510 DramcRxWindowPerbitCal(DramConfig, 1);
2511 #endif
2512
2513 #if DV_SIMULATION_TX_PERBIT
2514 DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, DISABLE_VREF_SCAN);
2515 #endif
2516 }
2517
2518 vSetRank(DramConfig, RANK_0);
2519#if DV_SIMULATION_GATING
2520 DramcRxdqsGatingPostProcess(DramConfig);
2521#endif
2522
2523#if DV_SIMULATION_DATLAT
2524 DramcDualRankRxdatlatCal(DramConfig);
2525#endif
2526
2527#if DV_SIMULATION_AFTER_K
2528 vApplyConfigAfterCalibration(DramConfig);
2529#endif
2530
2531}
2532#endif
2533
2534void DPI_SW_main_LP4(DRAMC_CTX_T *DramConfig)
2535{
2536 int ii;
2537 DRAM_STATUS_T VrefStatus;
2538
2539 U8 gu1BroadcastIsLP4 = TRUE;
2540 DramConfig->support_channel_num = CHANNEL_SINGLE;
2541 DramConfig->channel = CHANNEL_A;
2542 DramConfig->support_rank_num = RANK_DUAL;
2543 // DramRank
2544 DramConfig->rank = RANK_0;
2545 DramConfig->freq_sel = LP4_DDR2400;
2546 DramConfig->shu_type = DRAM_DFS_SHUFFLE_1;
2547 // DRAM type
2548 DramConfig->dram_type = TYPE_LPDDR4X;
2549 // DRAM Fast switch point type, only for LP4, useless in LP3
2550 DramConfig->dram_fsp = FSP_0;
2551 // DRAM CBT mode, only for LP4, useless in LP3
2552 DramConfig->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
2553 //DramConfig->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
2554 DramConfig->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
2555 // IC and DRAM read DBI
2556 DramConfig->DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2557 DramConfig->DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2558 #if ENABLE_READ_DBI
2559 DramConfig->DBI_R_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3
2560 #else
2561 DramConfig->DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2562 #endif
2563 // IC and DRAM write DBI
2564 DramConfig->DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3
2565 DramConfig->DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2566 #if ENABLE_WRITE_DBI
2567 DramConfig->DBI_W_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3
2568 #else
2569 DramConfig->DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3
2570 #endif
2571 // bus width
2572 DramConfig->data_width = DATA_WIDTH_16BIT;
2573 // DRAMC internal test engine-2 parameters in calibration
2574 DramConfig->test2_1 = DEFAULT_TEST2_1_CAL;
2575 DramConfig->test2_2 = DEFAULT_TEST2_2_CAL;
2576 // DRAMC test pattern in calibration
2577 DramConfig->test_pattern = TEST_XTALK_PATTERN;
2578 // DRAMC operation clock frequency in MHz
2579 DramConfig->frequency = 1200;
2580 // u2DelayCellTimex100
2581 DramConfig->u2DelayCellTimex100 = 0;
2582 DramConfig->vendor_id = 0x1;
2583 DramConfig->density = 0;
2584 //DramConfig->ranksize = {0,0};
2585
2586 DramConfig->enable_cbt_scan_vref = DISABLE_VREF_SCAN;
2587 DramConfig->enable_rx_scan_vref = DISABLE_VREF_SCAN;
2588 DramConfig->enable_tx_scan_vref = DISABLE_VREF_SCAN;
2589
2590 DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on
2591
2592 Global_Option_Init(DramConfig);
2593 Global_Option_Init2(DramConfig);
2594
2595 vDramcInit_PreSettings(DramConfig);
2596
2597 DDRPhyFreqSel(DramConfig, DramConfig->freq_sel);
2598
2599 vSetPHY2ChannelMapping(DramConfig, DramConfig->channel);
2600
2601#if DV_SIMULATION_SW_IMPED
2602 if (DramConfig->dram_type == TYPE_LPDDR4X)
2603 {
2604 DramcSwImpedanceCal(DramConfig,1, 0); //without term
2605 }
2606 DramcSwImpedanceCal(DramConfig,1, 1); //within term
2607 //update ODTP/ODTN of term to unterm
2608 DramcUpdateImpedanceTerm2UnTerm(DramConfig);
2609#endif
2610
2611
2612#if DV_SIMULATION_INIT_C
2613 DramcInit(DramConfig);
2614 vSetPHY2ChannelMapping(DramConfig, u1ChannelSet[0]);
2615 #if DV_SIMULATION_MIOCKJMETER
2616 #ifdef ENABLE_MIOCK_JMETER
2617 DramcMiockJmeter(DramConfig);
2618 #endif
2619 #endif
2620 #if ENABLE_RX_TRACKING_LP4
2621 DramcRxInputDelayTrackingInit_byFreq(DramConfig);
2622 DramcRxInputDelayTrackingInit_Common(DramConfig);
2623 DramcRxInputDelayTrackingHW(DramConfig);
2624 #endif
2625#endif
2626
2627
2628#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK
2629 memset(DramConfig->arfgWriteLevelingInitShif, FALSE, sizeof(DramConfig->arfgWriteLevelingInitShif));
2630 //>fgWriteLevelingInitShif= FALSE;
2631#endif
2632#if TX_PERBIT_INIT_FLOW_CONTROL
2633 memset(DramConfig->fgTXPerbifInit, FALSE, sizeof(DramConfig->fgTXPerbifInit));
2634#endif
2635
2636#if DV_SIMULATION_BEFORE_K
2637 vApplyConfigBeforeCalibration(DramConfig);
2638 //vMR2InitForSimulationTest(DramConfig);
2639#endif
2640
2641#if DV_SIMULATION_GATING
2642DramcRxdqsGatingPreProcess(DramConfig);
2643#endif
2644
2645#if 0//DV_SIMULATION_LP4_ZQ
2646 DramcZQCalibration(DramConfig);
2647#endif
2648
2649#if 0//DV_SIMULATION_CA_TRAINING
2650 vSetRank(DramConfig, RANK_0);
2651 CmdBusTrainingLP4(DramConfig);
2652#endif
2653
2654 vAutoRefreshSwitch(DramConfig, DISABLE);
2655
2656 #if DV_SIMULATION_CA_TRAINING
2657 for(ii=RANK_0; ii<RANK_MAX; ii++)
2658 {
2659 vSetRank(DramConfig, ii);
2660 CmdBusTrainingLP4(DramConfig);
2661
2662
2663 }
2664 vSetRank(DramConfig, RANK_0);
2665
2666 #if DUAL_FREQ_K
2667 No_Parking_On_CLRPLL(DramConfig);
2668 #endif
2669 #endif
2670
2671 for(ii=RANK_0; ii<RANK_MAX; ii++)
2672 {
2673 vSetRank(DramConfig, ii);
2674
2675 #if DV_SIMULATION_WRITE_LEVELING
2676 //if (ii==RANK_1)
2677 DramcWriteLeveling(DramConfig);
2678 #endif
2679
2680 vAutoRefreshSwitch(DramConfig, ENABLE);
2681
2682 #if DV_SIMULATION_GATING
2683 // Gating calibration of single rank
2684 DramcRxdqsGatingCal(DramConfig);
2685 #endif
2686
2687 #if DV_SIMULATION_RX_PERBIT
2688 DramcRxWindowPerbitCal(DramConfig, 0);
2689 #endif
2690
2691 #if DV_SIMULATION_TX_PERBIT
2692 DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, DISABLE_VREF_SCAN);
2693 VrefStatus = DramcTxWindowPerbitCal((DRAMC_CTX_T *) DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,DramConfig->enable_tx_scan_vref);
2694 #endif
2695
2696 #if DV_SIMULATION_DATLAT
2697 // RX Datlat calibration of single rank
2698 DramcRxdatlatCal(DramConfig);
2699 #endif
2700
2701 #if DV_SIMULATION_RX_PERBIT
2702 DramcRxWindowPerbitCal(DramConfig, 1);
2703 #endif
2704
2705 #if 0//DV_SIMULATION_TX_PERBIT
2706 DramcTxOECalibration(DramConfig);
2707 #endif
2708
2709 #if DV_SIMULATION_DBI_ON
2710 #if ENABLE_READ_DBI
2711 //Read DBI ON
2712 SetDramModeRegForReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]);
2713 #endif
2714
2715 #if ENABLE_WRITE_DBI
2716 //Write DBI ON
2717 DramcWriteMinus1MCKForWriteDBI(DramConfig, -8); //Tx DQ/DQM -1 MCK for write DBI ON
2718 SetDramModeRegForWriteDBIOnOff(DramConfig, DramConfig->DBI_W_onoff[DramConfig->dram_fsp]);
2719 #endif
2720 #endif
2721 }
2722
2723 vSetRank(DramConfig, RANK_0);
2724#if DV_SIMULATION_GATING
2725 DramcRxdqsGatingPostProcess(DramConfig);
2726#endif
2727
2728#if DV_SIMULATION_DATLAT
2729 DramcDualRankRxdatlatCal(DramConfig);
2730#endif
2731
2732#if DV_SIMULATION_AFTER_K
2733 vApplyConfigAfterCalibration(DramConfig);
2734#endif
2735
2736 #if DV_SIMULATION_DBI_ON
2737 #if ENABLE_READ_DBI
2738 DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]);
2739 #endif
2740
2741 #if ENABLE_WRITE_DBI
2742 DramcWriteDBIOnOff(DramConfig, DramConfig->DBI_W_onoff[DramConfig->dram_fsp]);
2743 #endif
2744 #endif
2745
2746#if DV_SIMULATION_RUN_TIME_MRW
2747 enter_pasr_dpd_config(0, 0xFF);
2748#endif
2749
2750#if DV_SIMULATION_RUNTIME_CONFIG
2751 DramcRunTimeConfig(DramConfig);
2752#endif
2753
2754}
2755
2756#endif
2757
2758