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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / dramk_2731 / emi.c
blob: f26302613f5fedd6b9c414196f128b162809f87c [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1//=============================================================================
2// Include Files
3//=============================================================================
4#include <dramc_common.h>
5
6#if !__FLASH_TOOL_DA__ && (FOR_DV_SIMULATION_USED==0)
7 #include <emi_hw.h>
8#endif
9
10#if defined(DEF_LAST_DRAMC)
11#include <platform/plat_dbg_info.h>
12#endif
13
14#include <emi.h>
15
16#if !__FLASH_TOOL_DA__ && !__ETT__
17#include <custom_emi.h>
18#endif
19
20#if __ETT__
21#include "ett_common.h"
22#include "emi.h"
23#endif
24
25#if CFG_BOOT_ARGUMENT
26#define bootarg g_dram_buf->bootarg
27#endif
28
29#if (FOR_DV_SIMULATION_USED==0)
30#if __ETT__
31#include <pmic.h>
32#else
33#include <platform/pmic.h>
34#include <platform/mtk_drm.h>
35#endif
36//#include <rt5738.h>
37/* now we can use definition MTK_PMIC_CHIP_MT6356 */
38#if __ETT__
39//#undef MTK_PMIC_CHIP_MT6356
40#undef MTK_PMIC_CHIP_RT5738 //sagy
41#else
42
43#ifdef PMIC_CHIP_MT6356
44#define MTK_PMIC_CHIP_MT6356
45#define MTK_PMIC_CHIP_RT5738
46#endif
47
48#ifdef PMIC_CHIP_MT6389
49#define MTK_PMIC_CHIP_MT6389
50#endif
51
52#endif
53#endif
54
55#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
56#if __ETT__
57#include <regulator/mtk_regulator.h>
58#else
59#include <platform/regulator/mtk_regulator.h>
60#endif
61#endif
62
63#ifdef MTK_PMIC_CHIP_RT5738
64#if !__ETT__
65#include <platform/rt5738.h>
66#endif
67#endif
68
69#if !__ETT__
70#define CQ_DMA_BASE (IO_PHYS+0x212000)
71#endif
72
73//=============================================================================
74// Definition
75//=============================================================================
76static unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
77
78//=============================================================================
79// Global Variables
80//=============================================================================
81#ifdef DRAM_ADAPTIVE
82static unsigned char auto_detect_done;
83#endif
84int emi_setting_index = -1;
85static unsigned int mr5;
86static unsigned int rank_swap;
87extern DRAMC_CTX_T *psCurrDramCtx;
88#ifdef DRAM_ADAPTIVE
89extern EMI_SETTINGS g_default_emi_setting;
90#else
91extern EMI_SETTINGS default_emi_setting;
92#endif
93#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
94static struct mtk_regulator reg_vdram, reg_vcore, reg_vddq;
95#endif
96
97#ifdef LAST_DRAMC
98static LAST_DRAMC_INFO_T* last_dramc_info_ptr;
99#endif
100
101#ifdef LAST_EMI
102static LAST_EMI_INFO_T* last_emi_info_ptr;
103#endif
104
105#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
106extern u64 get_part_addr(const char *name);
107static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
108static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
109#if !__ETT__ && (FOR_DV_SIMULATION_USED == 0)
110static u64 part_dram_data_addr = 0;
111static unsigned int dram_offline_data_flags = 0;
112#endif
113#endif
114//=============================================================================
115// External references
116//=============================================================================
117extern DRAMC_CTX_T *psCurrDramCtx;
118extern char* opt_dle_value;
119
120void print_DBG_info(DRAMC_CTX_T *p);
121void Dump_EMIRegisters(DRAMC_CTX_T *p);
122
123#define EMI_APB_BASE ((volatile void *)EMI_BASE)
124#define EMI_CHANNEL_APB_BASE ((volatile void *)CHN0_EMI_BASE)
125#define INFRA_DRAMC_REG_CONFIG ((volatile void *)0x100010b4)
126
127#define CHN_EMI_CONA(base) ((volatile unsigned int *)(base + 0x000))
128#define CHN_EMI_CONC(base) ((volatile unsigned int *)(base + 0x010))
129
130unsigned int mt_get_dram_type_from_hw_trap(void);
131
132static void emi_cen_config_lp4(unsigned long cfg_base_addr)
133{
134 #ifdef RANK_512MB // => 1channel , one rank , total= 512MB
135 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103016);
136 #else //RANK_1G => 1channel , one rank , total= 1GB
137 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103014);
138 #endif
139 mt_reg_sync_write(EMI_APB_BASE+0x00000004,0x0e290e28); //800 (1:4) r12 - r9 overhead
140 mt_reg_sync_write(EMI_APB_BASE+0x00000008,0x091e1322); //800 (1:4) r4 - r1 overhead
141 mt_reg_sync_write(EMI_APB_BASE+0x0000000c,0x0f29112a); //800 (1:4) r16 - r13 overhead
142 mt_reg_sync_write(EMI_APB_BASE+0x00000010,0x0c240a1f); //800 (1:4) r8 - r5 overhead
143 mt_reg_sync_write(EMI_APB_BASE+0x000008b0,0x071b1222); //1200 (1:4) r4 - r1 overhead
144 mt_reg_sync_write(EMI_APB_BASE+0x000008b4,0x0a21091e); //1200 (1:4) r8 - r5 overhead
145 mt_reg_sync_write(EMI_APB_BASE+0x0000001c,0x0e250c23); //1200 (1:4) r12 - r9 overhead
146 mt_reg_sync_write(EMI_APB_BASE+0x00000024,0x11291127); //1200 (1:4) r16 - r13 overhead
147 mt_reg_sync_write(EMI_APB_BASE+0x00000034,0x081c1423); //1600 (1:4) r4 - r1 overhead
148 mt_reg_sync_write(EMI_APB_BASE+0x0000006c,0x0a21091d); //1600 (1:4) r8 - r5 overhead
149 mt_reg_sync_write(EMI_APB_BASE+0x0000013c,0x0e260d24); //1600 (1:4) r12 - r9 overhead
150 mt_reg_sync_write(EMI_APB_BASE+0x00000640,0x12291128); //1600 (1:4) r16 - r13 overhead
151 mt_reg_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1600 (1:8) r4 - r1 overhead
152 mt_reg_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1600 (1:8) r8 - r5 overhead
153 mt_reg_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1600 (1:8) r12 - r9 overhead
154 mt_reg_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1600 (1:8) r16 - r13 overhead
155 mt_reg_sync_write(EMI_APB_BASE+0x0000004c,0x1024202c); //2400 (1:8) r4 - r1 overhead
156 mt_reg_sync_write(EMI_APB_BASE+0x00000084,0x0b210c21); //2400 (1:8) r8 - r5 overhead
157 mt_reg_sync_write(EMI_APB_BASE+0x000001e4,0x0f250d23); //2400 (1:8) r12 - r9 overhead
158 mt_reg_sync_write(EMI_APB_BASE+0x00000648,0x152b1228); //2400 (1:8) r16 - r13 overhead
159 mt_reg_sync_write(EMI_APB_BASE+0x00000054,0x182e2d33); //3200 (1:8) r4 - r1 overhead
160 mt_reg_sync_write(EMI_APB_BASE+0x0000008c,0x0f251025); //3200 (1:8) r8 - r5 overhead
161 mt_reg_sync_write(EMI_APB_BASE+0x000001e8,0x122a1027); //3200 (1:8) r12 - r9 overhead
162 mt_reg_sync_write(EMI_APB_BASE+0x0000064c,0x1a31162d); //3200 (1:8) r16 - r13 overhead
163 mt_reg_sync_write(EMI_APB_BASE+0x0000005c,0x182e2d33); //3733 (1:8) r4 - r1 overhead
164 mt_reg_sync_write(EMI_APB_BASE+0x00000094,0x0f251025); //3733 (1:8) r8 - r5 overhead
165 mt_reg_sync_write(EMI_APB_BASE+0x000001c8,0x122a1027); //3733 (1:8) r12 - r9 overhead
166 mt_reg_sync_write(EMI_APB_BASE+0x00000660,0x1a31162d); //3733 (1:8) r16 - r13 overhead
167 mt_reg_sync_write(EMI_APB_BASE+0x00000064,0x182e2d33); //4266 (1:8) r4 - r1 overhead
168 mt_reg_sync_write(EMI_APB_BASE+0x0000009c,0x0f251025); //4266 (1:8) r8 - r5 overhead
169 mt_reg_sync_write(EMI_APB_BASE+0x000001f4,0x122a1027); //4266 (1:8) r12 - r9 overhead
170 mt_reg_sync_write(EMI_APB_BASE+0x00000664,0x1a31162d); //4266 (1:8) r16 - r13 overhead
171
172 mt_reg_sync_write(EMI_APB_BASE+0x00000030,0x37333034); //800 (1:4) r8 - r2 non-align overhead
173 mt_reg_sync_write(EMI_APB_BASE+0x00000014,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
174 mt_reg_sync_write(EMI_APB_BASE+0x000008b8,0x33313035); //1200 (1:4) r8 - r2 non-align overhead
175 mt_reg_sync_write(EMI_APB_BASE+0x0000002c,0x38383735); //1200 (1:4) r16 - r10 non-align overhead
176 mt_reg_sync_write(EMI_APB_BASE+0x000000c4,0x34322e33); //1600 (1:4) r8 - r2 non-align overhead
177 mt_reg_sync_write(EMI_APB_BASE+0x00000668,0x38383735); //1600 (1:4) r16 - r10 non-align overhead
178 mt_reg_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
179 mt_reg_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
180 mt_reg_sync_write(EMI_APB_BASE+0x000000cc,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
181 mt_reg_sync_write(EMI_APB_BASE+0x00000694,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
182 mt_reg_sync_write(EMI_APB_BASE+0x000000e4,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
183 mt_reg_sync_write(EMI_APB_BASE+0x00000708,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
184 mt_reg_sync_write(EMI_APB_BASE+0x000000f4,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead
185 mt_reg_sync_write(EMI_APB_BASE+0x0000070c,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead
186 mt_reg_sync_write(EMI_APB_BASE+0x0000012c,0x37373a57); //4266 (1:8) r8 - r2 non-align overhead
187 mt_reg_sync_write(EMI_APB_BASE+0x00000748,0x3f3f3c39); //4266 (1:8) r16 - r10 non-align overhead
188
189 mt_reg_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
190 mt_reg_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
191 mt_reg_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
192 mt_reg_sync_write(EMI_APB_BASE+0x00000038,0x88220003);
193 mt_reg_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
194 mt_reg_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
195 mt_reg_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
196 mt_reg_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
197 mt_reg_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
198 mt_reg_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
199 mt_reg_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
200 mt_reg_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
201 mt_reg_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
202 mt_reg_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
203 mt_reg_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
204 mt_reg_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
205 mt_reg_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
206 mt_reg_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
207 mt_reg_sync_write(EMI_APB_BASE+0x000000f0,0x384a0034);
208 mt_reg_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
209#ifdef SCN_ICFP
210 mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
211 mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
212 mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
213 mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
214 mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
215 mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
216 mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
217 mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
218#else //SCN_UI
219 mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107250);
220 mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107050);
221 mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
222 mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
223 mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x30306050); // [31:24]: MDHW {w,r} age
224 mt_reg_sync_write(EMI_APB_BASE+0x00000124,0x00000034);
225 mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
226 mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837048);
227 mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837048);
228#endif
229 mt_reg_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
230 mt_reg_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
231 mt_reg_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
232 mt_reg_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
233 mt_reg_sync_write(EMI_APB_BASE+0x00000400,0x00ff0000); //[27:20] enable monitor
234 mt_reg_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
235 mt_reg_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
236 mt_reg_sync_write(EMI_APB_BASE+0x00000808,0x0a0a0a0a);
237 mt_reg_sync_write(EMI_APB_BASE+0x0000080c,0x0a0a0a0a);
238 mt_reg_sync_write(EMI_APB_BASE+0x00000820,0x24240000); //wostd throttle
239 mt_reg_sync_write(EMI_APB_BASE+0x00000824,0x00002424); //wostd throttle
240 mt_reg_sync_write(EMI_APB_BASE+0x00000828,0x50500000); //rostd throttle
241 mt_reg_sync_write(EMI_APB_BASE+0x0000082c,0x00005050); //rostd throttle
242 mt_reg_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a70);
243 mt_reg_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
244 mt_reg_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
245 mt_reg_sync_write(EMI_APB_BASE+0x0000083c,0x3c785a3c);
246 mt_reg_sync_write(EMI_APB_BASE+0x00000840,0x00000000);
247 mt_reg_sync_write(EMI_APB_BASE+0x00000844,0x00000000);
248 mt_reg_sync_write(EMI_APB_BASE+0x00000848,0x00000000);
249 mt_reg_sync_write(EMI_APB_BASE+0x0000084c,0x00000000);
250 mt_reg_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
251 mt_reg_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
252 mt_reg_sync_write(EMI_APB_BASE+0x00000858,0x02533c15);
253 mt_reg_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
254 mt_reg_sync_write(EMI_APB_BASE+0x00000874,0x00002328);
255 mt_reg_sync_write(EMI_APB_BASE+0x00000878,0x005a0000);
256 mt_reg_sync_write(EMI_APB_BASE+0x0000087c,0x0250250f);
257 mt_reg_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
258 mt_reg_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
259 mt_reg_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
260 mt_reg_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
261 mt_reg_sync_write(EMI_APB_BASE+0x000008c0,0x00002ee0);
262 mt_reg_sync_write(EMI_APB_BASE+0x000008c4,0x00780000);
263 mt_reg_sync_write(EMI_APB_BASE+0x000008c8,0x000036b0);
264 mt_reg_sync_write(EMI_APB_BASE+0x000008cc,0x008c0000);
265 mt_reg_sync_write(EMI_APB_BASE+0x000008d0,0x00003e80);
266 mt_reg_sync_write(EMI_APB_BASE+0x000008d4,0x00a00000);
267 mt_reg_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
268 mt_reg_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
269 mt_reg_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
270 mt_reg_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
271 mt_reg_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
272 mt_reg_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
273 mt_reg_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
274 mt_reg_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
275 mt_reg_sync_write(EMI_APB_BASE+0x000009f0,0x32644b32);
276 mt_reg_sync_write(EMI_APB_BASE+0x000009f4,0x8574644b);
277 mt_reg_sync_write(EMI_APB_BASE+0x000009f8,0x00001770);
278 mt_reg_sync_write(EMI_APB_BASE+0x000009fc,0x00002328);
279 mt_reg_sync_write(EMI_APB_BASE+0x00000b00,0x00002ee0);
280 mt_reg_sync_write(EMI_APB_BASE+0x00000b04,0x00001770);
281 mt_reg_sync_write(EMI_APB_BASE+0x00000b08,0x00002328);
282 mt_reg_sync_write(EMI_APB_BASE+0x00000b0c,0x00002ee0);
283 mt_reg_sync_write(EMI_APB_BASE+0x00000b10,0x000036b0);
284 mt_reg_sync_write(EMI_APB_BASE+0x00000b14,0x00003e80);
285 mt_reg_sync_write(EMI_APB_BASE+0x00000b28,0x1e3c2d1e);
286 mt_reg_sync_write(EMI_APB_BASE+0x00000b2c,0x4b463c2d);
287
288 mt_reg_sync_write(EMI_APB_BASE+0x00000b60,0x14281e14);
289 mt_reg_sync_write(EMI_APB_BASE+0x00000b64,0x352e281e);
290 mt_reg_sync_write(EMI_APB_BASE+0x00000b98,0x64c89664);
291 mt_reg_sync_write(EMI_APB_BASE+0x00000b9c,0xffe9c896);
292 mt_reg_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
293 mt_reg_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
294 mt_reg_sync_write(EMI_APB_BASE+0x00000c08,0x64c89664);
295 mt_reg_sync_write(EMI_APB_BASE+0x00000c0c,0xffe9c896);
296 mt_reg_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
297 mt_reg_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
298 mt_reg_sync_write(EMI_APB_BASE+0x00000c4c,0x00000025);
299 mt_reg_sync_write(EMI_APB_BASE+0x00000c80,0x00003e80);
300 mt_reg_sync_write(EMI_APB_BASE+0x00000c84,0x00005dc0);
301 mt_reg_sync_write(EMI_APB_BASE+0x00000c88,0x00007d00);
302 mt_reg_sync_write(EMI_APB_BASE+0x00000c8c,0x00003e80);
303 mt_reg_sync_write(EMI_APB_BASE+0x00000c90,0x00005dc0);
304 mt_reg_sync_write(EMI_APB_BASE+0x00000c94,0x00007d00);
305 mt_reg_sync_write(EMI_APB_BASE+0x00000c98,0x000091d5);
306 mt_reg_sync_write(EMI_APB_BASE+0x00000c9c,0x0000a6aa);
307 mt_reg_sync_write(EMI_APB_BASE+0x00000cb0,0x50a07850);
308 mt_reg_sync_write(EMI_APB_BASE+0x00000cb4,0xd5baa078);
309 mt_reg_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
310 mt_reg_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
311
312 mt_reg_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
313 mt_reg_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
314 mt_reg_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
315 mt_reg_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
316 mt_reg_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
317 mt_reg_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
318 mt_reg_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
319 mt_reg_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
320 mt_reg_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
321 mt_reg_sync_write(EMI_APB_BASE+0x00000d3c,0x00000100); //APR shf1 event selet
322 mt_reg_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
323 mt_reg_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
324 mt_reg_sync_write(EMI_APB_BASE+0x00000d50,0x00001000); //APW shf1 event selet
325// mt_reg_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
326// mt_reg_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
327// mt_reg_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
328// mt_reg_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
329// mt_reg_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
330// mt_reg_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
331// mt_reg_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
332// mt_reg_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
333// mt_reg_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
334// mt_reg_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
335// mt_reg_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
336// mt_reg_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
337// mt_reg_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
338// mt_reg_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
339 mt_reg_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
340 mt_reg_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
341 mt_reg_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
342 mt_reg_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
343 mt_reg_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
344// mt_reg_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
345// mt_reg_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
346// mt_reg_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
347// mt_reg_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
348// mt_reg_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
349 mt_reg_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
350 mt_reg_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
351 mt_reg_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
352 mt_reg_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
353 mt_reg_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
354 mt_reg_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
355 mt_reg_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
356 mt_reg_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
357 mt_reg_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
358 mt_reg_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
359 mt_reg_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
360 mt_reg_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
361 mt_reg_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
362 mt_reg_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
363 mt_reg_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
364 mt_reg_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
365}
366
367static void emi_cen_config_lp2(unsigned long cfg_base_addr)
368{
369#ifndef ONE_CH
370 #ifdef RANK_512MB // => 1channel , one rank , total= 512MB
371 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0x30103016);
372 #else //RANK_1G => 2channel , dual rank , total=4G
373 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
374 #endif
375#else
376 #ifdef RANK_512MB
377 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xa053a054);
378 #else
379 mt_reg_sync_write(EMI_APB_BASE+0x00000000,0xf053f054);
380 #endif
381#endif
382 mt_reg_sync_write(EMI_APB_BASE+0x00000004,0x0e290e28); //800 (1:4) r12 - r9 overhead
383 mt_reg_sync_write(EMI_APB_BASE+0x00000008,0x091e1322); //800 (1:4) r4 - r1 overhead
384 mt_reg_sync_write(EMI_APB_BASE+0x0000000c,0x0f29112a); //800 (1:4) r16 - r13 overhead
385 mt_reg_sync_write(EMI_APB_BASE+0x00000010,0x0c240a1f); //800 (1:4) r8 - r5 overhead
386 mt_reg_sync_write(EMI_APB_BASE+0x000008b0,0x071b1222); //1200 (1:4) r4 - r1 overhead
387 mt_reg_sync_write(EMI_APB_BASE+0x000008b4,0x0a21091e); //1200 (1:4) r8 - r5 overhead
388 mt_reg_sync_write(EMI_APB_BASE+0x0000001c,0x0e250c23); //1200 (1:4) r12 - r9 overhead
389 mt_reg_sync_write(EMI_APB_BASE+0x00000024,0x11291127); //1200 (1:4) r16 - r13 overhead
390 mt_reg_sync_write(EMI_APB_BASE+0x00000034,0x081c1423); //1600 (1:4) r4 - r1 overhead
391 mt_reg_sync_write(EMI_APB_BASE+0x0000006c,0x0a21091d); //1600 (1:4) r8 - r5 overhead
392 mt_reg_sync_write(EMI_APB_BASE+0x0000013c,0x0e260d24); //1600 (1:4) r12 - r9 overhead
393 mt_reg_sync_write(EMI_APB_BASE+0x00000640,0x12291128); //1600 (1:4) r16 - r13 overhead
394 mt_reg_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1600 (1:8) r4 - r1 overhead
395 mt_reg_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1600 (1:8) r8 - r5 overhead
396 mt_reg_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1600 (1:8) r12 - r9 overhead
397 mt_reg_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1600 (1:8) r16 - r13 overhead
398 mt_reg_sync_write(EMI_APB_BASE+0x0000004c,0x1024202c); //2400 (1:8) r4 - r1 overhead
399 mt_reg_sync_write(EMI_APB_BASE+0x00000084,0x0b210c21); //2400 (1:8) r8 - r5 overhead
400 mt_reg_sync_write(EMI_APB_BASE+0x000001e4,0x0f250d23); //2400 (1:8) r12 - r9 overhead
401 mt_reg_sync_write(EMI_APB_BASE+0x00000648,0x152b1228); //2400 (1:8) r16 - r13 overhead
402 mt_reg_sync_write(EMI_APB_BASE+0x00000054,0x182e2d33); //3200 (1:8) r4 - r1 overhead
403 mt_reg_sync_write(EMI_APB_BASE+0x0000008c,0x0f251025); //3200 (1:8) r8 - r5 overhead
404 mt_reg_sync_write(EMI_APB_BASE+0x000001e8,0x122a1027); //3200 (1:8) r12 - r9 overhead
405 mt_reg_sync_write(EMI_APB_BASE+0x0000064c,0x1a31162d); //3200 (1:8) r16 - r13 overhead
406 mt_reg_sync_write(EMI_APB_BASE+0x0000005c,0x182e2d33); //3733 (1:8) r4 - r1 overhead
407 mt_reg_sync_write(EMI_APB_BASE+0x00000094,0x0f251025); //3733 (1:8) r8 - r5 overhead
408 mt_reg_sync_write(EMI_APB_BASE+0x000001c8,0x122a1027); //3733 (1:8) r12 - r9 overhead
409 mt_reg_sync_write(EMI_APB_BASE+0x00000660,0x1a31162d); //3733 (1:8) r16 - r13 overhead
410 mt_reg_sync_write(EMI_APB_BASE+0x00000064,0x182e2d33); //4266 (1:8) r4 - r1 overhead
411 mt_reg_sync_write(EMI_APB_BASE+0x0000009c,0x0f251025); //4266 (1:8) r8 - r5 overhead
412 mt_reg_sync_write(EMI_APB_BASE+0x000001f4,0x122a1027); //4266 (1:8) r12 - r9 overhead
413 mt_reg_sync_write(EMI_APB_BASE+0x00000664,0x1a31162d); //4266 (1:8) r16 - r13 overhead
414
415 mt_reg_sync_write(EMI_APB_BASE+0x00000030,0x37333034); //800 (1:4) r8 - r2 non-align overhead
416 mt_reg_sync_write(EMI_APB_BASE+0x00000014,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
417 mt_reg_sync_write(EMI_APB_BASE+0x000008b8,0x33313035); //1200 (1:4) r8 - r2 non-align overhead
418 mt_reg_sync_write(EMI_APB_BASE+0x0000002c,0x38383735); //1200 (1:4) r16 - r10 non-align overhead
419 mt_reg_sync_write(EMI_APB_BASE+0x000000c4,0x34322e33); //1600 (1:4) r8 - r2 non-align overhead
420 mt_reg_sync_write(EMI_APB_BASE+0x00000668,0x38383735); //1600 (1:4) r16 - r10 non-align overhead
421 mt_reg_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
422 mt_reg_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
423 mt_reg_sync_write(EMI_APB_BASE+0x000000cc,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
424 mt_reg_sync_write(EMI_APB_BASE+0x00000694,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
425 mt_reg_sync_write(EMI_APB_BASE+0x000000e4,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
426 mt_reg_sync_write(EMI_APB_BASE+0x00000708,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
427 mt_reg_sync_write(EMI_APB_BASE+0x000000f4,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead
428 mt_reg_sync_write(EMI_APB_BASE+0x0000070c,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead
429 mt_reg_sync_write(EMI_APB_BASE+0x0000012c,0x37373a57); //4266 (1:8) r8 - r2 non-align overhead
430 mt_reg_sync_write(EMI_APB_BASE+0x00000748,0x3f3f3c39); //4266 (1:8) r16 - r10 non-align overhead
431
432 mt_reg_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
433 mt_reg_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
434 mt_reg_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
435 mt_reg_sync_write(EMI_APB_BASE+0x00000038,0x88220003);
436 mt_reg_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
437 mt_reg_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
438 mt_reg_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
439 mt_reg_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
440 mt_reg_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
441 mt_reg_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
442 mt_reg_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
443 mt_reg_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
444 mt_reg_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
445 mt_reg_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
446 mt_reg_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
447 mt_reg_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
448 mt_reg_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
449 mt_reg_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
450 mt_reg_sync_write(EMI_APB_BASE+0x000000f0,0x384a0034);
451 mt_reg_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
452#ifdef SCN_ICFP
453 mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
454 mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
455 mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
456 mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
457 mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
458 mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
459 mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
460 mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
461#else //SCN_UI
462 mt_reg_sync_write(EMI_APB_BASE+0x00000100,0x20107250);
463 mt_reg_sync_write(EMI_APB_BASE+0x00000108,0x10107050);
464 mt_reg_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
465 mt_reg_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
466 mt_reg_sync_write(EMI_APB_BASE+0x00000120,0x10106050);
467 mt_reg_sync_write(EMI_APB_BASE+0x00000124,0x00000034);
468 mt_reg_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
469 mt_reg_sync_write(EMI_APB_BASE+0x00000130,0x83837048);
470 mt_reg_sync_write(EMI_APB_BASE+0x00000138,0x83837048);
471#endif
472 mt_reg_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
473 mt_reg_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
474 mt_reg_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
475 mt_reg_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
476 mt_reg_sync_write(EMI_APB_BASE+0x00000400,0x00ff0000); //[27:20] enable monitor
477 mt_reg_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
478 mt_reg_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
479 mt_reg_sync_write(EMI_APB_BASE+0x00000808,0x0a0a0a0a);
480 mt_reg_sync_write(EMI_APB_BASE+0x0000080c,0x0a0a0a0a);
481 mt_reg_sync_write(EMI_APB_BASE+0x00000820,0x24240101); //wostd throttle
482 mt_reg_sync_write(EMI_APB_BASE+0x00000824,0x01012424); //wostd throttle
483 mt_reg_sync_write(EMI_APB_BASE+0x00000828,0x50500101); //rostd throttle
484 mt_reg_sync_write(EMI_APB_BASE+0x0000082c,0x01015050); //rostd throttle
485 mt_reg_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a70);
486 mt_reg_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
487 mt_reg_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
488 mt_reg_sync_write(EMI_APB_BASE+0x0000083c,0x3c785a3c);
489 mt_reg_sync_write(EMI_APB_BASE+0x00000840,0x00000000);
490 mt_reg_sync_write(EMI_APB_BASE+0x00000844,0x00000000);
491 mt_reg_sync_write(EMI_APB_BASE+0x00000848,0x00000000);
492 mt_reg_sync_write(EMI_APB_BASE+0x0000084c,0x00000000);
493 mt_reg_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
494 mt_reg_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
495 mt_reg_sync_write(EMI_APB_BASE+0x00000858,0x02533c15);
496 mt_reg_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
497 mt_reg_sync_write(EMI_APB_BASE+0x00000874,0x00002328);
498 mt_reg_sync_write(EMI_APB_BASE+0x00000878,0x005a0000);
499 mt_reg_sync_write(EMI_APB_BASE+0x0000087c,0x0250250f);
500 mt_reg_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
501 mt_reg_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
502 mt_reg_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
503 mt_reg_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
504 mt_reg_sync_write(EMI_APB_BASE+0x000008c0,0x00002ee0);
505 mt_reg_sync_write(EMI_APB_BASE+0x000008c4,0x00780000);
506 mt_reg_sync_write(EMI_APB_BASE+0x000008c8,0x000036b0);
507 mt_reg_sync_write(EMI_APB_BASE+0x000008cc,0x008c0000);
508 mt_reg_sync_write(EMI_APB_BASE+0x000008d0,0x00003e80);
509 mt_reg_sync_write(EMI_APB_BASE+0x000008d4,0x00a00000);
510 mt_reg_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
511 mt_reg_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
512 mt_reg_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
513 mt_reg_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
514 mt_reg_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
515 mt_reg_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
516 mt_reg_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
517 mt_reg_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
518 mt_reg_sync_write(EMI_APB_BASE+0x000009f0,0x32644b32);
519 mt_reg_sync_write(EMI_APB_BASE+0x000009f4,0x8574644b);
520 mt_reg_sync_write(EMI_APB_BASE+0x000009f8,0x00001770);
521 mt_reg_sync_write(EMI_APB_BASE+0x000009fc,0x00002328);
522 mt_reg_sync_write(EMI_APB_BASE+0x00000b00,0x00002ee0);
523 mt_reg_sync_write(EMI_APB_BASE+0x00000b04,0x00001770);
524 mt_reg_sync_write(EMI_APB_BASE+0x00000b08,0x00002328);
525 mt_reg_sync_write(EMI_APB_BASE+0x00000b0c,0x00002ee0);
526 mt_reg_sync_write(EMI_APB_BASE+0x00000b10,0x000036b0);
527 mt_reg_sync_write(EMI_APB_BASE+0x00000b14,0x00003e80);
528 mt_reg_sync_write(EMI_APB_BASE+0x00000b28,0x1e3c2d1e);
529 mt_reg_sync_write(EMI_APB_BASE+0x00000b2c,0x4b463c2d);
530
531 mt_reg_sync_write(EMI_APB_BASE+0x00000b60,0x14281e14);
532 mt_reg_sync_write(EMI_APB_BASE+0x00000b64,0x352e281e);
533 mt_reg_sync_write(EMI_APB_BASE+0x00000b98,0x64c89664);
534 mt_reg_sync_write(EMI_APB_BASE+0x00000b9c,0xffe9c896);
535 mt_reg_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
536 mt_reg_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
537 mt_reg_sync_write(EMI_APB_BASE+0x00000c08,0x64c89664);
538 mt_reg_sync_write(EMI_APB_BASE+0x00000c0c,0xffe9c896);
539 mt_reg_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
540 mt_reg_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
541 mt_reg_sync_write(EMI_APB_BASE+0x00000c4c,0x00000025);
542 mt_reg_sync_write(EMI_APB_BASE+0x00000c80,0x00003e80);
543 mt_reg_sync_write(EMI_APB_BASE+0x00000c84,0x00005dc0);
544 mt_reg_sync_write(EMI_APB_BASE+0x00000c88,0x00007d00);
545 mt_reg_sync_write(EMI_APB_BASE+0x00000c8c,0x00003e80);
546 mt_reg_sync_write(EMI_APB_BASE+0x00000c90,0x00005dc0);
547 mt_reg_sync_write(EMI_APB_BASE+0x00000c94,0x00007d00);
548 mt_reg_sync_write(EMI_APB_BASE+0x00000c98,0x000091d5);
549 mt_reg_sync_write(EMI_APB_BASE+0x00000c9c,0x0000a6aa);
550 mt_reg_sync_write(EMI_APB_BASE+0x00000cb0,0x50a07850);
551 mt_reg_sync_write(EMI_APB_BASE+0x00000cb4,0xd5baa078);
552 mt_reg_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
553 mt_reg_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
554
555 mt_reg_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
556 mt_reg_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
557 mt_reg_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
558 mt_reg_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
559 mt_reg_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
560 mt_reg_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
561 mt_reg_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
562 mt_reg_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
563 mt_reg_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
564 mt_reg_sync_write(EMI_APB_BASE+0x00000d3c,0x00000100); //APR shf1 event selet
565 mt_reg_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
566 mt_reg_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
567 mt_reg_sync_write(EMI_APB_BASE+0x00000d50,0x00001000); //APW shf1 event selet
568// mt_reg_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
569// mt_reg_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
570// mt_reg_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
571// mt_reg_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
572// mt_reg_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
573// mt_reg_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
574// mt_reg_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
575// mt_reg_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
576// mt_reg_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
577// mt_reg_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
578// mt_reg_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
579// mt_reg_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
580// mt_reg_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
581// mt_reg_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
582 mt_reg_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
583 mt_reg_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
584 mt_reg_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
585 mt_reg_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
586 mt_reg_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
587// mt_reg_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
588// mt_reg_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
589// mt_reg_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
590// mt_reg_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
591// mt_reg_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
592 mt_reg_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
593 mt_reg_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
594 mt_reg_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
595 mt_reg_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
596 mt_reg_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
597 mt_reg_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
598 mt_reg_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
599 mt_reg_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
600 mt_reg_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
601 mt_reg_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
602 mt_reg_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
603 mt_reg_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
604 mt_reg_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
605 mt_reg_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
606 mt_reg_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
607 mt_reg_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
608}
609
610 void emi_cen_config(unsigned long cfg_base_addr) {
611 unsigned int type = mt_get_dram_type_from_hw_trap();
612
613 if (type == TYPE_LPDDR4X) {
614 emi_cen_config_lp4(cfg_base_addr);
615 } else if (type == TYPE_LPDDR2) {
616 emi_cen_config_lp2(cfg_base_addr);
617 } else {
618 dramc_debug("no dram type for init %u\n", type);
619 ASSERT(0);
620 }
621 }//void emi_cen_config()
622
623static void emi_chn_config_lp4(unsigned long cfg_base_addr)
624{
625#ifdef RANK_512MB // => 1channel , one rank , total= 512MB
626 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x00223012);
627#else //RANK_1G => 1channel , one rank , total= 1GB
628 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x04242010);
629#endif
630 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
631 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
632 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
633 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
634 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
635 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
636 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
637 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
638 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003101);
639 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
640 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
641 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x91fff928); // continous read/write service count and post_wr settings
642 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x91fff928); // continous read/write service count and post_wr settings
643 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3fc79);
644 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3fc79);
645 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
646#ifdef SCN_ICFP
647 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x884102a2); // Stop urgent read first when write command buffer remain < 8
648#else //SCN_UI
649 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x024102a2); // disable all exception read events
650#endif
651 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
652 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
653 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c822f); // Rank-Aware arbitration
654 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
655 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
656 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff); // MD BANK_MASK : disable exception read events
657 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa616cff);
658 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa4178ff); // MD BANK_MASK shuffle 0 (MDR urgent): disable exception read events
659 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
660}
661
662static void emi_chn_config_lp2(unsigned long cfg_base_addr)
663{
664#ifdef RANK_512MB // => 1channel , one rank , total= 512MB
665 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x00223012);
666#else //RANK_1G => 2channel , dual rank , total=4G
667 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
668#endif
669 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
670 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
671 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
672 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
673 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
674 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
675 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
676 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
677 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003101);
678 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
679 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
680 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x0719595e);
681 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x0719595e);
682 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3fc79);
683 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3fc79);
684 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
685#ifdef SCN_ICFP
686 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x884102a2); // Stop urgent read first when write command buffer remain < 8
687#else //SCN_UI
688 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0x824102a2); // Stop urgent read first when write command buffer remain < 2
689#endif
690 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
691 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
692 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c822f); // Rank-Aware arbitration
693 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
694 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
695 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
696 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa616cff);
697 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa417eff);
698 mt_reg_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
699}
700
701void emi_chn_config(unsigned long cfg_base_addr) {
702 unsigned int type = mt_get_dram_type_from_hw_trap();
703
704 if (type == TYPE_LPDDR4X) {
705 emi_chn_config_lp4(cfg_base_addr);
706 } else if (type == TYPE_LPDDR2) {
707 emi_chn_config_lp2(cfg_base_addr);
708 } else {
709 dramc_debug("no dram type for init %u\n", type);
710 ASSERT(0);
711 }
712 }//void emi_chn_config()
713
714 //This is for Chip, Please don't remove it.
715 //This is for Chip, Please don't remove it.
716 //#define EMI_APB_BASE 0x10219000
717 //#define EMI_CHANNEL_APB_BASE 0x10235000
718
719 void emi_init(void)
720 {
721 //Broadcast on
722 //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG,0x0000007f);
723
724 emi_cen_config(EMI_BASE);
725 emi_chn_config(CHN0_EMI_BASE);
726
727 //Broadcast off
728 //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG,0x00000000);
729 }
730
731void emi_init2(void)
732 {
733 //Broadcast on
734 //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG, 0x0000007f);
735
736 mt_reg_sync_write(CHN0_EMI_BASE+0x00000010, 0x00000005);
737 mt_reg_sync_write(EMI_BASE+0x00000060, 0x007815ff);
738
739 //Broadcast off
740 //mt_reg_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000);
741 }
742
743
744void EMI_ESL_Setting1(void)
745{
746 emi_init();
747}
748
749void EMI_ESL_Setting2(void)
750{
751 emi_init2();
752}
753
754
755void EMI_Patch(void)
756{
757 //The following is EMI patch
758
759#if !__ETT__
760 // Enable MPU violation interrupt to MD for D1 and D7
761 *((volatile unsigned int *)EMI_MPU_CTRL_D(1)) |= 0x10;
762 *((volatile unsigned int *)EMI_MPU_CTRL_D(7)) |= 0x10;
763
764 // DVFS threshold
765 if (u1IsLP4Family(mt_get_dram_type_from_hw_trap())){
766 /*LP4*/
767 *((volatile unsigned int *)EMI_BWCT0) = 0x0a000705;
768 *((volatile unsigned int *)EMI_BWCT0_3RD) = 0x0;
769 } else {
770 *((volatile unsigned int *)EMI_BWCT0) = 0x07000505; //total BW setting for VcoreDVFS
771 *((volatile unsigned int *)EMI_BWCT0_3RD) = 0x0;
772 }
773
774 // EMI QoS0.5
775 *((volatile unsigned int *) EMI_BWCT0_2ND) = 0x00030023; // monitor AP
776 *((volatile unsigned int *) EMI_BWCT0_4TH) = 0x00C00023; // monitor GPU
777 *((volatile unsigned int *) EMI_BWCT0_5TH) = 0x00240023; // monitor MM
778
779#ifdef LAST_EMI
780 last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
781 last_emi_info_ptr->decs_magic = LAST_EMI_MAGIC_PATTERN;
782#if CFG_LAST_EMI_BW_DUMP
783 last_emi_info_ptr->decs_ctrl = 0xDECDDECD;
784#else
785 last_emi_info_ptr->decs_ctrl = 0xDEC8DEC8;
786#endif
787 last_emi_info_ptr->decs_dram_type = 0;
788 last_emi_info_ptr->decs_diff_us = 0;
789#endif
790#endif
791}
792
793#if !__ETT__
794void reserve_emi_mbw_buf(void)
795{
796#if 0//def LAST_EMI
797 unsigned long long rsv_start;
798 dram_addr_t dram_addr;
799
800 dram_addr.ch = 0;
801 dram_addr.rk = 0;
802 get_dramc_addr(&dram_addr, 0x0);
803
804 if (dram_addr.full_sys_addr > 0xFFFFFFFF)
805 rsv_start = mblock_reserve_ext(&bootarg.mblock_info, 0x800000, 0x800000, 0x100000000, 0, "emi_mbw_buf");
806 else
807 rsv_start = mblock_reserve_ext(&bootarg.mblock_info, 0x800000, 0x800000, dram_addr.full_sys_addr, 0, "emi_mbw_buf");
808
809 last_emi_info_ptr->mbw_buf_l = (unsigned int) (rsv_start & 0xFFFFFFFF);
810 last_emi_info_ptr->mbw_buf_h = (unsigned int) (rsv_start >> 32);
811#endif
812}
813#endif
814
815static void EMI_rank_swap_emi_setting(EMI_SETTINGS *emi_set)
816{
817 static unsigned int temp;
818
819 if (emi_set->EMI_CONA_VAL & 0x20000) {
820 temp = emi_set->EMI_CONA_VAL;
821 emi_set->EMI_CONA_VAL &= ~(0xF3F0F0F0);
822 emi_set->EMI_CONA_VAL |= (temp & 0xC0C0C0C0) >> 2;
823 emi_set->EMI_CONA_VAL |= (temp & 0x30303030) << 2;
824 emi_set->EMI_CONA_VAL |= (temp & 0x02000000) >> 1;
825 emi_set->EMI_CONA_VAL |= (temp & 0x01000000) << 1;
826
827 temp = emi_set->EMI_CONH_VAL;
828 emi_set->EMI_CONH_VAL &= ~(0xFFFF0030);
829 emi_set->EMI_CONH_VAL |= (temp & 0xF0F00000) >> 4;
830 emi_set->EMI_CONH_VAL |= (temp & 0x0F0F0000) << 4;
831 emi_set->EMI_CONH_VAL |= (temp & 0x00000020) >> 1;
832 emi_set->EMI_CONH_VAL |= (temp & 0x00000010) << 1;
833
834 temp = emi_set->CHN0_EMI_CONA_VAL;
835 emi_set->CHN0_EMI_CONA_VAL &= ~(0x00FFF0FC);
836 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00F00000) >> 4;
837 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x000F0000) << 4;
838 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x0000C0C0) >> 2;
839 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00003030) << 2;
840 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000008) >> 1;
841 emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000004) << 1;
842
843 emi_set->CHN0_EMI_CONA_VAL |= 0x80000000;
844
845 temp = emi_set->DRAM_RANK_SIZE[0];
846 emi_set->DRAM_RANK_SIZE[0] = emi_set->DRAM_RANK_SIZE[1];
847 emi_set->DRAM_RANK_SIZE[1] = temp;
848
849 if (emi_set->dram_cbt_mode_extern == CBT_R0_NORMAL_R1_BYTE)
850 emi_set->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
851 else if (emi_set->dram_cbt_mode_extern == CBT_R0_BYTE_R1_NORMAL)
852 emi_set->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
853 }
854}
855
856#ifdef DRAM_ADAPTIVE
857void EMI_rank_swap_handle(void)
858{
859 static unsigned int handled = 0;
860 int i;
861
862 if (!handled) {
863 EMI_rank_swap_emi_setting(&g_default_emi_setting);
864 handled = 1;
865 }
866}
867#else
868static void EMI_rank_swap_handle(void)
869{
870 static unsigned int handled = 0;
871 int i;
872
873 if (!handled) {
874 EMI_rank_swap_emi_setting(&default_emi_setting);
875
876 for (i = 0 ; i < num_of_emi_records; i++)
877 EMI_rank_swap_emi_setting(&emi_settings[i]);
878
879 handled = 1;
880 }
881}
882#endif
883
884void EMI_set_rank_swap(unsigned int enable)
885{
886 rank_swap = (enable) ? 1 : 0;
887}
888
889void EMI_Init(DRAMC_CTX_T *p)
890{
891 EMI_SETTINGS *emi_set;
892
893 emi_set = get_emi_setting();
894
895 if (rank_swap)
896 EMI_rank_swap_handle();
897
898 EMI_ESL_Setting1(); //Copy Paste from DE
899
900 //The following is MDL settings
901 *(volatile unsigned *)EMI_CONA = emi_set->EMI_CONA_VAL;
902 *(volatile unsigned *)EMI_CONH = emi_set->EMI_CONH_VAL;
903
904 // CHNA and CHNB uses the same CH0 setting
905 *(volatile unsigned *)CHN_EMI_CONA(CHN0_EMI_BASE) = emi_set->CHN0_EMI_CONA_VAL;
906
907//#if CHANNEL_NUM == 1
908// *(volatile unsigned *)EMI_CONF = 0x0;
909//#else
910 *(volatile unsigned *)EMI_CONF = emi_set->EMI_CONF_VAL;
911 if (u1IsLP4Family(p->dram_type))
912 {
913 *(volatile unsigned *)CHN_EMI_CONC(CHN0_EMI_BASE) = 0x0;
914 } else {
915 *(volatile unsigned *)CHN_EMI_CONC(CHN0_EMI_BASE) = emi_set->EMI_CONF_VAL;
916 }
917//#endif
918
919#if 0
920#if __ETT__ && !defined(__LPAE__)
921 /*
922 * special emi mapping w/o LPAE support
923 * RANK0_MAX_SIZE_ETT = 0x40000000 --> RANK0 @0x4000_0000~0x7fff_ffff
924 * RANK1_MAX_SIZE_ETT = 0x40000000 --> RANK1 @0x8000_0000~0xbfff_ffff
925 */
926 /* set all the rank size of all the channels to the minimum value */
927 *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x11110000));
928
929 /* set all the rank size of all channel-0 to the minimum value */
930 *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
931 = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00110000));
932
933#endif
934#endif
935
936 dsb();
937}
938
939void EMI_Init2(void)
940{
941 EMI_ESL_Setting2(); //Copy Paste from DE
942
943 EMI_Patch(); //Please add the EMI patch here
944}
945
946static unsigned int emi_conh = 0;
947static unsigned int chn_emi_cona[2] = {0, 0};
948
949/* return the start address of rank1 */
950unsigned int set_emi_before_rank1_mem_test(void)
951{
952
953 unsigned int emi_cona;
954
955 emi_cona = *(volatile unsigned int*)EMI_CONA;
956 emi_conh = *(volatile unsigned int*)EMI_CONH;
957 chn_emi_cona[0] = *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE);
958#if 0
959 if (emi_cona & 0x100) {
960 /* set all the rank size of all the channels to the minimum value */
961 *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x22220000));
962
963 /* set all the rank size of all channel-0 to the minimum value */
964 *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
965 = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00220000));
966 } else {
967 /* set all the rank size of all the channels to the minimum value */
968 *(volatile unsigned int*)EMI_CONH = ((*(volatile unsigned int*)EMI_CONH & 0x0000ffff) | (0x44440000));
969
970 /* set all the rank size of all channel-0 to the minimum value */
971 *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE)
972 = ((*(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) & 0xff00ffff ) | (0x00440000));
973 }
974
975 dsb();
976#endif
977 return 0x20000000;
978
979}
980
981void restore_emi_after_rank1_mem_test(void)
982{
983 *(volatile unsigned int*)EMI_CONH = emi_conh;
984 *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE) = chn_emi_cona[0];
985 dsb();
986}
987
988unsigned int check_gating_error(void)
989{
990 unsigned int ret = 0;
991
992#ifdef LAST_DRAMC
993 unsigned long phy_base;
994 unsigned int i, err_code = 0;
995 unsigned int misc_stberr_rk0_r, misc_stberr_rk0_f, misc_stberr_rk1_r, misc_stberr_rk1_f;
996
997 phy_base = Channel_B_PHY_AO_BASE_ADDRESS;
998
999 for (i = 0; i < CHANNEL_NUM; ++i, phy_base += 0x8000, err_code = 0) {
1000 misc_stberr_rk0_r = *(volatile unsigned int*)(phy_base + 0x510);
1001 misc_stberr_rk0_f = *(volatile unsigned int*)(phy_base + 0x514);
1002 misc_stberr_rk1_r = *(volatile unsigned int*)(phy_base + 0x518);
1003 misc_stberr_rk1_f = *(volatile unsigned int*)(phy_base + 0x51c);
1004 if (misc_stberr_rk0_r & (1 << 16)) {
1005 ret |= (1 << i);
1006 if ((misc_stberr_rk0_r & 0xffff) != 0) {
1007 err_code |= ERR_DRAM_GATING_RK0_R;
1008 }
1009 if ((misc_stberr_rk0_f & 0xffff) != 0) {
1010 err_code |= ERR_DRAM_GATING_RK0_F;
1011 }
1012 if ((misc_stberr_rk1_r & 0xffff) != 0) {
1013 err_code |= ERR_DRAM_GATING_RK1_R;
1014 }
1015 if ((misc_stberr_rk1_f & 0xffff) != 0) {
1016 err_code |= ERR_DRAM_GATING_RK1_F;
1017 }
1018 dram_fatal_set_gating_err(i, err_code);
1019 dram_fatal_set_stberr(i, 0, (misc_stberr_rk0_r & 0xffff) | ((misc_stberr_rk0_f & 0xffff) << 16));
1020 dram_fatal_set_stberr(i, 1, (misc_stberr_rk1_r & 0xffff) | ((misc_stberr_rk1_f & 0xffff) << 16));
1021 } else {
1022 dram_fatal_set_gating_err(i, 0);
1023 dram_fatal_set_stberr(i, 0, 0);
1024 dram_fatal_set_stberr(i, 1, 0);
1025 }
1026 }
1027#endif
1028
1029 return ret;
1030}
1031
1032#if 0
1033void CHA_HWGW_Print(DRAMC_CTX_T *p)
1034{
1035 U8 u1RefreshRate;
1036 U32 backup_channel, chIdx;
1037
1038 backup_channel = p->channel;
1039
1040#if (FOR_DV_SIMULATION_USED==0)
1041 // Read HW gating tracking
1042#ifdef HW_GATING
1043 for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
1044 {
1045 DramcPrintHWGatingStatus(p, chIdx);
1046 }
1047#endif
1048
1049#if ENABLE_RX_TRACKING_LP4
1050 for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
1051 {
1052 DramcPrintRXDQDQSStatus(p, chIdx);
1053 }
1054#endif
1055
1056#ifdef IMPEDANCE_TRACKING_ENABLE
1057 if(u1IsLP4Family(p->dram_type))
1058 {
1059 DramcPrintIMPTrackingStatus(p, CHANNEL_A);
1060//CH_B HW Fail, can't use DramcPrintIMPTrackingStatus(p, CHANNEL_B);
1061 }
1062#endif
1063
1064#ifdef TEMP_SENSOR_ENABLE
1065 for(chIdx=0; chIdx<p->support_channel_num; chIdx++)
1066 {
1067 u1RefreshRate = u1GetMR4RefreshRate(p, chIdx);
1068 mcSHOW_ERR_MSG(("[CH%d] MRR(MR4) [10:8]=%x\n", chIdx, u1RefreshRate));
1069 }
1070#endif
1071#endif
1072
1073 vSetPHY2ChannelMapping(p, backup_channel);
1074}
1075#endif
1076
1077void Dump_EMIRegisters(DRAMC_CTX_T *p)
1078{
1079#ifndef OLYMPUS_TO_BE_PORTING
1080
1081 U8 ucstatus = 0;
1082 U32 uiAddr;
1083 U32 u4value;
1084
1085 for (uiAddr=0; uiAddr<0x160; uiAddr+=4)
1086 {
1087 mcSHOW_DBG_MSG(("EMI offset:%x, value:%x\n", uiAddr, *(volatile unsigned *)(EMI_APB_BASE+uiAddr)));
1088 }
1089#endif
1090}
1091
1092void print_DBG_info(DRAMC_CTX_T *p)
1093{
1094#ifndef OLYMPUS_TO_BE_PORTING
1095
1096 unsigned int addr = 0x0;
1097 U32 u4value;
1098
1099#ifdef DDR_INIT_TIME_PROFILING
1100 return;
1101#endif
1102
1103 mcSHOW_DBG_MSG(("EMI_CONA=%x\n",*(volatile unsigned *)(EMI_APB_BASE+0x00000000)));
1104 mcSHOW_DBG_MSG(("EMI_CONH=%x\n",*(volatile unsigned *)(EMI_APB_BASE+0x00000038)));
1105
1106 //RISCReadAll();
1107#endif
1108}
1109
1110int mt_get_dram_type(void)
1111{
1112#if (fcFOR_CHIP_ID == fcLaurel)
1113 return (*((volatile unsigned *)(Channel_A_DRAMC_AO_BASE_ADDRESS+0x10)) >> 10) & 0x7;
1114#else
1115 #error No defined mt_get_dram_type for your chip !!!
1116#endif
1117}
1118
1119int mt_get_freq_setting(DRAMC_CTX_T *p)
1120{
1121 return p->frequency;
1122}
1123
1124#ifdef DDR_RESERVE_MODE
1125extern u32 g_ddr_reserve_enable;
1126extern u32 g_ddr_reserve_success;
1127#define TIMEOUT 3
1128extern void before_Dramc_DDR_Reserved_Mode_setting(void);
1129#endif
1130
1131#ifdef DDR_RESERVE_MODE
1132
1133#define CHAN_DRAMC_NAO_MISC_STATUSA(base) (base + 0x80)
1134#define SREF_STATE (1 << 16)
1135
1136static unsigned int is_dramc_exit_slf(void)
1137{
1138 unsigned int ret;
1139 U32 u4DramType = 0;
1140
1141 u4DramType = (*((volatile unsigned int *)(IO_PHYS + 0x22A010)) >> 10 & 0x7);
1142 if(u4DramType >=2) //LP3:1, LP4:2, LP4X:3
1143 {
1144 ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_B_DRAMC_NAO_BASE_ADDRESS);
1145 if ((ret & SREF_STATE) != 0) {
1146 dramc_crit("DRAM CHAN-B is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
1147 return 0;
1148 }
1149 }
1150 else
1151 {
1152 ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_A_DRAMC_NAO_BASE_ADDRESS);
1153 if ((ret & SREF_STATE) != 0) {
1154 dramc_crit("DRAM CHAN-A is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
1155 return 0;
1156 }
1157 }
1158 dramc_crit("ALL DRAM CHAN is not in self-refresh\n");
1159 return 1;
1160}
1161
1162#endif
1163
1164unsigned int dramc_set_vcore_voltage(unsigned int vcore)
1165{
1166#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1167 return mtk_regulator_set_voltage(&reg_vcore, vcore, MAX_VCORE);
1168#endif
1169 return 0;
1170}
1171
1172unsigned int dramc_get_vcore_voltage(void)
1173{
1174#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1175 return mtk_regulator_get_voltage(&reg_vcore);
1176#else
1177 return 0;
1178#endif
1179}
1180
1181unsigned int dramc_set_vdd1_voltage(unsigned int ddr_type, unsigned int vdd1)
1182{
1183#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1184 unsigned int vio18_vocal;
1185 unsigned int vio18_votrim;
1186
1187 if (vdd1 > 1980000)
1188 vdd1 = 188;
1189 else if (vdd1 < 1730000)
1190 vdd1 = 173;
1191 else
1192 vdd1 = vdd1 / 10000;
1193
1194 if (vdd1 > 190) {
1195 vio18_vocal = 0xa;
1196 vio18_votrim = (198 - vdd1);
1197 vio18_votrim |= 0x8;
1198 } else if (vdd1 < 180) {
1199 vio18_vocal = 0x0;
1200 vio18_votrim = (180 - vdd1);
1201 } else {
1202 vio18_vocal = (vdd1 - 180);
1203 vio18_votrim = 0x0;
1204 }
1205
1206#ifdef MTK_PMIC_CHIP_MT6389
1207 pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9C76, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
1208#endif
1209 pmic_config_interface(PMIC_RG_VIO18_VOCAL_ADDR, vio18_vocal, PMIC_RG_VIO18_VOCAL_MASK, PMIC_RG_VIO18_VOCAL_SHIFT);
1210 pmic_config_interface(PMIC_RG_VIO18_VOTRIM_ADDR, vio18_votrim, PMIC_RG_VIO18_VOTRIM_MASK, PMIC_RG_VIO18_VOTRIM_SHIFT);
1211#ifdef MTK_PMIC_CHIP_MT6389
1212 pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
1213#endif
1214#endif
1215
1216 return 0;
1217}
1218
1219unsigned int dramc_get_vdd1_voltage(void)
1220{
1221#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1222 unsigned int vio18_vocal;
1223 unsigned int vio18_votrim;
1224 unsigned int vio18 = 0;
1225
1226 pmic_read_interface(PMIC_RG_VIO18_VOCAL_ADDR, &vio18_vocal, PMIC_RG_VIO18_VOCAL_MASK, PMIC_RG_VIO18_VOCAL_SHIFT);
1227 pmic_read_interface(PMIC_RG_VIO18_VOTRIM_ADDR, &vio18_votrim, PMIC_RG_VIO18_VOTRIM_MASK, PMIC_RG_VIO18_VOTRIM_SHIFT);
1228
1229 vio18 = (180 + vio18_vocal + (vio18_votrim & 0x8) - (vio18_votrim & 0x7)) * 10000;
1230
1231 return vio18;
1232#else
1233 return 0;
1234#endif
1235}
1236
1237#ifdef MTK_PMIC_CHIP_MT6356
1238static unsigned int lp2_vdram_base[] = {1100000, 1200000};
1239static unsigned int lp2_vdram_ofs[] = {20000, 40000};
1240#endif
1241
1242unsigned int dramc_set_vdd2_voltage(unsigned int ddr_type, unsigned int vdd2)
1243{
1244#ifdef MTK_PMIC_CHIP_MT6356
1245 int ret;
1246 int mvdd2;
1247
1248 pmic_config_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, 0, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
1249 if (vdd2 < lp2_vdram_base[0]) {
1250 ret = 0;
1251 mvdd2 = lp2_vdram_base[ret] + lp2_vdram_ofs[ret] - vdd2;
1252 if (mvdd2 > 70000) {
1253 mvdd2 = 70000;
1254 dramc_debug("voltage too low, reset to lowest=%u\n", mvdd2);
1255 }
1256
1257 mvdd2 /= 10000;
1258 mtk_regulator_set_voltage(&reg_vdram, lp2_vdram_base[ret] + lp2_vdram_ofs[ret], 1300000);
1259 pmic_config_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, mvdd2, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
1260 return 0;
1261 }
1262
1263 for (ret = 0;(unsigned int)ret < (sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base));ret++) {
1264 if (vdd2 < lp2_vdram_base[ret]) {
1265 ret -= 1;
1266 break;
1267 }
1268 }
1269
1270 if (ret == sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base))
1271 ret -= 1;
1272
1273 vdd2 -= lp2_vdram_base[ret];
1274 if (vdd2 > 100000) {
1275 vdd2 = 100000;
1276 dramc_debug("voltage offset too high, reset to highest=%u\n", vdd2);
1277 }
1278
1279 vdd2 /= 10000;
1280
1281 mtk_regulator_set_voltage(&reg_vdram, lp2_vdram_base[ret] + lp2_vdram_ofs[ret], 1300000);
1282 pmic_config_interface(PMIC_RG_VDRAM_VOCAL_ADDR, vdd2, PMIC_RG_VDRAM_VOCAL_MASK, PMIC_RG_VDRAM_VOCAL_SHIFT);
1283#endif
1284
1285#ifdef MTK_PMIC_CHIP_MT6389
1286 mtk_regulator_set_voltage(&reg_vdram, vdd2, 1493750);
1287
1288#endif
1289 return 0;
1290}
1291
1292unsigned int dramc_get_vdd2_voltage(unsigned int ddr_type)
1293{
1294 unsigned int sum = 0;
1295#ifdef MTK_PMIC_CHIP_MT6356
1296 unsigned int min = 0;
1297
1298 sum = mtk_regulator_get_voltage(&reg_vdram);
1299 int ret;
1300
1301 for (ret = 0;(unsigned int)ret < sizeof(lp2_vdram_base) / sizeof(*lp2_vdram_base);ret++) {
1302 if (sum == lp2_vdram_base[ret] + lp2_vdram_ofs[ret]) {
1303 break;
1304 }
1305 }
1306
1307 pmic_read_interface(PMIC_RG_VDRAM_VOCAL_ADDR, &sum, PMIC_RG_VDRAM_VOCAL_MASK, PMIC_RG_VDRAM_VOCAL_SHIFT);
1308
1309 sum = lp2_vdram_base[ret] + (sum * 10000);
1310
1311 pmic_read_interface(PMIC_RG_VDRAM_VOTRIM_ADDR, &min, PMIC_RG_VDRAM_VOTRIM_MASK, PMIC_RG_VDRAM_VOTRIM_SHIFT);
1312
1313 sum -= (min * 10000);
1314#endif
1315
1316#ifdef MTK_PMIC_CHIP_MT6389
1317 sum = mtk_regulator_get_voltage(&reg_vdram);
1318#endif
1319 return sum;
1320}
1321
1322#ifdef MTK_PMIC_CHIP_MT6389
1323static unsigned int vdram2_base[] = {600000, 1800000};
1324#endif
1325unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq)
1326{
1327#ifdef MTK_PMIC_CHIP_MT6356
1328#if __ETT__
1329 mtk_regulator_get("ext_buck_vddq", &reg_vddq);
1330 if (ddr_type == TYPE_LPDDR4X)
1331 mtk_regulator_set_voltage(&reg_vddq, vddq, 1300000);
1332#endif
1333#endif
1334
1335#ifdef MTK_PMIC_CHIP_RT5738
1336 if (ddr_type == TYPE_LPDDR4X)
1337 rt5738_set_voltage(RT5738_VDDQ, vddq);
1338#endif
1339
1340#ifdef MTK_PMIC_CHIP_MT6389
1341 mtk_regulator_get("vdram2", &reg_vddq);
1342 if (ddr_type == TYPE_LPDDR4X)
1343 mtk_regulator_set_voltage(&reg_vddq, vddq, 1300000);
1344
1345 unsigned int add = 0;
1346 pmic_config_interface(PMIC_TMA_KEY_ADDR, 0x9C76, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
1347 pmic_config_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, 0, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
1348 pmic_config_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, 0, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
1349 if (vddq > vdram2_base[0])
1350 {
1351 vddq = vddq - vdram2_base[0];
1352 vddq /= 10000;
1353 pmic_config_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, vddq, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
1354 pmic_read_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, &add, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
1355 pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
1356 return 0;
1357 }
1358
1359 if (vddq < vdram2_base[0])
1360 {
1361 vddq = vdram2_base[0] - vddq;
1362 vddq /= 10000;
1363 pmic_config_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, vddq, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
1364 pmic_config_interface(PMIC_TMA_KEY_ADDR, 0, PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
1365 }
1366#endif
1367 return 0;
1368}
1369
1370unsigned int dramc_get_vddq_voltage(unsigned int ddr_type)
1371{
1372#ifdef MTK_PMIC_CHIP_MT6356
1373#if __ETT__
1374 unsigned int sum = 0;
1375
1376 sum = mtk_regulator_get_voltage(&reg_vddq);
1377 return sum;
1378#endif
1379#endif
1380
1381#ifdef MTK_PMIC_CHIP_RT5738
1382 unsigned int sum = 0;
1383 if (ddr_type == TYPE_LPDDR4X)
1384 sum = rt5738_get_voltage(RT5738_VDDQ);
1385 return sum;
1386#endif
1387
1388#ifdef MTK_PMIC_CHIP_MT6389
1389 unsigned int sum = 0;
1390
1391 sum = mtk_regulator_get_voltage(&reg_vddq);
1392 unsigned int add = 0;
1393 pmic_read_interface(PMIC_RG_VDRAM2_VOCAL_0_ADDR, &add, PMIC_RG_VDRAM2_VOCAL_0_MASK, PMIC_RG_VDRAM2_VOCAL_0_SHIFT);
1394 sum += add*10000;
1395 pmic_read_interface(PMIC_RG_VDRAM2_VOTRIM_ADDR, &add, PMIC_RG_VDRAM2_VOTRIM_MASK, PMIC_RG_VDRAM2_VOTRIM_SHIFT);
1396 sum -= add*10000;
1397
1398 return sum;
1399#endif
1400}
1401
1402unsigned int mt_get_dram_type_from_hw_trap(void)
1403{
1404 static unsigned int ddr_type_detected = 0;
1405 static unsigned int pmic_trap_ddr_type = TYPE_LPDDR2;
1406
1407 if (!ddr_type_detected) {
1408#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1409 unsigned int hw_trap;
1410 hw_trap = get_dram_type();
1411
1412 switch (hw_trap) {
1413 case 0:
1414 pmic_trap_ddr_type = TYPE_LPDDR2;
1415 break;
1416 case 2:
1417 pmic_trap_ddr_type = TYPE_LPDDR4X;
1418 break;
1419 default:
1420 dramc_crit("[dramc] Wrong HW TRAP\n");
1421 ASSERT(0);
1422 break;
1423 }
1424 dramc_debug("PMIC TRAP GET DDR TYPE: 0x%x\n", pmic_trap_ddr_type);
1425#endif
1426 ddr_type_detected = 1;
1427 }
1428
1429 return pmic_trap_ddr_type;
1430}
1431
1432void setup_dramc_voltage_by_pmic(void)
1433{
1434#ifdef MTK_PMIC_CHIP_MT6356
1435 unsigned int ddr_type = TYPE_LPDDR4X;//mt_get_dram_type_from_hw_trap();
1436#endif
1437
1438#ifdef MTK_PMIC_CHIP_MT6389
1439 unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
1440#endif
1441
1442#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1443 int ret;
1444
1445 ret = mtk_regulator_get("vcore", &reg_vcore);
1446 if (ret)
1447 dramc_crit("mtk_regulator_get vcore fail\n");
1448
1449#ifdef MTK_PMIC_CHIP_MT6356
1450 ret = mtk_regulator_get("vdram", &reg_vdram);
1451#endif
1452#ifdef MTK_PMIC_CHIP_MT6389
1453 ret = mtk_regulator_get("vdram1", &reg_vdram);
1454#endif
1455 if (ret)
1456 dramc_crit("mtk_regulator_get vdram fail\n");
1457
1458 mtk_regulator_set_mode(&reg_vcore, 0x1);
1459#endif
1460
1461 if (u1IsLP4Family(ddr_type)) {
1462 dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP4));
1463 dramc_set_vddq_voltage(ddr_type, SEL_PREFIX_VDDQ);
1464
1465#ifdef VCORE_BIN
1466 dramc_set_vcore_voltage(get_vcore_uv_table(0));
1467#else
1468 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KOPP0));
1469#endif
1470 } else {
1471 /* LPDDR2 */
1472#ifdef VCORE_BIN
1473 dramc_set_vcore_voltage(get_vcore_uv_table(0));
1474#else
1475 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP2, KOPP0));
1476#endif
1477 dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP2));
1478 }
1479
1480 dramc_crit("Vcore = %d\n", dramc_get_vcore_voltage());
1481 dramc_crit("Vdram = %d\n", dramc_get_vdd2_voltage(ddr_type));
1482 dramc_crit("Vdd1 = %d\n", dramc_get_vdd1_voltage());
1483 if (ddr_type == TYPE_LPDDR4X)
1484 dramc_crit("Vddq = %d\n", dramc_get_vddq_voltage(ddr_type));
1485}
1486
1487static void restore_vcore_setting(void)
1488{
1489#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1490 int ret;
1491
1492 ret = mtk_regulator_get("vcore", &reg_vcore);
1493 if (ret)
1494 dramc_crit("mtk_regulator_get vcore fail\n");
1495#endif
1496
1497#ifdef VCORE_BIN
1498 dramc_set_vcore_voltage(get_vcore_uv_table(0));
1499#else
1500 if (u1IsLP4Family(mt_get_dram_type_from_hw_trap()))
1501 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KOPP0));
1502 else
1503 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP2, KOPP0));
1504#endif
1505
1506 dramc_crit("Vcore = %d\n", dramc_get_vcore_voltage());
1507}
1508
1509static void restore_pmic_setting(void)
1510{
1511 unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
1512
1513 restore_vcore_setting();
1514
1515#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1516 int ret;
1517
1518#ifdef MTK_PMIC_CHIP_MT6356
1519 ret = mtk_regulator_get("vdram", &reg_vdram);
1520#endif
1521#ifdef MTK_PMIC_CHIP_MT6389
1522 ret = mtk_regulator_get("vdram1", &reg_vdram);
1523#endif
1524 if (ret) {
1525 dramc_crit("mtk_regulator_get vdram fail\n");
1526 return;
1527 }
1528#endif
1529
1530 if (u1IsLP4Family(ddr_type)) {
1531 /* LPDDR4 */
1532#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1533 ret = mtk_regulator_enable(&reg_vdram, 1);
1534 if (ret)
1535 dramc_crit("disable reg_vdram failed\n");
1536#endif
1537 dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP4));
1538 dramc_set_vddq_voltage(ddr_type, SEL_PREFIX_VDDQ);
1539 } else
1540 dramc_set_vdd2_voltage(ddr_type, SEL_PREFIX_VDRAM(LP2));
1541
1542 dramc_crit("Vdram = %d\n", dramc_get_vdd2_voltage(ddr_type));
1543 if (ddr_type == TYPE_LPDDR4X)
1544 dramc_crit("Vddq = %d\n", dramc_get_vddq_voltage(ddr_type));
1545}
1546
1547void switch_dramc_voltage_to_auto_mode(void)
1548{
1549#if defined(MTK_PMIC_CHIP_MT6356) || defined(MTK_PMIC_CHIP_MT6389)
1550 mtk_regulator_set_mode(&reg_vcore, 0x0);
1551#endif
1552
1553#if 0//def MTK_PMIC_CHIP_RT5738
1554 if (u1IsLP4Family(mt_get_dram_type_from_hw_trap())) {
1555 rt5738_set_mode(RT5738_VDD2, 0x0);
1556 rt5738_set_mode(RT5738_VDDQ, 0x0);
1557 }
1558#endif
1559}
1560
1561void release_dram(void)
1562{
1563#ifdef DDR_RESERVE_MODE
1564 int i;
1565 int counter = TIMEOUT;
1566
1567 // scy: restore pmic setting (VCORE, VDRAM, VSRAM, VDDQ)
1568 restore_pmic_setting();
1569 drm_release_rg_dramc_conf_iso();//Release DRAMC/PHY conf ISO
1570 Dramc_DDR_Reserved_Mode_setting();
1571 drm_release_rg_dramc_iso();//Release PHY IO ISO
1572 drm_release_rg_dramc_sref();//Let DRAM Leave SR
1573
1574 // setup for EMI: touch center EMI and channel EMI to enable CLK
1575 dramc_crit("[DDR reserve] EMI CONA: %x\n", *(volatile unsigned int*)EMI_CONA);
1576 dramc_crit("[DDR reserve] EMI CHA CONA: %x\n", *(volatile unsigned int*)CHN_EMI_CONA(CHN0_EMI_BASE));
1577 for (i=0;i<10;i++);
1578
1579 while(counter)
1580 {
1581 if(is_dramc_exit_slf() == 1) /* expect to exit dram-self-refresh */
1582 break;
1583 counter--;
1584 }
1585
1586 if(counter == 0)
1587 {
1588 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
1589 {
1590 dramc_crit("[DDR Reserve] release dram from self-refresh FAIL!\n");
1591 g_ddr_reserve_success = 0;
1592 }
1593 }
1594 else
1595 {
1596 dramc_crit("[DDR Reserve] release dram from self-refresh PASS!\n");
1597 }
1598 Dramc_DDR_Reserved_Mode_AfterSR();
1599 //Expect to Use LPDDR3200 and PHYPLL as output, so no need to handle
1600 //shuffle status since the status will be reset by system reset
1601 //There is an PLLL_SHU_GP in SPM which will reset by system reset
1602 return;
1603#endif
1604}
1605
1606void check_ddr_reserve_status(void)
1607{
1608#ifdef DDR_RESERVE_MODE
1609 /* get status of DCS and DVFSRC */
1610 int dvfsrc_success = drm_is_dvfsrc_success();
1611 int dvfsrc_en = drm_is_dvfsrc_enable();
1612 int counter = TIMEOUT;
1613
1614 if(drm_is_reserve_ddr_enabled())
1615 {
1616 g_ddr_reserve_enable = 1;
1617#ifdef LAST_DRAMC
1618 dram_fatal_set_ddr_rsv_mode_flow();
1619#endif
1620
1621 if(drm_is_reserve_ddr_mode_success())
1622 {
1623 while(counter)
1624 {
1625 if(drm_is_dram_slf())
1626 {
1627 g_ddr_reserve_success = 1;
1628 break;
1629 }
1630 counter--;
1631 }
1632 if(counter == 0)
1633 {
1634 dramc_crit("[DDR Reserve] ddr reserve mode success but DRAM not in self-refresh!\n");
1635 g_ddr_reserve_success = 0;
1636#ifdef LAST_DRAMC
1637 dram_fatal_set_ddr_rsv_mode_err();
1638#endif
1639 }
1640 }
1641 else
1642 {
1643 dramc_crit("[DDR Reserve] ddr reserve mode FAIL!\n");
1644 g_ddr_reserve_success = 0;
1645#ifdef LAST_DRAMC
1646 dram_fatal_set_ddr_rsv_mode_err();
1647#endif
1648 }
1649 /* Disable DDR-reserve mode in pre-loader stage then enable it again in kernel stage */
1650 //drm_dram_reserved(0);
1651
1652 /* overwrite g_ddr_reserve_success if some of dvfsrc/drs failed */
1653 /* TODO: check DRS status */
1654 if (dvfsrc_en == 1 && dvfsrc_success == 0) {
1655 dramc_crit("[DDR Reserve] DRAM content might be corrupted -> clear g_ddr_reserve_success\n");
1656 g_ddr_reserve_success = 0;
1657
1658 if (dvfsrc_en == 1 && dvfsrc_success == 0) {
1659 dramc_crit("[DDR Reserve] DVFSRC fail!\n");
1660#if 0//def LAST_DRAMC
1661 dram_fatal_set_dvfsrc_err();
1662#endif
1663 }
1664 } else {
1665 dramc_crit("[DDR Reserve] DCS/DVFSRC success! (dvfsrc_en=%d)\n", dvfsrc_en);
1666 }
1667 /* release dram, no matter success or failed */
1668 release_dram();
1669 }
1670 else
1671 {
1672 dramc_crit("[DDR Reserve] ddr reserve mode not be enabled yet\n");
1673 g_ddr_reserve_enable = 0;
1674 }
1675#endif
1676}
1677
1678unsigned int DRAM_MRR(int MRR_num)
1679{
1680 u16 MRR_value = 0x0;
1681 DRAMC_CTX_T *p = psCurrDramCtx;
1682
1683 DramcModeRegRead(p, MRR_num, &MRR_value);
1684 return MRR_value;
1685}
1686
1687static int mt_get_dram_type_for_dis(void)
1688{
1689 return mt_get_dram_type_from_hw_trap();
1690}
1691
1692#ifndef DRAM_ADAPTIVE
1693#ifdef COMBO_MCP
1694static char id[22];
1695static int enable_combo_dis = 0;
1696static int emmc_nand_id_len=8;
1697static int fw_id_len;
1698static int mt_get_mdl_number(void)
1699{
1700 static int found = 0;
1701 static int mdl_number = -1;
1702 int i;
1703 int j;
1704 int has_emmc_nand = 0;
1705 int discrete_dram_num = 0;
1706 int mcp_dram_num = 0;
1707 u64 rank0_size=0, rank1_size=0;
1708
1709 extern int platform_get_mcp_id(u8 *id, u32 len, u32 *fw_id_len);
1710 unsigned int dram_type;
1711 DRAM_INFO_BY_MRR_T DramInfo;
1712 DRAM_DRAM_TYPE_T Dis_DramType;
1713 DRAM_CBT_MODE_EXTERN_T DramMode;
1714
1715 if (!(found)) {
1716 int result=0;
1717
1718 for (i = 0 ; i < num_of_emi_records; i++) {
1719 if ((emi_settings[i].type & 0x0F00) == 0x0000)
1720 discrete_dram_num ++;
1721 else
1722 mcp_dram_num ++;
1723 }
1724
1725 /*If the number >=2 &&
1726 * one of them is discrete DRAM
1727 * enable combo discrete dram parse flow
1728 * */
1729 if ((discrete_dram_num > 0) && (num_of_emi_records >= 2))
1730 enable_combo_dis = 1;
1731
1732 dramc_crit("[EMI] mcp_dram_num:%d,discrete_dram_num:%d,enable_combo_dis:%d\r\n",mcp_dram_num,discrete_dram_num,enable_combo_dis);
1733
1734 Dis_DramType = mt_get_dram_type_for_dis();
1735 /* resetting dram type */
1736 if (Dis_DramType == TYPE_LPDDR2)
1737 Dis_DramType = TYPE_LPDDR3;
1738#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1739 if (!u1IsLP4Family(Dis_DramType) || read_offline_dram_mdl_data(&DramInfo)) {
1740#endif
1741 if (u1IsLP4Family(Dis_DramType))
1742 DramMode = CBT_BYTE_MODE1;
1743 else
1744 DramMode = CBT_NORMAL_MODE;
1745
1746 Init_DRAM(Dis_DramType, DramMode, &DramInfo, GET_MDL_USED);
1747 DramInfo.u2MR5VendorID &= 0xFF;
1748
1749#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1750 if (u1IsLP4Family(Dis_DramType))
1751 write_offline_dram_mdl_data(&DramInfo);
1752 }
1753#endif
1754
1755
1756 if (u1IsLP4Family(Dis_DramType)) {
1757 rank0_size = (u64) DramInfo.u8MR8Density[1][0]; //now only K CHB to save time
1758 rank1_size = (u64) DramInfo.u8MR8Density[1][1]; //now only K CHB to save time
1759 } else {
1760 rank0_size = (u64) DramInfo.u8MR8Density[0][0]; //now only K CHA to save time
1761 rank1_size = (u64) DramInfo.u8MR8Density[0][1]; //now only K CHA to save time
1762 }
1763
1764 /*
1765 *
1766 * 0. if there is only one discrete dram, use index=0 emi setting and boot it.
1767 * */
1768 if ((0 == mcp_dram_num) && (1 == discrete_dram_num)) {
1769 mdl_number = 0;
1770 found = 1;
1771
1772 //K first frequency (1066MHz)
1773
1774 return mdl_number;
1775 }
1776
1777 /* 1.
1778 * if there is MCP dram in the list, we try to find emi setting by emmc ID
1779 * */
1780 if (mcp_dram_num > 0) {
1781 result = platform_get_mcp_id(id, emmc_nand_id_len,&fw_id_len);
1782 for (i = 0; i < num_of_emi_records; i++) {
1783 if ((emi_settings[i].type & 0xF) != Dis_DramType)
1784 continue;
1785
1786 if (emi_settings[i].type != 0) {
1787 if ((emi_settings[i].type & 0xF00) != 0x000) {
1788 /* valid ID */
1789 if (result == 0
1790#if 0//SUPPORT_SAVE_TIME_FOR_CALIBRATION
1791 && (emi_settings[i].DRAM_RANK_SIZE[0] == rank0_size) &&
1792 (emi_settings[i].DRAM_RANK_SIZE[1] == rank1_size)
1793#endif
1794 ) {
1795 if ((emi_settings[i].type & 0xF00) == 0x200) {
1796 /* eMMC */
1797 if (memcmp(id, emi_settings[i].ID, emi_settings[i].id_length) == 0) {
1798 mdl_number = i;
1799 found = 1;
1800 break;
1801 } else {
1802 dramc_crit("[MDL] index(%d) emmc id match failed\n",i);
1803 }
1804 }
1805 else if ((emi_settings[i].type & 0xF00) == 0x100)
1806 {
1807 /* nand */
1808 if (memcmp(id, emi_settings[i].ID, emi_settings[i].id_length) == 0){
1809 mdl_number = i;
1810 found = 1;
1811 break;
1812 } else {
1813 dramc_crit("[MDL] index(%d) nand id match failed\n",i);
1814 }
1815 }
1816 }
1817 }
1818 }
1819 }
1820 }
1821
1822 /* 2. find emi setting by MODE register 5
1823 * */
1824 // if we have found the index from by eMMC ID checking, we can boot android by the setting
1825 // if not, we try by vendor ID
1826 if ((0 == found) && (1 == enable_combo_dis))
1827 {
1828 EMI_SETTINGS *emi_set;
1829
1830 // try to find discrete dram by MR5 (vendor ID)
1831 for (i = 0; i < num_of_emi_records; i++) {
1832 dramc_crit("[MDL]index:%d, MR5:%x, type:%x, vender_id:%x\n", i, emi_settings[i].iLPDDR3_MODE_REG_5, emi_settings[i].type, DramInfo.u2MR5VendorID);
1833 // only check discrete dram type
1834 if ((emi_settings[i].type & 0xF) == Dis_DramType && (emi_settings[i].type & 0x0F00) == 0x0000) {
1835 // support for combo discrete dram
1836 if (emi_settings[i].iLPDDR3_MODE_REG_5 == DramInfo.u2MR5VendorID) {
1837 dramc_debug("[MDL] index:%d, rank0_size:0x%llx(0x%llx), rank1_size:0x%llx(0x%llx)\n", i,
1838 rank0_size, emi_settings[i].DRAM_RANK_SIZE[0],
1839 rank1_size, emi_settings[i].DRAM_RANK_SIZE[1]);
1840 if((emi_settings[i].DRAM_RANK_SIZE[0] == rank0_size) && (emi_settings[i].DRAM_RANK_SIZE[1] == rank1_size)) {
1841 mdl_number = i;
1842 found = 1;
1843 break;
1844 }
1845 }
1846 }
1847 }
1848 }
1849
1850 dramc_crit("found:%d,i:%d\n",found,i);
1851 }
1852
1853 return mdl_number;
1854}
1855#endif
1856
1857int get_dram_channel_nr(void)
1858{
1859 int channel_nr;
1860
1861 channel_nr = (*((volatile unsigned int*)(EMI_CONA)) >> 8) & 0x3;
1862
1863 return (0x1 << channel_nr);
1864}
1865
1866int get_dram_rank_nr(void)
1867{
1868 int emi_cona;
1869
1870#ifdef COMBO_MCP
1871 int index;
1872#ifdef DDR_RESERVE_MODE
1873 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
1874 {
1875 emi_cona = *(volatile unsigned int*)(EMI_CONA);
1876 }
1877 else
1878#endif
1879 {
1880 index = mt_get_mdl_number();
1881 if (index < 0 || index >= num_of_emi_records)
1882 {
1883 return -1;
1884 }
1885
1886 emi_cona = emi_settings[index].EMI_CONA_VAL;
1887 }
1888#else
1889 emi_cona = default_emi_setting.EMI_CONA_VAL;
1890#if CFG_FPGA_PLATFORM
1891 return 1;
1892#endif
1893#endif
1894
1895 if ((emi_cona & (1 << 17)) != 0 || //for channel 0
1896 (emi_cona & (1 << 16)) != 0 ) //for channel 1
1897 return 2;
1898 else
1899 return 1;
1900}
1901
1902unsigned int get_dram_mr(unsigned int index)
1903{
1904 switch (index) {
1905 case 5:
1906 return mr5;
1907 default:
1908 return 0;
1909 }
1910}
1911
1912void get_dram_rank_size_by_EMI_CONA (u64 dram_rank_size[])
1913{
1914 unsigned col_bit, row_bit;
1915 u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size;
1916#ifndef COMBO_MCP
1917 unsigned emi_cona = default_emi_setting.EMI_CONA_VAL;
1918 unsigned emi_conh = default_emi_setting.EMI_CONH_VAL;
1919#else
1920 unsigned emi_cona = *(volatile unsigned int*)(EMI_CONA);
1921 unsigned emi_conh = *(volatile unsigned int*)(EMI_CONH);
1922#endif
1923 unsigned nr_chan_enabled = 1;
1924 u64 per_chan_rank0_size = 0, per_chan_rank1_size = 0;
1925 unsigned shift_for_16bit = 1; // data width = 2 bytes
1926
1927 if (emi_cona & 0x2)
1928 shift_for_16bit = 0; // data width = 4 bytes
1929
1930 dram_rank_size[0] = 0;
1931 dram_rank_size[1] = 0;
1932
1933 ch0_rank0_size = (emi_conh >> 16) & 0xf;
1934 ch0_rank1_size = (emi_conh >> 20) & 0xf;
1935 ch1_rank0_size = (emi_conh >> 24) & 0xf;
1936 ch1_rank1_size = (emi_conh >> 28) & 0xf;
1937
1938 switch ((emi_cona >> 8) & 0x3) {
1939 case 0:
1940 nr_chan_enabled = 1;
1941 break;
1942 case 1:
1943 nr_chan_enabled = 2;
1944 break;
1945 case 2:
1946 nr_chan_enabled = 4;
1947 break;
1948 case 3:
1949 default:
1950 dramc_crit("invalid CHN_EN field in EMI_CONA (0x%x)\n", emi_cona);
1951 // assume 4 channel by default
1952 nr_chan_enabled = 2;
1953 break;
1954 }
1955
1956 // CH0 EMI
1957 {
1958 if(ch0_rank0_size == 0)
1959 {
1960 //rank 0 setting
1961 col_bit = ((emi_cona >> 4) & 0x03) + 9;
1962 row_bit = ((((emi_cona >> 24) & 0x01) << 2) + ((emi_cona >> 12) & 0x03)) + 13;
1963 per_chan_rank0_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
1964 }
1965 else
1966 {
1967 per_chan_rank0_size = (ch0_rank0_size * 256 << 20);
1968 }
1969
1970 if (0 != (emi_cona & (1 << 17))) //rank 1 exist
1971 {
1972 if(ch0_rank1_size == 0)
1973 {
1974 col_bit = ((emi_cona >> 6) & 0x03) + 9;
1975 row_bit = ((((emi_cona >> 25) & 0x01) << 2) + ((emi_cona >> 14) & 0x03)) + 13;
1976 per_chan_rank1_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
1977 }
1978 else
1979 {
1980 per_chan_rank1_size = (ch0_rank1_size * 256 << 20);
1981 }
1982 }
1983
1984 if (nr_chan_enabled > 2) {
1985 // CH0 EMI have CHA+CHB
1986 dram_rank_size[0] = per_chan_rank0_size * 2;
1987 dram_rank_size[1] = per_chan_rank1_size * 2;
1988 } else {
1989 // CH0 EMI is CHA
1990 dram_rank_size[0] = per_chan_rank0_size;
1991 dram_rank_size[1] = per_chan_rank1_size;
1992 }
1993 }
1994
1995 // CH1 EMI
1996 if(nr_chan_enabled >= 2)
1997 {
1998 if(ch1_rank0_size == 0)
1999 {
2000 //rank0 setting
2001 col_bit = ((emi_cona >> 20) & 0x03) + 9;
2002 row_bit = ((((emi_conh >> 4) & 0x01) << 2) + ((emi_cona >> 28) & 0x03)) + 13;
2003 per_chan_rank0_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
2004 }
2005 else
2006 {
2007 per_chan_rank0_size = (ch1_rank0_size * 256 << 20);
2008 }
2009
2010 if (0 != (emi_cona & (1 << 16))) //rank 1 exist
2011 {
2012 if(ch1_rank1_size == 0)
2013 {
2014 col_bit = ((emi_cona >> 22) & 0x03) + 9;
2015 row_bit = ((((emi_conh >> 5) & 0x01) << 2) + ((emi_cona >> 30) & 0x03)) + 13;
2016 per_chan_rank1_size = ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); // data width (bytes) * 8 banks
2017 }
2018 else
2019 {
2020 per_chan_rank1_size = (ch1_rank1_size * 256 << 20);
2021 }
2022 }
2023 if (nr_chan_enabled > 2) {
2024 // CH1 EMI have CHC+CHD
2025 dram_rank_size[0] += per_chan_rank0_size * 2;
2026 dram_rank_size[1] += per_chan_rank1_size * 2;
2027 } else {
2028 // CH1 EMI is CHB
2029 dram_rank_size[0] += per_chan_rank0_size;
2030 dram_rank_size[1] += per_chan_rank1_size;
2031 }
2032 }
2033
2034 //dramc_debug("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n", dram_rank_size[0], dram_rank_size[1]);
2035}
2036
2037#if (FOR_DV_SIMULATION_USED==0)
2038#if !__FLASH_TOOL_DA__ && !__ETT__
2039void get_dram_rank_size(u64 dram_rank_size[])
2040{
2041#ifdef COMBO_MCP
2042 int index, rank_nr, i;
2043
2044#ifdef DDR_RESERVE_MODE
2045 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
2046 {
2047 get_dram_rank_size_by_EMI_CONA(dram_rank_size);
2048 }
2049 else
2050#endif
2051 {
2052 index = mt_get_mdl_number();
2053
2054 if (index < 0 || index >= num_of_emi_records)
2055 {
2056 return;
2057 }
2058
2059 rank_nr = get_dram_rank_nr();
2060
2061 for(i = 0; i < rank_nr; i++){
2062 dram_rank_size[i] = emi_settings[index].DRAM_RANK_SIZE[i];
2063
2064 dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
2065 }
2066 }
2067 return;
2068#else
2069 get_dram_rank_size_by_EMI_CONA(dram_rank_size);
2070 return;
2071#endif
2072}
2073
2074void reserve_dramc_dummy_read(void)
2075{
2076#if 0//def LAST_DRAMC
2077 unsigned long long reserve_start;
2078 char *reserve_name[4] = {"dramc-rk0", "dramc-rk1", "dramc-rk2", "dramc-rk3"};
2079 unsigned int i;
2080 int rank_nr;
2081 dram_addr_t dram_addr;
2082
2083 dram_addr.ch = 0;
2084
2085 rank_nr = get_dram_rank_nr();
2086 if (rank_nr <= 0) {
2087 dramc_crit("[DRAMC] reserve dummy read fail\n");
2088 ASSERT(0);
2089 }
2090
2091 for (i = 0; i < (unsigned int)rank_nr; i++) {
2092 dram_addr.rk = i;
2093 get_dramc_addr(&dram_addr, 0x0);
2094#ifdef CUSTOM_CONFIG_MAX_DRAM_SIZE
2095 if (dram_addr.full_sys_addr > (unsigned long long)CUSTOM_CONFIG_MAX_DRAM_SIZE + 0x40000000LL)
2096 break;
2097#endif
2098 reserve_start = mblock_reserve_ext(&bootarg.mblock_info, 0x1000, 0x1000, dram_addr.full_sys_addr, 0, reserve_name[i]);
2099 if (reserve_start != (dram_addr.full_sys_addr - 0x1000)) {
2100 dramc_crit("[DRAMC] dummy read fail (0x%llx)\n", reserve_start);
2101 ASSERT(0);
2102 }
2103 }
2104#endif
2105}
2106#endif //#if !__FLASH_TOOL_DA__ && !__ETT__
2107#endif
2108#endif //DRAM_ADAPTIVE
2109
2110#ifdef DRAM_ADAPTIVE
2111void get_rank_size_by_emi(u64 dram_rank_size[]);
2112int get_dram_channel_nr(void)
2113{
2114 int channel_nr;
2115
2116 channel_nr = (*((volatile unsigned int*)(EMI_CONA)) >> 8) & 0x3;
2117
2118 return (0x1 << channel_nr);
2119}
2120
2121int get_rank_nr_by_emi(void)
2122{
2123 unsigned int cen_emi_cona = *(volatile unsigned int*)(EMI_CONA);
2124
2125 if (cen_emi_cona & (0x3 << 16))
2126 return 2;
2127 else
2128 return 1;
2129}
2130
2131int get_dram_rank_nr(void)
2132{
2133 int cen_emi_cona;
2134
2135#ifdef DDR_RESERVE_MODE
2136 if (g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
2137 return get_rank_nr_by_emi();
2138#endif
2139
2140#ifdef DRAM_ADAPTIVE
2141 if (!auto_detect_done)
2142 ASSERT(0);
2143#endif
2144
2145 cen_emi_cona = g_default_emi_setting.EMI_CONA_VAL;
2146
2147 if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0
2148 (cen_emi_cona & (1 << 16)) != 0 ) //for channel 1
2149 return 2;
2150 else
2151 return 1;
2152}
2153
2154void get_rank_size_by_emi(u64 dram_rank_size[])
2155{
2156 int i;
2157 unsigned int quad_ch_ratio;
2158 unsigned int col_bit, row_bit;
2159 unsigned long long ch0_rank0_size, ch0_rank1_size;
2160 unsigned long long ch1_rank0_size, ch1_rank1_size;
2161 unsigned int cen_emi_conh = *(volatile unsigned int*)(EMI_CONH);
2162 unsigned long long dq_width;
2163
2164 switch (mt_get_dram_type_from_hw_trap()) {
2165 case TYPE_LPDDR4X:
2166 case TYPE_LPDDR2:
2167 dq_width = 1;
2168 break;
2169 default:
2170 ASSERT(0);
2171 }
2172
2173 dram_rank_size[0] = 0;
2174 dram_rank_size[1] = 0;
2175
2176 ch0_rank0_size = (cen_emi_conh >> 16) & 0xF;
2177 ch0_rank1_size = (cen_emi_conh >> 20) & 0xF;
2178 ch1_rank0_size = (cen_emi_conh >> 24) & 0xF;
2179 ch1_rank1_size = (cen_emi_conh >> 28) & 0xF;
2180
2181 quad_ch_ratio = (get_rank_nr_by_emi() == 4)? 2 : 1;
2182 ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28;
2183 ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28;
2184 ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28;
2185 ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28;
2186
2187 if(ch0_rank0_size == 0) {
2188 dramc_crit("[EMI] undefined CONH for CH0 RANK0\n");
2189 ASSERT(0);
2190 }
2191 dram_rank_size[0] += ch0_rank0_size;
2192
2193 if (get_rank_nr_by_emi() > 1) {
2194 if(ch0_rank1_size == 0) {
2195 dramc_crit("[EMI] undefined CONH for CH0 RANK1\n");
2196 ASSERT(0);
2197 }
2198 dram_rank_size[1] += ch0_rank1_size;
2199 }
2200
2201 if(get_dram_channel_nr() > 1) {
2202 if(ch1_rank0_size == 0) {
2203 dramc_crit("[EMI] undefined CONH for CH1 RANK0\n");
2204 ASSERT(0);
2205 }
2206 dram_rank_size[0] += ch1_rank0_size;
2207
2208 if (get_rank_nr_by_emi() > 1) {
2209 if(ch1_rank1_size == 0) {
2210 dramc_crit("[EMI] undefined CONH for CH1 RANK1\n");
2211 ASSERT(0);
2212 }
2213 dram_rank_size[1] += ch1_rank1_size;
2214 }
2215 }
2216
2217 dramc_crit("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n",
2218 dram_rank_size[0], dram_rank_size[1]);
2219}
2220
2221
2222unsigned int get_dram_mr(unsigned int index)
2223{
2224 switch (index) {
2225 case 5:
2226 return mr5;
2227 default:
2228 return 0;
2229 }
2230}
2231
2232#if (FOR_DV_SIMULATION_USED==0)
2233#if !__FLASH_TOOL_DA__ && !__ETT__
2234void get_dram_rank_size(u64 dram_rank_size[])
2235{
2236 int rank_nr, i;
2237
2238#ifdef DDR_RESERVE_MODE
2239 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
2240 return get_rank_size_by_emi(dram_rank_size);
2241#endif
2242
2243#ifdef DRAM_ADAPTIVE
2244 if (!auto_detect_done)
2245 ASSERT(0);
2246#endif
2247
2248 rank_nr = get_dram_rank_nr();
2249
2250 for(i = 0; i < rank_nr; i++) {
2251 dram_rank_size[i] = g_default_emi_setting.DRAM_RANK_SIZE[i];
2252 dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
2253 }
2254}
2255
2256#endif //#if !__FLASH_TOOL_DA__ && !__ETT__
2257#endif
2258
2259static int update_dram_setting(EMI_SETTINGS *default_emi_setting, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
2260{
2261 default_emi_setting->type = dram_type;
2262
2263 if (dram_info != NULL) {
2264 default_emi_setting->DRAM_RANK_SIZE[0] = (u64)(dram_info->u8MR8Density[0][0] + dram_info->u8MR8Density[1][0]);
2265 default_emi_setting->DRAM_RANK_SIZE[1] = (u64)(dram_info->u8MR8Density[1][0] + dram_info->u8MR8Density[1][1]);
2266
2267 default_emi_setting->iLPDDR3_MODE_REG_5 = dram_info->u2MR5VendorID;
2268
2269 if (dram_info->u4RankNum == 1) { // single rank
2270 if (dram_info->u1DieNum[RANK_0] == 1)
2271 default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
2272 else if (dram_info->u1DieNum[RANK_0] == 2)
2273 default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
2274 else
2275 return -1;
2276 } else if (dram_info->u4RankNum == 2) { // dual rank
2277 if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 1))
2278 default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
2279 else if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 2))
2280 default_emi_setting->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
2281 else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 1))
2282 default_emi_setting->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
2283 else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 2))
2284 default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
2285 else
2286 return -2;
2287 } else
2288 return -3;
2289 } else
2290 return -4;
2291
2292 return 0;
2293}
2294
2295int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info)
2296{
2297 unsigned int ddr_type;
2298 unsigned int cen_cona_val, cen_conf_val, cen_conh_val;
2299 unsigned int chn_cona_val;
2300 unsigned int cen_conf_shf;
2301 unsigned int col, row, row_ext, rk_size, rk_size_ext, rk_size_chn_ext;
2302 unsigned int temp_val;
2303 int i;
2304
2305 ddr_type = default_emi_setting->type & 0xFF;
2306 cen_conh_val = 0x00000003;
2307 if (u1IsLP4Family(ddr_type)) {
2308 cen_cona_val = 0x00000004;
2309 chn_cona_val = 0x04000000;
2310 } else {
2311 cen_cona_val = 0x00000006;
2312 if (emi_info->bank_width[0] == 3)
2313 chn_cona_val = 0x00000002;
2314 else
2315 chn_cona_val = 0x03000002;
2316 }
2317
2318 for (i = 0; i < emi_info->rk_num; i++) {
2319 row = emi_info->row_width[i] - 13;
2320 row_ext = row >> 2;
2321 row &= 0x3;
2322
2323 col = emi_info->col_width[i] - 9;
2324
2325 rk_size = emi_info->rank_size[i] >> 28;
2326 if (u1IsLP4Family(ddr_type))
2327 rk_size >>= 1;
2328 rk_size_ext = rk_size >> 4;
2329 rk_size_chn_ext = rk_size_ext & 0x1;
2330 rk_size &= 0xF;
2331
2332 if (i == 1) {
2333 col <<= 2;
2334 row <<= 2;
2335 row_ext <<= 1;
2336 rk_size <<= 4;
2337 rk_size_ext <<= 4;
2338 rk_size_chn_ext <<= 1;
2339 cen_cona_val |= 0x00030000;
2340 chn_cona_val |= 0x00000001;
2341 }
2342
2343 cen_cona_val |=
2344 (col << 4) | (row << 12) | (col << 20) |
2345 (row_ext << 24) | (row << 28);
2346 cen_conh_val |=
2347 (row_ext << 4) | (rk_size << 16);
2348 chn_cona_val |=
2349 (row_ext << 2) | (col << 4) | (row << 12) |
2350 (rk_size << 16) | (rk_size_chn_ext << 8);
2351 }
2352
2353 cen_conf_shf = 0;
2354 for (i = 0; i < emi_info->rk_num; i++) {
2355 temp_val = 2 + emi_info->col_width[i];
2356 if (cen_conf_shf < temp_val)
2357 cen_conf_shf = temp_val;
2358 }
2359 if (u1IsLP4Family(ddr_type))
2360 cen_conf_val = 0x421 << ((cen_conf_shf - 9) * 4);
2361 else
2362 {
2363 if (emi_info->bank_width[0] == 3)
2364 cen_conf_val = 0x421 << ((cen_conf_shf - 8) * 4);
2365 else
2366 cen_conf_val = 0x21 << ((cen_conf_shf - 8) * 4);
2367 }
2368
2369 while(cen_conf_val & 0xFFF) {
2370 cen_conf_val <<= 4;
2371 }
2372
2373 dramc_crit("[EMI] %s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x)\n",
2374 "CEN_CONA", cen_cona_val,
2375 "CEN_CONF", cen_conf_val,
2376 "CEN_CONH", cen_conh_val,
2377 "CHN_CONA", chn_cona_val);
2378
2379 default_emi_setting->EMI_CONA_VAL = cen_cona_val;
2380 default_emi_setting->EMI_CONF_VAL = cen_conf_val;
2381 default_emi_setting->EMI_CONH_VAL = cen_conh_val;
2382 default_emi_setting->CHN0_EMI_CONA_VAL = chn_cona_val;
2383 default_emi_setting->CHN1_EMI_CONA_VAL = chn_cona_val;
2384
2385 return 0;
2386}
2387
2388static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
2389{
2390 unsigned int i;
2391 unsigned long long die_size;
2392
2393 emi_info->dram_type = dram_type;
2394 emi_info->ch_num = 1;
2395 if (dram_info->u4BankMode == BANK_TYPE_S2) {
2396 emi_info->bank_width[0] = 2;
2397 emi_info->bank_width[1] = 2;
2398 }
2399 else {
2400 emi_info->bank_width[0] = 3;
2401 emi_info->bank_width[1] = 3;
2402 }
2403 emi_info->col_width[0] = 10;
2404 emi_info->col_width[1] = 10;
2405
2406 if (dram_info != NULL) {
2407 emi_info->rank_size[0] = (u64)(dram_info->u8MR8Density[0][0] + dram_info->u8MR8Density[1][0]);
2408 emi_info->rank_size[1] = (u64)(dram_info->u8MR8Density[1][0] + dram_info->u8MR8Density[1][1]);
2409
2410 emi_info->rk_num = dram_info->u4RankNum;
2411
2412 for (i = 0; i < emi_info->rk_num; i++) {
2413 die_size = emi_info->rank_size[i] / dram_info->u1DieNum[i];
2414 switch (die_size | (dram_info->u1DieNum[i] << 4) | u1IsLP4Family(dram_type)) {
2415 case 0x20000011ULL: // 4Gb, x16, LP4
2416 emi_info->row_width[i] = 14;
2417 break;
2418 case 0x20000021ULL: // 4Gb, x8, LP4
2419 case 0x40000021ULL: // 8Gb, x8, LP4
2420 case 0x30000011ULL: // 6Gb, x16, LP4
2421 case 0x40000011ULL: // 8Gb, x16, LP4
2422 emi_info->row_width[i] = 15;
2423 break;
2424 case 0x30000021ULL: // 6Gb, x8, LP4
2425 case 0x60000011ULL: // 12Gb, x16, LP4
2426 case 0x80000011ULL: // 16Gb, x16, LP4
2427 emi_info->row_width[i] = 16;
2428 break;
2429 case 0x060000021ULL: // 12Gb, x8, LP4
2430 case 0x080000021ULL: // 16Gb, x8, LP4
2431 case 0x0C0000011ULL: // 24Gb, x16, LP4
2432 case 0x100000011ULL: // 32Gb, x16, LP4
2433 emi_info->row_width[i] = 17;
2434 break;
2435 case 0x0C0000021ULL: // 24Gb, x8, LP4
2436 case 0x100000021ULL: // 32Gb, x8, LP4
2437 emi_info->row_width[i] = 18;
2438 break;
2439 //FOR LP2 Decode
2440 #if 0
2441 case 0x800010ULL: // 64Mb, x32, LP2
2442 emi_info->col_width[i] = 7;
2443 emi_info->row_width[i] = 12;
2444 emi_info->bank_width[i] = 2;
2445 break;
2446 case 0x800020ULL: // 64Mb, x16, LP2
2447 case 0x1000010ULL: // 128Mb, x32, LP2
2448 emi_info->col_width[i] = 8;
2449 emi_info->row_width[i] = 12;
2450 emi_info->bank_width[i] = 2;
2451 break;
2452 case 0x1000020ULL: // 128Mb, x16, LP2
2453 emi_info->col_width[i] = 9;
2454 emi_info->row_width[i] = 12;
2455 emi_info->bank_width[i] = 2;
2456 break;
2457 case 0x2000010ULL: // 256Mb, x32, LP2
2458 emi_info->col_width[i] = 8;
2459 emi_info->row_width[i] = 13;
2460 emi_info->bank_width[i] = 2;
2461 break;
2462 case 0x2000020ULL: // 256Mb, x16, LP2
2463 case 0x4000010ULL: // 512Mb, x32, LP2
2464 emi_info->bank_width[i] = 2;
2465 emi_info->col_width[i] = 9;
2466 emi_info->row_width[i] = 13;
2467 break;
2468 case 0x4000020ULL: // 512Mb, x16, LP2
2469 emi_info->col_width[i] = 10;
2470 emi_info->row_width[i] = 13;
2471 emi_info->bank_width[i] = 2;
2472 break;
2473 #endif
2474 case 0x8000010ULL: // 1Gb, x32, LP2
2475 if (dram_info->u4BankMode == BANK_TYPE_S2) {
2476 emi_info->col_width[i] = 9;
2477 emi_info->row_width[i] = 14;
2478 } else {
2479 emi_info->col_width[i] = 9;
2480 emi_info->row_width[i] = 13;
2481 }
2482 break;
2483 case 0x8000020ULL: // 1Gb, x16, LP2
2484 if (dram_info->u4BankMode == BANK_TYPE_S2) {
2485 emi_info->col_width[i] = 10;
2486 emi_info->row_width[i] = 14;
2487 } else {
2488 emi_info->col_width[i] = 10;
2489 emi_info->row_width[i] = 13;
2490 }
2491 break;
2492 case 0x10000010ULL: // 2Gb, x32, LP2
2493 if (dram_info->u4BankMode == BANK_TYPE_S2) {
2494 emi_info->col_width[i] = 9;
2495 emi_info->row_width[i] = 15;
2496 } else {
2497 emi_info->col_width[i] = 9;
2498 emi_info->row_width[i] = 14;
2499 }
2500 break;
2501 case 0x10000020ULL: // 2Gb, x16, LP2
2502 if (dram_info->u4BankMode == BANK_TYPE_S2) {
2503 emi_info->col_width[i] = 10;
2504 emi_info->row_width[i] = 15;
2505 } else {
2506 emi_info->col_width[i] = 10;
2507 emi_info->row_width[i] = 14;
2508 }
2509 break;
2510 case 0x20000010ULL: // 4Gb, x32, LP2
2511 emi_info->col_width[i] = 10;
2512 emi_info->row_width[i] = 14;
2513 break;
2514 case 0x20000020ULL: // 4Gb, x16, LP2
2515 emi_info->col_width[i] = 11;
2516 emi_info->row_width[i] = 14;
2517 break;
2518 case 0x40000010ULL: // 8Gb, x32, LP2
2519 emi_info->col_width[i] = 10;
2520 emi_info->row_width[i] = 15;
2521 break;
2522 case 0x40000020ULL: // 8Gb, x16, LP2
2523 emi_info->col_width[i] = 11;
2524 emi_info->row_width[i] = 15;
2525 break;
2526 default:
2527 return -1;
2528 }
2529 }
2530 } else
2531 return -1;
2532
2533 return 0;
2534}
2535#endif
2536
2537
2538#if (FOR_DV_SIMULATION_USED==0)
2539#if !__ETT__
2540#ifdef DRAM_ADAPTIVE
2541void dram_auto_detection(void)
2542{
2543 DRAM_INFO_BY_MRR_T dram_info = {0};
2544 EMI_INFO_T emi_info = {0};
2545 DRAM_CBT_MODE_EXTERN_T dram_mode;
2546 unsigned int dram_type;
2547 int ret;
2548
2549 dram_type = (unsigned int)mt_get_dram_type_for_dis();
2550 if (dram_type == TYPE_LPDDR2)
2551 dram_type = TYPE_LPDDR3;
2552 g_default_emi_setting.type &= ~0xFF;
2553 g_default_emi_setting.type |= (dram_type & 0xFF);
2554#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2555 if (!u1IsLP4Family(dram_type) ||
2556 read_offline_dram_mdl_data(&dram_info) < 0) {
2557#endif
2558 dram_mode = (u1IsLP4Family(dram_type))?
2559 CBT_BYTE_MODE1 : CBT_NORMAL_MODE;
2560
2561 dramc_crit("[DRAMC] Init_DRAM GET_MDL_USED start\n");
2562 Init_DRAM(dram_type, dram_mode, &dram_info, GET_MDL_USED);
2563 dramc_crit("[DRAMC] Init_DRAM GET_MDL_USED end\n");
2564#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
2565 if (u1IsLP4Family(dram_type))
2566 write_offline_dram_mdl_data(&dram_info);
2567 }
2568#endif
2569
2570
2571 ret = update_dram_setting(&g_default_emi_setting, dram_type, &dram_info);
2572 if (ret) {
2573 dramc_crit("[DRAMC] update_dram_setting err %d\n", ret);
2574 ASSERT(0);
2575 }
2576
2577 ret = decode_emi_info(&emi_info, dram_type, &dram_info);
2578 if (ret) {
2579 dramc_crit("[DRAMC] decode_emi_info err %d\n", ret);
2580 ASSERT(0);
2581 }
2582
2583 ret = update_emi_setting(&g_default_emi_setting, &emi_info);
2584 if (ret) {
2585 dramc_crit("[DRAMC] update_emi_setting err %d\n", ret);
2586 ASSERT(0);
2587 }
2588
2589 auto_detect_done = 1;
2590}
2591#endif
2592
2593void mt_set_emi(void)
2594{
2595 /*unsigned int SW_CTRL_VC, HW_CTRL_VC;*/
2596 EMI_SETTINGS *emi_set;
2597
2598 // set voltage and hw trapping before mdl
2599 setup_dramc_voltage_by_pmic();
2600
2601#ifdef VCORE_BIN
2602 dvfsrc_opp_level_mapping();
2603#endif
2604
2605#ifndef DRAM_ADAPTIVE
2606#ifdef COMBO_MCP
2607 int index;
2608
2609 index = mt_get_mdl_number();
2610 dramc_crit("[EMI] MDL number = %d\r\n", index);
2611 if (index < 0 || index >= num_of_emi_records)
2612 {
2613 dramc_crit("[EMI] setting failed 0x%x\r\n", index);
2614 ASSERT(0);
2615 }
2616 else
2617 {
2618 emi_setting_index = index;
2619 emi_set = &emi_settings[emi_setting_index];
2620 }
2621#else
2622 dramc_crit("[EMI] ComboMCP not ready, using default setting\n");
2623 emi_setting_index = -1;
2624 emi_set = &default_emi_setting;
2625#endif
2626 mr5 = emi_set->iLPDDR3_MODE_REG_5;
2627#else
2628 dram_auto_detection();
2629 emi_set = &g_default_emi_setting;
2630#endif
2631
2632#ifdef DDR_RESERVE_MODE
2633 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==0)
2634 Before_Init_DRAM_While_Reserve_Mode_fail(emi_set->type & 0xF);
2635#endif
2636
2637 Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
2638 switch_dramc_voltage_to_auto_mode();
2639 restore_vcore_setting();
2640
2641#if 0
2642 {
2643 DRAMC_CTX_T * p = psCurrDramCtx;
2644 DramcRegDump(p);
2645 }
2646#endif
2647}
2648#endif
2649#endif
2650
2651#define DRAMC_ADDR_SHIFT_CHN(addr, channel) (addr + (channel * 0x10000))
2652
2653void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
2654{
2655 unsigned int emi_cona, emi_conf;
2656 unsigned long long rank_size[4];
2657 unsigned int channel_num, rank_num;
2658 unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width;
2659 unsigned int temp;
2660 unsigned int index;
2661 unsigned int ddr_type = mt_get_dram_type_from_hw_trap();
2662
2663 emi_cona = *((volatile unsigned int *)EMI_CONA);
2664 emi_conf = *((volatile unsigned int *)EMI_CONF) >> 8;
2665 #ifdef DRAM_ADAPTIVE
2666 get_rank_size_by_emi(rank_size);
2667 #else
2668 get_dram_rank_size_by_EMI_CONA(rank_size);
2669 #endif
2670 rank_num = (unsigned int) get_dram_rank_nr();
2671 channel_num = (unsigned int) get_dram_channel_nr();
2672
2673 if (rank_num >= sizeof(rank_size) / sizeof(*rank_size)) {
2674 dramc_crit("[Dramc] Wrong rank_num: %u\n", rank_num);
2675 ASSERT(0);
2676 }
2677
2678 phy_addr -= 0x40000000;
2679 for (index = 0; index < rank_num; index++) {
2680 if (phy_addr >= rank_size[index])
2681 phy_addr -= rank_size[index];
2682 else
2683 break;
2684 }
2685
2686 for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
2687 bit_xor = (emi_conf >> (4 * (bit_scramble - 11))) & 0xf;
2688 bit_xor &= phy_addr >> 16;
2689 for (bit_shift = 0; bit_shift < 4; bit_shift++)
2690 phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble;
2691 }
2692
2693 if (channel_num > 1) {
2694 channel_pos = ((emi_cona >> 2) & 0x3) + 7;
2695
2696 for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) {
2697 if ((unsigned int)(1 << bit_shift) >= channel_num)
2698 break;
2699 channel_width++;
2700 }
2701
2702 switch (channel_width) {
2703 case 2:
2704 dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2);
2705 break;
2706 default:
2707 dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1);
2708 break;
2709 }
2710 dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1));
2711 } else {
2712 dram_addr->addr = phy_addr;
2713 }
2714
2715 if (u1IsLP4Family(ddr_type))
2716 dram_addr->addr >>= 1;
2717 else
2718 dram_addr->addr >>= 2;
2719
2720 temp = dram_addr->addr;
2721 switch ((emi_cona >> 4) & 0x3) {
2722 case 0:
2723 dram_addr->col = temp & 0x1FF;
2724 temp = temp >> 9;
2725 break;
2726 case 1:
2727 dram_addr->col = temp & 0x3FF;
2728 temp = temp >> 10;
2729 break;
2730 case 2:
2731 default:
2732 dram_addr->col = temp & 0x7FF;
2733 temp = temp >> 11;
2734 break;
2735 }
2736 dram_addr->bk = temp & 0x7;
2737 temp = temp >> 3;
2738
2739 dram_addr->row = temp;
2740
2741 //mcSHOW_DBG_MSG(("ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr));
2742 //mcSHOW_DBG_MSG(("bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col));
2743}
2744
2745void put_dummy_read_pattern(unsigned long long dst_pa, unsigned long src_pa, unsigned int len)
2746{
2747 *((volatile unsigned int *)(CQ_DMA_BASE + 0x018)) = 7 << 16;
2748
2749 *((volatile unsigned int *)(CQ_DMA_BASE + 0x01c)) = src_pa & 0xffffffff;
2750 *((volatile unsigned int *)(CQ_DMA_BASE + 0x060)) = 0;
2751
2752 *((volatile unsigned int *)(CQ_DMA_BASE + 0x020)) = dst_pa & 0xffffffff;
2753 *((volatile unsigned int *)(CQ_DMA_BASE + 0x064)) = dst_pa >> 32;
2754
2755 *((volatile unsigned int *)(CQ_DMA_BASE + 0x024)) = len;
2756 dsb();
2757 *((volatile unsigned int *)(CQ_DMA_BASE + 0x008)) = 0x1;
2758
2759 while(*((volatile unsigned int *)(CQ_DMA_BASE + 0x008)));
2760
2761 *((volatile unsigned int *)(CQ_DMA_BASE + 0x064)) = 0;
2762}
2763
2764static unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset)
2765{
2766 unsigned int channel_num, rank_num;
2767 unsigned long long dummy_read_addr;
2768 unsigned long long rank_size[4];
2769 unsigned int index;
2770 unsigned int *src_addr;
2771
2772 channel_num = (unsigned int) get_dram_channel_nr();
2773 rank_num = (unsigned int) get_dram_rank_nr();
2774 #ifdef DRAM_ADAPTIVE
2775 get_rank_size_by_emi(rank_size);
2776 #else
2777 get_dram_rank_size_by_EMI_CONA(rank_size);
2778 #endif
2779 dummy_read_addr = 0x40000000;
2780 src_addr = (unsigned int *) 0x40000000;
2781
2782 if (dram_addr->ch >= channel_num) {
2783 mcSHOW_DBG_MSG(("[DRAMC] invalid channel: %d\n", dram_addr->ch));
2784 return 0;
2785 }
2786
2787 if (dram_addr->rk >= rank_num) {
2788 mcSHOW_DBG_MSG(("[DRAMC] invalid rank: %d\n", dram_addr->rk));
2789 return 0;
2790 }
2791
2792 for (index = 0; index <= dram_addr->rk; index++)
2793 dummy_read_addr += rank_size[index];
2794 dummy_read_addr -= offset;
2795 if (dram_addr->ch == 0)
2796 dummy_read_addr &= ~(0x100);
2797
2798 if (offset == 0x20) {
2799 for (index = 0; index < 4; index++)
2800 *(src_addr + index) = 0xAAAA5555;
2801 put_dummy_read_pattern(dummy_read_addr, (unsigned long)src_addr, 16);
2802 }
2803
2804 dram_addr->full_sys_addr = dummy_read_addr;
2805 phy_addr_to_dram_addr(dram_addr, dummy_read_addr);
2806
2807 return dram_addr->addr;
2808}
2809
2810unsigned int get_dummy_read_addr(dram_addr_t *dram_addr)
2811{
2812 return get_dramc_addr(dram_addr, 0x20); // 32-byte align for dummy RW pattern
2813}
2814
2815unsigned int get_ta2_addr(dram_addr_t *dram_addr)
2816{
2817 unsigned int addr = get_dramc_addr(dram_addr, 0x1000);
2818
2819 if (!u1IsLP4Family(mt_get_dram_type_from_hw_trap()))
2820 addr <<= 2;
2821
2822 return addr & 0xFFFFFFF0;
2823}
2824
2825void init_ta2_single_channel(unsigned int channel)
2826{
2827 unsigned int temp;
2828 unsigned int matype[2];
2829 unsigned int col_shf[2] = {0, 0};
2830 dram_addr_t dram_addr;
2831 DRAMC_CTX_T *p = psCurrDramCtx;
2832 int rank_nr;
2833
2834 // mt6771: CHN0_EMI for CHN-A; CHN1_EMI for CHN-B
2835 if(channel < 2) {
2836 matype[0] = (*(volatile unsigned *)EMI_CONA >> 4) & 0x3;
2837 matype[1] = (*(volatile unsigned *)EMI_CONA >> 6) & 0x3;
2838 } else {
2839 matype[0] = (*(volatile unsigned *)EMI_CONA >> 20) & 0x3;
2840 matype[1] = (*(volatile unsigned *)EMI_CONA >> 22) & 0x3;
2841 }
2842
2843 rank_nr = get_dram_rank_nr();
2844 if (rank_nr > 1) {
2845 if (matype[0] < matype[1]) {
2846 col_shf[0] = matype[1] - matype[0];
2847 matype[0] = matype[1];
2848 } else if (matype[1] < matype[0])
2849 col_shf[1] = matype[0] - matype[1];
2850 }
2851
2852 matype[0] = (matype[0] + 1) << 30;
2853
2854 // disable self test engine1 and self test engine2
2855 temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel)) & 0x1FFFFFFF;
2856 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel), temp);
2857
2858 // set MATYPE
2859 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
2860 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU_CONF0, channel), temp);
2861 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU2_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
2862 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU2_CONF0, channel), temp);
2863 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU3_CONF0, channel)) & 0x3FFFFFFF) | matype[0];
2864 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_SHU3_CONF0, channel), temp);
2865
2866 if (rank_nr > 1) {
2867 // set rank address for test agent to auto
2868 temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_4, channel)) & 0x8FFFFFFF;
2869 temp |= (0x4 << 28);
2870 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_4, channel), temp);
2871
2872 // set test for both rank0 and rank1
2873 temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel)) & 0xFFFFFFF0;
2874 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_3, channel), temp | 0x1);
2875 }
2876
2877 // set base address for test agent to reserved space
2878 dram_addr.ch = channel;
2879 dram_addr.rk = 0;
2880 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_1, channel)) & 0x0000000F);
2881 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_1, channel), temp | (get_ta2_addr(&dram_addr) << col_shf[0]));
2882 dram_addr.rk = 1;
2883 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_5, channel)) & 0x0000000F);
2884 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_5, channel), temp | (get_ta2_addr(&dram_addr) << col_shf[1]));
2885
2886 // set test length (offset) to 0x20
2887 temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_2, channel)) & 0x0000000F) | (0x20 << 4);
2888 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_2, channel), temp);
2889
2890 return;
2891}
2892
2893#ifdef LAST_DRAMC
2894
2895static unsigned int is_last_dramc_initialized(void)
2896{
2897 if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
2898 return 0;
2899 } else {
2900 return 1;
2901 }
2902}
2903
2904void update_last_dramc_info(void)
2905{
2906 unsigned int chn;
2907 unsigned int latch_result = 0;
2908 unsigned int temp;
2909 unsigned int *curr;
2910 DRAMC_CTX_T *p = psCurrDramCtx;
2911
2912 // init checksum and magic pattern
2913 if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
2914 last_dramc_info_ptr->ta2_result_magic = LAST_DRAMC_MAGIC_PATTERN;
2915 last_dramc_info_ptr->ta2_result_last = 0;
2916 last_dramc_info_ptr->ta2_result_past = 0;
2917 last_dramc_info_ptr->ta2_result_checksum = LAST_DRAMC_MAGIC_PATTERN;
2918 last_dramc_info_ptr->reboot_count = 0;
2919 } else {
2920 last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
2921 last_dramc_info_ptr->reboot_count++;
2922 last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
2923 }
2924
2925 // TODO: check DCS status
2926
2927 // read data from latch register and reset
2928 for (chn = 0; chn < CHANNEL_NUM; ++chn) {
2929 //dramc_crit("[LastDRAMC] latch result before RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
2930 latch_result = (latch_result << 16) | u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0xFFFF;
2931 temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn));
2932 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn), temp | 0x00000004);
2933 vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_DDRCONF0, chn), temp & 0xFFFFFFFB);
2934 //dramc_crit("[LastDRAMC] latch result after RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
2935 }
2936
2937 last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->ta2_result_past ^ latch_result;
2938 last_dramc_info_ptr->ta2_result_past = last_dramc_info_ptr->ta2_result_last;
2939 last_dramc_info_ptr->ta2_result_last = latch_result;
2940 for (temp = 0; temp < sizeof(LAST_DRAMC_INFO_T) / sizeof(temp); temp++) {
2941 curr = (unsigned int *)last_dramc_info_ptr + temp;
2942 dramc_crit("[LastDRAMC] 0x%x: 0x%x\n", curr, *curr);
2943 }
2944
2945 return;
2946}
2947
2948void update_last_dramc_k_voltage(DRAMC_CTX_T *p, unsigned int voltage)
2949{
2950 unsigned int shu_type;
2951
2952 shu_type = get_shuffleIndex_by_Freq(p);
2953
2954 last_dramc_info_ptr->k_voltage[shu_type] = voltage;
2955}
2956
2957void init_ta2_all_channel(void)
2958{
2959 unsigned int chn;
2960
2961 update_last_dramc_info();
2962
2963 // TODO: consider DCS
2964 for (chn = 0; chn < CHANNEL_NUM; ++chn)
2965 init_ta2_single_channel(chn);
2966}
2967
2968
2969unsigned int check_gating_err_in_dramc_latch(void)
2970{
2971 unsigned int chn, ret = 0;
2972 DRAMC_CTX_T *p = psCurrDramCtx;
2973
2974 if (/*(g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
2975 || mtk_wdt_is_pmic_full_reset() ||*/ (is_last_dramc_initialized() == 0)){
2976 dramc_crit("for cold boot, always return 0\n");
2977 return 0;
2978 }
2979
2980 for (chn = 0; chn <= 3; ++chn) {
2981 if (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0x80) {
2982 dramc_crit("[dramc] found gating error in channel %d (0x%x)\n",
2983 chn, u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
2984 ret |= (1 << chn);
2985 }
2986 }
2987
2988 return ret;
2989}
2990
2991void dram_fatal_exception_detection_start(void)
2992{
2993 last_dramc_info_ptr = (LAST_DRAMC_INFO_T *) get_dbg_info_base(KEY_LAST_DRAMC);
2994
2995 if (/*(g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
2996 || mtk_wdt_is_pmic_full_reset() ||*/ (is_last_dramc_initialized() == 0)){
2997 /* cold boot: initialize last_dram_fatal_err_flag and dram_fatal_err_flag */
2998 dramc_crit("[dramc] init SRAM region for DRAM exception detection\n");
2999 last_dramc_info_ptr->last_fatal_err_flag = 0x0;
3000 last_dramc_info_ptr->storage_api_err_flag = 0x0;
3001 dram_fatal_init_stberr();
3002 } else {
3003 last_dramc_info_ptr->last_fatal_err_flag = last_dramc_info_ptr->fatal_err_flag;
3004 last_dramc_info_ptr->storage_api_err_flag = 0x0;
3005 dram_fatal_backup_stberr();
3006 dram_fatal_init_stberr();
3007 }
3008
3009 last_dramc_info_ptr->fatal_err_flag = 1 << OFFSET_DRAM_FATAL_ERR;
3010 dsb();
3011}
3012
3013void dram_fatal_exception_detection_end(void)
3014{
3015 last_dramc_info_ptr->fatal_err_flag = 0x0;
3016 dsb();
3017}
3018
3019unsigned int check_dram_fatal_exception(void)
3020{
3021 dramc_crit("[dramc] DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->fatal_err_flag);
3022
3023 return ((last_dramc_info_ptr->fatal_err_flag & ~((1 << OFFSET_DRAM_FATAL_ERR)|DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
3024}
3025
3026unsigned int check_last_dram_fatal_exception(void)
3027{
3028 dramc_crit("[dramc] LAST_DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->last_fatal_err_flag);
3029
3030 return ((last_dramc_info_ptr->last_fatal_err_flag & ~(DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
3031}
3032
3033void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code)
3034{
3035 unsigned int shift = OFFSET_DRAM_TA2_ERR + 2 * chn, ret;
3036
3037 if (chn > 3)
3038 return;
3039
3040 ret = last_dramc_info_ptr->fatal_err_flag & ~(0x7 << shift);
3041 last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0x7) << shift);
3042 dsb();
3043}
3044
3045void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code)
3046{
3047 unsigned int shift = OFFSET_DRAM_GATING_ERR + 4 * chn, ret;
3048
3049 if (chn > 3)
3050 return;
3051
3052 ret = last_dramc_info_ptr->fatal_err_flag & ~(0xf << shift);
3053 last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0xf) << shift);
3054 dsb();
3055}
3056
3057void dram_fatal_init_stberr(void)
3058{
3059 last_dramc_info_ptr->gating_err[0][0] = 0x0;
3060 last_dramc_info_ptr->gating_err[0][1] = 0x0;
3061 last_dramc_info_ptr->gating_err[1][0] = 0x0;
3062 last_dramc_info_ptr->gating_err[1][1] = 0x0;
3063
3064 dsb();
3065}
3066
3067void dram_fatal_backup_stberr(void)
3068{
3069 last_dramc_info_ptr->last_gating_err[0][0] = last_dramc_info_ptr->gating_err[0][0];
3070 last_dramc_info_ptr->last_gating_err[0][1] = last_dramc_info_ptr->gating_err[0][1];
3071 last_dramc_info_ptr->last_gating_err[1][0] = last_dramc_info_ptr->gating_err[1][0];
3072 last_dramc_info_ptr->last_gating_err[1][1] = last_dramc_info_ptr->gating_err[1][1];
3073
3074 dsb();
3075}
3076
3077void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code)
3078{
3079 if ((chn > 1) || (rk > 1))
3080 return;
3081
3082 last_dramc_info_ptr->gating_err[chn][rk] = err_code;
3083
3084 dsb();
3085}
3086
3087void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset)
3088{
3089 unsigned int ret;
3090
3091 ret = last_dramc_info_ptr->fatal_err_flag & ~(mask << offset);
3092 last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & mask) << offset);
3093 dsb();
3094}
3095
3096#endif
3097
3098#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
3099
3100#if !__ETT__
3101#include <lib/bio.h>
3102//#include <partition.h>
3103#include <pl_version.h>
3104#endif
3105
3106u32 g_dram_storage_api_err_code;
3107
3108static u16 crc16(const u8* data, u32 length){
3109 u8 x;
3110 u16 crc = 0xFFFF;
3111
3112 while (length--) {
3113 x = crc >> 8 ^ *data++;
3114 x ^= x >> 4;
3115 crc = (crc << 8) ^ ((u8)(x << 12)) ^ ((u8)(x <<5)) ^ ((u8)x);
3116 }
3117 return crc;
3118}
3119
3120static void assign_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
3121{
3122 /* need to initialize checksum to 0 before calculation */
3123 shu_data->checksum = 0;
3124 shu_data->checksum = crc16((u8*)shu_data, sizeof(*shu_data));
3125}
3126
3127static int check_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
3128{
3129 u16 checksum_in_storage = shu_data->checksum;
3130
3131 assign_checksum_for_dram_data(shu_data);
3132
3133 return (shu_data->checksum == checksum_in_storage) ? 1 : 0;
3134}
3135
3136#ifdef COMBO_MCP
3137static void assign_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
3138{
3139 /* need to initialize checksum to 0 before calculation */
3140 mrr_info->checksum = 0;
3141 mrr_info->checksum = crc16((u8*)mrr_info, sizeof(*mrr_info));
3142}
3143
3144static int check_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
3145{
3146 u16 checksum_in_storage = mrr_info->checksum;
3147
3148 assign_checksum_for_mdl_data(mrr_info);
3149
3150 return (mrr_info->checksum == checksum_in_storage) ? 1 : 0;
3151}
3152#endif
3153
3154#if !__ETT__
3155#ifdef COMBO_MCP
3156static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
3157{
3158 int i, ret;
3159 u16 emi_checksum;
3160 bdev_t *bootdev = NULL;
3161 DRAM_CALIBRATION_HEADER_T hdr;
3162 DRAM_CALIBRATION_MRR_DATA_T mrr_info;
3163 DRAM_CALIBRATION_SHU_DATA_T shu_data;
3164 DRAM_CALIBRATION_DATA_T *datap = NULL;
3165
3166 if (dram_offline_data_flags)
3167 goto exit;
3168
3169 if (DramInfo == NULL) {
3170 dramc_crit("[dramc] DramInfo == NULL, skip\n");
3171 dram_offline_data_flags = ERR_NULL_POINTER;
3172 goto exit;
3173 }
3174
3175 bootdev = bio_open_by_label("bootpara");
3176 if (!bootdev) {
3177 bootdev = bio_open("bootpara");
3178 if (!bootdev) {
3179 dramc_crit("bootpara is not exist.");
3180 dram_offline_data_flags = ERR_BLKDEV_NO_PART;
3181 goto exit;
3182 }
3183 }
3184
3185 ret = bio_read(bootdev, (u8*)&hdr, 0, sizeof(hdr));
3186 if (ret != 0) {
3187 dramc_crit("[dramc] bio_read %s failed\n", "hdr");
3188 dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
3189 goto exit;
3190 }
3191
3192 if (hdr.pl_version != PL_VERSION) {
3193 /* current preloader version does not match the calibration hdr in storage -> erase the partition */
3194 dramc_crit("[dramc] PL_VERSION is updated, erase the DRAM shu_data\n");
3195
3196 shu_data.checksum = 0;
3197
3198 /* clear each shuffle */
3199 for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
3200 ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
3201 if (ret != 0) {
3202 dramc_crit("[dramc] bio_write failed\n");
3203 dram_offline_data_flags = ERR_BLKDEV_WRITE_FAIL;
3204 goto exit;
3205 }
3206 }
3207
3208 dram_offline_data_flags = ERR_PL_UPDATED;
3209 goto exit;
3210 }
3211
3212 /* check magic number */
3213 if (hdr.magic_number != DRAM_CALIBRATION_DATA_MAGIC) {
3214 dramc_crit("[dramc] magic number mismatch\n");
3215 dram_offline_data_flags = ERR_MAGIC_NUMBER;
3216 goto exit;
3217 }
3218
3219 ret = bio_read(bootdev, (u8*)&mrr_info, ((unsigned long) &datap->mrr_info), sizeof(mrr_info));
3220 if (ret != 0) {
3221 dramc_crit("[dramc] bio_read %s failed\n", "data");
3222 dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
3223 goto exit;
3224 }
3225
3226 /* check checksum */
3227 if (check_checksum_for_mdl_data(&mrr_info) != 1) {
3228 dramc_crit("[dramc] checksum failed\n");
3229 dram_offline_data_flags = ERR_CHECKSUM;
3230
3231 goto exit;
3232 }
3233
3234 emi_checksum = crc16((u8*)emi_settings, sizeof(emi_settings));
3235
3236 if (emi_checksum != mrr_info.emi_checksum) {
3237 dramc_crit("[dramc] emi checksum failed\n");
3238 dram_offline_data_flags = ERR_CHECKSUM;
3239
3240 goto exit;
3241 }
3242
3243 /* copy the data stored in storage to the data structure for calibration */
3244 memcpy(DramInfo, &(mrr_info.DramInfo), sizeof(*DramInfo));
3245
3246exit:
3247 if (dram_offline_data_flags)
3248 SET_DRAM_STORAGE_API_ERR(dram_offline_data_flags, DRAM_STORAGE_API_READ);
3249
3250 return 0 - dram_offline_data_flags;
3251}
3252
3253static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
3254{
3255 int ret;
3256 bdev_t *bootdev = NULL;
3257 DRAM_CALIBRATION_HEADER_T hdr;
3258 DRAM_CALIBRATION_MRR_DATA_T mrr_info;
3259 DRAM_CALIBRATION_DATA_T *datap = NULL;
3260
3261 if (DramInfo == NULL) {
3262 dramc_crit("[dramc] DramInfo == NULL, skip\n");
3263 SET_DRAM_STORAGE_API_ERR(ERR_NULL_POINTER, DRAM_STORAGE_API_WRITE);
3264 return -ERR_NULL_POINTER;
3265 }
3266
3267 bootdev = bio_open_by_label("bootpara");
3268 if (!bootdev) {
3269 bootdev = bio_open("bootpara");
3270 if (!bootdev) {
3271 dramc_crit("bootpara is not exist.");
3272 return -ERR_BLKDEV_NO_PART;
3273 }
3274 }
3275
3276 memcpy(&(mrr_info.DramInfo), DramInfo, sizeof(*DramInfo));
3277
3278#if 0
3279 /* assign PL version */
3280 hdr.pl_version = PL_VERSION;
3281
3282 /* assign magic number */
3283 hdr.magic_number = DRAM_CALIBRATION_DATA_MAGIC;
3284
3285 /* assign api error code */
3286 hdr.calib_err_code = g_dram_storage_api_err_code;
3287
3288 ret = blkdev_write(bootdev, part_dram_data_addr, sizeof(hdr), (u8*)&hdr, PART_ID_DRAM_DATA);
3289 if (ret != 0) {
3290 dramc_crit("[dramc] blkdev_write failed\n");
3291 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
3292 return -ERR_BLKDEV_WRITE_FAIL;
3293 }
3294#endif
3295
3296 /* calculate and assign checksum */
3297 mrr_info.emi_checksum = crc16((u8*)emi_settings, sizeof(emi_settings));
3298 assign_checksum_for_mdl_data(&mrr_info);
3299
3300 ret = bio_write(bootdev, (u8*)&mrr_info, ((unsigned long) &datap->mrr_info), sizeof(mrr_info));
3301 if (ret != 0) {
3302 dramc_crit("[dramc] bio_write failed\n");
3303 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
3304 return -ERR_BLKDEV_WRITE_FAIL;
3305 }
3306
3307 return 0;
3308}
3309#endif
3310
3311int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
3312{
3313 int i, ret;
3314 bdev_t *bootdev = NULL;
3315 DRAM_CALIBRATION_HEADER_T hdr;
3316 DRAM_CALIBRATION_SHU_DATA_T shu_data;
3317 DRAM_CALIBRATION_DATA_T *datap = NULL;
3318 unsigned char *ch;
3319
3320 if (dram_offline_data_flags)
3321 goto exit;
3322
3323 if (offLine_SaveData == NULL) {
3324 dramc_crit("[dramc] offLine_SaveData == NULL, skip\n");
3325 dram_offline_data_flags = ERR_NULL_POINTER;
3326 goto exit;
3327 }
3328
3329 bootdev = bio_open_by_label("bootpara");
3330 if (!bootdev) {
3331 bootdev = bio_open("bootpara");
3332 if (!bootdev) {
3333 dramc_crit("bootpara is not exist.");
3334 goto exit;
3335 }
3336 }
3337
3338 if (!part_dram_data_addr) {
3339 dram_offline_data_flags = ERR_BLKDEV_NO_PART;
3340 goto exit;
3341 }
3342
3343 ret = bio_read(bootdev, (u8*)&hdr, 0, sizeof(hdr));
3344 if (ret != 0) {
3345 dramc_crit("[dramc] bio_read %s failed\n", "hdr");
3346 dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
3347 goto exit;
3348 }
3349
3350 /* check preloader version */
3351 if (hdr.pl_version != PL_VERSION) {
3352 /* current preloader version does not match the calibration hdr in storage -> erase the partition */
3353 dramc_crit("[dramc] PL_VERSION is updated, erase the DRAM shu_data\n");
3354
3355 shu_data.checksum = 0;
3356
3357 /* clear each shuffle */
3358 for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
3359 ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
3360 if (ret != 0) {
3361 dramc_crit("[dramc] bio_write failed\n");
3362 dram_offline_data_flags = ERR_BLKDEV_WRITE_FAIL;
3363 goto exit;
3364 }
3365 }
3366
3367 dram_offline_data_flags = ERR_PL_UPDATED;
3368 goto exit;
3369 }
3370
3371 /* check magic number */
3372 if (hdr.magic_number != DRAM_CALIBRATION_DATA_MAGIC) {
3373 dramc_crit("[dramc] magic number mismatch\n");
3374 dram_offline_data_flags = ERR_MAGIC_NUMBER;
3375 goto exit;
3376 }
3377
3378 ret = bio_read(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[shuffle]), sizeof(shu_data));
3379 if (ret != 0) {
3380 dramc_crit("[dramc] bio_read %s failed\n", "data");
3381 dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
3382 goto exit;
3383 }
3384
3385 /* check checksum */
3386 if (check_checksum_for_dram_data(&shu_data) != 1) {
3387 dramc_crit("[dramc] checksum failed\n");
3388 dram_offline_data_flags = ERR_CHECKSUM;
3389 goto exit;
3390 }
3391
3392 /* copy the data stored in storage to the data structure for calibration */
3393 memcpy(offLine_SaveData, &(shu_data.calibration_data), sizeof(*offLine_SaveData));
3394
3395exit:
3396 if (dram_offline_data_flags)
3397 SET_DRAM_STORAGE_API_ERR(dram_offline_data_flags, DRAM_STORAGE_API_READ);
3398
3399 return 0 - dram_offline_data_flags;
3400}
3401
3402int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
3403{
3404 int ret;
3405 bdev_t *bootdev = NULL;
3406 DRAM_CALIBRATION_HEADER_T hdr;
3407 DRAM_CALIBRATION_SHU_DATA_T shu_data;
3408 DRAM_CALIBRATION_DATA_T *datap = NULL;
3409
3410 if (offLine_SaveData == NULL) {
3411 dramc_crit("[dramc] offLine_SaveData == NULL, skip\n");
3412 SET_DRAM_STORAGE_API_ERR(ERR_NULL_POINTER, DRAM_STORAGE_API_WRITE);
3413 return -ERR_NULL_POINTER;
3414 }
3415
3416 bootdev = bio_open_by_label("bootpara");
3417 if (!bootdev) {
3418 bootdev = bio_open("bootpara");
3419 if (!bootdev) {
3420 dramc_crit("bootpara is not exist.");
3421 return -ERR_BLKDEV_NO_PART;
3422 }
3423 }
3424
3425 memcpy(&(shu_data.calibration_data), offLine_SaveData, sizeof(*offLine_SaveData));
3426
3427 /* assign PL version */
3428 hdr.pl_version = PL_VERSION;
3429
3430 /* assign magic number */
3431 hdr.magic_number = DRAM_CALIBRATION_DATA_MAGIC;
3432
3433 /* assign api error code */
3434 hdr.calib_err_code = g_dram_storage_api_err_code;
3435
3436 ret = bio_write(bootdev, (u8*)&hdr, 0, sizeof(hdr));
3437 if (ret != 0) {
3438 dramc_crit("[dramc] bio_write failed\n");
3439 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
3440 return -ERR_BLKDEV_WRITE_FAIL;
3441 }
3442
3443 /* calculate and assign checksum */
3444 assign_checksum_for_dram_data(&shu_data);
3445
3446 ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[shuffle]), sizeof(shu_data));
3447 if (ret != 0) {
3448 dramc_crit("[dramc] bio_write failed\n");
3449 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
3450 return -ERR_BLKDEV_WRITE_FAIL;
3451 }
3452
3453 return 0;
3454}
3455
3456int clean_dram_calibration_data(void)
3457{
3458 int i, ret;
3459 bdev_t *bootdev = NULL;
3460 DRAM_CALIBRATION_HEADER_T hdr;
3461 DRAM_CALIBRATION_SHU_DATA_T shu_data;
3462 DRAM_CALIBRATION_DATA_T *datap = NULL;
3463
3464 bootdev = bio_open_by_label("bootpara");
3465 if (!bootdev) {
3466 bootdev = bio_open("bootpara");
3467 if (!bootdev) {
3468 dramc_crit("bootpara is not exist.");
3469 return -ERR_BLKDEV_NO_PART;
3470 }
3471 }
3472
3473 memset(&hdr, 0, sizeof(hdr));
3474
3475 ret = bio_write(bootdev, (u8*)&hdr, 0, sizeof(hdr));
3476 if (ret != 0) {
3477 dramc_crit("[dramc] bio_write failed\n");
3478 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_CLEAN);
3479 return -ERR_BLKDEV_WRITE_FAIL;
3480 }
3481
3482 shu_data.checksum = 0;
3483
3484 /* clear each shuffle */
3485 for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
3486 ret = bio_write(bootdev, (u8*)&shu_data, ((unsigned long) &datap->data[i]), sizeof(shu_data));
3487 if (ret != 0) {
3488 dramc_crit("[dramc] bio_write failed\n");
3489 SET_DRAM_STORAGE_API_ERR(ERR_BLKDEV_WRITE_FAIL, DRAM_STORAGE_API_WRITE);
3490 return -ERR_BLKDEV_WRITE_FAIL;
3491 }
3492 }
3493
3494 return 0;
3495}
3496
3497#else
3498
3499DRAM_CALIBRATION_DATA_T dram_data; // using global variable to avoid stack overflow
3500
3501int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
3502{
3503 return 0;
3504}
3505
3506int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
3507{
3508 return 0;
3509}
3510
3511int clean_dram_calibration_data(void)
3512{
3513 return;
3514}
3515#endif
3516
3517
3518void set_err_code_for_storage_api(void)
3519{
3520#ifdef LAST_DRAMC
3521 last_dramc_info_ptr->storage_api_err_flag = g_dram_storage_api_err_code;
3522 dsb();
3523#endif
3524}
3525
3526#endif
3527
3528#if __ETT__
3529#define FHCTL_HP_EN (FHCTL_BASE + 0x004)
3530#define MPLL_FHCTL_CFG (FHCTL_BASE + 0x0A0)
3531#define MPLL_FHCTL_LMT (FHCTL_BASE + 0x0A4)
3532#define MPLL_FHCTL_DDS (FHCTL_BASE + 0x0A8)
3533#define MPLL_CON1 (APMIXED_BASE + 0x2A4)
3534#define MPLL_ID 5
3535#define SETTING_DF 9
3536#define SETTING_DT 0
3537#define SETTING_LOWBND 1 // ssc ratio
3538#define PERCENT_TO_DDSLMT(dDS, pERCENT_M10) (((dDS * pERCENT_M10) >> 5) / 100)
3539
3540void en_mpll_ssc(void)
3541{
3542 unsigned int reg_val;
3543
3544 *((volatile unsigned int *)0x1000CE08) = 0x1FF;
3545 *((volatile unsigned int *)0x1000CE0C) = 0x1FF;
3546
3547 reg_val = *((volatile unsigned int *)MPLL_FHCTL_CFG);
3548 reg_val &= ~0xFF0000;
3549 *((volatile unsigned int *)MPLL_FHCTL_CFG) = reg_val | (SETTING_DF << 20) | (SETTING_DT << 16);
3550
3551 reg_val = (*((volatile unsigned int *)MPLL_CON1) & 0x3FFFFF) | 0x80000000;
3552 *((volatile unsigned int *)MPLL_FHCTL_DDS) = reg_val;
3553
3554 reg_val &= 0x3FFFFF;
3555 reg_val = PERCENT_TO_DDSLMT(reg_val, SETTING_LOWBND) << 16;
3556 *((volatile unsigned int *)MPLL_FHCTL_LMT) = reg_val;
3557
3558 *((volatile unsigned int *)FHCTL_HP_EN) |= (1 << MPLL_ID);
3559 dsb();
3560 *((volatile unsigned int *)MPLL_FHCTL_CFG) |= 0x2;
3561 dsb();
3562 *((volatile unsigned int *)MPLL_FHCTL_CFG) |= 0x1;
3563 dsb();
3564}
3565
3566void dis_mpll_ssc(void)
3567{
3568 *((volatile unsigned int *)MPLL_FHCTL_CFG) &= ~0x2;
3569 dsb();
3570 *((volatile unsigned int *)MPLL_FHCTL_CFG) &= ~0x1;
3571 dsb();
3572 *((volatile unsigned int *)FHCTL_HP_EN) &= ~(1 << MPLL_ID);
3573 dsb();
3574}
3575#endif