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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / dramk_2731 / include / emi.h
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein is
5 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
6 * the prior written permission of MediaTek inc. and/or its licensors, any
7 * reproduction, modification, use or disclosure of MediaTek Software, and
8 * information contained herein, in whole or in part, shall be strictly
9 * prohibited.
10 *
11 * MediaTek Inc. (C) 2010. All rights reserved.
12 *
13 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
14 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
15 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
16 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
17 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
19 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
20 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
21 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
22 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
23 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
24 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
25 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
26 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
27 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
28 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
29 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
30 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
31 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
32 *
33 * The following software/firmware and/or related documentation ("Media Tek
34 * Software") have been modified by MediaTek Inc. All revisions are subject to
35 * any receiver's applicable license agreements with MediaTek Inc.
36 */
37
38#ifndef MT_EMI_H
39#define MT_EMI_H
40#ifdef FLASH_TOOL_DA
41 #include "sw_types.h"
42#else
43 #include <platform/mt_typedefs.h>
44#endif
45#include "dramc_common.h"
46#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
47#if !__ETT__ && (FOR_DV_SIMULATION_USED == 0)
48//#include "boot_device.h"
49#endif
50#endif
51
52#if !__ETT__
53#if (FOR_DV_SIMULATION_USED==0)
54#if ARCH_ARM64
55#define DRAM_BASE (KERNEL_ASPACE_BASE+0x40000000ULL)
56#else
57#define DRAM_BASE (0x40000000)
58#endif
59#define DDR_BASE DRAM_BASE
60#define DDR_RESERVE_MODE
61#ifdef PMIC_CHIP_MT6389
62#define COMBO_MCP
63#endif
64#define LAST_DRAMC
65#define DRAM_ADAPTIVE
66#if defined(DRAM_ADAPTIVE) || defined(MTK_BUILD_USER_LOAD)
67#undef COMBO_MCP
68#endif
69//#define LAST_EMI
70#endif
71#endif
72
73#if __ETT__
74#define dramc_crit printf
75#define dramc_debug printf
76#elif __FLASH_TOOL_DA__
77#define dramc_crit LOGD
78#define dramc_debug LOGD
79#else
80#define dramc_crit printf
81#define dramc_debug printf
82#endif
83
84#if (FOR_DV_SIMULATION_USED==1 || SW_CHANGE_FOR_SIMULATION==1)
85typedef unsigned long long u64;
86#endif
87
88#define MAX_CH 2
89#define MAX_RK 2
90
91int get_dram_channel_nr(void);
92int get_dram_rank_nr(void);
93void get_dram_rank_size(u64 dram_rank_size[]);
94void reserve_dramc_dummy_read(void);
95unsigned int get_dram_mr(unsigned int index);
96
97typedef struct {
98 unsigned int dram_type;
99 unsigned int ch_num;
100 unsigned int rk_num;
101 unsigned int bank_width[MAX_RK];
102 unsigned int row_width[MAX_RK];
103 unsigned int col_width[MAX_RK];
104 u64 rank_size[MAX_RK];
105} EMI_INFO_T;
106
107typedef struct _AC_TIMING_EXTERNAL_T
108{
109 // U 00
110 U32 AC_TIME_EMI_FREQUENCY :16;
111 U32 AC_TIME_EMI_TRAS :8;
112 U32 AC_TIME_EMI_TRP :8;
113
114 // U 01
115 U32 AC_TIME_EMI_TRPAB :8;
116 U32 AC_TIME_EMI_TRC :8;
117 U32 AC_TIME_EMI_TRFC :8;
118 U32 AC_TIME_EMI_TRFCPB :8;
119
120 // U 02
121 U32 AC_TIME_EMI_TXP :8;
122 U32 AC_TIME_EMI_TRTP :8;
123 U32 AC_TIME_EMI_TRCD :8;
124 U32 AC_TIME_EMI_TWR :8;
125
126 // U 03
127 U32 AC_TIME_EMI_TWTR :8;
128 U32 AC_TIME_EMI_TRRD :8;
129 U32 AC_TIME_EMI_TFAW :8;
130 U32 AC_TIME_EMI_TRTW_ODT_OFF :4;
131 U32 AC_TIME_EMI_TRTW_ODT_ON :4;
132
133 // U 04
134 U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0)
135 U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1)
136 U32 AC_TIME_EMI_TXREFCNT :8;
137 U32 AC_TIME_EMI_TZQCS :8;
138
139 // U 05
140 U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olympus new
141 U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olympus new
142 U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olympus new
143 U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olympus new
144
145 // U 06
146 // Byte0
147 U32 AC_TIME_EMI_TRAS_05T :2;
148 U32 AC_TIME_EMI_TRP_05T :2;
149 U32 AC_TIME_EMI_TRPAB_05T :2;
150 U32 AC_TIME_EMI_TRC_05T :2;
151 // Byte1
152 U32 AC_TIME_EMI_TRFC_05T :2;
153 U32 AC_TIME_EMI_TRFCPB_05T :2;
154 U32 AC_TIME_EMI_TXP_05T :2;
155 U32 AC_TIME_EMI_TRTP_05T :2;
156 // Byte2
157 U32 AC_TIME_EMI_TRCD_05T :2;
158 U32 AC_TIME_EMI_TWR_05T :2;
159 U32 AC_TIME_EMI_TWTR_05T :2; // Olympus modified
160 U32 AC_TIME_EMI_TRRD_05T :2;
161 // Byte3
162 U32 AC_TIME_EMI_TFAW_05T :2;
163 U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2;
164 U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2;
165 U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olympus new
166
167 // U 07
168 // Byte0
169 U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olympus new
170 U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olympus and Elbrus
171 U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olympus and Elbrus
172
173
174}AC_TIMING_EXTERNAL_T;
175
176
177#ifdef DRAM_ADAPTIVE
178typedef struct
179{
180 unsigned int type; /* 0x0000 : Invalid
181 0x0001 : Discrete DDR1
182 0x0002 : Discrete LPDDR2
183 0x0003 : Discrete LPDDR3
184 0x0004 : Discrete PCDDR3
185 0x0005 : Discrete LPDDR4
186 0x0006 : Discrete LPDR4X
187 0x0101 : MCP(NAND+DDR1)
188 0x0102 : MCP(NAND+LPDDR2)
189 0x0103 : MCP(NAND+LPDDR3)
190 0x0104 : MCP(NAND+PCDDR3)
191 0x0201 : MCP(eMMC+DDR1)
192 0x0202 : MCP(eMMC+LPDDR2)
193 0x0203 : MCP(eMMC+LPDDR3)
194 0x0204 : MCP(eMMC+PCDDR3)
195 0x0205 : MCP(eMMC+LPDDR4)
196 0x0206 : MCP(eMMC+LPDR4X) */
197 unsigned int EMI_CONA_VAL;
198 unsigned int EMI_CONH_VAL;
199 unsigned int EMI_CONF_VAL;
200 union {
201 unsigned int DRAMC_ACTIME_UNION[8];
202 AC_TIMING_EXTERNAL_T AcTimeEMI;
203 };
204 unsigned int CHN0_EMI_CONA_VAL;
205 unsigned int CHN1_EMI_CONA_VAL;
206 u64 DRAM_RANK_SIZE[4];
207 unsigned int dram_cbt_mode_extern;
208 unsigned int iLPDDR3_MODE_REG_5;
209 unsigned int PIN_MUX_TYPE;
210} EMI_SETTINGS;
211#else
212typedef struct
213{
214 unsigned int sub_version; // sub_version: 0x1 for new version
215 unsigned int type; /* 0x0000 : Invalid
216 0x0001 : Discrete DDR1
217 0x0002 : Discrete LPDDR2
218 0x0003 : Discrete LPDDR3
219 0x0004 : Discrete PCDDR3
220 0x0005 : Discrete LPDDR4
221 0x0006 : Discrete LPDR4X
222 0x0101 : MCP(NAND+DDR1)
223 0x0102 : MCP(NAND+LPDDR2)
224 0x0103 : MCP(NAND+LPDDR3)
225 0x0104 : MCP(NAND+PCDDR3)
226 0x0201 : MCP(eMMC+DDR1)
227 0x0202 : MCP(eMMC+LPDDR2)
228 0x0203 : MCP(eMMC+LPDDR3)
229 0x0204 : MCP(eMMC+PCDDR3)
230 0x0205 : MCP(eMMC+LPDDR4)
231 0x0206 : MCP(eMMC+LPDR4X)
232 */
233 unsigned int id_length; // EMMC and NAND ID checking length
234 unsigned int fw_id_length; // FW ID checking length
235 unsigned char ID[16];
236 unsigned char fw_id[8]; // To save fw id
237 unsigned int EMI_CONA_VAL; //@0x3000
238 unsigned int EMI_CONH_VAL;
239
240 union {
241 unsigned int DRAMC_ACTIME_UNION[8];
242 AC_TIMING_EXTERNAL_T AcTimeEMI;
243 };
244
245 u64 DRAM_RANK_SIZE[4];
246 unsigned int EMI_CONF_VAL;
247 unsigned int CHN0_EMI_CONA_VAL;
248 unsigned int CHN1_EMI_CONA_VAL;
249 /* Single field to store LP4 dram type (normal, byte, mixed) */
250 unsigned int dram_cbt_mode_extern;
251 unsigned int reserved[6];
252
253#if 0
254 union
255 {
256 struct
257 {
258 int iLPDDR2_MODE_REG_1;
259 int iLPDDR2_MODE_REG_2;
260 int iLPDDR2_MODE_REG_3;
261 int iLPDDR2_MODE_REG_5;
262 int iLPDDR2_MODE_REG_10;
263 int iLPDDR2_MODE_REG_63;
264 };
265 struct
266 {
267 int iDDR1_MODE_REG;
268 int iDDR1_EXT_MODE_REG;
269 };
270 struct
271 {
272 int iPCDDR3_MODE_REG0;
273 int iPCDDR3_MODE_REG1;
274 int iPCDDR3_MODE_REG2;
275 int iPCDDR3_MODE_REG3;
276 };
277 struct
278 {
279 int iLPDDR3_MODE_REG_1;
280 int iLPDDR3_MODE_REG_2;
281 int iLPDDR3_MODE_REG_3;
282 int iLPDDR3_MODE_REG_5;
283 int iLPDDR3_MODE_REG_10;
284 int iLPDDR3_MODE_REG_63;
285 };
286 };
287#else
288 unsigned int iLPDDR3_MODE_REG_5;
289#endif
290 unsigned int PIN_MUX_TYPE;
291} EMI_SETTINGS;
292#endif
293
294//typedef EMI_SETTINGS_v15 EMI_SETTINGS;
295#if (FOR_DV_SIMULATION_USED==0)
296void setup_dramc_voltage_by_pmic(void);
297void switch_dramc_voltage_to_auto_mode(void);
298unsigned int mt_get_dram_type_from_hw_trap(void);
299unsigned int dramc_set_vcore_voltage(unsigned int vcore);
300unsigned int dramc_get_vcore_voltage(void);
301unsigned int dramc_set_vdd1_voltage(unsigned int ddr_type, unsigned int vdd1);
302unsigned int dramc_get_vdd1_voltage(void);
303unsigned int dramc_set_vdd2_voltage(unsigned int ddr_type, unsigned int vdd2);
304unsigned int dramc_get_vdd2_voltage(unsigned int ddr_type);
305unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq);
306unsigned int dramc_get_vddq_voltage(unsigned int ddr_type);
307#if __ETT__
308void hqa_set_voltage_by_freq(DRAMC_CTX_T *p, unsigned int *vio18, unsigned int *vcore, unsigned int *vdram, unsigned int *vddq);
309#endif
310#endif
311
312extern int num_of_emi_records;
313extern int emi_setting_index;
314extern EMI_SETTINGS emi_settings[];
315#ifdef DRAM_ADAPTIVE
316extern EMI_SETTINGS g_default_emi_setting;
317#else
318extern EMI_SETTINGS default_emi_setting;
319#endif
320extern EMI_SETTINGS emi_setting_default_lpddr3;
321extern EMI_SETTINGS emi_setting_default_lpddr4;
322
323#ifdef DRAM_ADAPTIVE
324static inline EMI_SETTINGS *get_emi_setting(void)
325{
326 return &g_default_emi_setting;
327}
328#else
329static inline EMI_SETTINGS *get_emi_setting(void)
330{
331 EMI_SETTINGS *emi_set = &default_emi_setting;
332#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
333 if(emi_setting_index != -1)
334 emi_set = &emi_settings[emi_setting_index];
335#endif
336 return emi_set;
337}
338#endif
339
340int mt_get_dram_type(void);
341
342#include "x_hal_io.h"
343
344void init_ta2_single_channel(unsigned int);
345#ifdef LAST_DRAMC
346#define LAST_DRAMC_MAGIC_PATTERN 0x19870611
347static void update_last_dramc_info(void);
348void update_last_dramc_k_voltage(DRAMC_CTX_T *p, unsigned int voltage);
349void init_ta2_all_channel(void);
350typedef struct {
351 unsigned int ta2_result_magic;
352 unsigned int ta2_result_last;
353 unsigned int ta2_result_past;
354 unsigned int ta2_result_checksum;
355 unsigned int reboot_count;
356 volatile unsigned int last_fatal_err_flag;
357 volatile unsigned int fatal_err_flag;
358 volatile unsigned int storage_api_err_flag;
359 volatile unsigned int last_gating_err[2][2]; // [channel][rank]
360 volatile unsigned int gating_err[2][2]; // [channel][rank]
361 unsigned int k_voltage[DRAM_DFS_SHUFFLE_MAX];
362} LAST_DRAMC_INFO_T;
363#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T
364
365#define OFFSET_DRAM_FATAL_ERR (31)
366#define OFFSET_DRAM_TA2_ERR (23)
367#define OFFSET_DRAM_GATING_ERR (7)
368#define OFFSET_CPU_RW_ERR (5)
369#define OFFSET_DDR_RSV_MODE_FLOW (4)
370#define OFFSET_DDR_RSV_MODE_ERR (3)
371#define OFFSET_EMI_DCS_ERR (2)
372#define OFFSET_DVFSRC_ERR (1)
373#define OFFSET_DRS_ERR (0)
374
375#define ERR_DRAM_TA2_RK0 (1 << 0)
376#define ERR_DRAM_TA2_RK1 (1 << 1)
377
378#define ERR_DRAM_GATING_RK0_R (1 << 0)
379#define ERR_DRAM_GATING_RK0_F (1 << 1)
380#define ERR_DRAM_GATING_RK1_R (1 << 2)
381#define ERR_DRAM_GATING_RK1_F (1 << 3)
382
383#define ERR_CPU_RW_RK0 (1 << 0)
384#define ERR_CPU_RW_RK1 (1 << 1)
385
386/* 0x1f -> bit[4:0] is for DDR reserve mode */
387#define DDR_RSV_MODE_ERR_MASK (0x1f)
388
389unsigned int check_last_dram_fatal_exception(void);
390unsigned int check_dram_fatal_exception(void);
391void set_err_code_for_storage_api(void);
392void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code);
393void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code);
394void dram_fatal_set_cpu_rw_err(unsigned int err_code);
395void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code);
396
397void dram_fatal_backup_stberr(void);
398void dram_fatal_init_stberr(void);
399void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
400
401extern unsigned int check_gating_err_in_dramc_latch(void);
402extern unsigned int check_gating_error(void);
403extern void dram_fatal_exception_detection_start(void);
404extern void dram_fatal_exception_detection_end(void);
405
406#define dram_fatal_set_cpu_rw_err(err_code)\
407 do {\
408 dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\
409 } while(0)
410
411#define dram_fatal_set_ddr_rsv_mode_err()\
412 do {\
413 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\
414 } while(0)
415
416#define dram_fatal_set_emi_dcs_err()\
417 do {\
418 dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\
419 } while(0)
420
421#define dram_fatal_set_dvfsrc_err()\
422 do {\
423 dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\
424 } while(0)
425
426#define dram_fatal_set_drs_err()\
427 do {\
428 dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\
429 } while(0)
430
431#define dram_fatal_set_ddr_rsv_mode_flow()\
432 do {\
433 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
434 } while(0)
435
436#endif //LAST_DRAMC
437
438//================================================
439//=============pmic related api for ETT HQA test ==============
440//================================================
441#if __ETT__
442#define DRAM_HQA
443#endif
444
445#define MAX_VCORE 1196875
446#define MAX_VDRAM 1309375
447#define MAX_VDDQ 1190625
448
449#define UNIT_VIO18 10000
450#define UNIT_VCORE 6250
451#define UNIT_VDRAM 10000
452#define UNIT_VDDQ 10000
453
454#define HQA_VIO18_HV 1950000
455#define HQA_VIO18_NV 1800000
456#define HQA_VIO18_LV 1730000
457
458#define HQA_VIO18_HV 1950000
459#define HQA_VCORE_HV_LP4_KOPP0 843750
460#define HQA_VCORE_HV_LP4_KOPP1 843750
461#define HQA_VDRAM_HV_LP4 1170000
462#define HQA_VDDQ_HV_LP4 650000
463
464#define HQA_VIO18_NV 1800000
465#define HQA_VCORE_NV_LP4_KOPP0 800000
466#define HQA_VCORE_NV_LP4_KOPP1 800000
467#define HQA_VDRAM_NV_LP4 1120000
468#define HQA_VDDQ_NV_LP4 600000
469
470#define HQA_VIO18_LV 1730000
471#define HQA_VCORE_LV_LP4_KOPP0 756250
472#define HQA_VCORE_LV_LP4_KOPP1 756250
473#define HQA_VDRAM_LV_LP4 1060000
474#define HQA_VDDQ_LV_LP4 570000
475
476#define HQA_VCORE_HV_LP2_KOPP0 843750
477#define HQA_VCORE_HV_LP2_KOPP1 787500
478#define HQA_VDRAM_HV_LP2 1300000
479
480#define HQA_VCORE_NV_LP2_KOPP0 800000
481#define HQA_VCORE_NV_LP2_KOPP1 750000 //750000
482#define HQA_VDRAM_NV_LP2 1220000
483
484#define HQA_VCORE_LV_LP2_KOPP0 756250
485#define HQA_VCORE_LV_LP2_KOPP1 712500
486#define HQA_VDRAM_LV_LP2 1160000
487
488#define _SEL_PREFIX_OPP(type, vol, dtype, opp) HQA_##type##_##vol##_##dtype##_##opp
489#define _SEL_PREFIX(type, vol, dtype) HQA_##type##_##vol##_##dtype
490#define _SEL_VIO18(vol) HQA_VIO18_##vol
491
492#define STD_VIO18 _SEL_VIO18(NV)
493#define STD_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, NV, dtype, opp)
494#define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM, NV, dtype)
495#define STD_VDDQ _SEL_PREFIX(VDDQ, NV, LP4)
496
497#ifdef DRAM_HQA
498
499//#define HVCORE_HVDRAM
500#define NVCORE_NVDRAM
501//#define LVCORE_LVDRAM
502//#define HVCORE_LVDRAM
503//#define LVCORE_HVDRAM
504
505#if defined(HVCORE_HVDRAM)
506 #define HQA_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, HV, dtype, opp)
507 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM, HV, dtype)
508 #define HQA_VDDQ _SEL_PREFIX(VDDQ, HV, LP4)
509 #define HQA_VIO18 _SEL_VIO18(HV)
510#elif defined(NVCORE_NVDRAM)
511 #define HQA_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, NV, dtype, opp)
512 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM, NV, dtype)
513 #define HQA_VDDQ _SEL_PREFIX(VDDQ, NV, LP4)
514 #define HQA_VIO18 _SEL_VIO18(NV)
515#elif defined(LVCORE_LVDRAM)
516 #define HQA_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, LV, dtype, opp)
517 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM, LV, dtype)
518 #define HQA_VDDQ _SEL_PREFIX(VDDQ, LV, LP4)
519 #define HQA_VIO18 _SEL_VIO18(LV)
520#elif defined(HVCORE_LVDRAM)
521 #define HQA_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, HV, dtype, opp)
522 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM, LV, dtype)
523 #define HQA_VDDQ _SEL_PREFIX(VDDQ, LV, LP4)
524 #define HQA_VIO18 _SEL_VIO18(LV)
525#elif defined(LVCORE_HVDRAM)
526 #define HQA_VCORE(dtype, opp) _SEL_PREFIX_OPP(VCORE, LV, dtype, opp)
527 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM, HV, dtype)
528 #define HQA_VDDQ _SEL_PREFIX(VDDQ, HV, LP4)
529 #define HQA_VIO18 _SEL_VIO18(HV)
530#else
531 #error "Please set HQA voltage type"
532#endif
533
534#define SEL_PREFIX_VCORE(dtype, opp) HQA_VCORE(dtype, opp)
535#define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype)
536#define SEL_PREFIX_VDDQ HQA_VDDQ
537#else
538#if !__ETT__
539//#define VCORE_BIN
540#endif
541#define SEL_PREFIX_VCORE(dtype, opp) STD_VCORE(dtype, opp)
542#define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype)
543#define SEL_PREFIX_VDDQ STD_VDDQ
544#endif
545
546#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
547
548#define PART_DRAM_DATA_SIZE 0x100000
549
550#if !__ETT__
551#if !defined(BOOTDEV_UFS) && !defined(BOOTDEV_SDMMC)
552//#error "BOOTDEV_UFS & BOOTDEV_SDMMC not defined"
553#endif
554#endif
555
556#if (CFG_BOOT_DEV == BOOTDEV_UFS)
557#define PART_ID_DRAM_DATA UFS_LU_USER
558#elif (CFG_BOOT_DEV == BOOTDEV_SDMMC)
559#define PART_ID_DRAM_DATA EMMC_PART_USER
560#endif
561
562#define DRAM_CALIBRATION_DATA_MAGIC 0x9502
563
564typedef struct _DRAM_CALIBRATION_HEADER_T
565{
566 u32 pl_version;
567 u16 magic_number;
568 u32 calib_err_code;
569} DRAM_CALIBRATION_HEADER_T;
570
571typedef struct _DRAM_CALIBRATION_MRR_DATA_T
572{
573 u16 checksum;
574 u16 emi_checksum;
575 DRAM_INFO_BY_MRR_T DramInfo;
576} DRAM_CALIBRATION_MRR_DATA_T;
577
578typedef struct _DRAM_CALIBRATION_SHU_DATA_T
579{
580 u16 checksum;
581 SAVE_TIME_FOR_CALIBRATION_T calibration_data;
582} DRAM_CALIBRATION_SHU_DATA_T;
583
584typedef struct _DRAM_CALIBRATION_DATA_T
585{
586 DRAM_CALIBRATION_HEADER_T header;
587 DRAM_CALIBRATION_MRR_DATA_T mrr_info;
588 DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX];
589} DRAM_CALIBRATION_DATA_T;
590
591
592/*
593 * g_dram_storage_api_err_code:
594 * bit[0:3] -> read api
595 * bit[4:7] -> write api
596 * bit[8:11] -> clean api
597 * bit[12:12] -> data formatted due to fatal exception
598 */
599#define ERR_NULL_POINTER (0x1)
600#define ERR_MAGIC_NUMBER (0x2)
601#define ERR_CHECKSUM (0x3)
602#define ERR_PL_UPDATED (0x4)
603#define ERR_BLKDEV_NOT_FOUND (0x5)
604#define ERR_BLKDEV_READ_FAIL (0x6)
605#define ERR_BLKDEV_WRITE_FAIL (0x7)
606#define ERR_BLKDEV_NO_PART (0x8)
607
608#define ERR_DATA_FORMATTED_OFFSET (12)
609
610typedef enum {
611 DRAM_STORAGE_API_READ = 0,
612 DRAM_STORAGE_API_WRITE,
613 DRAM_STORAGE_API_CLEAN,
614} DRAM_STORAGE_API_TPYE;
615
616extern u32 g_dram_storage_api_err_code;
617#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \
618do {\
619 g_dram_storage_api_err_code |= (err_type << (api_type * 4));\
620} while(0)
621
622#define SET_DATA_FORMATTED_STORAGE_API_ERR() \
623do {\
624 g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\
625} while(0)
626
627int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
628int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
629int clean_dram_calibration_data(void);
630
631#define CBT_VREF_OFFSET 2
632#define WRITE_LEVELING_OFFSET 5
633#define GATING_START_OFFSET 0
634#define GATING_PASS_WIN_OFFSET 3
635#define RX_WIN_PERBIT_OFFSET 5
636#define RX_WIN_PERBIT_VREF_OFFSET 4
637#define TX_WIN_PERBIT_OFFSET 5
638#define TX_WIN_PERBIT_VREF_OFFSET 4
639#define RX_DATLAT_OFFSET 1
640#define RX_WIN_HIGH_SPEED_TH 10
641#define RX_WIN_LOW_SPEED_TH 100
642#define TX_WIN_TH 12
643
644#endif
645
646unsigned long long get_dram_size(void);
647
648typedef struct {
649 unsigned long long full_sys_addr;
650 unsigned int addr;
651 unsigned int row;
652 unsigned int col;
653 unsigned char ch;
654 unsigned char rk;
655 unsigned char bk;
656 unsigned char dummy;
657} dram_addr_t;
658
659unsigned int get_dummy_read_addr(dram_addr_t *dram_addr);
660
661#ifdef LAST_EMI
662#define LAST_EMI_MAGIC_PATTERN 0x19870611
663typedef struct {
664 unsigned int decs_magic;
665 unsigned int decs_ctrl;
666 unsigned int decs_dram_type;
667 unsigned int decs_diff_us;
668 unsigned int mbw_buf_l;
669 unsigned int mbw_buf_h;
670} LAST_EMI_INFO_T;
671#define DEF_LAST_EMI LAST_EMI_INFO_T
672
673void reserve_emi_mbw_buf(void);
674#endif
675
676void en_mpll_ssc(void);
677void dis_mpll_ssc(void);
678
679void mt_set_emi(void);
680unsigned int set_emi_before_rank1_mem_test(void);
681
682void print_DBG_info(DRAMC_CTX_T *p);
683void Dump_EMIRegisters(DRAMC_CTX_T *p);
684
685#endif