blob: 73968edd2f9b2e641558f13ccc50f180041325b9 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2015 Brian Swetland
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include <debug.h>
25#include <string.h>
26#include <stdlib.h>
27#include <printf.h>
28#include <reg.h>
29
30#include <platform/lpc43xx-spifi.h>
31
32#define CMD_PAGE_PROGRAM 0x02
33#define CMD_READ_DATA 0x03
34#define CMD_READ_STATUS 0x05
35#define CMD_WRITE_ENABLE 0x06
36#define CMD_SECTOR_ERASE 0x20
37
38static void spifi_write_enable(void) {
39 writel(CMD_FF_SERIAL | CMD_FR_OP | CMD_OPCODE(CMD_WRITE_ENABLE),
40 SPIFI_CMD);
41 while (readl(SPIFI_STAT) & STAT_CMD) ;
42}
43
44static void spifi_wait_busy(void) {
45 while (readl(SPIFI_STAT) & STAT_CMD) ;
46 writel(CMD_POLLBIT(0) | CMD_POLLCLR | CMD_POLL |
47 CMD_FF_SERIAL | CMD_FR_OP | CMD_OPCODE(CMD_READ_STATUS),
48 SPIFI_CMD);
49 while (readl(SPIFI_STAT) & STAT_CMD) ;
50 // discard matching status byte from fifo
51 readb(SPIFI_DATA);
52}
53
54void spifi_page_program(u32 addr, u32 *ptr, u32 count) {
55 spifi_write_enable();
56 writel(addr, SPIFI_ADDR);
57 writel(CMD_DATALEN(count * 4) | CMD_FF_SERIAL | CMD_FR_OP_3B |
58 CMD_DOUT | CMD_OPCODE(CMD_PAGE_PROGRAM), SPIFI_CMD);
59 while (count-- > 0) {
60 writel(*ptr++, SPIFI_DATA);
61 }
62 spifi_wait_busy();
63}
64
65void spifi_sector_erase(u32 addr) {
66 spifi_write_enable();
67 writel(addr, SPIFI_ADDR);
68 writel(CMD_FF_SERIAL | CMD_FR_OP_3B | CMD_OPCODE(CMD_SECTOR_ERASE),
69 SPIFI_CMD);
70 spifi_wait_busy();
71}
72
73int spifi_verify_erased(u32 addr, u32 count) {
74 int err = 0;
75 writel(addr, SPIFI_ADDR);
76 writel(CMD_DATALEN(count * 4) | CMD_FF_SERIAL | CMD_FR_OP_3B |
77 CMD_OPCODE(CMD_READ_DATA), SPIFI_CMD);
78 while (count-- > 0) {
79 if (readl(SPIFI_DATA) != 0xFFFFFFFF) err = -1;
80 }
81 while (readl(SPIFI_STAT) & STAT_CMD) ;
82 return err;
83}
84
85int spifi_verify_page(u32 addr, u32 *ptr) {
86 int count = 256 / 4;
87 int err = 0;
88 writel(addr, SPIFI_ADDR);
89 writel(CMD_DATALEN(count * 4) | CMD_FF_SERIAL | CMD_FR_OP_3B |
90 CMD_OPCODE(CMD_READ_DATA), SPIFI_CMD);
91 while (count-- > 0) {
92 if (readl(SPIFI_DATA) != *ptr++) err = -1;
93 }
94 while (readl(SPIFI_STAT) & STAT_CMD) ;
95 return err;
96}
97
98// at reset-stop, all clocks are running from 12MHz internal osc
99// todo: run SPIFI_CLK at a much higher rate
100// todo: use 4bit modes
101void spifi_init(void) {
102 // reset spifi controller
103 writel(STAT_RESET, SPIFI_STAT);
104 while (readl(SPIFI_STAT) & STAT_RESET) ;
105 writel(0xFFFFF, SPIFI_CTRL);
106}
107