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rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2015 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <asm.h>
24#include <arch/mips.h>
25
26.section ".text.vectab"
27FUNCTION(vectab)
28.org 0
29_tlb_refill:
30 b .
31
32.macro iframe_save
33 .set push
34 .set noat
35 addiu $sp, -88
36
37 /* save all the non temporary registers */
38 sw $at, 0($sp)
39 sw $v0, 4($sp)
40 sw $v1, 8($sp)
41 sw $a0, 12($sp)
42 sw $a1, 16($sp)
43 sw $a2, 20($sp)
44 sw $a3, 24($sp)
45 sw $t0, 28($sp)
46 sw $t1, 32($sp)
47 sw $t2, 36($sp)
48 sw $t3, 40($sp)
49 sw $t4, 44($sp)
50 sw $t5, 48($sp)
51 sw $t6, 52($sp)
52 sw $t7, 56($sp)
53 sw $t8, 60($sp)
54 sw $t9, 64($sp)
55 sw $gp, 68($sp)
56 sw $ra, 72($sp)
57
58 /* save the control registers */
59 mfc0 $at, $12 /* status */
60 sw $at, 76($sp)
61 mfc0 $at, $13 /* cause */
62 sw $at, 80($sp)
63 mfc0 $at, $14 /* epc */
64 sw $at, 84($sp)
65
66 .set pop
67.endm
68
69.macro iframe_restore
70 .set push
71 .set noat
72
73 /* restore the temporary registers */
74 lw $at, 0($sp)
75 lw $v0, 4($sp)
76 lw $v1, 8($sp)
77 lw $a0, 12($sp)
78 lw $a1, 16($sp)
79 lw $a2, 20($sp)
80 lw $a3, 24($sp)
81 lw $t0, 28($sp)
82 lw $t1, 32($sp)
83 lw $t2, 36($sp)
84 lw $t3, 40($sp)
85 lw $t4, 44($sp)
86 lw $t5, 48($sp)
87 lw $t6, 52($sp)
88 lw $t7, 56($sp)
89 lw $t8, 60($sp)
90 lw $t9, 64($sp)
91 lw $gp, 68($sp)
92 lw $ra, 72($sp)
93
94 /* restore the control registers */
95 lw $k0, 76($sp)
96 mtc0 $k0, $12 /* status */
97 lw $k0, 80($sp)
98 mtc0 $k0, $13 /* cause */
99 lw $k0, 84($sp)
100 mtc0 $k0, $14 /* epc */
101
102 addiu $sp, 88
103 .set pop
104.endm
105
106/* compatibility mode irq/syscall/general exception */
107.org 0x180
108_irq:
109 la $k0, mips_gen_exception
110 li $k1, 0
111 b shared_irq_save_return
112
113/* vectored base */
114.macro vectored_irq, num
115.org 0x200 + VECTORED_OFFSET_SHIFT * \num
116_vectored_irq\num:
117 la $k0, mips_irq
118 li $k1, \num
119 b shared_irq_save_return
120 b .
121.endm
122
123vectored_irq 0
124vectored_irq 1
125vectored_irq 2
126vectored_irq 3
127vectored_irq 4
128vectored_irq 5
129vectored_irq 6
130vectored_irq 7
131vectored_irq 8
132vectored_irq 9
133
134/* branched to from above, k0 holds address to call, k1 holds arg to function */
135shared_irq_save_return:
136 iframe_save
137
138 move $a0, $sp
139 move $a1, $k1
140 jal $k0
141
142 iframe_restore
143
144 eret
145