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rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2019 MediaTek Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include <debug.h>
25#include <kernel/thread.h>
26#include <platform/interrupts.h>
27#include <platform/mt_reg_base.h>
28#include <platform/mt_irq.h>
29#include <platform/reg_utils.h>
30
31/* set for mt_gic */
32void mt_irq_set_polarity(unsigned int irq, unsigned int polarity)
33{
34 unsigned int offset;
35 unsigned int reg_index;
36 unsigned int value;
37
38 /* peripheral device's IRQ line is using GIC's SPI, and line ID >= GIC_PRIVATE_SIGNALS */
39 if (irq < GIC_PRIVATE_SIGNALS) {
40 dprintf(SPEW, "The Interrupt ID < 32, please check!\n");
41 return;
42 }
43
44 offset = (irq - GIC_PRIVATE_SIGNALS) & 0x1F;
45 reg_index = (irq - GIC_PRIVATE_SIGNALS) >> 5;
46 if (polarity == 0) {
47 value = readl(INT_POL_CTL0 + (reg_index * 4));
48 value |= (1 << offset); /* always invert the incoming IRQ's polarity */
49 writel_r((INT_POL_CTL0 + (reg_index * 4)), value);
50 } else {
51 value = readl(INT_POL_CTL0 + (reg_index * 4));
52 value &= ~(0x1 << offset);
53 writel_r(INT_POL_CTL0 + (reg_index * 4), value);
54 }
55}
56
57/* set for arm gic */
58void mt_irq_set_sens(unsigned int irq, unsigned int sens)
59{
60 unsigned int config;
61
62 if (sens == EDGE_SENSITIVE) {
63 config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
64 config |= (0x2 << (irq % 16) * 2);
65 writel_r(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
66 } else {
67 config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
68 config &= ~(0x2 << (irq % 16) * 2);
69 writel_r( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
70 }
71 DSB;
72}