blob: 265625e2cc94ee6174ba13619dffb1820751e00e [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2016 MediaTek Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22*/
23
24#include <arch.h>
25#include <arch/arm64/mmu.h>
26#include <arch/ops.h>
27#include <assert.h>
28#include <debug.h>
29#include <dev/interrupt/arm_gic.h>
30#include <dev/timer/arm_generic.h>
31#include <dev/uart.h>
32#include <err.h>
33#include <kernel/vm.h>
34#include <platform.h>
35#include <platform/emi.h>
36#include <platform/memory.h>
37#include <platform/mmc_core.h>
38#include <platform/mt2635.h>
39#include <platform/mtk_timer.h>
40#include <platform/mtk_wdt.h>
41#include <platform/pll.h>
42#include <platform/pmic.h>
43#include <lib/bio.h>
44#include <lib/mempool.h>
45
46#if WITH_KERNEL_VM
47#define L2C_MAPPING_IDX 0
48#define PERIPHERAL_MAPPING_IDX 1
49#define SRAM_MAPPING_IDX 2
50#define DRAM_MAPPING_IDX 3
51
52/* initial memory mappings. parsed by start.S */
53struct mmu_initial_mapping mmu_initial_mappings[] = {
54 {
55 .phys = MEMORY_BASE_PHYS,
56 .virt = MEMORY_BASE_VIRT,
57 .size = MEMORY_APERTURE_SIZE,
58 .flags = 0,
59 .name = "l2c"
60 },
61 {
62 .phys = PERIPHERAL_BASE_PHYS,
63 .virt = PERIPHERAL_BASE_VIRT,
64 .size = PERIPHERAL_BASE_SIZE,
65 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
66 .name = "peripherals"
67 },
68 /* reserved for internal sram */
69 { 0 },
70 /* reserved for dram */
71 { 0 },
72 /* null entry to terminate the list */
73 { 0 }
74};
75
76static pmm_arena_t arena = {
77 .name = "sdram",
78 .base = SRAM_BASE_PHYS,
79 .size = SRAM_BASE_SIZE,
80 .flags = PMM_ARENA_FLAG_KMAP,
81};
82
83/* only enable el1 dcache */
84static void dcache_enable(void)
85{
86 uint32_t sctlr;
87
88 asm volatile("mrs %0, sctlr_el1" : "=r" (sctlr) : : "cc");
89 asm volatile("msr sctlr_el1, %0" : : "r" (sctlr | (1 << 2)) : "cc");
90 asm volatile("isb");
91}
92
93#endif /* WITH_KERNEL_VM */
94
95void platform_early_init(void)
96{
97 uart_init_early();
98
99 /* initialize the interrupt controller */
100 arm_gic_init();
101
102 /* initialize the timer block */
103 mtk_timer_init();
104
105 mtk_wdt_init();
106 arm_generic_timer_init(ARM_GENERIC_TIMER_PHYSICAL_INT, 13000000);
107
108#if WITH_KERNEL_VM
109 arch_disable_cache(DCACHE);
110#endif
111 mt_pll_init();
112
113 mt_pmic_init();
114
115 /*
116 * mt_init_mempll() and mt_pll_post_init() should be invoked
117 * after pmic_ini
118 */
119 mt_init_mempll();
120 mt_pll_post_init();
121 /* dram calibration, mapping and test */
122 mt_mem_init();
123
124#if WITH_KERNEL_VM
125 dcache_enable();
126
127 /* add DRAM to mmu_initial_mappings for physical-to-virtual translation */
128 mmu_initial_mappings[DRAM_MAPPING_IDX].phys = DRAM_BASE_PHY;
129 mmu_initial_mappings[DRAM_MAPPING_IDX].virt = DRAM_BASE_VIRT;
130 mmu_initial_mappings[DRAM_MAPPING_IDX].size = get_dram_size();
131 mmu_initial_mappings[DRAM_MAPPING_IDX].flags = 0;
132 mmu_initial_mappings[DRAM_MAPPING_IDX].name = "dram";
133
134 /* mapping internel sram to cacheable memory */
135 arch_mmu_map(SRAM_BASE_VIRT, SRAM_BASE_PHYS, SRAM_BASE_SIZE >> PAGE_SIZE_SHIFT, 0);
136 /* add intrenal sram to mmu_initial_mappings for heap */
137 mmu_initial_mappings[SRAM_MAPPING_IDX].phys = SRAM_BASE_PHYS;
138 mmu_initial_mappings[SRAM_MAPPING_IDX].virt = SRAM_BASE_VIRT;
139 mmu_initial_mappings[SRAM_MAPPING_IDX].size = SRAM_BASE_SIZE;
140 mmu_initial_mappings[SRAM_MAPPING_IDX].flags = 0;
141 mmu_initial_mappings[SRAM_MAPPING_IDX].name = "sram";
142
143 pmm_add_arena(&arena);
144#endif
145}
146
147void platform_init(void)
148{
149 int ret;
150 bdev_t *rpdev;
151 unsigned int *rpmb_size;
152
153 ret = mempool_init((void *)CACHED_MEMPOOL_ADDR, CACHED_MEMPOOL_SIZE,
154 MEMPOOL_CACHE);
155 if (ret != NO_ERROR)
156 platform_halt(HALT_ACTION_REBOOT, HALT_REASON_SW_PANIC);
157
158 emmc_init();
159
160 rpdev = bio_open("mmc0rpmb");
161 if (rpdev != NULL) {
162 rpmb_size = (unsigned int *)(readl(SRAMROM_BASE + 0x3c) + 0x8fc + KERNEL_ASPACE_BASE);
163 *rpmb_size = rpdev->total_size;
164 bio_close(rpdev);
165 }
166}